Revision 180:96ed750bd169, committed 2018-01-17

Comitter:

Anna Bridge

Date:

Wed Jan 17 15:23:54 2018 +0000

Parent:

179:b0033dcd6934

Child:

181:57724642e740

Commit message:

mbed-dev libray. Release version 158

Changed in this revision

--- a/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,673 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_armcc.h
- * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.00
- * @date     22. Feb 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCC_H
-#define __CMSIS_ARMCC_H
-
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* CMSIS compiler control architecture macros */
-#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A  == 1))
-  #define __ARM_ARCH_7A__           1
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                  __inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE           static __inline
-#endif
-#ifndef   __STATIC_ASM
-  #define __STATIC_ASM              static __asm
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN               __declspec(noreturn)
-#endif
-#ifndef   __USED
-  #define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-  #define __UNALIGNED_UINT32(x)     (*((__packed uint32_t *)(x)))
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                  __attribute__((packed))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-
-/**
-  \brief   Get FPSCR
-  \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0U);
-#endif
-}
-
-/**
-  \brief   Set FPSCR
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#else
-  (void)fpscr;
-#endif
-}
-
-/* ##########################  Core Instruction Access  ######################### */
-/**
-  \brief   No Operation
- */
-#define __NOP                             __nop
-
-/**
-  \brief   Wait For Interrupt
- */
-#define __WFI                             __wfi
-
-/**
-  \brief   Wait For Event
- */
-#define __WFE                             __wfe
-
-/**
-  \brief   Send Event
- */
-#define __SEV                             __sev
-
-/**
-  \brief   Instruction Synchronization Barrier
- */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Data Synchronization Barrier
- */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Data Memory Barrier
- */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV                             __rev
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/**
-  \brief   Reverse byte order in signed short value
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-#define __ROR                             __ror
-
-/**
-  \brief   Breakpoint
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                     __breakpoint(value)
-
-/**
-  \brief   Reverse bit order of value
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-/**
-  \brief   Count leading zeros
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-/** \brief  Get CPSR Register
-    \return               CPSR Register value
- */
-__STATIC_INLINE uint32_t __get_CPSR(void)
-{
-  register uint32_t __regCPSR          __ASM("cpsr");
-  return(__regCPSR);
-}
-
-
-/** \brief  Set CPSR Register
-    \param [in]    cpsr  CPSR value to set
- */
-__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
-{
-  register uint32_t __regCPSR          __ASM("cpsr");
-  __regCPSR = cpsr;
-}
-
-/** \brief  Get Mode
-    \return                Processor Mode
- */
-__STATIC_INLINE uint32_t __get_mode(void) {
-  return (__get_CPSR() & 0x1FU);
-}
-
-/** \brief  Set Mode
-    \param [in]    mode  Mode value to set
- */
-__STATIC_INLINE __ASM void __set_mode(uint32_t mode) {
-  MOV  r1, lr
-  MSR  CPSR_C, r0
-  BX   r1
-}
-
-/** \brief  Set Stack Pointer
-    \param [in]    stack  Stack Pointer value to set
- */
-__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
-{
-  MOV  sp, r0
-  BX   lr
-}
-
-/** \brief  Set Process Stack Pointer
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-__STATIC_INLINE __ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  ARM
-  PRESERVE8
-
-  BIC     R0, R0, #7  ;ensure stack is 8-byte aligned
-  MRS     R1, CPSR
-  CPS     #0x1F       ;no effect in USR mode
-  MOV     SP, R0
-  MSR     CPSR_c, R1  ;no effect in USR mode
-  ISB
-  BX      LR
-}
-
-/** \brief  Set User Mode
- */
-__STATIC_INLINE __ASM void __set_CPS_USR(void)
-{
-  ARM
-
-  CPS  #0x10
-  BX   LR
-}
-
-/** \brief  Get FPEXC
-    \return               Floating Point Exception Control register value
- */
-__STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpexc         __ASM("fpexc");
-  return(__regfpexc);
-#else
-  return(0);
-#endif
-}
-
-/** \brief  Set FPEXC
-    \param [in]    fpexc  Floating Point Exception Control value to set
- */
-__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpexc         __ASM("fpexc");
-  __regfpexc = (fpexc);
-#endif
-}
-
-/** \brief  Get CPACR
-    \return               Coprocessor Access Control register value
- */
-__STATIC_INLINE uint32_t __get_CPACR(void)
-{
-  register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-  return __regCPACR;
-}
-
-/** \brief  Set CPACR
-    \param [in]    cpacr  Coprocessor Acccess Control value to set
- */
-__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
-  register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-  __regCPACR = cpacr;
-}
-
-/** \brief  Get CBAR
-    \return               Configuration Base Address register value
- */
-__STATIC_INLINE uint32_t __get_CBAR() {
-  register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
-  return(__regCBAR);
-}
-
-/** \brief  Get TTBR0
-
-    This function returns the value of the Translation Table Base Register 0.
-
-    \return               Translation Table Base Register 0 value
- */
-__STATIC_INLINE uint32_t __get_TTBR0() {
-  register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-  return(__regTTBR0);
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-  register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-  __regTTBR0 = ttbr0;
-}
-
-/** \brief  Get DACR
-
-    This function returns the value of the Domain Access Control Register.
-
-    \return               Domain Access Control Register value
- */
-__STATIC_INLINE uint32_t __get_DACR() {
-  register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-  return(__regDACR);
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
-  register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-  __regDACR = dacr;
-}
-
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
-  register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-  __regSCTLR = sctlr;
-}
-
-/** \brief  Get SCTLR
-    \return               System Control Register value
- */
-__STATIC_INLINE uint32_t __get_SCTLR() {
-  register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-  return(__regSCTLR);
-}
-
-/** \brief  Set ACTRL
-    \param [in]    actrl  Auxiliary Control Register value to set
- */
-__STATIC_INLINE void __set_ACTRL(uint32_t actrl)
-{
-  register uint32_t __regACTRL         __ASM("cp15:0:c1:c0:1");
-  __regACTRL = actrl;
-}
-
-/** \brief  Get ACTRL
-    \return               Auxiliary Control Register value
- */
-__STATIC_INLINE uint32_t __get_ACTRL(void)
-{
-  register uint32_t __regACTRL         __ASM("cp15:0:c1:c0:1");
-  return(__regACTRL);
-}
-
-/** \brief  Get MPIDR
-
-    This function returns the value of the Multiprocessor Affinity Register.
-
-    \return               Multiprocessor Affinity Register value
- */
-__STATIC_INLINE uint32_t __get_MPIDR(void)
-{
-  register uint32_t __regMPIDR         __ASM("cp15:0:c0:c0:5");
-  return(__regMPIDR);
-}
-
- /** \brief  Get VBAR
-
-    This function returns the value of the Vector Base Address Register.
-
-    \return               Vector Base Address Register
- */
-__STATIC_INLINE uint32_t __get_VBAR(void)
-{
-  register uint32_t __regVBAR         __ASM("cp15:0:c12:c0:0");
-  return(__regVBAR);
-}
-
-/** \brief  Set VBAR
-
-    This function assigns the given value to the Vector Base Address Register.
-
-    \param [in]    vbar  Vector Base Address Register value to set
- */
-__STATIC_INLINE void __set_VBAR(uint32_t vbar)
-{
-  register uint32_t __regVBAR          __ASM("cp15:0:c12:c0:0");
-  __regVBAR = vbar;
-}
-
-/** \brief  Set CNTP_TVAL
-
-  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
-
-  \param [in]    value  CNTP_TVAL Register value to set
-*/
-__STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
-  register uint32_t __regCNTP_TVAL         __ASM("cp15:0:c14:c2:0");
-  __regCNTP_TVAL = value;
-}
-
-/** \brief  Get CNTP_TVAL
-
-    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
-
-    \return               CNTP_TVAL Register value
- */
-__STATIC_INLINE uint32_t __get_CNTP_TVAL() {
-  register uint32_t __regCNTP_TVAL         __ASM("cp15:0:c14:c2:0");
-  return(__regCNTP_TVAL);
-}
-
-/** \brief  Set CNTP_CTL
-
-  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
-
-  \param [in]    value  CNTP_CTL Register value to set
-*/
-__STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
-  register uint32_t __regCNTP_CTL          __ASM("cp15:0:c14:c2:1");
-  __regCNTP_CTL = value;
-}
-
-/** \brief  Set TLBIALL
-
-  TLB Invalidate All
- */
-__STATIC_INLINE void __set_TLBIALL(uint32_t value) {
-  register uint32_t __TLBIALL              __ASM("cp15:0:c8:c7:0");
-  __TLBIALL = value;
-}
-
-/** \brief  Set BPIALL.
-
-  Branch Predictor Invalidate All
- */
-__STATIC_INLINE void __set_BPIALL(uint32_t value) {
-  register uint32_t __BPIALL            __ASM("cp15:0:c7:c5:6");
-  __BPIALL = value;
-}
-
-/** \brief  Set ICIALLU
-
-  Instruction Cache Invalidate All
- */
-__STATIC_INLINE void __set_ICIALLU(uint32_t value) {
-  register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
-  __ICIALLU = value;
-}
-
-/** \brief  Set DCCMVAC
-
-  Data cache clean
- */
-__STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
-  register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
-  __DCCMVAC = value;
-}
-
-/** \brief  Set DCIMVAC
-
-  Data cache invalidate
- */
-__STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
-  register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
-  __DCIMVAC = value;
-}
-
-/** \brief  Set DCCIMVAC
-
-  Data cache clean and invalidate
- */
-__STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
-  register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
-  __DCCIMVAC = value;
-}
-
-/** \brief  Clean and Invalidate the entire data or unified cache
-
-  Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
- */
-#pragma push
-#pragma arm
-__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) {
-        ARM
-
-        PUSH    {R4-R11}
-
-        MRC     p15, 1, R6, c0, c0, 1      // Read CLIDR
-        ANDS    R3, R6, #0x07000000        // Extract coherency level
-        MOV     R3, R3, LSR #23            // Total cache levels << 1
-        BEQ     Finished                   // If 0, no need to clean
-
-        MOV     R10, #0                    // R10 holds current cache level << 1
-Loop1   ADD     R2, R10, R10, LSR #1       // R2 holds cache "Set" position
-        MOV     R1, R6, LSR R2             // Bottom 3 bits are the Cache-type for this level
-        AND     R1, R1, #7                 // Isolate those lower 3 bits
-        CMP     R1, #2
-        BLT     Skip                       // No cache or only instruction cache at this level
-
-        MCR     p15, 2, R10, c0, c0, 0     // Write the Cache Size selection register
-        ISB                                // ISB to sync the change to the CacheSizeID reg
-        MRC     p15, 1, R1, c0, c0, 0      // Reads current Cache Size ID register
-        AND     R2, R1, #7                 // Extract the line length field
-        ADD     R2, R2, #4                 // Add 4 for the line length offset (log2 16 bytes)
-        LDR     R4, =0x3FF
-        ANDS    R4, R4, R1, LSR #3         // R4 is the max number on the way size (right aligned)
-        CLZ     R5, R4                     // R5 is the bit position of the way size increment
-        LDR     R7, =0x7FFF
-        ANDS    R7, R7, R1, LSR #13        // R7 is the max number of the index size (right aligned)
-
-Loop2   MOV     R9, R4                     // R9 working copy of the max way size (right aligned)
-
-Loop3   ORR     R11, R10, R9, LSL R5       // Factor in the Way number and cache number into R11
-        ORR     R11, R11, R7, LSL R2       // Factor in the Set number
-        CMP     R0, #0
-        BNE     Dccsw
-        MCR     p15, 0, R11, c7, c6, 2     // DCISW. Invalidate by Set/Way
-        B       cont
-Dccsw   CMP     R0, #1
-        BNE     Dccisw
-        MCR     p15, 0, R11, c7, c10, 2    // DCCSW. Clean by Set/Way
-        B       cont
-Dccisw  MCR     p15, 0, R11, c7, c14, 2    // DCCISW. Clean and Invalidate by Set/Way
-cont    SUBS    R9, R9, #1                 // Decrement the Way number
-        BGE     Loop3
-        SUBS    R7, R7, #1                 // Decrement the Set number
-        BGE     Loop2
-Skip    ADD     R10, R10, #2               // Increment the cache number
-        CMP     R3, R10
-        BGT     Loop1
-
-Finished
-        DSB
-        POP    {R4-R11}
-        BX     lr
-}
-#pragma pop
-
-/** \brief  Enable Floating Point Unit
-
-  Critical section, called from undef handler, so systick is disabled
- */
-#pragma push
-#pragma arm
-__STATIC_INLINE __ASM void __FPU_Enable(void) {
-        ARM
-
-        //Permit access to VFP/NEON, registers by modifying CPACR
-        MRC     p15,0,R1,c1,c0,2
-        ORR     R1,R1,#0x00F00000
-        MCR     p15,0,R1,c1,c0,2
-
-        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
-        ISB
-
-        //Enable VFP/NEON
-        VMRS    R1,FPEXC
-        ORR     R1,R1,#0x40000000
-        VMSR    FPEXC,R1
-
-        //Initialise VFP/NEON registers to 0
-        MOV     R2,#0
-  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16
-        //Initialise D16 registers to 0
-        VMOV    D0, R2,R2
-        VMOV    D1, R2,R2
-        VMOV    D2, R2,R2
-        VMOV    D3, R2,R2
-        VMOV    D4, R2,R2
-        VMOV    D5, R2,R2
-        VMOV    D6, R2,R2
-        VMOV    D7, R2,R2
-        VMOV    D8, R2,R2
-        VMOV    D9, R2,R2
-        VMOV    D10,R2,R2
-        VMOV    D11,R2,R2
-        VMOV    D12,R2,R2
-        VMOV    D13,R2,R2
-        VMOV    D14,R2,R2
-        VMOV    D15,R2,R2
-  ENDIF
-  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
-        //Initialise D32 registers to 0
-        VMOV    D16,R2,R2
-        VMOV    D17,R2,R2
-        VMOV    D18,R2,R2
-        VMOV    D19,R2,R2
-        VMOV    D20,R2,R2
-        VMOV    D21,R2,R2
-        VMOV    D22,R2,R2
-        VMOV    D23,R2,R2
-        VMOV    D24,R2,R2
-        VMOV    D25,R2,R2
-        VMOV    D26,R2,R2
-        VMOV    D27,R2,R2
-        VMOV    D28,R2,R2
-        VMOV    D29,R2,R2
-        VMOV    D30,R2,R2
-        VMOV    D31,R2,R2
-  ENDIF
-
-        //Initialise FPSCR to a known state
-        VMRS    R2,FPSCR
-        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-        AND     R2,R2,R3
-        VMSR    FPSCR,R2
-
-        BX      LR
-}
-#pragma pop
-
-#endif /* __CMSIS_ARMCC_H */

--- a/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armclang.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,646 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_armclang.h
- * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.00
- * @date     05. Apr 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCLANG_H
-#define __CMSIS_ARMCLANG_H
-
-#ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                  __inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE           static __inline
-#endif
-#ifndef   __STATIC_ASM
-  #define __STATIC_ASM              static __asm
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN               __declspec(noreturn)
-#endif
-#ifndef   __USED
-  #define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-  #define __UNALIGNED_UINT32(x)     (*((__packed uint32_t *)(x)))
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                  __attribute__((packed))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-
-/**
-  \brief   Get FPSCR
-  \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  uint32_t result;
-  __ASM volatile("MRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0U);
-#endif
-}
-
-/**
-  \brief   Set FPSCR
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) : "memory");
-#else
-  (void)fpscr;
-#endif
-}
-
-/* ##########################  Core Instruction Access  ######################### */
-/**
-  \brief   No Operation
- */
-#define __NOP                             __builtin_arm_nop
-
-/**
-  \brief   Wait For Interrupt
- */
-#define __WFI                             __builtin_arm_wfi
-
-/**
-  \brief   Wait For Event
- */
-#define __WFE                             __builtin_arm_wfe
-
-/**
-  \brief   Send Event
- */
-#define __SEV                             __builtin_arm_sev
-
-/**
-  \brief   Instruction Synchronization Barrier
- */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __builtin_arm_isb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Data Synchronization Barrier
- */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __builtin_arm_dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Data Memory Barrier
- */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __builtin_arm_dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV                             __builtin_bswap32
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-  __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
-  return result;
-}
-#endif
-
-/**
-  \brief   Reverse byte order in signed short value
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-  int32_t result;
-  __ASM volatile("revsh %0, %1" : "=r" (result) : "r" (value));
-  return result;
-}
-#endif
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-/**
-  \brief   Breakpoint
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-/**
-  \brief   Reverse bit order of value
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __RBIT                            __builtin_arm_rbit
-
-/**
-  \brief   Count leading zeros
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ                             __builtin_clz
-
-/** \brief  Get CPSR Register
-    \return               CPSR Register value
- */
-__STATIC_INLINE uint32_t __get_CPSR(void)
-{
-  uint32_t result;
-  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
-  return(result);
-}
-
-/** \brief  Get Mode
-    \return                Processor Mode
- */
-__STATIC_INLINE uint32_t __get_mode(void) {
-    return (__get_CPSR() & 0x1FU);
-}
-
-/** \brief  Set Mode
-    \param [in]    mode  Mode value to set
- */
-__STATIC_INLINE void __set_mode(uint32_t mode) {
-  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
-}
-
-/** \brief  Set Stack Pointer
-    \param [in]    stack  Stack Pointer value to set
- */
-__STATIC_INLINE void __set_SP(uint32_t stack)
-{
-  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
-}
-
-/** \brief  Set Process Stack Pointer
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile(
-    ".preserve8         \n"
-    "BIC     r0, r0, #7 \n" // ensure stack is 8-byte aligned
-    "MRS     r1, cpsr   \n"
-    "CPS     #0x1F      \n" // no effect in USR mode
-    "MOV     sp, r0     \n"
-    "MSR     cpsr_c, r1 \n" // no effect in USR mode
-    "ISB"
-   );
-}
-
-/** \brief  Set User Mode
- */
-__STATIC_INLINE void __set_CPS_USR(void)
-{
-  __ASM volatile("CPS  #0x10");
-}
-
-/** \brief  Get FPEXC
-    \return               Floating Point Exception Control register value
- */
-__STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
-  uint32_t result;
-  __ASM volatile("MRS %0, fpexc" : "=r" (result) );
-  return(result);
-#else
-  return(0);
-#endif
-}
-
-/** \brief  Set FPEXC
-    \param [in]    fpexc  Floating Point Exception Control value to set
- */
-__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpexc, %0" : : "r" (fpexc) : "memory");
-#endif
-}
-
-/** \brief  Get CPACR
-    \return               Coprocessor Access Control register value
- */
-__STATIC_INLINE uint32_t __get_CPACR(void)
-{
-  uint32_t result;
-  __ASM volatile("MRC p15, 0, %0, c1, c0, 2" : "=r"(result));
-  return result;
-}
-
-/** \brief  Set CPACR
-    \param [in]    cpacr  Coprocessor Acccess Control value to set
- */
-__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
-  __ASM volatile("MCR p15, 0, %0, c1, c0, 2" : : "r"(cpacr) : "memory");
-}
-
-/** \brief  Get CBAR
-    \return               Configuration Base Address register value
- */
-__STATIC_INLINE uint32_t __get_CBAR() {
-  uint32_t result;
-  __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result));
-  return result;
-}
-
-/** \brief  Get TTBR0
-
-    This function returns the value of the Translation Table Base Register 0.
-
-    \return               Translation Table Base Register 0 value
- */
-__STATIC_INLINE uint32_t __get_TTBR0() {
-  uint32_t result;
-  __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result));
-  return result;
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-  __ASM volatile("MCR p15, 0, %0, c2, c0, 0" : : "r"(ttbr0) : "memory");
-}
-
-/** \brief  Get DACR
-
-    This function returns the value of the Domain Access Control Register.
-
-    \return               Domain Access Control Register value
- */
-__STATIC_INLINE uint32_t __get_DACR() {
-  uint32_t result;
-  __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result));
-  return result;
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
-  __ASM volatile("MCR p15, 0, %0, c3, c0, 0" : : "r"(dacr) : "memory");
-}
-
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
-  __ASM volatile("MCR p15, 0, %0, c1, c0, 0" : : "r"(sctlr) : "memory");
-}
-
-/** \brief  Get SCTLR
-    \return               System Control Register value
- */
-__STATIC_INLINE uint32_t __get_SCTLR() {
-  uint32_t result;
-  __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result));
-  return result;
-}
-
-/** \brief  Set ACTRL
-    \param [in]    actrl  Auxiliary Control Register value to set
- */
-__STATIC_INLINE void __set_ACTRL(uint32_t actrl)
-{
-  __ASM volatile("MCR p15, 0, %0, c1, c0, 1" : : "r"(actrl) : "memory");
-}
-
-/** \brief  Get ACTRL
-    \return               Auxiliary Control Register value
- */
-__STATIC_INLINE uint32_t __get_ACTRL(void)
-{
-  uint32_t result;
-  __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r"(result));
-  return result;
-}
-
-/** \brief  Get MPIDR
-
-    This function returns the value of the Multiprocessor Affinity Register.
-
-    \return               Multiprocessor Affinity Register value
- */
-__STATIC_INLINE uint32_t __get_MPIDR(void)
-{
-  uint32_t result;
-  __ASM volatile("MRC p15, 0, %0, c0, c0, 5" : "=r"(result));
-  return result;
-}
-
- /** \brief  Get VBAR
-
-    This function returns the value of the Vector Base Address Register.
-
-    \return               Vector Base Address Register
- */
-__STATIC_INLINE uint32_t __get_VBAR(void)
-{
-  uint32_t result;
-  __ASM volatile("MRC p15, 0, %0, c12, c0, 0" : "=r"(result));
-  return result;
-}
-
-/** \brief  Set VBAR
-
-    This function assigns the given value to the Vector Base Address Register.
-
-    \param [in]    vbar  Vector Base Address Register value to set
- */
-__STATIC_INLINE void __set_VBAR(uint32_t vbar)
-{
-  __ASM volatile("MCR p15, 0, %0, c12, c0, 1" : : "r"(vbar) : "memory");
-}
-
-/** \brief  Set CNTP_TVAL
-
-  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
-
-  \param [in]    value  CNTP_TVAL Register value to set
-*/
-__STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
-  __ASM volatile("MCR p15, 0, %0, c14, c2, 0" : : "r"(value) : "memory");
-}
-
-/** \brief  Get CNTP_TVAL
-
-    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
-
-    \return               CNTP_TVAL Register value
- */
-__STATIC_INLINE uint32_t __get_CNTP_TVAL() {
-  uint32_t result;
-  __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result));
-  return result;
-}
-
-/** \brief  Set CNTP_CTL
-
-  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
-
-  \param [in]    value  CNTP_CTL Register value to set
-*/
-__STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
-  __ASM volatile("MCR p15, 0, %0, c14, c2, 1" : : "r"(value) : "memory");
-}
-
-/** \brief  Set TLBIALL
-
-  TLB Invalidate All
- */
-__STATIC_INLINE void __set_TLBIALL(uint32_t value) {
-  __ASM volatile("MCR p15, 0, %0, c8, c7, 0" : : "r"(value) : "memory");
-}
-
-/** \brief  Set BPIALL.
-
-  Branch Predictor Invalidate All
- */
-__STATIC_INLINE void __set_BPIALL(uint32_t value) {
-  __ASM volatile("MCR p15, 0, %0, c7, c5, 6" : : "r"(value) : "memory");
-}
-
-/** \brief  Set ICIALLU
-
-  Instruction Cache Invalidate All
- */
-__STATIC_INLINE void __set_ICIALLU(uint32_t value) {
-  __ASM volatile("MCR p15, 0, %0, c7, c5, 0" : : "r"(value) : "memory");
-}
-
-/** \brief  Set DCCMVAC
-
-  Data cache clean
- */
-__STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
-  __ASM volatile("MCR p15, 0, %0, c7, c10, 1" : : "r"(value) : "memory");
-}
-
-/** \brief  Set DCIMVAC
-
-  Data cache invalidate
- */
-__STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
-  __ASM volatile("MCR p15, 0, %0, c7, c6, 1" : : "r"(value) : "memory");
-}
-
-/** \brief  Set DCCIMVAC
-
-  Data cache clean and invalidate
- */
-__STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
-  __ASM volatile("MCR p15, 0, %0, c7, c14, 1" : : "r"(value) : "memory");
-}
-
-/** \brief  Clean and Invalidate the entire data or unified cache
-
-  Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
- */
-__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) {
-  __ASM volatile(
-    "        PUSH    {R4-R11}                   \n"
-
-    "        MRC     p15, 1, R6, c0, c0, 1      \n" // Read CLIDR
-    "        ANDS    R3, R6, #0x07000000        \n" // Extract coherency level
-    "        MOV     R3, R3, LSR #23            \n" // Total cache levels << 1
-    "        BEQ     Finished                   \n" // If 0, no need to clean
-
-    "        MOV     R10, #0                    \n" // R10 holds current cache level << 1
-    "Loop1:  ADD     R2, R10, R10, LSR #1       \n" // R2 holds cache "Set" position
-    "        MOV     R1, R6, LSR R2             \n" // Bottom 3 bits are the Cache-type for this level
-    "        AND     R1, R1, #7                 \n" // Isolate those lower 3 bits
-    "        CMP     R1, #2                     \n"
-    "        BLT     Skip                       \n" // No cache or only instruction cache at this level
-
-    "        MCR     p15, 2, R10, c0, c0, 0     \n" // Write the Cache Size selection register
-    "        ISB                                \n" // ISB to sync the change to the CacheSizeID reg
-    "        MRC     p15, 1, R1, c0, c0, 0      \n" // Reads current Cache Size ID register
-    "        AND     R2, R1, #7                 \n" // Extract the line length field
-    "        ADD     R2, R2, #4                 \n" // Add 4 for the line length offset (log2 16 bytes)
-    "        LDR     R4, =0x3FF                 \n"
-    "        ANDS    R4, R4, R1, LSR #3         \n" // R4 is the max number on the way size (right aligned)
-    "        CLZ     R5, R4                     \n" // R5 is the bit position of the way size increment
-    "        LDR     R7, =0x7FFF                \n"
-    "        ANDS    R7, R7, R1, LSR #13        \n" // R7 is the max number of the index size (right aligned)
-
-    "Loop2:  MOV     R9, R4                     \n" // R9 working copy of the max way size (right aligned)
-
-    "Loop3:  ORR     R11, R10, R9, LSL R5       \n" // Factor in the Way number and cache number into R11
-    "        ORR     R11, R11, R7, LSL R2       \n" // Factor in the Set number
-    "        CMP     R0, #0                     \n"
-    "        BNE     Dccsw                      \n"
-    "        MCR     p15, 0, R11, c7, c6, 2     \n" // DCISW. Invalidate by Set/Way
-    "        B       cont                       \n"
-    "Dccsw:  CMP     R0, #1                     \n"
-    "        BNE     Dccisw                     \n"
-    "        MCR     p15, 0, R11, c7, c10, 2    \n" // DCCSW. Clean by Set/Way
-    "        B       cont                       \n"
-    "Dccisw: MCR     p15, 0, R11, c7, c14, 2    \n" // DCCISW. Clean and Invalidate by Set/Way
-    "cont:   SUBS    R9, R9, #1                 \n" // Decrement the Way number
-    "        BGE     Loop3                      \n"
-    "        SUBS    R7, R7, #1                 \n" // Decrement the Set number
-    "        BGE     Loop2                      \n"
-    "Skip:   ADD     R10, R10, #2               \n" // Increment the cache number
-    "        CMP     R3, R10                    \n"
-    "        BGT     Loop1                      \n"
-
-    "Finished:                                  \n"
-    "        DSB                                \n"
-    "        POP    {R4-R11}                      "
-  );
-}
-
-/** \brief  Enable Floating Point Unit
-
-  Critical section, called from undef handler, so systick is disabled
- */
-__STATIC_INLINE void __FPU_Enable(void) {
-  __ASM volatile(
-        //Permit access to VFP/NEON, registers by modifying CPACR
-    "        MRC     p15,0,R1,c1,c0,2  \n"
-    "        ORR     R1,R1,#0x00F00000 \n"
-    "        MCR     p15,0,R1,c1,c0,2  \n"
-
-        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
-    "        ISB                       \n"
-
-        //Enable VFP/NEON
-    "        VMRS    R1,FPEXC          \n"
-    "        ORR     R1,R1,#0x40000000 \n"
-    "        VMSR    FPEXC,R1          \n"
-
-        //Initialise VFP/NEON registers to 0
-    "        MOV     R2,#0             \n"
-#if 0 // TODO: Initialize FPU registers according to available register count
-    ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16 \n"
-        //Initialise D16 registers to 0
-    "        VMOV    D0, R2,R2         \n"
-    "        VMOV    D1, R2,R2         \n"
-    "        VMOV    D2, R2,R2         \n"
-    "        VMOV    D3, R2,R2         \n"
-    "        VMOV    D4, R2,R2         \n"
-    "        VMOV    D5, R2,R2         \n"
-    "        VMOV    D6, R2,R2         \n"
-    "        VMOV    D7, R2,R2         \n"
-    "        VMOV    D8, R2,R2         \n"
-    "        VMOV    D9, R2,R2         \n"
-    "        VMOV    D10,R2,R2         \n"
-    "        VMOV    D11,R2,R2         \n"
-    "        VMOV    D12,R2,R2         \n"
-    "        VMOV    D13,R2,R2         \n"
-    "        VMOV    D14,R2,R2         \n"
-    "        VMOV    D15,R2,R2         \n"
-    ".endif                            \n"
-
-    ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 \n"
-        //Initialise D32 registers to 0
-    "        VMOV    D16,R2,R2         \n"
-    "        VMOV    D17,R2,R2         \n"
-    "        VMOV    D18,R2,R2         \n"
-    "        VMOV    D19,R2,R2         \n"
-    "        VMOV    D20,R2,R2         \n"
-    "        VMOV    D21,R2,R2         \n"
-    "        VMOV    D22,R2,R2         \n"
-    "        VMOV    D23,R2,R2         \n"
-    "        VMOV    D24,R2,R2         \n"
-    "        VMOV    D25,R2,R2         \n"
-    "        VMOV    D26,R2,R2         \n"
-    "        VMOV    D27,R2,R2         \n"
-    "        VMOV    D28,R2,R2         \n"
-    "        VMOV    D29,R2,R2         \n"
-    "        VMOV    D30,R2,R2         \n"
-    "        VMOV    D31,R2,R2         \n"
-    ".endif                            \n"
-#endif
-        //Initialise FPSCR to a known state
-    "        VMRS    R2,FPSCR          \n"
-    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-    "        AND     R2,R2,R3          \n"
-    "        VMSR    FPSCR,R2            "
-  );
-}
-
-#endif /* __CMSIS_ARMCC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_A/cmsis_armcc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,544 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.1
+ * @date     07. Sep 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A  == 1))
+  #define __ARM_ARCH_7A__           1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __forceinline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   CMSIS_DEPRECATED
+  #define CMSIS_DEPRECATED                       __attribute__((deprecated))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP                             __nop
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI                             __wfi
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE                             __wfe
+
+/**
+  \brief   Send Event
+ */
+#define __SEV                             __sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                     __breakpoint(value)
+
+/**
+  \brief   Reverse bit order of value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Get FPSCR (Floating Point Status/Control)
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+/**
+  \brief   Set FPSCR (Floating Point Status/Control)
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+/** \brief  Get CPSR (Current Program Status Register)
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  return(__regCPSR);
+}
+
+
+/** \brief  Set CPSR (Current Program Status Register)
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  __regCPSR = cpsr;
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_INLINE uint32_t __get_mode(void)
+{
+  return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_INLINE __ASM void __set_mode(uint32_t mode)
+{
+  MOV  r1, lr
+  MSR  CPSR_C, r0
+  BX   r1
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer
+ */
+__STATIC_INLINE __ASM uint32_t __get_SP(void)
+{
+  MOV  r0, sp
+  BX   lr
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
+{
+  MOV  sp, r0
+  BX   lr
+}
+
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYSStack Pointer
+ */
+__STATIC_INLINE __ASM uint32_t __get_SP_usr(void)
+{
+  ARM
+  PRESERVE8
+
+  MRS     R1, CPSR
+  CPS     #0x1F       ;no effect in USR mode
+  MOV     R0, SP
+  MSR     CPSR_c, R1  ;no effect in USR mode
+  ISB
+  BX      LR
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
+{
+  ARM
+  PRESERVE8
+
+  MRS     R1, CPSR
+  CPS     #0x1F       ;no effect in USR mode
+  MOV     SP, R0
+  MSR     CPSR_c, R1  ;no effect in USR mode
+  ISB
+  BX      LR
+}
+
+/** \brief  Get FPEXC (Floating Point Exception Control Register)
+    \return               Floating Point Exception Control Register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  return(__regfpexc);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC (Floating Point Exception Control Register)
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  __regfpexc = (fpexc);
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
+#define __get_CP64(cp, op1, Rt, CRm) \
+  do { \
+    uint32_t ltmp, htmp; \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+    (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
+  } while(0)
+
+#define __set_CP64(cp, op1, Rt, CRm) \
+  do { \
+    const uint64_t tmp = (Rt); \
+    const uint32_t ltmp = (uint32_t)(tmp); \
+    const uint32_t htmp = (uint32_t)(tmp >> 32U); \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+  } while(0)
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE __ASM void __FPU_Enable(void)
+{
+        ARM
+
+        //Permit access to VFP/NEON, registers by modifying CPACR
+        MRC     p15,0,R1,c1,c0,2
+        ORR     R1,R1,#0x00F00000
+        MCR     p15,0,R1,c1,c0,2
+
+        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+        ISB
+
+        //Enable VFP/NEON
+        VMRS    R1,FPEXC
+        ORR     R1,R1,#0x40000000
+        VMSR    FPEXC,R1
+
+        //Initialise VFP/NEON registers to 0
+        MOV     R2,#0
+
+        //Initialise D16 registers to 0
+        VMOV    D0, R2,R2
+        VMOV    D1, R2,R2
+        VMOV    D2, R2,R2
+        VMOV    D3, R2,R2
+        VMOV    D4, R2,R2
+        VMOV    D5, R2,R2
+        VMOV    D6, R2,R2
+        VMOV    D7, R2,R2
+        VMOV    D8, R2,R2
+        VMOV    D9, R2,R2
+        VMOV    D10,R2,R2
+        VMOV    D11,R2,R2
+        VMOV    D12,R2,R2
+        VMOV    D13,R2,R2
+        VMOV    D14,R2,R2
+        VMOV    D15,R2,R2
+
+  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+        //Initialise D32 registers to 0
+        VMOV    D16,R2,R2
+        VMOV    D17,R2,R2
+        VMOV    D18,R2,R2
+        VMOV    D19,R2,R2
+        VMOV    D20,R2,R2
+        VMOV    D21,R2,R2
+        VMOV    D22,R2,R2
+        VMOV    D23,R2,R2
+        VMOV    D24,R2,R2
+        VMOV    D25,R2,R2
+        VMOV    D26,R2,R2
+        VMOV    D27,R2,R2
+        VMOV    D28,R2,R2
+        VMOV    D29,R2,R2
+        VMOV    D30,R2,R2
+        VMOV    D31,R2,R2
+  ENDIF
+
+        //Initialise FPSCR to a known state
+        VMRS    R2,FPSCR
+        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+        AND     R2,R2,R3
+        VMSR    FPSCR,R2
+
+        BX      LR
+}
+
+#endif /* __CMSIS_ARMCC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_A/cmsis_armclang.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,503 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.1
+ * @date     07. Sep 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __attribute__((always_inline))
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   CMSIS_DEPRECATED
+  #define CMSIS_DEPRECATED                       __attribute__((deprecated))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP                             __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI                             __builtin_arm_wfi
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE                             __builtin_arm_wfe
+
+/**
+  \brief   Send Event
+ */
+#define __SEV                             __builtin_arm_sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)   __ASM volatile ("bkpt "#value)
+
+/**
+  \brief   Reverse bit order of value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT          __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ           (uint8_t)__builtin_clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#define __get_FPSCR      __builtin_arm_get_fpscr
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#define __set_FPSCR      __builtin_arm_set_fpscr
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+	return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP()
+{
+  uint32_t result;
+  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
+  return result;
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr()
+{
+  uint32_t cpsr;
+  uint32_t result;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     %1, sp     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" :  "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+   );
+  return result;
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, %1     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+   );
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm)         __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm)         __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+  __ASM volatile(
+    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#if __ARM_NEON == 1
+    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2            "
+  );
+}
+
+#endif /* __CMSIS_ARMCLANG_H */

--- a/cmsis/TARGET_CORTEX_A/cmsis_compiler.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/cmsis/TARGET_CORTEX_A/cmsis_compiler.h	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_compiler.h
  * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.00
- * @date     22. Feb 2017
+ * @version  V1.0.1
+ * @date     01. December 2017
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
@@ -52,39 +52,7 @@
  * IAR Compiler
  */
 #elif defined ( __ICCARM__ )
-
-  #ifndef   __ASM
-    #define __ASM                     __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                  inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE           static inline
-  #endif
-
-  #include <cmsis_iar.h>
-
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN               __noreturn
-  #endif
-  #ifndef   __USED
-    #define __USED                    __root
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                    __weak
-  #endif
-  #ifndef   __UNALIGNED_UINT32
-    __packed struct T_UINT32 { uint32_t v; };
-      #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-    #define __ALIGNED(x)
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                  __packed
-  #endif
+  #include "cmsis_iccarm.h"
 
 
 /*
@@ -102,9 +70,18 @@
   #ifndef   __STATIC_INLINE
     #define __STATIC_INLINE           static inline
   #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
   #ifndef   __NO_RETURN
     #define __NO_RETURN               __attribute__((noreturn))
   #endif
+  #ifndef   CMSIS_DEPRECATED
+    #define CMSIS_DEPRECATED          __attribute__((deprecated))
+  #endif
   #ifndef   __USED
     #define __USED                    __attribute__((used))
   #endif
@@ -142,9 +119,15 @@
   #ifndef   __STATIC_INLINE
     #define __STATIC_INLINE           static inline
   #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
   #ifndef   __NO_RETURN
     #define __NO_RETURN               __attribute__((noreturn))
   #endif
+  #ifndef   CMSIS_DEPRECATED
+    #define CMSIS_DEPRECATED          __attribute__((deprecated))
+  #endif
   #ifndef   __USED
     #define __USED                    __attribute__((used))
   #endif
@@ -178,6 +161,9 @@
   #ifndef   __STATIC_INLINE
     #define __STATIC_INLINE           static inline
   #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
   #ifndef   __NO_RETURN
     // NO RETURN is automatically detected hence no warning here
     #define __NO_RETURN
@@ -186,6 +172,10 @@
     #warning No compiler specific solution for __USED. __USED is ignored.
     #define __USED
   #endif
+  #ifndef   CMSIS_DEPRECATED
+    #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.
+    #define CMSIS_DEPRECATED
+  #endif
   #ifndef   __WEAK
     #define __WEAK                    __weak
   #endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_A/cmsis_cp15.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,471 @@
+/**************************************************************************//**
+ * @file     cmsis_cp15.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.1
+ * @date     07. Sep 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_CP15_H
+#define __CMSIS_CP15_H
+
+/** \brief  Get ACTLR
+    \return               Auxiliary Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 1);
+  return(result);
+}
+
+/** \brief  Set ACTLR
+    \param [in]    actlr  Auxiliary Control value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
+{
+  __set_CP(15, 0, actlr, 1, 0, 1);
+}
+
+/** \brief  Get CPACR
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 2);
+  return result;
+}
+
+/** \brief  Set CPACR
+    \param [in]    cpacr  Coprocessor Access Control value to set
+ */
+__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
+{
+  __set_CP(15, 0, cpacr, 1, 0, 2);
+}
+
+/** \brief  Get DFSR
+    \return               Data Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 5, 0, 0);
+  return result;
+}
+
+/** \brief  Set DFSR
+    \param [in]    dfsr  Data Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
+{
+  __set_CP(15, 0, dfsr, 5, 0, 0);
+}
+
+/** \brief  Get IFSR
+    \return               Instruction Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 5, 0, 1);
+  return result;
+}
+
+/** \brief  Set IFSR
+    \param [in]    ifsr  Instruction Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
+{
+  __set_CP(15, 0, ifsr, 5, 0, 1);
+}
+
+/** \brief  Get ISR
+    \return               Interrupt Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ISR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 1, 0);
+  return result;
+}
+
+/** \brief  Get CBAR
+    \return               Configuration Base Address register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 4, result, 15, 0, 0);
+  return result;
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 2, 0, 0);
+  return result;
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
+{
+  __set_CP(15, 0, ttbr0, 2, 0, 0);
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DACR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 3, 0, 0);
+  return result;
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
+{
+  __set_CP(15, 0, dacr, 3, 0, 0);
+}
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
+{
+  __set_CP(15, 0, sctlr, 1, 0, 0);
+}
+
+/** \brief  Get SCTLR
+    \return               System Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 0);
+  return result;
+}
+
+/** \brief  Set ACTRL
+    \param [in]    actrl  Auxiliary Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
+{
+  __set_CP(15, 0, actrl, 1, 0, 1);
+}
+
+/** \brief  Get ACTRL
+    \return               Auxiliary Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 1);
+  return result;
+}
+
+/** \brief  Get MPIDR
+
+    This function returns the value of the Multiprocessor Affinity Register.
+
+    \return               Multiprocessor Affinity Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 0, 0, 5);
+  return result;
+}
+
+ /** \brief  Get VBAR
+
+    This function returns the value of the Vector Base Address Register.
+
+    \return               Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 0, 0);
+  return result;
+}
+
+/** \brief  Set VBAR
+
+    This function assigns the given value to the Vector Base Address Register.
+
+    \param [in]    vbar  Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
+{
+  __set_CP(15, 0, vbar, 12, 0, 1);
+}
+
+#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
+    defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
+    defined(DOXYGEN)
+
+/** \brief  Set CNTFRQ
+
+  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+  \param [in]    value  CNTFRQ Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 0, 0);
+}
+
+/** \brief  Get CNTFRQ
+
+    This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+    \return               CNTFRQ Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 0 , 0);
+  return result;
+}
+
+/** \brief  Set CNTP_TVAL
+
+  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+  \param [in]    value  CNTP_TVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 2, 0);
+}
+
+/** \brief  Get CNTP_TVAL
+
+    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+    \return               CNTP_TVAL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 2, 0);
+  return result;
+}
+
+/** \brief  Get CNTPCT
+
+    This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
+
+    \return               CNTPCT Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
+{
+  uint64_t result;
+  __get_CP64(15, 0, result, 14);
+  return result;
+}
+
+/** \brief  Set CNTP_CVAL
+
+  This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+  \param [in]    value  CNTP_CVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
+{
+  __set_CP64(15, 2, value, 14);
+}
+
+/** \brief  Get CNTP_CVAL
+
+    This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+    \return               CNTP_CVAL Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
+{
+  uint64_t result;
+  __get_CP64(15, 2, result, 14);
+  return result;
+}
+
+/** \brief  Set CNTP_CTL
+
+  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+  \param [in]    value  CNTP_CTL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 2, 1);
+}
+
+/** \brief  Get CNTP_CTL register
+    \return               CNTP_CTL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 2, 1);
+  return result;
+}
+
+#endif
+
+/** \brief  Set TLBIALL
+
+  TLB Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
+{
+  __set_CP(15, 0, value, 8, 7, 0);
+}
+
+/** \brief  Set BPIALL.
+
+  Branch Predictor Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 6);
+}
+
+/** \brief  Set ICIALLU
+
+  Instruction Cache Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 0);
+}
+
+/** \brief  Set DCCMVAC
+
+  Data cache clean
+ */
+__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 10, 1);
+}
+
+/** \brief  Set DCIMVAC
+
+  Data cache invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 6, 1);
+}
+
+/** \brief  Set DCCIMVAC
+
+  Data cache clean and invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 14, 1);
+}
+
+
+/** \brief  Set CCSIDR
+ */
+__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
+  __set_CP(15, 2, value, 0, 0, 0);
+}
+
+/** \brief  Get CCSIDR
+    \return CCSIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
+  __get_CP(15, 1, result, 0, 0, 0);
+  return result;
+}
+
+/** \brief  Get CLIDR
+    \return CLIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
+  __get_CP(15, 1, result, 0, 0, 1);
+  return result;
+}
+
+/** \brief  Set DCISW
+ */
+__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 6, 2);
+}
+
+/** \brief  Set DCCSW
+ */
+__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 10, 2);
+}
+
+/** \brief  Set DCCISW
+ */
+__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 14, 2);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,675 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.1
+ * @date     07. Sep 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __attribute__((always_inline))
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   CMSIS_DEPRECATED
+ #define  CMSIS_DEPRECATED                       __attribute__((deprecated))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+/**
+  \brief   Send Event
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE  void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE  void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE  void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
+  return result;
+}
+#endif
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE  uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U) {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             (uint8_t)__builtin_clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE  void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE  void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return Floating Point Status/Control register value
+*/
+__STATIC_FORCEINLINE  uint32_t __get_FPSCR(void)
+{
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    return __builtin_arm_get_fpscr();
+  #else
+    uint32_t result;
+
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    return(result);
+  #endif
+  #else
+    return(0U);
+  #endif
+}
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in] fpscr  Floating Point Status/Control value to set
+*/
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    __builtin_arm_set_fpscr(fpscr);
+  #else
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+  #endif
+  #else
+    (void)fpscr;
+  #endif
+}
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+    return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP(void)
+{
+  uint32_t result;
+  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
+  return result;
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
+{
+  uint32_t cpsr = __get_CPSR();
+  uint32_t result;
+  __ASM volatile(
+    "CPS     #0x1F  \n"
+    "MOV     %0, sp   " : "=r"(result) : : "memory"
+   );
+  __set_CPSR(cpsr);
+  __ISB();
+  return result;
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr = __get_CPSR();
+  __ASM volatile(
+    "CPS     #0x1F  \n"
+    "MOV     sp, %0   " : : "r" (topOfProcStack) : "memory"
+   );
+  __set_CPSR(cpsr);
+  __ISB();
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+  __ASM volatile(
+    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#if __ARM_NEON == 1
+    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2            "
+  );
+}
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,559 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR compiler) header file
+ * @version  V5.0.4
+ * @date     01. December 2017
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#pragma language=extended
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_7A__
+/* Macro already defined */
+#else
+  #if defined(__ARM7A__)
+    #define __ARM_ARCH_7A__ 1
+  #endif
+#endif
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  /* Needs IAR language extensions */
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  /* Needs IAR language extensions */
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  /* Needs IAR language extensions */
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef   CMSIS_DEPRECATED
+  #define CMSIS_DEPRECATED      __attribute__((deprecated))
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+  {
+    return *(__packed uint16_t*)(ptr);
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+  {
+    *(__packed uint16_t*)(ptr) = val;;
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+  {
+    return *(__packed uint32_t*)(ptr);
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+  {
+    *(__packed uint32_t*)(ptr) = val;;
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#if 0
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+  #pragma language=save
+  #pragma language=extended
+  __packed struct  __iar_u32 { uint32_t v; };
+  #pragma language=restore
+  #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq    __iar_builtin_enable_fiq
+  #define __disable_fault_irq   __iar_builtin_disable_fiq
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+  #if __FPU_PRESENT
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+  #else
+    #define __get_FPSCR()             ( 0 )
+  #endif
+
+  #define __set_FPSCR(VALUE)          (__arm_wsr("FPSCR", VALUE))
+
+  #define __get_CPSR()                (__arm_rsr("CPSR"))
+  #define __get_mode()                (__get_CPSR() & 0x1FU)
+
+  #define __set_CPSR(VALUE)           (__arm_wsr("CPSR", (VALUE)))
+  #define __set_mode(VALUE)           (__arm_wsr("CPSR_c", (VALUE)))
+
+
+  #define __get_FPEXC()       (__arm_rsr("FPEXC"))
+  #define __set_FPEXC(VALUE)    (__arm_wsr("FPEXC", VALUE))
+
+  #define __get_CP(cp, op1, RT, CRn, CRm, op2) \
+    ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
+
+  #define __set_CP(cp, op1, RT, CRn, CRm, op2) \
+    (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
+
+  #define __get_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+
+  #define __set_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+  #include "cmsis_cp15.h"
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #define __SSAT    __iar_builtin_SSAT
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #define __USAT    __iar_builtin_USAT
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #define __SADD8   __iar_builtin_SADD8
+  #define __QADD8   __iar_builtin_QADD8
+  #define __SHADD8  __iar_builtin_SHADD8
+  #define __UADD8   __iar_builtin_UADD8
+  #define __UQADD8  __iar_builtin_UQADD8
+  #define __UHADD8  __iar_builtin_UHADD8
+  #define __SSUB8   __iar_builtin_SSUB8
+  #define __QSUB8   __iar_builtin_QSUB8
+  #define __SHSUB8  __iar_builtin_SHSUB8
+  #define __USUB8   __iar_builtin_USUB8
+  #define __UQSUB8  __iar_builtin_UQSUB8
+  #define __UHSUB8  __iar_builtin_UHSUB8
+  #define __SADD16  __iar_builtin_SADD16
+  #define __QADD16  __iar_builtin_QADD16
+  #define __SHADD16 __iar_builtin_SHADD16
+  #define __UADD16  __iar_builtin_UADD16
+  #define __UQADD16 __iar_builtin_UQADD16
+  #define __UHADD16 __iar_builtin_UHADD16
+  #define __SSUB16  __iar_builtin_SSUB16
+  #define __QSUB16  __iar_builtin_QSUB16
+  #define __SHSUB16 __iar_builtin_SHSUB16
+  #define __USUB16  __iar_builtin_USUB16
+  #define __UQSUB16 __iar_builtin_UQSUB16
+  #define __UHSUB16 __iar_builtin_UHSUB16
+  #define __SASX    __iar_builtin_SASX
+  #define __QASX    __iar_builtin_QASX
+  #define __SHASX   __iar_builtin_SHASX
+  #define __UASX    __iar_builtin_UASX
+  #define __UQASX   __iar_builtin_UQASX
+  #define __UHASX   __iar_builtin_UHASX
+  #define __SSAX    __iar_builtin_SSAX
+  #define __QSAX    __iar_builtin_QSAX
+  #define __SHSAX   __iar_builtin_SHSAX
+  #define __USAX    __iar_builtin_USAX
+  #define __UQSAX   __iar_builtin_UQSAX
+  #define __UHSAX   __iar_builtin_UHSAX
+  #define __USAD8   __iar_builtin_USAD8
+  #define __USADA8  __iar_builtin_USADA8
+  #define __SSAT16  __iar_builtin_SSAT16
+  #define __USAT16  __iar_builtin_USAT16
+  #define __UXTB16  __iar_builtin_UXTB16
+  #define __UXTAB16 __iar_builtin_UXTAB16
+  #define __SXTB16  __iar_builtin_SXTB16
+  #define __SXTAB16 __iar_builtin_SXTAB16
+  #define __SMUAD   __iar_builtin_SMUAD
+  #define __SMUADX  __iar_builtin_SMUADX
+  #define __SMMLA   __iar_builtin_SMMLA
+  #define __SMLAD   __iar_builtin_SMLAD
+  #define __SMLADX  __iar_builtin_SMLADX
+  #define __SMLALD  __iar_builtin_SMLALD
+  #define __SMLALDX __iar_builtin_SMLALDX
+  #define __SMUSD   __iar_builtin_SMUSD
+  #define __SMUSDX  __iar_builtin_SMUSDX
+  #define __SMLSD   __iar_builtin_SMLSD
+  #define __SMLSDX  __iar_builtin_SMLSDX
+  #define __SMLSLD  __iar_builtin_SMLSLD
+  #define __SMLSLDX __iar_builtin_SMLSLDX
+  #define __SEL     __iar_builtin_SEL
+  #define __QADD    __iar_builtin_QADD
+  #define __QSUB    __iar_builtin_QSUB
+  #define __PKHBT   __iar_builtin_PKHBT
+  #define __PKHTB   __iar_builtin_PKHTB
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if !__FPU_PRESENT
+  #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if !__FPU_PRESENT
+  #define __get_FPSCR() (0)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq        __enable_interrupt
+  #define __disable_irq       __disable_interrupt
+  #define __enable_fault_irq    __enable_fiq
+  #define __disable_fault_irq   __disable_fiq
+  #define __NOP               __no_operation
+
+  #define __get_xPSR          __get_PSR
+
+  __IAR_FT void __set_mode(uint32_t mode)
+  {
+    __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+  }
+
+  __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+  {
+    return __LDREX((unsigned long *)ptr);
+  }
+
+  __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+  {
+    return __STREX(value, (unsigned long *)ptr);
+  }
+
+
+  __IAR_FT uint32_t __RRX(uint32_t value)
+  {
+    uint32_t result;
+    __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+    return(result);
+  }
+
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  __IAR_FT uint32_t __get_FPEXC(void)
+  {
+  #if (__FPU_PRESENT == 1)
+    uint32_t result;
+    __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+    return(result);
+  #else
+    return(0);
+  #endif
+  }
+
+  __IAR_FT void __set_FPEXC(uint32_t fpexc)
+  {
+  #if (__FPU_PRESENT == 1)
+    __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+  #endif
+  }
+
+
+  #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
+    __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+  #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
+    __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+  #define __get_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+  #define __set_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+  #include "cmsis_cp15.h"
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+
+__IAR_FT uint32_t __get_SP_usr(void)
+{
+  uint32_t cpsr;
+  uint32_t result;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     %1, sp     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" :  "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+   );
+  return result;
+}
+
+__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, %1     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+   );
+}
+
+#define __get_mode()                (__get_CPSR() & 0x1FU)
+
+__STATIC_INLINE
+void __FPU_Enable(void)
+{
+  __ASM volatile(
+    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#ifdef __ARM_ADVANCED_SIMD__
+    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        MOV32   R3,#0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2          \n");
+}
+
+
+
+#undef __IAR_FT
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_A/core_ca.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,2616 @@
+/**************************************************************************//**
+ * @file     core_ca.h
+ * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File
+ * @version  V1.00
+ * @date     22. Feb 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CA_H_GENERIC
+#define __CORE_CA_H_GENERIC
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+
+/*  CMSIS CA definitions */
+#define __CA_CMSIS_VERSION_MAIN  (1U)                                      /*!< \brief [31:16] CMSIS-Core(A) main version   */
+#define __CA_CMSIS_VERSION_SUB   (1U)                                      /*!< \brief [15:0]  CMSIS-Core(A) sub version    */
+#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CA_CMSIS_VERSION_SUB          )       /*!< \brief CMSIS-Core(A) version number         */
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CA_H_DEPENDANT
+#define __CORE_CA_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+ /* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CA_REV
+    #define __CA_REV              0x0000U
+    #warning "__CA_REV not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+    
+  #ifndef __GIC_PRESENT
+    #define __GIC_PRESENT             1U
+    #warning "__GIC_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __TIM_PRESENT
+    #define __TIM_PRESENT             1U
+    #warning "__TIM_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __L2C_PRESENT
+    #define __L2C_PRESENT             0U
+    #warning "__L2C_PRESENT not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< \brief Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< \brief Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< \brief Defines 'write only' permissions */
+#define     __IO    volatile             /*!< \brief Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*!< \brief Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*!< \brief Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*!< \brief Defines 'read / write' structure member permissions */
+#define RESERVED(N, T) T RESERVED##N;    // placeholder struct members used for "reserved" areas
+
+ /*******************************************************************************
+  *                 Register Abstraction
+   Core Register contain:
+   - CPSR
+   - CP15 Registers
+   - L2C-310 Cache Controller
+   - Generic Interrupt Controller Distributor
+   - Generic Interrupt Controller Interface
+  ******************************************************************************/
+
+/* Core Register CPSR */
+typedef union
+{
+  struct
+  {
+    uint32_t M:5;                        /*!< \brief bit:  0.. 4  Mode field */
+    uint32_t T:1;                        /*!< \brief bit:      5  Thumb execution state bit */
+    uint32_t F:1;                        /*!< \brief bit:      6  FIQ mask bit */
+    uint32_t I:1;                        /*!< \brief bit:      7  IRQ mask bit */
+    uint32_t A:1;                        /*!< \brief bit:      8  Asynchronous abort mask bit */
+    uint32_t E:1;                        /*!< \brief bit:      9  Endianness execution state bit */
+    uint32_t IT1:6;                      /*!< \brief bit: 10..15  If-Then execution state bits 2-7 */
+    uint32_t GE:4;                       /*!< \brief bit: 16..19  Greater than or Equal flags */
+    RESERVED(0:4, uint32_t)              
+    uint32_t J:1;                        /*!< \brief bit:     24  Jazelle bit */
+    uint32_t IT0:2;                      /*!< \brief bit: 25..26  If-Then execution state bits 0-1 */
+    uint32_t Q:1;                        /*!< \brief bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< \brief bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< \brief bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< \brief bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< \brief bit:     31  Negative condition code flag */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} CPSR_Type;
+
+
+
+/* CPSR Register Definitions */
+#define CPSR_N_Pos                       31U                                    /*!< \brief CPSR: N Position */
+#define CPSR_N_Msk                       (1UL << CPSR_N_Pos)                    /*!< \brief CPSR: N Mask */
+
+#define CPSR_Z_Pos                       30U                                    /*!< \brief CPSR: Z Position */
+#define CPSR_Z_Msk                       (1UL << CPSR_Z_Pos)                    /*!< \brief CPSR: Z Mask */
+
+#define CPSR_C_Pos                       29U                                    /*!< \brief CPSR: C Position */
+#define CPSR_C_Msk                       (1UL << CPSR_C_Pos)                    /*!< \brief CPSR: C Mask */
+
+#define CPSR_V_Pos                       28U                                    /*!< \brief CPSR: V Position */
+#define CPSR_V_Msk                       (1UL << CPSR_V_Pos)                    /*!< \brief CPSR: V Mask */
+
+#define CPSR_Q_Pos                       27U                                    /*!< \brief CPSR: Q Position */
+#define CPSR_Q_Msk                       (1UL << CPSR_Q_Pos)                    /*!< \brief CPSR: Q Mask */
+
+#define CPSR_IT0_Pos                     25U                                    /*!< \brief CPSR: IT0 Position */
+#define CPSR_IT0_Msk                     (3UL << CPSR_IT0_Pos)                  /*!< \brief CPSR: IT0 Mask */
+
+#define CPSR_J_Pos                       24U                                    /*!< \brief CPSR: J Position */
+#define CPSR_J_Msk                       (1UL << CPSR_J_Pos)                    /*!< \brief CPSR: J Mask */
+
+#define CPSR_GE_Pos                      16U                                    /*!< \brief CPSR: GE Position */
+#define CPSR_GE_Msk                      (0xFUL << CPSR_GE_Pos)                 /*!< \brief CPSR: GE Mask */
+
+#define CPSR_IT1_Pos                     10U                                    /*!< \brief CPSR: IT1 Position */
+#define CPSR_IT1_Msk                     (0x3FUL << CPSR_IT1_Pos)               /*!< \brief CPSR: IT1 Mask */
+
+#define CPSR_E_Pos                       9U                                     /*!< \brief CPSR: E Position */
+#define CPSR_E_Msk                       (1UL << CPSR_E_Pos)                    /*!< \brief CPSR: E Mask */
+
+#define CPSR_A_Pos                       8U                                     /*!< \brief CPSR: A Position */
+#define CPSR_A_Msk                       (1UL << CPSR_A_Pos)                    /*!< \brief CPSR: A Mask */
+
+#define CPSR_I_Pos                       7U                                     /*!< \brief CPSR: I Position */
+#define CPSR_I_Msk                       (1UL << CPSR_I_Pos)                    /*!< \brief CPSR: I Mask */
+
+#define CPSR_F_Pos                       6U                                     /*!< \brief CPSR: F Position */
+#define CPSR_F_Msk                       (1UL << CPSR_F_Pos)                    /*!< \brief CPSR: F Mask */
+
+#define CPSR_T_Pos                       5U                                     /*!< \brief CPSR: T Position */
+#define CPSR_T_Msk                       (1UL << CPSR_T_Pos)                    /*!< \brief CPSR: T Mask */
+
+#define CPSR_M_Pos                       0U                                     /*!< \brief CPSR: M Position */
+#define CPSR_M_Msk                       (0x1FUL << CPSR_M_Pos)                 /*!< \brief CPSR: M Mask */
+
+#define CPSR_M_USR                       0x10U                                  /*!< \brief CPSR: M User mode (PL0) */
+#define CPSR_M_FIQ                       0x11U                                  /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
+#define CPSR_M_IRQ                       0x12U                                  /*!< \brief CPSR: M Interrupt mode (PL1) */
+#define CPSR_M_SVC                       0x13U                                  /*!< \brief CPSR: M Supervisor mode (PL1) */
+#define CPSR_M_MON                       0x16U                                  /*!< \brief CPSR: M Monitor mode (PL1) */
+#define CPSR_M_ABT                       0x17U                                  /*!< \brief CPSR: M Abort mode (PL1) */
+#define CPSR_M_HYP                       0x1AU                                  /*!< \brief CPSR: M Hypervisor mode (PL2) */
+#define CPSR_M_UND                       0x1BU                                  /*!< \brief CPSR: M Undefined mode (PL1) */
+#define CPSR_M_SYS                       0x1FU                                  /*!< \brief CPSR: M System mode (PL1) */
+
+/* CP15 Register SCTLR */
+typedef union
+{
+  struct
+  {
+    uint32_t M:1;                        /*!< \brief bit:     0  MMU enable */
+    uint32_t A:1;                        /*!< \brief bit:     1  Alignment check enable */
+    uint32_t C:1;                        /*!< \brief bit:     2  Cache enable */
+    RESERVED(0:2, uint32_t)              
+    uint32_t CP15BEN:1;                  /*!< \brief bit:     5  CP15 barrier enable */
+    RESERVED(1:1, uint32_t)              
+    uint32_t B:1;                        /*!< \brief bit:     7  Endianness model */
+    RESERVED(2:2, uint32_t)              
+    uint32_t SW:1;                       /*!< \brief bit:    10  SWP and SWPB enable */
+    uint32_t Z:1;                        /*!< \brief bit:    11  Branch prediction enable */
+    uint32_t I:1;                        /*!< \brief bit:    12  Instruction cache enable */
+    uint32_t V:1;                        /*!< \brief bit:    13  Vectors bit */
+    uint32_t RR:1;                       /*!< \brief bit:    14  Round Robin select */
+    RESERVED(3:2, uint32_t)              
+    uint32_t HA:1;                       /*!< \brief bit:    17  Hardware Access flag enable */
+    RESERVED(4:1, uint32_t)              
+    uint32_t WXN:1;                      /*!< \brief bit:    19  Write permission implies XN */
+    uint32_t UWXN:1;                     /*!< \brief bit:    20  Unprivileged write permission implies PL1 XN */
+    uint32_t FI:1;                       /*!< \brief bit:    21  Fast interrupts configuration enable */
+    uint32_t U:1;                        /*!< \brief bit:    22  Alignment model */
+    RESERVED(5:1, uint32_t)              
+    uint32_t VE:1;                       /*!< \brief bit:    24  Interrupt Vectors Enable */
+    uint32_t EE:1;                       /*!< \brief bit:    25  Exception Endianness */
+    RESERVED(6:1, uint32_t)              
+    uint32_t NMFI:1;                     /*!< \brief bit:    27  Non-maskable FIQ (NMFI) support */
+    uint32_t TRE:1;                      /*!< \brief bit:    28  TEX remap enable. */
+    uint32_t AFE:1;                      /*!< \brief bit:    29  Access flag enable */
+    uint32_t TE:1;                       /*!< \brief bit:    30  Thumb Exception enable */
+    RESERVED(7:1, uint32_t)              
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} SCTLR_Type;
+
+#define SCTLR_TE_Pos                     30U                                    /*!< \brief SCTLR: TE Position */
+#define SCTLR_TE_Msk                     (1UL << SCTLR_TE_Pos)                  /*!< \brief SCTLR: TE Mask */
+
+#define SCTLR_AFE_Pos                    29U                                    /*!< \brief SCTLR: AFE Position */
+#define SCTLR_AFE_Msk                    (1UL << SCTLR_AFE_Pos)                 /*!< \brief SCTLR: AFE Mask */
+
+#define SCTLR_TRE_Pos                    28U                                    /*!< \brief SCTLR: TRE Position */
+#define SCTLR_TRE_Msk                    (1UL << SCTLR_TRE_Pos)                 /*!< \brief SCTLR: TRE Mask */
+
+#define SCTLR_NMFI_Pos                   27U                                    /*!< \brief SCTLR: NMFI Position */
+#define SCTLR_NMFI_Msk                   (1UL << SCTLR_NMFI_Pos)                /*!< \brief SCTLR: NMFI Mask */
+
+#define SCTLR_EE_Pos                     25U                                    /*!< \brief SCTLR: EE Position */
+#define SCTLR_EE_Msk                     (1UL << SCTLR_EE_Pos)                  /*!< \brief SCTLR: EE Mask */
+
+#define SCTLR_VE_Pos                     24U                                    /*!< \brief SCTLR: VE Position */
+#define SCTLR_VE_Msk                     (1UL << SCTLR_VE_Pos)                  /*!< \brief SCTLR: VE Mask */
+
+#define SCTLR_U_Pos                      22U                                    /*!< \brief SCTLR: U Position */
+#define SCTLR_U_Msk                      (1UL << SCTLR_U_Pos)                   /*!< \brief SCTLR: U Mask */
+
+#define SCTLR_FI_Pos                     21U                                    /*!< \brief SCTLR: FI Position */
+#define SCTLR_FI_Msk                     (1UL << SCTLR_FI_Pos)                  /*!< \brief SCTLR: FI Mask */
+
+#define SCTLR_UWXN_Pos                   20U                                    /*!< \brief SCTLR: UWXN Position */
+#define SCTLR_UWXN_Msk                   (1UL << SCTLR_UWXN_Pos)                /*!< \brief SCTLR: UWXN Mask */
+
+#define SCTLR_WXN_Pos                    19U                                    /*!< \brief SCTLR: WXN Position */
+#define SCTLR_WXN_Msk                    (1UL << SCTLR_WXN_Pos)                 /*!< \brief SCTLR: WXN Mask */
+
+#define SCTLR_HA_Pos                     17U                                    /*!< \brief SCTLR: HA Position */
+#define SCTLR_HA_Msk                     (1UL << SCTLR_HA_Pos)                  /*!< \brief SCTLR: HA Mask */
+
+#define SCTLR_RR_Pos                     14U                                    /*!< \brief SCTLR: RR Position */
+#define SCTLR_RR_Msk                     (1UL << SCTLR_RR_Pos)                  /*!< \brief SCTLR: RR Mask */
+
+#define SCTLR_V_Pos                      13U                                    /*!< \brief SCTLR: V Position */
+#define SCTLR_V_Msk                      (1UL << SCTLR_V_Pos)                   /*!< \brief SCTLR: V Mask */
+
+#define SCTLR_I_Pos                      12U                                    /*!< \brief SCTLR: I Position */
+#define SCTLR_I_Msk                      (1UL << SCTLR_I_Pos)                   /*!< \brief SCTLR: I Mask */
+
+#define SCTLR_Z_Pos                      11U                                    /*!< \brief SCTLR: Z Position */
+#define SCTLR_Z_Msk                      (1UL << SCTLR_Z_Pos)                   /*!< \brief SCTLR: Z Mask */
+
+#define SCTLR_SW_Pos                     10U                                    /*!< \brief SCTLR: SW Position */
+#define SCTLR_SW_Msk                     (1UL << SCTLR_SW_Pos)                  /*!< \brief SCTLR: SW Mask */
+
+#define SCTLR_B_Pos                      7U                                     /*!< \brief SCTLR: B Position */
+#define SCTLR_B_Msk                      (1UL << SCTLR_B_Pos)                   /*!< \brief SCTLR: B Mask */
+
+#define SCTLR_CP15BEN_Pos                5U                                     /*!< \brief SCTLR: CP15BEN Position */
+#define SCTLR_CP15BEN_Msk                (1UL << SCTLR_CP15BEN_Pos)             /*!< \brief SCTLR: CP15BEN Mask */
+
+#define SCTLR_C_Pos                      2U                                     /*!< \brief SCTLR: C Position */
+#define SCTLR_C_Msk                      (1UL << SCTLR_C_Pos)                   /*!< \brief SCTLR: C Mask */
+
+#define SCTLR_A_Pos                      1U                                     /*!< \brief SCTLR: A Position */
+#define SCTLR_A_Msk                      (1UL << SCTLR_A_Pos)                   /*!< \brief SCTLR: A Mask */
+
+#define SCTLR_M_Pos                      0U                                     /*!< \brief SCTLR: M Position */
+#define SCTLR_M_Msk                      (1UL << SCTLR_M_Pos)                   /*!< \brief SCTLR: M Mask */
+
+/* CP15 Register ACTLR */
+typedef union
+{
+#if __CORTEX_A == 5 || defined(DOXYGEN)
+  /** \brief Structure used for bit access on Cortex-A5 */
+  struct
+  {
+    uint32_t FW:1;                      /*!< \brief bit:      0  Cache and TLB maintenance broadcast */
+    RESERVED(0:5, uint32_t)              
+    uint32_t SMP:1;                      /*!< \brief bit:     6  Enables coherent requests to the processor */
+    uint32_t EXCL:1;                     /*!< \brief bit:     7  Exclusive L1/L2 cache control */
+    RESERVED(1:2, uint32_t)
+    uint32_t DODMBS:1;                   /*!< \brief bit:    10  Disable optimized data memory barrier behavior */
+    uint32_t DWBST:1;                    /*!< \brief bit:    11  AXI data write bursts to Normal memory */
+    uint32_t RADIS:1;                    /*!< \brief bit:    12  L1 Data Cache read-allocate mode disable */
+    uint32_t L1PCTL:2;                   /*!< \brief bit:13..14  L1 Data prefetch control */    
+    uint32_t BP:2;                       /*!< \brief bit:16..15  Branch prediction policy */
+    uint32_t RSDIS:1;                    /*!< \brief bit:    17  Disable return stack operation */
+    uint32_t BTDIS:1;                    /*!< \brief bit:    18  Disable indirect Branch Target Address Cache (BTAC) */
+    RESERVED(3:9, uint32_t)             
+    uint32_t DBDI:1;                     /*!< \brief bit:    28  Disable branch dual issue */
+    RESERVED(7:3, uint32_t)              
+ } b;
+#endif  
+#if __CORTEX_A == 7 || defined(DOXYGEN)
+  /** \brief Structure used for bit access on Cortex-A7 */
+  struct
+  {
+    RESERVED(0:6, uint32_t)              
+    uint32_t SMP:1;                      /*!< \brief bit:     6  Enables coherent requests to the processor */
+    RESERVED(1:3, uint32_t)              
+    uint32_t DODMBS:1;                   /*!< \brief bit:    10  Disable optimized data memory barrier behavior */
+    uint32_t L2RADIS:1;                  /*!< \brief bit:    11  L2 Data Cache read-allocate mode disable */
+    uint32_t L1RADIS:1;                  /*!< \brief bit:    12  L1 Data Cache read-allocate mode disable */
+    uint32_t L1PCTL:2;                   /*!< \brief bit:13..14  L1 Data prefetch control */
+    uint32_t DDVM:1;                     /*!< \brief bit:    15  Disable Distributed Virtual Memory (DVM) transactions */
+    RESERVED(3:12, uint32_t)             
+    uint32_t DDI:1;                      /*!< \brief bit:    28  Disable dual issue */
+    RESERVED(7:3, uint32_t)              
+  } b;
+#endif  
+#if __CORTEX_A == 9 || defined(DOXYGEN)
+  /** \brief Structure used for bit access on Cortex-A9 */
+  struct
+  {
+    uint32_t FW:1;                       /*!< \brief bit:     0  Cache and TLB maintenance broadcast */
+    RESERVED(0:1, uint32_t)
+    uint32_t L1PE:1;                     /*!< \brief bit:     2  Dside prefetch */
+    uint32_t WFLZM:1;                    /*!< \brief bit:     3  Cache and TLB maintenance broadcast */
+    RESERVED(1:2, uint32_t)
+    uint32_t SMP:1;                      /*!< \brief bit:     6  Enables coherent requests to the processor */
+    uint32_t EXCL:1;                     /*!< \brief bit:     7  Exclusive L1/L2 cache control */
+    uint32_t AOW:1;                      /*!< \brief bit:     8  Enable allocation in one cache way only */
+    uint32_t PARITY:1;                   /*!< \brief bit:     9  Support for parity checking, if implemented */
+    RESERVED(7:22, uint32_t)              
+  } b;
+#endif  
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} ACTLR_Type;
+
+#define ACTLR_DDI_Pos                    28U                                     /*!< \brief ACTLR: DDI Position */
+#define ACTLR_DDI_Msk                    (1UL << ACTLR_DDI_Pos)                  /*!< \brief ACTLR: DDI Mask */
+
+#define ACTLR_DBDI_Pos                   28U                                     /*!< \brief ACTLR: DBDI Position */
+#define ACTLR_DBDI_Msk                   (1UL << ACTLR_DBDI_Pos)                 /*!< \brief ACTLR: DBDI Mask */
+
+#define ACTLR_BTDIS_Pos                  18U                                     /*!< \brief ACTLR: BTDIS Position */
+#define ACTLR_BTDIS_Msk                  (1UL << ACTLR_BTDIS_Pos)                /*!< \brief ACTLR: BTDIS Mask */
+
+#define ACTLR_RSDIS_Pos                  17U                                     /*!< \brief ACTLR: RSDIS Position */
+#define ACTLR_RSDIS_Msk                  (1UL << ACTLR_RSDIS_Pos)                /*!< \brief ACTLR: RSDIS Mask */
+
+#define ACTLR_BP_Pos                     15U                                     /*!< \brief ACTLR: BP Position */
+#define ACTLR_BP_Msk                     (3UL << ACTLR_BP_Pos)                   /*!< \brief ACTLR: BP Mask */
+
+#define ACTLR_DDVM_Pos                   15U                                     /*!< \brief ACTLR: DDVM Position */
+#define ACTLR_DDVM_Msk                   (1UL << ACTLR_DDVM_Pos)                 /*!< \brief ACTLR: DDVM Mask */
+
+#define ACTLR_L1PCTL_Pos                 13U                                     /*!< \brief ACTLR: L1PCTL Position */
+#define ACTLR_L1PCTL_Msk                 (3UL << ACTLR_L1PCTL_Pos)               /*!< \brief ACTLR: L1PCTL Mask */
+
+#define ACTLR_RADIS_Pos                  12U                                     /*!< \brief ACTLR: RADIS Position */
+#define ACTLR_RADIS_Msk                  (1UL << ACTLR_RADIS_Pos)                /*!< \brief ACTLR: RADIS Mask */
+
+#define ACTLR_L1RADIS_Pos                12U                                     /*!< \brief ACTLR: L1RADIS Position */
+#define ACTLR_L1RADIS_Msk                (1UL << ACTLR_L1RADIS_Pos)              /*!< \brief ACTLR: L1RADIS Mask */
+
+#define ACTLR_DWBST_Pos                  11U                                     /*!< \brief ACTLR: DWBST Position */
+#define ACTLR_DWBST_Msk                  (1UL << ACTLR_DWBST_Pos)                /*!< \brief ACTLR: DWBST Mask */
+
+#define ACTLR_L2RADIS_Pos                11U                                     /*!< \brief ACTLR: L2RADIS Position */
+#define ACTLR_L2RADIS_Msk                (1UL << ACTLR_L2RADIS_Pos)              /*!< \brief ACTLR: L2RADIS Mask */
+
+#define ACTLR_DODMBS_Pos                 10U                                     /*!< \brief ACTLR: DODMBS Position */
+#define ACTLR_DODMBS_Msk                 (1UL << ACTLR_DODMBS_Pos)               /*!< \brief ACTLR: DODMBS Mask */
+
+#define ACTLR_PARITY_Pos                 9U                                      /*!< \brief ACTLR: PARITY Position */
+#define ACTLR_PARITY_Msk                 (1UL << ACTLR_PARITY_Pos)               /*!< \brief ACTLR: PARITY Mask */
+
+#define ACTLR_AOW_Pos                    8U                                      /*!< \brief ACTLR: AOW Position */
+#define ACTLR_AOW_Msk                    (1UL << ACTLR_AOW_Pos)                  /*!< \brief ACTLR: AOW Mask */
+
+#define ACTLR_EXCL_Pos                   7U                                      /*!< \brief ACTLR: EXCL Position */
+#define ACTLR_EXCL_Msk                   (1UL << ACTLR_EXCL_Pos)                 /*!< \brief ACTLR: EXCL Mask */
+
+#define ACTLR_SMP_Pos                    6U                                      /*!< \brief ACTLR: SMP Position */
+#define ACTLR_SMP_Msk                    (1UL << ACTLR_SMP_Pos)                  /*!< \brief ACTLR: SMP Mask */
+
+#define ACTLR_WFLZM_Pos                  3U                                      /*!< \brief ACTLR: WFLZM Position */
+#define ACTLR_WFLZM_Msk                  (1UL << ACTLR_WFLZM_Pos)                /*!< \brief ACTLR: WFLZM Mask */
+
+#define ACTLR_L1PE_Pos                   2U                                      /*!< \brief ACTLR: L1PE Position */
+#define ACTLR_L1PE_Msk                   (1UL << ACTLR_L1PE_Pos)                 /*!< \brief ACTLR: L1PE Mask */
+
+#define ACTLR_FW_Pos                     0U                                      /*!< \brief ACTLR: FW Position */
+#define ACTLR_FW_Msk                     (1UL << ACTLR_FW_Pos)                   /*!< \brief ACTLR: FW Mask */
+
+/* CP15 Register CPACR */
+typedef union
+{
+  struct
+  {
+    uint32_t CP0:2;                      /*!< \brief bit:  0..1  Access rights for coprocessor 0 */
+    uint32_t CP1:2;                      /*!< \brief bit:  2..3  Access rights for coprocessor 1 */
+    uint32_t CP2:2;                      /*!< \brief bit:  4..5  Access rights for coprocessor 2 */
+    uint32_t CP3:2;                      /*!< \brief bit:  6..7  Access rights for coprocessor 3 */
+    uint32_t CP4:2;                      /*!< \brief bit:  8..9  Access rights for coprocessor 4 */
+    uint32_t CP5:2;                      /*!< \brief bit:10..11  Access rights for coprocessor 5 */
+    uint32_t CP6:2;                      /*!< \brief bit:12..13  Access rights for coprocessor 6 */
+    uint32_t CP7:2;                      /*!< \brief bit:14..15  Access rights for coprocessor 7 */
+    uint32_t CP8:2;                      /*!< \brief bit:16..17  Access rights for coprocessor 8 */
+    uint32_t CP9:2;                      /*!< \brief bit:18..19  Access rights for coprocessor 9 */
+    uint32_t CP10:2;                     /*!< \brief bit:20..21  Access rights for coprocessor 10 */
+    uint32_t CP11:2;                     /*!< \brief bit:22..23  Access rights for coprocessor 11 */
+    uint32_t CP12:2;                     /*!< \brief bit:24..25  Access rights for coprocessor 11 */
+    uint32_t CP13:2;                     /*!< \brief bit:26..27  Access rights for coprocessor 11 */
+    uint32_t TRCDIS:1;                   /*!< \brief bit:    28  Disable CP14 access to trace registers */
+    RESERVED(0:1, uint32_t)              
+    uint32_t D32DIS:1;                   /*!< \brief bit:    30  Disable use of registers D16-D31 of the VFP register file */
+    uint32_t ASEDIS:1;                   /*!< \brief bit:    31  Disable Advanced SIMD Functionality */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} CPACR_Type;
+
+#define CPACR_ASEDIS_Pos                 31U                                    /*!< \brief CPACR: ASEDIS Position */
+#define CPACR_ASEDIS_Msk                 (1UL << CPACR_ASEDIS_Pos)              /*!< \brief CPACR: ASEDIS Mask */
+
+#define CPACR_D32DIS_Pos                 30U                                    /*!< \brief CPACR: D32DIS Position */
+#define CPACR_D32DIS_Msk                 (1UL << CPACR_D32DIS_Pos)              /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_TRCDIS_Pos                 28U                                    /*!< \brief CPACR: D32DIS Position */
+#define CPACR_TRCDIS_Msk                 (1UL << CPACR_D32DIS_Pos)              /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_CP_Pos_(n)                 (n*2U)                                 /*!< \brief CPACR: CPn Position */
+#define CPACR_CP_Msk_(n)                 (3UL << CPACR_CP_Pos_(n))              /*!< \brief CPACR: CPn Mask */
+
+#define CPACR_CP_NA                      0U                                     /*!< \brief CPACR CPn field: Access denied. */
+#define CPACR_CP_PL1                     1U                                     /*!< \brief CPACR CPn field: Accessible from PL1 only. */
+#define CPACR_CP_FA                      3U                                     /*!< \brief CPACR CPn field: Full access. */
+
+/* CP15 Register DFSR */
+typedef union
+{
+  struct
+  {
+    uint32_t FS0:4;                      /*!< \brief bit: 0.. 3  Fault Status bits bit 0-3 */
+    uint32_t Domain:4;                   /*!< \brief bit: 4.. 7  Fault on which domain */
+    RESERVED(0:1, uint32_t)              
+    uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    uint32_t FS1:1;                      /*!< \brief bit:    10  Fault Status bits bit 4 */
+    uint32_t WnR:1;                      /*!< \brief bit:    11  Write not Read bit */
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    uint32_t CM:1;                       /*!< \brief bit:    13  Cache maintenance fault */
+    RESERVED(1:18, uint32_t)             
+  } s;                                   /*!< \brief Structure used for bit  access in short format */
+  struct
+  {
+    uint32_t STATUS:5;                   /*!< \brief bit: 0.. 5  Fault Status bits */
+    RESERVED(0:3, uint32_t)              
+    uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    RESERVED(1:1, uint32_t)              
+    uint32_t WnR:1;                      /*!< \brief bit:    11  Write not Read bit */
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    uint32_t CM:1;                       /*!< \brief bit:    13  Cache maintenance fault */
+    RESERVED(2:18, uint32_t)             
+  } l;                                   /*!< \brief Structure used for bit  access in long format */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} DFSR_Type;
+
+#define DFSR_CM_Pos                      13U                                    /*!< \brief DFSR: CM Position */
+#define DFSR_CM_Msk                      (1UL << DFSR_CM_Pos)                   /*!< \brief DFSR: CM Mask */
+
+#define DFSR_Ext_Pos                     12U                                    /*!< \brief DFSR: Ext Position */
+#define DFSR_Ext_Msk                     (1UL << DFSR_Ext_Pos)                  /*!< \brief DFSR: Ext Mask */
+
+#define DFSR_WnR_Pos                     11U                                    /*!< \brief DFSR: WnR Position */
+#define DFSR_WnR_Msk                     (1UL << DFSR_WnR_Pos)                  /*!< \brief DFSR: WnR Mask */
+
+#define DFSR_FS1_Pos                     10U                                    /*!< \brief DFSR: FS1 Position */
+#define DFSR_FS1_Msk                     (1UL << DFSR_FS1_Pos)                  /*!< \brief DFSR: FS1 Mask */
+
+#define DFSR_LPAE_Pos                    9U                                    /*!< \brief DFSR: LPAE Position */
+#define DFSR_LPAE_Msk                    (1UL << DFSR_LPAE_Pos)                /*!< \brief DFSR: LPAE Mask */
+
+#define DFSR_Domain_Pos                  4U                                     /*!< \brief DFSR: Domain Position */
+#define DFSR_Domain_Msk                  (0xFUL << DFSR_Domain_Pos)             /*!< \brief DFSR: Domain Mask */
+
+#define DFSR_FS0_Pos                     0U                                     /*!< \brief DFSR: FS0 Position */
+#define DFSR_FS0_Msk                     (0xFUL << DFSR_FS0_Pos)                /*!< \brief DFSR: FS0 Mask */
+
+#define DFSR_STATUS_Pos                  0U                                     /*!< \brief DFSR: STATUS Position */
+#define DFSR_STATUS_Msk                  (0x3FUL << DFSR_STATUS_Pos)            /*!< \brief DFSR: STATUS Mask */
+
+/* CP15 Register IFSR */
+typedef union
+{
+  struct
+  {
+    uint32_t FS0:4;                      /*!< \brief bit: 0.. 3  Fault Status bits bit 0-3 */
+    RESERVED(0:5, uint32_t)              
+    uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    uint32_t FS1:1;                      /*!< \brief bit:    10  Fault Status bits bit 4 */
+    RESERVED(1:1, uint32_t)              
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    RESERVED(2:19, uint32_t)             
+  } s;                                   /*!< \brief Structure used for bit access in short format */
+  struct
+  {
+    uint32_t STATUS:6;                   /*!< \brief bit: 0.. 5  Fault Status bits */
+    RESERVED(0:3, uint32_t)              
+    uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    RESERVED(1:2, uint32_t)              
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    RESERVED(2:19, uint32_t)             
+  } l;                                   /*!< \brief Structure used for bit access in long format */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} IFSR_Type;
+
+#define IFSR_ExT_Pos                     12U                                    /*!< \brief IFSR: ExT Position */
+#define IFSR_ExT_Msk                     (1UL << IFSR_ExT_Pos)                  /*!< \brief IFSR: ExT Mask */
+
+#define IFSR_FS1_Pos                     10U                                    /*!< \brief IFSR: FS1 Position */
+#define IFSR_FS1_Msk                     (1UL << IFSR_FS1_Pos)                  /*!< \brief IFSR: FS1 Mask */
+
+#define IFSR_LPAE_Pos                    9U                                     /*!< \brief IFSR: LPAE Position */
+#define IFSR_LPAE_Msk                    (0x1UL << IFSR_LPAE_Pos)               /*!< \brief IFSR: LPAE Mask */
+
+#define IFSR_FS0_Pos                     0U                                     /*!< \brief IFSR: FS0 Position */
+#define IFSR_FS0_Msk                     (0xFUL << IFSR_FS0_Pos)                /*!< \brief IFSR: FS0 Mask */
+
+#define IFSR_STATUS_Pos                  0U                                     /*!< \brief IFSR: STATUS Position */
+#define IFSR_STATUS_Msk                  (0x3FUL << IFSR_STATUS_Pos)            /*!< \brief IFSR: STATUS Mask */
+
+/* CP15 Register ISR */
+typedef union
+{
+  struct
+  {
+    RESERVED(0:6, uint32_t)              
+    uint32_t F:1;                        /*!< \brief bit:     6  FIQ pending bit */
+    uint32_t I:1;                        /*!< \brief bit:     7  IRQ pending bit */
+    uint32_t A:1;                        /*!< \brief bit:     8  External abort pending bit */
+    RESERVED(1:23, uint32_t)             
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} ISR_Type;
+
+#define ISR_A_Pos                        13U                                    /*!< \brief ISR: A Position */
+#define ISR_A_Msk                        (1UL << ISR_A_Pos)                     /*!< \brief ISR: A Mask */
+
+#define ISR_I_Pos                        12U                                    /*!< \brief ISR: I Position */
+#define ISR_I_Msk                        (1UL << ISR_I_Pos)                     /*!< \brief ISR: I Mask */
+
+#define ISR_F_Pos                        11U                                    /*!< \brief ISR: F Position */
+#define ISR_F_Msk                        (1UL << ISR_F_Pos)                     /*!< \brief ISR: F Mask */
+
+/* DACR Register */
+#define DACR_D_Pos_(n)                   (2U*n)                                 /*!< \brief DACR: Dn Position */
+#define DACR_D_Msk_(n)                   (3UL << DACR_D_Pos_(n))                /*!< \brief DACR: Dn Mask */
+#define DACR_Dn_NOACCESS                 0U                                     /*!< \brief DACR Dn field: No access */
+#define DACR_Dn_CLIENT                   1U                                     /*!< \brief DACR Dn field: Client */
+#define DACR_Dn_MANAGER                  3U                                     /*!< \brief DACR Dn field: Manager */
+
+/**
+  \brief     Mask and shift a bit field value for use in a register bit range.
+  \param [in] field  Name of the register bit field.
+  \param [in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param [in] field  Name of the register bit field.
+  \param [in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+
+/**
+ \brief  Union type to access the L2C_310 Cache Controller.
+*/
+#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+typedef struct
+{
+  __IM  uint32_t CACHE_ID;                   /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register               */
+  __IM  uint32_t CACHE_TYPE;                 /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register             */
+        RESERVED(0[0x3e], uint32_t)
+  __IOM uint32_t CONTROL;                    /*!< \brief Offset: 0x0100 (R/W) Control Register                */
+  __IOM uint32_t AUX_CNT;                    /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control               */
+        RESERVED(1[0x3e], uint32_t)
+  __IOM uint32_t EVENT_CONTROL;              /*!< \brief Offset: 0x0200 (R/W) Event Counter Control           */
+  __IOM uint32_t EVENT_COUNTER1_CONF;        /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration   */
+  __IOM uint32_t EVENT_COUNTER0_CONF;        /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration   */
+        RESERVED(2[0x2], uint32_t)
+  __IOM uint32_t INTERRUPT_MASK;             /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask                  */
+  __IM  uint32_t MASKED_INT_STATUS;          /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status         */
+  __IM  uint32_t RAW_INT_STATUS;             /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status            */
+  __OM  uint32_t INTERRUPT_CLEAR;            /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear                 */
+        RESERVED(3[0x143], uint32_t)
+  __IOM uint32_t CACHE_SYNC;                 /*!< \brief Offset: 0x0730 (R/W) Cache Sync                      */
+        RESERVED(4[0xf], uint32_t)
+  __IOM uint32_t INV_LINE_PA;                /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA           */
+        RESERVED(6[2], uint32_t)
+  __IOM uint32_t INV_WAY;                    /*!< \brief Offset: 0x077c (R/W) Invalidate by Way               */
+        RESERVED(5[0xc], uint32_t)
+  __IOM uint32_t CLEAN_LINE_PA;              /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA                */
+        RESERVED(7[1], uint32_t)
+  __IOM uint32_t CLEAN_LINE_INDEX_WAY;       /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way         */
+  __IOM uint32_t CLEAN_WAY;                  /*!< \brief Offset: 0x07bc (R/W) Clean by Way                    */
+        RESERVED(8[0xc], uint32_t)
+  __IOM uint32_t CLEAN_INV_LINE_PA;          /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA  */
+        RESERVED(9[1], uint32_t)
+  __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY;   /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way  */
+  __IOM uint32_t CLEAN_INV_WAY;              /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way     */
+        RESERVED(10[0x40], uint32_t)
+  __IOM uint32_t DATA_LOCK_0_WAY;            /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way          */
+  __IOM uint32_t INST_LOCK_0_WAY;            /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way   */
+  __IOM uint32_t DATA_LOCK_1_WAY;            /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way          */
+  __IOM uint32_t INST_LOCK_1_WAY;            /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way   */
+  __IOM uint32_t DATA_LOCK_2_WAY;            /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way          */
+  __IOM uint32_t INST_LOCK_2_WAY;            /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way   */
+  __IOM uint32_t DATA_LOCK_3_WAY;            /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way          */
+  __IOM uint32_t INST_LOCK_3_WAY;            /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way   */
+  __IOM uint32_t DATA_LOCK_4_WAY;            /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way          */
+  __IOM uint32_t INST_LOCK_4_WAY;            /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way   */
+  __IOM uint32_t DATA_LOCK_5_WAY;            /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way          */
+  __IOM uint32_t INST_LOCK_5_WAY;            /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way   */
+  __IOM uint32_t DATA_LOCK_6_WAY;            /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way          */
+  __IOM uint32_t INST_LOCK_6_WAY;            /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way   */
+  __IOM uint32_t DATA_LOCK_7_WAY;            /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way          */
+  __IOM uint32_t INST_LOCK_7_WAY;            /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way   */
+        RESERVED(11[0x4], uint32_t)
+  __IOM uint32_t LOCK_LINE_EN;               /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable         */
+  __IOM uint32_t UNLOCK_ALL_BY_WAY;          /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way         */
+        RESERVED(12[0xaa], uint32_t)
+  __IOM uint32_t ADDRESS_FILTER_START;       /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start         */
+  __IOM uint32_t ADDRESS_FILTER_END;         /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End           */
+        RESERVED(13[0xce], uint32_t)
+  __IOM uint32_t DEBUG_CONTROL;              /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register          */
+} L2C_310_TypeDef;
+
+#define L2C_310           ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
+#endif
+
+#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+    
+/** \brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)
+*/
+typedef struct
+{
+  __IOM uint32_t CTLR;                 /*!< \brief  Offset: 0x000 (R/W) Distributor Control Register */
+  __IM  uint32_t TYPER;                /*!< \brief  Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+  __IM  uint32_t IIDR;                 /*!< \brief  Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
+        RESERVED(0, uint32_t)
+  __IOM uint32_t STATUSR;              /*!< \brief  Offset: 0x010 (R/W) Error Reporting Status Register, optional */
+        RESERVED(1[11], uint32_t)
+  __OM  uint32_t SETSPI_NSR;           /*!< \brief  Offset: 0x040 ( /W) Set SPI Register */
+        RESERVED(2, uint32_t)
+  __OM  uint32_t CLRSPI_NSR;           /*!< \brief  Offset: 0x048 ( /W) Clear SPI Register */
+        RESERVED(3, uint32_t)
+  __OM  uint32_t SETSPI_SR;            /*!< \brief  Offset: 0x050 ( /W) Set SPI, Secure Register */
+        RESERVED(4, uint32_t)
+  __OM  uint32_t CLRSPI_SR;            /*!< \brief  Offset: 0x058 ( /W) Clear SPI, Secure Register */
+        RESERVED(5[9], uint32_t)
+  __IOM uint32_t IGROUPR[32];          /*!< \brief  Offset: 0x080 (R/W) Interrupt Group Registers */
+  __IOM uint32_t ISENABLER[32];        /*!< \brief  Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
+  __IOM uint32_t ICENABLER[32];        /*!< \brief  Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
+  __IOM uint32_t ISPENDR[32];          /*!< \brief  Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
+  __IOM uint32_t ICPENDR[32];          /*!< \brief  Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
+  __IOM uint32_t ISACTIVER[32];        /*!< \brief  Offset: 0x300 (R/W) Interrupt Set-Active Registers */
+  __IOM uint32_t ICACTIVER[32];        /*!< \brief  Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
+  __IOM uint32_t IPRIORITYR[255];      /*!< \brief  Offset: 0x400 (R/W) Interrupt Priority Registers */
+        RESERVED(6, uint32_t)
+  __IOM uint32_t  ITARGETSR[255];      /*!< \brief  Offset: 0x800 (R/W) Interrupt Targets Registers */
+        RESERVED(7, uint32_t)
+  __IOM uint32_t ICFGR[64];            /*!< \brief  Offset: 0xC00 (R/W) Interrupt Configuration Registers */
+  __IOM uint32_t IGRPMODR[32];         /*!< \brief  Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
+        RESERVED(8[32], uint32_t)
+  __IOM uint32_t NSACR[64];            /*!< \brief  Offset: 0xE00 (R/W) Non-secure Access Control Registers */
+  __OM  uint32_t SGIR;                 /*!< \brief  Offset: 0xF00 ( /W) Software Generated Interrupt Register */
+        RESERVED(9[3], uint32_t)
+  __IOM uint32_t CPENDSGIR[4];         /*!< \brief  Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
+  __IOM uint32_t SPENDSGIR[4];         /*!< \brief  Offset: 0xF20 (R/W) SGI Set-Pending Registers */
+        RESERVED(10[5236], uint32_t)
+  __IOM uint64_t IROUTER[988];         /*!< \brief  Offset: 0x6100(R/W) Interrupt Routing Registers */
+}  GICDistributor_Type;
+
+#define GICDistributor      ((GICDistributor_Type      *)     GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
+
+/** \brief  Structure type to access the Generic Interrupt Controller Interface (GICC)
+*/
+typedef struct
+{
+  __IOM uint32_t CTLR;                 /*!< \brief  Offset: 0x000 (R/W) CPU Interface Control Register */
+  __IOM uint32_t PMR;                  /*!< \brief  Offset: 0x004 (R/W) Interrupt Priority Mask Register */
+  __IOM uint32_t BPR;                  /*!< \brief  Offset: 0x008 (R/W) Binary Point Register */
+  __IM  uint32_t IAR;                  /*!< \brief  Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
+  __OM  uint32_t EOIR;                 /*!< \brief  Offset: 0x010 ( /W) End Of Interrupt Register */
+  __IM  uint32_t RPR;                  /*!< \brief  Offset: 0x014 (R/ ) Running Priority Register */
+  __IM  uint32_t HPPIR;                /*!< \brief  Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
+  __IOM uint32_t ABPR;                 /*!< \brief  Offset: 0x01C (R/W) Aliased Binary Point Register */
+  __IM  uint32_t AIAR;                 /*!< \brief  Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
+  __OM  uint32_t AEOIR;                /*!< \brief  Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
+  __IM  uint32_t AHPPIR;               /*!< \brief  Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
+  __IOM uint32_t STATUSR;              /*!< \brief  Offset: 0x02C (R/W) Error Reporting Status Register, optional */
+        RESERVED(1[40], uint32_t)
+  __IOM uint32_t APR[4];               /*!< \brief  Offset: 0x0D0 (R/W) Active Priority Register */
+  __IOM uint32_t NSAPR[4];             /*!< \brief  Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
+        RESERVED(2[3], uint32_t)
+  __IM  uint32_t IIDR;                 /*!< \brief  Offset: 0x0FC (R/ ) CPU Interface Identification Register */
+        RESERVED(3[960], uint32_t)
+  __OM  uint32_t DIR;                  /*!< \brief  Offset: 0x1000( /W) Deactivate Interrupt Register */
+}  GICInterface_Type;
+
+#define GICInterface        ((GICInterface_Type        *)     GIC_INTERFACE_BASE )   /*!< \brief GIC Interface register set access pointer */
+#endif
+
+#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
+/** \brief Structure type to access the Private Timer
+*/
+typedef struct
+{
+  __IOM uint32_t LOAD;            //!< \brief  Offset: 0x000 (R/W) Private Timer Load Register
+  __IOM uint32_t COUNTER;         //!< \brief  Offset: 0x004 (R/W) Private Timer Counter Register
+  __IOM uint32_t CONTROL;         //!< \brief  Offset: 0x008 (R/W) Private Timer Control Register
+  __IOM uint32_t ISR;             //!< \brief  Offset: 0x00C (R/W) Private Timer Interrupt Status Register
+        RESERVED(0[4], uint32_t)
+  __IOM uint32_t WLOAD;           //!< \brief  Offset: 0x020 (R/W) Watchdog Load Register
+  __IOM uint32_t WCOUNTER;        //!< \brief  Offset: 0x024 (R/W) Watchdog Counter Register
+  __IOM uint32_t WCONTROL;        //!< \brief  Offset: 0x028 (R/W) Watchdog Control Register
+  __IOM uint32_t WISR;            //!< \brief  Offset: 0x02C (R/W) Watchdog Interrupt Status Register
+  __IOM uint32_t WRESET;          //!< \brief  Offset: 0x030 (R/W) Watchdog Reset Status Register
+  __OM  uint32_t WDISABLE;        //!< \brief  Offset: 0x034 ( /W) Watchdog Disable Register
+} Timer_Type;
+#define PTIM ((Timer_Type *) TIMER_BASE )   /*!< \brief Timer register struct */
+#endif
+#endif
+
+ /*******************************************************************************
+  *                Hardware Abstraction Layer
+   Core Function Interface contains:
+   - L1 Cache Functions
+   - L2C-310 Cache Controller Functions 
+   - PL1 Timer Functions
+   - GIC Functions
+   - MMU Functions
+  ******************************************************************************/
+ 
+/* ##########################  L1 Cache functions  ################################# */
+
+/** \brief Enable Caches by setting I and C bits in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_EnableCaches(void) {
+  __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);
+  __ISB();
+}
+
+/** \brief Disable Caches by clearing I and C bits in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_DisableCaches(void) {
+  __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
+  __ISB();
+}
+
+/** \brief  Enable Branch Prediction by setting Z bit in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
+  __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);
+  __ISB();
+}
+
+/** \brief  Disable Branch Prediction by clearing Z bit in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
+  __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
+  __ISB();
+}
+
+/** \brief  Invalidate entire branch predictor array
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
+  __set_BPIALL(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new state
+}
+
+/** \brief  Invalidate the whole instruction cache
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
+  __set_ICIALLU(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+/** \brief  Clean data cache line by address.
+* \param [in] va Pointer to data to clear the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
+  __set_DCCMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Invalidate data cache line by address.
+* \param [in] va Pointer to data to invalidate the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
+  __set_DCIMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate data cache by address.
+* \param [in] va Pointer to data to invalidate the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
+  __set_DCCIMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief Calculate log2 rounded up
+*  - log(0)  => 0
+*  - log(1)  => 0
+*  - log(2)  => 1
+*  - log(3)  => 2
+*  - log(4)  => 2
+*  - log(5)  => 3
+*        :      :
+*  - log(16) => 4
+*  - log(32) => 5
+*        :      :
+* \param [in] n input value parameter 
+* \return log2(n)
+*/
+__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
+{
+  if (n < 2U) {
+    return 0U;
+  }
+  uint8_t log = 0U;
+  uint32_t t = n;
+  while(t > 1U)
+  {
+    log++;
+    t >>= 1U;
+  }
+  if (n & 1U) { log++; }
+  return log;
+}
+
+/** \brief  Apply cache maintenance to given cache level.
+* \param [in] level cache level to be maintained
+* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+*/
+__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
+{
+  register volatile uint32_t Dummy;
+  register volatile uint32_t ccsidr;
+  uint32_t num_sets;
+  uint32_t num_ways;
+  uint32_t shift_way;
+  uint32_t log2_linesize;
+   int32_t log2_num_ways;
+
+  Dummy = level << 1U;
+  /* set csselr, select ccsidr register */
+  __set_CCSIDR(Dummy);
+  /* get current ccsidr register */
+  ccsidr = __get_CCSIDR();
+  num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
+  num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
+  log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
+  log2_num_ways = __log2_up(num_ways);
+  if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
+    return; // FATAL ERROR
+  }
+  shift_way = 32U - (uint32_t)log2_num_ways;
+  for(int32_t way = num_ways-1; way >= 0; way--)
+  {
+    for(int32_t set = num_sets-1; set >= 0; set--)
+    {
+      Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);
+      switch (maint)
+      {
+        case 0U: __set_DCISW(Dummy);  break;
+        case 1U: __set_DCCSW(Dummy);  break;
+        default: __set_DCCISW(Dummy); break;
+      }
+    }
+  }
+  __DMB();
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+*/
+__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
+  register volatile uint32_t clidr;
+  uint32_t cache_type;
+  clidr =  __get_CLIDR();
+  for(uint32_t i = 0U; i<7U; i++)
+  {
+    cache_type = (clidr >> i*3U) & 0x7UL;
+    if ((cache_type >= 2U) && (cache_type <= 4U))
+    {
+      __L1C_MaintainDCacheSetWay(i, op);
+    }
+  }
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+* \deprecated Use generic L1C_CleanInvalidateCache instead.
+*/
+CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
+  L1C_CleanInvalidateCache(op);
+}
+
+/** \brief  Invalidate the whole data cache.
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
+  L1C_CleanInvalidateCache(0);
+}
+
+/** \brief  Clean the whole data cache.
+ */
+__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
+  L1C_CleanInvalidateCache(1);
+}
+
+/** \brief  Clean and invalidate the whole data cache.
+ */
+__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
+  L1C_CleanInvalidateCache(2);
+}
+
+/* ##########################  L2 Cache functions  ################################# */
+#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+/** \brief Cache Sync operation by writing CACHE_SYNC register.
+*/
+__STATIC_INLINE void L2C_Sync(void)
+{
+  L2C_310->CACHE_SYNC = 0x0;
+}
+
+/** \brief Read cache controller cache ID from CACHE_ID register.
+ * \return L2C_310_TypeDef::CACHE_ID
+ */
+__STATIC_INLINE int L2C_GetID (void)
+{
+  return L2C_310->CACHE_ID;
+}
+
+/** \brief Read cache controller cache type from CACHE_TYPE register.
+*  \return L2C_310_TypeDef::CACHE_TYPE
+*/
+__STATIC_INLINE int L2C_GetType (void)
+{
+  return L2C_310->CACHE_TYPE;
+}
+
+/** \brief Invalidate all cache by way
+*/
+__STATIC_INLINE void L2C_InvAllByWay (void)
+{
+  unsigned int assoc;
+
+  if (L2C_310->AUX_CNT & (1U << 16U)) {
+    assoc = 16U;
+  } else {
+    assoc =  8U;
+  }
+  
+  L2C_310->INV_WAY = (1U << assoc) - 1U;
+  while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
+
+  L2C_Sync();
+}
+
+/** \brief Clean and Invalidate all cache by way
+*/
+__STATIC_INLINE void L2C_CleanInvAllByWay (void)
+{
+  unsigned int assoc;
+
+  if (L2C_310->AUX_CNT & (1U << 16U)) {
+    assoc = 16U;
+  } else {
+    assoc =  8U;
+  }
+
+  L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
+  while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
+
+  L2C_Sync();
+}
+
+/** \brief Enable Level 2 Cache
+*/
+__STATIC_INLINE void L2C_Enable(void)
+{
+  L2C_310->CONTROL = 0;
+  L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
+  L2C_310->DEBUG_CONTROL = 0;
+  L2C_310->DATA_LOCK_0_WAY = 0;
+  L2C_310->CACHE_SYNC = 0;
+  L2C_310->CONTROL = 0x01;
+  L2C_Sync();
+}
+
+/** \brief Disable Level 2 Cache
+*/
+__STATIC_INLINE void L2C_Disable(void)
+{
+  L2C_310->CONTROL = 0x00;
+  L2C_Sync();
+}
+
+/** \brief Invalidate cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_InvPa (void *pa)
+{
+  L2C_310->INV_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+
+/** \brief Clean cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_CleanPa (void *pa)
+{
+  L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+
+/** \brief Clean and invalidate cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_CleanInvPa (void *pa)
+{
+  L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+#endif
+
+/* ##########################  GIC functions  ###################################### */
+#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+  
+/** \brief  Enable the interrupt distributor using the GIC's CTLR register.
+*/
+__STATIC_INLINE void GIC_EnableDistributor(void)
+{
+  GICDistributor->CTLR |= 1U;
+}
+
+/** \brief Disable the interrupt distributor using the GIC's CTLR register.
+*/
+__STATIC_INLINE void GIC_DisableDistributor(void)
+{
+  GICDistributor->CTLR &=~1U;
+}
+
+/** \brief Read the GIC's TYPER register.
+* \return GICDistributor_Type::TYPER
+*/
+__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
+{
+  return (GICDistributor->TYPER);
+}
+
+/** \brief Reads the GIC's IIDR register.
+* \return GICDistributor_Type::IIDR
+*/
+__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
+{
+  return (GICDistributor->IIDR);
+}
+
+/** \brief Sets the GIC's ITARGETSR register for the given interrupt.
+* \param [in] IRQn Interrupt to be configured.
+* \param [in] cpu_target CPU interfaces to assign this interrupt to.
+*/
+__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
+{
+  uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
+  GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
+}
+
+/** \brief Read the GIC's ITARGETSR register.
+* \param [in] IRQn Interrupt to acquire the configuration for.
+* \return GICDistributor_Type::ITARGETSR
+*/
+__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
+{
+  return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+}
+
+/** \brief Enable the CPU's interrupt interface.
+*/
+__STATIC_INLINE void GIC_EnableInterface(void)
+{
+  GICInterface->CTLR |= 1U; //enable interface
+}
+
+/** \brief Disable the CPU's interrupt interface.
+*/
+__STATIC_INLINE void GIC_DisableInterface(void)
+{
+  GICInterface->CTLR &=~1U; //disable distributor
+}
+
+/** \brief Read the CPU's IAR register.
+* \return GICInterface_Type::IAR
+*/
+__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
+{
+  return (IRQn_Type)(GICInterface->IAR);
+}
+
+/** \brief Writes the given interrupt number to the CPU's EOIR register.
+* \param [in] IRQn The interrupt to be signaled as finished.
+*/
+__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
+{
+  GICInterface->EOIR = IRQn;
+}
+
+/** \brief Enables the given interrupt using GIC's ISENABLER register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
+{
+  GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
+}
+
+/** \brief Get interrupt enable status using GIC's ISENABLER register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
+*/
+__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+}
+
+/** \brief Disables the given interrupt using GIC's ICENABLER register.
+* \param [in] IRQn The interrupt to be disabled.
+*/
+__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
+{
+  GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
+}
+
+/** \brief Get interrupt pending status from GIC's ISPENDR register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - interrupt is not pending, 1 - interrupt is pendig.
+*/
+__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  uint32_t pend;
+
+  if (IRQn >= 16U) {
+    pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+  } else {
+    // INTID 0-15 Software Generated Interrupt
+    pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+    // No CPU identification offered
+    if (pend != 0U) {
+      pend = 1U;
+    } else {
+      pend = 0U;
+    }
+  }
+
+  return (pend);
+}
+
+/** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if (IRQn >= 16U) {
+    GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
+  } else {
+    // INTID 0-15 Software Generated Interrupt
+    GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
+    // Forward the interrupt to the CPU interface that requested it
+    GICDistributor->SGIR = (IRQn | 0x02000000U);
+  }
+}
+
+/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if (IRQn >= 16U) {
+    GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
+  } else {
+    // INTID 0-15 Software Generated Interrupt
+    GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
+  }
+}
+
+/** \brief Sets the interrupt configuration using GIC's ICFGR register.
+* \param [in] IRQn The interrupt to be configured.
+* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
+*                                           Bit 1: 0 - level sensitive, 1 - edge triggered
+*/
+__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
+{
+  uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
+  uint32_t shift = (IRQn % 16U) << 1U;
+
+  icfgr &= (~(3U         << shift));
+  icfgr |= (  int_config << shift);
+
+  GICDistributor->ICFGR[IRQn / 16U] = icfgr;
+}
+
+/** \brief Get the interrupt configuration from the GIC's ICFGR register.
+* \param [in] IRQn Interrupt to acquire the configuration for.
+* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
+*                                 Bit 1: 0 - level sensitive, 1 - edge triggered
+*/
+__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
+{
+  return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
+}
+
+/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
+* \param [in] IRQn The interrupt to be configured.
+* \param [in] priority The priority for the interrupt, lower values denote higher priorities.
+*/
+__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
+  GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
+}
+
+/** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
+* \param [in] IRQn The interrupt to be queried.
+*/
+__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
+{
+  return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+}
+
+/** \brief Set the interrupt priority mask using CPU's PMR register.
+* \param [in] priority Priority mask to be set.
+*/
+__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
+{
+  GICInterface->PMR = priority & 0xFFUL; //set priority mask
+}
+
+/** \brief Read the current interrupt priority mask from CPU's PMR register.
+* \result GICInterface_Type::PMR
+*/
+__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
+{
+  return GICInterface->PMR;
+}
+
+/** \brief Configures the group priority and subpriority split point using CPU's BPR register.
+* \param [in] binary_point Amount of bits used as subpriority.
+*/
+__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
+{
+  GICInterface->BPR = binary_point & 7U; //set binary point
+}
+
+/** \brief Read the current group priority and subpriority split point from CPU's BPR register.
+* \return GICInterface_Type::BPR
+*/
+__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
+{
+  return GICInterface->BPR;
+}
+
+/** \brief Get the status for a given interrupt.
+* \param [in] IRQn The interrupt to get status for.
+* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
+*/
+__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
+{
+  uint32_t pending, active;
+
+  active = ((GICDistributor->ISACTIVER[IRQn / 32U])  >> (IRQn % 32U)) & 1UL;
+  pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
+
+  return ((active<<1U) | pending);
+}
+
+/** \brief Generate a software interrupt using GIC's SGIR register.
+* \param [in] IRQn Software interrupt to be generated.
+* \param [in] target_list List of CPUs the software interrupt should be forwarded to.
+* \param [in] filter_list Filter to be applied to determine interrupt receivers.
+*/
+__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+{
+  GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
+}
+
+/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
+* \return GICInterface_Type::HPPIR
+*/
+__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) 
+{ 
+  return GICInterface->HPPIR; 
+}
+
+/** \brief Provides information about the implementer and revision of the CPU interface.
+* \return GICInterface_Type::IIDR
+*/
+__STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
+{ 
+  return GICInterface->IIDR; 
+}
+
+/** \brief Set the interrupt group from the GIC's IGROUPR register.
+* \param [in] IRQn The interrupt to be queried.
+* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
+*/
+__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
+{
+  uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
+  uint32_t shift   = (IRQn % 32U);
+
+  igroupr &= (~(1U          << shift));
+  igroupr |= ( (group & 1U) << shift);
+
+  GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
+}
+#define GIC_SetSecurity         GIC_SetGroup
+
+/** \brief Get the interrupt group from the GIC's IGROUPR register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - Group 0, 1 - Group 1
+*/
+__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
+{
+  return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+}
+#define GIC_GetSecurity         GIC_GetGroup
+
+/** \brief Initialize the interrupt distributor.
+*/
+__STATIC_INLINE void GIC_DistInit(void)
+{
+  uint32_t i;
+  uint32_t num_irq = 0U;
+  uint32_t priority_field;
+
+  //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
+  //configuring all of the interrupts as Secure.
+
+  //Disable interrupt forwarding
+  GIC_DisableDistributor();
+  //Get the maximum number of interrupts that the GIC supports
+  num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
+
+  /* Priority level is implementation defined.
+   To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
+   priority field and read back the value stored.*/
+  GIC_SetPriority((IRQn_Type)0U, 0xFFU);
+  priority_field = GIC_GetPriority((IRQn_Type)0U);
+
+  for (i = 32U; i < num_irq; i++)
+  {
+      //Disable the SPI interrupt
+      GIC_DisableIRQ((IRQn_Type)i);
+      //Set level-sensitive (and N-N model)
+      GIC_SetConfiguration((IRQn_Type)i, 0U);
+      //Set priority
+      GIC_SetPriority((IRQn_Type)i, priority_field/2U);
+      //Set target list to CPU0
+      GIC_SetTarget((IRQn_Type)i, 1U);
+  }
+  //Enable distributor
+  GIC_EnableDistributor();
+}
+
+/** \brief Initialize the CPU's interrupt interface
+*/
+__STATIC_INLINE void GIC_CPUInterfaceInit(void)
+{
+  uint32_t i;
+  uint32_t priority_field;
+
+  //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
+  //configuring all of the interrupts as Secure.
+
+  //Disable interrupt forwarding
+  GIC_DisableInterface();
+
+  /* Priority level is implementation defined.
+   To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
+   priority field and read back the value stored.*/
+  GIC_SetPriority((IRQn_Type)0U, 0xFFU);
+  priority_field = GIC_GetPriority((IRQn_Type)0U);
+
+  //SGI and PPI
+  for (i = 0U; i < 32U; i++)
+  {
+    if(i > 15U) {
+      //Set level-sensitive (and N-N model) for PPI
+      GIC_SetConfiguration((IRQn_Type)i, 0U);
+    }
+    //Disable SGI and PPI interrupts
+    GIC_DisableIRQ((IRQn_Type)i);
+    //Set priority
+    GIC_SetPriority((IRQn_Type)i, priority_field/2U);
+  }
+  //Enable interface
+  GIC_EnableInterface();
+  //Set binary point to 0
+  GIC_SetBinaryPoint(0U);
+  //Set priority mask
+  GIC_SetInterfacePriorityMask(0xFFU);
+}
+
+/** \brief Initialize and enable the GIC
+*/
+__STATIC_INLINE void GIC_Enable(void)
+{
+  GIC_DistInit();
+  GIC_CPUInterfaceInit(); //per CPU
+}
+#endif
+
+/* ##########################  Generic Timer functions  ############################ */
+#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+  
+/* PL1 Physical Timer */
+#if (__CORTEX_A == 7U) || defined(DOXYGEN)
+  
+/** \brief Physical Timer Control register */
+typedef union
+{
+  struct
+  {
+    uint32_t ENABLE:1;      /*!< \brief bit: 0      Enables the timer. */
+    uint32_t IMASK:1;       /*!< \brief bit: 1      Timer output signal mask bit. */
+    uint32_t ISTATUS:1;     /*!< \brief bit: 2      The status of the timer. */
+    RESERVED(0:29, uint32_t)
+  } b;                      /*!< \brief Structure used for bit  access */
+  uint32_t w;               /*!< \brief Type      used for word access */
+} CNTP_CTL_Type;
+
+/** \brief Configures the frequency the timer shall run at.
+* \param [in] value The timer frequency in Hz.
+*/
+__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
+{
+  __set_CNTFRQ(value);
+  __ISB();
+}
+
+/** \brief Sets the reset value of the timer.
+* \param [in] value The value the timer is loaded with.
+*/
+__STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
+{
+  __set_CNTP_TVAL(value);
+  __ISB();
+}
+
+/** \brief Get the current counter value.
+* \return Current counter value.
+*/
+__STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
+{
+  return(__get_CNTP_TVAL());
+}
+
+/** \brief Get the current physical counter value.
+* \return Current physical counter value.
+*/
+__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
+{
+  return(__get_CNTPCT());
+}
+
+/** \brief Set the physical compare value.
+* \param [in] value New physical timer compare value.
+*/
+__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
+{
+  __set_CNTP_CVAL(value);
+  __ISB();
+}
+
+/** \brief Get the physical compare value.
+* \return Physical compare value.
+*/
+__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
+{
+  return(__get_CNTP_CVAL());
+}
+
+/** \brief Configure the timer by setting the control value.
+* \param [in] value New timer control value.
+*/
+__STATIC_INLINE void PL1_SetControl(uint32_t value)
+{
+  __set_CNTP_CTL(value);
+  __ISB();
+}
+
+/** \brief Get the control value.
+* \return Control value.
+*/
+__STATIC_INLINE uint32_t PL1_GetControl(void)
+{
+  return(__get_CNTP_CTL());
+}
+#endif
+
+/* Private Timer */
+#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
+/** \brief Set the load value to timers LOAD register.
+* \param [in] value The load value to be set.
+*/
+__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
+{
+  PTIM->LOAD = value;
+}
+
+/** \brief Get the load value from timers LOAD register.
+* \return Timer_Type::LOAD
+*/
+__STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
+{
+  return(PTIM->LOAD);
+}
+
+/** \brief Set current counter value from its COUNTER register.
+*/
+__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
+{
+  PTIM->COUNTER = value;
+}
+
+/** \brief Get current counter value from timers COUNTER register.
+* \result Timer_Type::COUNTER
+*/
+__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
+{
+  return(PTIM->COUNTER);
+}
+
+/** \brief Configure the timer using its CONTROL register.
+* \param [in] value The new configuration value to be set.
+*/
+__STATIC_INLINE void PTIM_SetControl(uint32_t value)
+{
+  PTIM->CONTROL = value;
+}
+
+/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
+* \return Timer_Type::CONTROL
+*/
+__STATIC_INLINE uint32_t PTIM_GetControl(void)
+{
+  return(PTIM->CONTROL);
+}
+
+/** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
+* \return 0 - flag is not set, 1- flag is set
+*/
+__STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
+{
+  return (PTIM->ISR & 1UL);
+}
+
+/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
+*/
+__STATIC_INLINE void PTIM_ClearEventFlag(void)
+{
+  PTIM->ISR = 1;
+}
+#endif
+#endif
+
+/* ##########################  MMU functions  ###################################### */
+
+#define SECTION_DESCRIPTOR      (0x2)
+#define SECTION_MASK            (0xFFFFFFFC)
+
+#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
+#define SECTION_B_SHIFT         (2)
+#define SECTION_C_SHIFT         (3)
+#define SECTION_TEX0_SHIFT      (12)
+#define SECTION_TEX1_SHIFT      (13)
+#define SECTION_TEX2_SHIFT      (14)
+
+#define SECTION_XN_MASK         (0xFFFFFFEF)
+#define SECTION_XN_SHIFT        (4)
+
+#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
+#define SECTION_DOMAIN_SHIFT    (5)
+
+#define SECTION_P_MASK          (0xFFFFFDFF)
+#define SECTION_P_SHIFT         (9)
+
+#define SECTION_AP_MASK         (0xFFFF73FF)
+#define SECTION_AP_SHIFT        (10)
+#define SECTION_AP2_SHIFT       (15)
+
+#define SECTION_S_MASK          (0xFFFEFFFF)
+#define SECTION_S_SHIFT         (16)
+
+#define SECTION_NG_MASK         (0xFFFDFFFF)
+#define SECTION_NG_SHIFT        (17)
+
+#define SECTION_NS_MASK         (0xFFF7FFFF)
+#define SECTION_NS_SHIFT        (19)
+
+#define PAGE_L1_DESCRIPTOR      (0x1)
+#define PAGE_L1_MASK            (0xFFFFFFFC)
+
+#define PAGE_L2_4K_DESC         (0x2)
+#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
+
+#define PAGE_L2_64K_DESC        (0x1)
+#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
+
+#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
+#define PAGE_4K_B_SHIFT         (2)
+#define PAGE_4K_C_SHIFT         (3)
+#define PAGE_4K_TEX0_SHIFT      (6)
+#define PAGE_4K_TEX1_SHIFT      (7)
+#define PAGE_4K_TEX2_SHIFT      (8)
+
+#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
+#define PAGE_64K_B_SHIFT        (2)
+#define PAGE_64K_C_SHIFT        (3)
+#define PAGE_64K_TEX0_SHIFT     (12)
+#define PAGE_64K_TEX1_SHIFT     (13)
+#define PAGE_64K_TEX2_SHIFT     (14)
+
+#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
+#define PAGE_B_SHIFT            (2)
+#define PAGE_C_SHIFT            (3)
+#define PAGE_TEX_SHIFT          (12)
+
+#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
+#define PAGE_XN_4K_SHIFT        (0)
+#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
+#define PAGE_XN_64K_SHIFT       (15)
+
+#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
+#define PAGE_DOMAIN_SHIFT       (5)
+
+#define PAGE_P_MASK             (0xFFFFFDFF)
+#define PAGE_P_SHIFT            (9)
+
+#define PAGE_AP_MASK            (0xFFFFFDCF)
+#define PAGE_AP_SHIFT           (4)
+#define PAGE_AP2_SHIFT          (9)
+
+#define PAGE_S_MASK             (0xFFFFFBFF)
+#define PAGE_S_SHIFT            (10)
+
+#define PAGE_NG_MASK            (0xFFFFF7FF)
+#define PAGE_NG_SHIFT           (11)
+
+#define PAGE_NS_MASK            (0xFFFFFFF7)
+#define PAGE_NS_SHIFT           (3)
+
+#define OFFSET_1M               (0x00100000)
+#define OFFSET_64K              (0x00010000)
+#define OFFSET_4K               (0x00001000)
+
+#define DESCRIPTOR_FAULT        (0x00000000)
+
+/* Attributes enumerations */
+
+/* Region size attributes */
+typedef enum
+{
+   SECTION,
+   PAGE_4k,
+   PAGE_64k,
+} mmu_region_size_Type;
+
+/* Region type attributes */
+typedef enum
+{
+   NORMAL,
+   DEVICE,
+   SHARED_DEVICE,
+   NON_SHARED_DEVICE,
+   STRONGLY_ORDERED
+} mmu_memory_Type;
+
+/* Region cacheability attributes */
+typedef enum
+{
+   NON_CACHEABLE,
+   WB_WA,
+   WT,
+   WB_NO_WA,
+} mmu_cacheability_Type;
+
+/* Region parity check attributes */
+typedef enum
+{
+   ECC_DISABLED,
+   ECC_ENABLED,
+} mmu_ecc_check_Type;
+
+/* Region execution attributes */
+typedef enum
+{
+   EXECUTE,
+   NON_EXECUTE,
+} mmu_execute_Type;
+
+/* Region global attributes */
+typedef enum
+{
+   GLOBAL,
+   NON_GLOBAL,
+} mmu_global_Type;
+
+/* Region shareability attributes */
+typedef enum
+{
+   NON_SHARED,
+   SHARED,
+} mmu_shared_Type;
+
+/* Region security attributes */
+typedef enum
+{
+   SECURE,
+   NON_SECURE,
+} mmu_secure_Type;
+
+/* Region access attributes */
+typedef enum
+{
+   NO_ACCESS,
+   RW,
+   READ,
+} mmu_access_Type;
+
+/* Memory Region definition */
+typedef struct RegionStruct {
+    mmu_region_size_Type rg_t;
+    mmu_memory_Type mem_t;
+    uint8_t domain;
+    mmu_cacheability_Type inner_norm_t;
+    mmu_cacheability_Type outer_norm_t;
+    mmu_ecc_check_Type e_t;
+    mmu_execute_Type xn_t;
+    mmu_global_Type g_t;
+    mmu_secure_Type sec_t;
+    mmu_access_Type priv_t;
+    mmu_access_Type user_t;
+    mmu_shared_Type sh_t;
+
+} mmu_region_attributes_Type;
+
+//Following macros define the descriptors and attributes
+//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
+#define section_normal(descriptor_l1, region)     region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
+#define section_normal_nc(descriptor_l1, region)     region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
+#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RO. Sect_Normal_Cod, but not executable
+#define section_normal_ro(descriptor_l1, region)  region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
+#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
+#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RW. Sect_Device_RO, but writeable
+#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Page_4k_Device_RW.  Shared device, not executable, rw, domain 0
+#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = SHARED_DEVICE; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+//Page_64k_Device_RW.  Shared device, not executable, rw, domain 0
+#define page64k_device_rw(descriptor_l1, descriptor_l2, region)  region.rg_t = PAGE_64k; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = SHARED_DEVICE; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+/** \brief  Set section execution-never attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
+{
+  *descriptor_l1 &= SECTION_XN_MASK;
+  *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section domain
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]            domain  Section domain
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
+{
+  *descriptor_l1 &= SECTION_DOMAIN_MASK;
+  *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section parity check
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+  *descriptor_l1 &= SECTION_P_MASK;
+  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section access privileges
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+  \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+  \param [in]               afe  Access flag enable
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+  uint32_t ap = 0;
+
+  if (afe == 0) { //full access
+    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+    else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  else { //Simplified access
+    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  *descriptor_l1 &= SECTION_AP_MASK;
+  *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
+  *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
+
+  return 0;
+}
+
+/** \brief  Set section shareability
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
+{
+  *descriptor_l1 &= SECTION_S_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section Global attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
+{
+  *descriptor_l1 &= SECTION_NG_MASK;
+  *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section Security attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+  *descriptor_l1 &= SECTION_NS_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
+  return 0;
+}
+
+/* Page 4k or 64k */
+/** \brief  Set 4k/64k page execution-never attribute
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
+  \param [in]              page  Page size: PAGE_4k, PAGE_64k,
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
+{
+  if (page == PAGE_4k)
+  {
+      *descriptor_l2 &= PAGE_XN_4K_MASK;
+      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
+  }
+  else
+  {
+      *descriptor_l2 &= PAGE_XN_64K_MASK;
+      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
+  }
+  return 0;
+}
+
+/** \brief  Set 4k/64k page domain
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]            domain  Page domain
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
+{
+  *descriptor_l1 &= PAGE_DOMAIN_MASK;
+  *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page parity check
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+  *descriptor_l1 &= SECTION_P_MASK;
+  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page access privileges
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+  \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+  \param [in]               afe  Access flag enable
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+  uint32_t ap = 0;
+
+  if (afe == 0) { //full access
+    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+    else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x6; }
+  }
+
+  else { //Simplified access
+    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  *descriptor_l2 &= PAGE_AP_MASK;
+  *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
+  *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
+
+  return 0;
+}
+
+/** \brief  Set 4k/64k page shareability
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
+{
+  *descriptor_l2 &= PAGE_S_MASK;
+  *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page Global attribute
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
+{
+  *descriptor_l2 &= PAGE_NG_MASK;
+  *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page Security attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+  *descriptor_l1 &= PAGE_NS_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
+  return 0;
+}
+
+/** \brief  Set Section memory attributes
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+  \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
+{
+  *descriptor_l1 &= SECTION_TEXCB_MASK;
+
+  if (STRONGLY_ORDERED == mem)
+  {
+    return 0;
+  }
+  else if (SHARED_DEVICE == mem)
+  {
+    *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+  }
+  else if (NON_SHARED_DEVICE == mem)
+  {
+    *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
+  }
+  else if (NORMAL == mem)
+  {
+   *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
+   switch(inner)
+   {
+      case NON_CACHEABLE:
+        break;
+      case WB_WA:
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+        break;
+      case WT:
+        *descriptor_l1 |= 1 << SECTION_C_SHIFT;
+        break;
+      case WB_NO_WA:
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
+        break;
+    }
+    switch(outer)
+    {
+      case NON_CACHEABLE:
+        break;
+      case WB_WA:
+        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
+        break;
+      case WT:
+        *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
+        break;
+      case WB_NO_WA:
+        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
+        break;
+    }
+  }
+  return 0;
+}
+
+/** \brief  Set 4k/64k page memory attributes
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+  \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]              page  Page size
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
+{
+  *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
+
+  if (page == PAGE_64k)
+  {
+    //same as section
+    MMU_MemorySection(descriptor_l2, mem, outer, inner);
+  }
+  else
+  {
+    if (STRONGLY_ORDERED == mem)
+    {
+      return 0;
+    }
+    else if (SHARED_DEVICE == mem)
+    {
+      *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+    }
+    else if (NON_SHARED_DEVICE == mem)
+    {
+      *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
+    }
+    else if (NORMAL == mem)
+    {
+      *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
+      switch(inner)
+      {
+        case NON_CACHEABLE:
+          break;
+        case WB_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+          break;
+        case WT:
+          *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
+          break;
+        case WB_NO_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
+          break;
+      }
+      switch(outer)
+      {
+        case NON_CACHEABLE:
+          break;
+        case WB_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
+          break;
+        case WT:
+          *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
+          break;
+        case WB_NO_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
+          break;
+      }
+    }
+  }
+
+  return 0;
+}
+
+/** \brief  Create a L1 section descriptor
+
+  \param [out]     descriptor  L1 descriptor
+  \param [in]      reg  Section attributes
+  
+  \return          0
+*/
+__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
+{
+  *descriptor  = 0;
+
+  MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
+  MMU_XNSection(descriptor,reg.xn_t);
+  MMU_DomainSection(descriptor, reg.domain);
+  MMU_PSection(descriptor, reg.e_t);
+  MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
+  MMU_SharedSection(descriptor,reg.sh_t);
+  MMU_GlobalSection(descriptor,reg.g_t);
+  MMU_SecureSection(descriptor,reg.sec_t);
+  *descriptor &= SECTION_MASK;
+  *descriptor |= SECTION_DESCRIPTOR;
+ 
+  return 0;
+}
+
+
+/** \brief  Create a L1 and L2 4k/64k page descriptor
+
+  \param [out]       descriptor  L1 descriptor
+  \param [out]      descriptor2  L2 descriptor
+  \param [in]               reg  4k/64k page attributes
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
+{
+  *descriptor  = 0;
+  *descriptor2 = 0;
+
+  switch (reg.rg_t)
+  {
+    case PAGE_4k:
+      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
+      MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
+      MMU_DomainPage(descriptor, reg.domain);
+      MMU_PPage(descriptor, reg.e_t);
+      MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+      MMU_SharedPage(descriptor2,reg.sh_t);
+      MMU_GlobalPage(descriptor2,reg.g_t);
+      MMU_SecurePage(descriptor,reg.sec_t);
+      *descriptor &= PAGE_L1_MASK;
+      *descriptor |= PAGE_L1_DESCRIPTOR;
+      *descriptor2 &= PAGE_L2_4K_MASK;
+      *descriptor2 |= PAGE_L2_4K_DESC;
+      break;
+
+    case PAGE_64k:
+      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
+      MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
+      MMU_DomainPage(descriptor, reg.domain);
+      MMU_PPage(descriptor, reg.e_t);
+      MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+      MMU_SharedPage(descriptor2,reg.sh_t);
+      MMU_GlobalPage(descriptor2,reg.g_t);
+      MMU_SecurePage(descriptor,reg.sec_t);
+      *descriptor &= PAGE_L1_MASK;
+      *descriptor |= PAGE_L1_DESCRIPTOR;
+      *descriptor2 &= PAGE_L2_64K_MASK;
+      *descriptor2 |= PAGE_L2_64K_DESC;
+      break;
+
+    case SECTION:
+      //error
+      break;
+  }
+  
+  return 0;
+}
+
+/** \brief  Create a 1MB Section
+
+  \param [in]               ttb  Translation table base address
+  \param [in]      base_address  Section base address
+  \param [in]             count  Number of sections to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
+{
+  uint32_t offset;
+  uint32_t entry;
+  uint32_t i;
+
+  offset = base_address >> 20;
+  entry  = (base_address & 0xFFF00000) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb = ttb + offset;
+
+  for (i = 0; i < count; i++ )
+  {
+    //4 bytes aligned
+    *ttb++ = entry;
+    entry += OFFSET_1M;
+  }
+}
+
+/** \brief  Create a 4k page entry
+
+  \param [in]               ttb  L1 table base address
+  \param [in]      base_address  4k base address
+  \param [in]             count  Number of 4k pages to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+  \param [in]            ttb_l2  L2 table base address
+  \param [in]     descriptor_l2  L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+
+  uint32_t offset, offset2;
+  uint32_t entry, entry2;
+  uint32_t i;
+
+  offset = base_address >> 20;
+  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb += offset;
+  //create l1_entry
+  *ttb = entry;
+
+  offset2 = (base_address & 0xff000) >> 12;
+  ttb_l2 += offset2;
+  entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
+  for (i = 0; i < count; i++ )
+  {
+    //4 bytes aligned
+    *ttb_l2++ = entry2;
+    entry2 += OFFSET_4K;
+  }
+}
+
+/** \brief  Create a 64k page entry
+
+  \param [in]               ttb  L1 table base address
+  \param [in]      base_address  64k base address
+  \param [in]             count  Number of 64k pages to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+  \param [in]            ttb_l2  L2 table base address
+  \param [in]     descriptor_l2  L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+  uint32_t offset, offset2;
+  uint32_t entry, entry2;
+  uint32_t i,j;
+
+
+  offset = base_address >> 20;
+  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb += offset;
+  //create l1_entry
+  *ttb = entry;
+
+  offset2 = (base_address & 0xff000) >> 12;
+  ttb_l2 += offset2;
+  entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
+  for (i = 0; i < count; i++ )
+  {
+    //create 16 entries
+    for (j = 0; j < 16; j++)
+    {
+      //4 bytes aligned
+      *ttb_l2++ = entry2;
+    }
+    entry2 += OFFSET_64K;
+  }
+}
+
+/** \brief  Enable MMU
+*/
+__STATIC_INLINE void MMU_Enable(void)
+{
+  // Set M bit 0 to enable the MMU
+  // Set AFE bit to enable simplified access permissions model
+  // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+  __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+  __ISB();
+}
+
+/** \brief  Disable MMU
+*/
+__STATIC_INLINE void MMU_Disable(void)
+{
+  // Clear M bit 0 to disable the MMU
+  __set_SCTLR( __get_SCTLR() & ~1);
+  __ISB();
+}
+
+/** \brief  Invalidate entire unified TLB
+*/
+
+__STATIC_INLINE void MMU_InvalidateTLB(void)
+{
+  __set_TLBIALL(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- a/cmsis/TARGET_CORTEX_A/core_ca9.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,276 +0,0 @@
-/**************************************************************************//**
- * @file     core_ca9.h
- * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date     25 March 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CA9_H_GENERIC
-#define __CORE_CA9_H_GENERIC
-
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_A9
-  @{
- */
-
-/*  CMSIS CA9 definitions */
-#define __CA9_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CA9_CMSIS_VERSION_SUB   (0x10)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CA9_CMSIS_VERSION       ((__CA9_CMSIS_VERSION_MAIN << 16) | \
-                                    __CA9_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_A                (0x09)                                   /*!< Cortex-A Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-  #define __STATIC_ASM     static __asm
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#include <stdint.h>
-inline uint32_t __get_PSR(void) {
-	__ASM("mrs r0, cpsr");
-}
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_caInstr.h"                /*!< Core Instruction Access                         */
-#include "core_caFunc.h"                 /*!< Core Function Access                            */
-#include "core_cm4_simd.h"               /*!< Compiler specific SIMD Intrinsics               */
-
-#endif /* __CORE_CA9_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CA9_H_DEPENDANT
-#define __CORE_CA9_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CA9_REV
-    #define __CA9_REV               0x0000
-    #warning "__CA9_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             1
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    1
-  #endif
-
-  #if __Vendor_SysTickConfig == 0
-    #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_A9 */
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-A processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t reserved1:7;                /*!< bit: 20..23  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */ 
-} APSR_Type;
-
-
-/*@} end of group CMSIS_CORE */
-
-/*@} end of CMSIS_Core_FPUFunctions */
-
-
-#endif /* __CORE_CA9_H_GENERIC */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-
-
-#endif

--- a/cmsis/TARGET_CORTEX_A/core_caFunc.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1444 +0,0 @@
-/**************************************************************************//**
- * @file     core_caFunc.h
- * @brief    CMSIS Cortex-A Core Function Access Header File
- * @version  V3.10
- * @date     30 Oct 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CAFUNC_H__
-#define __CORE_CAFUNC_H__
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get CPSR Register
-
-    This function returns the content of the CPSR Register.
-
-    \return               CPSR Register value
- */
-__STATIC_INLINE uint32_t __get_CPSR(void)
-{
-  register uint32_t __regCPSR          __ASM("cpsr");
-  return(__regCPSR);
-}
-
-/** \brief  Set Stack Pointer
-
-    This function assigns the given value to the current stack pointer.
-
-    \param [in]    topOfStack  Stack Pointer value to set
- */
-register uint32_t __regSP              __ASM("sp");
-__STATIC_INLINE void __set_SP(uint32_t topOfStack)
-{
-    __regSP = topOfStack;
-}
-
-
-/** \brief  Get link register
-
-    This function returns the value of the link register
-
-    \return    Value of link register
- */
-register uint32_t __reglr         __ASM("lr");
-__STATIC_INLINE uint32_t __get_LR(void)
-{
-  return(__reglr);
-}
-
-/** \brief  Set link register
-
-    This function sets the value of the link register
-
-    \param [in]    lr  LR value to set
- */
-__STATIC_INLINE void __set_LR(uint32_t lr)
-{
-  __reglr = lr;
-}
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-__STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
-{
-    ARM
-    PRESERVE8
-
-    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned
-    MRS     R1, CPSR
-    CPS     #MODE_SYS   ;no effect in USR mode
-    MOV     SP, R0
-    MSR     CPSR_c, R1  ;no effect in USR mode
-    ISB
-    BX      LR
-
-}
-
-/** \brief  Set User Mode
-
-    This function changes the processor state to User Mode
- */
-__STATIC_ASM void __set_CPS_USR(void)
-{
-    ARM 
-
-    CPS  #MODE_USR  
-    BX   LR
-}
-
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-/** \brief  Get FPEXC
-
-    This function returns the current value of the Floating Point Exception Control register.
-
-    \return               Floating Point Exception Control register value
- */
-__STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpexc         __ASM("fpexc");
-  return(__regfpexc);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPEXC
-
-    This function assigns the given value to the Floating Point Exception Control register.
-
-    \param [in]    fpscr  Floating Point Exception Control value to set
- */
-__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpexc         __ASM("fpexc");
-  __regfpexc = (fpexc);
-#endif
-}
-
-/** \brief  Get CPACR
-
-    This function returns the current value of the Coprocessor Access Control register.
-
-    \return               Coprocessor Access Control register value
- */
-__STATIC_INLINE uint32_t __get_CPACR(void)
-{
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-    return __regCPACR;
-}
-
-/** \brief  Set CPACR
-
-    This function assigns the given value to the Coprocessor Access Control register.
-
-    \param [in]    cpacr  Coprocessor Acccess Control value to set
- */
-__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-    __regCPACR = cpacr;
-    __ISB();
-}
-
-/** \brief  Get CBAR
-
-    This function returns the value of the Configuration Base Address register.
-
-    \return               Configuration Base Address register value
- */
-__STATIC_INLINE uint32_t __get_CBAR() {
-    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
-    return(__regCBAR);
-}
-
-/** \brief  Get TTBR0
-
-    This function returns the value of the Translation Table Base Register 0.
-
-    \return               Translation Table Base Register 0 value
- */
-__STATIC_INLINE uint32_t __get_TTBR0() {
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-    return(__regTTBR0);
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-    __regTTBR0 = ttbr0;
-    __ISB();
-}
-
-/** \brief  Get DACR
-
-    This function returns the value of the Domain Access Control Register.
-
-    \return               Domain Access Control Register value
- */
-__STATIC_INLINE uint32_t __get_DACR() {
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-    return(__regDACR);
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-    __regDACR = dacr;
-    __ISB();
-}
-
-/******************************** Cache and BTAC enable  ****************************************************/
-
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-    __regSCTLR = sctlr;
-}
-
-/** \brief  Get SCTLR
-
-    This function returns the value of the System Control Register.
-
-    \return               System Control Register value
- */
-__STATIC_INLINE uint32_t __get_SCTLR() {
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-    return(__regSCTLR);
-}
-
-/** \brief  Enable Caches
-
-    Enable Caches
- */
-__STATIC_INLINE void __enable_caches(void) {
-    // Set I bit 12 to enable I Cache
-    // Set C bit  2 to enable D Cache
-    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief  Disable Caches
-
-    Disable Caches
- */
-__STATIC_INLINE void __disable_caches(void) {
-    // Clear I bit 12 to disable I Cache
-    // Clear C bit  2 to disable D Cache
-    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
-    __ISB();
-}
-
-/** \brief  Enable BTAC
-
-    Enable BTAC
- */
-__STATIC_INLINE void __enable_btac(void) {
-    // Set Z bit 11 to enable branch prediction
-    __set_SCTLR( __get_SCTLR() | (1 << 11));
-    __ISB();
-}
-
-/** \brief  Disable BTAC
-
-    Disable BTAC
- */
-__STATIC_INLINE void __disable_btac(void) {
-    // Clear Z bit 11 to disable branch prediction
-    __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-
-/** \brief  Enable MMU
-
-    Enable MMU
- */
-__STATIC_INLINE void __enable_mmu(void) {
-    // Set M bit 0 to enable the MMU
-    // Set AFE bit to enable simplified access permissions model
-    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
-    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
-    __ISB();
-}
-
-/** \brief  Disable MMU
-
-    Disable MMU
- */
-__STATIC_INLINE void __disable_mmu(void) {
-    // Clear M bit 0 to disable the MMU
-    __set_SCTLR( __get_SCTLR() & ~1);
-    __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief  Invalidate the whole tlb
-
-    TLBIALL. Invalidate the whole tlb
- */
-
-__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");
-    __TLBIALL = 0;
-    __DSB();
-    __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief  Invalidate entire branch predictor array
-
-    BPIALL. Branch Predictor Invalidate All.
- */
-
-__STATIC_INLINE void __v7_inv_btac(void) {
-    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");
-    __BPIALL  = 0;
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief  Invalidate the whole I$
-
-    ICIALLU. Instruction Cache Invalidate All to PoU
- */
-__STATIC_INLINE void __v7_inv_icache_all(void) {
-    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
-    __ICIALLU = 0;
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief  Clean D$ by MVA
-
-    DCCMVAC. Data cache clean by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
-    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
-    __DCCMVAC = (uint32_t)va;
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Invalidate D$ by MVA
-
-    DCIMVAC. Data cache invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
-    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
-    __DCIMVAC = (uint32_t)va;
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate D$ by MVA
-
-    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
-    __DCCIMVAC = (uint32_t)va;
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate the entire data or unified cache
-
-    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
-#pragma push
-#pragma arm
-__STATIC_ASM void __v7_all_cache(uint32_t op) {
-        ARM 
-
-        PUSH    {R4-R11}
-
-        MRC     p15, 1, R6, c0, c0, 1      // Read CLIDR
-        ANDS    R3, R6, #0x07000000        // Extract coherency level
-        MOV     R3, R3, LSR #23            // Total cache levels << 1
-        BEQ     Finished                   // If 0, no need to clean
-
-        MOV     R10, #0                    // R10 holds current cache level << 1
-Loop1   ADD     R2, R10, R10, LSR #1       // R2 holds cache "Set" position
-        MOV     R1, R6, LSR R2             // Bottom 3 bits are the Cache-type for this level
-        AND     R1, R1, #7                 // Isolate those lower 3 bits
-        CMP     R1, #2
-        BLT     Skip                       // No cache or only instruction cache at this level
-
-        MCR     p15, 2, R10, c0, c0, 0     // Write the Cache Size selection register
-        ISB                                // ISB to sync the change to the CacheSizeID reg
-        MRC     p15, 1, R1, c0, c0, 0      // Reads current Cache Size ID register
-        AND     R2, R1, #7                 // Extract the line length field
-        ADD     R2, R2, #4                 // Add 4 for the line length offset (log2 16 bytes)
-        LDR     R4, =0x3FF
-        ANDS    R4, R4, R1, LSR #3         // R4 is the max number on the way size (right aligned)
-        CLZ     R5, R4                     // R5 is the bit position of the way size increment
-        LDR     R7, =0x7FFF
-        ANDS    R7, R7, R1, LSR #13        // R7 is the max number of the index size (right aligned)
-
-Loop2   MOV     R9, R4                     // R9 working copy of the max way size (right aligned)
-
-Loop3   ORR     R11, R10, R9, LSL R5       // Factor in the Way number and cache number into R11
-        ORR     R11, R11, R7, LSL R2       // Factor in the Set number
-        CMP     R0, #0
-        BNE     Dccsw
-        MCR     p15, 0, R11, c7, c6, 2     // DCISW. Invalidate by Set/Way
-        B       cont
-Dccsw   CMP     R0, #1
-        BNE     Dccisw
-        MCR     p15, 0, R11, c7, c10, 2    // DCCSW. Clean by Set/Way
-        B       cont
-Dccisw  MCR     p15, 0, R11, c7, c14, 2    // DCCISW. Clean and Invalidate by Set/Way
-cont    SUBS    R9, R9, #1                 // Decrement the Way number
-        BGE     Loop3
-        SUBS    R7, R7, #1                 // Decrement the Set number
-        BGE     Loop2
-Skip    ADD     R10, R10, #2               // Increment the cache number
-        CMP     R3, R10
-        BGT     Loop1
-
-Finished
-        DSB
-        POP    {R4-R11}
-        BX     lr
-
-}
-#pragma pop
-
-
-/** \brief  Invalidate the whole D$
-
-    DCISW. Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_inv_dcache_all(void) {
-    __v7_all_cache(0);
-}
-
-/** \brief  Clean the whole D$
-
-    DCCSW. Clean by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_dcache_all(void) {
-    __v7_all_cache(1);
-}
-
-/** \brief  Clean and invalidate the whole D$
-
-    DCCISW. Clean and Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
-    __v7_all_cache(2);
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-
-#define __inline inline
-
-inline static uint32_t __disable_irq_iar() {
-  int irq_dis = __get_CPSR() & 0x80;      // 7bit CPSR.I
-  __disable_irq();
-  return irq_dis;
-}
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-// from rt_CMSIS.c
-__arm static inline void __set_PSP(uint32_t topOfProcStack) {
-__asm(
-  "    ARM\n"
-//  "    PRESERVE8\n"
-
-  "    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned \n"
-  "    MRS     R1, CPSR \n"
-  "    CPS     #0x1F   ;no effect in USR mode \n"        // MODE_SYS
-  "    MOV     SP, R0 \n"
-  "    MSR     CPSR_c, R1  ;no effect in USR mode \n"
-  "    ISB \n"
-  "    BX      LR \n");
-}
-
-/** \brief  Set User Mode
-
-    This function changes the processor state to User Mode
- */
-// from rt_CMSIS.c
-__arm static inline void __set_CPS_USR(void) {
-__asm(
-  "    ARM \n"
-
-  "    CPS  #0x10  \n"                  // MODE_USR
-  "    BX   LR\n");
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-// from mmu_Renesas_RZ_A1.c
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-    __MCR(15, 0, ttbr0, 2, 0, 0);      // reg to cp15
-    __ISB();
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-// from mmu_Renesas_RZ_A1.c
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
-    __MCR(15, 0, dacr, 3, 0, 0);      // reg to cp15
-    __ISB();
-}
-
-
-/******************************** Cache and BTAC enable  ****************************************************/
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-// from __enable_mmu()
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
-    __MCR(15, 0, sctlr, 1, 0, 0);      // reg to cp15
-}
-
-/** \brief  Get SCTLR
-
-    This function returns the value of the System Control Register.
-
-    \return               System Control Register value
- */
-// from __enable_mmu()
-__STATIC_INLINE uint32_t __get_SCTLR() {
-	uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
-	return __regSCTLR;
-}
-
-/** \brief  Enable Caches
-
-    Enable Caches
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_caches(void) {
-    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief  Enable BTAC
-
-    Enable BTAC
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_btac(void) {
-    __set_SCTLR( __get_SCTLR() | (1 << 11));
-    __ISB();
-}
-
-/** \brief  Enable MMU
-
-    Enable MMU
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_mmu(void) {
-    // Set M bit 0 to enable the MMU
-    // Set AFE bit to enable simplified access permissions model
-    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
-    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
-    __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief  Invalidate the whole tlb
-
-    TLBIALL. Invalidate the whole tlb
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-	uint32_t val = 0;
-    __MCR(15, 0, val, 8, 7, 0);      // reg to cp15
-    __MCR(15, 0, val, 8, 6, 0);      // reg to cp15
-    __MCR(15, 0, val, 8, 5, 0);      // reg to cp15
-    __DSB();
-    __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief  Invalidate entire branch predictor array
-
-    BPIALL. Branch Predictor Invalidate All.
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_btac(void) {
-	uint32_t val = 0;
-    __MCR(15, 0, val, 7, 5, 6);      // reg to cp15
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief  Invalidate the whole I$
-
-    ICIALLU. Instruction Cache Invalidate All to PoU
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_icache_all(void) {
-	uint32_t val = 0;
-    __MCR(15, 0, val, 7, 5, 0);      // reg to cp15
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new I cache state
-}
-
-// from __v7_inv_dcache_all()
-__arm static inline void __v7_all_cache(uint32_t op) {
-__asm(
-	"        ARM \n"
-
-	"        PUSH    {R4-R11} \n"
-
-	"        MRC     p15, 1, R6, c0, c0, 1\n"      // Read CLIDR
-	"        ANDS    R3, R6, #0x07000000\n"        // Extract coherency level
-	"        MOV     R3, R3, LSR #23\n"            // Total cache levels << 1
-	"        BEQ     Finished\n"                   // If 0, no need to clean
-
-	"        MOV     R10, #0\n"                    // R10 holds current cache level << 1
-    "Loop1:   ADD     R2, R10, R10, LSR #1\n"       // R2 holds cache "Set" position
-	"        MOV     R1, R6, LSR R2 \n"            // Bottom 3 bits are the Cache-type for this level
-	"        AND     R1, R1, #7 \n"                // Isolate those lower 3 bits
-	"        CMP     R1, #2 \n"
-	"        BLT     Skip \n"                      // No cache or only instruction cache at this level
-
-	"        MCR     p15, 2, R10, c0, c0, 0 \n"    // Write the Cache Size selection register
-	"        ISB \n"                               // ISB to sync the change to the CacheSizeID reg
-	"        MRC     p15, 1, R1, c0, c0, 0 \n"     // Reads current Cache Size ID register
-	"        AND     R2, R1, #7 \n"                // Extract the line length field
-	"        ADD     R2, R2, #4 \n"                // Add 4 for the line length offset (log2 16 bytes)
-	"        movw    R4, #0x3FF \n"
-	"        ANDS    R4, R4, R1, LSR #3 \n"        // R4 is the max number on the way size (right aligned)
-	"        CLZ     R5, R4 \n"                    // R5 is the bit position of the way size increment
-	"        movw    R7, #0x7FFF \n"
-	"        ANDS    R7, R7, R1, LSR #13 \n"       // R7 is the max number of the index size (right aligned)
-
-	"Loop2:   MOV     R9, R4 \n"                    // R9 working copy of the max way size (right aligned)
-
-	"Loop3:   ORR     R11, R10, R9, LSL R5 \n"      // Factor in the Way number and cache number into R11
-	"        ORR     R11, R11, R7, LSL R2 \n"      // Factor in the Set number
-	"        CMP     R0, #0 \n"
-	"        BNE     Dccsw \n"
-	"        MCR     p15, 0, R11, c7, c6, 2 \n"    // DCISW. Invalidate by Set/Way
-	"        B       cont \n"
-	"Dccsw:   CMP     R0, #1 \n"
-	"        BNE     Dccisw \n"
-	"        MCR     p15, 0, R11, c7, c10, 2 \n"   // DCCSW. Clean by Set/Way
-	"        B       cont \n"
-	"Dccisw:  MCR     p15, 0, R11, c7, c14, 2 \n"   // DCCISW, Clean and Invalidate by Set/Way
-	"cont:    SUBS    R9, R9, #1 \n"                // Decrement the Way number
-	"        BGE     Loop3 \n"
-	"        SUBS    R7, R7, #1 \n"                // Decrement the Set number
-	"        BGE     Loop2 \n"
-	"Skip:    ADD     R10, R10, #2 \n"              // increment the cache number
-	"        CMP     R3, R10 \n"
-	"        BGT     Loop1 \n"
-
-	"Finished: \n"
-	"        DSB \n"
-	"        POP    {R4-R11} \n"
-	"        BX     lr \n" );
-}
-
-/** \brief  Invalidate the whole D$
-
-    DCISW. Invalidate by Set/Way
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_dcache_all(void) {
-    __v7_all_cache(0);
-}
-/** \brief  Clean the whole D$
-
-    DCCSW. Clean by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_dcache_all(void) {
-    __v7_all_cache(1);
-}
-
-/** \brief  Clean and invalidate the whole D$
-
-    DCCISW. Clean and Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
-    __v7_all_cache(2);
-}
-/** \brief  Clean and Invalidate D$ by MVA
-
-    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-    __MCR(15, 0, (uint32_t)va, 7, 14, 1);
-    __DMB();
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-    __ASM volatile ("cpsie i");
-}
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("mrs %0, cpsr" : "=r" (result));
-    __ASM volatile ("cpsid i");
-    return(result & 0x80);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-#if 1
-  register uint32_t __regAPSR;
-  __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
-#else
-  register uint32_t __regAPSR          __ASM("apsr");
-#endif
-  return(__regAPSR);
-}
-
-
-/** \brief  Get CPSR Register
-
-    This function returns the content of the CPSR Register.
-
-    \return               CPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
-{
-#if 1
-  register uint32_t __regCPSR;
-  __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
-#else
-  register uint32_t __regCPSR          __ASM("cpsr");
-#endif
-  return(__regCPSR);
-}
-
-#if 0
-/** \brief  Set Stack Pointer
-
-    This function assigns the given value to the current stack pointer.
-
-    \param [in]    topOfStack  Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
-{
-    register uint32_t __regSP       __ASM("sp");
-    __regSP = topOfStack;
-}
-#endif
-
-/** \brief  Get link register
-
-    This function returns the value of the link register
-
-    \return    Value of link register
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
-{
-  register uint32_t __reglr         __ASM("lr");
-  return(__reglr);
-}
-
-#if 0
-/** \brief  Set link register
-
-    This function sets the value of the link register
-
-    \param [in]    lr  LR value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
-{
-  register uint32_t __reglr         __ASM("lr");
-  __reglr = lr;
-}
-#endif
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-    __asm__ volatile (
-    ".ARM;"
-    ".eabi_attribute Tag_ABI_align8_preserved,1;"
-
-    "BIC     R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
-    "MRS     R1, CPSR;"
-    "CPS     %0;"         /* ;no effect in USR mode */
-    "MOV     SP, R0;"
-    "MSR     CPSR_c, R1;" /* ;no effect in USR mode */
-    "ISB;"
-    //"BX      LR;"
-    :
-    : "i"(MODE_SYS)
-    : "r0", "r1");
-    return;
-}
-
-/** \brief  Set User Mode
-
-    This function changes the processor state to User Mode
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
-{
-    __asm__ volatile (
-    ".ARM;"
-
-    "CPS  %0;"
-    //"BX   LR;"
-    :
-    : "i"(MODE_USR)
-    : );
-    return;
-}
-
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq()                __asm__ volatile ("cpsie f")
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq()               __asm__ volatile ("cpsid f")
-
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-#if 1
-    uint32_t result;
-
-    __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
-    return (result);
-#else
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#endif
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-#if 1
-    __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
-#else
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-#endif
-}
-
-/** \brief  Get FPEXC
-
-    This function returns the current value of the Floating Point Exception Control register.
-
-    \return               Floating Point Exception Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
-#if 1
-    uint32_t result;
-
-    __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
-    return (result);
-#else
-  register uint32_t __regfpexc         __ASM("fpexc");
-  return(__regfpexc);
-#endif
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPEXC
-
-    This function assigns the given value to the Floating Point Exception Control register.
-
-    \param [in]    fpscr  Floating Point Exception Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
-#if 1
-    __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
-#else
-  register uint32_t __regfpexc         __ASM("fpexc");
-  __regfpexc = (fpexc);
-#endif
-#endif
-}
-
-/** \brief  Get CPACR
-
-    This function returns the current value of the Coprocessor Access Control register.
-
-    \return               Coprocessor Access Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
-{
-#if 1
-    register uint32_t __regCPACR;
-    __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
-#else
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-#endif
-    return __regCPACR;
-}
-
-/** \brief  Set CPACR
-
-    This function assigns the given value to the Coprocessor Access Control register.
-
-    \param [in]    cpacr  Coprocessor Acccess Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
-#else
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-    __regCPACR = cpacr;
-#endif
-    __ISB();
-}
-
-/** \brief  Get CBAR
-
-    This function returns the value of the Configuration Base Address register.
-
-    \return               Configuration Base Address register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
-#if 1
-    register uint32_t __regCBAR;
-    __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
-#else
-    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
-#endif
-    return(__regCBAR);
-}
-
-/** \brief  Get TTBR0
-
-    This function returns the value of the Translation Table Base Register 0.
-
-    \return               Translation Table Base Register 0 value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
-#if 1
-    register uint32_t __regTTBR0;
-    __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
-#else
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-#endif
-    return(__regTTBR0);
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
-#else
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-    __regTTBR0 = ttbr0;
-#endif
-    __ISB();
-}
-
-/** \brief  Get DACR
-
-    This function returns the value of the Domain Access Control Register.
-
-    \return               Domain Access Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
-#if 1
-    register uint32_t __regDACR;
-    __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
-#else
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-#endif
-    return(__regDACR);
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
-#else
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-    __regDACR = dacr;
-#endif
-    __ISB();
-}
-
-/******************************** Cache and BTAC enable  ****************************************************/
-
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
-#else
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-    __regSCTLR = sctlr;
-#endif
-}
-
-/** \brief  Get SCTLR
-
-    This function returns the value of the System Control Register.
-
-    \return               System Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
-#if 1
-	register uint32_t __regSCTLR;
-	__ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
-#else
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-#endif
-    return(__regSCTLR);
-}
-
-/** \brief  Enable Caches
-
-    Enable Caches
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
-    // Set I bit 12 to enable I Cache
-    // Set C bit  2 to enable D Cache
-    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief  Disable Caches
-
-    Disable Caches
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
-    // Clear I bit 12 to disable I Cache
-    // Clear C bit  2 to disable D Cache
-    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
-    __ISB();
-}
-
-/** \brief  Enable BTAC
-
-    Enable BTAC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
-    // Set Z bit 11 to enable branch prediction
-    __set_SCTLR( __get_SCTLR() | (1 << 11));
-    __ISB();
-}
-
-/** \brief  Disable BTAC
-
-    Disable BTAC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
-    // Clear Z bit 11 to disable branch prediction
-    __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-
-/** \brief  Enable MMU
-
-    Enable MMU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
-    // Set M bit 0 to enable the MMU
-    // Set AFE bit to enable simplified access permissions model
-    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
-    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
-    __ISB();
-}
-
-/** \brief  Disable MMU
-
-    Disable MMU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
-    // Clear M bit 0 to disable the MMU
-    __set_SCTLR( __get_SCTLR() & ~1);
-    __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief  Invalidate the whole tlb
-
-    TLBIALL. Invalidate the whole tlb
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
-#else
-    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");
-    __TLBIALL = 0;
-#endif
-    __DSB();
-    __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief  Invalidate entire branch predictor array
-
-    BPIALL. Branch Predictor Invalidate All.
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
-#else
-    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");
-    __BPIALL  = 0;
-#endif
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief  Invalidate the whole I$
-
-    ICIALLU. Instruction Cache Invalidate All to PoU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
-#else
-    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
-    __ICIALLU = 0;
-#endif
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief  Clean D$ by MVA
-
-    DCCMVAC. Data cache clean by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
-#else
-    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
-    __DCCMVAC = (uint32_t)va;
-#endif
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Invalidate D$ by MVA
-
-    DCIMVAC. Data cache invalidate by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
-#else
-    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
-    __DCIMVAC = (uint32_t)va;
-#endif
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate D$ by MVA
-
-    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
-#else
-    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
-    __DCCIMVAC = (uint32_t)va;
-#endif
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate the entire data or unified cache
-
-    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
-extern void __v7_all_cache(uint32_t op);
-
-
-/** \brief  Invalidate the whole D$
-
-    DCISW. Invalidate by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
-    __v7_all_cache(0);
-}
-
-/** \brief  Clean the whole D$
-
-    DCCSW. Clean by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
-    __v7_all_cache(1);
-}
-
-/** \brief  Clean and invalidate the whole D$
-
-    DCCISW. Clean and Invalidate by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
-    __v7_all_cache(2);
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-
-#error TASKING Compiler support not implemented for Cortex-A
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CAFUNC_H__ */

--- a/cmsis/TARGET_CORTEX_A/core_caInstr.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/**************************************************************************//**
- * @file     core_caInstr.h
- * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date     04. December 2012
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#ifndef __CORE_CAINSTR_H__
-#define __CORE_CAINSTR_H__
-
-#define __CORTEX_M 0x3
-#include "core_cmInstr.h"
-#undef  __CORTEX_M
-
-#endif
-

--- a/cmsis/TARGET_CORTEX_A/core_ca_mmu.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,847 +0,0 @@
-;/**************************************************************************//**
-; * @file     core_ca_mmu.h
-; * @brief    MMU Startup File for A9_MP Device Series
-; * @version  V1.01
-; * @date     10 Sept 2014
-; *
-; * @note
-; *
-; ******************************************************************************/
-;/* Copyright (c) 2012-2014 ARM LIMITED
-;
-;   All rights reserved.
-;   Redistribution and use in source and binary forms, with or without
-;   modification, are permitted provided that the following conditions are met:
-;   - Redistributions of source code must retain the above copyright
-;     notice, this list of conditions and the following disclaimer.
-;   - Redistributions in binary form must reproduce the above copyright
-;     notice, this list of conditions and the following disclaimer in the
-;     documentation and/or other materials provided with the distribution.
-;   - Neither the name of ARM nor the names of its contributors may be used
-;     to endorse or promote products derived from this software without
-;     specific prior written permission.
-;   *
-;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-;   POSSIBILITY OF SUCH DAMAGE.
-;   ---------------------------------------------------------------------------*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef _MMU_FUNC_H
-#define _MMU_FUNC_H
-
-#define SECTION_DESCRIPTOR      (0x2)
-#define SECTION_MASK            (0xFFFFFFFC)
-
-#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
-#define SECTION_B_SHIFT         (2)
-#define SECTION_C_SHIFT         (3)
-#define SECTION_TEX0_SHIFT      (12)
-#define SECTION_TEX1_SHIFT      (13)
-#define SECTION_TEX2_SHIFT      (14)
-
-#define SECTION_XN_MASK         (0xFFFFFFEF)
-#define SECTION_XN_SHIFT        (4)
-
-#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
-#define SECTION_DOMAIN_SHIFT    (5)
-
-#define SECTION_P_MASK          (0xFFFFFDFF)
-#define SECTION_P_SHIFT         (9)
-
-#define SECTION_AP_MASK         (0xFFFF73FF)
-#define SECTION_AP_SHIFT        (10)
-#define SECTION_AP2_SHIFT       (15)
-
-#define SECTION_S_MASK          (0xFFFEFFFF)
-#define SECTION_S_SHIFT         (16)
-
-#define SECTION_NG_MASK         (0xFFFDFFFF)
-#define SECTION_NG_SHIFT        (17)
-
-#define SECTION_NS_MASK         (0xFFF7FFFF)
-#define SECTION_NS_SHIFT        (19)
-
-
-#define PAGE_L1_DESCRIPTOR      (0x1)
-#define PAGE_L1_MASK            (0xFFFFFFFC)
-
-#define PAGE_L2_4K_DESC         (0x2)
-#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
-
-#define PAGE_L2_64K_DESC        (0x1)
-#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
-
-#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
-#define PAGE_4K_B_SHIFT         (2)
-#define PAGE_4K_C_SHIFT         (3)
-#define PAGE_4K_TEX0_SHIFT      (6)
-#define PAGE_4K_TEX1_SHIFT      (7)
-#define PAGE_4K_TEX2_SHIFT      (8)
-
-#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
-#define PAGE_64K_B_SHIFT        (2)
-#define PAGE_64K_C_SHIFT        (3)
-#define PAGE_64K_TEX0_SHIFT     (12)
-#define PAGE_64K_TEX1_SHIFT     (13)
-#define PAGE_64K_TEX2_SHIFT     (14)
-
-#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
-#define PAGE_B_SHIFT            (2)
-#define PAGE_C_SHIFT            (3)
-#define PAGE_TEX_SHIFT          (12)
-
-#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
-#define PAGE_XN_4K_SHIFT        (0)
-#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
-#define PAGE_XN_64K_SHIFT       (15)
-
-
-#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
-#define PAGE_DOMAIN_SHIFT       (5)
-
-#define PAGE_P_MASK             (0xFFFFFDFF)
-#define PAGE_P_SHIFT            (9)
-
-#define PAGE_AP_MASK            (0xFFFFFDCF)
-#define PAGE_AP_SHIFT           (4)
-#define PAGE_AP2_SHIFT          (9)
-
-#define PAGE_S_MASK             (0xFFFFFBFF)
-#define PAGE_S_SHIFT            (10)
-
-#define PAGE_NG_MASK            (0xFFFFF7FF)
-#define PAGE_NG_SHIFT           (11)
-
-#define PAGE_NS_MASK            (0xFFFFFFF7)
-#define PAGE_NS_SHIFT           (3)
-
-#define OFFSET_1M               (0x00100000)
-#define OFFSET_64K              (0x00010000)
-#define OFFSET_4K               (0x00001000)
-
-#define DESCRIPTOR_FAULT        (0x00000000)
-
-/* ###########################  MMU Function Access  ########################### */
-/** \ingroup  MMU_FunctionInterface
-    \defgroup MMU_Functions MMU Functions Interface
-  @{
- */
-
-/* Attributes enumerations */
-
-/* Region size attributes */
-typedef enum
-{
-   SECTION,
-   PAGE_4k,
-   PAGE_64k,
-} mmu_region_size_Type;
-
-/* Region type attributes */
-typedef enum
-{
-   NORMAL,
-   DEVICE,
-   SHARED_DEVICE,
-   NON_SHARED_DEVICE,
-   STRONGLY_ORDERED
-} mmu_memory_Type;
-
-/* Region cacheability attributes */
-typedef enum
-{
-   NON_CACHEABLE,
-   WB_WA,
-   WT,
-   WB_NO_WA,
-} mmu_cacheability_Type;
-
-/* Region parity check attributes */
-typedef enum
-{
-   ECC_DISABLED,
-   ECC_ENABLED,
-} mmu_ecc_check_Type;
-
-/* Region execution attributes */
-typedef enum
-{
-   EXECUTE,
-   NON_EXECUTE,
-} mmu_execute_Type;
-
-/* Region global attributes */
-typedef enum
-{
-   GLOBAL,
-   NON_GLOBAL,
-} mmu_global_Type;
-
-/* Region shareability attributes */
-typedef enum
-{
-   NON_SHARED,
-   SHARED,
-} mmu_shared_Type;
-
-/* Region security attributes */
-typedef enum
-{
-   SECURE,
-   NON_SECURE,
-} mmu_secure_Type;
-
-/* Region access attributes */
-typedef enum
-{
-   NO_ACCESS,
-   RW,
-   READ,
-} mmu_access_Type;
-
-/* Memory Region definition */
-typedef struct RegionStruct {
-    mmu_region_size_Type rg_t;
-    mmu_memory_Type mem_t;
-    uint8_t domain;
-    mmu_cacheability_Type inner_norm_t;
-    mmu_cacheability_Type outer_norm_t;
-    mmu_ecc_check_Type e_t;
-    mmu_execute_Type xn_t;
-    mmu_global_Type g_t;
-    mmu_secure_Type sec_t;
-    mmu_access_Type priv_t;
-    mmu_access_Type user_t;
-    mmu_shared_Type sh_t;
-
-} mmu_region_attributes_Type;
-
-/** \brief  Set section execution-never attribute
-
-    The function sets section execution-never attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
-
-    \return          0  
- */
-__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
-{
-    *descriptor_l1 &= SECTION_XN_MASK;
-    *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section domain
-
-    The function sets section domain
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]            domain  Section domain
-
-    \return          0  
- */
-__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
-{
-    *descriptor_l1 &= SECTION_DOMAIN_MASK;
-    *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section parity check
-
-    The function sets section parity check
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
-    \return          0  
- */
-__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
-    *descriptor_l1 &= SECTION_P_MASK;
-    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section access privileges
-
-    The function sets section access privileges
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
-    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
-    \param [in]               afe  Access flag enable
-
-    \return          0  
- */
-__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
-{
-    uint32_t ap = 0;
-
-    if (afe == 0) { //full access
-        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
-        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
-        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-    }
-
-    else { //Simplified access
-        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-    }
-
-    *descriptor_l1 &= SECTION_AP_MASK;
-    *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
-    *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
-
-    return 0;
-}
-
-/** \brief  Set section shareability
-
-    The function sets section shareability
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
-
-    \return          0  
- */
-__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
-{
-    *descriptor_l1 &= SECTION_S_MASK;
-    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section Global attribute
-
-    The function sets section Global attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
-
-    \return          0  
- */
-__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
-{
-    *descriptor_l1 &= SECTION_NG_MASK;
-    *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section Security attribute
-
-    The function sets section Global attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
-
-    \return          0  
- */
-__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
-    *descriptor_l1 &= SECTION_NS_MASK;
-    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
-    return 0;
-}
-
-/* Page 4k or 64k */
-/** \brief  Set 4k/64k page execution-never attribute
-
-    The function sets 4k/64k page execution-never attribute
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
-    \param [in]              page  Page size: PAGE_4k, PAGE_64k,
-   
-    \return          0  
- */
-__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
-{
-    if (page == PAGE_4k)
-    {
-        *descriptor_l2 &= PAGE_XN_4K_MASK;
-        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
-    }
-    else
-    {
-        *descriptor_l2 &= PAGE_XN_64K_MASK;
-        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
-    }
-    return 0;
-}
-
-/** \brief  Set 4k/64k page domain
-
-    The function sets 4k/64k page domain
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]            domain  Page domain
-
-    \return          0  
- */
-__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
-{
-    *descriptor_l1 &= PAGE_DOMAIN_MASK;
-    *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page parity check
-
-    The function sets 4k/64k page parity check
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
-    \return          0  
- */
-__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
-    *descriptor_l1 &= SECTION_P_MASK;
-    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page access privileges
-
-    The function sets 4k/64k page access privileges
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
-    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
-    \param [in]               afe  Access flag enable
-
-    \return          0  
- */
-__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
-{
-    uint32_t ap = 0;
-
-    if (afe == 0) { //full access
-        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
-        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
-        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x6; }
-    }
-
-    else { //Simplified access
-        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-    }
-
-    *descriptor_l2 &= PAGE_AP_MASK;
-    *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
-    *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
-
-    return 0;
-}
-
-/** \brief  Set 4k/64k page shareability
-
-    The function sets 4k/64k page shareability
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
-
-    \return          0  
- */
-__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
-{
-    *descriptor_l2 &= PAGE_S_MASK;
-    *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page Global attribute
-
-    The function sets 4k/64k page Global attribute
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
-
-    \return          0  
- */
-__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
-{
-    *descriptor_l2 &= PAGE_NG_MASK;
-    *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page Security attribute
-
-    The function sets 4k/64k page Global attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
-
-    \return          0  
- */
-__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
-    *descriptor_l1 &= PAGE_NS_MASK;
-    *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
-    return 0;
-}
-
-
-/** \brief  Set Section memory attributes
-
-    The function sets section memory attributes
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
-    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
-    \return          0  
- */
-__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
-{
-    *descriptor_l1 &= SECTION_TEXCB_MASK;
-
-    if (STRONGLY_ORDERED == mem)
-    {
-        return 0;
-    }
-    else if (SHARED_DEVICE == mem)
-    {
-        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
-    }
-    else if (NON_SHARED_DEVICE == mem)
-    {
-        *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
-    }
-    else if (NORMAL == mem)
-    {
-           *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
-           switch(inner)
-           {
-            case NON_CACHEABLE:
-            break;
-            case WB_WA:
-                *descriptor_l1 |= (1 << SECTION_B_SHIFT);
-                break;
-            case WT:
-                *descriptor_l1 |= 1 << SECTION_C_SHIFT;
-                break;
-            case WB_NO_WA:
-                *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
-                break;
-        }
-        switch(outer)
-        {
-            case NON_CACHEABLE:
-             break;
-            case WB_WA:
-                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
-                break;
-            case WT:
-                *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
-                break;
-            case WB_NO_WA:
-                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
-                break;
-        }
-    }
-
-    return 0;
-}
-
-/** \brief  Set 4k/64k page memory attributes
-
-    The function sets 4k/64k page memory attributes
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
-    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
-    \return          0  
- */
-__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
-{
-    *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
-
-    if (page == PAGE_64k)
-    {
-        //same as section
-        __memory_section(descriptor_l2, mem, outer, inner);
-    }
-    else
-    {
-        if (STRONGLY_ORDERED == mem)
-        {
-            return 0;
-        }
-        else if (SHARED_DEVICE == mem)
-        {
-            *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
-        }
-        else if (NON_SHARED_DEVICE == mem)
-        {
-             *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
-        }
-        else if (NORMAL == mem)
-        {
-            *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
-            switch(inner)
-            {
-                case NON_CACHEABLE:
-                break;
-                case WB_WA:
-                     *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
-                     break;
-                case WT:
-                    *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
-                     break;
-                case WB_NO_WA:
-                    *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
-                    break;
-            }
-            switch(outer)
-            {
-                case NON_CACHEABLE:
-                break;
-                case WB_WA:
-                      *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
-                    break;
-                case WT:
-                     *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
-                    break;
-                case WB_NO_WA:
-                    *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
-                    break;
-            }
-        }
-    }
-
-    return 0;
-}
-
-/** \brief  Create a L1 section descriptor
-
-    The function creates a section descriptor.
-    
-    Assumptions:
-    - 16MB super sections not supported
-    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
-    - Functions always return 0
-
-    \param [out]       descriptor  L1 descriptor
-    \param [out]      descriptor2  L2 descriptor
-    \param [in]               reg  Section attributes
-
-    \return          0  
- */
-__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
-{
-    *descriptor  = 0;
-
-   __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
-   __xn_section(descriptor,reg.xn_t);
-   __domain_section(descriptor, reg.domain);
-   __p_section(descriptor, reg.e_t);
-   __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
-   __shared_section(descriptor,reg.sh_t);
-   __global_section(descriptor,reg.g_t);
-   __secure_section(descriptor,reg.sec_t);
-   *descriptor &= SECTION_MASK;
-   *descriptor |= SECTION_DESCRIPTOR;
-
-   return 0;
-
-}
-
-
-/** \brief  Create a L1 and L2 4k/64k page descriptor
-
-    The function creates a 4k/64k page descriptor.
-    Assumptions:
-    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
-    - Functions always return 0
-
-    \param [out]       descriptor  L1 descriptor
-    \param [out]      descriptor2  L2 descriptor
-    \param [in]               reg  4k/64k page attributes
-
-    \return          0  
- */
-__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
-{
-    *descriptor  = 0;
-    *descriptor2 = 0;
-
-    switch (reg.rg_t)
-    {
-        case PAGE_4k:
-            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
-            __xn_page(descriptor2, reg.xn_t, PAGE_4k);
-            __domain_page(descriptor, reg.domain);
-            __p_page(descriptor, reg.e_t);
-            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
-            __shared_page(descriptor2,reg.sh_t);
-            __global_page(descriptor2,reg.g_t);
-            __secure_page(descriptor,reg.sec_t);
-            *descriptor &= PAGE_L1_MASK;
-            *descriptor |= PAGE_L1_DESCRIPTOR;
-            *descriptor2 &= PAGE_L2_4K_MASK;
-            *descriptor2 |= PAGE_L2_4K_DESC;
-            break;
-
-        case PAGE_64k:
-            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
-            __xn_page(descriptor2, reg.xn_t, PAGE_64k);
-            __domain_page(descriptor, reg.domain);
-            __p_page(descriptor, reg.e_t);
-            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
-            __shared_page(descriptor2,reg.sh_t);
-            __global_page(descriptor2,reg.g_t);
-            __secure_page(descriptor,reg.sec_t);
-            *descriptor &= PAGE_L1_MASK;
-            *descriptor |= PAGE_L1_DESCRIPTOR;
-            *descriptor2 &= PAGE_L2_64K_MASK;
-            *descriptor2 |= PAGE_L2_64K_DESC;
-            break;
-
-        case SECTION:
-            //error
-            break;    
-
-    }
-
-   return 0;
-
-}
-
-/** \brief  Create a 1MB Section
-
-    \param [in]               ttb  Translation table base address
-    \param [in]      base_address  Section base address
-    \param [in]             count  Number of sections to create
-    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
-
- */
-__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
-{
-    uint32_t offset;
-    uint32_t entry;
-    uint32_t i;
-
-    offset = base_address >> 20;
-    entry  = (base_address & 0xFFF00000) | descriptor_l1;
-
-    //4 bytes aligned
-    ttb = ttb + offset;
-
-    for (i = 0; i < count; i++ )
-    {
-        //4 bytes aligned
-       *ttb++ = entry;
-       entry += OFFSET_1M;
-    }
-}
-
-/** \brief  Create a 4k page entry
-
-    \param [in]               ttb  L1 table base address
-    \param [in]      base_address  4k base address
-    \param [in]             count  Number of 4k pages to create
-    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
-    \param [in]            ttb_l2  L2 table base address
-    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
-
- */
-__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
-
-    uint32_t offset, offset2;
-    uint32_t entry, entry2;
-    uint32_t i;
-
-
-    offset = base_address >> 20;
-    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
-    //4 bytes aligned
-    ttb += offset;
-    //create l1_entry
-    *ttb = entry;
-
-    offset2 = (base_address & 0xff000) >> 12;
-    ttb_l2 += offset2;
-    entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
-    for (i = 0; i < count; i++ )
-    {
-        //4 bytes aligned
-       *ttb_l2++ = entry2;
-       entry2 += OFFSET_4K;
-    }
-}
-
-/** \brief  Create a 64k page entry
-
-    \param [in]               ttb  L1 table base address
-    \param [in]      base_address  64k base address
-    \param [in]             count  Number of 64k pages to create
-    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
-    \param [in]            ttb_l2  L2 table base address
-    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
-
- */
-__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
-    uint32_t offset, offset2;
-    uint32_t entry, entry2;
-    uint32_t i,j;
-
-
-    offset = base_address >> 20;
-    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
-    //4 bytes aligned
-    ttb += offset;
-    //create l1_entry
-    *ttb = entry;
-
-    offset2 = (base_address & 0xff000) >> 12;
-    ttb_l2 += offset2;
-    entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
-    for (i = 0; i < count; i++ )
-    {
-        //create 16 entries
-        for (j = 0; j < 16; j++)
-            //4 bytes aligned
-            *ttb_l2++ = entry2;
-        entry2 += OFFSET_64K;
-    }
-}
-
-/*@} end of MMU_Functions */
-#endif
-
-#ifdef __cplusplus
-}
-#endif

--- a/cmsis/TARGET_CORTEX_A/core_cm4_simd.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,673 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4_simd.h
- * @brief    CMSIS Cortex-M4 SIMD Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_iar.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_ccs.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif

--- a/cmsis/TARGET_CORTEX_A/core_cmInstr.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,916 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-  #define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
-  result = value;                      // r will be reversed bits of v; first get LSB of v
-  for (value >>= 1; value; value >>= 1)
-  {
-    result <<= 1;
-    result |= value & 1;
-    s--;
-  }
-  result <<= s;                       // shift when v's highest bits are zero
-  return(result);
-}
-#endif
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (short)__builtin_bswap16(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
-  result = value;                      // r will be reversed bits of v; first get LSB of v
-  for (value >>= 1; value; value >>= 1)
-  {
-    result <<= 1;
-    result |= value & 1;
-    s--;
-  }
-  result <<= s;                       // shift when v's highest bits are zero
-#endif
-  return(result);
-}
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_A/irq_ctrl.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,180 @@
+/**************************************************************************//**
+ * @file     irq_ctrl.h
+ * @brief    Interrupt Controller API header file
+ * @version  V1.0.0
+ * @date     23. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef IRQ_CTRL_H_
+#define IRQ_CTRL_H_
+
+#include <stdint.h>
+
+#ifndef IRQHANDLER_T
+#define IRQHANDLER_T
+/// Interrupt handler data type
+typedef void (*IRQHandler_t) (void);
+#endif
+
+#ifndef IRQN_ID_T
+#define IRQN_ID_T
+/// Interrupt ID number data type
+typedef int32_t IRQn_ID_t;
+#endif
+
+/* Interrupt mode bit-masks */
+#define IRQ_MODE_TRIG_Pos           (0U)
+#define IRQ_MODE_TRIG_Msk           (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
+#define IRQ_MODE_TRIG_LEVEL         (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_LOW     (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_HIGH    (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
+#define IRQ_MODE_TRIG_EDGE          (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_FALLING  (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_BOTH     (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
+
+#define IRQ_MODE_TYPE_Pos           (3U)
+#define IRQ_MODE_TYPE_Msk           (0x01UL << IRQ_MODE_TYPE_Pos)
+#define IRQ_MODE_TYPE_IRQ           (0x00UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU IRQ line
+#define IRQ_MODE_TYPE_FIQ           (0x01UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU FIQ line
+
+#define IRQ_MODE_DOMAIN_Pos         (4U)
+#define IRQ_MODE_DOMAIN_Msk         (0x01UL << IRQ_MODE_DOMAIN_Pos)
+#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting non-secure domain
+#define IRQ_MODE_DOMAIN_SECURE      (0x01UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting secure domain
+
+#define IRQ_MODE_CPU_Pos            (5U)
+#define IRQ_MODE_CPU_Msk            (0xFFUL << IRQ_MODE_CPU_Pos)
+#define IRQ_MODE_CPU_ALL            (0x00UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets all CPUs
+#define IRQ_MODE_CPU_0              (0x01UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 0
+#define IRQ_MODE_CPU_1              (0x02UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 1
+#define IRQ_MODE_CPU_2              (0x04UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 2
+#define IRQ_MODE_CPU_3              (0x08UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 3
+#define IRQ_MODE_CPU_4              (0x10UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 4
+#define IRQ_MODE_CPU_5              (0x20UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 5
+#define IRQ_MODE_CPU_6              (0x40UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 6
+#define IRQ_MODE_CPU_7              (0x80UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 7
+
+#define IRQ_MODE_ERROR              (0x80000000UL)                    ///< Bit indicating mode value error
+
+/* Interrupt priority bit-masks */
+#define IRQ_PRIORITY_Msk            (0x0000FFFFUL)                    ///< Interrupt priority value bit-mask
+#define IRQ_PRIORITY_ERROR          (0x80000000UL)                    ///< Bit indicating priority value error
+
+/// Initialize interrupt controller.
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Initialize (void);
+
+/// Register interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     handler       interrupt handler function address
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
+
+/// Get the registered interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \return registered interrupt handler function address.
+IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
+
+/// Enable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Enable (IRQn_ID_t irqn);
+
+/// Disable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Disable (IRQn_ID_t irqn);
+
+/// Get interrupt enable state.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
+uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
+
+/// Configure interrupt request mode.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     mode          mode configuration
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
+
+/// Get interrupt mode configuration.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
+uint32_t IRQ_GetMode (IRQn_ID_t irqn);
+
+/// Get ID number of current interrupt request (IRQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveIRQ (void);
+
+/// Get ID number of current fast interrupt request (FIQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveFIQ (void);
+
+/// Signal end of interrupt processing.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
+
+/// Set interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPending (IRQn_ID_t irqn);
+
+/// Get interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
+uint32_t IRQ_GetPending (IRQn_ID_t irqn);
+
+/// Clear interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_ClearPending (IRQn_ID_t irqn);
+
+/// Set interrupt priority value.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     priority      interrupt priority value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
+
+/// Get interrupt priority.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
+
+/// Set priority masking threshold.
+/// \param[in]     priority      priority masking threshold value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityMask (uint32_t priority);
+
+/// Get priority masking threshold
+/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityMask (void);
+
+/// Set priority grouping field split point
+/// \param[in]     bits          number of MSB bits included in the group priority field comparison
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
+
+/// Get priority grouping field split point
+/// \return current number of MSB bits included in the group priority field comparison with
+///         optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityGroupBits (void);
+
+#endif  // IRQ_CTRL_H_

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,403 @@
+/**************************************************************************//**
+ * @file     irq_ctrl_gic.c
+ * @brief    Interrupt controller handling implementation for GIC
+ * @version  V1.0.0
+ * @date     30. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+
+#include <cmsis.h>
+
+#include "irq_ctrl.h"
+
+#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
+
+/// Number of implemented interrupt lines
+#ifndef IRQ_GIC_LINE_COUNT
+#define IRQ_GIC_LINE_COUNT      (1020U)
+#endif
+
+static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
+static uint32_t   IRQ_ID0;
+
+/// Initialize interrupt controller.
+__WEAK int32_t IRQ_Initialize (void) {
+  uint32_t i;
+
+  for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
+    IRQTable[i] = (IRQHandler_t)NULL;
+  }
+  GIC_Enable();
+  return (0);
+}
+
+
+/// Register interrupt handler.
+__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    IRQTable[irqn] = handler;
+    status =  0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get the registered interrupt handler.
+__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
+  IRQHandler_t h;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    h = IRQTable[irqn];
+  } else {
+    h = (IRQHandler_t)0;
+  }
+
+  return (h);
+}
+
+
+/// Enable interrupt.
+__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EnableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Disable interrupt.
+__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_DisableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt enable state.
+__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
+  uint32_t enable;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
+  } else {
+    enable = 0U;
+  }
+
+  return (enable);
+}
+
+
+/// Configure interrupt request mode.
+__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
+  int32_t status;
+  uint32_t val;
+  uint8_t cfg;
+  uint8_t secure;
+  uint8_t cpu;
+
+  status = 0;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    // Check triggering mode
+    val = (mode & IRQ_MODE_TRIG_Msk);
+
+    if (val == IRQ_MODE_TRIG_LEVEL) {
+      cfg = 0x00U;
+    } else if (val == IRQ_MODE_TRIG_EDGE) {
+      cfg = 0x02U;
+    } else {
+      status = -1;
+    }
+
+    // Check interrupt type
+    val = mode & IRQ_MODE_TYPE_Msk;
+
+    if (val != IRQ_MODE_TYPE_IRQ) {
+      status = -1;
+    }
+
+    // Check interrupt domain
+    val = mode & IRQ_MODE_DOMAIN_Msk;
+
+    if (val == IRQ_MODE_DOMAIN_NONSECURE) {
+      secure = 0;
+    } else {
+      // Check security extensions support
+      val = GIC_DistributorInfo() & (1UL << 10U);
+
+      if (val != 0U) {
+        // Security extensions are supported
+        secure = 1;
+      } else {
+        status = -1;
+      }
+    }
+
+    // Check interrupt CPU targets
+    val = mode & IRQ_MODE_CPU_Msk;
+
+    if (val == IRQ_MODE_CPU_ALL) {
+      cpu = 0xFF;
+    } else {
+      cpu = val >> IRQ_MODE_CPU_Pos;
+    }
+
+    // Apply configuration if no mode error
+    if (status == 0) {
+      GIC_SetConfiguration((IRQn_Type)irqn, cfg);
+      GIC_SetTarget       ((IRQn_Type)irqn, cpu);
+
+      if (secure != 0U) {
+        GIC_SetGroup ((IRQn_Type)irqn, secure);
+      }
+    }
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt mode configuration.
+__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
+  uint32_t mode;
+  uint32_t val;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    mode = IRQ_MODE_TYPE_IRQ;
+
+    // Get trigger mode
+    val = GIC_GetConfiguration((IRQn_Type)irqn);
+
+    if ((val & 2U) != 0U) {
+      // Corresponding interrupt is edge triggered
+      mode |= IRQ_MODE_TRIG_EDGE;
+    } else {
+      // Corresponding interrupt is level triggered
+      mode |= IRQ_MODE_TRIG_LEVEL;
+    }
+
+    // Get interrupt CPU targets
+    mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
+
+  } else {
+    mode = IRQ_MODE_ERROR;
+  }
+
+  return (mode);
+}
+
+
+/// Get ID number of current interrupt request (IRQ).
+__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
+  IRQn_ID_t irqn;
+  uint32_t prio;
+
+  /* Dummy read to avoid GIC 390 errata 801120 */
+  GIC_GetHighPendingIRQ();
+
+  irqn = GIC_AcknowledgePending();
+
+  __DSB();
+
+  /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014)  */
+  /* The following workaround code is for a single-core system.  It would be       */
+  /* different in a multi-core system.                                             */
+  /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
+  /* so unlock it, otherwise service the interrupt as normal.                      */
+  /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2  */
+  /* so will not occur here.                                                       */
+
+  if ((irqn == 0) || (irqn >= 0x3FE)) {
+    /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
+    prio = GIC_GetPriority((IRQn_Type)0);
+    GIC_SetPriority ((IRQn_Type)0, prio);
+
+    __DSB();
+
+    if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
+      /* If the ID is 0, is active and has not been seen before */
+      IRQ_ID0 = 1U;
+    }
+    /* End of Workaround GIC 390 errata 733075 */
+  }
+
+  return (irqn);
+}
+
+
+/// Get ID number of current fast interrupt request (FIQ).
+__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
+  return ((IRQn_ID_t)-1);
+}
+
+
+/// Signal end of interrupt processing.
+__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EndInterrupt ((IRQn_Type)irqn);
+
+    if (irqn == 0) {
+      IRQ_ID0 = 0U;
+    }
+
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt pending flag.
+__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+/// Get interrupt pending flag.
+__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
+  uint32_t pending;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
+  } else {
+    pending = 0U;
+  }
+
+  return (pending & 1U);
+}
+
+
+/// Clear interrupt pending flag.
+__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_ClearPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt priority value.
+__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPriority ((IRQn_Type)irqn, priority);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt priority.
+__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
+  uint32_t priority;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    priority = GIC_GetPriority ((IRQn_Type)irqn);
+  } else {
+    priority = IRQ_PRIORITY_ERROR;
+  }
+
+  return (priority);
+}
+
+
+/// Set priority masking threshold.
+__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
+  GIC_SetInterfacePriorityMask (priority);
+  return (0);
+}
+
+
+/// Get priority masking threshold
+__WEAK uint32_t IRQ_GetPriorityMask (void) {
+  return GIC_GetInterfacePriorityMask();
+}
+
+
+/// Set priority grouping field split point
+__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
+  int32_t status;
+
+  if (bits == IRQ_PRIORITY_Msk) {
+    bits = 7U;
+  }
+
+  if (bits < 8U) {
+    GIC_SetBinaryPoint (7U - bits);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get priority grouping field split point
+__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
+  uint32_t bp;
+
+  bp = GIC_GetBinaryPoint() & 0x07U;
+
+  return (7U - bp);
+}
+
+#endif

--- a/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armcc.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,809 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_armcc.h
- * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCC_H
-#define __CMSIS_ARMCC_H
-
-
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* CMSIS compiler control architecture macros */
-#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
-     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
-  #define __ARM_ARCH_6M__           1
-#endif
-
-#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
-  #define __ARM_ARCH_7M__           1
-#endif
-
-#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
-  #define __ARM_ARCH_7EM__          1
-#endif
-
-  /* __ARM_ARCH_8M_BASE__  not applicable */
-  /* __ARM_ARCH_8M_MAIN__  not applicable */
-
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               __inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static __inline
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __declspec(noreturn)
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        __packed struct
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();     */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();    */
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
-  __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1U);
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#else
-  (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-  #define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
-#else
-  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
-#else
-  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
-#else
-  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX                           __clrex
-
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCC_H */

--- a/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1795 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_armclang.h
- * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
- * @version  V5.0.3
- * @date     27. March 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-//lint -esym(9058, IRQn)   disable MISRA 2012 Rule 2.4 for IRQn
-
-#ifndef __CMSIS_ARMCLANG_H
-#define __CMSIS_ARMCLANG_H
-
-#ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               __inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static __inline
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __attribute__((noreturn))
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-//lint -esym(9058, T_UINT32)  disable MISRA 2012 Rule 2.4 for T_UINT32
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-//lint -esym(9058, T_UINT16_WRITE)  disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-//lint -esym(9058, T_UINT16_READ)  disable MISRA 2012 Rule 2.4 for T_UINT16_READ
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-//lint -esym(9058, T_UINT32_WRITE)  disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
-  \return               SP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Set Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
-  \param [in]    topOfStack  Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
-  return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-/* #define __get_FPSCR      __builtin_arm_get_fpscr */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-  return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-/* #define __set_FPSCR      __builtin_arm_set_fpscr */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
-#else
-  (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP          __builtin_arm_nop
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI          __builtin_arm_wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE          __builtin_arm_wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV          __builtin_arm_sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB()        __builtin_arm_isb(0xF);
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()        __builtin_arm_dsb(0xF);
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB()        __builtin_arm_dmb(0xF);
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV          __builtin_bswap32
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV16          __builtin_bswap16                /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
-#if 0
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-                                                          /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-  int32_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-                                                          /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-  return(result);
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB        (uint8_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH        (uint16_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW        (uint32_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXB        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXH        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXW        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX             __builtin_arm_clrex
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT             __builtin_arm_ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT             __builtin_arm_usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEX                  (uint32_t)__builtin_arm_stlex
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
-  int32_t result;
-
-  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCLANG_H */

--- a/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1958 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_gcc.h
- * @brief    CMSIS compiler GCC header file
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static inline
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __attribute__((noreturn))
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
-  \return               SP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Set Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
-  \param [in]    topOfStack  Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
-  return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#else
-  (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-//{
-//  __ASM volatile ("nop");
-//}
-#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-//{
-//  __ASM volatile ("wfi");
-//}
-#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-//{
-//  __ASM volatile ("wfe");
-//}
-#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-//{
-//  __ASM volatile ("sev");
-//}
-#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (short)__builtin_bswap16(value);
-#else
-  int32_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-  return(result);
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/TOOLCHAIN_IAR/cmain.S	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,101 @@
+/**************************************************
+ *
+ * Part two of the system initialization code, contains C-level
+ * initialization, thumb-2 only variant.
+ *
+ * $Revision: 59783 $
+ *
+ **************************************************/
+/* Copyright 2008-2017, IAR Systems AB.
+   This source code is the property of IAR Systems. The source code may only
+   be used together with the IAR Embedded Workbench. Redistribution and use
+   in source and binary forms, with or without modification, is permitted
+   provided that the following conditions are met:
+   - Redistributions of source code, in whole or in part, must retain the
+     above copyright notice, this list of conditions and the disclaimer below.
+   - IAR Systems name may not be used to endorse or promote products
+     derived from this software without specific prior written permission.
+
+   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+; --------------------------------------------------
+; Module ?cmain, C-level initialization.
+;
+
+
+        SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
+        SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
+
+        SECTION .text:CODE:NOROOT(2)
+
+        PUBLIC  __cmain
+        ;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
+        PUBLIC  ?main
+        EXTWEAK __iar_data_init3
+        EXTWEAK __iar_argc_argv
+        EXTERN  __low_level_init
+        EXTERN  __call_ctors
+        EXTERN  main
+        EXTERN  exit
+        EXTERN  __iar_dynamic_initialization
+        EXTERN mbed_sdk_init
+        EXTERN mbed_main
+        EXTERN SystemInit
+        
+        THUMB
+__cmain:
+?main:
+
+; Initialize segments.
+; __segment_init and __low_level_init are assumed to use the same
+; instruction set and to be reachable by BL from the ICODE segment
+; (it is safest to link them in segment ICODE).
+
+          FUNCALL __cmain, __low_level_init
+        bl      __low_level_init
+        cmp     r0,#0
+        beq     ?l1
+          FUNCALL __cmain, __iar_data_init3
+        bl      __iar_data_init3
+        MOVS    r0,#0             ;  No parameters
+        FUNCALL __cmain, mbed_sdk_init
+        BL      mbed_sdk_init
+        MOVS    r0,#0             ;  No parameters        
+          FUNCALL __cmain, __iar_dynamic_initialization
+        BL      __iar_dynamic_initialization   ; C++ dynamic initialization  
+
+?l1:
+        REQUIRE ?l3
+
+        SECTION .text:CODE:NOROOT(2)
+
+        PUBLIC  _main
+        PUBLIC _call_main
+        THUMB
+
+__iar_init$$done:                 ; Copy initialization is done
+
+?l3:
+_call_main:
+        MOVS    r0,#0             ;  No parameters  
+          FUNCALL __cmain, __iar_argc_argv
+        BL      __iar_argc_argv   ; Maybe setup command line
+
+        MOVS    r0,#0             ;  No parameters  
+          FUNCALL __cmain, mbed_main
+        BL      mbed_main
+
+          FUNCALL __cmain, main
+        BL      main
+_main:
+          FUNCALL __cmain, exit
+        BL      exit
+
+        END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/arm_math.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,7190 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_math.h
+ * Description:  Public header file for CMSIS DSP Library
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+   * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
+   * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
+   * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
+   * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
+   * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+   * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
+   * 
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - ARM_MATH_ARMV8MxL:
+   *
+   * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
+   * on ARMv8M Mainline target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+   *
+   * - __DSP_PRESENT:
+   *
+   * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+  #include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+  #include "core_armv8mbl.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+  #include "core_armv8mml.h"
+  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+    #define ARM_MATH_DSP
+  #endif
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31          (0x100)
+#define DELTA_Q15          0x5
+#define INDEX_MASK         0x0000003F
+#ifndef PI
+  #define PI               3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING         0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if   defined ( __CC_ARM )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+#define __SIMD64(addr)        (*(int64_t **) & (addr))
+
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
+                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
+                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+    q31_t out;
+    uint32_t tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t) (__CLZ( in) - 1));
+    }
+    else
+    {
+      signBits = ((uint32_t) (__CLZ(-in) - 1));
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >> 24);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+      tempVal = 0x7FFFFFFFu - tempVal;
+      /*      1.31 with exp 1 */
+      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+  }
+
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+    q15_t out = 0;
+    uint32_t tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t)(__CLZ( in) - 17));
+    }
+    else
+    {
+      signBits = ((uint32_t)(__CLZ(-in) - 17));
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >>  8);
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFFu - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+  }
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
+    q31_t r = 0, s = 0;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+  uint32_t x)
+  {
+    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
+  }
+
+  /*
+   * @brief C custom defined SMMLA for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+  int32_t x,
+  int32_t y,
+  int32_t sum)
+  {
+    return (sum + (int32_t) (((int64_t) x * y) >> 32));
+  }
+
+#if 0
+  /*
+   * @brief C custom defined PKHBT for unavailable DSP extension
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
+  uint32_t x,
+  uint32_t y,
+  uint32_t leftshift)
+  {
+    return ( ((x             ) & 0x0000FFFFUL) |
+             ((y << leftshift) & 0xFFFF0000UL)  );
+  }
+
+  /*
+   * @brief C custom defined PKHTB for unavailable DSP extension
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
+  uint32_t x,
+  uint32_t y,
+  uint32_t rightshift)
+  {
+    return ( ((x              ) & 0xFFFF0000UL) |
+             ((y >> rightshift) & 0x0000FFFFUL)  );
+  }
+#endif
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed.
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in]  S          points to an instance of the Q15 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in]  S          points to an instance of the floating-point FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q15;
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_casd_df1_inst_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q31;
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]   pSrcA  points to the first input matrix structure
+   * @param[in]   pSrcB  points to the second input matrix structure
+   * @param[out]  pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  pSrc   points to the input matrix
+   * @param[in]  scale  scale factor
+   * @param[out] pDst   points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];     /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;          /**< The proportional gain. */
+    float32_t Ki;          /**< The integral gain. */
+    float32_t Kd;          /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] S               points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] S  is an instance of the floating-point PID Control structure
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] S   points to an instance of the Q31 PID Control structure
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] S  points to an instance of the q15 PID Control structure
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;        /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15 * S,
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31 * S,
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;             /**< length of the real sequence */
+    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+   arm_rfft_fast_instance_f32 * S,
+   uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    float32_t normalize;                 /**< normalizing factor. */
+    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;               /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q31_t normalize;                     /**< normalizing factor. */
+    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q15_t normalize;                     /**< normalizing factor. */
+    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  scale      scale factor to be applied
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q15(
+          q15_t * pSrcA,
+          uint32_t srcALen,
+          q15_t * pSrcB,
+          uint32_t srcBLen,
+          q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc  points to the block of input data.
+   * @param[out] pDst  points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   */
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.   The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process per call.
+ */
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] S          points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to the state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] S          points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;         /**< step size that control filter coefficient updates. */
+    float32_t energy;     /**< saves previous frame energy. */
+    float32_t x0;         /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
+    q15_t energy;         /**< saves previous frame energy. */
+    q15_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta   input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cos output.
+   */
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal);
+
+
+  /**
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cosine output.
+   */
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] S   is an instance of the floating-point PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] S  points to an instance of the Q31 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] S   points to an instance of the Q15 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#if defined (ARM_MATH_DSP)
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+  }
+
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+  }
+
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output   rotor reference frame d
+   * @param[out] pIq     points to output   rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+  }
+
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output rotor reference frame d
+   * @param[out] pIq     points to output rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for   Q31 version
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
+   * @param[in]     x  input sample to process
+   * @return y processed output sample.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if (i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if ((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 +  i      * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q31 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (q31_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q15 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (int32_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (q15_t) (y >> 20);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q7 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+    if (index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (q7_t) (y >> 20);
+     }
+  }
+
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  sin(x).
+   */
+  float32_t arm_sin_f32(
+  float32_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q31_t arm_sin_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q15_t arm_sin_q15(
+  q15_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  cos(x).
+   */
+  float32_t arm_cos_f32(
+  float32_t x);
+
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q31_t arm_cos_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in    input value.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if (in >= 0.0f)
+    {
+
+#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] result     is output pointer
+   * @param[in]  index      is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q31 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q15 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q7 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate.
+  * @param[in]     Y  interpolation coordinate.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
+    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
+    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return ((q31_t)(acc << 2));
+  }
+
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return ((q15_t)(acc >> 36));
+  }
+
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return ((q7_t)(acc >> 40));
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if   defined ( __CC_ARM )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("push")         \
+       _Pragma ("O1")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_EXIT \
+       _Pragma ("pop")
+  #else
+    #define LOW_OPTIMIZATION_EXIT
+  #endif
+
+  /* Enter low optimization region - place directly above function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+  #define LOW_OPTIMIZATION_ENTER \
+       __attribute__(( optimize("-O1") ))
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define LOW_OPTIMIZATION_EXIT
+
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef   __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/cmsis_armcc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,858 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint16_t __REV16(uint16_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U)) {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max) {
+      return max;
+    } else if (val < min) {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U) {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max) {
+      return max;
+    } else if (val < 0) {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/cmsis_armclang.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,1804 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version  V5.0.3
+ * @date     27. March 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV          (uint32_t)__builtin_bswap32
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16          (uint16_t)__builtin_bswap16
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value)
+{
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  
+  return result;
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            (uint32_t)__builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U)) {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max) {
+      return max;
+    } else if (val < min) {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U) {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max) {
+      return max;
+    } else if (val < 0) {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */

--- a/cmsis/TARGET_CORTEX_M/cmsis_compiler.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/cmsis/TARGET_CORTEX_M/cmsis_compiler.h	Wed Jan 17 15:23:54 2018 +0000
@@ -52,88 +52,9 @@
  * IAR Compiler
  */
 #elif defined ( __ICCARM__ )
-
-  #ifndef   __ASM
-    #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-
-  #include <cmsis_iar.h>
-
-  /* CMSIS compiler control architecture macros */
-  #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
-    #ifndef __ARM_ARCH_6M__
-      #define __ARM_ARCH_6M__                      1
-    #endif
-  #elif (__CORE__ == __ARM7M__)
-    #ifndef __ARM_ARCH_7M__
-      #define __ARM_ARCH_7M__                      1
-    #endif
-  #elif (__CORE__ == __ARM7EM__)
-    #ifndef __ARM_ARCH_7EM__
-      #define __ARM_ARCH_7EM__                     1
-    #endif
-  #elif (__CORE__ == __ARM8M_BASELINE__)
-    #ifndef __ARM_ARCH_8M_BASE__
-      #define __ARM_ARCH_8M_BASE__                 1
-    #endif
-  #elif (__CORE__ == __ARM8M_MAINLINE__)
-    #ifndef __ARM_ARCH_8M_MAIN__
-      #define __ARM_ARCH_8M_MAIN__                 1
-    #endif
-  #endif
-
-  // IAR version 7.8.1 and earlier do not include __ALIGNED
-  #ifndef __ALIGNED
-  #define __ALIGNED(x) __attribute__((aligned(x)))
-  #endif
+  #include <cmsis_iccarm.h>
 
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN                            __noreturn
-  #endif
-  #ifndef   __USED
-    #define __USED                                 __root
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __weak
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               __packed
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        __packed struct
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    __packed struct T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-    #define __ALIGNED(x)
-  #endif
-
-
+  
 /*
  * TI ARM Compiler
  */
@@ -164,6 +85,9 @@
   #ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        struct __attribute__((packed))
   #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
   #ifndef   __UNALIGNED_UINT32        /* deprecated */
     struct __attribute__((packed)) T_UINT32 { uint32_t v; };
     #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
@@ -187,6 +111,10 @@
   #ifndef   __ALIGNED
     #define __ALIGNED(x)                           __attribute__((aligned(x)))
   #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
 
 
 /*
@@ -223,6 +151,9 @@
   #ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        struct __packed__
   #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
   #ifndef   __UNALIGNED_UINT32        /* deprecated */
     struct __packed__ T_UINT32 { uint32_t v; };
     #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
@@ -246,6 +177,10 @@
   #ifndef   __ALIGNED
     #define __ALIGNED(x)              __align(x)
   #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
 
 
 /*
@@ -280,6 +215,9 @@
   #ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        @packed struct
   #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
   #ifndef   __UNALIGNED_UINT32        /* deprecated */
     @packed struct T_UINT32 { uint32_t v; };
     #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
@@ -304,6 +242,10 @@
     #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
     #define __ALIGNED(x)
   #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
 
 
 #else

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/cmsis_gcc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,2026 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+//{
+//  __ASM volatile ("nop");
+//}
+#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+//{
+//  __ASM volatile ("wfi");
+//}
+#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+//{
+//  __ASM volatile ("wfe");
+//}
+#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+//{
+//  __ASM volatile ("sev");
+//}
+#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in unsigned short value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __REV16(uint16_t value)
+{
+  uint16_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U)) {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max) {
+      return max;
+    } else if (val < min) {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U) {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max) {
+      return max;
+    } else if (val < 0) {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,771 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR compiler) header file
+ * @version  V5.0.3
+ * @date     29. August 2017
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((noreturn))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT restrict
+#endif
+
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr) {
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) {
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr) {
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) {
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr 			    __iar_builtin_rsr
+  #define __arm_wsr 			    __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #define __get_MSPLIM()              (__arm_rsr("MSPLIM"))
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+  #define __get_PSPLIM()              (__arm_rsr("PSPLIM"))
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+  #define __set_MSPLIM(VALUE)         (__arm_wsr("MSPLIM", (VALUE)))
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #define __set_PSPLIM(VALUE)         (__arm_wsr("PSPLIM", (VALUE)))
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+  #define __TZ_get_PSPLIM_NS()        (__arm_rsr("PSPLIM_NS"))
+  #define __TZ_set_PSPLIM_NS(VALUE)   (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP    __iar_builtin_no_operation
+
+  __IAR_FT uint8_t __CLZ(uint32_t val) {
+    return __iar_builtin_CLZ(val);
+  }
+
+  #define __CLREX __iar_builtin_CLREX
+
+  #define __DMB   __iar_builtin_DMB
+  #define __DSB   __iar_builtin_DSB
+  #define __ISB   __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int32_t __REVSH(int32_t val) {
+    return __iar_builtin_REVSH((int16_t)val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data) {
+      if (data == 0u) { return 32u; }
+
+      uint32_t count = 0;
+      uint32_t mask = 0x80000000;
+
+      while ((data & mask) == 0)
+      {
+        count += 1u;
+        mask = mask >> 1u;
+      }
+      return (count);
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v) {
+      uint8_t sc = 31;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void) {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value) {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value) {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq 	__enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void 	__TZ_set_CONTROL_NS(uint32_t value) {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t 	__TZ_get_PSP_NS(void) {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void 	__TZ_set_PSP_NS(uint32_t value) {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t 	__TZ_get_MSP_NS(void) {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void 	__TZ_set_MSP_NS(uint32_t value) {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t 	__TZ_get_SP_NS(void) {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void 	__TZ_set_SP_NS(uint32_t value) {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t 	__TZ_get_PRIMASK_NS(void) {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void 	__TZ_set_PRIMASK_NS(uint32_t value) {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t 	__TZ_get_BASEPRI_NS(void) {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void 	__TZ_set_BASEPRI_NS(uint32_t value) {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t 	__TZ_get_FAULTMASK_NS(void) {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void 	__TZ_set_FAULTMASK_NS(uint32_t value) {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t 	__TZ_get_PSPLIM_NS(void) {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void 	__TZ_set_PSPLIM_NS(uint32_t value) {
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t 	__TZ_get_MSPLIM_NS(void) {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void 	__TZ_set_MSPLIM_NS(uint32_t value) {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) {
+    if ((sat >= 1U) && (sat <= 32U)) {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max) {
+        return max;
+      } else if (val < min) {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) {
+    if (sat <= 31U) {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max) {
+        return max;
+      } else if (val < 0) {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) {
+    __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/cmsis_version.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_armv8mbl.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,1896 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS ARMv8MBL Core Peripheral Access Layer Header File
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+ 
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for ARMv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for ARMv8-M Baseline */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_armv8mml.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,2960 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS ARMv8MML Core Peripheral Access Layer Header File
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS ARMv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+  
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+  
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+  
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+  
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_cm0.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,888 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_cm0plus.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,1023 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0+ */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0+ */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_cm23.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,1896 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (23U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_cm3.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,1930 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_cm33.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,2960 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )     /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_cm4.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,2115 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_cm7.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,2657 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    register uint32_t ccsidr;
+    register uint32_t sets;
+    register uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_cmSecureAccess.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,201 @@
+/**************************************************************************//**
+ * @file     core_cmSecureAccess.h
+ * @brief    CMSIS Cortex-M Core Secure Access Header File
+ * @version  XXX
+ * @date     10. June 2016
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2016 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CM_SECURE_ACCESS_H
+#define __CORE_CM_SECURE_ACCESS_H
+
+
+/* ###########################  Core Secure Access  ########################### */
+
+#ifdef FEATURE_UVISOR
+#include "uvisor-lib/uvisor-lib.h"
+
+/* Secure uVisor implementation. */
+
+/** Set the value at the target address.
+ *
+ * Equivalent to: `*address = value`.
+ * @param address[in]  Target address
+ * @param value[in]    Value to write at the address location.
+ */
+#define SECURE_WRITE(address, value) \
+    uvisor_write(public_box, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
+
+/** Get the value at the target address.
+ *
+ * @param address[in]  Target address
+ * @returns The value `*address`.
+ */
+#define SECURE_READ(address) \
+    uvisor_read(public_box, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
+
+/** Get the selected bits at the target address.
+ *
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `*address & mask`.
+ */
+#define SECURE_BITS_GET(address, mask) \
+    UVISOR_BITS_GET(public_box, UVISOR_RGW_SHARED, address, mask)
+
+/** Check the selected bits at the target address.
+ *
+ * @param address[in]  Address at which to check the bits
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `((*address & mask) == mask)`.
+ */
+#define SECURE_BITS_CHECK(address, mask) \
+    UVISOR_BITS_CHECK(public_box, UVISOR_RGW_SHARED, address, mask)
+
+/** Set the selected bits to 1 at the target address.
+ *
+ * Equivalent to: `*address |= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_SET(address, mask) \
+    UVISOR_BITS_SET(public_box, UVISOR_RGW_SHARED, address, mask)
+
+/** Clear the selected bits at the target address.
+ *
+ * Equivalent to: `*address &= ~mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_CLEAR(address, mask) \
+    UVISOR_BITS_CLEAR(public_box, UVISOR_RGW_SHARED, address, mask)
+
+/** Set the selected bits at the target address to the given value.
+ *
+ * Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @param value[in]    Value to write at the address location. Note: The value
+ *                     must be already shifted to the correct bit position
+ */
+#define SECURE_BITS_SET_VALUE(address, mask, value) \
+    UVISOR_BITS_SET_VALUE(public_box, UVISOR_RGW_SHARED, address, mask, value)
+
+/** Toggle the selected bits at the target address.
+ *
+ * Equivalent to: `*address ^= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_TOGGLE(address, mask) \
+    UVISOR_BITS_TOGGLE(public_box, UVISOR_RGW_SHARED, address, mask)
+
+#else
+
+/* Insecure fallback implementation. */
+
+/** Set the value at the target address.
+ *
+ * Equivalent to: `*address = value`.
+ * @param address[in]  Target address
+ * @param value[in]    Value to write at the address location.
+ */
+#define SECURE_WRITE(address, value) \
+    *(address) = (value)
+
+/** Get the value at the target address.
+ *
+ * @param address[in]  Target address
+ * @returns The value `*address`.
+ */
+#define SECURE_READ(address) \
+    (*(address))
+
+/** Get the selected bits at the target address.
+ *
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `*address & mask`.
+ */
+#define SECURE_BITS_GET(address, mask) \
+    (*(address) & (mask))
+
+/** Check the selected bits at the target address.
+ *
+ * @param address[in]  Address at which to check the bits
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `((*address & mask) == mask)`.
+ */
+#define SECURE_BITS_CHECK(address, mask) \
+    ((*(address) & (mask)) == (mask))
+
+/** Set the selected bits to 1 at the target address.
+ *
+ * Equivalent to: `*address |= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_SET(address, mask) \
+    *(address) |= (mask)
+
+/** Clear the selected bits at the target address.
+ *
+ * Equivalent to: `*address &= ~mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_CLEAR(address, mask) \
+    *(address) &= ~(mask)
+
+/** Set the selected bits at the target address to the given value.
+ *
+ * Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @param value[in]    Value to write at the address location. Note: The value
+ *                     must be already shifted to the correct bit position
+ */
+#define SECURE_BITS_SET_VALUE(address, mask, value) \
+    *(address) = (*(address) & ~(mask)) | ((value) & (mask))
+
+/** Toggle the selected bits at the target address.
+ *
+ * Equivalent to: `*address ^= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_TOGGLE(address, mask) \
+    *(address) ^= (mask)
+
+#endif
+
+#endif /* __CORE_CM_SECURE_ACCESS_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_sc000.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,1016 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_sc300.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,1903 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/mpu_armv7.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,191 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for ARMv7 MPU
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
+
+#define ARM_MPU_AP_NONE 0U 
+#define ARM_MPU_AP_PRIV 1U
+#define ARM_MPU_AP_URO  2U
+#define ARM_MPU_AP_FULL 3U
+#define ARM_MPU_AP_PRO  5U
+#define ARM_MPU_AP_RO   6U
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Region Attribut and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ((((DisableExec     ) << MPU_RASR_XN_Pos)     & MPU_RASR_XN_Msk)     | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)     & MPU_RASR_AP_Msk)     | \
+   (((TypeExtField    ) << MPU_RASR_TEX_Pos)    & MPU_RASR_TEX_Msk)    | \
+   (((IsShareable     ) << MPU_RASR_S_Pos)      & MPU_RASR_S_Msk)      | \
+   (((IsCacheable     ) << MPU_RASR_C_Pos)      & MPU_RASR_C_Msk)      | \
+   (((IsBufferable    ) << MPU_RASR_B_Pos)      & MPU_RASR_B_Msk)      | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)    & MPU_RASR_SRD_Msk)    | \
+   (((Size            ) << MPU_RASR_SIZE_Pos)   & MPU_RASR_SIZE_Msk)   | \
+   (MPU_RASR_ENABLE_Msk))
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct _ARM_MPU_Region_t {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    ARM_MPU_Load(table+MPU_TYPE_RALIASES, cnt-MPU_TYPE_RALIASES);
+  } else {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/mpu_armv8.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,323 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for ARMv8 MPU
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Pos) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct _ARM_MPU_Region_t {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(MPU->MAIR) / sizeof(MPU->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  MPU->MAIR[reg] = ((MPU->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    if ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      ARM_MPU_LoadEx(mpu, rnr + c, table + c, cnt - c);
+    } else {
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+    }
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/tz_context.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date:        21. September 2016
+ * $Revision:    V1.0
+ *
+ * Project:      TrustZone for ARMv8-M
+ * Title:        Context Management for ARMv8-M TrustZone
+ *
+ * Version 1.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+  
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

--- a/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,94 +0,0 @@
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
- *      Functions
- *---------------------------------------------------------------------------*/
-    .text
-    .global __v7_all_cache
-/*
- * __STATIC_ASM void __v7_all_cache(uint32_t op) {
- */
-__v7_all_cache:
-        .arm
-
-        PUSH    {R4-R11}
-
-        MRC     p15, 1, R6, c0, c0, 1      /* Read CLIDR */
-        ANDS    R3, R6, #0x07000000        /* Extract coherency level */
-        MOV     R3, R3, LSR #23            /* Total cache levels << 1 */
-        BEQ     Finished                   /* If 0, no need to clean */
-
-        MOV     R10, #0                    /* R10 holds current cache level << 1 */
-Loop1:  ADD     R2, R10, R10, LSR #1       /* R2 holds cache "Set" position */
-        MOV     R1, R6, LSR R2             /* Bottom 3 bits are the Cache-type for this level */
-        AND     R1, R1, #7                 /* Isolate those lower 3 bits */
-        CMP     R1, #2
-        BLT     Skip                       /* No cache or only instruction cache at this level */
-
-        MCR     p15, 2, R10, c0, c0, 0     /* Write the Cache Size selection register */
-        ISB                                /* ISB to sync the change to the CacheSizeID reg */
-        MRC     p15, 1, R1, c0, c0, 0      /* Reads current Cache Size ID register */
-        AND     R2, R1, #7                 /* Extract the line length field */
-        ADD     R2, R2, #4                 /* Add 4 for the line length offset (log2 16 bytes) */
-        LDR     R4, =0x3FF
-        ANDS    R4, R4, R1, LSR #3         /* R4 is the max number on the way size (right aligned) */
-        CLZ     R5, R4                     /* R5 is the bit position of the way size increment */
-        LDR     R7, =0x7FFF
-        ANDS    R7, R7, R1, LSR #13        /* R7 is the max number of the index size (right aligned) */
-
-Loop2:  MOV     R9, R4                     /* R9 working copy of the max way size (right aligned) */
-
-Loop3:  ORR     R11, R10, R9, LSL R5       /* Factor in the Way number and cache number into R11 */
-        ORR     R11, R11, R7, LSL R2       /* Factor in the Set number */
-        CMP     R0, #0
-        BNE     Dccsw
-        MCR     p15, 0, R11, c7, c6, 2     /* DCISW. Invalidate by Set/Way */
-        B       cont
-Dccsw:  CMP     R0, #1
-        BNE     Dccisw
-        MCR     p15, 0, R11, c7, c10, 2    /* DCCSW. Clean by Set/Way */
-        B       cont
-Dccisw: MCR     p15, 0, R11, c7, c14, 2    /* DCCISW, Clean and Invalidate by Set/Way */
-cont:   SUBS    R9, R9, #1                 /* Decrement the Way number */
-        BGE     Loop3
-        SUBS    R7, R7, #1                 /* Decrement the Set number */
-        BGE     Loop2
-Skip:   ADD     R10, R10, #2               /* increment the cache number */
-        CMP     R3, R10
-        BGT     Loop1
-
-Finished:
-        DSB
-        POP    {R4-R11}
-        BX     lr
-
-
-    .END
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/

--- a/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,97 +0,0 @@
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
- *      Functions
- *---------------------------------------------------------------------------*/
-    SECTION `.text`:CODE:NOROOT(2)
-    arm 
-    PUBLIC __v7_all_cache
-/*
- * __STATIC_ASM void __v7_all_cache(uint32_t op) {
- */
-
-__v7_all_cache:
-
-
-        PUSH    {R4-R11}
-
-        MRC     p15, 1, R6, c0, c0, 1      /* Read CLIDR */
-        ANDS    R3, R6, #0x07000000        /* Extract coherency level */
-        MOV     R3, R3, LSR #23            /* Total cache levels << 1 */
-        BEQ     Finished                   /* If 0, no need to clean */
-
-        MOV     R10, #0                    /* R10 holds current cache level << 1 */
-Loop1:  ADD     R2, R10, R10, LSR #1       /* R2 holds cache "Set" position */
-        MOV     R1, R6, LSR R2             /* Bottom 3 bits are the Cache-type for this level */
-        AND     R1, R1, #7                 /* Isolate those lower 3 bits */
-        CMP     R1, #2
-        BLT     Skip                       /* No cache or only instruction cache at this level */
-
-        MCR     p15, 2, R10, c0, c0, 0     /* Write the Cache Size selection register */
-        ISB                                /* ISB to sync the change to the CacheSizeID reg */
-        MRC     p15, 1, R1, c0, c0, 0      /* Reads current Cache Size ID register */
-        AND     R2, R1, #7                 /* Extract the line length field */
-        ADD     R2, R2, #4                 /* Add 4 for the line length offset (log2 16 bytes) */
-        LDR     R4, =0x3FF
-        ANDS    R4, R4, R1, LSR #3         /* R4 is the max number on the way size (right aligned) */
-        CLZ     R5, R4                     /* R5 is the bit position of the way size increment */
-        LDR     R7, =0x7FFF
-        ANDS    R7, R7, R1, LSR #13        /* R7 is the max number of the index size (right aligned) */
-
-Loop2:  MOV     R9, R4                     /* R9 working copy of the max way size (right aligned) */
-
-Loop3:  ORR     R11, R10, R9, LSL R5       /* Factor in the Way number and cache number into R11 */
-        ORR     R11, R11, R7, LSL R2       /* Factor in the Set number */
-        CMP     R0, #0
-        BNE     Dccsw
-        MCR     p15, 0, R11, c7, c6, 2     /* DCISW. Invalidate by Set/Way */
-        B       cont
-Dccsw:  CMP     R0, #1
-        BNE     Dccisw
-        MCR     p15, 0, R11, c7, c10, 2    /* DCCSW. Clean by Set/Way */
-        B       cont
-Dccisw: MCR     p15, 0, R11, c7, c14, 2    /* DCCISW, Clean and Invalidate by Set/Way */
-cont:   SUBS    R9, R9, #1                 /* Decrement the Way number */
-        BGE     Loop3
-        SUBS    R7, R7, #1                 /* Decrement the Set number */
-        BGE     Loop2
-Skip:   ADD     R10, R10, #2               /* increment the cache number */
-        CMP     R3, R10
-        BGT     Loop1
-
-Finished:
-        DSB
-        POP    {R4-R11}
-        BX     lr
-
-
-    END
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
- 

--- a/cmsis/TOOLCHAIN_IAR/cmain.S	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,101 +0,0 @@
-/**************************************************
- *
- * Part two of the system initialization code, contains C-level
- * initialization, thumb-2 only variant.
- *
- * $Revision: 59783 $
- *
- **************************************************/
-/* Copyright 2008-2017, IAR Systems AB.
-   This source code is the property of IAR Systems. The source code may only
-   be used together with the IAR Embedded Workbench. Redistribution and use
-   in source and binary forms, with or without modification, is permitted
-   provided that the following conditions are met:
-   - Redistributions of source code, in whole or in part, must retain the
-     above copyright notice, this list of conditions and the disclaimer below.
-   - IAR Systems name may not be used to endorse or promote products
-     derived from this software without specific prior written permission.
-
-   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-; --------------------------------------------------
-; Module ?cmain, C-level initialization.
-;
-
-
-        SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
-        SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
-
-        SECTION .text:CODE:NOROOT(2)
-
-        PUBLIC  __cmain
-        ;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
-        PUBLIC  ?main
-        EXTWEAK __iar_data_init3
-        EXTWEAK __iar_argc_argv
-        EXTERN  __low_level_init
-        EXTERN  __call_ctors
-        EXTERN  main
-        EXTERN  exit
-        EXTERN  __iar_dynamic_initialization
-        EXTERN mbed_sdk_init
-        EXTERN mbed_main
-        EXTERN SystemInit
-        
-        THUMB
-__cmain:
-?main:
-
-; Initialize segments.
-; __segment_init and __low_level_init are assumed to use the same
-; instruction set and to be reachable by BL from the ICODE segment
-; (it is safest to link them in segment ICODE).
-
-          FUNCALL __cmain, __low_level_init
-        bl      __low_level_init
-        cmp     r0,#0
-        beq     ?l1
-          FUNCALL __cmain, __iar_data_init3
-        bl      __iar_data_init3
-        MOVS    r0,#0             ;  No parameters
-        FUNCALL __cmain, mbed_sdk_init
-        BL      mbed_sdk_init
-        MOVS    r0,#0             ;  No parameters        
-          FUNCALL __cmain, __iar_dynamic_initialization
-        BL      __iar_dynamic_initialization   ; C++ dynamic initialization  
-
-?l1:
-        REQUIRE ?l3
-
-        SECTION .text:CODE:NOROOT(2)
-
-        PUBLIC  _main
-        PUBLIC _call_main
-        THUMB
-
-__iar_init$$done:                 ; Copy initialization is done
-
-?l3:
-_call_main:
-        MOVS    r0,#0             ;  No parameters  
-          FUNCALL __cmain, __iar_argc_argv
-        BL      __iar_argc_argv   ; Maybe setup command line
-
-        MOVS    r0,#0             ;  No parameters  
-          FUNCALL __cmain, mbed_main
-        BL      mbed_main
-
-          FUNCALL __cmain, main
-        BL      main
-_main:
-          FUNCALL __cmain, exit
-        BL      exit
-
-        END

--- a/cmsis/arm_math.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,7257 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_math.h
- * Description:  Public header file for CMSIS DSP Library
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * Introduction
-   * ------------
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * Using the Library
-   * ------------
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
-   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
-   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
-   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
-   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
-   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
-   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
-   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
-   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
-   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
-   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
-   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
-   * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
-   * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
-   * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
-   * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
-   * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
-   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
-   * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
-   * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
-   * 
-   *
-   * Examples
-   * --------
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * Toolchain Support
-   * ------------
-   *
-   * The library has been developed and tested with MDK-ARM version 5.14.0.0
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * Building the Library
-   * ------------
-   *
-   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
-   * - arm_cortexM_math.uvprojx
-   *
-   *
-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
-   *
-   * Pre-processor Macros
-   * ------------
-   *
-   * Each library project have differant pre-processor macros.
-   *
-   * - UNALIGNED_SUPPORT_DISABLE:
-   *
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_CMx:
-   *
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
-   * ARM_MATH_CM7 for building the library on cortex-M7.
-   *
-   * - ARM_MATH_ARMV8MxL:
-   *
-   * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
-   * on ARMv8M Mainline target.
-   *
-   * - __FPU_PRESENT:
-   *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
-   *
-   * - __DSP_PRESENT:
-   *
-   * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
-   *
-   * <hr>
-   * CMSIS-DSP in ARM::CMSIS Pack
-   * -----------------------------
-   *
-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
-   * |File/Folder                   |Content                                                                 |
-   * |------------------------------|------------------------------------------------------------------------|
-   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
-   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
-   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
-   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
-   *
-   * <hr>
-   * Revision History of CMSIS-DSP
-   * ------------
-   * Please refer to \ref ChangeLog_pg.
-   *
-   * Copyright Notice
-   * ------------
-   *
-   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* Compiler specific diagnostic adjustment */
-#if   defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#else
-  #error Unknown compiler
-#endif
-
-
-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
-  #include "core_cm7.h"
-  #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM4)
-  #include "core_cm4.h"
-  #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM3)
-  #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-  #include "core_cm0.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
-  #include "core_cm0plus.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MBL)
-  #include "core_armv8mbl.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MML)
-  #include "core_armv8mml.h"
-  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
-    #define ARM_MATH_DSP
-  #endif
-#else
-  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
-#endif
-
-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31          (0x100)
-#define DELTA_Q15          0x5
-#define INDEX_MASK         0x0000003F
-#ifndef PI
-  #define PI               3.14159265358979f
-#endif
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define FAST_MATH_TABLE_SIZE  512
-#define FAST_MATH_Q31_SHIFT   (32 - 10)
-#define FAST_MATH_Q15_SHIFT   (16 - 10)
-#define CONTROLLER_Q31_SHIFT  (32 - 9)
-#define TABLE_SPACING_Q31     0x400000
-#define TABLE_SPACING_Q15     0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING         0xB60B61
-
-  /**
-   * @brief Macro for Unaligned Support
-   */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-    #define ALIGN4
-#else
-  #if defined  (__GNUC__)
-    #define ALIGN4 __attribute__((aligned(4)))
-  #else
-    #define ALIGN4 __align(4)
-  #endif
-#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-  {
-    ARM_MATH_SUCCESS = 0,                /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
-  } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief definition to read/write two 16 bit values.
-   */
-#if   defined ( __CC_ARM )
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __GNUC__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ICCARM__ )
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#elif defined ( __TI_ARM__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE
-
-#elif defined ( __CSMC__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#elif defined ( __TASKING__ )
-  #define __SIMD32_TYPE __unaligned int32_t
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#else
-  #error Unknown compiler
-#endif
-
-#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
-#define __SIMD64(addr)        (*(int64_t **) & (addr))
-
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
-                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
-                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-
-  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
-  q63_t x,
-  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-  }
-
-/*
-  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
-  #define __CLZ __clz
-  #endif
- */
-/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
-  CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
-  q31_t data);
-
-  CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
-  q31_t data)
-  {
-    uint32_t count = 0;
-    uint32_t mask = 0x80000000;
-
-    while ((data & mask) == 0)
-    {
-      count += 1u;
-      mask = mask >> 1u;
-    }
-
-    return (count);
-  }
-#endif
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
-   */
-
-  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
-  q31_t in,
-  q31_t * dst,
-  q31_t * pRecipTable)
-  {
-    q31_t out;
-    uint32_t tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if (in > 0)
-    {
-      signBits = ((uint32_t) (__CLZ( in) - 1));
-    }
-    else
-    {
-      signBits = ((uint32_t) (__CLZ(-in) - 1));
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >> 24);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++)
-    {
-      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
-      tempVal = 0x7FFFFFFFu - tempVal;
-      /*      1.31 with exp 1 */
-      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
-      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1u);
-  }
-
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
-  q15_t in,
-  q15_t * dst,
-  q15_t * pRecipTable)
-  {
-    q15_t out = 0;
-    uint32_t tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if (in > 0)
-    {
-      signBits = ((uint32_t)(__CLZ( in) - 17));
-    }
-    else
-    {
-      signBits = ((uint32_t)(__CLZ(-in) - 17));
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >>  8);
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++)
-    {
-      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
-      tempVal = 0x7FFFu - tempVal;
-      /*      1.15 with exp 1 */
-      out = (q15_t) (((q31_t) out * tempVal) >> 14);
-      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-  }
-
-
-  /*
-   * @brief C custom defined intrinisic function for only M0 processors
-   */
-#if defined(ARM_MATH_CM0_FAMILY)
-  CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
-  q31_t x,
-  uint32_t y)
-  {
-    int32_t posMax, negMin;
-    uint32_t i;
-
-    posMax = 1;
-    for (i = 0; i < (y - 1); i++)
-    {
-      posMax = posMax * 2;
-    }
-
-    if (x > 0)
-    {
-      posMax = (posMax - 1);
-
-      if (x > posMax)
-      {
-        x = posMax;
-      }
-    }
-    else
-    {
-      negMin = -posMax;
-
-      if (x < negMin)
-      {
-        x = negMin;
-      }
-    }
-    return (x);
-  }
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
-  /*
-   * @brief C custom defined intrinsic function for M3 and M0 processors
-   */
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
-
-  /*
-   * @brief C custom defined QADD8 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB8 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
-  uint32_t x,
-  uint32_t y)
-  {
-/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
-    q31_t r = 0, s = 0;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHADD16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHSUB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QASX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHASX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSAX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHSAX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SMUSDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-  }
-
-  /*
-   * @brief C custom defined SMUADX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined QADD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
-  int32_t x,
-  int32_t y)
-  {
-    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
-  int32_t x,
-  int32_t y)
-  {
-    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
-  }
-
-
-  /*
-   * @brief C custom defined SMLAD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLADX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLSDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLALD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
-  uint32_t x,
-  uint32_t y,
-  uint64_t sum)
-  {
-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLALDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
-  uint32_t x,
-  uint32_t y,
-  uint64_t sum)
-  {
-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMUAD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMUSD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined SXTB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
-  uint32_t x)
-  {
-    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
-                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
-  }
-
-  /*
-   * @brief C custom defined SMMLA for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
-  int32_t x,
-  int32_t y,
-  int32_t sum)
-  {
-    return (sum + (int32_t) (((int64_t) x * y) >> 32));
-  }
-
-#if 0
-  /*
-   * @brief C custom defined PKHBT for unavailable DSP extension
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
-  uint32_t x,
-  uint32_t y,
-  uint32_t leftshift)
-  {
-    return ( ((x             ) & 0x0000FFFFUL) |
-             ((y << leftshift) & 0xFFFF0000UL)  );
-  }
-
-  /*
-   * @brief C custom defined PKHTB for unavailable DSP extension
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
-  uint32_t x,
-  uint32_t y,
-  uint32_t rightshift)
-  {
-    return ( ((x              ) & 0xFFFF0000UL) |
-             ((y >> rightshift) & 0x0000FFFFUL)  );
-  }
-#endif
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] S          points to an instance of the Q7 FIR structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed.
-   */
-  void arm_fir_init_q7(
-  arm_fir_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in]  S          points to an instance of the Q15 FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
-   * <code>numTaps</code> is not a supported value.
-   */
-  arm_status arm_fir_init_q15(
-  arm_fir_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] S          points to an instance of the Q31 FIR structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   */
-  void arm_fir_init_q31(
-  arm_fir_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in]  S          points to an instance of the floating-point FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   */
-  void arm_fir_init_f32(
-  arm_fir_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
-  } arm_biquad_casd_df1_inst_q15;
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_casd_df1_inst_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cascade_df1_init_q15(
-  arm_biquad_casd_df1_inst_q15 * S,
-  uint8_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cascade_df1_init_q31(
-  arm_biquad_casd_df1_inst_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df1_init_f32(
-  arm_biquad_casd_df1_inst_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float64_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f64;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-  } arm_matrix_instance_q31;
-
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]   pSrcA  points to the first input matrix structure
-   * @param[in]   pSrcB  points to the second input matrix structure
-   * @param[out]  pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point, complex, matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15, complex,  matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Q31, complex, matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]  pSrcA   points to the first input matrix structure
-   * @param[in]  pSrcB   points to the second input matrix structure
-   * @param[out] pDst    points to output matrix structure
-   * @param[in]  pState  points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA   points to the first input matrix structure
-   * @param[in]  pSrcB   points to the second input matrix structure
-   * @param[out] pDst    points to output matrix structure
-   * @param[in]  pState  points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  pSrc   points to the input matrix
-   * @param[in]  scale  scale factor
-   * @param[out] pDst   points to the output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  float32_t scale,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]  pSrc        points to input matrix
-   * @param[in]  scaleFract  fractional portion of the scale factor
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  q15_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]  pSrc        points to input matrix
-   * @param[in]  scaleFract  fractional portion of the scale factor
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  q31_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_q31(
-  arm_matrix_instance_q31 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q31_t * pData);
-
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_q15(
-  arm_matrix_instance_q15 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q15_t * pData);
-
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_f32(
-  arm_matrix_instance_f32 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  float32_t * pData);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
-#if !defined (ARM_MATH_DSP)
-    q15_t A1;
-    q15_t A2;
-#else
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-    q15_t state[3];     /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;          /**< The proportional gain. */
-    float32_t Ki;          /**< The integral gain. */
-    float32_t Kd;          /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] S               points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_f32(
-  arm_pid_instance_f32 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] S  is an instance of the floating-point PID Control structure
-   */
-  void arm_pid_reset_f32(
-  arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] S               points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_q31(
-  arm_pid_instance_q31 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] S   points to an instance of the Q31 PID Control structure
-   */
-
-  void arm_pid_reset_q31(
-  arm_pid_instance_q31 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] S               points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_q15(
-  arm_pid_instance_q15 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] S  points to an instance of the q15 PID Control structure
-   */
-  void arm_pid_reset_q15(
-  arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-    uint32_t nValues;           /**< nValues */
-    float32_t x1;               /**< x1 */
-    float32_t xSpacing;         /**< xSpacing */
-    float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    float32_t *pData;   /**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q31_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q15_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q7_t *pData;        /**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q15(
-  arm_cfft_radix2_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-  q15_t * pSrc);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q15(
-  arm_cfft_radix4_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-  q15_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q31(
-  arm_cfft_radix2_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q31(
-  const arm_cfft_radix2_instance_q31 * S,
-  q31_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
-  void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-  q31_t * pSrc);
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q31(
-  arm_cfft_radix4_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-  } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_f32(
-  arm_cfft_radix2_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_f32(
-  const arm_cfft_radix2_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_f32(
-  arm_cfft_radix4_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_f32(
-  const arm_cfft_radix4_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q15;
-
-void arm_cfft_q15(
-    const arm_cfft_instance_q15 * S,
-    q15_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q31;
-
-void arm_cfft_q31(
-    const arm_cfft_instance_q31 * S,
-    q31_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_f32;
-
-  void arm_cfft_f32(
-  const arm_cfft_instance_f32 * S,
-  float32_t * p1,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q15;
-
-  arm_status arm_rfft_init_q15(
-  arm_rfft_instance_q15 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q15(
-  const arm_rfft_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst);
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q31;
-
-  arm_status arm_rfft_init_q31(
-  arm_rfft_instance_q31 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q31(
-  const arm_rfft_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  arm_status arm_rfft_init_f32(
-  arm_rfft_instance_f32 * S,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-typedef struct
-  {
-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
-    uint16_t fftLenRFFT;             /**< length of the real sequence */
-    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
-  } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
-   arm_rfft_fast_instance_f32 * S,
-   uint16_t fftLen);
-
-void arm_rfft_fast_f32(
-  arm_rfft_fast_instance_f32 * S,
-  float32_t * p, float32_t * pOut,
-  uint8_t ifftFlag);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    float32_t normalize;                 /**< normalizing factor. */
-    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    float32_t *pCosFactor;               /**< points to the cosFactor table. */
-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_f32(
-  arm_dct4_instance_f32 * S,
-  arm_rfft_instance_f32 * S_RFFT,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  float32_t normalize);
-
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-  float32_t * pState,
-  float32_t * pInlineBuffer);
-
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q31_t normalize;                     /**< normalizing factor. */
-    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
-    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_q31(
-  arm_dct4_instance_q31 * S,
-  arm_rfft_instance_q31 * S_RFFT,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q31_t normalize);
-
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-  q31_t * pState,
-  q31_t * pInlineBuffer);
-
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q15_t normalize;                     /**< normalizing factor. */
-    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
-    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_q15(
-  arm_dct4_instance_q15 * S,
-  arm_rfft_instance_q15 * S_RFFT,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q15_t normalize);
-
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-  q15_t * pState,
-  q15_t * pInlineBuffer);
-
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  scale      scale factor to be applied
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_scale_f32(
-  float32_t * pSrc,
-  float32_t scale,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q7(
-  q7_t * pSrc,
-  q7_t scaleFract,
-  int8_t shift,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q15(
-  q15_t * pSrc,
-  q15_t scaleFract,
-  int8_t shift,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q31(
-  q31_t * pSrc,
-  q31_t scaleFract,
-  int8_t shift,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t blockSize,
-  float32_t * result);
-
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  uint32_t blockSize,
-  q31_t * result);
-
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q7(
-  q7_t * pSrc,
-  int8_t shiftBits,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q15(
-  q15_t * pSrc,
-  int8_t shiftBits,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q31(
-  q31_t * pSrc,
-  int8_t shiftBits,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_f32(
-  float32_t * pSrc,
-  float32_t offset,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q7(
-  q7_t * pSrc,
-  q7_t offset,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q15(
-  q15_t * pSrc,
-  q15_t offset,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q31(
-  q31_t * pSrc,
-  q31_t offset,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a floating-point vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q7 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q15 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q31 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a floating-point vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_f32(
-  float32_t value,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q7(
-  q7_t value,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q15(
-  q15_t value,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q31(
-  q31_t value,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-  void arm_conv_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
-   */
-  void arm_conv_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-  void arm_conv_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_fast_q15(
-          q15_t * pSrcA,
-          uint32_t srcALen,
-          q15_t * pSrcB,
-          uint32_t srcBLen,
-          q15_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
-   */
-  void arm_conv_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-    /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   */
-  void arm_conv_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q7 sequences
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point FIR decimator.
-   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR decimator.
-   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_f32(
-  arm_fir_decimate_instance_f32 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_q15(
-  arm_fir_decimate_instance_q15 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
-   * @param[in]  pSrc  points to the block of input data.
-   * @param[out] pDst  points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   */
-  void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_fast_q31(
-  arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_q31(
-  arm_fir_decimate_instance_q31 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_q15(
-  arm_fir_interpolate_instance_q15 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_q31(
-  arm_fir_interpolate_instance_q31 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_f32(
-  arm_fir_interpolate_instance_f32 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cas_df1_32x64_init_q31(
-  arm_biquad_cas_df1_32x64_ins_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q63_t * pState,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_stereo_df2T_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f64;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df2T_f32(
-  const arm_biquad_cascade_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_stereo_df2T_f32(
-  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df2T_f64(
-  const arm_biquad_cascade_df2T_instance_f64 * S,
-  float64_t * pSrc,
-  float64_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df2T_init_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_stereo_df2T_init_f32(
-  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df2T_init_f64(
-  arm_biquad_cascade_df2T_instance_f64 * S,
-  uint8_t numStages,
-  float64_t * pCoeffs,
-  float64_t * pState);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages.
-   */
-  void arm_fir_lattice_init_q15(
-  arm_fir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] pState     points to the state buffer.   The array is of length numStages.
-   */
-  void arm_fir_lattice_init_q31(
-  arm_fir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S          points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.  The array is of length numStages.
- */
-  void arm_fir_lattice_init_f32(
-  arm_fir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages  number of stages in the filter.
-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_init_f32(
-  arm_iir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pkCoeffs,
-  float32_t * pvCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages  number of stages in the filter.
-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_init_q31(
-  arm_iir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pkCoeffs,
-  q31_t * pvCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize  number of samples to process per call.
- */
-  void arm_iir_lattice_init_q15(
-  arm_iir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pkCoeffs,
-  q15_t * pvCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] S          points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to the coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_lms_init_f32(
-  arm_lms_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] S          points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to the coefficient buffer.
-   * @param[in] pState     points to the state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_init_q15(
-  arm_lms_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q31;
-
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] S          points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_init_q31(
-  arm_lms_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;         /**< step size that control filter coefficient updates. */
-    float32_t energy;     /**< saves previous frame energy. */
-    float32_t x0;         /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_f32(
-  arm_lms_norm_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] S          points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_lms_norm_init_f32(
-  arm_lms_norm_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_q31(
-  arm_lms_norm_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_norm_init_q31(
-  arm_lms_norm_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< Number of coefficients in the filter. */
-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
-    q15_t energy;         /**< saves previous frame energy. */
-    q15_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_q15(
-  arm_lms_norm_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_norm_init_q15(
-  arm_lms_norm_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-   /**
-   * @brief Correlation of Q15 sequences
-   * @param[in]  pSrcA     points to the first input sequence.
-   * @param[in]  srcALen   length of the first input sequence.
-   * @param[in]  pSrcB     points to the second input sequence.
-   * @param[in]  srcBLen   length of the second input sequence.
-   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   */
-  void arm_correlate_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q15 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-
-  void arm_correlate_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-
-  void arm_correlate_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in]  pSrcA     points to the first input sequence.
-   * @param[in]  srcALen   length of the first input sequence.
-   * @param[in]  pSrcB     points to the second input sequence.
-   * @param[in]  srcBLen   length of the second input sequence.
-   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   */
-  void arm_correlate_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
- /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   */
-  void arm_correlate_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  pSrc        points to the block of input data.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   */
-  void arm_fir_sparse_f32(
-  arm_fir_sparse_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  float32_t * pScratchIn,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_f32(
-  arm_fir_sparse_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  pSrc        points to the block of input data.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   */
-  void arm_fir_sparse_q31(
-  arm_fir_sparse_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  q31_t * pScratchIn,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q31(
-  arm_fir_sparse_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  pSrc         points to the block of input data.
-   * @param[out] pDst         points to the block of output data
-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   */
-  void arm_fir_sparse_q15(
-  arm_fir_sparse_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  q15_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q15(
-  arm_fir_sparse_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  pSrc         points to the block of input data.
-   * @param[out] pDst         points to the block of output data
-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   */
-  void arm_fir_sparse_q7(
-  arm_fir_sparse_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  q7_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q7(
-  arm_fir_sparse_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta   input value in degrees
-   * @param[out] pSinVal  points to the processed sine output.
-   * @param[out] pCosVal  points to the processed cos output.
-   */
-  void arm_sin_cos_f32(
-  float32_t theta,
-  float32_t * pSinVal,
-  float32_t * pCosVal);
-
-
-  /**
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees
-   * @param[out] pSinVal  points to the processed sine output.
-   * @param[out] pCosVal  points to the processed cosine output.
-   */
-  void arm_sin_cos_q31(
-  q31_t theta,
-  q31_t * pSinVal,
-  q31_t * pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * <pre>
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  </pre>
-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   *
-   * \par
-   * \image html PID.gif "Proportional Integral Derivative Controller"
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.
-   * The proportional value determines the reaction to the current error,
-   * the integral value determines the reaction based on the sum of recent errors,
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
-   * A separate instance structure must be defined for each PID Controller.
-   * There are separate instance structure declarations for each of the 3 supported data types.
-   *
-   * \par Reset Functions
-   * There is also an associated reset function for each data type which clears the state array.
-   *
-   * \par Initialization Functions
-   * There is also an associated initialization function for each data type.
-   * The initialization function performs the following operations:
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.
-   *
-   * \par
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
-   *
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the fixed-point versions of the PID Controller functions.
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point PID Control.
-   * @param[in,out] S   is an instance of the floating-point PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
-  arm_pid_instance_f32 * S,
-  float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q31 PID Control.
-   * @param[in,out] S  points to an instance of the Q31 PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 64-bit accumulator.
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
-   * Thus, if the accumulator result overflows it wraps around rather than clip.
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
-  arm_pid_instance_q31 * S,
-  q31_t in)
-  {
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31u);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-  }
-
-
-  /**
-   * @brief  Process function for the Q15 PID Control.
-   * @param[in,out] S   points to an instance of the Q15 PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using a 64-bit internal accumulator.
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
-  arm_pid_instance_q15 * S,
-  q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-#if defined (ARM_MATH_DSP)
-    __SIMD32_TYPE *vstate;
-
-    /* Implementation of PID controller */
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    vstate = __SIMD32_CONST(S->state);
-    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
-#else
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-  }
-
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  src   points to the instance of the input floating-point matrix structure.
-   * @param[out] dst   points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-  arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * src,
-  arm_matrix_instance_f32 * dst);
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  src   points to the instance of the input floating-point matrix structure.
-   * @param[out] dst   points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-  arm_status arm_mat_inverse_f64(
-  const arm_matrix_instance_f64 * src,
-  arm_matrix_instance_f64 * dst);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]  Ia       input three-phase coordinate <code>a</code>
-   * @param[in]  Ib       input three-phase coordinate <code>b</code>
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
-  float32_t Ia,
-  float32_t Ib,
-  float32_t * pIalpha,
-  float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-  }
-
-
-  /**
-   * @brief  Clarke transform for Q31 version
-   * @param[in]  Ia       input three-phase coordinate <code>a</code>
-   * @param[in]  Ib       input three-phase coordinate <code>b</code>
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
-  q31_t Ia,
-  q31_t Ib,
-  q31_t * pIalpha,
-  q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_q7_to_q31(
-  q7_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pIa,
-  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
-  }
-
-
-  /**
-   * @brief  Inverse Clarke transform for Q31 version
-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the subtraction, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pIa,
-  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_q7_to_q15(
-  q7_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
-   * from the stationary to the moving reference frame and control the spatial relationship between
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]  Ialpha  input two-phase vector coordinate alpha
-   * @param[in]  Ibeta   input two-phase vector coordinate beta
-   * @param[out] pId     points to output   rotor reference frame d
-   * @param[out] pIq     points to output   rotor reference frame q
-   * @param[in]  sinVal  sine value of rotation angle theta
-   * @param[in]  cosVal  cosine value of rotation angle theta
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pId,
-  float32_t * pIq,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-  }
-
-
-  /**
-   * @brief  Park transform for Q31 version
-   * @param[in]  Ialpha  input two-phase vector coordinate alpha
-   * @param[in]  Ibeta   input two-phase vector coordinate beta
-   * @param[out] pId     points to output rotor reference frame d
-   * @param[out] pIq     points to output rotor reference frame q
-   * @param[in]  sinVal  sine value of rotation angle theta
-   * @param[in]  cosVal  cosine value of rotation angle theta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pId,
-  q31_t * pIq,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q7_to_float(
-  q7_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]  Id       input coordinate of rotor reference frame d
-   * @param[in]  Iq       input coordinate of rotor reference frame q
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]  sinVal   sine value of rotation angle theta
-   * @param[in]  cosVal   cosine value of rotation angle theta
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
-  float32_t Id,
-  float32_t Iq,
-  float32_t * pIalpha,
-  float32_t * pIbeta,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-  }
-
-
-  /**
-   * @brief  Inverse Park transform for   Q31 version
-   * @param[in]  Id       input coordinate of rotor reference frame d
-   * @param[in]  Iq       input coordinate of rotor reference frame q
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]  sinVal   sine value of rotation angle theta
-   * @param[in]  cosVal   cosine value of rotation angle theta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
-  q31_t Id,
-  q31_t Iq,
-  q31_t * pIalpha,
-  q31_t * pIbeta,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_float(
-  q31_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * <pre>
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * </pre>
-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
-   * <code>x</code> is the input sample value. The functions returns the output value.
-   *
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table
-   * if x is below input range and returns last value of table if x is above range.
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
-   * @param[in]     x  input sample to process
-   * @return y processed output sample.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
-  arm_linear_interp_instance_f32 * S,
-  float32_t x)
-  {
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t *pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (int32_t) ((x - S->x1) / xSpacing);
-
-    if (i < 0)
-    {
-      /* Iniatilize output for below specified range as least output value of table */
-      y = pYData[0];
-    }
-    else if ((uint32_t)i >= S->nValues)
-    {
-      /* Iniatilize output for above specified range as last output value of table */
-      y = pYData[S->nValues - 1];
-    }
-    else
-    {
-      /* Calculation of nearest input values */
-      x0 = S->x1 +  i      * xSpacing;
-      x1 = S->x1 + (i + 1) * xSpacing;
-
-      /* Read of nearest output values */
-      y0 = pYData[i];
-      y1 = pYData[i + 1];
-
-      /* Calculation of output */
-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-  }
-
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q31 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
-  q31_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (q31_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if (index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* shift left by 11 to keep fract in 1.31 format */
-      fract = (x & 0x000FFFFF) << 11;
-
-      /* Read two nearest output values from the index in 1.31(q31) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-      /* Convert y to 1.31 format */
-      return (y << 1u);
-    }
-  }
-
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q15 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
-  q15_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (int32_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if (index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-      y = ((q63_t) y0 * (0xFFFFF - fract));
-
-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-      y += ((q63_t) y1 * (fract));
-
-      /* convert y to 1.15 format */
-      return (q15_t) (y >> 20);
-    }
-  }
-
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q7 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
-  q7_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    uint32_t index;                              /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    if (x < 0)
-    {
-      return (pYData[0]);
-    }
-    index = (x >> 20) & 0xfff;
-
-    if (index >= (nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index and are in 1.7(q7) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-      y = ((y0 * (0xFFFFF - fract)));
-
-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-      y += (y1 * fract);
-
-      /* convert y to 1.7(q7) format */
-      return (q7_t) (y >> 20);
-     }
-  }
-
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x  input value in radians.
-   * @return  sin(x).
-   */
-  float32_t arm_sin_f32(
-  float32_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  sin(x).
-   */
-  q31_t arm_sin_q31(
-  q31_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  sin(x).
-   */
-  q15_t arm_sin_q15(
-  q15_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x  input value in radians.
-   * @return  cos(x).
-   */
-  float32_t arm_cos_f32(
-  float32_t x);
-
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  cos(x).
-   */
-  q31_t arm_cos_q31(
-  q31_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  cos(x).
-   */
-  q15_t arm_cos_q15(
-  q15_t x);
-
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * <pre>
-   *      x1 = x0 - f(x0)/f'(x0)
-   * </pre>
-   * where <code>x1</code> is the current estimate,
-   * <code>x0</code> is the previous estimate, and
-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
-   * For the square root function, the algorithm reduces to:
-   * <pre>
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * </pre>
-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-  /**
-   * @brief  Floating-point square root function.
-   * @param[in]  in    input value.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
-  float32_t in,
-  float32_t * pOut)
-  {
-    if (in >= 0.0f)
-    {
-
-#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
-      *pOut = __sqrtf(in);
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-      *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined(__GNUC__)
-      *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
-      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
-#else
-      *pOut = sqrtf(in);
-#endif
-
-      return (ARM_MATH_SUCCESS);
-    }
-    else
-    {
-      *pOut = 0.0f;
-      return (ARM_MATH_ARGUMENT_ERROR);
-    }
-  }
-
-
-  /**
-   * @brief Q31 square root function.
-   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut);
-
-
-  /**
-   * @brief  Q15 square root function.
-   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const int32_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  int32_t * dst,
-  int32_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (int32_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value  */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q15_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q15_t * dst,
-  q15_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (q15_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q7_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q7_t * dst,
-  q7_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (q7_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t numSamples,
-  q31_t * realResult,
-  q31_t * imagResult);
-
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t numSamples,
-  q63_t * realResult,
-  q63_t * imagResult);
-
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t numSamples,
-  float32_t * realResult,
-  float32_t * imagResult);
-
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_q15(
-  q15_t * pSrcCmplx,
-  q15_t * pSrcReal,
-  q15_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_q31(
-  q31_t * pSrcCmplx,
-  q31_t * pSrcReal,
-  q31_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_f32(
-  float32_t * pSrcCmplx,
-  float32_t * pSrcReal,
-  float32_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] result     is output pointer
-   * @param[in]  index      is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * result,
-  uint32_t * index);
-
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q31 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q31(
-  float32_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q15 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q15(
-  float32_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q7 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q7(
-  float32_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_q15(
-  q31_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_q7(
-  q31_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_float(
-  q15_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_q31(
-  q15_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_q7(
-  q15_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * <b>Algorithm</b>
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * <pre>
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * </pre>
-   *
-   * \par
-   * where <code>numRows</code> specifies the number of rows in the table;
-   * <code>numCols</code> specifies the number of columns in the table;
-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
-   *
-   * \par
-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
-   * <pre>
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * </pre>
-   * \par
-   * The interpolated output point is computed as:
-   * <pre>
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * </pre>
-   * Note that the coordinates (x, y) contain integer and fractional components.
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
-   */
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-
-  /**
-  *
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate.
-  * @param[in]     Y  interpolation coordinate.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
-  const arm_bilinear_interp_instance_f32 * S,
-  float32_t X,
-  float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-  }
-
-
-  /**
-  *
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
-  arm_bilinear_interp_instance_q31 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
-    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
-    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return ((q31_t)(acc << 2));
-  }
-
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
-  arm_bilinear_interp_instance_q15 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return ((q15_t)(acc >> 36));
-  }
-
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
-  arm_bilinear_interp_instance_q7 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return ((q7_t)(acc >> 40));
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
-    a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
-    a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
-    a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if   defined ( __CC_ARM )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("push")         \
-       _Pragma ("O1")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define LOW_OPTIMIZATION_EXIT \
-       _Pragma ("pop")
-  #else
-    #define LOW_OPTIMIZATION_EXIT
-  #endif
-
-  /* Enter low optimization region - place directly above function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
-  #define LOW_OPTIMIZATION_ENTER \
-       __attribute__(( optimize("-O1") ))
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define LOW_OPTIMIZATION_EXIT
-
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-/* Compiler specific diagnostic adjustment */
-#if   defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#else
-  #error Unknown compiler
-#endif
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */

--- a/cmsis/core_armv8mbl.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1876 +0,0 @@
-/**************************************************************************//**
- * @file     core_armv8mbl.h
- * @brief    CMSIS ARMv8MBL Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MBL_H_GENERIC
-#define __CORE_ARMV8MBL_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_ARMv8MBL
-  @{
- */
-
-/*  CMSIS cmGrebe definitions */
-#define __ARMv8MBL_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
-#define __ARMv8MBL_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
-                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MBL_H_DEPENDANT
-#define __CORE_ARMV8MBL_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __ARMv8MBL_REV
-    #define __ARMv8MBL_REV               0x0000U
-    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-
-  #ifndef __ETM_PRESENT
-    #define __ETM_PRESENT             0U
-    #warning "__ETM_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MTB_PRESENT
-    #define __MTB_PRESENT             0U
-    #warning "__MTB_PRESENT not defined in device header file; using default!"
-  #endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MBL */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-        uint32_t RESERVED0;
-#endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-        uint32_t RESERVED0[6U];
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-        uint32_t RESERVED0[7U];
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for ARMv8-M Baseline */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for ARMv8-M Baseline */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_armv8mml.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2900 +0,0 @@
-/**************************************************************************//**
- * @file     core_armv8mml.h
- * @brief    CMSIS ARMv8MML Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MML_H_GENERIC
-#define __CORE_ARMV8MML_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_ARMv8MML
-  @{
- */
-
-/*  CMSIS ARMv8MML definitions */
-#define __ARMv8MML_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
-#define __ARMv8MML_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
-                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MML_H_DEPENDANT
-#define __CORE_ARMV8MML_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __ARMv8MML_REV
-    #define __ARMv8MML_REV               0x0000U
-    #warning "__ARMv8MML_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DSP_PRESENT
-    #define __DSP_PRESENT             0U
-    #warning "__DSP_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MML */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
-    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
-    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED6[580U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-        uint32_t RESERVED4[15U];
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
-        uint32_t RESERVED5[1U];
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-        uint32_t RESERVED6[1U];
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-        uint32_t RESERVED7[6U];
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
-        uint32_t RESERVED6[4U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-        uint32_t RESERVED32[934U];
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-        uint32_t RESERVED33[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
-  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
-  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
-  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
-        uint32_t RESERVED0[1];
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#else
-        uint32_t RESERVED0[3];
-#endif
-  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
-  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
-  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
-  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Set Priority Grouping (non-secure)
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB_NS->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping (non-secure)
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
-  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = FPU->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
-  {
-    return 2U;           /* Double + Single precision FPU */
-  }
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_ca.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2016 +0,0 @@
-/**************************************************************************//**
- * @file     core_ca.h
- * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File
- * @version  V1.00
- * @date     22. Feb 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CA_H_GENERIC
-#define __CORE_CA_H_GENERIC
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-
-/*  CMSIS CA definitions */
-#define __CA_CMSIS_VERSION_MAIN  (1U)                                      /*!< \brief [31:16] CMSIS HAL main version   */
-#define __CA_CMSIS_VERSION_SUB   (0U)                                      /*!< \brief [15:0]  CMSIS HAL sub version    */
-#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CA_CMSIS_VERSION_SUB          )       /*!< \brief CMSIS HAL version number         */
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CA_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CA_H_DEPENDANT
-#define __CORE_CA_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
- /* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CA_REV
-    #define __CA_REV              0x0000U
-    #warning "__CA_REV not defined in device header file; using default!"
-  #endif
-  
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-  
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-  
-  #ifndef __GIC_PRESENT
-    #define __GIC_PRESENT             1U
-    #warning "__GIC_PRESENT not defined in device header file; using default!"
-  #endif
-  
-  #ifndef __TIM_PRESENT
-    #define __TIM_PRESENT             1U
-    #warning "__TIM_PRESENT not defined in device header file; using default!"
-  #endif
-  
-  #ifndef __L2C_PRESENT
-    #define __L2C_PRESENT             0U
-    #warning "__L2C_PRESENT not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< \brief Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< \brief Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< \brief Defines 'write only' permissions */
-#define     __IO    volatile             /*!< \brief Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*!< \brief Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*!< \brief Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*!< \brief Defines 'read / write' structure member permissions */
-
-
- /*******************************************************************************
-  *                 Register Abstraction
-   Core Register contain:
-   - CPSR
-   - CP15 Registers
-   - L2C-310 Cache Controller
-   - Generic Interrupt Controller Distributor
-   - Generic Interrupt Controller Interface
-  ******************************************************************************/
-
-/* Core Register CPSR */
-typedef union
-{
-  struct
-  {
-    uint32_t M:5;                        /*!< \brief bit:  0.. 4  Mode field */
-    uint32_t T:1;                        /*!< \brief bit:      5  Thumb execution state bit */
-    uint32_t F:1;                        /*!< \brief bit:      6  FIQ mask bit */
-    uint32_t I:1;                        /*!< \brief bit:      7  IRQ mask bit */
-    uint32_t A:1;                        /*!< \brief bit:      8  Asynchronous abort mask bit */
-    uint32_t E:1;                        /*!< \brief bit:      9  Endianness execution state bit */
-    uint32_t IT1:6;                      /*!< \brief bit: 10..15  If-Then execution state bits 2-7 */
-    uint32_t GE:4;                       /*!< \brief bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved0:4;               /*!< \brief bit: 20..23  Reserved */
-    uint32_t J:1;                        /*!< \brief bit:     24  Jazelle bit */
-    uint32_t IT0:2;                      /*!< \brief bit: 25..26  If-Then execution state bits 0-1 */
-    uint32_t Q:1;                        /*!< \brief bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< \brief bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< \brief bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< \brief bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< \brief bit:     31  Negative condition code flag */
-  } b;                                   /*!< \brief Structure used for bit  access */
-  uint32_t w;                            /*!< \brief Type      used for word access */
-} CPSR_Type;
-
-/* CPSR Register Definitions */
-#define CPSR_N_Pos                       31U                                    /*!< \brief CPSR: N Position */
-#define CPSR_N_Msk                       (1UL << CPSR_N_Pos)                    /*!< \brief CPSR: N Mask */
-
-#define CPSR_Z_Pos                       30U                                    /*!< \brief CPSR: Z Position */
-#define CPSR_Z_Msk                       (1UL << CPSR_Z_Pos)                    /*!< \brief CPSR: Z Mask */
-
-#define CPSR_C_Pos                       29U                                    /*!< \brief CPSR: C Position */
-#define CPSR_C_Msk                       (1UL << CPSR_C_Pos)                    /*!< \brief CPSR: C Mask */
-
-#define CPSR_V_Pos                       28U                                    /*!< \brief CPSR: V Position */
-#define CPSR_V_Msk                       (1UL << CPSR_V_Pos)                    /*!< \brief CPSR: V Mask */
-
-#define CPSR_Q_Pos                       27U                                    /*!< \brief CPSR: Q Position */
-#define CPSR_Q_Msk                       (1UL << CPSR_Q_Pos)                    /*!< \brief CPSR: Q Mask */
-
-#define CPSR_IT0_Pos                     25U                                    /*!< \brief CPSR: IT0 Position */
-#define CPSR_IT0_Msk                     (3UL << CPSR_IT0_Pos)                  /*!< \brief CPSR: IT0 Mask */
-
-#define CPSR_J_Pos                       24U                                    /*!< \brief CPSR: J Position */
-#define CPSR_J_Msk                       (1UL << CPSR_J_Pos)                    /*!< \brief CPSR: J Mask */
-
-#define CPSR_GE_Pos                      16U                                    /*!< \brief CPSR: GE Position */
-#define CPSR_GE_Msk                      (0xFUL << CPSR_GE_Pos)                 /*!< \brief CPSR: GE Mask */
-
-#define CPSR_IT1_Pos                     10U                                    /*!< \brief CPSR: IT1 Position */
-#define CPSR_IT1_Msk                     (0x3FUL << CPSR_IT1_Pos)               /*!< \brief CPSR: IT1 Mask */
-
-#define CPSR_E_Pos                       9U                                     /*!< \brief CPSR: E Position */
-#define CPSR_E_Msk                       (1UL << CPSR_E_Pos)                    /*!< \brief CPSR: E Mask */
-
-#define CPSR_A_Pos                       8U                                     /*!< \brief CPSR: A Position */
-#define CPSR_A_Msk                       (1UL << CPSR_A_Pos)                    /*!< \brief CPSR: A Mask */
-
-#define CPSR_I_Pos                       7U                                     /*!< \brief CPSR: I Position */
-#define CPSR_I_Msk                       (1UL << CPSR_I_Pos)                    /*!< \brief CPSR: I Mask */
-
-#define CPSR_F_Pos                       6U                                     /*!< \brief CPSR: F Position */
-#define CPSR_F_Msk                       (1UL << CPSR_F_Pos)                    /*!< \brief CPSR: F Mask */
-
-#define CPSR_T_Pos                       5U                                     /*!< \brief CPSR: T Position */
-#define CPSR_T_Msk                       (1UL << CPSR_T_Pos)                    /*!< \brief CPSR: T Mask */
-
-#define CPSR_M_Pos                       0U                                     /*!< \brief CPSR: M Position */
-#define CPSR_M_Msk                       (0x1FUL << CPSR_M_Pos)                 /*!< \brief CPSR: M Mask */
-
-/* CP15 Register SCTLR */
-typedef union
-{
-  struct
-  {
-    uint32_t M:1;                        /*!< \brief bit:     0  MMU enable */
-    uint32_t A:1;                        /*!< \brief bit:     1  Alignment check enable */
-    uint32_t C:1;                        /*!< \brief bit:     2  Cache enable */
-    uint32_t _reserved0:2;               /*!< \brief bit: 3.. 4  Reserved */
-    uint32_t CP15BEN:1;                  /*!< \brief bit:     5  CP15 barrier enable */
-    uint32_t _reserved1:1;               /*!< \brief bit:     6  Reserved */
-    uint32_t B:1;                        /*!< \brief bit:     7  Endianness model */
-    uint32_t _reserved2:2;               /*!< \brief bit: 8.. 9  Reserved */
-    uint32_t SW:1;                       /*!< \brief bit:    10  SWP and SWPB enable */
-    uint32_t Z:1;                        /*!< \brief bit:    11  Branch prediction enable */
-    uint32_t I:1;                        /*!< \brief bit:    12  Instruction cache enable */
-    uint32_t V:1;                        /*!< \brief bit:    13  Vectors bit */
-    uint32_t RR:1;                       /*!< \brief bit:    14  Round Robin select */
-    uint32_t _reserved3:2;               /*!< \brief bit:15..16  Reserved */
-    uint32_t HA:1;                       /*!< \brief bit:    17  Hardware Access flag enable */
-    uint32_t _reserved4:1;               /*!< \brief bit:    18  Reserved */
-    uint32_t WXN:1;                      /*!< \brief bit:    19  Write permission implies XN */
-    uint32_t UWXN:1;                     /*!< \brief bit:    20  Unprivileged write permission implies PL1 XN */
-    uint32_t FI:1;                       /*!< \brief bit:    21  Fast interrupts configuration enable */
-    uint32_t U:1;                        /*!< \brief bit:    22  Alignment model */
-    uint32_t _reserved5:1;               /*!< \brief bit:    23  Reserved */
-    uint32_t VE:1;                       /*!< \brief bit:    24  Interrupt Vectors Enable */
-    uint32_t EE:1;                       /*!< \brief bit:    25  Exception Endianness */
-    uint32_t _reserved6:1;               /*!< \brief bit:    26  Reserved */
-    uint32_t NMFI:1;                     /*!< \brief bit:    27  Non-maskable FIQ (NMFI) support */
-    uint32_t TRE:1;                      /*!< \brief bit:    28  TEX remap enable. */
-    uint32_t AFE:1;                      /*!< \brief bit:    29  Access flag enable */
-    uint32_t TE:1;                       /*!< \brief bit:    30  Thumb Exception enable */
-    uint32_t _reserved7:1;               /*!< \brief bit:    31  Reserved */
-  } b;                                   /*!< \brief Structure used for bit  access */
-  uint32_t w;                            /*!< \brief Type      used for word access */
-} SCTLR_Type;
-
-#define SCTLR_TE_Pos                     30U                                    /*!< \brief SCTLR: TE Position */
-#define SCTLR_TE_Msk                     (1UL << SCTLR_TE_Pos)                  /*!< \brief SCTLR: TE Mask */
-
-#define SCTLR_AFE_Pos                    29U                                    /*!< \brief SCTLR: AFE Position */
-#define SCTLR_AFE_Msk                    (1UL << SCTLR_AFE_Pos)                 /*!< \brief SCTLR: AFE Mask */
-
-#define SCTLR_TRE_Pos                    28U                                    /*!< \brief SCTLR: TRE Position */
-#define SCTLR_TRE_Msk                    (1UL << SCTLR_TRE_Pos)                 /*!< \brief SCTLR: TRE Mask */
-
-#define SCTLR_NMFI_Pos                   27U                                    /*!< \brief SCTLR: NMFI Position */
-#define SCTLR_NMFI_Msk                   (1UL << SCTLR_NMFI_Pos)                /*!< \brief SCTLR: NMFI Mask */
-
-#define SCTLR_EE_Pos                     25U                                    /*!< \brief SCTLR: EE Position */
-#define SCTLR_EE_Msk                     (1UL << SCTLR_EE_Pos)                  /*!< \brief SCTLR: EE Mask */
-
-#define SCTLR_VE_Pos                     24U                                    /*!< \brief SCTLR: VE Position */
-#define SCTLR_VE_Msk                     (1UL << SCTLR_VE_Pos)                  /*!< \brief SCTLR: VE Mask */
-
-#define SCTLR_U_Pos                      22U                                    /*!< \brief SCTLR: U Position */
-#define SCTLR_U_Msk                      (1UL << SCTLR_U_Pos)                   /*!< \brief SCTLR: U Mask */
-
-#define SCTLR_FI_Pos                     21U                                    /*!< \brief SCTLR: FI Position */
-#define SCTLR_FI_Msk                     (1UL << SCTLR_FI_Pos)                  /*!< \brief SCTLR: FI Mask */
-
-#define SCTLR_UWXN_Pos                   20U                                    /*!< \brief SCTLR: UWXN Position */
-#define SCTLR_UWXN_Msk                   (1UL << SCTLR_UWXN_Pos)                /*!< \brief SCTLR: UWXN Mask */
-
-#define SCTLR_WXN_Pos                    19U                                    /*!< \brief SCTLR: WXN Position */
-#define SCTLR_WXN_Msk                    (1UL << SCTLR_WXN_Pos)                 /*!< \brief SCTLR: WXN Mask */
-
-#define SCTLR_HA_Pos                     17U                                    /*!< \brief SCTLR: HA Position */
-#define SCTLR_HA_Msk                     (1UL << SCTLR_HA_Pos)                  /*!< \brief SCTLR: HA Mask */
-
-#define SCTLR_RR_Pos                     14U                                    /*!< \brief SCTLR: RR Position */
-#define SCTLR_RR_Msk                     (1UL << SCTLR_RR_Pos)                  /*!< \brief SCTLR: RR Mask */
-
-#define SCTLR_V_Pos                      13U                                    /*!< \brief SCTLR: V Position */
-#define SCTLR_V_Msk                      (1UL << SCTLR_V_Pos)                   /*!< \brief SCTLR: V Mask */
-
-#define SCTLR_I_Pos                      12U                                    /*!< \brief SCTLR: I Position */
-#define SCTLR_I_Msk                      (1UL << SCTLR_I_Pos)                   /*!< \brief SCTLR: I Mask */
-
-#define SCTLR_Z_Pos                      11U                                    /*!< \brief SCTLR: Z Position */
-#define SCTLR_Z_Msk                      (1UL << SCTLR_Z_Pos)                   /*!< \brief SCTLR: Z Mask */
-
-#define SCTLR_SW_Pos                     10U                                    /*!< \brief SCTLR: SW Position */
-#define SCTLR_SW_Msk                     (1UL << SCTLR_SW_Pos)                  /*!< \brief SCTLR: SW Mask */
-
-#define SCTLR_B_Pos                      7U                                     /*!< \brief SCTLR: B Position */
-#define SCTLR_B_Msk                      (1UL << SCTLR_B_Pos)                   /*!< \brief SCTLR: B Mask */
-
-#define SCTLR_CP15BEN_Pos                5U                                     /*!< \brief SCTLR: CP15BEN Position */
-#define SCTLR_CP15BEN_Msk                (1UL << SCTLR_CP15BEN_Pos)             /*!< \brief SCTLR: CP15BEN Mask */
-
-#define SCTLR_C_Pos                      2U                                     /*!< \brief SCTLR: C Position */
-#define SCTLR_C_Msk                      (1UL << SCTLR_C_Pos)                   /*!< \brief SCTLR: C Mask */
-
-#define SCTLR_A_Pos                      1U                                     /*!< \brief SCTLR: A Position */
-#define SCTLR_A_Msk                      (1UL << SCTLR_A_Pos)                   /*!< \brief SCTLR: A Mask */
-
-#define SCTLR_M_Pos                      0U                                     /*!< \brief SCTLR: M Position */
-#define SCTLR_M_Msk                      (1UL << SCTLR_M_Pos)                   /*!< \brief SCTLR: M Mask */
-
-/* CP15 Register CPACR */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:20;              /*!< \brief bit: 0..19  Reserved */
-    uint32_t cp10:2;                     /*!< \brief bit:20..21  Access rights for coprocessor 10 */
-    uint32_t cp11:2;                     /*!< \brief bit:22..23  Access rights for coprocessor 11 */
-    uint32_t _reserved1:6;               /*!< \brief bit:24..29  Reserved */
-    uint32_t D32DIS:1;                   /*!< \brief bit:    30  Disable use of registers D16-D31 of the VFP register file */
-    uint32_t ASEDIS:1;                   /*!< \brief bit:    31  Disable Advanced SIMD Functionality */
-  } b;                                   /*!< \brief Structure used for bit  access */
-  uint32_t w;                            /*!< \brief Type      used for word access */
-} CPACR_Type;
-
-#define CPACR_ASEDIS_Pos                 31U                                    /*!< \brief CPACR: ASEDIS Position */
-#define CPACR_ASEDIS_Msk                 (1UL << CPACR_ASEDIS_Pos)              /*!< \brief CPACR: ASEDIS Mask */
-
-#define CPACR_D32DIS_Pos                 30U                                    /*!< \brief CPACR: D32DIS Position */
-#define CPACR_D32DIS_Msk                 (1UL << CPACR_D32DIS_Pos)              /*!< \brief CPACR: D32DIS Mask */
-
-#define CPACR_cp11_Pos                   22U                                    /*!< \brief CPACR: cp11 Position */
-#define CPACR_cp11_Msk                   (3UL << CPACR_cp11_Pos)                /*!< \brief CPACR: cp11 Mask */
-
-#define CPACR_cp10_Pos                   20U                                    /*!< \brief CPACR: cp10 Position */
-#define CPACR_cp10_Msk                   (3UL << CPACR_cp10_Pos)                /*!< \brief CPACR: cp10 Mask */
-
-/* CP15 Register DFSR */
-typedef union
-{
-  struct
-  {
-    uint32_t FS0:4;                      /*!< \brief bit: 0.. 3  Fault Status bits bit 0-3 */
-    uint32_t Domain:4;                   /*!< \brief bit: 4.. 7  Fault on which domain */
-    uint32_t _reserved0:2;               /*!< \brief bit: 8.. 9  Reserved */
-    uint32_t FS1:1;                      /*!< \brief bit:    10  Fault Status bits bit 4 */
-    uint32_t WnR:1;                      /*!< \brief bit:    11  Write not Read bit */
-    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
-    uint32_t CM:1;                       /*!< \brief bit:    13  Cache maintenance fault */
-    uint32_t _reserved1:18;              /*!< \brief bit:14..31  Reserved */
-  } b;                                   /*!< \brief Structure used for bit  access */
-  uint32_t w;                            /*!< \brief Type      used for word access */
-} DFSR_Type;
-
-#define DFSR_CM_Pos                      13U                                    /*!< \brief DFSR: CM Position */
-#define DFSR_CM_Msk                      (1UL << DFSR_CM_Pos)                   /*!< \brief DFSR: CM Mask */
-
-#define DFSR_Ext_Pos                     12U                                    /*!< \brief DFSR: Ext Position */
-#define DFSR_Ext_Msk                     (1UL << DFSR_Ext_Pos)                  /*!< \brief DFSR: Ext Mask */
-
-#define DFSR_WnR_Pos                     11U                                    /*!< \brief DFSR: WnR Position */
-#define DFSR_WnR_Msk                     (1UL << DFSR_WnR_Pos)                  /*!< \brief DFSR: WnR Mask */
-
-#define DFSR_FS1_Pos                     10U                                    /*!< \brief DFSR: FS1 Position */
-#define DFSR_FS1_Msk                     (1UL << DFSR_FS1_Pos)                  /*!< \brief DFSR: FS1 Mask */
-
-#define DFSR_Domain_Pos                  4U                                     /*!< \brief DFSR: Domain Position */
-#define DFSR_Domain_Msk                  (0xFUL << DFSR_Domain_Pos)             /*!< \brief DFSR: Domain Mask */
-
-#define DFSR_FS0_Pos                     0U                                     /*!< \brief DFSR: FS0 Position */
-#define DFSR_FS0_Msk                     (0xFUL << DFSR_FS0_Pos)                /*!< \brief DFSR: FS0 Mask */
-
-/* CP15 Register IFSR */
-typedef union
-{
-  struct
-  {
-    uint32_t FS0:4;                      /*!< \brief bit: 0.. 3  Fault Status bits bit 0-3 */
-    uint32_t _reserved0:6;               /*!< \brief bit: 4.. 9  Reserved */
-    uint32_t FS1:1;                      /*!< \brief bit:    10  Fault Status bits bit 4 */
-    uint32_t _reserved1:1;               /*!< \brief bit:    11  Reserved */
-    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
-    uint32_t _reserved2:19;              /*!< \brief bit:13..31  Reserved */
-  } b;                                   /*!< \brief Structure used for bit  access */
-  uint32_t w;                            /*!< \brief Type      used for word access */
-} IFSR_Type;
-
-#define IFSR_ExT_Pos                     12U                                    /*!< \brief IFSR: ExT Position */
-#define IFSR_ExT_Msk                     (1UL << IFSR_ExT_Pos)                  /*!< \brief IFSR: ExT Mask */
-
-#define IFSR_FS1_Pos                     10U                                    /*!< \brief IFSR: FS1 Position */
-#define IFSR_FS1_Msk                     (1UL << IFSR_FS1_Pos)                  /*!< \brief IFSR: FS1 Mask */
-
-#define IFSR_FS0_Pos                     0U                                     /*!< \brief IFSR: FS0 Position */
-#define IFSR_FS0_Msk                     (0xFUL << IFSR_FS0_Pos)                /*!< \brief IFSR: FS0 Mask */
-
-/* CP15 Register ISR */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:6;               /*!< \brief bit: 0.. 5  Reserved */
-    uint32_t F:1;                        /*!< \brief bit:     6  FIQ pending bit */
-    uint32_t I:1;                        /*!< \brief bit:     7  IRQ pending bit */
-    uint32_t A:1;                        /*!< \brief bit:     8  External abort pending bit */
-    uint32_t _reserved1:23;              /*!< \brief bit:14..31  Reserved */
-  } b;                                   /*!< \brief Structure used for bit  access */
-  uint32_t w;                            /*!< \brief Type      used for word access */
-} ISR_Type;
-
-#define ISR_A_Pos                        13U                                    /*!< \brief ISR: A Position */
-#define ISR_A_Msk                        (1UL << ISR_A_Pos)                     /*!< \brief ISR: A Mask */
-
-#define ISR_I_Pos                        12U                                    /*!< \brief ISR: I Position */
-#define ISR_I_Msk                        (1UL << ISR_I_Pos)                     /*!< \brief ISR: I Mask */
-
-#define ISR_F_Pos                        11U                                    /*!< \brief ISR: F Position */
-#define ISR_F_Msk                        (1UL << ISR_F_Pos)                     /*!< \brief ISR: F Mask */
-
-
-/**
- \brief  Union type to access the L2C_310 Cache Controller.
-*/
-#if (__L2C_PRESENT == 1U)
-typedef struct
-{
-  __I  uint32_t CACHE_ID;                   /*!< \brief Offset: 0x0000   Cache ID Register               */
-  __I  uint32_t CACHE_TYPE;                 /*!< \brief Offset: 0x0004   Cache Type Register             */
-       uint32_t RESERVED0[0x3e];
-  __IO uint32_t CONTROL;                    /*!< \brief Offset: 0x0100   Control Register                */
-  __IO uint32_t AUX_CNT;                    /*!< \brief Offset: 0x0104   Auxiliary Control               */
-       uint32_t RESERVED1[0x3e];
-  __IO uint32_t EVENT_CONTROL;              /*!< \brief Offset: 0x0200   Event Counter Control           */
-  __IO uint32_t EVENT_COUNTER1_CONF;        /*!< \brief Offset: 0x0204   Event Counter 1 Configuration   */
-  __IO uint32_t EVENT_COUNTER0_CONF;        /*!< \brief Offset: 0x0208   Event Counter 1 Configuration   */
-       uint32_t RESERVED2[0x2];
-  __IO uint32_t INTERRUPT_MASK;             /*!< \brief Offset: 0x0214   Interrupt Mask                  */
-  __I  uint32_t MASKED_INT_STATUS;          /*!< \brief Offset: 0x0218   Masked Interrupt Status         */
-  __I  uint32_t RAW_INT_STATUS;             /*!< \brief Offset: 0x021c   Raw Interrupt Status            */
-  __O  uint32_t INTERRUPT_CLEAR;            /*!< \brief Offset: 0x0220   Interrupt Clear                 */
-       uint32_t RESERVED3[0x143];
-  __IO uint32_t CACHE_SYNC;                 /*!< \brief Offset: 0x0730   Cache Sync                      */
-       uint32_t RESERVED4[0xf];
-  __IO uint32_t INV_LINE_PA;                /*!< \brief Offset: 0x0770   Invalidate Line By PA           */
-       uint32_t RESERVED6[2];
-  __IO uint32_t INV_WAY;                    /*!< \brief Offset: 0x077c   Invalidate by Way               */
-       uint32_t RESERVED5[0xc];
-  __IO uint32_t CLEAN_LINE_PA;              /*!< \brief Offset: 0x07b0   Clean Line by PA                */
-       uint32_t RESERVED7[1];
-  __IO uint32_t CLEAN_LINE_INDEX_WAY;       /*!< \brief Offset: 0x07b8   Clean Line by Index/Way         */
-  __IO uint32_t CLEAN_WAY;                  /*!< \brief Offset: 0x07bc   Clean by Way                    */
-       uint32_t RESERVED8[0xc];
-  __IO uint32_t CLEAN_INV_LINE_PA;          /*!< \brief Offset: 0x07f0   Clean and Invalidate Line by PA  */
-       uint32_t RESERVED9[1];
-  __IO uint32_t CLEAN_INV_LINE_INDEX_WAY;   /*!< \brief Offset: 0x07f8   Clean and Invalidate Line by Index/Way  */
-  __IO uint32_t CLEAN_INV_WAY;              /*!< \brief Offset: 0x07fc   Clean and Invalidate by Way     */
-       uint32_t RESERVED10[0x40];
-  __IO uint32_t DATA_LOCK_0_WAY;            /*!< \brief Offset: 0x0900   Data Lockdown 0 by Way          */
-  __IO uint32_t INST_LOCK_0_WAY;            /*!< \brief Offset: 0x0904   Instruction Lockdown 0 by Way   */
-  __IO uint32_t DATA_LOCK_1_WAY;            /*!< \brief Offset: 0x0908   Data Lockdown 1 by Way          */
-  __IO uint32_t INST_LOCK_1_WAY;            /*!< \brief Offset: 0x090c   Instruction Lockdown 1 by Way   */
-  __IO uint32_t DATA_LOCK_2_WAY;            /*!< \brief Offset: 0x0910   Data Lockdown 2 by Way          */
-  __IO uint32_t INST_LOCK_2_WAY;            /*!< \brief Offset: 0x0914   Instruction Lockdown 2 by Way   */
-  __IO uint32_t DATA_LOCK_3_WAY;            /*!< \brief Offset: 0x0918   Data Lockdown 3 by Way          */
-  __IO uint32_t INST_LOCK_3_WAY;            /*!< \brief Offset: 0x091c   Instruction Lockdown 3 by Way   */
-  __IO uint32_t DATA_LOCK_4_WAY;            /*!< \brief Offset: 0x0920   Data Lockdown 4 by Way          */
-  __IO uint32_t INST_LOCK_4_WAY;            /*!< \brief Offset: 0x0924   Instruction Lockdown 4 by Way   */
-  __IO uint32_t DATA_LOCK_5_WAY;            /*!< \brief Offset: 0x0928   Data Lockdown 5 by Way          */
-  __IO uint32_t INST_LOCK_5_WAY;            /*!< \brief Offset: 0x092c   Instruction Lockdown 5 by Way   */
-  __IO uint32_t DATA_LOCK_6_WAY;            /*!< \brief Offset: 0x0930   Data Lockdown 5 by Way          */
-  __IO uint32_t INST_LOCK_6_WAY;            /*!< \brief Offset: 0x0934   Instruction Lockdown 5 by Way   */
-  __IO uint32_t DATA_LOCK_7_WAY;            /*!< \brief Offset: 0x0938   Data Lockdown 6 by Way          */
-  __IO uint32_t INST_LOCK_7_WAY;            /*!< \brief Offset: 0x093c   Instruction Lockdown 6 by Way   */
-       uint32_t RESERVED11[0x4];
-  __IO uint32_t LOCK_LINE_EN;               /*!< \brief Offset: 0x0950   Lockdown by Line Enable         */
-  __IO uint32_t UNLOCK_ALL_BY_WAY;          /*!< \brief Offset: 0x0954   Unlock All Lines by Way         */
-       uint32_t RESERVED12[0xaa];
-  __IO uint32_t ADDRESS_FILTER_START;       /*!< \brief Offset: 0x0c00   Address Filtering Start         */
-  __IO uint32_t ADDRESS_FILTER_END;         /*!< \brief Offset: 0x0c04   Address Filtering End           */
-       uint32_t RESERVED13[0xce];
-  __IO uint32_t DEBUG_CONTROL;              /*!< \brief Offset: 0x0f40   Debug Control Register          */
-} L2C_310_TypeDef;
-
-#define L2C_310           ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 Declaration */
-#endif
-
-#if (__GIC_PRESENT == 1U)
-/** \brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)
-*/
-typedef struct
-{
- __IO uint32_t ICDDCR;
- __I  uint32_t ICDICTR;
- __I  uint32_t ICDIIDR;
-      uint32_t RESERVED0[29];
- __IO uint32_t ICDISR[32];
- __IO uint32_t ICDISER[32];
- __IO uint32_t ICDICER[32];
- __IO uint32_t ICDISPR[32];
- __IO uint32_t ICDICPR[32];
- __I  uint32_t ICDABR[32];
-      uint32_t RESERVED1[32];
- __IO uint32_t ICDIPR[256];
- __IO uint32_t ICDIPTR[256];
- __IO uint32_t ICDICFR[64];
-      uint32_t RESERVED2[128];
- __IO uint32_t ICDSGIR;
-}  GICDistributor_Type;
-
-#define GICDistributor      ((GICDistributor_Type      *)     GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
-
-/** \brief  Structure type to access the Generic Interrupt Controller Interface (GICC)
-*/
-typedef struct
-{
-  __IO uint32_t ICCICR;          //!< \brief  +0x000 - RW - CPU Interface Control Register
-  __IO uint32_t ICCPMR;          //!< \brief  +0x004 - RW - Interrupt Priority Mask Register
-  __IO uint32_t ICCBPR;          //!< \brief  +0x008 - RW - Binary Point Register
-  __I  uint32_t ICCIAR;          //!< \brief  +0x00C - RO - Interrupt Acknowledge Register
-  __IO uint32_t ICCEOIR;         //!< \brief  +0x010 - WO - End of Interrupt Register
-  __I  uint32_t ICCRPR;          //!< \brief  +0x014 - RO - Running Priority Register
-  __I  uint32_t ICCHPIR;         //!< \brief  +0x018 - RO - Highest Pending Interrupt Register
-  __IO uint32_t ICCABPR;         //!< \brief  +0x01C - RW - Aliased Binary Point Register
-  uint32_t RESERVED[55];
-  __I  uint32_t ICCIIDR;         //!< \brief  +0x0FC - RO - CPU Interface Identification Register
-}  GICInterface_Type;
-
-#define GICInterface        ((GICInterface_Type        *)     GIC_INTERFACE_BASE )   /*!< GIC Interface configuration struct */
-#endif
-
-#if (__TIM_PRESENT == 1U)
-#if ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
-/** \brief Structure type to access the Private Timer
-*/
-typedef struct
-{
-  __IO uint32_t LOAD;            //!< \brief  +0x000 - RW - Private Timer Load Register
-  __IO uint32_t COUNTER;         //!< \brief  +0x004 - RW - Private Timer Counter Register
-  __IO uint32_t CONTROL;         //!< \brief  +0x008 - RW - Private Timer Control Register
-  __IO uint32_t ISR;             //!< \brief  +0x00C - RO - Private Timer Interrupt Status Register
-  uint32_t RESERVED[8];
-  __IO uint32_t WLOAD;           //!< \brief  +0x020 - RW - Watchdog Load Register
-  __IO uint32_t WCOUNTER;        //!< \brief  +0x024 - RW - Watchdog Counter Register
-  __IO uint32_t WCONTROL;        //!< \brief  +0x028 - RW - Watchdog Control Register
-  __IO uint32_t WISR;            //!< \brief  +0x02C - RW - Watchdog Interrupt Status Register
-  __IO uint32_t WRESET;          //!< \brief  +0x030 - RW - Watchdog Reset Status Register
-  __I  uint32_t WDISABLE;        //!< \brief  +0x0FC - RO - Watchdog Disable Register
-} Timer_Type;
-#define PTIM ((Timer_Type *) TIMER_BASE )   /*!< \brief Timer configuration struct */
-#endif
-#endif
-
- /*******************************************************************************
-  *                Hardware Abstraction Layer
-   Core Function Interface contains:
-   - L1 Cache Functions
-   - L2C-310 Cache Controller Functions 
-   - PL1 Timer Functions
-   - GIC Functions
-   - MMU Functions
-  ******************************************************************************/
- 
-/* ##########################  L1 Cache functions  ################################# */
-
-/** \brief  Enable Caches
-
-  Enable Caches
- */
-__STATIC_INLINE void L1C_EnableCaches(void) {
-  // Set I bit 12 to enable I Cache
-  // Set C bit  2 to enable D Cache
-  __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief  Disable Caches
-
-  Disable Caches
- */
-__STATIC_INLINE void L1C_DisableCaches(void) {
-  // Clear I bit 12 to disable I Cache
-  // Clear C bit  2 to disable D Cache
-  __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
-  __ISB();
-}
-
-/** \brief  Enable BTAC
-
-  Enable BTAC
- */
-__STATIC_INLINE void L1C_EnableBTAC(void) {
-  // Set Z bit 11 to enable branch prediction
-  __set_SCTLR( __get_SCTLR() | (1 << 11));
-  __ISB();
-}
-
-/** \brief  Disable BTAC
-
-  Disable BTAC
- */
-__STATIC_INLINE void L1C_DisableBTAC(void) {
-  // Clear Z bit 11 to disable branch prediction
-  __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-/** \brief  Invalidate entire branch predictor array
-
-  BPIALL. Branch Predictor Invalidate All.
- */
-
-__STATIC_INLINE void L1C_InvalidateBTAC(void) {
-  __set_BPIALL(0);
-  __DSB();     //ensure completion of the invalidation
-  __ISB();     //ensure instruction fetch path sees new state
-}
-
-/** \brief  Invalidate the whole I$
-
-  ICIALLU. Instruction Cache Invalidate All to PoU
-*/
-__STATIC_INLINE void L1C_InvalidateICacheAll(void) {
-  __set_ICIALLU(0);
-  __DSB();     //ensure completion of the invalidation
-  __ISB();     //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief  Clean D$ by MVA
-
-  DCCMVAC. Data cache clean by MVA to PoC
-*/
-__STATIC_INLINE void L1C_CleanDCacheMVA(void *va) {
-  __set_DCCMVAC((uint32_t)va);
-  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Invalidate D$ by MVA
-
-  DCIMVAC. Data cache invalidate by MVA to PoC
-*/
-__STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) {
-  __set_DCIMVAC((uint32_t)va);
-  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate D$ by MVA
-
-  DCCIMVAC. Data cache clean and invalidate by MVA to PoC
-*/
-__STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
-  __set_DCCIMVAC((uint32_t)va);
-  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate the entire data or unified cache
-
-  Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
-*/
-__STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) {
-  __L1C_CleanInvalidateCache(op);  // compiler specific call
-}
-
-
-/** \brief  Invalidate the whole D$
-
-  DCISW. Invalidate by Set/Way
-*/
-
-__STATIC_INLINE void L1C_InvalidateDCacheAll(void) {
-  L1C_CleanInvalidateCache(0);
-}
-
-/** \brief  Clean the whole D$
-
-    DCCSW. Clean by Set/Way
- */
-
-__STATIC_INLINE void L1C_CleanDCacheAll(void) {
-  L1C_CleanInvalidateCache(1);
-}
-
-/** \brief  Clean and invalidate the whole D$
-
-    DCCISW. Clean and Invalidate by Set/Way
- */
-
-__STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
-  L1C_CleanInvalidateCache(2);
-}
-
-
-/* ##########################  L2 Cache functions  ################################# */
-#if (__L2C_PRESENT == 1U)
-//Cache Sync operation
-__STATIC_INLINE void L2C_Sync(void)
-{
-  L2C_310->CACHE_SYNC = 0x0;
-}
-
-//return Cache controller cache ID
-__STATIC_INLINE int L2C_GetID (void)
-{
-  return L2C_310->CACHE_ID;
-}
-
-//return Cache controller cache Type
-__STATIC_INLINE int L2C_GetType (void)
-{
-  return L2C_310->CACHE_TYPE;
-}
-
-//Invalidate all cache by way
-__STATIC_INLINE void L2C_InvAllByWay (void)
-{
-  unsigned int assoc;
-
-  if (L2C_310->AUX_CNT & (1<<16))
-    assoc = 16;
-  else
-    assoc =  8;
-
-  L2C_310->INV_WAY = (1 << assoc) - 1;
-  while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
-
-  L2C_Sync();
-}
-
-//Clean and Invalidate all cache by way
-__STATIC_INLINE void L2C_CleanInvAllByWay (void)
-{
-  unsigned int assoc;
-
-  if (L2C_310->AUX_CNT & (1<<16))
-    assoc = 16;
-  else
-    assoc =  8;
-
-  L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1;
-  while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
-
-  L2C_Sync();
-}
-
-//Enable Cache
-__STATIC_INLINE void L2C_Enable(void)
-{
-  L2C_310->CONTROL = 0;
-  L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
-  L2C_310->DEBUG_CONTROL = 0;
-  L2C_310->DATA_LOCK_0_WAY = 0;
-  L2C_310->CACHE_SYNC = 0;
-  L2C_310->CONTROL = 0x01;
-  L2C_Sync();
-}
-//Disable Cache
-__STATIC_INLINE void L2C_Disable(void)
-{
-  L2C_310->CONTROL = 0x00;
-  L2C_Sync();
-}
-
-//Invalidate cache by physical address
-__STATIC_INLINE void L2C_InvPa (void *pa)
-{
-  L2C_310->INV_LINE_PA = (unsigned int)pa;
-  L2C_Sync();
-}
-
-//Clean cache by physical address
-__STATIC_INLINE void L2C_CleanPa (void *pa)
-{
-  L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
-  L2C_Sync();
-}
-
-//Clean and invalidate cache by physical address
-__STATIC_INLINE void L2C_CleanInvPa (void *pa)
-{
-  L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
-  L2C_Sync();
-}
-#endif
-
-/* ##########################  GIC functions  ###################################### */
-#if (__GIC_PRESENT == 1U)
-  
-__STATIC_INLINE void GIC_EnableDistributor(void)
-{
-  GICDistributor->ICDDCR |= 1; //enable distributor
-}
-
-__STATIC_INLINE void GIC_DisableDistributor(void)
-{
-  GICDistributor->ICDDCR &=~1; //disable distributor
-}
-
-__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
-{
-  return (uint32_t)(GICDistributor->ICDICTR);
-}
-
-__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
-{
-  return (uint32_t)(GICDistributor->ICDIIDR);
-}
-
-__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
-{
-  char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
-  field += IRQn % 4;
-  *field = (char)cpu_target & 0xf;
-}
-
-__STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn)
-{
-  uint32_t i, num_irq;
-
-  //Get the maximum number of interrupts that the GIC supports
-  num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
-
-  for (i = 0; i < (num_irq/16); i++)
-  {
-    GICDistributor->ICDISPR[i] = *ICDICFRn++;
-  }
-}
-
-__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
-{
-  char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
-  field += IRQn % 4;
-  return ((uint32_t)*field & 0xf);
-}
-
-__STATIC_INLINE void GIC_EnableInterface(void)
-{
-  GICInterface->ICCICR |= 1; //enable interface
-}
-
-__STATIC_INLINE void GIC_DisableInterface(void)
-{
-  GICInterface->ICCICR &=~1; //disable distributor
-}
-
-__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
-{
-  return (IRQn_Type)(GICInterface->ICCIAR);
-}
-
-__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
-{
-  GICInterface->ICCEOIR = IRQn;
-}
-
-__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
-{
-  GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
-{
-  GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-__STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
-{   
-  // Word-size read/writes must be used to access this register
-  volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]);
-  unsigned bit_shift = (IRQn % 16)<<1;
-  unsigned int save_word;
-
-  save_word = *field;
-  save_word &= (~(3 << bit_shift));
-
-  *field = (save_word | (((edge_level<<1) | model) << bit_shift));
-}
-
-__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
-  field += IRQn % 4;
-  *field = (char)priority;
-}
-
-__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
-{
-  char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
-  field += IRQn % 4;
-  return (uint32_t)*field;
-}
-
-__STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority)
-{
-  GICInterface->ICCPMR = priority & 0xff; //set priority mask
-}
-
-__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
-{
-  GICInterface->ICCBPR = binary_point & 0x07; //set binary point
-}
-
-__STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
-{
-  return (uint32_t)GICInterface->ICCBPR;
-}
-
-__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
-{
-  uint32_t pending, active;
-
-  active = ((GICDistributor->ICDABR[IRQn / 32])  >> (IRQn % 32)) & 0x1;
-  pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
-
-  return ((active<<1) | pending);
-}
-
-__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
-{
-  GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
-}
-
-__STATIC_INLINE void GIC_DistInit(void)
-{
-  IRQn_Type i;
-  uint32_t num_irq = 0;
-  uint32_t priority_field;
-
-  //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
-  //configuring all of the interrupts as Secure.
-
-  //Disable interrupt forwarding
-  GIC_DisableDistributor();
-  //Get the maximum number of interrupts that the GIC supports
-  num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
-
-  /* Priority level is implementation defined.
-   To determine the number of priority bits implemented write 0xFF to an ICDIPR
-   priority field and read back the value stored.*/
-  GIC_SetPriority((IRQn_Type)0, 0xff);
-  priority_field = GIC_GetPriority((IRQn_Type)0);
-
-  for (i = (IRQn_Type)32; i < num_irq; i++)
-  {
-      //Disable the SPI interrupt
-      GIC_DisableIRQ(i);
-      //Set level-sensitive and 1-N model
-      GIC_SetLevelModel(i, 0, 1);
-      //Set priority
-      GIC_SetPriority(i, priority_field/2);
-      //Set target list to CPU0
-      GIC_SetTarget(i, 1);
-  }
-  //Enable distributor
-  GIC_EnableDistributor();
-}
-
-__STATIC_INLINE void GIC_CPUInterfaceInit(void)
-{
-  IRQn_Type i;
-  uint32_t priority_field;
-
-  //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
-  //configuring all of the interrupts as Secure.
-
-  //Disable interrupt forwarding
-  GIC_DisableInterface();
-
-  /* Priority level is implementation defined.
-   To determine the number of priority bits implemented write 0xFF to an ICDIPR
-   priority field and read back the value stored.*/
-  GIC_SetPriority((IRQn_Type)0, 0xff);
-  priority_field = GIC_GetPriority((IRQn_Type)0);
-
-  //SGI and PPI
-  for (i = (IRQn_Type)0; i < 32; i++)
-  {
-      //Set level-sensitive and 1-N model for PPI
-    if(i > 15)
-          GIC_SetLevelModel(i, 0, 1);
-      //Disable SGI and PPI interrupts
-      GIC_DisableIRQ(i);
-      //Set priority
-      GIC_SetPriority(i, priority_field/2);
-  }
-  //Enable interface
-  GIC_EnableInterface();
-  //Set binary point to 0
-  GIC_SetBinaryPoint(0);
-  //Set priority mask
-  GIC_InterfacePriorityMask(0xff);
-}
-
-__STATIC_INLINE void GIC_Enable(void)
-{
-  GIC_DistInit();
-  GIC_CPUInterfaceInit(); //per CPU
-}
-#endif
-
-/* ##########################  Generic Timer functions  ############################ */
-#if (__TIM_PRESENT == 1U)
-  
-/* PL1 Physical Timer */
-#if (__CORTEX_A == 7U)
-__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
-  __set_CNTP_TVAL(value);
-  __ISB();
-}
-
-__STATIC_INLINE uint32_t PL1_GetCurrentValue() {
-  return(__get_CNTP_TVAL());
-}
-
-__STATIC_INLINE void PL1_SetControl(uint32_t value) {
-  __set_CNTP_CTL(value);
-  __ISB();
-}
-
-/* Private Timer */
-#elif ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
-__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
-  PTIM->LOAD = value;
-}
-
-__STATIC_INLINE uint32_t PTIM_GetLoadValue() {
-  return(PTIM->LOAD);
-}
-
-__STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
-  return(PTIM->COUNTER);
-}
-
-__STATIC_INLINE void PTIM_SetControl(uint32_t value) {
-  PTIM->CONTROL = value;
-}
-
-__STATIC_INLINE uint32_t PTIM_GetControl(void) {
-  return(PTIM->CONTROL);
-}
-
-__STATIC_INLINE void PTIM_ClearEventFlag(void) {
-  PTIM->ISR = 1;
-}
-#endif
-#endif
-
-/* ##########################  MMU functions  ###################################### */
-
-#define SECTION_DESCRIPTOR      (0x2)
-#define SECTION_MASK            (0xFFFFFFFC)
-
-#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
-#define SECTION_B_SHIFT         (2)
-#define SECTION_C_SHIFT         (3)
-#define SECTION_TEX0_SHIFT      (12)
-#define SECTION_TEX1_SHIFT      (13)
-#define SECTION_TEX2_SHIFT      (14)
-
-#define SECTION_XN_MASK         (0xFFFFFFEF)
-#define SECTION_XN_SHIFT        (4)
-
-#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
-#define SECTION_DOMAIN_SHIFT    (5)
-
-#define SECTION_P_MASK          (0xFFFFFDFF)
-#define SECTION_P_SHIFT         (9)
-
-#define SECTION_AP_MASK         (0xFFFF73FF)
-#define SECTION_AP_SHIFT        (10)
-#define SECTION_AP2_SHIFT       (15)
-
-#define SECTION_S_MASK          (0xFFFEFFFF)
-#define SECTION_S_SHIFT         (16)
-
-#define SECTION_NG_MASK         (0xFFFDFFFF)
-#define SECTION_NG_SHIFT        (17)
-
-#define SECTION_NS_MASK         (0xFFF7FFFF)
-#define SECTION_NS_SHIFT        (19)
-
-#define PAGE_L1_DESCRIPTOR      (0x1)
-#define PAGE_L1_MASK            (0xFFFFFFFC)
-
-#define PAGE_L2_4K_DESC         (0x2)
-#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
-
-#define PAGE_L2_64K_DESC        (0x1)
-#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
-
-#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
-#define PAGE_4K_B_SHIFT         (2)
-#define PAGE_4K_C_SHIFT         (3)
-#define PAGE_4K_TEX0_SHIFT      (6)
-#define PAGE_4K_TEX1_SHIFT      (7)
-#define PAGE_4K_TEX2_SHIFT      (8)
-
-#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
-#define PAGE_64K_B_SHIFT        (2)
-#define PAGE_64K_C_SHIFT        (3)
-#define PAGE_64K_TEX0_SHIFT     (12)
-#define PAGE_64K_TEX1_SHIFT     (13)
-#define PAGE_64K_TEX2_SHIFT     (14)
-
-#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
-#define PAGE_B_SHIFT            (2)
-#define PAGE_C_SHIFT            (3)
-#define PAGE_TEX_SHIFT          (12)
-
-#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
-#define PAGE_XN_4K_SHIFT        (0)
-#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
-#define PAGE_XN_64K_SHIFT       (15)
-
-#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
-#define PAGE_DOMAIN_SHIFT       (5)
-
-#define PAGE_P_MASK             (0xFFFFFDFF)
-#define PAGE_P_SHIFT            (9)
-
-#define PAGE_AP_MASK            (0xFFFFFDCF)
-#define PAGE_AP_SHIFT           (4)
-#define PAGE_AP2_SHIFT          (9)
-
-#define PAGE_S_MASK             (0xFFFFFBFF)
-#define PAGE_S_SHIFT            (10)
-
-#define PAGE_NG_MASK            (0xFFFFF7FF)
-#define PAGE_NG_SHIFT           (11)
-
-#define PAGE_NS_MASK            (0xFFFFFFF7)
-#define PAGE_NS_SHIFT           (3)
-
-#define OFFSET_1M               (0x00100000)
-#define OFFSET_64K              (0x00010000)
-#define OFFSET_4K               (0x00001000)
-
-#define DESCRIPTOR_FAULT        (0x00000000)
-
-/* Attributes enumerations */
-
-/* Region size attributes */
-typedef enum
-{
-   SECTION,
-   PAGE_4k,
-   PAGE_64k,
-} mmu_region_size_Type;
-
-/* Region type attributes */
-typedef enum
-{
-   NORMAL,
-   DEVICE,
-   SHARED_DEVICE,
-   NON_SHARED_DEVICE,
-   STRONGLY_ORDERED
-} mmu_memory_Type;
-
-/* Region cacheability attributes */
-typedef enum
-{
-   NON_CACHEABLE,
-   WB_WA,
-   WT,
-   WB_NO_WA,
-} mmu_cacheability_Type;
-
-/* Region parity check attributes */
-typedef enum
-{
-   ECC_DISABLED,
-   ECC_ENABLED,
-} mmu_ecc_check_Type;
-
-/* Region execution attributes */
-typedef enum
-{
-   EXECUTE,
-   NON_EXECUTE,
-} mmu_execute_Type;
-
-/* Region global attributes */
-typedef enum
-{
-   GLOBAL,
-   NON_GLOBAL,
-} mmu_global_Type;
-
-/* Region shareability attributes */
-typedef enum
-{
-   NON_SHARED,
-   SHARED,
-} mmu_shared_Type;
-
-/* Region security attributes */
-typedef enum
-{
-   SECURE,
-   NON_SECURE,
-} mmu_secure_Type;
-
-/* Region access attributes */
-typedef enum
-{
-   NO_ACCESS,
-   RW,
-   READ,
-} mmu_access_Type;
-
-/* Memory Region definition */
-typedef struct RegionStruct {
-    mmu_region_size_Type rg_t;
-    mmu_memory_Type mem_t;
-    uint8_t domain;
-    mmu_cacheability_Type inner_norm_t;
-    mmu_cacheability_Type outer_norm_t;
-    mmu_ecc_check_Type e_t;
-    mmu_execute_Type xn_t;
-    mmu_global_Type g_t;
-    mmu_secure_Type sec_t;
-    mmu_access_Type priv_t;
-    mmu_access_Type user_t;
-    mmu_shared_Type sh_t;
-
-} mmu_region_attributes_Type;
-
-//Following macros define the descriptors and attributes
-//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
-#define section_normal(descriptor_l1, region)     region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
-
-//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
-#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = EXECUTE; \
-                                   region.priv_t = READ; \
-                                   region.user_t = READ; \
-                                   region.sh_t = NON_SHARED; \
-                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
-
-//Sect_Normal_RO. Sect_Normal_Cod, but not executable
-#define section_normal_ro(descriptor_l1, region)  region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = READ; \
-                                   region.user_t = READ; \
-                                   region.sh_t = NON_SHARED; \
-                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
-
-//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
-#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
-//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
-#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = STRONGLY_ORDERED; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
-
-//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
-#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = STRONGLY_ORDERED; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = READ; \
-                                   region.user_t = READ; \
-                                   region.sh_t = NON_SHARED; \
-                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
-
-//Sect_Device_RW. Sect_Device_RO, but writeable
-#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = STRONGLY_ORDERED; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
-//Page_4k_Device_RW.  Shared device, not executable, rw, domain 0
-#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = SHARED_DEVICE; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
-
-//Page_64k_Device_RW.  Shared device, not executable, rw, domain 0
-#define page64k_device_rw(descriptor_l1, descriptor_l2, region)  region.rg_t = PAGE_64k; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = SHARED_DEVICE; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
-
-/** \brief  Set section execution-never attribute
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
-{
-  *descriptor_l1 &= SECTION_XN_MASK;
-  *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
-  return 0;
-}
-
-/** \brief  Set section domain
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]            domain  Section domain
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
-{
-  *descriptor_l1 &= SECTION_DOMAIN_MASK;
-  *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
-  return 0;
-}
-
-/** \brief  Set section parity check
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
-  *descriptor_l1 &= SECTION_P_MASK;
-  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
-  return 0;
-}
-
-/** \brief  Set section access privileges
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]              user  User Level Access: NO_ACCESS, RW, READ
-  \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
-  \param [in]               afe  Access flag enable
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
-{
-  uint32_t ap = 0;
-
-  if (afe == 0) { //full access
-    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
-    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
-    else if ((priv == RW) && (user == READ))        { ap = 0x2; }
-    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-  }
-
-  else { //Simplified access
-    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
-    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-  }
-
-  *descriptor_l1 &= SECTION_AP_MASK;
-  *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
-  *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
-
-  return 0;
-}
-
-/** \brief  Set section shareability
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
-{
-  *descriptor_l1 &= SECTION_S_MASK;
-  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
-  return 0;
-}
-
-/** \brief  Set section Global attribute
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
-{
-  *descriptor_l1 &= SECTION_NG_MASK;
-  *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
-  return 0;
-}
-
-/** \brief  Set section Security attribute
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
-  *descriptor_l1 &= SECTION_NS_MASK;
-  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
-  return 0;
-}
-
-/* Page 4k or 64k */
-/** \brief  Set 4k/64k page execution-never attribute
-
-  \param [out]    descriptor_l2  L2 descriptor.
-  \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
-  \param [in]              page  Page size: PAGE_4k, PAGE_64k,
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
-{
-  if (page == PAGE_4k)
-  {
-      *descriptor_l2 &= PAGE_XN_4K_MASK;
-      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
-  }
-  else
-  {
-      *descriptor_l2 &= PAGE_XN_64K_MASK;
-      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
-  }
-  return 0;
-}
-
-/** \brief  Set 4k/64k page domain
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]            domain  Page domain
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
-{
-  *descriptor_l1 &= PAGE_DOMAIN_MASK;
-  *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
-  return 0;
-}
-
-/** \brief  Set 4k/64k page parity check
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
-  *descriptor_l1 &= SECTION_P_MASK;
-  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
-  return 0;
-}
-
-/** \brief  Set 4k/64k page access privileges
-
-  \param [out]    descriptor_l2  L2 descriptor.
-  \param [in]              user  User Level Access: NO_ACCESS, RW, READ
-  \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
-  \param [in]               afe  Access flag enable
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
-{
-  uint32_t ap = 0;
-
-  if (afe == 0) { //full access
-    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
-    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
-    else if ((priv == RW) && (user == READ))        { ap = 0x2; }
-    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-    else if ((priv == READ) && (user == READ))      { ap = 0x6; }
-  }
-
-  else { //Simplified access
-    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
-    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-  }
-
-  *descriptor_l2 &= PAGE_AP_MASK;
-  *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
-  *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
-
-  return 0;
-}
-
-/** \brief  Set 4k/64k page shareability
-
-  \param [out]    descriptor_l2  L2 descriptor.
-  \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
-{
-  *descriptor_l2 &= PAGE_S_MASK;
-  *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
-  return 0;
-}
-
-/** \brief  Set 4k/64k page Global attribute
-
-  \param [out]    descriptor_l2  L2 descriptor.
-  \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
-{
-  *descriptor_l2 &= PAGE_NG_MASK;
-  *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
-  return 0;
-}
-
-/** \brief  Set 4k/64k page Security attribute
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
-  *descriptor_l1 &= PAGE_NS_MASK;
-  *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
-  return 0;
-}
-
-/** \brief  Set Section memory attributes
-
-  \param [out]    descriptor_l1  L1 descriptor.
-  \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
-  \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-  \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
-{
-  *descriptor_l1 &= SECTION_TEXCB_MASK;
-
-  if (STRONGLY_ORDERED == mem)
-  {
-    return 0;
-  }
-  else if (SHARED_DEVICE == mem)
-  {
-    *descriptor_l1 |= (1 << SECTION_B_SHIFT);
-  }
-  else if (NON_SHARED_DEVICE == mem)
-  {
-    *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
-  }
-  else if (NORMAL == mem)
-  {
-   *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
-   switch(inner)
-   {
-      case NON_CACHEABLE:
-        break;
-      case WB_WA:
-        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
-        break;
-      case WT:
-        *descriptor_l1 |= 1 << SECTION_C_SHIFT;
-        break;
-      case WB_NO_WA:
-        *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
-        break;
-    }
-    switch(outer)
-    {
-      case NON_CACHEABLE:
-        break;
-      case WB_WA:
-        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
-        break;
-      case WT:
-        *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
-        break;
-      case WB_NO_WA:
-        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
-        break;
-    }
-  }
-  return 0;
-}
-
-/** \brief  Set 4k/64k page memory attributes
-
-  \param [out]    descriptor_l2  L2 descriptor.
-  \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
-  \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-  \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-  \param [in]              page  Page size
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
-{
-  *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
-
-  if (page == PAGE_64k)
-  {
-    //same as section
-    MMU_MemorySection(descriptor_l2, mem, outer, inner);
-  }
-  else
-  {
-    if (STRONGLY_ORDERED == mem)
-    {
-      return 0;
-    }
-    else if (SHARED_DEVICE == mem)
-    {
-      *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
-    }
-    else if (NON_SHARED_DEVICE == mem)
-    {
-      *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
-    }
-    else if (NORMAL == mem)
-    {
-      *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
-      switch(inner)
-      {
-        case NON_CACHEABLE:
-          break;
-        case WB_WA:
-          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
-          break;
-        case WT:
-          *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
-          break;
-        case WB_NO_WA:
-          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
-          break;
-      }
-      switch(outer)
-      {
-        case NON_CACHEABLE:
-          break;
-        case WB_WA:
-          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
-          break;
-        case WT:
-          *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
-          break;
-        case WB_NO_WA:
-          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
-          break;
-      }
-    }
-  }
-
-  return 0;
-}
-
-/** \brief  Create a L1 section descriptor
-
-  \param [out]     descriptor  L1 descriptor
-  \param [in]      reg  Section attributes
-  
-  \return          0
-*/
-__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
-{
-  *descriptor  = 0;
-
-  MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
-  MMU_XNSection(descriptor,reg.xn_t);
-  MMU_DomainSection(descriptor, reg.domain);
-  MMU_PSection(descriptor, reg.e_t);
-  MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
-  MMU_SharedSection(descriptor,reg.sh_t);
-  MMU_GlobalSection(descriptor,reg.g_t);
-  MMU_SecureSection(descriptor,reg.sec_t);
-  *descriptor &= SECTION_MASK;
-  *descriptor |= SECTION_DESCRIPTOR;
- 
-  return 0;
-}
-
-
-/** \brief  Create a L1 and L2 4k/64k page descriptor
-
-  \param [out]       descriptor  L1 descriptor
-  \param [out]      descriptor2  L2 descriptor
-  \param [in]               reg  4k/64k page attributes
-
-  \return          0
-*/
-__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
-{
-  *descriptor  = 0;
-  *descriptor2 = 0;
-
-  switch (reg.rg_t)
-  {
-    case PAGE_4k:
-      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
-      MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
-      MMU_DomainPage(descriptor, reg.domain);
-      MMU_PPage(descriptor, reg.e_t);
-      MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
-      MMU_SharedPage(descriptor2,reg.sh_t);
-      MMU_GlobalPage(descriptor2,reg.g_t);
-      MMU_SecurePage(descriptor,reg.sec_t);
-      *descriptor &= PAGE_L1_MASK;
-      *descriptor |= PAGE_L1_DESCRIPTOR;
-      *descriptor2 &= PAGE_L2_4K_MASK;
-      *descriptor2 |= PAGE_L2_4K_DESC;
-      break;
-
-    case PAGE_64k:
-      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
-      MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
-      MMU_DomainPage(descriptor, reg.domain);
-      MMU_PPage(descriptor, reg.e_t);
-      MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
-      MMU_SharedPage(descriptor2,reg.sh_t);
-      MMU_GlobalPage(descriptor2,reg.g_t);
-      MMU_SecurePage(descriptor,reg.sec_t);
-      *descriptor &= PAGE_L1_MASK;
-      *descriptor |= PAGE_L1_DESCRIPTOR;
-      *descriptor2 &= PAGE_L2_64K_MASK;
-      *descriptor2 |= PAGE_L2_64K_DESC;
-      break;
-
-    case SECTION:
-      //error
-      break;
-  }
-  
-  return 0;
-}
-
-/** \brief  Create a 1MB Section
-
-  \param [in]               ttb  Translation table base address
-  \param [in]      base_address  Section base address
-  \param [in]             count  Number of sections to create
-  \param [in]     descriptor_l1  L1 descriptor (region attributes)
-
-*/
-__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
-{
-  uint32_t offset;
-  uint32_t entry;
-  uint32_t i;
-
-  offset = base_address >> 20;
-  entry  = (base_address & 0xFFF00000) | descriptor_l1;
-
-  //4 bytes aligned
-  ttb = ttb + offset;
-
-  for (i = 0; i < count; i++ )
-  {
-    //4 bytes aligned
-    *ttb++ = entry;
-    entry += OFFSET_1M;
-  }
-}
-
-/** \brief  Create a 4k page entry
-
-  \param [in]               ttb  L1 table base address
-  \param [in]      base_address  4k base address
-  \param [in]             count  Number of 4k pages to create
-  \param [in]     descriptor_l1  L1 descriptor (region attributes)
-  \param [in]            ttb_l2  L2 table base address
-  \param [in]     descriptor_l2  L2 descriptor (region attributes)
-
-*/
-__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
-
-  uint32_t offset, offset2;
-  uint32_t entry, entry2;
-  uint32_t i;
-
-  offset = base_address >> 20;
-  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
-  //4 bytes aligned
-  ttb += offset;
-  //create l1_entry
-  *ttb = entry;
-
-  offset2 = (base_address & 0xff000) >> 12;
-  ttb_l2 += offset2;
-  entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
-  for (i = 0; i < count; i++ )
-  {
-    //4 bytes aligned
-    *ttb_l2++ = entry2;
-    entry2 += OFFSET_4K;
-  }
-}
-
-/** \brief  Create a 64k page entry
-
-  \param [in]               ttb  L1 table base address
-  \param [in]      base_address  64k base address
-  \param [in]             count  Number of 64k pages to create
-  \param [in]     descriptor_l1  L1 descriptor (region attributes)
-  \param [in]            ttb_l2  L2 table base address
-  \param [in]     descriptor_l2  L2 descriptor (region attributes)
-
-*/
-__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
-  uint32_t offset, offset2;
-  uint32_t entry, entry2;
-  uint32_t i,j;
-
-
-  offset = base_address >> 20;
-  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
-  //4 bytes aligned
-  ttb += offset;
-  //create l1_entry
-  *ttb = entry;
-
-  offset2 = (base_address & 0xff000) >> 12;
-  ttb_l2 += offset2;
-  entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
-  for (i = 0; i < count; i++ )
-  {
-    //create 16 entries
-    for (j = 0; j < 16; j++)
-    {
-      //4 bytes aligned
-      *ttb_l2++ = entry2;
-    }
-    entry2 += OFFSET_64K;
-  }
-}
-
-/** \brief  Enable MMU
-
-  Enable MMU
-*/
-__STATIC_INLINE void MMU_Enable(void) {
-  // Set M bit 0 to enable the MMU
-  // Set AFE bit to enable simplified access permissions model
-  // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
-  __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
-  __ISB();
-}
-
-/** \brief  Disable MMU
-
-  Disable MMU
-*/
-__STATIC_INLINE void MMU_Disable(void) {
-  // Clear M bit 0 to disable the MMU
-  __set_SCTLR( __get_SCTLR() & ~1);
-  __ISB();
-}
-
-/** \brief  Invalidate entire unified TLB
-
-  TLBIALL. Invalidate entire unified TLB
-*/
-
-__STATIC_INLINE void MMU_InvalidateTLB(void) {
-  __set_TLBIALL(0);
-  __DSB();     //ensure completion of the invalidation
-  __ISB();     //ensure instruction fetch path sees new state
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CA_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_cm0.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,886 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM0_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000U
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-        uint32_t RESERVED0;
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           Address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)0x0U;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)0x0U;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_cm0plus.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1012 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0+ definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB  ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000U
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-        uint32_t RESERVED0;
-#endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0+ header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0+ */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0+ */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-    uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_cm23.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1876 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm23.h
- * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM23_H_GENERIC
-#define __CORE_CM23_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M23
-  @{
- */
-
-/*  CMSIS cmGrebe definitions */
-#define __CM23_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM23_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
-                                     __CM23_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                     (23U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM23_H_DEPENDANT
-#define __CORE_CM23_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM23_REV
-    #define __CM23_REV                0x0000U
-    #warning "__CM23_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-
-  #ifndef __ETM_PRESENT
-    #define __ETM_PRESENT             0U
-    #warning "__ETM_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MTB_PRESENT
-    #define __MTB_PRESENT             0U
-    #warning "__MTB_PRESENT not defined in device header file; using default!"
-  #endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M23 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-        uint32_t RESERVED0;
-#endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-        uint32_t RESERVED0[6U];
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-        uint32_t RESERVED0[7U];
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_cm3.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1919 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M3
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM3_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM3_REV
-    #define __CM3_REV               0x0200U
-    #warning "__CM3_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
-    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[5U];
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-#else
-        uint32_t RESERVED1[1U];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_cm33.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2896 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm33.h
- * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM33_H_GENERIC
-#define __CORE_CM33_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M33
-  @{
- */
-
-/*  CMSIS CM33 definitions */
-#define __CM33_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM33_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
-                                     __CM33_CMSIS_VERSION_SUB           )     /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM33_H_DEPENDANT
-#define __CORE_CM33_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM33_REV
-    #define __CM33_REV                0x0000U
-    #warning "__CM33_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DSP_PRESENT
-    #define __DSP_PRESENT             0U
-    #warning "__DSP_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M33 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
-    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
-    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED6[580U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-        uint32_t RESERVED4[15U];
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
-        uint32_t RESERVED5[1U];
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-        uint32_t RESERVED6[1U];
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-        uint32_t RESERVED7[6U];
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
-        uint32_t RESERVED6[4U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-        uint32_t RESERVED32[934U];
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-        uint32_t RESERVED33[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
-  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
-  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
-  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
-        uint32_t RESERVED0[1];
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#else
-        uint32_t RESERVED0[3];
-#endif
-  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
-  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
-  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
-  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Set Priority Grouping (non-secure)
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB_NS->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping (non-secure)
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
-  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = FPU->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
-  {
-    return 2U;           /* Double + Single precision FPU */
-  }
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_cm4.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2103 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM4_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000U
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[5U];
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = FPU->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_cm7.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2646 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm7.h
- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M7
-  @{
- */
-
-/*  CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM7_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM7_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM7_REV
-    #define __CM7_REV               0x0000U
-    #warning "__CM7_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __ICACHE_PRESENT
-    #define __ICACHE_PRESENT          0U
-    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DCACHE_PRESENT
-    #define __DCACHE_PRESENT          0U
-    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DTCM_PRESENT
-    #define __DTCM_PRESENT            0U
-    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-        uint32_t RESERVED3[93U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-        uint32_t RESERVED4[15U];
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
-        uint32_t RESERVED5[1U];
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-        uint32_t RESERVED6[1U];
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-        uint32_t RESERVED7[6U];
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED3[981U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 Definitions */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = SCB->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
-  {
-    return 2U;           /* Double + Single precision FPU */
-  }
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################  Cache functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_CacheFunctions Cache Functions
-  \brief    Functions that configure Instruction and Data cache.
-  @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
-
-
-/**
-  \brief   Enable I-Cache
-  \details Turns on I-Cache
-  */
-__STATIC_INLINE void SCB_EnableICache (void)
-{
-  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
-    __DSB();
-    __ISB();
-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Disable I-Cache
-  \details Turns off I-Cache
-  */
-__STATIC_INLINE void SCB_DisableICache (void)
-{
-  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Invalidate I-Cache
-  \details Invalidates I-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateICache (void)
-{
-  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Enable D-Cache
-  \details Turns on D-Cache
-  */
-__STATIC_INLINE void SCB_EnableDCache (void)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways-- != 0U);
-    } while(sets-- != 0U);
-    __DSB();
-
-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Disable D-Cache
-  \details Turns off D-Cache
-  */
-__STATIC_INLINE void SCB_DisableDCache (void)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    register uint32_t ccsidr;
-    register uint32_t sets;
-    register uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* clean & invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Invalidate D-Cache
-  \details Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Clean D-Cache
-  \details Cleans D-Cache
-  */
-__STATIC_INLINE void SCB_CleanDCache (void)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-   __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* clean D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
-                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Clean & Invalidate D-Cache
-  \details Cleans and Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* clean & invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   D-Cache Invalidate by address
-  \details Invalidates D-Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-     int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t)addr;
-     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCIMVAC = op_addr;
-      op_addr += (uint32_t)linesize;
-      op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   D-Cache Clean by address
-  \details Cleans D-Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-     int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCCMVAC = op_addr;
-      op_addr += (uint32_t)linesize;
-      op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   D-Cache Clean and Invalidate by address
-  \details Cleans and invalidates D_Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-     int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCCIMVAC = op_addr;
-      op_addr += (uint32_t)linesize;
-      op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_cmSecureAccess.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,201 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmSecureAccess.h
- * @brief    CMSIS Cortex-M Core Secure Access Header File
- * @version  XXX
- * @date     10. June 2016
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2016 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CM_SECURE_ACCESS_H
-#define __CORE_CM_SECURE_ACCESS_H
-
-
-/* ###########################  Core Secure Access  ########################### */
-
-#ifdef FEATURE_UVISOR
-#include "uvisor-lib/uvisor-lib.h"
-
-/* Secure uVisor implementation. */
-
-/** Set the value at the target address.
- *
- * Equivalent to: `*address = value`.
- * @param address[in]  Target address
- * @param value[in]    Value to write at the address location.
- */
-#define SECURE_WRITE(address, value) \
-    uvisor_write(public_box, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
-
-/** Get the value at the target address.
- *
- * @param address[in]  Target address
- * @returns The value `*address`.
- */
-#define SECURE_READ(address) \
-    uvisor_read(public_box, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
-
-/** Get the selected bits at the target address.
- *
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- * @returns The value `*address & mask`.
- */
-#define SECURE_BITS_GET(address, mask) \
-    UVISOR_BITS_GET(public_box, UVISOR_RGW_SHARED, address, mask)
-
-/** Check the selected bits at the target address.
- *
- * @param address[in]  Address at which to check the bits
- * @param mask[in]     Bits to select out of the target address
- * @returns The value `((*address & mask) == mask)`.
- */
-#define SECURE_BITS_CHECK(address, mask) \
-    UVISOR_BITS_CHECK(public_box, UVISOR_RGW_SHARED, address, mask)
-
-/** Set the selected bits to 1 at the target address.
- *
- * Equivalent to: `*address |= mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_SET(address, mask) \
-    UVISOR_BITS_SET(public_box, UVISOR_RGW_SHARED, address, mask)
-
-/** Clear the selected bits at the target address.
- *
- * Equivalent to: `*address &= ~mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_CLEAR(address, mask) \
-    UVISOR_BITS_CLEAR(public_box, UVISOR_RGW_SHARED, address, mask)
-
-/** Set the selected bits at the target address to the given value.
- *
- * Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- * @param value[in]    Value to write at the address location. Note: The value
- *                     must be already shifted to the correct bit position
- */
-#define SECURE_BITS_SET_VALUE(address, mask, value) \
-    UVISOR_BITS_SET_VALUE(public_box, UVISOR_RGW_SHARED, address, mask, value)
-
-/** Toggle the selected bits at the target address.
- *
- * Equivalent to: `*address ^= mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_TOGGLE(address, mask) \
-    UVISOR_BITS_TOGGLE(public_box, UVISOR_RGW_SHARED, address, mask)
-
-#else
-
-/* Insecure fallback implementation. */
-
-/** Set the value at the target address.
- *
- * Equivalent to: `*address = value`.
- * @param address[in]  Target address
- * @param value[in]    Value to write at the address location.
- */
-#define SECURE_WRITE(address, value) \
-    *(address) = (value)
-
-/** Get the value at the target address.
- *
- * @param address[in]  Target address
- * @returns The value `*address`.
- */
-#define SECURE_READ(address) \
-    (*(address))
-
-/** Get the selected bits at the target address.
- *
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- * @returns The value `*address & mask`.
- */
-#define SECURE_BITS_GET(address, mask) \
-    (*(address) & (mask))
-
-/** Check the selected bits at the target address.
- *
- * @param address[in]  Address at which to check the bits
- * @param mask[in]     Bits to select out of the target address
- * @returns The value `((*address & mask) == mask)`.
- */
-#define SECURE_BITS_CHECK(address, mask) \
-    ((*(address) & (mask)) == (mask))
-
-/** Set the selected bits to 1 at the target address.
- *
- * Equivalent to: `*address |= mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_SET(address, mask) \
-    *(address) |= (mask)
-
-/** Clear the selected bits at the target address.
- *
- * Equivalent to: `*address &= ~mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_CLEAR(address, mask) \
-    *(address) &= ~(mask)
-
-/** Set the selected bits at the target address to the given value.
- *
- * Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- * @param value[in]    Value to write at the address location. Note: The value
- *                     must be already shifted to the correct bit position
- */
-#define SECURE_BITS_SET_VALUE(address, mask, value) \
-    *(address) = (*(address) & ~(mask)) | ((value) & (mask))
-
-/** Toggle the selected bits at the target address.
- *
- * Equivalent to: `*address ^= mask`.
- * @param address[in]  Target address
- * @param mask[in]     Bits to select out of the target address
- */
-#define SECURE_BITS_TOGGLE(address, mask) \
-    *(address) ^= (mask)
-
-#endif
-
-#endif /* __CORE_CM_SECURE_ACCESS_H */

--- a/cmsis/core_sc000.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1014 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc000.h
- * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup SC000
-  @{
- */
-
-/*  CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
-                                      __SC000_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __SC000_REV
-    #define __SC000_REV             0x0000U
-    #warning "__SC000_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-        uint32_t RESERVED1[154U];
-  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the SC000 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/core_sc300.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1901 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc300.h
- * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     13. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup SC3000
-  @{
- */
-
-/*  CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
-                                      __SC300_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC300_H_DEPENDANT
-#define __CORE_SC300_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __SC300_REV
-    #define __SC300_REV               0x0000U
-    #warning "__SC300_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC300 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
-    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[5U];
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-        uint32_t RESERVED1[129U];
-  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-        uint32_t RESERVED1[1U];
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

--- a/cmsis/tz_context.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * ----------------------------------------------------------------------------
- *
- * $Date:        21. September 2016
- * $Revision:    V1.0
- *
- * Project:      TrustZone for ARMv8-M
- * Title:        Context Management for ARMv8-M TrustZone
- *
- * Version 1.0
- *    Initial Release
- *---------------------------------------------------------------------------*/
-  
-#ifndef TZ_CONTEXT_H
-#define TZ_CONTEXT_H
- 
-#include <stdint.h>
- 
-#ifndef TZ_MODULEID_T
-#define TZ_MODULEID_T
-/// \details Data type that identifies secure software modules called by a process.
-typedef uint32_t TZ_ModuleId_t;
-#endif
- 
-/// \details TZ Memory ID identifies an allocated memory slot.
-typedef uint32_t TZ_MemoryId_t;
-  
-/// Initialize secure context memory system
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_InitContextSystem_S (void);
- 
-/// Allocate context memory for calling secure software modules in TrustZone
-/// \param[in]  module   identifies software modules called from non-secure mode
-/// \return value != 0 id TrustZone memory slot identifier
-/// \return value 0    no memory available or internal error
-TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
- 
-/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
- 
-/// Load secure context (called on RTOS thread context switch)
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
- 
-/// Store secure context (called on RTOS thread context switch)
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
- 
-#endif  // TZ_CONTEXT_H

--- a/drivers/I2C.cpp	Thu Dec 07 14:01:42 2017 +0000
+++ b/drivers/I2C.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -28,9 +28,10 @@
 
 I2C::I2C(PinName sda, PinName scl) :
 #if DEVICE_I2C_ASYNCH
-                                     _irq(this), _usage(DMA_USAGE_NEVER),
+    _irq(this), _usage(DMA_USAGE_NEVER), _deep_sleep_locked(false),
 #endif
-                                      _i2c(), _hz(100000) {
+    _i2c(), _hz(100000)
+{
     // No lock needed in the constructor
 
     // The init function also set the frequency to 100000
@@ -133,7 +134,7 @@
         unlock();
         return -1; // transaction ongoing
     }
-    sleep_manager_lock_deep_sleep();
+    lock_deep_sleep();
     aquire();
 
     _callback = callback;
@@ -148,7 +149,7 @@
 {
     lock();
     i2c_abort_asynch(&_i2c);
-    sleep_manager_unlock_deep_sleep();
+    unlock_deep_sleep();
     unlock();
 }
 
@@ -159,11 +160,26 @@
         _callback.call(event);
     }
     if (event) {
-        sleep_manager_unlock_deep_sleep();
+        unlock_deep_sleep();
     }
 
 }
 
+void I2C::lock_deep_sleep()
+{
+    if (_deep_sleep_locked == false) {
+        sleep_manager_lock_deep_sleep();
+        _deep_sleep_locked = true;
+    }
+}
+
+void I2C::unlock_deep_sleep()
+{
+    if (_deep_sleep_locked == true) {
+        sleep_manager_unlock_deep_sleep();
+        _deep_sleep_locked = false;
+    }
+}
 
 #endif
 

--- a/drivers/I2C.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/drivers/I2C.h	Wed Jan 17 15:23:54 2018 +0000
@@ -176,11 +176,19 @@
     /** Abort the on-going I2C transfer
      */
     void abort_transfer();
-protected:
+
+  protected:
+    /** Lock deep sleep only if it is not yet locked */
+    void lock_deep_sleep();
+
+    /** Unlock deep sleep only if it has been locked */
+    void unlock_deep_sleep();
+
     void irq_handler_asynch(void);
     event_callback_t _callback;
     CThunk<I2C> _irq;
     DMAUsage _usage;
+    bool _deep_sleep_locked;
 #endif
 
 protected:

--- a/drivers/InterruptManager.cpp	Thu Dec 07 14:01:42 2017 +0000
+++ b/drivers/InterruptManager.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -16,6 +16,12 @@
 #include "cmsis.h"
 #if defined(NVIC_NUM_VECTORS)
 
+// Suppress deprecation warnings since this whole
+// class is deprecated already
+#include "mbed_toolchain.h"
+#undef MBED_DEPRECATED_SINCE
+#define MBED_DEPRECATED_SINCE(...)
+
 #include "drivers/InterruptManager.h"
 #include "platform/mbed_critical.h"
 #include <string.h>

--- a/drivers/InterruptManager.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/drivers/InterruptManager.h	Wed Jan 17 15:23:54 2018 +0000
@@ -60,10 +60,14 @@
      *
      *  @return the only instance of this class
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     static InterruptManager* get();
 
     /** Destroy the current instance of the interrupt manager
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     static void destroy();
 
     /** Add a handler for an interrupt at the end of the handler list
@@ -74,6 +78,8 @@
      *  @returns
      *  The function object created for 'function'
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
         // Underlying call is thread safe
         return add_common(function, irq);
@@ -87,6 +93,8 @@
      *  @returns
      *  The function object created for 'function'
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
         // Underlying call is thread safe
         return add_common(function, irq, true);
@@ -102,6 +110,8 @@
      *  The function object created for 'tptr' and 'mptr'
      */
     template<typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
         // Underlying call is thread safe
         return add_common(tptr, mptr, irq);
@@ -117,6 +127,8 @@
      *  The function object created for 'tptr' and 'mptr'
      */
     template<typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
         // Underlying call is thread safe
         return add_common(tptr, mptr, irq, true);
@@ -130,6 +142,8 @@
      *  @returns
      *  true if the handler was found and removed, false otherwise
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
 
 private:

--- a/drivers/SPI.cpp	Thu Dec 07 14:01:42 2017 +0000
+++ b/drivers/SPI.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -33,6 +33,7 @@
 #if DEVICE_SPI_ASYNCH
         _irq(this),
         _usage(DMA_USAGE_NEVER),
+        _deep_sleep_locked(false),
 #endif
         _bits(8),
         _mode(0),
@@ -140,7 +141,7 @@
 void SPI::abort_transfer()
 {
     spi_abort_asynch(&_spi);
-    sleep_manager_unlock_deep_sleep();
+    unlock_deep_sleep();
 #if TRANSACTION_QUEUE_SIZE_SPI
     dequeue_transaction();
 #endif
@@ -200,13 +201,29 @@
 
 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
 {
-    sleep_manager_lock_deep_sleep();
+    lock_deep_sleep();
     _acquire();
     _callback = callback;
     _irq.callback(&SPI::irq_handler_asynch);
     spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
 }
 
+void SPI::lock_deep_sleep()
+{
+    if (_deep_sleep_locked == false) {
+        sleep_manager_lock_deep_sleep();
+        _deep_sleep_locked = true;
+    }
+}
+
+void SPI::unlock_deep_sleep()
+{
+    if (_deep_sleep_locked == true) {
+        sleep_manager_unlock_deep_sleep();
+        _deep_sleep_locked = false;
+    }
+}
+
 #if TRANSACTION_QUEUE_SIZE_SPI
 
 void SPI::start_transaction(transaction_t *data)
@@ -230,7 +247,7 @@
 {
     int event = spi_irq_handler_asynch(&_spi);
     if (_callback && (event & SPI_EVENT_ALL)) {
-        sleep_manager_unlock_deep_sleep();
+        unlock_deep_sleep();
         _callback.call(event & SPI_EVENT_ALL);
     }
 #if TRANSACTION_QUEUE_SIZE_SPI

--- a/drivers/SPI.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/drivers/SPI.h	Wed Jan 17 15:23:54 2018 +0000
@@ -246,6 +246,14 @@
     */
     void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
 
+private:
+    /** Lock deep sleep only if it is not yet locked */
+    void lock_deep_sleep();
+
+    /** Unlock deep sleep in case it is locked */
+    void unlock_deep_sleep();
+
+
 #if TRANSACTION_QUEUE_SIZE_SPI
 
     /** Start a new transaction
@@ -274,6 +282,7 @@
     CThunk<SPI> _irq;
     event_callback_t _callback;
     DMAUsage _usage;
+    bool _deep_sleep_locked;
 #endif
 
     void aquire(void);

--- a/drivers/UARTSerial.cpp	Thu Dec 07 14:01:42 2017 +0000
+++ b/drivers/UARTSerial.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -32,6 +32,7 @@
         SerialBase(tx, rx, baud),
         _blocking(true),
         _tx_irq_enabled(false),
+        _rx_irq_enabled(true),
         _dcd_irq(NULL)
 {
     /* Attatch IRQ routines to the serial device. */
@@ -68,6 +69,22 @@
     }
 }
 
+void UARTSerial::set_format(int bits, Parity parity, int stop_bits)
+{
+    api_lock();
+    SerialBase::format(bits, parity, stop_bits);
+    api_unlock();
+}
+
+#if DEVICE_SERIAL_FC
+void UARTSerial::set_flow_control(Flow type, PinName flow1, PinName flow2)
+{
+    api_lock();
+    SerialBase::set_flow_control(type, flow1, flow2);
+    api_unlock();
+}
+#endif
+
 int UARTSerial::close()
 {
     /* Does not let us pass a file descriptor. So how to close ?
@@ -121,36 +138,47 @@
     size_t data_written = 0;
     const char *buf_ptr = static_cast<const char *>(buffer);
 
-    api_lock();
-
-    while (_txbuf.full()) {
-        if (!_blocking) {
-            api_unlock();
-            return -EAGAIN;
-        }
-        api_unlock();
-        wait_ms(1); // XXX todo - proper wait, WFE for non-rtos ?
-        api_lock();
+    if (length == 0) {
+        return 0;
     }
 
-    while (data_written < length && !_txbuf.full()) {
-        _txbuf.push(*buf_ptr++);
-        data_written++;
-    }
+    api_lock();
+
+    // Unlike read, we should write the whole thing if blocking. POSIX only
+    // allows partial as a side-effect of signal handling; it normally tries to
+    // write everything if blocking. Without signals we can always write all.
+    while (data_written < length) {
 
-    core_util_critical_section_enter();
-    if (!_tx_irq_enabled) {
-        UARTSerial::tx_irq();                // only write to hardware in one place
-        if (!_txbuf.empty()) {
-            SerialBase::attach(callback(this, &UARTSerial::tx_irq), TxIrq);
-            _tx_irq_enabled = true;
+        if (_txbuf.full()) {
+            if (!_blocking) {
+                break;
+            }
+            do {
+                api_unlock();
+                wait_ms(1); // XXX todo - proper wait, WFE for non-rtos ?
+                api_lock();
+            } while (_txbuf.full());
         }
+
+        while (data_written < length && !_txbuf.full()) {
+            _txbuf.push(*buf_ptr++);
+            data_written++;
+        }
+
+        core_util_critical_section_enter();
+        if (!_tx_irq_enabled) {
+            UARTSerial::tx_irq();                // only write to hardware in one place
+            if (!_txbuf.empty()) {
+                SerialBase::attach(callback(this, &UARTSerial::tx_irq), TxIrq);
+                _tx_irq_enabled = true;
+            }
+        }
+        core_util_critical_section_exit();
     }
-    core_util_critical_section_exit();
 
     api_unlock();
 
-    return data_written;
+    return data_written != 0 ? (ssize_t) data_written : (ssize_t) -EAGAIN;
 }
 
 ssize_t UARTSerial::read(void* buffer, size_t length)
@@ -159,6 +187,10 @@
 
     char *ptr = static_cast<char *>(buffer);
 
+    if (length == 0) {
+        return 0;
+    }
+
     api_lock();
 
     while (_rxbuf.empty()) {
@@ -176,6 +208,16 @@
         data_read++;
     }
 
+    core_util_critical_section_enter();
+    if (!_rx_irq_enabled) {
+        UARTSerial::rx_irq();               // only read from hardware in one place
+        if (!_rxbuf.full()) {
+            SerialBase::attach(callback(this, &UARTSerial::rx_irq), RxIrq);
+            _rx_irq_enabled = true;
+        }
+    }
+    core_util_critical_section_exit();
+
     api_unlock();
 
     return data_read;
@@ -243,13 +285,14 @@
 
     /* Fill in the receive buffer if the peripheral is readable
      * and receive buffer is not full. */
-    while (SerialBase::readable()) {
+    while (!_rxbuf.full() && SerialBase::readable()) {
         char data = SerialBase::_base_getc();
-        if (!_rxbuf.full()) {
-            _rxbuf.push(data);
-        } else {
-            /* Drop - can we report in some way? */
-        }
+        _rxbuf.push(data);
+    }
+
+    if (_rx_irq_enabled && _rxbuf.full()) {
+        SerialBase::attach(NULL, RxIrq);
+        _rx_irq_enabled = false;
     }
 
     /* Report the File handler that data is ready to be read from the buffer. */

--- a/drivers/UARTSerial.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/drivers/UARTSerial.h	Wed Jan 17 15:23:54 2018 +0000
@@ -71,6 +71,12 @@
 
     /** Write the contents of a buffer to a file
      *
+     *  Follows POSIX semantics:
+     *
+     * * if blocking, block until all data is written
+     * * if no data can be written, and non-blocking set, return -EAGAIN
+     * * if some data can be written, and non-blocking set, write partial
+     *
      *  @param buffer   The buffer to write from
      *  @param length   The number of bytes to write
      *  @return         The number of bytes written, negative error on failure
@@ -171,6 +177,42 @@
      */
     void set_baud(int baud);
 
+    // Expose private SerialBase::Parity as UARTSerial::Parity
+    using SerialBase::Parity;
+    // In C++11, we wouldn't need to also have using directives for each value
+    using SerialBase::None;
+    using SerialBase::Odd;
+    using SerialBase::Even;
+    using SerialBase::Forced1;
+    using SerialBase::Forced0;
+
+    /** Set the transmission format used by the serial port
+     *
+     *  @param bits The number of bits in a word (5-8; default = 8)
+     *  @param parity The parity used (None, Odd, Even, Forced1, Forced0; default = None)
+     *  @param stop_bits The number of stop bits (1 or 2; default = 1)
+     */
+    void set_format(int bits=8, Parity parity=UARTSerial::None, int stop_bits=1);
+
+#if DEVICE_SERIAL_FC
+    // For now use the base enum - but in future we may have extra options
+    // such as XON/XOFF or manual GPIO RTSCTS.
+    using SerialBase::Flow;
+    // In C++11, we wouldn't need to also have using directives for each value
+    using SerialBase::Disabled;
+    using SerialBase::RTS;
+    using SerialBase::CTS;
+    using SerialBase::RTSCTS;
+
+    /** Set the flow control type on the serial port
+     *
+     *  @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+     *  @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+     *  @param flow2 the second flow control pin (CTS for RTSCTS)
+     */
+    void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
+#endif
+
 private:
 
     void wait_ms(uint32_t millisec);
@@ -199,6 +241,7 @@
 
     bool _blocking;
     bool _tx_irq_enabled;
+    bool _rx_irq_enabled;
     InterruptIn *_dcd_irq;
 
     /** Device Hanged up

--- a/hal/lp_ticker_api.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/hal/lp_ticker_api.h	Wed Jan 17 15:23:54 2018 +0000
@@ -34,6 +34,20 @@
  * @{
  */
 
+typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
+
+/** Set low power ticker IRQ handler
+ *
+ * @param ticker_irq_handler IRQ handler to be connected
+ *
+ * @return previous ticker IRQ handler
+ *
+ * @note by default IRQ handler is set to ticker_irq_handler()
+ * @note this function is primarily for testing purposes and it's not required part of HAL implementation
+ *
+ */
+ticker_irq_handler_type set_lp_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler);
+
 /** Get low power ticker's data
  *
  * @return The low power ticker data
@@ -80,6 +94,11 @@
  */
 void lp_ticker_fire_interrupt(void);
 
+/** Get frequency and counter bits of this ticker.
+ *
+ */
+const ticker_info_t* lp_ticker_get_info(void);
+
 /**@}*/
 
 #ifdef __cplusplus

--- a/hal/mbed_lp_ticker_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/hal/mbed_lp_ticker_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -19,6 +19,8 @@
 
 static ticker_event_queue_t events = { 0 };
 
+static ticker_irq_handler_type irq_handler = ticker_irq_handler;
+
 static const ticker_interface_t lp_interface = {
     .init = lp_ticker_init,
     .read = lp_ticker_read,
@@ -26,6 +28,7 @@
     .clear_interrupt = lp_ticker_clear_interrupt,
     .set_interrupt = lp_ticker_set_interrupt,
     .fire_interrupt = lp_ticker_fire_interrupt,
+    .get_info = lp_ticker_get_info,
 };
 
 static const ticker_data_t lp_data = {
@@ -38,9 +41,20 @@
     return &lp_data;
 }
 
+ticker_irq_handler_type set_lp_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler)
+{
+    ticker_irq_handler_type prev_irq_handler = irq_handler;
+
+    irq_handler = ticker_irq_handler;
+
+    return prev_irq_handler;
+}
+
 void lp_ticker_irq_handler(void)
 {
-    ticker_irq_handler(&lp_data);
+    if (irq_handler) {
+        irq_handler(&lp_data);
+    }
 }
 
 #endif

--- a/hal/mbed_ticker_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/hal/mbed_ticker_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -17,6 +17,7 @@
 #include <stddef.h>
 #include "hal/ticker_api.h"
 #include "platform/mbed_critical.h"
+#include "mbed_assert.h"
 
 static void schedule_interrupt(const ticker_data_t *const ticker);
 static void update_present_time(const ticker_data_t *const ticker);
@@ -33,9 +34,31 @@
     }
 
     ticker->interface->init();
-    
+
+    const ticker_info_t *info = ticker->interface->get_info();
+    uint32_t frequency = info->frequency;
+    if (info->frequency == 0) {
+        MBED_ASSERT(0);
+        frequency = 1000000;
+    }
+
+    uint32_t bits = info->bits;
+    if ((info->bits > 32) || (info->bits < 4)) {
+        MBED_ASSERT(0);
+        bits = 32;
+    }
+    uint32_t max_delta = 0x7 << (bits - 4); // 7/16th
+    uint64_t max_delta_us =
+            ((uint64_t)max_delta * 1000000 + frequency - 1) / frequency;
+
     ticker->queue->event_handler = NULL;
     ticker->queue->head = NULL;
+    ticker->queue->tick_last_read = ticker->interface->read();
+    ticker->queue->tick_remainder = 0;
+    ticker->queue->frequency = frequency;
+    ticker->queue->bitmask = ((uint64_t)1 << bits) - 1;
+    ticker->queue->max_delta = max_delta;
+    ticker->queue->max_delta_us = max_delta_us;
     ticker->queue->present_time = 0;
     ticker->queue->initialized = true;
     
@@ -86,53 +109,143 @@
  * Update the present timestamp value of a ticker.
  */
 static void update_present_time(const ticker_data_t *const ticker)
-{ 
-    ticker->queue->present_time = convert_timestamp(
-        ticker->queue->present_time, 
-        ticker->interface->read()
-    );
+{
+
+    ticker_event_queue_t *queue = ticker->queue;
+    uint32_t ticker_time = ticker->interface->read();
+    if (ticker_time == ticker->queue->tick_last_read) {
+        // No work to do
+        return;
+    }
+
+    uint64_t elapsed_ticks = (ticker_time - queue->tick_last_read) & queue->bitmask;
+    queue->tick_last_read = ticker_time;
+
+    uint64_t elapsed_us;
+    if (1000000 == queue->frequency) {
+        // Optimized for 1MHz
+
+        elapsed_us = elapsed_ticks;
+    } else if (32768 == queue->frequency) {
+        // Optimized for 32KHz
+
+        uint64_t us_x_ticks = elapsed_ticks * 1000000;
+        elapsed_us = us_x_ticks >> 15;
+
+        // Update remainder
+        queue->tick_remainder += us_x_ticks - (elapsed_us << 15);
+        if (queue->tick_remainder >= queue->frequency) {
+            elapsed_us += 1;
+            queue->tick_remainder -= queue->frequency;
+        }
+    } else {
+        // General case
+
+        uint64_t us_x_ticks = elapsed_ticks * 1000000;
+        elapsed_us = us_x_ticks / queue->frequency;
+
+        // Update remainder
+        queue->tick_remainder += us_x_ticks - elapsed_us * queue->frequency;
+        if (queue->tick_remainder >= queue->frequency) {
+            elapsed_us += 1;
+            queue->tick_remainder -= queue->frequency;
+        }
+    }
+
+    // Update current time
+    queue->present_time += elapsed_us;
+}
+
+/**
+ * Given the absolute timestamp compute the hal tick timestamp.
+ */
+static timestamp_t compute_tick(const ticker_data_t *const ticker, us_timestamp_t timestamp)
+{
+    ticker_event_queue_t *queue = ticker->queue;
+    us_timestamp_t delta_us = timestamp - queue->present_time;
+
+    timestamp_t delta = ticker->queue->max_delta;
+    if (delta_us <=  ticker->queue->max_delta_us) {
+        // Checking max_delta_us ensures the operation will not overflow
+
+        if (1000000 == queue->frequency) {
+            // Optimized for 1MHz
+
+            delta = delta_us;
+            if (delta > ticker->queue->max_delta) {
+                delta = ticker->queue->max_delta;
+            }
+        } else if (32768 == queue->frequency) {
+            // Optimized for 32KHz
+
+            delta = (delta_us << 15) / 1000000;
+            if (delta > ticker->queue->max_delta) {
+                delta = ticker->queue->max_delta;
+            }
+        } else {
+            // General case
+
+            delta = delta_us * queue->frequency / 1000000;
+            if (delta > ticker->queue->max_delta) {
+                delta = ticker->queue->max_delta;
+            }
+        }
+    }
+    return (queue->tick_last_read + delta) & queue->bitmask;
+}
+
+/**
+ * Return 1 if the tick has incremented to or past match_tick, otherwise 0.
+ */
+int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick)
+{
+    if (match_tick > prev_tick) {
+        return (cur_tick >= match_tick) || (cur_tick < prev_tick);
+    } else {
+        return (cur_tick < prev_tick) && (cur_tick >= match_tick);
+    }
 }
 
 /**
  * Compute the time when the interrupt has to be triggered and schedule it.  
  * 
  * If there is no event in the queue or the next event to execute is in more 
- * than MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA us from now then the ticker 
- * irq will be scheduled in MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA us.
- * Otherwise the irq will be scheduled to happen when the running counter reach 
- * the timestamp of the first event in the queue.
+ * than ticker.queue.max_delta ticks from now then the ticker irq will be
+ * scheduled in ticker.queue.max_delta ticks. Otherwise the irq will be
+ * scheduled to happen when the running counter reach the timestamp of the
+ * first event in the queue.
  * 
  * @note If there is no event in the queue then the interrupt is scheduled to 
- * in MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA. This is necessary to keep track 
+ * in ticker.queue.max_delta. This is necessary to keep track
  * of the timer overflow.
  */
 static void schedule_interrupt(const ticker_data_t *const ticker)
 {
+    ticker_event_queue_t *queue = ticker->queue;
     update_present_time(ticker);
-    uint32_t relative_timeout = MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA;
 
     if (ticker->queue->head) {
         us_timestamp_t present = ticker->queue->present_time;
-        us_timestamp_t next_event_timestamp = ticker->queue->head->timestamp;
+        us_timestamp_t match_time = ticker->queue->head->timestamp;
 
         // if the event at the head of the queue is in the past then schedule
         // it immediately.
-        if (next_event_timestamp <= present) {
+        if (match_time <= present) {
             ticker->interface->fire_interrupt();
             return;
-        } else if ((next_event_timestamp - present) < MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA) {
-            relative_timeout = next_event_timestamp - present;
         }
-    } 
+
+        timestamp_t match_tick = compute_tick(ticker, match_time);
+        ticker->interface->set_interrupt(match_tick);
+        timestamp_t cur_tick = ticker->interface->read();
 
-    us_timestamp_t new_match_time = ticker->queue->present_time + relative_timeout;
-    ticker->interface->set_interrupt(new_match_time);
-    // there could be a delay, reread the time, check if it was set in the past
-    // As result, if it is already in the past, we fire it immediately
-    update_present_time(ticker);
-    us_timestamp_t present = ticker->queue->present_time;
-    if (present >= new_match_time) {
-        ticker->interface->fire_interrupt();
+        if (_ticker_match_interval_passed(queue->tick_last_read, cur_tick, match_tick)) {
+            ticker->interface->fire_interrupt();
+        }
+    } else {
+        uint32_t match_tick =
+                (queue->tick_last_read + queue->max_delta) & queue->bitmask;
+        ticker->interface->set_interrupt(match_tick);
     }
 }
 

--- a/hal/mbed_us_ticker_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/hal/mbed_us_ticker_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -17,6 +17,8 @@
 
 static ticker_event_queue_t events = { 0 };
 
+static ticker_irq_handler_type irq_handler = ticker_irq_handler;
+
 static const ticker_interface_t us_interface = {
     .init = us_ticker_init,
     .read = us_ticker_read,
@@ -24,6 +26,7 @@
     .clear_interrupt = us_ticker_clear_interrupt,
     .set_interrupt = us_ticker_set_interrupt,
     .fire_interrupt = us_ticker_fire_interrupt,
+    .get_info = us_ticker_get_info,
 };
 
 static const ticker_data_t us_data = {
@@ -36,7 +39,18 @@
     return &us_data;
 }
 
+ticker_irq_handler_type set_us_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler)
+{
+    ticker_irq_handler_type prev_irq_handler = irq_handler;
+
+    irq_handler = ticker_irq_handler;
+
+    return prev_irq_handler;
+}
+
 void us_ticker_irq_handler(void)
 {
-    ticker_irq_handler(&us_data);
+    if (irq_handler) {
+        irq_handler(&us_data);
+    }
 }

--- a/hal/ticker_api.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/hal/ticker_api.h	Wed Jan 17 15:23:54 2018 +0000
@@ -24,11 +24,6 @@
 #include "device.h"
 
 /**
- * Maximum delta (in us) between too interrupts.
- */
-#define MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA   0x70000000ULL
-
-/**
  * Legacy format representing a timestamp in us.
  * Given it is modeled as a 32 bit integer, this type can represent timestamp
  * up to 4294 seconds (71 minutes).
@@ -52,6 +47,14 @@
 
 typedef void (*ticker_event_handler)(uint32_t id);
 
+/** Information about the ticker implementation
+ */
+typedef struct {
+    uint32_t frequency;                           /**< Frequency in Hz this ticker runs at */
+    uint32_t bits;                                /**< Number of bits this ticker supports */
+} ticker_info_t;
+
+
 /** Ticker's interface structure - required API for a ticker
  */
 typedef struct {
@@ -61,6 +64,7 @@
     void (*clear_interrupt)(void);                /**< Clear interrupt function */
     void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
     void (*fire_interrupt)(void);                 /**< Fire interrupt right-away */
+    const ticker_info_t *(*get_info)(void);       /**< Return info about this ticker's implementation */
 } ticker_interface_t;
 
 /** Ticker's event queue structure
@@ -68,6 +72,12 @@
 typedef struct {
     ticker_event_handler event_handler; /**< Event handler */
     ticker_event_t *head;               /**< A pointer to head */
+    uint32_t frequency;                 /**< Frequency of the timer in Hz */
+    uint32_t bitmask;                   /**< Mask to be applied to time values read */
+    uint32_t max_delta;                 /**< Largest delta in ticks that can be used when scheduling */
+    uint64_t max_delta_us;              /**< Largest delta in us that can be used when scheduling */
+    uint32_t tick_last_read;            /**< Last tick read */
+    uint64_t tick_remainder;            /**< Ticks that have not been added to base_time */
     us_timestamp_t present_time;        /**< Store the timestamp used for present time */
     bool initialized;                   /**< Indicate if the instance is initialized */
 } ticker_event_queue_t;
@@ -171,6 +181,19 @@
  */
 int ticker_get_next_timestamp(const ticker_data_t *const ticker, timestamp_t *timestamp);
 
+/* Private functions
+ *
+ * @cond PRIVATE
+ *
+ */
+
+int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick);
+
+/*
+ * @endcond PRIVATE
+ *
+ */
+
 /**@}*/
 
 #ifdef __cplusplus

--- a/hal/us_ticker_api.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/hal/us_ticker_api.h	Wed Jan 17 15:23:54 2018 +0000
@@ -31,6 +31,20 @@
  * @{
  */
 
+typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
+
+/** Set ticker IRQ handler
+ *
+ * @param ticker_irq_handler IRQ handler to be connected
+ *
+ * @return previous ticker IRQ handler
+ *
+ * @note by default IRQ handler is set to ticker_irq_handler()
+ * @note this function is primarily for testing purposes and it's not required part of HAL implementation
+ *
+ */
+ticker_irq_handler_type set_us_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler);
+
 /** Get ticker's data
  *
  * @return The low power ticker data
@@ -78,6 +92,11 @@
  */
 void us_ticker_fire_interrupt(void);
 
+/** Get frequency and counter bits of this ticker.
+ *
+ */
+const ticker_info_t* us_ticker_get_info(void);
+
 /**@}*/
 
 #ifdef __cplusplus

--- a/mbed.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/mbed.h	Wed Jan 17 15:23:54 2018 +0000
@@ -16,13 +16,13 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 157
+#define MBED_LIBRARY_VERSION 158
 
 #if MBED_CONF_RTOS_PRESENT
 // RTOS present, this is valid only for mbed OS 5
 #define MBED_MAJOR_VERSION 5
-#define MBED_MINOR_VERSION 6
-#define MBED_PATCH_VERSION 6
+#define MBED_MINOR_VERSION 7
+#define MBED_PATCH_VERSION 3
 
 #else
 // mbed 2
@@ -32,8 +32,7 @@
 #endif
 
 #define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch))
-#define MBED_VERSION MBED_ENCODE_VERSION(MBED_MAJOR_VERSION, MBED_MINOR_VERSION, MBED_PATCH_VERSION)
-
+#define MBED_VERSION MBED_ENCODE_VERSION(MBED_MAJOR_VERSION, MBED_MINOR_VERSION, MBED_PATCH_VERSION)        
 #if MBED_CONF_RTOS_PRESENT
 #include "rtos/rtos.h"
 #endif

--- a/platform/CThunk.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/CThunk.h	Wed Jan 17 15:23:54 2018 +0000
@@ -222,15 +222,15 @@
                 uint32_t start_addr = (uint32_t)&m_thunk & 0xFFFFFFE0;
                 uint32_t end_addr   = (uint32_t)&m_thunk + sizeof(m_thunk);
                 uint32_t addr;
-                
+
                 /* Data cache clean and invalid */
                 for (addr = start_addr; addr < end_addr; addr += 0x20) {
-                    __v7_clean_inv_dcache_mva((void *)addr);
+                    L1C_CleanInvalidateDCacheMVA((void *)addr);
                 }
                 /* Instruction cache invalid */
-                __v7_inv_icache_all();
-                __ca9u_inv_tlb_all();
-                __v7_inv_btac();
+                L1C_InvalidateICacheAll();
+                MMU_InvalidateTLB();
+                L1C_InvalidateBTAC();
             }
 #endif
 #if defined(__CORTEX_M7)

--- a/platform/CallChain.cpp	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/CallChain.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -1,3 +1,10 @@
+
+// Suppress deprecation warnings since this whole
+// class is deprecated already
+#include "mbed_toolchain.h"
+#undef MBED_DEPRECATED_SINCE
+#define MBED_DEPRECATED_SINCE(...)
+
 #include "platform/CallChain.h"
 #include "cmsis.h"
 #include "platform/mbed_critical.h"

--- a/platform/CallChain.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/CallChain.h	Wed Jan 17 15:23:54 2018 +0000
@@ -77,7 +77,12 @@
      *
      *  @param size (optional) Initial size of the chain
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     CallChain(int size = 4);
+
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     virtual ~CallChain();
 
     /** Add a function at the end of the chain
@@ -87,6 +92,8 @@
      *  @returns
      *  The function object created for 'func'
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     pFunctionPointer_t add(Callback<void()> func);
 
     /** Add a function at the end of the chain
@@ -116,6 +123,8 @@
      *  @returns
      *  The function object created for 'func'
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     pFunctionPointer_t add_front(Callback<void()> func);
 
     /** Add a function at the beginning of the chain
@@ -140,6 +149,8 @@
 
     /** Get the number of functions in the chain
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     int size() const;
 
     /** Get a function object from the chain
@@ -149,6 +160,8 @@
      *  @returns
      *  The function object at position 'i' in the chain
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     pFunctionPointer_t get(int i) const;
 
     /** Look for a function object in the call chain
@@ -158,10 +171,14 @@
      *  @returns
      *  The index of the function object if found, -1 otherwise.
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     int find(pFunctionPointer_t f) const;
 
     /** Clear the call chain (remove all functions in the chain).
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     void clear();
 
     /** Remove a function object from the chain
@@ -171,15 +188,24 @@
      *  @returns
      *  true if the function object was found and removed, false otherwise.
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     bool remove(pFunctionPointer_t f);
 
     /** Call all the functions in the chain in sequence
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     void call();
 
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     void operator ()(void) {
         call();
     }
+
+    MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+        "public API of mbed-os and is being removed in the future.")
     pFunctionPointer_t operator [](int i) const {
         return get(i);
     }

--- a/platform/CircularBuffer.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/CircularBuffer.h	Wed Jan 17 15:23:54 2018 +0000
@@ -109,6 +109,23 @@
         core_util_critical_section_exit();
     }
 
+    /** Get the number of elements currently stored in the circular_buffer */
+    CounterType size() const {
+        core_util_critical_section_enter();
+        CounterType elements;
+        if (!_full) {
+            if (_head < _tail) {
+                elements = BufferSize + _head - _tail;
+            } else {
+                elements = _head - _tail;
+            }
+        } else {
+            elements = BufferSize;
+        }
+        core_util_critical_section_exit();
+        return elements;
+    }
+    
 private:
     T _pool[BufferSize];
     volatile CounterType _head;

--- a/platform/FileHandle.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/FileHandle.h	Wed Jan 17 15:23:54 2018 +0000
@@ -51,7 +51,7 @@
      *  Devices acting as FileHandles should follow POSIX semantics:
      *
      *  * if no data is available, and non-blocking set return -EAGAIN
-     *  * if no data is available, and blocking set, wait until data is available
+     *  * if no data is available, and blocking set, wait until some data is available
      *  * If any data is available, call returns immediately
      *
      *  @param buffer   The buffer to read in to
@@ -62,6 +62,12 @@
 
     /** Write the contents of a buffer to a file
      *
+     *  Devices acting as FileHandles should follow POSIX semantics:
+     *
+     * * if blocking, block until all data is written
+     * * if no data can be written, and non-blocking set, return -EAGAIN
+     * * if some data can be written, and non-blocking set, write partial
+     *
      *  @param buffer   The buffer to write from
      *  @param size     The number of bytes to write 
      *  @return         The number of bytes written, negative error on failure

--- a/platform/NonCopyable.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/NonCopyable.h	Wed Jan 17 15:23:54 2018 +0000
@@ -16,153 +16,196 @@
 #ifndef MBED_NONCOPYABLE_H_
 #define MBED_NONCOPYABLE_H_
 
-namespace mbed { 
+#if (!defined(MBED_DEBUG) && (MBED_CONF_PLATFORM_FORCE_NON_COPYABLE_ERROR == 0))
+#include "mbed_toolchain.h"
+#include "mbed_debug.h"
+#endif
+
+namespace mbed {
 
 /**
- * Inheriting from this class autogeneration of copy construction and copy 
- * assignement operations. 
- * 
- * Classes which are not value type should inherit privately from this class 
+ * Inheriting from this class autogeneration of copy construction and copy
+ * assignement operations.
+ *
+ * Classes which are not value type should inherit privately from this class
  * to avoid generation of invalid copy constructor or copy assignement operator
- * which can lead to unoticeable programming errors. 
- * 
- * As an example consider the following signature: 
- * 
+ * which can lead to unoticeable programming errors.
+ *
+ * As an example consider the following signature:
+ *
  * @code
- * class Resource; 
+ * class Resource;
  *
- * class Foo { 
- * public:     
+ * class Foo {
+ * public:
  *   Foo() : _resource(new Resource()) { }
- *   ~Foo() { delete _resource; } 
+ *   ~Foo() { delete _resource; }
  * private:
  *   Resource* _resource;
  * }
- * 
+ *
  * Foo get_foo();
- * 
+ *
  * Foo foo = get_foo();
- * @endcode 
- * 
- * There is a bug in this function, it returns a temporary value which will be 
- * byte copied into foo then destroyed. Unfortunately, internaly the Foo class 
- * manage a pointer to a Resource object. This pointer will be released when the 
- * temporary is destroyed and foo will manage a pointer to an already released 
+ * @endcode
+ *
+ * There is a bug in this function, it returns a temporary value which will be
+ * byte copied into foo then destroyed. Unfortunately, internaly the Foo class
+ * manage a pointer to a Resource object. This pointer will be released when the
+ * temporary is destroyed and foo will manage a pointer to an already released
  * Resource.
- * 
- * Two issues has to be fixed in the example above: 
- *   - Function signature has to be changed to reflect the fact that Foo 
- *     instances cannot be copied. In that case accessor should return a 
- *     reference to give access to objects already existing and managed. 
+ *
+ * Two issues has to be fixed in the example above:
+ *   - Function signature has to be changed to reflect the fact that Foo
+ *     instances cannot be copied. In that case accessor should return a
+ *     reference to give access to objects already existing and managed.
  *     Generator on the other hand should return a pointer to the created object.
- * 
- * @code 
+ *
+ * @code
  * // return a reference to an already managed Foo instance
- * Foo& get_foo(); 
+ * Foo& get_foo();
  * Foo& foo = get_foo();
- * 
+ *
  * // create a new Foo instance
  * Foo* make_foo();
  * Foo* m = make_foo();
  * @endcode
- * 
- *   - Copy constructor and copy assignement operator has to be made private 
- *     in the Foo class. It prevents unwanted copy of Foo objects. This can be 
- *     done by declaring copy constructor and copy assignement in the private 
+ *
+ *   - Copy constructor and copy assignement operator has to be made private
+ *     in the Foo class. It prevents unwanted copy of Foo objects. This can be
+ *     done by declaring copy constructor and copy assignement in the private
  *     section of the Foo class.
- *     
- * @code 
- * class Foo { 
- * public:     
+ *
+ * @code
+ * class Foo {
+ * public:
  *   Foo() : _resource(new Resource()) { }
- *   ~Foo() { delete _resource; } 
+ *   ~Foo() { delete _resource; }
  * private:
- *   // disallow copy operations 
+ *   // disallow copy operations
  *   Foo(const Foo&);
  *   Foo& operator=(const Foo&);
- *   // data members 
+ *   // data members
  *   Resource* _resource;
  * }
  * @endcode
- * 
- * Another solution is to inherit privately from the NonCopyable class. 
- * It reduces the boiler plate needed to avoid copy operations but more 
+ *
+ * Another solution is to inherit privately from the NonCopyable class.
+ * It reduces the boiler plate needed to avoid copy operations but more
  * importantly it clarifies the programer intent and the object semantic.
  *
- * class Foo : private NonCopyable<Foo> { 
- * public:     
+ * class Foo : private NonCopyable<Foo> {
+ * public:
  *   Foo() : _resource(new Resource()) { }
- *   ~Foo() { delete _resource; } 
+ *   ~Foo() { delete _resource; }
  * private:
  *   Resource* _resource;
  * }
- * 
- * @tparam T The type that should be made non copyable. It prevent cases where 
- * the empty base optimization cannot be applied and therefore ensure that the 
- * cost of this semantic sugar is null. 
- * 
- * As an example, the empty base optimization is prohibited if one of the empty 
- * base class is also a base type of the first non static data member: 
- * 
- * @code 
+ *
+ * @tparam T The type that should be made non copyable. It prevent cases where
+ * the empty base optimization cannot be applied and therefore ensure that the
+ * cost of this semantic sugar is null.
+ *
+ * As an example, the empty base optimization is prohibited if one of the empty
+ * base class is also a base type of the first non static data member:
+ *
+ * @code
  * struct A { };
- * struct B : A { 
+ * struct B : A {
  *    int foo;
  * };
  * // thanks to empty base optimization, sizeof(B) == sizeof(int)
- * 
- * struct C : A { 
+ *
+ * struct C : A {
  *   B b;
  * };
- * 
+ *
  * // empty base optimization cannot be applied here because A from C and A from
- * // B shall have a different address. In that case, with the alignement 
+ * // B shall have a different address. In that case, with the alignement
  * // sizeof(C) == 2* sizeof(int)
  * @endcode
- * 
- * The solution to that problem is to templatize the empty class to makes it 
- * unique to the type it is applied to: 
- * 
- * @code 
+ *
+ * The solution to that problem is to templatize the empty class to makes it
+ * unique to the type it is applied to:
+ *
+ * @code
  * template<typename T>
  * struct A<T> { };
- * struct B : A<B> { 
+ * struct B : A<B> {
  *    int foo;
  * };
- * struct C : A<C> { 
+ * struct C : A<C> {
  *   B b;
  * };
- * 
- * // empty base optimization can be applied B and C does not refer to the same 
+ *
+ * // empty base optimization can be applied B and C does not refer to the same
  * // kind of A. sizeof(C) == sizeof(B) == sizeof(int).
  * @endcode
+ *
+ * @note Compile time errors are disabled if the develop or the release profile
+ * is used. To override this behavior and force compile time errors in all profile
+ * set the configuration parameter "platform.force-non-copyable-error" to true.
  */
 template<typename T>
-class NonCopyable { 
+class NonCopyable {
 protected:
-    /** 
+    /**
      * Disalow construction of NonCopyable objects from outside of its hierarchy.
      */
     NonCopyable() { }
-    /** 
+    /**
      * Disalow destruction of NonCopyable objects from outside of its hierarchy.
      */
     ~NonCopyable() { }
 
-private: 
+#if (!defined(MBED_DEBUG) && (MBED_CONF_PLATFORM_FORCE_NON_COPYABLE_ERROR == 0))
+    /**
+     * NonCopyable copy constructor.
+     *
+     * A compile time warning is issued when this function is used and a runtime
+     * warning is printed when the copy construction of the non copyable happens.
+     *
+     * If you see this warning, your code is probably doing something unspecified.
+     * Copy of non copyable resources can lead to resource leak and random error.
+     */
+    MBED_DEPRECATED("Invalid copy construction of a NonCopyable resource.")
+    NonCopyable(const NonCopyable&)
+    {
+        debug("Invalid copy construction of a NonCopyable resource: %s\r\n", MBED_PRETTY_FUNCTION);
+    }
+
     /**
-     * Declare copy constructor as private, any attempt to copy construct 
+     * NonCopyable copy assignment operator.
+     *
+     * A compile time warning is issued when this function is used and a runtime
+     * warning is printed when the copy construction of the non copyable happens.
+     *
+     * If you see this warning, your code is probably doing something unspecified.
+     * Copy of non copyable resources can lead to resource leak and random error.
+     */
+    MBED_DEPRECATED("Invalid copy assignment of a NonCopyable resource.")
+    NonCopyable& operator=(const NonCopyable&)
+    {
+        debug("Invalid copy assignment of a NonCopyable resource: %s\r\n", MBED_PRETTY_FUNCTION);
+        return *this;
+    }
+
+#else
+private:
+    /**
+     * Declare copy constructor as private, any attempt to copy construct
      * a NonCopyable will fail at compile time.
      */
     NonCopyable(const NonCopyable&);
 
     /**
-     * Declare copy assignement operator as private, any attempt to copy assign 
+     * Declare copy assignement operator as private, any attempt to copy assign
      * a NonCopyable will fail at compile time.
      */
     NonCopyable& operator=(const NonCopyable&);
+#endif
 };
 
-} // namespace mbed 
+} // namespace mbed
 
 #endif /* MBED_NONCOPYABLE_H_ */

--- a/platform/mbed_alloc_wrappers.cpp	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/mbed_alloc_wrappers.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -46,9 +46,6 @@
     uint32_t pad;
 } alloc_info_t;
 
-#ifdef MBED_MEM_TRACING_ENABLED
-static SingletonPtr<PlatformMutex> mem_trace_mutex;
-#endif
 #ifdef MBED_HEAP_STATS_ENABLED
 static SingletonPtr<PlatformMutex> malloc_stats_mutex;
 static mbed_stats_heap_t heap_stats = {0, 0, 0, 0, 0};
@@ -91,6 +88,9 @@
 
 extern "C" void * __wrap__malloc_r(struct _reent * r, size_t size) {
     void *ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+    mbed_mem_trace_lock();
+#endif
 #ifdef MBED_HEAP_STATS_ENABLED
     malloc_stats_mutex->lock();
     alloc_info_t *alloc_info = (alloc_info_t*)__real__malloc_r(r, size + sizeof(alloc_info_t));
@@ -111,15 +111,17 @@
     ptr = __real__malloc_r(r, size);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
-    mem_trace_mutex->lock();
     mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR());
-    mem_trace_mutex->unlock();
+    mbed_mem_trace_unlock();
 #endif // #ifdef MBED_MEM_TRACING_ENABLED
     return ptr;
 }
 
 extern "C" void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) {
     void *new_ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+    mbed_mem_trace_lock();
+#endif
 #ifdef MBED_HEAP_STATS_ENABLED
     // Implement realloc_r with malloc and free.
     // The function realloc_r can't be used here directly since
@@ -151,14 +153,16 @@
     new_ptr = __real__realloc_r(r, ptr, size);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
-    mem_trace_mutex->lock();
     mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
-    mem_trace_mutex->unlock();
+    mbed_mem_trace_unlock();
 #endif // #ifdef MBED_MEM_TRACING_ENABLED
     return new_ptr;
 }
 
 extern "C" void __wrap__free_r(struct _reent * r, void * ptr) {
+#ifdef MBED_MEM_TRACING_ENABLED
+    mbed_mem_trace_lock();
+#endif
 #ifdef MBED_HEAP_STATS_ENABLED
     malloc_stats_mutex->lock();
     alloc_info_t *alloc_info = NULL;
@@ -173,14 +177,16 @@
     __real__free_r(r, ptr);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
-    mem_trace_mutex->lock();
     mbed_mem_trace_free(ptr, MBED_CALLER_ADDR());
-    mem_trace_mutex->unlock();
+    mbed_mem_trace_unlock();
 #endif // #ifdef MBED_MEM_TRACING_ENABLED
 }
 
 extern "C" void * __wrap__calloc_r(struct _reent * r, size_t nmemb, size_t size) {
     void *ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+    mbed_mem_trace_lock();
+#endif
 #ifdef MBED_HEAP_STATS_ENABLED
     // Note - no lock needed since malloc is thread safe
 
@@ -192,9 +198,8 @@
     ptr = __real__calloc_r(r, nmemb, size);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
-    mem_trace_mutex->lock();
     mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
-    mem_trace_mutex->unlock();
+    mbed_mem_trace_unlock();
 #endif // #ifdef MBED_MEM_TRACING_ENABLED
     return ptr;
 }
@@ -244,6 +249,9 @@
 
 extern "C" void* SUB_MALLOC(size_t size) {
     void *ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+    mbed_mem_trace_lock();
+#endif
 #ifdef MBED_HEAP_STATS_ENABLED
     malloc_stats_mutex->lock();
     alloc_info_t *alloc_info = (alloc_info_t*)SUPER_MALLOC(size + sizeof(alloc_info_t));
@@ -264,15 +272,17 @@
     ptr = SUPER_MALLOC(size);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
-    mem_trace_mutex->lock();
     mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR());
-    mem_trace_mutex->unlock();
+    mbed_mem_trace_unlock();
 #endif // #ifdef MBED_MEM_TRACING_ENABLED
     return ptr;
 }
 
 extern "C" void* SUB_REALLOC(void *ptr, size_t size) {
     void *new_ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+    mbed_mem_trace_lock();
+#endif
 #ifdef MBED_HEAP_STATS_ENABLED
     // Note - no lock needed since malloc and free are thread safe
 
@@ -299,15 +309,17 @@
     new_ptr = SUPER_REALLOC(ptr, size);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
-    mem_trace_mutex->lock();
     mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
-    mem_trace_mutex->unlock();
+    mbed_mem_trace_unlock();
 #endif // #ifdef MBED_MEM_TRACING_ENABLED
     return new_ptr;
 }
 
 extern "C" void *SUB_CALLOC(size_t nmemb, size_t size) {
     void *ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+    mbed_mem_trace_lock();
+#endif
 #ifdef MBED_HEAP_STATS_ENABLED
     // Note - no lock needed since malloc is thread safe
     ptr = malloc(nmemb * size);
@@ -318,14 +330,16 @@
     ptr = SUPER_CALLOC(nmemb, size);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
-    mem_trace_mutex->lock();
     mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
-    mem_trace_mutex->unlock();
+    mbed_mem_trace_unlock();
 #endif // #ifdef MBED_MEM_TRACING_ENABLED
     return ptr;
 }
 
 extern "C" void SUB_FREE(void *ptr) {
+#ifdef MBED_MEM_TRACING_ENABLED
+    mbed_mem_trace_lock();
+#endif
 #ifdef MBED_HEAP_STATS_ENABLED
     malloc_stats_mutex->lock();
     alloc_info_t *alloc_info = NULL;
@@ -340,9 +354,8 @@
     SUPER_FREE(ptr);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
-    mem_trace_mutex->lock();
     mbed_mem_trace_free(ptr, MBED_CALLER_ADDR());
-    mem_trace_mutex->unlock();
+    mbed_mem_trace_unlock();
 #endif // #ifdef MBED_MEM_TRACING_ENABLED
 }
 

--- a/platform/mbed_critical.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/mbed_critical.c	Wed Jan 17 15:23:54 2018 +0000
@@ -39,10 +39,10 @@
 {
 #if defined(__CORTEX_A9)
     switch(__get_CPSR() & 0x1FU) {
-        case MODE_USR:
-        case MODE_SYS:
+        case CPSR_M_USR:
+        case CPSR_M_SYS:
             return false;
-        case MODE_SVC:
+        case CPSR_M_SVC:
         default:
             return true;
     }
@@ -110,39 +110,42 @@
 
 bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
 {
-    uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr);
-    if (currentValue != *expectedCurrentValue) {
-        *expectedCurrentValue = currentValue;
-        __CLREX();
-        return false;
-    }
-
-    return !__STREXB(desiredValue, (volatile uint8_t*)ptr);
+    do {
+        uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr);
+        if (currentValue != *expectedCurrentValue) {
+            *expectedCurrentValue = currentValue;
+            __CLREX();
+            return false;
+        }
+    } while (__STREXB(desiredValue, (volatile uint8_t*)ptr));
+    return true;
 }
 
 bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
 {
-    uint16_t currentValue = __LDREXH((volatile uint16_t*)ptr);
-    if (currentValue != *expectedCurrentValue) {
-        *expectedCurrentValue = currentValue;
-        __CLREX();
-        return false;
-    }
-
-    return !__STREXH(desiredValue, (volatile uint16_t*)ptr);
+    do {
+        uint16_t currentValue = __LDREXH((volatile uint16_t*)ptr);
+        if (currentValue != *expectedCurrentValue) {
+            *expectedCurrentValue = currentValue;
+            __CLREX();
+            return false;
+        }
+    } while (__STREXH(desiredValue, (volatile uint16_t*)ptr));
+    return true;
 }
 
 
 bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
 {
-    uint32_t currentValue = __LDREXW((volatile uint32_t*)ptr);
-    if (currentValue != *expectedCurrentValue) {
-        *expectedCurrentValue = currentValue;
-        __CLREX();
-        return false;
-    }
-
-    return !__STREXW(desiredValue, (volatile uint32_t*)ptr);
+    do {
+        uint32_t currentValue = __LDREXW((volatile uint32_t*)ptr);
+        if (currentValue != *expectedCurrentValue) {
+            *expectedCurrentValue = currentValue;
+            __CLREX();
+            return false;
+        }
+    } while (__STREXW(desiredValue, (volatile uint32_t*)ptr));
+    return true;
 }
 
 uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)

--- a/platform/mbed_critical.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/mbed_critical.h	Wed Jan 17 15:23:54 2018 +0000
@@ -121,7 +121,7 @@
  * }
  *
  * @note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
+ * pointed to by expectedCurrentValue is instead updated with the current value.
  * This property helps writing concise code for the following incr:
  *
  * function incr(p : pointer to int, a : int) returns int {
@@ -132,6 +132,10 @@
  *     }
  *     return value + a
  * }
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
  */
 bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
 
@@ -174,7 +178,7 @@
  * }
  *
  * @note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
+ * pointed to by expectedCurrentValue is instead updated with the current value.
  * This property helps writing concise code for the following incr:
  *
  * function incr(p : pointer to int, a : int) returns int {
@@ -185,6 +189,10 @@
  *     }
  *     return value + a
  * }
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
  */
 bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
 
@@ -227,7 +235,7 @@
  * }
  *
  * @note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
+ * pointed to by expectedCurrentValue is instead updated with the current value.
  * This property helps writing concise code for the following incr:
  *
  * function incr(p : pointer to int, a : int) returns int {
@@ -237,6 +245,10 @@
  *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
  *     }
  *     return value + a
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
  * }
  */
 bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
@@ -280,7 +292,7 @@
  * }
  *
  * @note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
+ * pointed to by expectedCurrentValue is instead updated with the current value.
  * This property helps writing concise code for the following incr:
  *
  * function incr(p : pointer to int, a : int) returns int {
@@ -291,6 +303,10 @@
  *     }
  *     return value + a
  * }
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
  */
 bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue);
 

--- a/platform/mbed_lib.json	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/mbed_lib.json	Wed Jan 17 15:23:54 2018 +0000
@@ -19,6 +19,11 @@
         "default-serial-baud-rate": {
             "help": "Default baud rate for a Serial or RawSerial instance (if not specified in the constructor)",
             "value": 9600
+        },
+
+        "force-non-copyable-error": {
+            "help": "Force compile time error when a NonCopyable object is copied",
+            "value": false
         }
     },
     "target_overrides": {

--- a/platform/mbed_mem_trace.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,115 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2016 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <stdlib.h>
-#include <stdarg.h>
-#include <stdio.h>
-#include "platform/mbed_mem_trace.h"
-#include "platform/mbed_critical.h"
-
-/******************************************************************************
- * Internal variables, functions and helpers
- *****************************************************************************/
-
-/* The callback function that will be called after a traced memory operations finishes. */
-static mbed_mem_trace_cb_t mem_trace_cb;
-/* 'trave_level' guards "trace inside trace" situations (for example, the implementation
- * of realloc() might call malloc() internally, and since malloc() is also traced, this could
- * result in two calls to the callback function instead of one. */
-static uint8_t trace_level;
-
-/******************************************************************************
- * Public interface
- *****************************************************************************/
-
-void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb) {
-    mem_trace_cb = cb;
-}
-
-void *mbed_mem_trace_malloc(void *res, size_t size, void *caller) {
-    if (mem_trace_cb) {
-        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
-            mem_trace_cb(MBED_MEM_TRACE_MALLOC, res, caller, size);
-        }
-        core_util_atomic_decr_u8(&trace_level, 1);
-    }
-    return res;
-}
-
-void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller) {
-    if (mem_trace_cb) {
-        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
-            mem_trace_cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size);
-        }
-        core_util_atomic_decr_u8(&trace_level, 1);
-    }
-    return res;
-}
-
-void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller) {
-    if (mem_trace_cb) {
-        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
-            mem_trace_cb(MBED_MEM_TRACE_CALLOC, res, caller, num, size);
-        }
-        core_util_atomic_decr_u8(&trace_level, 1);
-    }
-    return res;
-}
-
-void mbed_mem_trace_free(void *ptr, void *caller) {
-    if (mem_trace_cb) {
-        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
-            mem_trace_cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr);
-        }
-        core_util_atomic_decr_u8(&trace_level, 1);
-    }
-}
-
-void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...) {
-    va_list va;
-    size_t temp_s1, temp_s2;
-    void *temp_ptr;
-
-    va_start(va, caller);
-    switch(op) {
-        case MBED_MEM_TRACE_MALLOC:
-            temp_s1 = va_arg(va, size_t);
-            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "m:%p;%p-%u\n", res, caller, temp_s1);
-            break;
-
-        case MBED_MEM_TRACE_REALLOC:
-            temp_ptr = va_arg(va, void*);
-            temp_s1 = va_arg(va, size_t);
-            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "r:%p;%p-%p;%u\n", res, caller, temp_ptr, temp_s1);
-            break;
-
-        case MBED_MEM_TRACE_CALLOC:
-            temp_s1 = va_arg(va, size_t);
-            temp_s2 = va_arg(va, size_t);
-            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "c:%p;%p-%u;%u\n", res, caller, temp_s1, temp_s2);
-            break;
-
-        case MBED_MEM_TRACE_FREE:
-            temp_ptr = va_arg(va, void*);
-            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "f:%p;%p-%p\n", res, caller, temp_ptr);
-            break;
-
-        default:
-            printf("?\n");
-    }
-    va_end(va);
-}
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_mem_trace.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,129 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include "platform/mbed_mem_trace.h"
+#include "platform/mbed_critical.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+
+/******************************************************************************
+ * Internal variables, functions and helpers
+ *****************************************************************************/
+
+/* The callback function that will be called after a traced memory operations finishes. */
+static mbed_mem_trace_cb_t mem_trace_cb;
+/* 'trace_lock_count' guards "trace inside trace" situations (for example, the implementation
+ * of realloc() might call malloc() internally, and since malloc() is also traced, this could
+ * result in two calls to the callback function instead of one. */
+static uint8_t trace_lock_count;
+static SingletonPtr<PlatformMutex> mem_trace_mutex;
+
+#define TRACE_FIRST_LOCK() (trace_lock_count < 2)
+
+
+/******************************************************************************
+ * Public interface
+ *****************************************************************************/
+
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb) {
+    mem_trace_cb = cb;
+}
+
+void mbed_mem_trace_lock()
+{
+    mem_trace_mutex->lock();
+    trace_lock_count++;
+}
+
+void mbed_mem_trace_unlock()
+{
+    trace_lock_count--;
+    mem_trace_mutex->unlock();
+}
+
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (TRACE_FIRST_LOCK()) {
+            mem_trace_cb(MBED_MEM_TRACE_MALLOC, res, caller, size);
+        }
+    }
+    return res;
+}
+
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (TRACE_FIRST_LOCK()) {
+            mem_trace_cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size);
+        }
+    }
+    return res;
+}
+
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (TRACE_FIRST_LOCK()) {
+            mem_trace_cb(MBED_MEM_TRACE_CALLOC, res, caller, num, size);
+        }
+    }
+    return res;
+}
+
+void mbed_mem_trace_free(void *ptr, void *caller) {
+    if (mem_trace_cb) {
+        if (TRACE_FIRST_LOCK()) {
+            mem_trace_cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr);
+        }
+    }
+}
+
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...) {
+    va_list va;
+    size_t temp_s1, temp_s2;
+    void *temp_ptr;
+
+    va_start(va, caller);
+    switch(op) {
+        case MBED_MEM_TRACE_MALLOC:
+            temp_s1 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "m:%p;%p-%u\n", res, caller, temp_s1);
+            break;
+
+        case MBED_MEM_TRACE_REALLOC:
+            temp_ptr = va_arg(va, void*);
+            temp_s1 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "r:%p;%p-%p;%u\n", res, caller, temp_ptr, temp_s1);
+            break;
+
+        case MBED_MEM_TRACE_CALLOC:
+            temp_s1 = va_arg(va, size_t);
+            temp_s2 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "c:%p;%p-%u;%u\n", res, caller, temp_s1, temp_s2);
+            break;
+
+        case MBED_MEM_TRACE_FREE:
+            temp_ptr = va_arg(va, void*);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "f:%p;%p-%p\n", res, caller, temp_ptr);
+            break;
+
+        default:
+            printf("?\n");
+    }
+    va_end(va);
+}
+

--- a/platform/mbed_mem_trace.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/mbed_mem_trace.h	Wed Jan 17 15:23:54 2018 +0000
@@ -73,6 +73,17 @@
 void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb);
 
 /**
+ * Trace lock.
+ * @note Locking prevent recursive tracing of malloc/free inside relloc/calloc
+ */
+void mbed_mem_trace_lock();
+
+/**
+ * Trace unlock.
+ */
+void mbed_mem_trace_unlock();
+
+/**
  * Trace a call to 'malloc'.
  * @param res the result of running 'malloc'.
  * @param size the 'size' argument given to 'malloc'.

--- a/platform/mbed_retarget.cpp	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/mbed_retarget.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -27,6 +27,8 @@
 #include "platform/mbed_stats.h"
 #include "platform/mbed_critical.h"
 #include "platform/PlatformMutex.h"
+#include "us_ticker_api.h"
+#include "lp_ticker_api.h"
 #include <stdlib.h>
 #include <string.h>
 #include <limits.h>
@@ -61,7 +63,6 @@
 #   define STDERR_FILENO    2
 
 #else
-#   include <sys/stat.h>
 #   include <sys/syslimits.h>
 #   define PREFIX(x)    x
 #endif
@@ -350,7 +351,9 @@
 }
 
 extern "C" void _ttywrch(int ch) {
+#if DEVICE_SERIAL
     serial_putc(&stdio_uart, ch);
+#endif
 }
 #endif
 
@@ -738,6 +741,7 @@
 
 // Dynamic memory allocation related syscall.
 #if defined(TARGET_NUVOTON)
+
 // Overwrite _sbrk() to support two region model (heap and stack are two distinct regions).
 // __wrap__sbrk() is implemented in:
 // TARGET_NUMAKER_PFM_NUC472    targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/TOOLCHAIN_GCC_ARM/nuc472_retarget.c
@@ -976,6 +980,10 @@
     __rtos_env_unlock(_r);
 }
 
+#endif
+
+#if defined (__GNUC__) || defined(__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+
 #define CXA_GUARD_INIT_DONE             (1 << 0)
 #define CXA_GUARD_INIT_IN_PROGRESS      (1 << 1)
 #define CXA_GUARD_MASK                  (CXA_GUARD_INIT_DONE | CXA_GUARD_INIT_IN_PROGRESS)
@@ -1044,15 +1052,11 @@
 
 void operator delete(void *ptr)
 {
-    if (ptr != NULL) {
-        free(ptr);
-    }
+    free(ptr);
 }
 void operator delete[](void *ptr)
 {
-    if (ptr != NULL) {
-        free(ptr);
-    }
+    free(ptr);
 }
 
 /* @brief   standard c library clock() function.
@@ -1073,3 +1077,23 @@
     _mutex->unlock();
     return t;
 }
+
+// temporary - Default to 1MHz at 32 bits if target does not have us_ticker_get_info
+MBED_WEAK const ticker_info_t* us_ticker_get_info()
+{
+    static const ticker_info_t info = {
+        1000000,
+        32
+    };
+    return &info;
+}
+
+// temporary - Default to 1MHz at 32 bits if target does not have lp_ticker_get_info
+MBED_WEAK const ticker_info_t* lp_ticker_get_info()
+{
+    static const ticker_info_t info = {
+        1000000,
+        32
+    };
+    return &info;
+}

--- a/platform/mbed_retarget.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/mbed_retarget.h	Wed Jan 17 15:23:54 2018 +0000
@@ -28,15 +28,16 @@
 /* We can get the following standard types from sys/types for gcc, but we
  * need to define the types ourselves for the other compilers that normally
  * target embedded systems */
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
 typedef signed   int  ssize_t;  ///< Signed size type, usually encodes negative errors
 typedef signed   long off_t;    ///< Offset in a data stream
+#if defined(__ARMCC_VERSION) || !defined(__GNUC__)
 typedef unsigned int  mode_t;   ///< Mode for opening files
 typedef unsigned int  dev_t;    ///< Device ID type
 typedef unsigned long ino_t;    ///< File serial number
 typedef unsigned int  nlink_t;  ///< Number of links to a file
 typedef unsigned int  uid_t;    ///< User ID
 typedef unsigned int  gid_t;    ///< Group ID
+#endif
 
 #define O_RDONLY 0      ///< Open for reading
 #define O_WRONLY 1      ///< Open for writing
@@ -45,19 +46,12 @@
 #define O_TRUNC  0x0400 ///< Truncate file to zero length
 #define O_EXCL   0x0800 ///< Fail if file exists
 #define O_APPEND 0x0008 ///< Set file offset to end of file prior to each write
+#define O_BINARY 0x8000 ///< Open file in binary mode
 
 #define NAME_MAX 255    ///< Maximum size of a name in a file path
 
 #include <time.h>
 
-#else
-
-#include <sys/fcntl.h>
-#include <sys/types.h>
-#include <sys/syslimits.h>
-
-#endif
-
 /** \addtogroup platform */
 /** @{*/
 /**
@@ -94,7 +88,6 @@
 #endif
 
 
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
 /* The intent of this section is to unify the errno error values to match
  * the POSIX definitions for the GCC_ARM, ARMCC and IAR compilers. This is
  * necessary because the ARMCC/IAR errno.h, or sys/stat.h are missing some
@@ -365,9 +358,7 @@
 #define EOWNERDEAD      130     /* Owner died */
 #undef  ENOTRECOVERABLE
 #define ENOTRECOVERABLE 131     /* State not recoverable */
-#endif
 
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
 /* Missing stat.h defines.
  * The following are sys/stat.h definitions not currently present in the ARMCC
  * errno.h. Note, ARMCC errno.h defines some symbol values differing from
@@ -424,7 +415,13 @@
     time_t    st_ctime;   ///< Time of last status change
 };
 
-#endif /* defined(__ARMCC_VERSION) || defined(__ICCARM__) */
+#if __cplusplus
+extern "C" {
+#endif
+    int stat(const char *path, struct stat *st);
+#if __cplusplus
+};
+#endif
 
 
 /* The following are dirent.h definitions are declared here to garuntee

--- a/platform/mbed_toolchain.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/platform/mbed_toolchain.h	Wed Jan 17 15:23:54 2018 +0000
@@ -5,7 +5,7 @@
  * \defgroup platform_toolchain Toolchain functions
  * @{
  */
- 
+
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -63,7 +63,7 @@
  *
  *  @note
  *  IAR does not support alignment greater than word size on the stack
- *  
+ *
  *  @code
  *  #include "mbed_toolchain.h"
  *
@@ -125,16 +125,16 @@
  *  should contain a regular function declaration to insure the function is emitted.
  *  A function marked weak will not be emitted if an alternative non-weak
  *  implementation is defined.
- *  
+ *
  *  @note
  *  Weak functions are not friendly to making code re-usable, as they can only
  *  be overridden once (and if they are multiply overridden the linker will emit
  *  no warning). You should not normally use weak symbols as part of the API to
  *  re-usable modules.
- *  
+ *
  *  @code
  *  #include "mbed_toolchain.h"
- *  
+ *
  *  MBED_WEAK void foo() {
  *      // a weak implementation of foo that can be overriden by a definition
  *      // without  __weak
@@ -173,9 +173,9 @@
  *
  *  @code
  *  #include "mbed_toolchain.h"
- *  
+ *
  *  MBED_NOINLINE void foo() {
- *  
+ *
  *  }
  *  @endcode
  */
@@ -195,9 +195,9 @@
  *
  *  @code
  *  #include "mbed_toolchain.h"
- *  
+ *
  *  MBED_FORCEINLINE void foo() {
- *  
+ *
  *  }
  *  @endcode
  */
@@ -216,7 +216,7 @@
  *
  *  @code
  *  #include "mbed_toolchain.h"
- *  
+ *
  *  MBED_NORETURN void foo() {
  *      // must never return
  *      while (1) {}
@@ -266,7 +266,7 @@
  *
  *  @code
  *  #include "mbed_toolchain.h"
- *  
+ *
  *  MBED_DEPRECATED("don't foo any more, bar instead")
  *  void foo(int arg);
  *  @endcode
@@ -330,6 +330,20 @@
 #endif
 #endif
 
+/**
+ * Macro expanding to a string literal of the enclosing function name.
+ *
+ * The string returned takes into account language specificity and yield human
+ * readable content.
+ *
+ * As an example, if the macro is used within a C++ function then the string
+ * literal containing the function name will contain the complete signature of
+ * the function - including template parameters - and namespace qualifications.
+ */
+#ifndef MBED_PRETTY_FUNCTION
+#define MBED_PRETTY_FUNCTION __PRETTY_FUNCTION__
+#endif
+
 #ifndef MBED_PRINTF
 #if defined(__GNUC__) || defined(__CC_ARM)
 #define MBED_PRINTF(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx, first_param_idx)))

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c	Wed Jan 17 15:23:54 2018 +0000
@@ -45,7 +45,7 @@
  *
  *****************************************************************************/
 #include <stdint.h>
-#ifdef __CC_ARM
+#ifdef __ARMCC_VERSION
 #include <rt_misc.h>
 #endif
 #include <cmsis.h>
@@ -61,8 +61,8 @@
 /*----------------------------------------------------------------------------
   Checksum options
  *----------------------------------------------------------------------------*/
- #if defined (__CC_ARM)
-__attribute__ ((at(0x000001A0u)))
+#if defined (__ARMCC_VERSION)
+__attribute__((section(".ARM.__at_0x000001A0")))
 #elif defined( __ICCARM__)
 __root
 #endif /* __ICCARM__ */
@@ -151,7 +151,7 @@
 /*----------------------------------------------------------------------------
 * Initialize .bss and .data for GNU
 *----------------------------------------------------------------------------*/
-#if defined( __GNUC__) && !defined (__CC_ARM)
+#if defined( __GNUC__) && !defined (__ARMCC_VERSION)
 void zero_bss(void)
 {
     uint32_t *pSrc, *pDest;
@@ -248,7 +248,7 @@
        may reside in DSRAM bank B. */
     SramInit();
 
-#if defined(__GNUC__) && !defined (__CC_ARM)
+#if defined(__GNUC__) && !defined (__ARMCC_VERSION)
     /* Clear the bss section for GCC build only */
     zero_bss();
 #endif
@@ -263,7 +263,7 @@
 /*----------------------------------------------------------------------------
   Default Handler for Exceptions / Interrupts
  *----------------------------------------------------------------------------*/
-#if defined(__CC_ARM) || defined (__GNUC__)
+#if defined(__ARMCC_VERSION) || defined (__GNUC__)
 void Default_Handler(void)
 {
     while(1);

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h	Wed Jan 17 15:23:54 2018 +0000
@@ -63,16 +63,14 @@
 
 #define VECTOR_SECTION                 ".vectors"
 
-#ifdef __CC_ARM
-extern unsigned Image$$ADUCM_HEAP$$Base[];
-extern unsigned Image$$ADUCM_HEAP$$ZI$$Limit[];
+#ifdef __ARMCC_VERSION
 void Default_Handler(void);
-#define SECTION_NAME(sectionname)      __attribute__ ((section(sectionname)))
-#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname)))
+#define SECTION_NAME(sectionname)      __attribute__((section(sectionname)))
+#define SECTION_PLACE(def,sectionname) def __attribute__((section(sectionname)))
 #define IVT_NAME                       __Vectors
 #define RESET_EXCPT_HNDLR              __main
 #define COMPILER_NAME                  "ARMCC"
-#define WEAK_FUNCTION(x)               void x (void) __attribute__ ((weak, alias("Default_Handler")));
+#define WEAK_FUNCTION(x)               void x (void) __attribute__((weak, alias("Default_Handler")));
 
 #elif defined(__ICCARM__)
 #pragma diag_suppress=Pm093,Pm140

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -47,7 +47,6 @@
 #include "pinmap.h"
 #include "PeripheralPins.h"
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -80,7 +79,10 @@
     ADCName peripheral;
     uint32_t function, channel;
 
-    peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]);	// gives peripheral
+    memset(obj, 0, sizeof(analogin_t) );
+    memset( DeviceMemory, 0, sizeof( DeviceMemory ) );
+
+    peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]);   // gives peripheral
     MBED_ASSERT(peripheral != (ADCName)NC);
 
     /* verify read function */
@@ -142,6 +144,7 @@
 
     /* Set the acquisition time. (Application need to change it based on the impedence) */
     adi_adc_SetAcquisitionTime(hDevice, obj->SampleCycles);
+
 }
 
 /** Read the input voltage, represented as a float in the range [0.0, 1.0]
@@ -165,6 +168,11 @@
 {
     ADI_ADC_HANDLE  hDevice = obj->hDevice;
     ADI_ADC_BUFFER  *pAdcBuffer;
+    uint32_t        ADCsample;
+
+    obj->UserBuffer.pDataBuffer = &ADCsample;
+    obj->UserBuffer.nNumConversionPasses = 1;
+    obj->UserBuffer.nBuffSize = 1;
 
     /* Submit the buffer to the driver */
     adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer);
@@ -178,8 +186,9 @@
     return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) );
 }
 
-/* Retrieve te active channel correspondoing to the input pin */
-static uint32_t adi_pin2channel(PinName pin) {
+/* Retrieve the active channel corresponding to the input pin */
+static uint32_t adi_pin2channel(PinName pin)
+{
 
     uint32_t activech;
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -46,9 +46,12 @@
 
 #define MUX_FUNC_0 0x0
 #define NUM_GPIO_PORTS 4
-
-extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
-extern uint8_t gpio_initialized;
+/*******************************************************************************
+   ADI_GPIO_DEV_DATA Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
+extern uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4];
+extern uint8_t  gpio_initialized;
 
 static uint16_t gpio_oen[NUM_GPIO_PORTS] = {0};
 static uint16_t gpio_output_val[NUM_GPIO_PORTS] = {0};

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c	Wed Jan 17 15:23:54 2018 +0000
@@ -39,9 +39,12 @@
  ******************************************************************************/
 
 #include <drivers/gpio/adi_gpio.h>
-
+/*******************************************************************************
+   ADI_GPIO_DEV_DATA Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
 // ADI GPIO device driver state memory. Only one state memory is required globally.
-uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
+uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4];
 
 // Flag to indicate whether the GPIO driver has been initialized
-uint8_t gpio_initialized = 0;
+uint8_t  gpio_initialized = 0;

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -53,9 +53,12 @@
     gpio_irq_event event;
     uint8_t int_enable;
 } gpio_chan_info_t;
-
-extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
-extern uint8_t gpio_initialized;
+/*******************************************************************************
+   ADI_GPIO_DEV_DATA Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
+extern uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4];
+extern uint8_t  gpio_initialized;
 static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES];
 static gpio_irq_handler irq_handler = NULL;
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -57,7 +57,11 @@
 int adi_i2c_memtype = 0;
 #endif
 #else
-static uint8_t          i2c_Mem[ADI_I2C_MEMORY_SIZE];
+/*******************************************************************************
+   ADI_I2C_DEV_DATA_TYPE Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
+static uint32_t         i2c_Mem[(ADI_I2C_MEMORY_SIZE + 3)/4];
 static ADI_I2C_HANDLE   i2c_Handle;
 #if defined(ADI_DEBUG)
 #warning "BUILD_I2C_MI_DYNAMIC is NOT defined.  Memory allocation for I2C will be static"
@@ -72,7 +76,7 @@
     uint32_t        i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
     uint32_t        i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
     ADI_I2C_HANDLE  *pI2C_Handle;
-    uint8_t         *I2C_Mem;
+    uint32_t        *I2C_Mem;
     ADI_I2C_RESULT  I2C_Return = ADI_I2C_SUCCESS;
     uint32_t        I2C_DevNum = I2C_0;     /* ADuCM3029 only has 1 I2C port */
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h	Wed Jan 17 15:23:54 2018 +0000
@@ -79,7 +79,11 @@
     ADI_I2C_HANDLE  *pI2C_Handle;
 #if defined(BUILD_I2C_MI_DYNAMIC)
     ADI_I2C_HANDLE  I2C_Handle;
-    uint8_t         I2C_Mem[ADI_I2C_MEMORY_SIZE];
+/*******************************************************************************
+   ADI_I2C_DEV_DATA_TYPE Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
+    uint32_t        I2C_Mem[(ADI_I2C_MEMORY_SIZE + 3)/4];
 #endif
 };
 
@@ -90,7 +94,11 @@
     ADI_SPI_HANDLE  *pSPI_Handle;
 #if defined(BUILD_SPI_MI_DYNAMIC)
     ADI_SPI_HANDLE  SPI_Handle;
-    uint8_t         SPI_Mem[ADI_SPI_MEMORY_SIZE];
+/*******************************************************************************
+   ADI_SPI_DEV_DATA_TYPE Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
+    uint32_t        SPI_Mem[(ADI_SPI_MEMORY_SIZE + 3)/4];
 #endif
 };
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -46,7 +46,11 @@
 #include "adi_pwr.h"
 
 #define RTC_DEVICE_NUM    0
-static uint8_t aRtcDevMem0[ADI_RTC_MEMORY_SIZE];
+/*******************************************************************************
+   ADI_RTC_DEVICE Instance memory containing memory pointer should guarantee
+   4 byte alignmnet.
+ *******************************************************************************/
+static uint32_t       aRtcDevMem0[(ADI_RTC_MEMORY_SIZE + 3)/4];
 static ADI_RTC_HANDLE hDevice0 = NULL;
 
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -59,12 +59,16 @@
 int adi_spi_memtype = 0;
 #endif
 #else
+/*******************************************************************************
+   ADI_SPI_DEV_DATA_TYPE Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
 ADI_SPI_HANDLE      spi_Handle0;
-uint8_t             spi_Mem0[ADI_SPI_MEMORY_SIZE];
+uint32_t            spi_Mem0[(ADI_SPI_MEMORY_SIZE + 3)/4];
 ADI_SPI_HANDLE      spi_Handle1;
-uint8_t             spi_Mem1[ADI_SPI_MEMORY_SIZE];
+uint32_t            spi_Mem1[(ADI_SPI_MEMORY_SIZE + 3)/4];
 ADI_SPI_HANDLE      spi_Handle2;
-uint8_t             spi_Mem2[ADI_SPI_MEMORY_SIZE];
+uint32_t            spi_Mem2[(ADI_SPI_MEMORY_SIZE + 3)/4];
 #if defined(ADI_DEBUG)
 #warning "BUILD_SPI_MI_DYNAMIC is NOT defined.  Memory allocation for SPI will be static"
 int adi_spi_memtype = 1;
@@ -92,7 +96,7 @@
     uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
     uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
     ADI_SPI_HANDLE      *pSPI_Handle;
-    uint8_t             *SPI_Mem;
+    uint32_t            *SPI_Mem;
     ADI_SPI_RESULT      SPI_Return = ADI_SPI_SUCCESS;
     uint32_t            nDeviceNum = 0;
     ADI_SPI_CHIP_SELECT spi_cs = ADI_SPI_CS_NONE;

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -54,8 +54,15 @@
 #define TRNG_CNT_VAL    4095
 #define TRNG_PRESCALER  2
 
-/* RNG Device memory */
-static uint8_t RngDevMem[ADI_RNG_MEMORY_SIZE];
+/*******************************************************************************
+   RNG Device memory is the instance of ADI_RNG_DEV_DATA_TYPE that contains
+   pointers and requires 4 byte alignment. The use of uint8_t may cause memory
+   access fault for some compilers which are not configured to handle unaligned
+   accesses to SRAM. The size in uint8_t for RngDevMem is ADI_RNG_MEMORY_SIZE.
+   The size in uint32_t for RngDevMem is recalculated to be
+   (ADI_RNG_MEMORY_SIZE + 3)/4.
+ *******************************************************************************/
+static uint32_t RngDevMem[(ADI_RNG_MEMORY_SIZE + 3)/4];
 
 void trng_init(trng_t *obj)
 {

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h	Wed Jan 17 15:23:54 2018 +0000
@@ -62,10 +62,6 @@
 #pragma diag_suppress=Pm008,Pm093
 #endif /* __ICCARM__ */
 
-#if defined (__CC_ARM)
-#pragma anon_unions
-#endif /* __CC_ARM */
-
 #define __ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__
 
 #include <sys/ADuCM302x_typedefs.h>

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c	Wed Jan 17 15:23:54 2018 +0000
@@ -123,7 +123,7 @@
 #define __ADI_BYTE_SWAP(X)                        __REV(X)
 #elif defined (__GNUC__)
 #define __ADI_BYTE_SWAP(X)                        __builtin_bswap32(X)
-#elif defined (__CC_ARM)
+#elif defined (__ARMCC_VERSION)
 #define __ADI_BYTE_SWAP(X)                        __rev(X)
 #else
 #error "This toolchain is not supported"

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c	Wed Jan 17 15:23:54 2018 +0000
@@ -272,7 +272,7 @@
 /* ARM Cortex-M3/M4, GNU-ARM compiler */
 #define ADI_CLZ(X)     __builtin_clz(X)
 
-#elif defined(__CC_ARM)
+#elif defined(__ARMCC_VERSION)
 
 /* ARM Cortex-M3/M4, Keil compiler */
 #define ADI_CLZ(X)    __clz(X)

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h	Wed Jan 17 15:23:54 2018 +0000
@@ -82,10 +82,10 @@
   #define ADI_ALIGNED_ATTRIBUTE(num)
   #define ADI_ALIGNED_PRAGMA(num) PRAGMA(data_alignment=num) 
   #define ADI_UNUSED_ATTRIBUTE
-#elif defined (__CC_ARM)
+#elif defined (__ARMCC_VERSION)
   /* Keil uses a decorator which is placed in the same position as pragmas */
   #define ADI_ALIGNED_ATTRIBUTE(num)
-  #define ADI_ALIGNED_PRAGMA(num) __align(##num)
+  #define ADI_ALIGNED_PRAGMA(num) __attribute__((aligned(num)))
   #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused)
 #else
 #error "Toolchain not supported"

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h	Wed Jan 17 15:23:54 2018 +0000
@@ -25,12 +25,6 @@
 /* pickup register bitfield and bit masks */
 #include "ADuCM302x_typedefs.h"
 
-#if defined ( __CC_ARM   )
-#pragma push
-#pragma anon_unions
-#endif
-
-
 #ifndef __IO
 #ifdef __cplusplus
 #define     __I     volatile      /* read-only */
@@ -1209,9 +1203,4 @@
 #pragma diag(pop)
 #endif /* _MISRA_RULES */
 
-
-#if defined (__CC_ARM)
-#pragma pop
-#endif 
-
 #endif

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h	Wed Jan 17 15:23:54 2018 +0000
@@ -22,12 +22,6 @@
 #include <stdint.h>
 #endif /* _LANGUAGE_C */
 
-#if defined ( __CC_ARM   )
-#pragma push
-#pragma anon_unions
-#endif
-
-
 #if defined (_MISRA_RULES)
 /*
   anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1.
@@ -9556,9 +9550,4 @@
 #pragma diag(pop)
 #endif /* _MISRA_RULES */
 
-
-#if defined (__CC_ARM)
-#pragma pop
-#endif 
-
 #endif

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c	Wed Jan 17 15:23:54 2018 +0000
@@ -44,7 +44,7 @@
 EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  *****************************************************************************/
-#ifdef __CC_ARM
+#ifdef __ARMCC_VERSION
 #include <stdint.h>
 #include <rt_misc.h>
 #endif
@@ -55,8 +55,8 @@
 /*----------------------------------------------------------------------------
   Checksum options
  *----------------------------------------------------------------------------*/
-#if defined (__CC_ARM)
-__attribute__ ((at(0x000001A0u)))
+#if defined (__ARMCC_VERSION)
+__attribute__((section(".ARM.__at_0x000001A0")))
 #elif defined(__ICCARM__)
 __root
 #endif
@@ -155,7 +155,7 @@
 /*----------------------------------------------------------------------------
 * Initialize .bss and .data for GNU
 *----------------------------------------------------------------------------*/
-#if defined( __GNUC__) && !defined (__CC_ARM)
+#if defined( __GNUC__) && !defined (__ARMCC_VERSION)
 void zero_bss(void)
 {
     uint32_t *pSrc, *pDest;
@@ -251,7 +251,7 @@
     /* Initialize SRAM configuration. */
     SramInit();
 
-#if defined(__GNUC__) && !defined (__CC_ARM)
+#if defined(__GNUC__) && !defined (__ARMCC_VERSION)
     zero_bss();
 #endif
 
@@ -265,7 +265,7 @@
 /*----------------------------------------------------------------------------
   Default Handler for Exceptions / Interrupts
  *----------------------------------------------------------------------------*/
-#if defined(__CC_ARM) || defined (__GNUC__)
+#if defined(__ARMCC_VERSION) || defined (__GNUC__)
 void Default_Handler(void)
 {
     while(1);

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h	Wed Jan 17 15:23:54 2018 +0000
@@ -63,16 +63,14 @@
 
 #include <adi_types.h>
 #define VECTOR_SECTION                 ".vectors"
-#ifdef __CC_ARM
-extern unsigned Image$$ADUCM_HEAP$$Base[];
-extern unsigned Image$$ADUCM_HEAP$$ZI$$Limit[];
+#ifdef __ARMCC_VERSION
 void Default_Handler(void);
-#define SECTION_NAME(sectionname)      __attribute__ ((section(sectionname)))
-#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname)))
+#define SECTION_NAME(sectionname)      __attribute__((section(sectionname)))
+#define SECTION_PLACE(def,sectionname) def __attribute__((section(sectionname)))
 #define IVT_NAME                       __Vectors
 #define RESET_EXCPT_HNDLR              __main
 #define COMPILER_NAME                  "ARMCC"
-#define WEAK_FUNCTION(x)               void x (void) __attribute__ ((weak, alias("Default_Handler")));
+#define WEAK_FUNCTION(x)               void x (void) __attribute__((weak, alias("Default_Handler")));
 #elif defined(__ICCARM__)
 /*
 * IAR MISRA C 2004 error suppressions:

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -79,7 +79,10 @@
     ADCName peripheral;
     uint32_t function, channel;
 
-    peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]);	// gives peripheral
+    memset(obj, 0, sizeof(analogin_t) );
+    memset( DeviceMemory, 0, sizeof( DeviceMemory ) );
+
+    peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]);   // gives peripheral
     MBED_ASSERT(peripheral != (ADCName)NC);
 
     /* verify read function */
@@ -165,6 +168,11 @@
 {
     ADI_ADC_HANDLE  hDevice = obj->hDevice;
     ADI_ADC_BUFFER  *pAdcBuffer;
+    uint32_t        ADCsample;
+
+    obj->UserBuffer.pDataBuffer = &ADCsample;
+    obj->UserBuffer.nNumConversionPasses = 1;
+    obj->UserBuffer.nBuffSize = 1;
 
     /* Submit the buffer to the driver */
     adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer);
@@ -178,7 +186,7 @@
     return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) );
 }
 
-/* Retrieve te active channel correspondoing to the input pin */
+/* Retrieve the active channel corresponding to the input pin */
 static uint32_t adi_pin2channel(PinName pin)
 {
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -46,9 +46,12 @@
 
 #define MUX_FUNC_0 0x0
 #define NUM_GPIO_PORTS 4
-
-extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
-extern uint8_t gpio_initialized;
+/*******************************************************************************
+   ADI_GPIO_DEV_DATA Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
+extern uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4];
+extern uint8_t  gpio_initialized;
 
 static uint16_t gpio_oen[NUM_GPIO_PORTS] = {0};
 static uint16_t gpio_output_val[NUM_GPIO_PORTS] = {0};

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c	Wed Jan 17 15:23:54 2018 +0000
@@ -39,9 +39,12 @@
  ******************************************************************************/
 
 #include <drivers/gpio/adi_gpio.h>
-
+/*******************************************************************************
+   ADI_GPIO_DEV_DATA Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
 // ADI GPIO device driver state memory. Only one state memory is required globally.
-uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
+uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE +3)/4];
 
 // Flag to indicate whether the GPIO driver has been initialized
-uint8_t gpio_initialized = 0;
+uint8_t  gpio_initialized = 0;

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -52,9 +52,12 @@
     gpio_irq_event event;
     uint8_t int_enable;
 } gpio_chan_info_t;
-
-extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
-extern uint8_t gpio_initialized;
+/*******************************************************************************
+   ADI_GPIO_DEV_DATA Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
+extern uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4];
+extern uint8_t  gpio_initialized;
 static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES];
 static gpio_irq_handler irq_handler = NULL;
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -57,7 +57,11 @@
 int adi_i2c_memtype = 0;
 #endif
 #else
-static uint8_t          i2c_Mem[ADI_I2C_MEMORY_SIZE];
+/*******************************************************************************
+   ADI_I2C_DEV_DATA_TYPE Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
+static uint32_t         i2c_Mem[(ADI_I2C_MEMORY_SIZE + 3)/4];
 static ADI_I2C_HANDLE   i2c_Handle;
 #if defined(ADI_DEBUG)
 #warning "BUILD_I2C_MI_DYNAMIC is NOT defined.  Memory allocation for I2C will be static"
@@ -72,7 +76,7 @@
     uint32_t        i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
     uint32_t        i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
     ADI_I2C_HANDLE  *pI2C_Handle;
-    uint8_t         *I2C_Mem;
+    uint32_t        *I2C_Mem;
     ADI_I2C_RESULT  I2C_Return = ADI_I2C_SUCCESS;
     uint32_t        I2C_DevNum = I2C_0;     /* ADuCM4050 only has 1 I2C port */
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h	Wed Jan 17 15:23:54 2018 +0000
@@ -79,7 +79,11 @@
     ADI_I2C_HANDLE  *pI2C_Handle;
 #if defined(BUILD_I2C_MI_DYNAMIC)
     ADI_I2C_HANDLE  I2C_Handle;
-    uint8_t         I2C_Mem[ADI_I2C_MEMORY_SIZE];
+/*******************************************************************************
+   ADI_I2C_DEV_DATA_TYPE Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
+    uint32_t        I2C_Mem[(ADI_I2C_MEMORY_SIZE + 3)/4];
 #endif
 };
 
@@ -90,7 +94,11 @@
     ADI_SPI_HANDLE  *pSPI_Handle;
 #if defined(BUILD_SPI_MI_DYNAMIC)
     ADI_SPI_HANDLE  SPI_Handle;
-    uint8_t         SPI_Mem[ADI_SPI_MEMORY_SIZE];
+/*******************************************************************************
+   ADI_SPI_DEV_DATA_TYPE Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
+    uint32_t        SPI_Mem[(ADI_SPI_MEMORY_SIZE + 3)/4];
 #endif
 };
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -46,7 +46,11 @@
 #include "adi_pwr.h"
 
 #define RTC_DEVICE_NUM    0
-static uint8_t aRtcDevMem0[ADI_RTC_MEMORY_SIZE];
+/*******************************************************************************
+   ADI_RTC_DEVICE Instance memory containing memory pointer should guarantee
+   4 byte alignmnet.
+ *******************************************************************************/
+static uint32_t       aRtcDevMem0[(ADI_RTC_MEMORY_SIZE + 3)/4];
 static ADI_RTC_HANDLE hDevice0 = NULL;
 
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -61,12 +61,16 @@
 int adi_spi_memtype = 0;
 #endif
 #else
+/*******************************************************************************
+   ADI_SPI_DEV_DATA_TYPE Instance memory containing memory pointer should
+   guarantee 4 byte alignmnet.
+ *******************************************************************************/
 ADI_SPI_HANDLE      spi_Handle0;
-uint8_t             spi_Mem0[ADI_SPI_MEMORY_SIZE];
+uint32_t            spi_Mem0[(ADI_SPI_MEMORY_SIZE + 3)/4];
 ADI_SPI_HANDLE      spi_Handle1;
-uint8_t             spi_Mem1[ADI_SPI_MEMORY_SIZE];
+uint32_t            spi_Mem1[(ADI_SPI_MEMORY_SIZE + 3)/4];
 ADI_SPI_HANDLE      spi_Handle2;
-uint8_t             spi_Mem2[ADI_SPI_MEMORY_SIZE];
+uint32_t            spi_Mem2[(ADI_SPI_MEMORY_SIZE + 3)/4];
 #if defined(ADI_DEBUG)
 #warning "BUILD_SPI_MI_DYNAMIC is NOT defined.  Memory allocation for SPI will be static"
 int adi_spi_memtype = 1;
@@ -94,7 +98,7 @@
     uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
     uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
     ADI_SPI_HANDLE      *pSPI_Handle;
-    uint8_t             *SPI_Mem;
+    uint32_t            *SPI_Mem;
     ADI_SPI_RESULT      SPI_Return = ADI_SPI_SUCCESS;
     uint32_t            nDeviceNum = 0;
     ADI_SPI_CHIP_SELECT spi_cs = ADI_SPI_CS_NONE;

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c	Wed Jan 17 15:23:54 2018 +0000
@@ -121,7 +121,7 @@
 #define __ADI_BYTE_SWAP(X)                        __REV(X)
 #elif defined (__GNUC__)
 #define __ADI_BYTE_SWAP(X)                        __builtin_bswap32(X)
-#elif defined (__CC_ARM)
+#elif defined (__ARMCC_VERSION)
 #define __ADI_BYTE_SWAP(X)                        __rev(X)
 #else
 #error "This toolchain is not supported"

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c	Wed Jan 17 15:23:54 2018 +0000
@@ -272,7 +272,7 @@
 /* ARM Cortex-M3/M4, GNU-ARM compiler */
 #define ADI_CLZ(X)     __builtin_clz(X)
 
-#elif defined(__CC_ARM)
+#elif defined(__ARMCC_VERSION)
 
 /* ARM Cortex-M3/M4, Keil compiler */
 #define ADI_CLZ(X)    __clz(X)

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h	Wed Jan 17 15:23:54 2018 +0000
@@ -82,10 +82,10 @@
   #define ADI_ALIGNED_ATTRIBUTE(num)
   #define ADI_ALIGNED_PRAGMA(num) PRAGMA(data_alignment=num) 
   #define ADI_UNUSED_ATTRIBUTE
-#elif defined (__CC_ARM)
+#elif defined (__ARMCC_VERSION)
   /* Keil uses a decorator which is placed in the same position as pragmas */
   #define ADI_ALIGNED_ATTRIBUTE(num)
-  #define ADI_ALIGNED_PRAGMA(num) __align(##num)
+  #define ADI_ALIGNED_PRAGMA(num) __attribute__((aligned(num)))
   #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused)
 #else
 #error "Toolchain not supported"

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h	Wed Jan 17 15:23:54 2018 +0000
@@ -25,12 +25,6 @@
 /* pickup register bitfield and bit masks */
 #include "adi_ADuCM4050_typedefs.h"
 
-#if defined ( __CC_ARM   )
-#pragma push
-#pragma anon_unions
-#endif
-
-
 #ifndef __IO
 #ifdef __cplusplus
 #define     __I     volatile      /* read-only */
@@ -1330,9 +1324,4 @@
 #pragma diag(pop)
 #endif /* _MISRA_RULES */
 
-
-#if defined (__CC_ARM)
-#pragma pop
-#endif 
-
 #endif

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h	Wed Jan 17 15:23:54 2018 +0000
@@ -22,12 +22,6 @@
 #include <stdint.h>
 #endif /* _LANGUAGE_C */
 
-#if defined ( __CC_ARM   )
-#pragma push
-#pragma anon_unions
-#endif
-
-
 #if defined (_MISRA_RULES)
 /*
   anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1.
@@ -11244,9 +11238,4 @@
 #pragma diag(pop)
 #endif /* _MISRA_RULES */
 
-
-#if defined (__CC_ARM)
-#pragma pop
-#endif 
-
 #endif

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/MK24FN1M0xxx12.sct	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/MK24FN1M0xxx12.sct	Wed Jan 17 15:23:54 2018 +0000
@@ -55,14 +55,22 @@
   #define __ram_vector_table_size__    0x00000000
 #endif
 
-#define m_interrupts_start             0x00000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x100000
+#endif
+
+#define m_interrupts_start             MBED_APP_START
 #define m_interrupts_size              0x00000400
 
-#define m_flash_config_start           0x00000400
+#define m_flash_config_start           MBED_APP_START + 0x400
 #define m_flash_config_size            0x00000010
 
-#define m_text_start                   0x00000410
-#define m_text_size                    0x000FFBF0
+#define m_text_start                   MBED_APP_START + 0x410
+#define m_text_size                    MBED_APP_SIZE - 0x410
 
 #define m_interrupts_ram_start         0x1FFF0000
 #define m_interrupts_ram_size          __ram_vector_table_size__

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld	Wed Jan 17 15:23:54 2018 +0000
@@ -56,16 +56,24 @@
 __stack_size__ = 0x8000;
 __heap_size__ = 0x10000;
 
-HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
-STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x100000
+#endif
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x8000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
 M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
 
 /* Specify the memory areas */
 MEMORY
 {
-  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
-  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
-  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0
+  m_interrupts          (RX)  : ORIGIN = MBED_APP_START, LENGTH = 0x400
+  m_flash_config        (RX)  : ORIGIN = MBED_APP_START + 0x400, LENGTH = 0x10
+  m_text                (RX)  : ORIGIN = MBED_APP_START + 0x410, LENGTH = MBED_APP_SIZE - 0x410
   m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
   m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000
 }

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/MK24FN1M0xxx12.icf	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/MK24FN1M0xxx12.icf	Wed Jan 17 15:23:54 2018 +0000
@@ -52,17 +52,25 @@
 define symbol __stack_size__=0x8000;
 define symbol __heap_size__=0x10000;
 
+if (!isdefinedsymbol(MBED_APP_START)) {
+    define symbol MBED_APP_START = 0;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+    define symbol MBED_APP_SIZE = 0x100000;
+}
+
 define symbol __ram_vector_table_size__ =  isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
 define symbol __ram_vector_table_offset__ =  isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
 
-define symbol m_interrupts_start       = 0x00000000;
-define symbol m_interrupts_end         = 0x000003FF;
+define symbol m_interrupts_start       = MBED_APP_START;
+define symbol m_interrupts_end         = MBED_APP_START + 0x3FF;
 
-define symbol m_flash_config_start     = 0x00000400;
-define symbol m_flash_config_end       = 0x0000040F;
+define symbol m_flash_config_start     = MBED_APP_START + 0x400;
+define symbol m_flash_config_end       = MBED_APP_START + 0x40F;
 
-define symbol m_text_start             = 0x00000410;
-define symbol m_text_end               = 0x000FFFFF;
+define symbol m_text_start             = MBED_APP_START + 0x410;
+define symbol m_text_end               = MBED_APP_START + MBED_APP_SIZE - 1;
 
 define symbol m_interrupts_ram_start   = 0x1FFF0000;
 define symbol m_interrupts_ram_end     = 0x1FFF0000 + __ram_vector_table_offset__;

--- a/targets/TARGET_Maxim/TARGET_MAX32625/mxc/mxc_lock.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/mxc/mxc_lock.h	Wed Jan 17 15:23:54 2018 +0000
@@ -69,7 +69,7 @@
     do {
 
         // Return if the lock is taken by a different thread
-        if(__LDREXW((volatile unsigned long *)lock) != 0) {
+        if(__LDREXW((volatile uint32_t *)lock) != 0) {
             return E_BUSY;
         }
 

--- a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h	Wed Jan 17 15:23:54 2018 +0000
@@ -80,12 +80,12 @@
     do {
 
         // Return if the lock is taken by a different thread
-        if(__LDREXW((volatile unsigned long *)lock) != 0) {
+        if(__LDREXW((volatile uint32_t *)lock) != 0) {
             return E_BUSY;
         }
 
         // Attempt to take the lock
-    } while(__STREXW(value, (volatile unsigned long *)lock) != 0);
+    } while(__STREXW(value, (volatile uint32_t *)lock) != 0);
 
     // Do not start any other memory access until memory barrier is complete
     __DMB();

--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -67,7 +67,7 @@
     
     // initialization by assigment because IAR dosen't support variable initializer in declaration statement.
     adc_channel.config.config.resolution = NRF_ADC_CONFIG_RES_10BIT;
-    adc_channel.config.config.input      = NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE;
+    adc_channel.config.config.input      = NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD;
     adc_channel.config.config.reference  = NRF_ADC_CONFIG_REF_VBG;
     adc_channel.config.config.ain        = (obj->adc_pin);
     adc_channel.p_next = NULL;

--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,13 +0,0 @@
-LR_IROM1 0x21000 0x00DF000  {
-  ER_IROM1 0x21000 0x00DF000  {
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM0 0x20003288 UNINIT 0x000000F8  { ;no init section
-        *(*noinit)
-  }
-  RW_IRAM1 0x20003380 0x0003cc80  {
-   .ANY (+RW +ZI)
-  }
-}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,23 @@
+#! armcc -E
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x21000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0xDF000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM0 0x20003288 UNINIT 0x000000F8  { ;no init section
+        *(*noinit)
+  }
+  RW_IRAM1 0x20003380 0x0003cc80  {
+   .ANY (+RW +ZI)
+  }
+}

--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld	Wed Jan 17 15:23:54 2018 +0000
@@ -16,9 +16,17 @@
 
 /* Linker script to configure memory regions. */
 
+#if !defined(MBED_APP_START)
+    #define MBED_APP_START 0x21000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0xDF000
+#endif
+
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x21000, LENGTH = 0xDF000
+  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
   RAM (rwx) :  ORIGIN = 0x20003288, LENGTH = 0x3cd78
 }
 
@@ -130,7 +138,7 @@
         PROVIDE(__start_fs_data = .);
         KEEP(*(.fs_data))
         PROVIDE(__stop_fs_data = .);
-        
+
         *(.jcr)
         . = ALIGN(4);
         /* All data end */
@@ -146,7 +154,7 @@
       KEEP(*(.noinit))
       PROVIDE(__stop_noinit = .);
     } > RAM
-    
+
     .bss :
     {
         . = ALIGN(4);

--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52832.icf	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,46 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x21000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x21000;
-define symbol __ICFEDIT_region_ROM_end__     = 0xfffff;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20003288;
-define symbol __ICFEDIT_region_RAM_end__     = 0x2003ffff;
-export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
-/*-Sizes-*/
-/*Heap 1/4 of ram and stack 1/8*/
-define symbol __ICFEDIT_size_cstack__   = 0x800;
-define symbol __ICFEDIT_size_heap__     = 0x3000;
-/**** End of ICF editor section. ###ICF###*/
-
-define symbol __code_start_soft_device__ = 0x0;
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-keep { section .intvec };
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block HEAP,
-                        block CSTACK };
-
-/*This is used for mbed applications build inside the Embedded workbench
-Applications build with the python scritps use a hex merge so need to merge it
-inside the linker. The linker can only use binary files so the hex merge is not possible
-through the linker. That is why a binary is used instead of a hex image for the embedded project.
-*/
-if(isdefinedsymbol(SOFT_DEVICE_BIN))
-{
-  place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
-}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52840.icf	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,57 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+    define symbol MBED_APP_START = 0x21000;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+    define symbol MBED_APP_SIZE = 0xDF000;
+}
+
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__     = MBED_APP_START + MBED_APP_SIZE - 1;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20003288;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2003ffff;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__   = 0x800;
+define symbol __ICFEDIT_size_heap__     = 0x3000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __code_start_soft_device__ = 0x0;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block HEAP,
+                        block CSTACK };
+
+/*This is used for mbed applications build inside the Embedded workbench
+Applications build with the python scritps use a hex merge so need to merge it
+inside the linker. The linker can only use binary files so the hex merge is not possible
+through the linker. That is why a binary is used instead of a hex image for the embedded project.
+*/
+if(isdefinedsymbol(SOFT_DEVICE_BIN))
+{
+  place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
+}

--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h	Wed Jan 17 15:23:54 2018 +0000
@@ -1,28 +1,28 @@
-/* 
+/*
  * Copyright (c) 2013 Nordic Semiconductor ASA
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
- * 
- *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *
+ *   1. Redistributions of source code must retain the above copyright notice, this list
  *      of conditions and the following disclaimer.
  *
- *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
- *      integrated circuit in a product or a software update for such product, must reproduce 
- *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
+ *      integrated circuit in a product or a software update for such product, must reproduce
+ *      the above copyright notice, this list of conditions and the following disclaimer in
  *      the documentation and/or other materials provided with the distribution.
  *
- *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
- *      used to endorse or promote products derived from this software without specific prior 
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
+ *      used to endorse or promote products derived from this software without specific prior
  *      written permission.
  *
- *   4. This software, with or without modification, must only be used with a 
+ *   4. This software, with or without modification, must only be used with a
  *      Nordic Semiconductor ASA integrated circuit.
  *
- *   5. Any software provided in binary or object form under this license must not be reverse 
- *      engineered, decompiled, modified and/or disassembled. 
- * 
+ *   5. Any software provided in binary or object form under this license must not be reverse
+ *      engineered, decompiled, modified and/or disassembled.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -33,7 +33,7 @@
  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  */
 
 
@@ -57,7 +57,7 @@
 #include "app_error.h"
 #include "app_util.h"
 
-#define BLE_STACK_EVT_MSG_BUF_SIZE       (sizeof(ble_evt_t) + (GATT_MTU_SIZE_DEFAULT))     /**< Size of BLE event message buffer. This will be provided to the SoftDevice while fetching an event. */
+#define BLE_STACK_EVT_MSG_BUF_SIZE       (sizeof(ble_evt_t) + (3 * sizeof(ble_gattc_attr_info_t)) + (GATT_MTU_SIZE_DEFAULT))     /**< Size of BLE event message buffer. This will be provided to the SoftDevice while fetching an event. */
 #define BLE_STACK_HANDLER_SCHED_EVT_SIZE 0                                                 /**< The size of the scheduler event used by SoftDevice handler when passing BLE events using the @ref app_scheduler. */
 
 /**@brief Application stack event handler type. */

--- a/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c	Wed Jan 17 15:23:54 2018 +0000
@@ -15,43 +15,88 @@
  * limitations under the License.
  */
 
-#include <stdint.h>                  // uint32_t, UINT32_MAX
-#include <assert.h>                  // uint32_t, UINT32_MAX
-#include "cmsis.h"
-#include "nrf_soc.h"
-#include "nrf_sdm.h"
-#include "nrf_nvic.h"
+#include <stdint.h>
+#include "app_util_platform.h"
 
-static uint8_t  _sd_state = 0;
-static volatile uint32_t _entry_count = 0;
+#if defined(SOFTDEVICE_PRESENT)
+static volatile uint32_t nordic_cr_nested = 0;
+
+static void nordic_nvic_critical_region_enter(void);
+static void nordic_nvic_critical_region_exit(void);
+#endif
 
 void core_util_critical_section_enter()
 {
-    // if a critical section has already been entered, just update the counter
-    if (_entry_count) {
-        ++_entry_count;
-        return;
-    }
+#ifdef NRF52
+    ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get())
+#endif
 
-    // in this path, a critical section has never been entered
-    // routine of SD V11 work even if the softdevice is not active
-    sd_nvic_critical_region_enter(&_sd_state);
-
-    assert(_entry_count == 0); // entry count should always be equal to 0 at this point
-    ++_entry_count;
+#if defined(SOFTDEVICE_PRESENT)
+    /* return value can be safely ignored */
+    nordic_nvic_critical_region_enter();
+#else
+    app_util_disable_irq();
+#endif
 }
 
 void core_util_critical_section_exit()
 {
-    assert(_entry_count > 0);
-    --_entry_count;
+#ifdef NRF52
+    ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get())
+#endif
+
+#if defined(SOFTDEVICE_PRESENT)
+    /* return value can be safely ignored */
+    nordic_nvic_critical_region_exit();
+#else
+    app_util_enable_irq();
+#endif
+}
 
-    // If their is other segments which have entered the critical section, just leave
-    if (_entry_count) {
-        return;
+#if defined(SOFTDEVICE_PRESENT)
+/**@brief Enters critical region.
+ *
+ * @post Application interrupts will be disabled.
+ * @sa nordic_nvic_critical_region_exit
+ */
+static inline void nordic_nvic_critical_region_enter(void)
+{
+    int was_masked = __sd_nvic_irq_disable();
+
+    if (nordic_cr_nested == 0) {
+            nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 );
+            NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0;
+#ifdef NRF52
+            nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 );
+            NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1;
+#endif
     }
 
-    // This is the last segment of the critical section, state should be restored as before entering
-    // the critical section
-    sd_nvic_critical_region_exit(_sd_state);
+    nordic_cr_nested++;
+
+    if (!was_masked) {
+        __sd_nvic_irq_enable();
+    }
 }
+
+/**@brief Exit critical region.
+ *
+ * @pre Application has entered a critical region using ::nordic_nvic_critical_region_enter.
+ * @post If not in a nested critical region, the application interrupts will restored to the state before ::nordic_nvic_critical_region_enter was called.
+ */
+static inline void nordic_nvic_critical_region_exit(void)
+{
+    nordic_cr_nested--;
+
+    if (nordic_cr_nested == 0) {
+        int was_masked = __sd_nvic_irq_disable();
+        NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0];
+#ifdef NRF52
+        NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1];
+#endif
+        if (!was_masked) {
+        __sd_nvic_irq_enable();
+        }
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,255 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "mbed_critical.h"
+#include "mbed_error.h"
+#include <limits.h>
+#include "nu_modutil.h"
+#include "nu_bitutil.h"
+#include "crypto-misc.h"
+
+/* Track if AES H/W is available */
+static uint16_t crypto_aes_avail = 1;
+/* Track if DES H/W is available */
+static uint16_t crypto_des_avail = 1;
+/* Track if SHA H/W is available */
+static uint16_t crypto_sha_avail = 1;
+
+/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */
+static uint16_t crypto_init_counter = 0U;
+
+static bool crypto_submodule_acquire(uint16_t *submodule_avail);
+static void crypto_submodule_release(uint16_t *submodule_avail);
+
+/* Track if PRNG H/W operation is done */
+static volatile uint16_t crypto_prng_done;
+/* Track if AES H/W operation is done */
+static volatile uint16_t crypto_aes_done;
+/* Track if DES H/W operation is done */
+static volatile uint16_t crypto_des_done;
+
+static void crypto_submodule_prestart(volatile uint16_t *submodule_done);
+static bool crypto_submodule_wait(volatile uint16_t *submodule_done);
+
+/* As crypto init counter changes from 0 to 1:
+ *
+ * 1. Enable crypto clock
+ * 2. Enable crypto interrupt
+ */
+void crypto_init(void)
+{
+    core_util_critical_section_enter();
+    if (crypto_init_counter == USHRT_MAX) {
+        core_util_critical_section_exit();
+        error("Crypto clock enable counter would overflow (> USHRT_MAX)");
+    }
+    core_util_atomic_incr_u16(&crypto_init_counter, 1);
+    if (crypto_init_counter == 1) {
+        SYS_UnlockReg();    // Unlock protected register
+        CLK_EnableModuleClock(CRPT_MODULE);
+        SYS_LockReg();      // Lock protected register
+        
+        NVIC_EnableIRQ(CRPT_IRQn);
+    }
+    core_util_critical_section_exit();
+}
+
+/* As crypto init counter changes from 1 to 0:
+ *
+ * 1. Disable crypto interrupt 
+ * 2. Disable crypto clock
+ */
+void crypto_uninit(void)
+{
+    core_util_critical_section_enter();
+    if (crypto_init_counter == 0) {
+        core_util_critical_section_exit();
+        error("Crypto clock enable counter would underflow (< 0)");
+    }
+    core_util_atomic_decr_u16(&crypto_init_counter, 1);
+    if (crypto_init_counter == 0) {
+        NVIC_DisableIRQ(CRPT_IRQn);
+        
+        SYS_UnlockReg();    // Unlock protected register
+        CLK_DisableModuleClock(CRPT_MODULE);
+        SYS_LockReg();      // Lock protected register
+    }
+    core_util_critical_section_exit();
+}
+
+/* Implementation that should never be optimized out by the compiler */
+void crypto_zeroize(void *v, size_t n)
+{
+    volatile unsigned char *p = (unsigned char*) v;
+    while (n--) {
+        *p++ = 0;
+    }
+}
+
+bool crypto_aes_acquire(void)
+{
+    return crypto_submodule_acquire(&crypto_aes_avail);
+}
+
+void crypto_aes_release(void)
+{
+    crypto_submodule_release(&crypto_aes_avail);
+}
+
+bool crypto_des_acquire(void)
+{
+    return crypto_submodule_acquire(&crypto_des_avail);
+}
+
+void crypto_des_release(void)
+{
+    crypto_submodule_release(&crypto_des_avail);
+}
+
+bool crypto_sha_acquire(void)
+{
+    return crypto_submodule_acquire(&crypto_sha_avail);
+}
+
+void crypto_sha_release(void)
+{
+    crypto_submodule_release(&crypto_sha_avail);
+}
+
+void crypto_prng_prestart(void)
+{
+    crypto_submodule_prestart(&crypto_prng_done);
+}
+
+bool crypto_prng_wait(void)
+{
+    return crypto_submodule_wait(&crypto_prng_done);
+}
+
+void crypto_aes_prestart(void)
+{
+    crypto_submodule_prestart(&crypto_aes_done);
+}
+
+bool crypto_aes_wait(void)
+{
+    return crypto_submodule_wait(&crypto_aes_done);
+}
+
+void crypto_des_prestart(void)
+{
+    crypto_submodule_prestart(&crypto_des_done);
+}
+
+bool crypto_des_wait(void)
+{
+    return crypto_submodule_wait(&crypto_des_done);
+}
+
+bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to)
+{
+    uint32_t buff_ = (uint32_t) buff;
+
+    return (((buff_ & 0x03) == 0) &&                                        /* Word-aligned buffer base address */
+        ((buff_size & (size_aligned_to - 1)) == 0) &&                       /* Crypto submodule dependent buffer size alignment */
+        (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_))));   /* 0x20000000-0x2FFFFFFF */
+}
+
+/* Overlap cases
+ *
+ * 1. in_buff in front of out_buff:
+ *
+ * in             in_end
+ * |              |
+ * ||||||||||||||||
+ *     ||||||||||||||||
+ *     |              |
+ *     out            out_end
+ *
+ * 2. out_buff in front of in_buff:
+ *
+ *     in             in_end
+ *     |              |
+ *     ||||||||||||||||
+ * ||||||||||||||||
+ * |              |
+ * out            out_end
+ */
+bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size)
+{
+    uint32_t in = (uint32_t) in_buff;
+    uint32_t in_end = in + in_buff_size;
+    uint32_t out = (uint32_t) out_buff;
+    uint32_t out_end = out + out_buff_size;
+
+    bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end);
+    
+    return overlap;
+}
+
+static bool crypto_submodule_acquire(uint16_t *submodule_avail)
+{
+    uint16_t expectedCurrentValue = 1;
+    return core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 0);
+}
+
+static void crypto_submodule_release(uint16_t *submodule_avail)
+{
+    uint16_t expectedCurrentValue = 0;
+    while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1));
+}
+
+static void crypto_submodule_prestart(volatile uint16_t *submodule_done)
+{
+    *submodule_done = 0;
+    
+    /* Ensure memory accesses above are completed before DMA is started
+     *
+     * Replacing __DSB() with __DMB() is also OK in this case.
+     *
+     * Refer to "multi-master systems" section with DMA in:
+     * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf
+     */
+    __DSB();
+}
+
+static bool crypto_submodule_wait(volatile uint16_t *submodule_done)
+{
+    while (! *submodule_done);
+
+    /* Ensure while loop above and subsequent code are not reordered */
+    __DSB();
+
+    return true;
+}
+
+/* Crypto interrupt handler */
+void CRYPTO_IRQHandler()
+{
+    if (PRNG_GET_INT_FLAG()) {
+        crypto_prng_done = 1;
+        PRNG_CLR_INT_FLAG();
+    }  else if (AES_GET_INT_FLAG()) {
+        crypto_aes_done = 1;
+        AES_CLR_INT_FLAG();
+    } else if (TDES_GET_INT_FLAG()) {
+        crypto_des_done = 1;
+        TDES_CLR_INT_FLAG();
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CRYPTO_MISC_H
+#define MBED_CRYPTO_MISC_H
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Init/Uninit crypto module */
+void crypto_init(void);
+void crypto_uninit(void);
+
+/* Clear buffer to zero
+ * Implementation that should never be optimized out by the compiler */
+void crypto_zeroize(void *v, size_t n);
+
+/* Acquire/release ownership of AES H/W */
+/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */
+bool crypto_aes_acquire(void);
+void crypto_aes_release(void);
+
+/* Acquire/release ownership of DES H/W */
+/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */
+bool crypto_des_acquire(void);
+void crypto_des_release(void);
+
+/* Acquire/release ownership of SHA H/W */
+/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */
+bool crypto_sha_acquire(void);
+void crypto_sha_release(void);
+
+/* Flow control between crypto/xxx start and crypto/xxx ISR 
+ *
+ * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR.
+ * 
+ * crypto_xxx_prestart will also address synchronization issue with memory barrier instruction.
+ *
+ * On finish, return of crypto_xxx_wait indicates success or not:
+ *   true if successful
+ *   false if failed
+ *
+ * Example: Start AES H/W and wait for its finish
+ *   crypto_aes_prestart();
+ *   AES_Start();
+ *   crypto_aes_wait();
+ */
+void crypto_prng_prestart(void);
+bool crypto_prng_wait(void);
+void crypto_aes_prestart(void);
+bool crypto_aes_wait(void);
+void crypto_des_prestart(void);
+bool crypto_des_wait(void);
+
+
+/* Check if buffer can be used for crypto DMA. It has the following requirements:
+ * (1) Word-aligned buffer base address
+ * (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power.
+ * (3) Located in 0x20000000-0x2FFFFFFF region
+ */
+bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to);
+
+/* Check if input/output buffers are overlapped */
+bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -21,6 +21,7 @@
 #include "cmsis.h"
 #include "us_ticker_api.h"
 #include "trng_api.h"
+#include "crypto-misc.h"
 
 /*
  * Get Random number generator.
@@ -28,25 +29,6 @@
 
 #define PRNG_KEY_SIZE  (0x20UL)
 
-static volatile int  g_PRNG_done;
-volatile int  g_AES_done;
-
-/* Implementation that should never be optimized out by the compiler */
-static void trng_zeroize( void *v, size_t n ) {
-    volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
-}
-
-void CRYPTO_IRQHandler()
-{
-    if (PRNG_GET_INT_FLAG()) {
-        g_PRNG_done = 1;
-        PRNG_CLR_INT_FLAG();
-    } else	if (AES_GET_INT_FLAG()) {
-        g_AES_done = 1;
-        AES_CLR_INT_FLAG();
-    }
-}
-
 static void trng_get(unsigned char *pConversionData)
 {
     uint32_t *p32ConversionData;
@@ -54,8 +36,9 @@
     p32ConversionData = (uint32_t *)pConversionData;
 
     PRNG_Open(PRNG_KEY_SIZE_256, 1, us_ticker_read());
+    crypto_prng_prestart();
     PRNG_Start();
-    while (!g_PRNG_done);
+    crypto_prng_wait();
 
     PRNG_Read(p32ConversionData);
 }
@@ -63,23 +46,21 @@
 void trng_init(trng_t *obj)
 {
     (void)obj;
-    /* Unlock protected registers */
-    SYS_UnlockReg();
-    /* Enable IP clock */
-    CLK_EnableModuleClock(CRPT_MODULE);
-
-    /* Lock protected registers */
-    SYS_LockReg();
-
-    NVIC_EnableIRQ(CRPT_IRQn);
+    
+    /* Init crypto module */
+    crypto_init();
+    
     PRNG_ENABLE_INT();
 }
 
 void trng_free(trng_t *obj)
 {
     (void)obj;
+    
     PRNG_DISABLE_INT();
-    NVIC_DisableIRQ(CRPT_IRQn);
+    
+    /* Uninit crypto module */
+    crypto_uninit();
 }
 
 int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
@@ -98,11 +79,10 @@
         trng_get(tmpBuff);
         memcpy(output, tmpBuff, length);
         cur_length += length;
-        trng_zeroize(tmpBuff, sizeof(tmpBuff));
+        crypto_zeroize(tmpBuff, sizeof(tmpBuff));
     }
     *output_length = cur_length;
     return 0;
 }
 
 #endif
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,255 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "mbed_critical.h"
+#include "mbed_error.h"
+#include <limits.h>
+#include "nu_modutil.h"
+#include "nu_bitutil.h"
+#include "crypto-misc.h"
+
+/* Track if AES H/W is available */
+static uint16_t crypto_aes_avail = 1;
+/* Track if DES H/W is available */
+static uint16_t crypto_des_avail = 1;
+/* Track if SHA H/W is available */
+static uint16_t crypto_sha_avail = 1;
+
+/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */
+static uint16_t crypto_init_counter = 0U;
+
+static bool crypto_submodule_acquire(uint16_t *submodule_avail);
+static void crypto_submodule_release(uint16_t *submodule_avail);
+
+/* Track if PRNG H/W operation is done */
+static volatile uint16_t crypto_prng_done;
+/* Track if AES H/W operation is done */
+static volatile uint16_t crypto_aes_done;
+/* Track if DES H/W operation is done */
+static volatile uint16_t crypto_des_done;
+
+static void crypto_submodule_prestart(volatile uint16_t *submodule_done);
+static bool crypto_submodule_wait(volatile uint16_t *submodule_done);
+
+/* As crypto init counter changes from 0 to 1:
+ *
+ * 1. Enable crypto clock
+ * 2. Enable crypto interrupt
+ */
+void crypto_init(void)
+{
+    core_util_critical_section_enter();
+    if (crypto_init_counter == USHRT_MAX) {
+        core_util_critical_section_exit();
+        error("Crypto clock enable counter would overflow (> USHRT_MAX)");
+    }
+    core_util_atomic_incr_u16(&crypto_init_counter, 1);
+    if (crypto_init_counter == 1) {
+        SYS_UnlockReg();    // Unlock protected register
+        CLK_EnableModuleClock(CRPT_MODULE);
+        SYS_LockReg();      // Lock protected register
+        
+        NVIC_EnableIRQ(CRPT_IRQn);
+    }
+    core_util_critical_section_exit();
+}
+
+/* As crypto init counter changes from 1 to 0:
+ *
+ * 1. Disable crypto interrupt 
+ * 2. Disable crypto clock
+ */
+void crypto_uninit(void)
+{
+    core_util_critical_section_enter();
+    if (crypto_init_counter == 0) {
+        core_util_critical_section_exit();
+        error("Crypto clock enable counter would underflow (< 0)");
+    }
+    core_util_atomic_decr_u16(&crypto_init_counter, 1);
+    if (crypto_init_counter == 0) {
+        NVIC_DisableIRQ(CRPT_IRQn);
+        
+        SYS_UnlockReg();    // Unlock protected register
+        CLK_DisableModuleClock(CRPT_MODULE);
+        SYS_LockReg();      // Lock protected register
+    }
+    core_util_critical_section_exit();
+}
+
+/* Implementation that should never be optimized out by the compiler */
+void crypto_zeroize(void *v, size_t n)
+{
+    volatile unsigned char *p = (unsigned char*) v;
+    while (n--) {
+        *p++ = 0;
+    }
+}
+
+bool crypto_aes_acquire(void)
+{
+    return crypto_submodule_acquire(&crypto_aes_avail);
+}
+
+void crypto_aes_release(void)
+{
+    crypto_submodule_release(&crypto_aes_avail);
+}
+
+bool crypto_des_acquire(void)
+{
+    return crypto_submodule_acquire(&crypto_des_avail);
+}
+
+void crypto_des_release(void)
+{
+    crypto_submodule_release(&crypto_des_avail);
+}
+
+bool crypto_sha_acquire(void)
+{
+    return crypto_submodule_acquire(&crypto_sha_avail);
+}
+
+void crypto_sha_release(void)
+{
+    crypto_submodule_release(&crypto_sha_avail);
+}
+
+void crypto_prng_prestart(void)
+{
+    crypto_submodule_prestart(&crypto_prng_done);
+}
+
+bool crypto_prng_wait(void)
+{
+    return crypto_submodule_wait(&crypto_prng_done);
+}
+
+void crypto_aes_prestart(void)
+{
+    crypto_submodule_prestart(&crypto_aes_done);
+}
+
+bool crypto_aes_wait(void)
+{
+    return crypto_submodule_wait(&crypto_aes_done);
+}
+
+void crypto_des_prestart(void)
+{
+    crypto_submodule_prestart(&crypto_des_done);
+}
+
+bool crypto_des_wait(void)
+{
+    return crypto_submodule_wait(&crypto_des_done);
+}
+
+bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to)
+{
+    uint32_t buff_ = (uint32_t) buff;
+
+    return (((buff_ & 0x03) == 0) &&                                        /* Word-aligned buffer base address */
+        ((buff_size & (size_aligned_to - 1)) == 0) &&                       /* Crypto submodule dependent buffer size alignment */
+        (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_))));   /* 0x20000000-0x2FFFFFFF */
+}
+
+/* Overlap cases
+ *
+ * 1. in_buff in front of out_buff:
+ *
+ * in             in_end
+ * |              |
+ * ||||||||||||||||
+ *     ||||||||||||||||
+ *     |              |
+ *     out            out_end
+ *
+ * 2. out_buff in front of in_buff:
+ *
+ *     in             in_end
+ *     |              |
+ *     ||||||||||||||||
+ * ||||||||||||||||
+ * |              |
+ * out            out_end
+ */
+bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size)
+{
+    uint32_t in = (uint32_t) in_buff;
+    uint32_t in_end = in + in_buff_size;
+    uint32_t out = (uint32_t) out_buff;
+    uint32_t out_end = out + out_buff_size;
+
+    bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end);
+    
+    return overlap;
+}
+
+static bool crypto_submodule_acquire(uint16_t *submodule_avail)
+{
+    uint16_t expectedCurrentValue = 1;
+    return core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 0);
+}
+
+static void crypto_submodule_release(uint16_t *submodule_avail)
+{
+    uint16_t expectedCurrentValue = 0;
+    while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1));
+}
+
+static void crypto_submodule_prestart(volatile uint16_t *submodule_done)
+{
+    *submodule_done = 0;
+    
+    /* Ensure memory accesses above are completed before DMA is started
+     *
+     * Replacing __DSB() with __DMB() is also OK in this case.
+     *
+     * Refer to "multi-master systems" section with DMA in:
+     * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf
+     */
+    __DSB();
+}
+
+static bool crypto_submodule_wait(volatile uint16_t *submodule_done)
+{
+    while (! *submodule_done);
+
+    /* Ensure while loop above and subsequent code are not reordered */
+    __DSB();
+
+    return true;
+}
+
+/* Crypto interrupt handler */
+void CRYPTO_IRQHandler()
+{
+    if (PRNG_GET_INT_FLAG()) {
+        crypto_prng_done = 1;
+        PRNG_CLR_INT_FLAG();
+    }  else if (AES_GET_INT_FLAG()) {
+        crypto_aes_done = 1;
+        AES_CLR_INT_FLAG();
+    } else if (TDES_GET_INT_FLAG()) {
+        crypto_des_done = 1;
+        TDES_CLR_INT_FLAG();
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CRYPTO_MISC_H
+#define MBED_CRYPTO_MISC_H
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Init/Uninit crypto module */
+void crypto_init(void);
+void crypto_uninit(void);
+
+/* Clear buffer to zero
+ * Implementation that should never be optimized out by the compiler */
+void crypto_zeroize(void *v, size_t n);
+
+/* Acquire/release ownership of AES H/W */
+/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */
+bool crypto_aes_acquire(void);
+void crypto_aes_release(void);
+
+/* Acquire/release ownership of DES H/W */
+/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */
+bool crypto_des_acquire(void);
+void crypto_des_release(void);
+
+/* Acquire/release ownership of SHA H/W */
+/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */
+bool crypto_sha_acquire(void);
+void crypto_sha_release(void);
+
+/* Flow control between crypto/xxx start and crypto/xxx ISR 
+ *
+ * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR.
+ * 
+ * crypto_xxx_prestart will also address synchronization issue with memory barrier instruction.
+ *
+ * On finish, return of crypto_xxx_wait indicates success or not:
+ *   true if successful
+ *   false if failed
+ *
+ * Example: Start AES H/W and wait for its finish
+ *   crypto_aes_prestart();
+ *   AES_Start();
+ *   crypto_aes_wait();
+ */
+void crypto_prng_prestart(void);
+bool crypto_prng_wait(void);
+void crypto_aes_prestart(void);
+bool crypto_aes_wait(void);
+void crypto_des_prestart(void);
+bool crypto_des_wait(void);
+
+
+/* Check if buffer can be used for crypto DMA. It has the following requirements:
+ * (1) Word-aligned buffer base address
+ * (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power.
+ * (3) Located in 0x20000000-0x2FFFFFFF region
+ */
+bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to);
+
+/* Check if input/output buffers are overlapped */
+bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     crypto.c
  * @version  V1.10
- * $Revision: 11 $
- * $Date: 14/10/03 1:54p $
+ * $Revision: 12 $
+ * $Date: 15/11/06 2:17p $
  * @brief  Cryptographic Accelerator driver source file
  *
  * @note
@@ -141,13 +141,15 @@
   */
 void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize)
 {
-    int       i, wcnt;
-    uint32_t  *key_ptr;
+    uint32_t  i, wcnt, key_reg_addr;
+
+    key_reg_addr = (uint32_t)&CRPT->AES0_KEY0 + (u32Channel * 0x3CUL);
+    wcnt = 4UL + u32KeySize*2UL;
 
-    key_ptr = (uint32_t *)((uint32_t)&CRPT->AES0_KEY0 + (u32Channel * 0x3C));
-    wcnt = 4 + u32KeySize*2;
-    for (i = 0; i < wcnt; i++, key_ptr++)
-        *key_ptr = au32Keys[i];
+    for (i = 0U; i < wcnt; i++) {
+        outpw(key_reg_addr, au32Keys[i]);
+        key_reg_addr += 4UL;
+    }
 }
 
 /**
@@ -158,12 +160,14 @@
   */
 void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[])
 {
-    int       i;
-    uint32_t  *key_ptr;
+    uint32_t  i, key_reg_addr;
+
+    key_reg_addr = (uint32_t)&CRPT->AES0_IV0 + (u32Channel * 0x3CUL);
 
-    key_ptr = (uint32_t *)((uint32_t)&CRPT->AES0_IV0 + (u32Channel * 0x3C));
-    for (i = 0; i < 4; i++, key_ptr++)
-        *key_ptr = au32IV[i];
+    for (i = 0U; i < 4U; i++) {
+        outpw(key_reg_addr, au32IV[i]);
+        key_reg_addr += 4UL;
+    }
 }
 
 /**
@@ -177,15 +181,24 @@
 void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr,
                         uint32_t u32DstAddr, uint32_t u32TransCnt)
 {
-    *(uint32_t *)((uint32_t)&CRPT->AES0_SADDR + (u32Channel * 0x3C)) = u32SrcAddr;
-    *(uint32_t *)((uint32_t)&CRPT->AES0_DADDR + (u32Channel * 0x3C)) = u32DstAddr;
-    *(uint32_t *)((uint32_t)&CRPT->AES0_CNT + (u32Channel * 0x3C)) = u32TransCnt;
+    uint32_t  reg_addr;
+
+    reg_addr = (uint32_t)&CRPT->AES0_SADDR + (u32Channel * 0x3CUL);
+    outpw(reg_addr, u32SrcAddr);
+
+    reg_addr = (uint32_t)&CRPT->AES0_DADDR + (u32Channel * 0x3CUL);
+    outpw(reg_addr, u32DstAddr);
+
+    reg_addr = (uint32_t)&CRPT->AES0_CNT + (u32Channel * 0x3CUL);
+    outpw(reg_addr, u32TransCnt);
 }
 
 /**
   * @brief  Open TDES encrypt/decrypt function.
   * @param[in]  u32Channel   TDES channel. Must be 0~3.
   * @param[in]  u32EncDec    1: TDES encode; 0: TDES decode
+  * @param[in]  Is3DES       1: TDES; 0: DES
+  * @param[in]  Is3Key       1: TDES 3 key mode; 0: TDES 2 key mode
   * @param[in]  u32OpMode    TDES operation mode, including:
   *         - \ref TDES_MODE_ECB
   *         - \ref TDES_MODE_CBC
@@ -203,12 +216,18 @@
   *         - \ref TDES_IN_OUT_WHL_SWAP
   * @return None
   */
-void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32SwapType)
+void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key,
+               uint32_t u32OpMode, uint32_t u32SwapType)
 {
     g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) |
                              (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) |
-                             u32OpMode |
-                             (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos);
+                             u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos);
+    if (Is3DES) {
+        g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk;
+    }
+    if (Is3Key) {
+        g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk;
+    }
 }
 
 /**
@@ -229,17 +248,21 @@
 /**
   * @brief  Set TDES keys
   * @param[in]  u32Channel  TDES channel. Must be 0~3.
-  * @param[in]  au8Keys     The TDES keys.
+  * @param[in]  au32Keys    The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word.
   * @return None
   */
-void TDES_SetKey(uint32_t u32Channel, uint8_t au8Keys[3][8])
+void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2])
 {
-    int         i;
-    uint8_t     *pu8TKey;
+    uint32_t   i, reg_addr;
+
+    reg_addr = (uint32_t)&CRPT->TDES0_KEY1H + (0x40UL * u32Channel);
 
-    pu8TKey = (uint8_t *)((uint32_t)&CRPT->TDES0_KEY1H + (0x40 * u32Channel));
-    for (i = 0; i < 3; i++, pu8TKey+=8)
-        memcpy(pu8TKey, &au8Keys[i][0], 8);
+    for (i = 0U; i < 3U; i++) {
+        outpw(reg_addr, au32Keys[i][0]);   /* TDESn_KEYxH */
+        reg_addr += 4UL;
+        outpw(reg_addr, au32Keys[i][1]);   /* TDESn_KEYxL */
+        reg_addr += 4UL;
+    }
 }
 
 /**
@@ -251,8 +274,13 @@
   */
 void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL)
 {
-    *(uint32_t *)((uint32_t)&CRPT->TDES0_IVH + 0x40 * u32Channel) = u32IVH;
-    *(uint32_t *)((uint32_t)&CRPT->TDES0_IVL + 0x40 * u32Channel) = u32IVL;
+    uint32_t  reg_addr;
+
+    reg_addr = (uint32_t)&CRPT->TDES0_IVH + (u32Channel * 0x40UL);
+    outpw(reg_addr, u32IVH);
+
+    reg_addr = (uint32_t)&CRPT->TDES0_IVL + (u32Channel * 0x40UL);
+    outpw(reg_addr, u32IVL);
 }
 
 /**
@@ -266,9 +294,16 @@
 void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr,
                          uint32_t u32DstAddr, uint32_t u32TransCnt)
 {
-    *(uint32_t *)((uint32_t)&CRPT->TDES0_SADDR + (u32Channel * 0x40)) = u32SrcAddr;
-    *(uint32_t *)((uint32_t)&CRPT->TDES0_DADDR + (u32Channel * 0x40)) = u32DstAddr;
-    *(uint32_t *)((uint32_t)&CRPT->TDES0_CNT + (u32Channel * 0x40)) = u32TransCnt;
+    uint32_t  reg_addr;
+
+    reg_addr = (uint32_t)&CRPT->TDES0_SADDR + (u32Channel * 0x40UL);
+    outpw(reg_addr, u32SrcAddr);
+
+    reg_addr = (uint32_t)&CRPT->TDES0_DADDR + (u32Channel * 0x40UL);
+    outpw(reg_addr, u32DstAddr);
+
+    reg_addr = (uint32_t)&CRPT->TDES0_CNT + (u32Channel * 0x40UL);
+    outpw(reg_addr, u32TransCnt);
 }
 
 /**

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h	Wed Jan 17 15:23:54 2018 +0000
@@ -275,9 +275,9 @@
 void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
 void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]);
 void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
-void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32SwapType);
+void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType);
 void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode);
-void TDES_SetKey(uint32_t u32Channel, uint8_t au8Keys[3][8]);
+void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2]);
 void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL);
 void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
 void SHA_Open(uint32_t u32OpMode, uint32_t u32SwapType);

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -23,9 +23,9 @@
 #include <stdlib.h>
 #include <string.h>
 #include "cmsis.h"
-#include "NUC472_442.h"
 #include "us_ticker_api.h"
 #include "trng_api.h"
+#include "crypto-misc.h"
 
 /*
  * Get Random number generator.
@@ -33,25 +33,6 @@
 
 #define PRNG_KEY_SIZE  (0x20UL)
 
-static volatile int  g_PRNG_done;
-volatile int  g_AES_done;
-
-/* Implementation that should never be optimized out by the compiler */
-static void trng_zeroize( void *v, size_t n ) {
-    volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
-}
-
-void CRYPTO_IRQHandler()
-{
-    if (PRNG_GET_INT_FLAG()) {
-        g_PRNG_done = 1;
-        PRNG_CLR_INT_FLAG();
-    }  else if (AES_GET_INT_FLAG()) {
-        g_AES_done = 1;
-        AES_CLR_INT_FLAG();
-    }
-} 
-
 static void trng_get(unsigned char *pConversionData)
 {
     uint32_t *p32ConversionData;
@@ -59,8 +40,9 @@
     p32ConversionData = (uint32_t *)pConversionData;
 
     PRNG_Open(PRNG_KEY_SIZE_256, 1, us_ticker_read());
+    crypto_prng_prestart();
     PRNG_Start();
-    while (!g_PRNG_done);
+    crypto_prng_wait();
 
     PRNG_Read(p32ConversionData);
 }
@@ -68,23 +50,21 @@
 void trng_init(trng_t *obj)
 {
     (void)obj;
-    /* Unlock protected registers */
-    SYS_UnlockReg();    
-    /* Enable IP clock */
-    CLK_EnableModuleClock(CRPT_MODULE);
     
-    /* Lock protected registers */
-    SYS_LockReg();
+    /* Init crypto module */
+    crypto_init();
     
-    NVIC_EnableIRQ(CRPT_IRQn);
     PRNG_ENABLE_INT();
 }
 
 void trng_free(trng_t *obj)
 {
     (void)obj;
+    
     PRNG_DISABLE_INT();
-    NVIC_DisableIRQ(CRPT_IRQn);
+    
+    /* Uninit crypto module */
+    crypto_uninit();
 }
 
 int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
@@ -103,11 +83,10 @@
         trng_get(tmpBuff);
         memcpy(output, tmpBuff, length);
         cur_length += length;
-        trng_zeroize(tmpBuff, sizeof(tmpBuff));
+        crypto_zeroize(tmpBuff, sizeof(tmpBuff));
     }
     *output_length = cur_length;
     return 0;
 }
- 
+
 #endif
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/nu_timer.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef NU_TIMER_H
+#define NU_TIMER_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "cmsis.h"
+#include "mbed_sleep.h"
+#include "mbed_critical.h"
+#include "ticker_api.h"
+#include "us_ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* A simple count-down timer used for Nuvoton ported drivers
+ *
+ * NOTE: nu_countdown_init must be paired with nu_countdown_free.
+ *
+ * Example:
+ * nu_countdown_ctx_s ctx;
+ * 
+ * // Set up 2 ms timeout
+ * nu_countdown_init(&ctx, 2000);
+ *
+ * // Timed-wait for a task
+ * while (true) {
+ *     // Poll the task
+ *
+ *     if (nu_countdown_expired(&ctx)) {
+ *         // Timeout
+ *     }
+ * }
+ *
+ * // Must pair nu_countdown_init with nu_countdown_free in the end
+ * nu_countdown_free(&ctx);
+ */
+
+struct nu_countdown_ctx_s {
+    const ticker_data_t *   _ticker_data;       // Hold ticker_data_t
+    us_timestamp_t          _interval_end_us;   // End of interval in us
+    bool                    _expired;           // Expired or not
+};
+
+__STATIC_INLINE void nu_countdown_init(struct nu_countdown_ctx_s *ctx, us_timestamp_t interval_us)
+{
+    core_util_critical_section_enter();
+    sleep_manager_lock_deep_sleep();
+    ctx->_ticker_data = get_us_ticker_data();
+    ctx->_interval_end_us = ticker_read_us(ctx->_ticker_data) + interval_us;
+    ctx->_expired = false;
+    core_util_critical_section_exit();
+}
+
+__STATIC_INLINE bool nu_countdown_expired(struct nu_countdown_ctx_s *ctx)
+{
+    core_util_critical_section_enter();
+    if (! ctx->_expired) {
+        ctx->_expired = ticker_read_us(ctx->_ticker_data) >= ctx->_interval_end_us;
+    }
+    core_util_critical_section_exit();
+    
+    return ctx->_expired;
+}
+
+__STATIC_INLINE void nu_countdown_free(struct nu_countdown_ctx_s *ctx)
+{
+    core_util_critical_section_enter();
+    sleep_manager_unlock_deep_sleep();
+    core_util_critical_section_exit();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c	Wed Jan 17 15:23:54 2018 +0000
@@ -120,6 +120,6 @@
     {P0_19   , PWM_3,  4},
     {P0_22   , PWM_4,  4},
     {P0_28   , PWM_8,  4},
-    {P0_29   , PWM_9,  4},
+    {P1_31   , PWM_7,  4},
     {NC      , NC,     0}
 };

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h	Wed Jan 17 15:23:54 2018 +0000
@@ -183,9 +183,9 @@
 
 
     // mbed original LED naming
-    LED1 = P0_13,
+    LED1 = P1_3,
     LED2 = P1_27,
-    LED3 = P0_14,
+    LED3 = P1_26,
     LED4 = P1_28,
 
 
@@ -223,7 +223,7 @@
     p23 = P0_19,
     p24 = P0_22,
     p25 = P0_28,
-    p26 = P0_29,
+    p26 = P1_31,
     p27 = P1_30,
     p28 = P1_29,
     p29 = P0_0,

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,278 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_phy.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief Defines the timeout macro. */
-#define PHY_TIMEOUT_COUNT 0xFFFFFFU
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*!
- * @brief Get the ENET instance from peripheral base address.
- *
- * @param base ENET peripheral base address.
- * @return ENET instance.
- */
-extern uint32_t ENET_GetInstance(ENET_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Pointers to enet clocks for each instance. */
-#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
-extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
-#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
-extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_LPC_ENET_COUNT];
-#endif
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
-{
-    uint32_t reg;
-    uint32_t idReg = 0;
-    uint32_t delay = PHY_TIMEOUT_COUNT;
-    uint32_t instance = ENET_GetInstance(base);
-    bool status = false;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Set SMI first. */
-    CLOCK_EnableClock(s_enetClock[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
-    ENET_SetSMI(base, srcClock_Hz, false);
-#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
-    ENET_SetSMI(base);
-#endif
-    /* Initialization after PHY stars to work. */
-    while ((idReg != PHY_CONTROL_ID1) && (delay != 0))
-    {
-        PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
-        delay --;       
-    }
-
-    if (!delay)
-    {
-        return kStatus_Fail;
-    }
-    delay = PHY_TIMEOUT_COUNT;
-
-    /* Reset PHY and wait until completion. */
-    PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
-    do
-    {
-        PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &reg);
-    } while (delay-- && reg & PHY_BCTL_RESET_MASK);
-
-    if (!delay)
-    {
-        return kStatus_Fail;
-    }
-
-    /* Set the ability. */
-    PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_ALL_CAPABLE_MASK | 0x1U));
-
-    /* Start Auto negotiation and wait until auto negotiation completion */
-    PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
-    delay = PHY_TIMEOUT_COUNT;
-    do
-    {
-        PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, &reg);
-        delay --;
-    } while (delay && ((reg & PHY_SPECIALCTL_AUTONEGDONE_MASK) == 0));
-
-    if (!delay)
-    {
-        return kStatus_Fail;
-    }
-
-    /* Waiting a moment for phy stable. */
-    for (delay = 0; delay < PHY_TIMEOUT_COUNT; delay++)
-    {
-        __ASM("nop");
-        PHY_GetLinkStatus(base, phyAddr, &status);
-        if (status)
-        {
-            break;
-        }
-    }
-
-    return kStatus_Success;
-}
-
-status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
-{
-#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
-    uint32_t counter;
-
-    /* Clear the SMI interrupt event. */
-    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
-
-    /* Starts a SMI write command. */
-    ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
-
-    /* Wait for SMI complete. */
-    for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
-    {
-        if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
-        {
-            break;
-        }
-    }
-
-    /* Check for timeout. */
-    if (!counter)
-    {
-        return kStatus_PHY_SMIVisitTimeout;
-    }
-
-    /* Clear MII interrupt event. */
-    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
-
-#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
-    ENET_StartSMIWrite(base, phyAddr, phyReg, data);
-    while (ENET_IsSMIBusy(base))
-        ;
-#endif
-    return kStatus_Success;
-}
-
-status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
-{
-#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
-     assert(dataPtr);
-
-    uint32_t counter;
-
-    /* Clear the MII interrupt event. */
-    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
-
-    /* Starts a SMI read command operation. */
-    ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
-
-    /* Wait for MII complete. */
-    for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
-    {
-        if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
-        {
-            break;
-        }
-    }
-
-    /* Check for timeout. */
-    if (!counter)
-    {
-        return kStatus_PHY_SMIVisitTimeout;
-    }
-
-    /* Get data from MII register. */
-    *dataPtr = ENET_ReadSMIData(base);
-
-    /* Clear MII interrupt event. */
-    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
-#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
-    ENET_StartSMIRead(base, phyAddr, phyReg);
-    while (ENET_IsSMIBusy(base))
-        ;
-    *dataPtr = ENET_ReadSMIData(base);
-#endif
-     return kStatus_Success;
-}
-
-status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
-{
-    uint32_t reg;
-    status_t result = kStatus_Success;
-
-    /* Read the basic status register. */
-    result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &reg);
-    if (result == kStatus_Success)
-    {
-        if (reg & PHY_BSTATUS_LINKSTATUS_MASK)
-        {
-            /* link up. */
-            *status = true;
-        }
-        else
-        {
-            *status = false;
-        }        
-    }
-    return result;
-}
-
-status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
-{
-    assert(duplex);
-    assert(speed);
-
-    uint32_t reg;
-    status_t result = kStatus_Success;
-
-    /* Read the control two register. */
-    result = PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, &reg);
-    if (result == kStatus_Success)
-    {
-        if (reg & PHY_SPECIALCTL_DUPLEX_MASK)
-        {
-            /* Full duplex. */
-            *duplex = kPHY_FullDuplex;
-        }
-        else
-        {
-            /* Half duplex. */
-            *duplex = kPHY_HalfDuplex;
-        }
-
-        if (reg & PHY_SPECIALCTL_100SPEED_MASK)
-        {
-            /* 100M speed. */
-            *speed = kPHY_Speed100M;
-        }
-        else
-        { /* 10M speed. */
-            *speed = kPHY_Speed10M;
-        }        
-    }
-    return result;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_PHY_H_
-#define _FSL_PHY_H_
-
-#include "fsl_enet.h"
-
-/*!
- * @addtogroup phy_driver
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief PHY driver version */
-#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
-
-/*! @brief Defines the PHY registers. */
-#define PHY_BASICCONTROL_REG 0x00U      /*!< The PHY basic control register. */
-#define PHY_BASICSTATUS_REG 0x01U       /*!< The PHY basic status register. */
-#define PHY_ID1_REG 0x02U               /*!< The PHY ID one register. */
-#define PHY_ID2_REG 0x03U               /*!< The PHY ID two register. */
-#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
-#define PHY_SEPCIAL_CONTROL_REG 0x1FU   /*!< The PHY control two register. */
-
-#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/
-
-/*! @brief Defines the mask flag in basic control register. */
-#define PHY_BCTL_DUPLEX_MASK 0x0100U          /*!< The PHY duplex bit mask. */
-#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
-#define PHY_BCTL_AUTONEG_MASK 0x1000U         /*!< The PHY auto negotiation bit mask. */
-#define PHY_BCTL_SPEED_MASK 0x2000U           /*!< The PHY speed bit mask. */
-#define PHY_BCTL_LOOP_MASK 0x4000U            /*!< The PHY loop bit mask. */
-#define PHY_BCTL_RESET_MASK 0x8000U           /*!< The PHY reset bit mask. */
-
-/*!@brief Defines the mask flag of operation mode in special control register*/
-#define PHY_SPECIALCTL_AUTONEGDONE_MASK 0x1000U /*!< The PHY auto-negotiation complete mask. */
-#define PHY_SPECIALCTL_DUPLEX_MASK 0x0010U      /*!< The PHY duplex mask. */
-#define PHY_SPECIALCTL_100SPEED_MASK 0x0008U    /*!< The PHY speed mask. */
-#define PHY_SPECIALCTL_10SPEED_MASK 0x0004U     /*!< The PHY speed mask. */
-#define PHY_SPECIALCTL_SPEEDUPLX_MASK 0x001cU   /*!< The PHY speed and duplex mask. */
-
-/*! @brief Defines the mask flag in basic status register. */
-#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
-
-/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
-#define PHY_ALL_CAPABLE_MASK 0x1e0U
-
-/*! @brief Defines the PHY status. */
-enum _phy_status
-{
-    kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 0),  /*!< ENET PHY SMI visit timeout. */
-};
-
-/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
-typedef enum _phy_speed {
-    kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
-    kPHY_Speed100M      /*!< ENET PHY 100M speed. */
-} phy_speed_t;
-
-/*! @brief Defines the PHY link duplex. */
-typedef enum _phy_duplex {
-    kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
-    kPHY_FullDuplex       /*!< ENET PHY full duplex. */
-} phy_duplex_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
-  * @name PHY Driver
-  * @{
-  */
-
-/*!
- * @brief Initializes PHY.
- *
- *  This function initialize the SMI interface and initialize PHY.
- *  The SMI is the MII management interface between PHY and MAC, which should be
- *  firstly initialized before any other operation for PHY.
- *
- * @param base       ENET peripheral base address.
- * @param phyAddr    The PHY address.
- * @param srcClock_Hz  The module clock frequency - system clock for MII management interface - SMI.
- * @retval kStatus_Success  PHY initialize success
- * @retval kStatus_Fail  PHY initialize fail
- */
-status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
-
-/*!
- * @brief PHY Write function. This function write data over the SMI to
- * the specified PHY register. This function is called by all PHY interfaces.
- *
- * @param base    ENET peripheral base address.
- * @param phyAddr The PHY address.
- * @param phyReg  The PHY register.
- * @param data    The data written to the PHY register.
- * @retval kStatus_Success     PHY write success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
-
-/*!
- * @brief PHY Read function. This interface read data over the SMI from the
- * specified PHY register. This function is called by all PHY interfaces.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param phyReg   The PHY register.
- * @param dataPtr  The address to store the data read from the PHY register.
- * @retval kStatus_Success  PHY read success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
-
-/*!
- * @brief Gets the PHY link status.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param status   The link up or down status of the PHY.
- *         - true the link is up.
- *         - false the link is down.
- * @retval kStatus_Success   PHY get link status success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
-
-/*!
- * @brief Gets the PHY link speed and duplex.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param speed    The address of PHY link speed.
- * @param duplex   The link duplex of PHY.
- * @retval kStatus_Success   PHY get link speed and duplex success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_PHY_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_phy.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Defines the timeout macro. */
+#define PHY_TIMEOUT_COUNT 0xFFFFFFU
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the ENET instance from peripheral base address.
+ *
+ * @param base ENET peripheral base address.
+ * @return ENET instance.
+ */
+extern uint32_t ENET_GetInstance(ENET_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to enet clocks for each instance. */
+#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
+extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
+#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
+extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_LPC_ENET_COUNT];
+#endif
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
+{
+    uint32_t reg;
+    uint32_t idReg = 0;
+    uint32_t delay = PHY_TIMEOUT_COUNT;
+    uint32_t instance = ENET_GetInstance(base);
+    bool status = false;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Set SMI first. */
+    CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
+    ENET_SetSMI(base, srcClock_Hz, false);
+#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
+    ENET_SetSMI(base);
+#endif
+    /* Initialization after PHY stars to work. */
+    while ((idReg != PHY_CONTROL_ID1) && (delay != 0))
+    {
+        PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
+        delay --;       
+    }
+
+    if (!delay)
+    {
+        return kStatus_Fail;
+    }
+    delay = PHY_TIMEOUT_COUNT;
+
+    /* Reset PHY and wait until completion. */
+    PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
+    do
+    {
+        PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &reg);
+    } while (delay-- && reg & PHY_BCTL_RESET_MASK);
+
+    if (!delay)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Set the ability. */
+    PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_ALL_CAPABLE_MASK | 0x1U));
+
+    /* Start Auto negotiation and wait until auto negotiation completion */
+    PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
+    delay = PHY_TIMEOUT_COUNT;
+    do
+    {
+        PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, &reg);
+        delay --;
+    } while (delay && ((reg & PHY_SPECIALCTL_AUTONEGDONE_MASK) == 0));
+
+    if (!delay)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Waiting a moment for phy stable. */
+    for (delay = 0; delay < PHY_TIMEOUT_COUNT; delay++)
+    {
+        __ASM("nop");
+        PHY_GetLinkStatus(base, phyAddr, &status);
+        if (status)
+        {
+            break;
+        }
+    }
+
+    return kStatus_Success;
+}
+
+status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
+{
+#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
+    uint32_t counter;
+
+    /* Clear the SMI interrupt event. */
+    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+    /* Starts a SMI write command. */
+    ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
+
+    /* Wait for SMI complete. */
+    for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
+    {
+        if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
+        {
+            break;
+        }
+    }
+
+    /* Check for timeout. */
+    if (!counter)
+    {
+        return kStatus_PHY_SMIVisitTimeout;
+    }
+
+    /* Clear MII interrupt event. */
+    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
+    ENET_StartSMIWrite(base, phyAddr, phyReg, data);
+    while (ENET_IsSMIBusy(base))
+        ;
+#endif
+    return kStatus_Success;
+}
+
+status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
+{
+#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
+     assert(dataPtr);
+
+    uint32_t counter;
+
+    /* Clear the MII interrupt event. */
+    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+    /* Starts a SMI read command operation. */
+    ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
+
+    /* Wait for MII complete. */
+    for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
+    {
+        if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
+        {
+            break;
+        }
+    }
+
+    /* Check for timeout. */
+    if (!counter)
+    {
+        return kStatus_PHY_SMIVisitTimeout;
+    }
+
+    /* Get data from MII register. */
+    *dataPtr = ENET_ReadSMIData(base);
+
+    /* Clear MII interrupt event. */
+    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
+    ENET_StartSMIRead(base, phyAddr, phyReg);
+    while (ENET_IsSMIBusy(base))
+        ;
+    *dataPtr = ENET_ReadSMIData(base);
+#endif
+     return kStatus_Success;
+}
+
+status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
+{
+    uint32_t reg;
+    status_t result = kStatus_Success;
+
+    /* Read the basic status register. */
+    result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &reg);
+    if (result == kStatus_Success)
+    {
+        if (reg & PHY_BSTATUS_LINKSTATUS_MASK)
+        {
+            /* link up. */
+            *status = true;
+        }
+        else
+        {
+            *status = false;
+        }        
+    }
+    return result;
+}
+
+status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
+{
+    assert(duplex);
+    assert(speed);
+
+    uint32_t reg;
+    status_t result = kStatus_Success;
+
+    /* Read the control two register. */
+    result = PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, &reg);
+    if (result == kStatus_Success)
+    {
+        if (reg & PHY_SPECIALCTL_DUPLEX_MASK)
+        {
+            /* Full duplex. */
+            *duplex = kPHY_FullDuplex;
+        }
+        else
+        {
+            /* Half duplex. */
+            *duplex = kPHY_HalfDuplex;
+        }
+
+        if (reg & PHY_SPECIALCTL_100SPEED_MASK)
+        {
+            /* 100M speed. */
+            *speed = kPHY_Speed100M;
+        }
+        else
+        { /* 10M speed. */
+            *speed = kPHY_Speed10M;
+        }        
+    }
+    return result;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_PHY_H_
+#define _FSL_PHY_H_
+
+#include "fsl_enet.h"
+
+/*!
+ * @addtogroup phy_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief PHY driver version */
+#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+
+/*! @brief Defines the PHY registers. */
+#define PHY_BASICCONTROL_REG 0x00U      /*!< The PHY basic control register. */
+#define PHY_BASICSTATUS_REG 0x01U       /*!< The PHY basic status register. */
+#define PHY_ID1_REG 0x02U               /*!< The PHY ID one register. */
+#define PHY_ID2_REG 0x03U               /*!< The PHY ID two register. */
+#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
+#define PHY_SEPCIAL_CONTROL_REG 0x1FU   /*!< The PHY control two register. */
+
+#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/
+
+/*! @brief Defines the mask flag in basic control register. */
+#define PHY_BCTL_DUPLEX_MASK 0x0100U          /*!< The PHY duplex bit mask. */
+#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
+#define PHY_BCTL_AUTONEG_MASK 0x1000U         /*!< The PHY auto negotiation bit mask. */
+#define PHY_BCTL_SPEED_MASK 0x2000U           /*!< The PHY speed bit mask. */
+#define PHY_BCTL_LOOP_MASK 0x4000U            /*!< The PHY loop bit mask. */
+#define PHY_BCTL_RESET_MASK 0x8000U           /*!< The PHY reset bit mask. */
+
+/*!@brief Defines the mask flag of operation mode in special control register*/
+#define PHY_SPECIALCTL_AUTONEGDONE_MASK 0x1000U /*!< The PHY auto-negotiation complete mask. */
+#define PHY_SPECIALCTL_DUPLEX_MASK 0x0010U      /*!< The PHY duplex mask. */
+#define PHY_SPECIALCTL_100SPEED_MASK 0x0008U    /*!< The PHY speed mask. */
+#define PHY_SPECIALCTL_10SPEED_MASK 0x0004U     /*!< The PHY speed mask. */
+#define PHY_SPECIALCTL_SPEEDUPLX_MASK 0x001cU   /*!< The PHY speed and duplex mask. */
+
+/*! @brief Defines the mask flag in basic status register. */
+#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
+
+/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
+#define PHY_ALL_CAPABLE_MASK 0x1e0U
+
+/*! @brief Defines the PHY status. */
+enum _phy_status
+{
+    kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 0),  /*!< ENET PHY SMI visit timeout. */
+};
+
+/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
+typedef enum _phy_speed {
+    kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
+    kPHY_Speed100M      /*!< ENET PHY 100M speed. */
+} phy_speed_t;
+
+/*! @brief Defines the PHY link duplex. */
+typedef enum _phy_duplex {
+    kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
+    kPHY_FullDuplex       /*!< ENET PHY full duplex. */
+} phy_duplex_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+  * @name PHY Driver
+  * @{
+  */
+
+/*!
+ * @brief Initializes PHY.
+ *
+ *  This function initialize the SMI interface and initialize PHY.
+ *  The SMI is the MII management interface between PHY and MAC, which should be
+ *  firstly initialized before any other operation for PHY.
+ *
+ * @param base       ENET peripheral base address.
+ * @param phyAddr    The PHY address.
+ * @param srcClock_Hz  The module clock frequency - system clock for MII management interface - SMI.
+ * @retval kStatus_Success  PHY initialize success
+ * @retval kStatus_Fail  PHY initialize fail
+ */
+status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
+
+/*!
+ * @brief PHY Write function. This function write data over the SMI to
+ * the specified PHY register. This function is called by all PHY interfaces.
+ *
+ * @param base    ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg  The PHY register.
+ * @param data    The data written to the PHY register.
+ * @retval kStatus_Success     PHY write success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
+
+/*!
+ * @brief PHY Read function. This interface read data over the SMI from the
+ * specified PHY register. This function is called by all PHY interfaces.
+ *
+ * @param base     ENET peripheral base address.
+ * @param phyAddr  The PHY address.
+ * @param phyReg   The PHY register.
+ * @param dataPtr  The address to store the data read from the PHY register.
+ * @retval kStatus_Success  PHY read success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
+
+/*!
+ * @brief Gets the PHY link status.
+ *
+ * @param base     ENET peripheral base address.
+ * @param phyAddr  The PHY address.
+ * @param status   The link up or down status of the PHY.
+ *         - true the link is up.
+ *         - false the link is down.
+ * @retval kStatus_Success   PHY get link status success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
+
+/*!
+ * @brief Gets the PHY link speed and duplex.
+ *
+ * @param base     ENET peripheral base address.
+ * @param phyAddr  The PHY address.
+ * @param speed    The address of PHY link speed.
+ * @param duplex   The link duplex of PHY.
+ * @retval kStatus_Success   PHY get link speed and duplex success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_PHY_H_ */

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -340,6 +340,7 @@
             }
             InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
             GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
+            GIC_SetConfiguration(can_int_info[obj->ch][type].int_num, 1);
             GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
         } else {
             GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h	Wed Jan 17 15:23:54 2018 +0000
@@ -1,1059 +1,1 @@
-/*******************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only
-* intended for use with Renesas products. No other uses are authorized. This
-* software is owned by Renesas Electronics Corporation and is protected under
-* all applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
-* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
-* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
-* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
-* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
-* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
-* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
-* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
-* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software
-* and to discontinue the availability of this software. By using this software,
-* you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
-*******************************************************************************/
-/**************************************************************************//**
- * @file     MBRZA1H.h
- * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File for 
- *           Renesas MBRZA1H Device Series
- * @version
- * @date     19 Sept 2013
- *
- * @note
- *
- ******************************************************************************/
-
-#ifndef __MBRZA1H_H__
-#define __MBRZA1H_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* -------------------------  Interrupt Number Definition  ------------------------ */
-
-typedef enum IRQn
-{
-/******  SGI Interrupts Numbers                 ****************************************/
-  SGI0_IRQn           =  0,
-  SGI1_IRQn           =  1,
-  SGI2_IRQn           =  2,
-  SGI3_IRQn           =  3,
-  SGI4_IRQn           =  4,
-  SGI5_IRQn           =  5,
-  SGI6_IRQn           =  6,
-  SGI7_IRQn           =  7,
-  SGI8_IRQn           =  8,
-  SGI9_IRQn           =  9,
-  SGI10_IRQn          = 10,
-  SGI11_IRQn          = 11,
-  SGI12_IRQn          = 12,
-  SGI13_IRQn          = 13,
-  SGI14_IRQn          = 14,
-  SGI15_IRQn          = 15,
-
-/******  Cortex-A9 Processor Exceptions Numbers ****************************************/
-  /* 16 - 578 */
-  PMUIRQ0_IRQn         = 16,
-  COMMRX0_IRQn         = 17,
-  COMMTX0_IRQn         = 18,
-  CTIIRQ0_IRQn         = 19,
-
-  IRQ0_IRQn            = 32,
-  IRQ1_IRQn            = 33,
-  IRQ2_IRQn            = 34,
-  IRQ3_IRQn            = 35,
-  IRQ4_IRQn            = 36,
-  IRQ5_IRQn            = 37,
-  IRQ6_IRQn            = 38,
-  IRQ7_IRQn            = 39,
-
-  PL310ERR_IRQn        = 40,
-
-  DMAINT0_IRQn         = 41,        /*!< DMAC Interrupt         */
-  DMAINT1_IRQn         = 42,        /*!< DMAC Interrupt         */
-  DMAINT2_IRQn         = 43,        /*!< DMAC Interrupt         */
-  DMAINT3_IRQn         = 44,        /*!< DMAC Interrupt         */
-  DMAINT4_IRQn         = 45,        /*!< DMAC Interrupt         */
-  DMAINT5_IRQn         = 46,        /*!< DMAC Interrupt         */
-  DMAINT6_IRQn         = 47,        /*!< DMAC Interrupt         */
-  DMAINT7_IRQn         = 48,        /*!< DMAC Interrupt         */
-  DMAINT8_IRQn         = 49,        /*!< DMAC Interrupt         */
-  DMAINT9_IRQn         = 50,        /*!< DMAC Interrupt         */
-  DMAINT10_IRQn        = 51,        /*!< DMAC Interrupt         */
-  DMAINT11_IRQn        = 52,        /*!< DMAC Interrupt         */
-  DMAINT12_IRQn        = 53,        /*!< DMAC Interrupt         */
-  DMAINT13_IRQn        = 54,        /*!< DMAC Interrupt         */
-  DMAINT14_IRQn        = 55,        /*!< DMAC Interrupt         */
-  DMAINT15_IRQn        = 56,        /*!< DMAC Interrupt         */
-  DMAERR_IRQn          = 57,        /*!< DMAC Interrupt         */
-
-  /* 58-72 Reserved */
-
-  USBI0_IRQn           = 73,
-  USBI1_IRQn           = 74,
-
-  S0_VI_VSYNC0_IRQn    = 75,
-  S0_LO_VSYNC0_IRQn    = 76,
-  S0_VSYNCERR0_IRQn    = 77,
-  GR3_VLINE0_IRQn      = 78,
-  S0_VFIELD0_IRQn      = 79,
-  IV1_VBUFERR0_IRQn    = 80,
-  IV3_VBUFERR0_IRQn    = 81,
-  IV5_VBUFERR0_IRQn    = 82,
-  IV6_VBUFERR0_IRQn    = 83,
-  S0_WLINE0_IRQn       = 84,
-  S1_VI_VSYNC0_IRQn    = 85,
-  S1_LO_VSYNC0_IRQn    = 86,
-  S1_VSYNCERR0_IRQn    = 87,
-  S1_VFIELD0_IRQn      = 88,
-  IV2_VBUFERR0_IRQn    = 89,
-  IV4_VBUFERR0_IRQn    = 90,
-  S1_WLINE0_IRQn       = 91,
-  OIR_VI_VSYNC0_IRQn   = 92,
-  OIR_LO_VSYNC0_IRQn   = 93,
-  OIR_VSYNCERR0_IRQn   = 94,
-  OIR_VFIELD0_IRQn     = 95,
-  IV7_VBUFERR0_IRQn    = 96,
-  IV8_VBUFERR0_IRQn    = 97,
-  /* 98 Reserved */
-  S0_VI_VSYNC1_IRQn    = 99,
-  S0_LO_VSYNC1_IRQn    = 100,
-  S0_VSYNCERR1_IRQn    = 101,
-  GR3_VLINE1_IRQn      = 102,
-  S0_VFIELD1_IRQn      = 103,
-  IV1_VBUFERR1_IRQn    = 104,
-  IV3_VBUFERR1_IRQn    = 105,
-  IV5_VBUFERR1_IRQn    = 106,
-  IV6_VBUFERR1_IRQn    = 107,
-  S0_WLINE1_IRQn       = 108,
-  S1_VI_VSYNC1_IRQn    = 109,
-  S1_LO_VSYNC1_IRQn    = 110,
-  S1_VSYNCERR1_IRQn    = 111,
-  S1_VFIELD1_IRQn      = 112,
-  IV2_VBUFERR1_IRQn    = 113,
-  IV4_VBUFERR1_IRQn    = 114,
-  S1_WLINE1_IRQn       = 115,
-  OIR_VI_VSYNC1_IRQn   = 116,
-  OIR_LO_VSYNC1_IRQn   = 117,
-  OIR_VSYNCERR1_IRQn   = 118,
-  OIR_VFIELD1_IRQn     = 119,
-  IV7_VBUFERR1_IRQn    = 120,
-  IV8_VBUFERR1_IRQn    = 121,
-  /* Reserved = 122 */
-
-  IMRDI_IRQn           = 123,
-  IMR2I0_IRQn          = 124,
-  IMR2I1_IRQn          = 125,
-
-  JEDI_IRQn            = 126,
-  JDTI_IRQn            = 127,
-
-  CMP0_IRQn            = 128,
-  CMP1_IRQn            = 129,
-
-  INT0_IRQn            = 130,
-  INT1_IRQn            = 131,
-  INT2_IRQn            = 132,
-  INT3_IRQn            = 133,
-
-  OSTMI0TINT_IRQn      = 134,       /*!< OSTM Interrupt         */
-  OSTMI1TINT_IRQn      = 135,       /*!< OSTM Interrupt         */
-
-  CMI_IRQn             = 136,
-  WTOUT_IRQn           = 137,
-
-  ITI_IRQn             = 138,
-
-  TGI0A_IRQn           = 139,
-  TGI0B_IRQn           = 140,
-  TGI0C_IRQn           = 141,
-  TGI0D_IRQn           = 142,
-  TGI0V_IRQn           = 143,
-  TGI0E_IRQn           = 144,
-  TGI0F_IRQn           = 145,
-  TGI1A_IRQn           = 146,
-  TGI1B_IRQn           = 147,
-  TGI1V_IRQn           = 148,
-  TGI1U_IRQn           = 149,
-  TGI2A_IRQn           = 150,
-  TGI2B_IRQn           = 151,
-  TGI2V_IRQn           = 152,
-  TGI2U_IRQn           = 153,
-  TGI3A_IRQn           = 154,
-  TGI3B_IRQn           = 155,
-  TGI3C_IRQn           = 156,
-  TGI3D_IRQn           = 157,
-  TGI3V_IRQn           = 158,
-  TGI4A_IRQn           = 159,
-  TGI4B_IRQn           = 160,
-  TGI4C_IRQn           = 161,
-  TGI4D_IRQn           = 162,
-  TGI4V_IRQn           = 163,
-
-  CMI1_IRQn            = 164,
-  CMI2_IRQn            = 165,
-
-  SGDEI0_IRQn          = 166,
-  SGDEI1_IRQn          = 167,
-  SGDEI2_IRQn          = 168,
-  SGDEI3_IRQn          = 169,
-
-  ADI_IRQn             = 170,
-  LMTI_IRQn            = 171,
-
-  SSII0_IRQn           = 172,       /*!< SSIF Interrupt         */
-  SSIRXI0_IRQn         = 173,       /*!< SSIF Interrupt         */
-  SSITXI0_IRQn         = 174,       /*!< SSIF Interrupt         */
-  SSII1_IRQn           = 175,       /*!< SSIF Interrupt         */
-  SSIRXI1_IRQn         = 176,       /*!< SSIF Interrupt         */
-  SSITXI1_IRQn         = 177,       /*!< SSIF Interrupt         */
-  SSII2_IRQn           = 178,       /*!< SSIF Interrupt         */
-  SSIRTI2_IRQn         = 179,       /*!< SSIF Interrupt         */
-  SSII3_IRQn           = 180,       /*!< SSIF Interrupt         */
-  SSIRXI3_IRQn         = 181,       /*!< SSIF Interrupt         */
-  SSITXI3_IRQn         = 182,       /*!< SSIF Interrupt         */
-  SSII4_IRQn           = 183,       /*!< SSIF Interrupt         */
-  SSIRTI4_IRQn         = 184,       /*!< SSIF Interrupt         */
-  SSII5_IRQn           = 185,       /*!< SSIF Interrupt         */
-  SSIRXI5_IRQn         = 186,       /*!< SSIF Interrupt         */
-  SSITXI5_IRQn         = 187,       /*!< SSIF Interrupt         */
-
-  SPDIFI_IRQn          = 188,
-
-  INTIICTEI0_IRQn      = 189,       /*!< RIIC Interrupt         */
-  INTIICRI0_IRQn       = 190,       /*!< RIIC Interrupt         */
-  INTIICTI0_IRQn       = 191,       /*!< RIIC Interrupt         */
-  INTIICSPI0_IRQn      = 192,       /*!< RIIC Interrupt         */
-  INTIICSTI0_IRQn      = 193,       /*!< RIIC Interrupt         */
-  INTIICNAKI0_IRQn     = 194,       /*!< RIIC Interrupt         */
-  INTIICALI0_IRQn      = 195,       /*!< RIIC Interrupt         */
-  INTIICTMOI0_IRQn     = 196,       /*!< RIIC Interrupt         */
-  INTIICTEI1_IRQn      = 197,       /*!< RIIC Interrupt         */
-  INTIICRI1_IRQn       = 198,       /*!< RIIC Interrupt         */
-  INTIICTI1_IRQn       = 199,       /*!< RIIC Interrupt         */
-  INTIICSPI1_IRQn      = 200,       /*!< RIIC Interrupt         */
-  INTIICSTI1_IRQn      = 201,       /*!< RIIC Interrupt         */
-  INTIICNAKI1_IRQn     = 202,       /*!< RIIC Interrupt         */
-  INTIICALI1_IRQn      = 203,       /*!< RIIC Interrupt         */
-  INTIICTMOI1_IRQn     = 204,       /*!< RIIC Interrupt         */
-  INTIICTEI2_IRQn      = 205,       /*!< RIIC Interrupt         */
-  INTIICRI2_IRQn       = 206,       /*!< RIIC Interrupt         */
-  INTIICTI2_IRQn       = 207,       /*!< RIIC Interrupt         */
-  INTIICSPI2_IRQn      = 208,       /*!< RIIC Interrupt         */
-  INTIICSTI2_IRQn      = 209,       /*!< RIIC Interrupt         */
-  INTIICNAKI2_IRQn     = 210,       /*!< RIIC Interrupt         */
-  INTIICALI2_IRQn      = 211,       /*!< RIIC Interrupt         */
-  INTIICTMOI2_IRQn     = 212,       /*!< RIIC Interrupt         */
-  INTIICTEI3_IRQn      = 213,       /*!< RIIC Interrupt         */
-  INTIICRI3_IRQn       = 214,       /*!< RIIC Interrupt         */
-  INTIICTI3_IRQn       = 215,       /*!< RIIC Interrupt         */
-  INTIICSPI3_IRQn      = 216,       /*!< RIIC Interrupt         */
-  INTIICSTI3_IRQn      = 217,       /*!< RIIC Interrupt         */
-  INTIICNAKI3_IRQn     = 218,       /*!< RIIC Interrupt         */
-  INTIICALI3_IRQn      = 219,       /*!< RIIC Interrupt         */
-  INTIICTMOI3_IRQn     = 220,       /*!< RIIC Interrupt         */
-
-  SCIFBRI0_IRQn        = 221,       /*!< SCIF Interrupt         */
-  SCIFERI0_IRQn        = 222,       /*!< SCIF Interrupt         */
-  SCIFRXI0_IRQn        = 223,       /*!< SCIF Interrupt         */
-  SCIFTXI0_IRQn        = 224,       /*!< SCIF Interrupt         */
-  SCIFBRI1_IRQn        = 225,       /*!< SCIF Interrupt         */
-  SCIFERI1_IRQn        = 226,       /*!< SCIF Interrupt         */
-  SCIFRXI1_IRQn        = 227,       /*!< SCIF Interrupt         */
-  SCIFTXI1_IRQn        = 228,       /*!< SCIF Interrupt         */
-  SCIFBRI2_IRQn        = 229,       /*!< SCIF Interrupt         */
-  SCIFERI2_IRQn        = 230,       /*!< SCIF Interrupt         */
-  SCIFRXI2_IRQn        = 231,       /*!< SCIF Interrupt         */
-  SCIFTXI2_IRQn        = 232,       /*!< SCIF Interrupt         */
-  SCIFBRI3_IRQn        = 233,       /*!< SCIF Interrupt         */
-  SCIFERI3_IRQn        = 234,       /*!< SCIF Interrupt         */
-  SCIFRXI3_IRQn        = 235,       /*!< SCIF Interrupt         */
-  SCIFTXI3_IRQn        = 236,       /*!< SCIF Interrupt         */
-  SCIFBRI4_IRQn        = 237,       /*!< SCIF Interrupt         */
-  SCIFERI4_IRQn        = 238,       /*!< SCIF Interrupt         */
-  SCIFRXI4_IRQn        = 239,       /*!< SCIF Interrupt         */
-  SCIFTXI4_IRQn        = 240,       /*!< SCIF Interrupt         */
-  SCIFBRI5_IRQn        = 241,       /*!< SCIF Interrupt         */
-  SCIFERI5_IRQn        = 242,       /*!< SCIF Interrupt         */
-  SCIFRXI5_IRQn        = 243,       /*!< SCIF Interrupt         */
-  SCIFTXI5_IRQn        = 244,       /*!< SCIF Interrupt         */
-  SCIFBRI6_IRQn        = 245,       /*!< SCIF Interrupt         */
-  SCIFERI6_IRQn        = 246,       /*!< SCIF Interrupt         */
-  SCIFRXI6_IRQn        = 247,       /*!< SCIF Interrupt         */
-  SCIFTXI6_IRQn        = 248,       /*!< SCIF Interrupt         */
-  SCIFBRI7_IRQn        = 249,       /*!< SCIF Interrupt         */
-  SCIFERI7_IRQn        = 250,       /*!< SCIF Interrupt         */
-  SCIFRXI7_IRQn        = 251,       /*!< SCIF Interrupt         */
-  SCIFTXI7_IRQn        = 252,       /*!< SCIF Interrupt         */
-
-  INTRCANGERR_IRQn     = 253,
-  INTRCANGRECC_IRQn    = 254,
-  INTRCAN0REC_IRQn     = 255,
-  INTRCAN0ERR_IRQn     = 256,
-  INTRCAN0TRX_IRQn     = 257,
-  INTRCAN1REC_IRQn     = 258,
-  INTRCAN1ERR_IRQn     = 259,
-  INTRCAN1TRX_IRQn     = 260,
-  INTRCAN2REC_IRQn     = 261,
-  INTRCAN2ERR_IRQn     = 262,
-  INTRCAN2TRX_IRQn     = 263,
-  INTRCAN3REC_IRQn     = 264,
-  INTRCAN3ERR_IRQn     = 265,
-  INTRCAN3TRX_IRQn     = 266,
-  INTRCAN4REC_IRQn     = 267,
-  INTRCAN4ERR_IRQn     = 268,
-  INTRCAN4TRX_IRQn     = 269,
-
-  RSPISPEI0_IRQn       = 270,       /*!< RSPI Interrupt         */
-  RSPISPRI0_IRQn       = 271,       /*!< RSPI Interrupt         */
-  RSPISPTI0_IRQn       = 272,       /*!< RSPI Interrupt         */
-  RSPISPEI1_IRQn       = 273,       /*!< RSPI Interrupt         */
-  RSPISPRI1_IRQn       = 274,       /*!< RSPI Interrupt         */
-  RSPISPTI1_IRQn       = 275,       /*!< RSPI Interrupt         */
-  RSPISPEI2_IRQn       = 276,       /*!< RSPI Interrupt         */
-  RSPISPRI2_IRQn       = 277,       /*!< RSPI Interrupt         */
-  RSPISPTI2_IRQn       = 278,       /*!< RSPI Interrupt         */
-  RSPISPEI3_IRQn       = 279,       /*!< RSPI Interrupt         */
-  RSPISPRI3_IRQn       = 280,       /*!< RSPI Interrupt         */
-  RSPISPTI3_IRQn       = 281,       /*!< RSPI Interrupt         */
-  RSPISPEI4_IRQn       = 282,       /*!< RSPI Interrupt         */
-  RSPISPRI4_IRQn       = 283,       /*!< RSPI Interrupt         */
-  RSPISPTI4_IRQn       = 284,       /*!< RSPI Interrupt         */
-
-  IEBBTD_IRQn          = 285,
-  IEBBTERR_IRQn        = 286,
-  IEBBTSTA_IRQn        = 287,
-  IEBBTV_IRQn          = 288,
-
-  ISY_IRQn             = 289,
-  IERR_IRQn            = 290,
-  ITARG_IRQn           = 291,
-  ISEC_IRQn            = 292,
-  IBUF_IRQn            = 293,
-  IREADY_IRQn          = 294,
-
-  STERB_IRQn           = 295,
-  FLTENDI_IRQn         = 296,
-  FLTREQ0I_IRQn        = 297,
-  FLTREQ1I_IRQn        = 298,
-
-  MMC0_IRQn            = 299,
-  MMC1_IRQn            = 300,
-  MMC2_IRQn            = 301,
-
-  SCHI0_3_IRQn         = 302,
-  SDHI0_0_IRQn         = 303,
-  SDHI0_1_IRQn         = 304,
-  SCHI1_3_IRQn         = 305,
-  SDHI1_0_IRQn         = 306,
-  SDHI1_1_IRQn         = 307,
-
-  ARM_IRQn             = 308,
-  PRD_IRQn             = 309,
-  CUP_IRQn             = 310,
-
-  SCUAI0_IRQn          = 311,
-  SCUAI1_IRQn          = 312,
-  SCUFDI0_IRQn         = 313,
-  SCUFDI1_IRQn         = 314,
-  SCUFDI2_IRQn         = 315,
-  SCUFDI3_IRQn         = 316,
-  SCUFUI0_IRQn         = 317,
-  SCUFUI1_IRQn         = 318,
-  SCUFUI2_IRQn         = 319,
-  SCUFUI3_IRQn         = 320,
-  SCUDVI0_IRQn         = 321,
-  SCUDVI1_IRQn         = 322,
-  SCUDVI2_IRQn         = 323,
-  SCUDVI3_IRQn         = 324,
-
-  MLB_CINT_IRQn        = 325,
-  MLB_SINT_IRQn        = 326,
-
-  DRC10_IRQn           = 327,
-  DRC11_IRQn           = 328,
-
-  /* 329-330 Reserved  */
-
-  LINI0_INT_T_IRQn     = 331,
-  LINI0_INT_R_IRQn     = 332,
-  LINI0_INT_S_IRQn     = 333,
-  LINI0_INT_M_IRQn     = 334,
-  LINI1_INT_T_IRQn     = 335,
-  LINI1_INT_R_IRQn     = 336,
-  LINI1_INT_S_IRQn     = 337,
-  LINI1_INT_M_IRQn     = 338,
-
-  /* 339-346 Reserved */
-
-  SCIERI0_IRQn         = 347,
-  SCIRXI0_IRQn         = 348,
-  SCITXI0_IRQn         = 349,
-  SCITEI0_IRQn         = 350,
-  SCIERI1_IRQn         = 351,
-  SCIRXI1_IRQn         = 352,
-  SCITXI1_IRQn         = 353,
-  SCITEI1_IRQn         = 354,
-
-  AVBI_DATA            = 355,
-  AVBI_ERROR           = 356,
-  AVBI_MANAGE          = 357,
-  AVBI_MAC             = 358,
-
-  ETHERI_IRQn          = 359,
-
-  /* 360-363 Reserved */
-
-  CEUI_IRQn            = 364,
-
-  /* 365-380 Reserved */
-
-
-  H2XMLB_ERRINT_IRQn   = 381,
-  H2XIC1_ERRINT_IRQn   = 382,
-  X2HPERI1_ERRINT_IRQn = 383,
-  X2HPERR2_ERRINT_IRQn = 384,
-  X2HPERR34_ERRINT_IRQn= 385,
-  X2HPERR5_ERRINT_IRQn = 386,
-  X2HPERR67_ERRINT_IRQn= 387,
-  X2HDBGR_ERRINT_IRQn  = 388,
-  X2HBSC_ERRINT_IRQn   = 389,   
-  X2HSPI1_ERRINT_IRQn  = 390,   
-  X2HSPI2_ERRINT_IRQn  = 391,   
-  PRRI_IRQn            = 392,
-
-  IFEI0_IRQn           = 393,
-  OFFI0_IRQn           = 394,
-  PFVEI0_IRQn          = 395,
-  IFEI1_IRQn           = 396,
-  OFFI1_IRQn           = 397,
-  PFVEI1_IRQn          = 398,
-
-  /* 399-415 Reserved */
-  TINT0_IRQn           = 416,
-  TINT1_IRQn           = 417,
-  TINT2_IRQn           = 418,
-  TINT3_IRQn           = 419,
-  TINT4_IRQn           = 420,
-  TINT5_IRQn           = 421,
-  TINT6_IRQn           = 422,
-  TINT7_IRQn           = 423,
-  TINT8_IRQn           = 424,
-  TINT9_IRQn           = 425,
-  TINT10_IRQn          = 426,
-  TINT11_IRQn          = 427,
-  TINT12_IRQn          = 428,
-  TINT13_IRQn          = 429,
-  TINT14_IRQn          = 430,
-  TINT15_IRQn          = 431,
-  TINT16_IRQn          = 432,
-  TINT17_IRQn          = 433,
-  TINT18_IRQn          = 434,
-  TINT19_IRQn          = 435,
-  TINT20_IRQn          = 436,
-  TINT21_IRQn          = 437,
-  TINT22_IRQn          = 438,
-  TINT23_IRQn          = 439,
-  TINT24_IRQn          = 440,
-  TINT25_IRQn          = 441,
-  TINT26_IRQn          = 442,
-  TINT27_IRQn          = 443,
-  TINT28_IRQn          = 444,
-  TINT29_IRQn          = 445,
-  TINT30_IRQn          = 446,
-  TINT31_IRQn          = 447,
-  TINT32_IRQn          = 448,
-  TINT33_IRQn          = 449,
-  TINT34_IRQn          = 450,
-  TINT35_IRQn          = 451,
-  TINT36_IRQn          = 452,
-  TINT37_IRQn          = 453,
-  TINT38_IRQn          = 454,
-  TINT39_IRQn          = 455,
-  TINT40_IRQn          = 456,
-  TINT41_IRQn          = 457,
-  TINT42_IRQn          = 458,
-  TINT43_IRQn          = 459,
-  TINT44_IRQn          = 460,
-  TINT45_IRQn          = 461,
-  TINT46_IRQn          = 462,
-  TINT47_IRQn          = 463,
-  TINT48_IRQn          = 464,
-  TINT49_IRQn          = 465,
-  TINT50_IRQn          = 466,
-  TINT51_IRQn          = 467,
-  TINT52_IRQn          = 468,
-  TINT53_IRQn          = 469,
-  TINT54_IRQn          = 470,
-  TINT55_IRQn          = 471,
-  TINT56_IRQn          = 472,
-  TINT57_IRQn          = 473,
-  TINT58_IRQn          = 474,
-  TINT59_IRQn          = 475,
-  TINT60_IRQn          = 476,
-  TINT61_IRQn          = 477,
-  TINT62_IRQn          = 478,
-  TINT63_IRQn          = 479,
-  TINT64_IRQn          = 480,
-  TINT65_IRQn          = 481,
-  TINT66_IRQn          = 482,
-  TINT67_IRQn          = 483,
-  TINT68_IRQn          = 484,
-  TINT69_IRQn          = 485,
-  TINT70_IRQn          = 486,
-  TINT71_IRQn          = 487,
-  TINT72_IRQn          = 488,
-  TINT73_IRQn          = 489,
-  TINT74_IRQn          = 490,
-  TINT75_IRQn          = 491,
-  TINT76_IRQn          = 492,
-  TINT77_IRQn          = 493,
-  TINT78_IRQn          = 494,
-  TINT79_IRQn          = 495,
-  TINT80_IRQn          = 496,
-  TINT81_IRQn          = 497,
-  TINT82_IRQn          = 498,
-  TINT83_IRQn          = 499,
-  TINT84_IRQn          = 500,
-  TINT85_IRQn          = 501,
-  TINT86_IRQn          = 502,
-  TINT87_IRQn          = 503,
-  TINT88_IRQn          = 504,
-  TINT89_IRQn          = 505,
-  TINT90_IRQn          = 506,
-  TINT91_IRQn          = 507,
-  TINT92_IRQn          = 508,
-  TINT93_IRQn          = 509,
-  TINT94_IRQn          = 510,
-  TINT95_IRQn          = 511,
-  TINT96_IRQn          = 512,
-  TINT97_IRQn          = 513,
-  TINT98_IRQn          = 514,
-  TINT99_IRQn          = 515,
-  TINT100_IRQn         = 516,
-  TINT101_IRQn         = 517,
-  TINT102_IRQn         = 518,
-  TINT103_IRQn         = 519,
-  TINT104_IRQn         = 520,
-  TINT105_IRQn         = 521,
-  TINT106_IRQn         = 522,
-  TINT107_IRQn         = 523,
-  TINT108_IRQn         = 524,
-  TINT109_IRQn         = 525,
-  TINT110_IRQn         = 526,
-  TINT111_IRQn         = 527,
-  TINT112_IRQn         = 528,
-  TINT113_IRQn         = 529,
-  TINT114_IRQn         = 530,
-  TINT115_IRQn         = 531,
-  TINT116_IRQn         = 532,
-  TINT117_IRQn         = 533,
-  TINT118_IRQn         = 534,
-  TINT119_IRQn         = 535,
-  TINT120_IRQn         = 536,
-  TINT121_IRQn         = 537,
-  TINT122_IRQn         = 538,
-  TINT123_IRQn         = 539,
-  TINT124_IRQn         = 540,
-  TINT125_IRQn         = 541,
-  TINT126_IRQn         = 542,
-  TINT127_IRQn         = 543,
-  TINT128_IRQn         = 544,
-  TINT129_IRQn         = 545,
-  TINT130_IRQn         = 546,
-  TINT131_IRQn         = 547,
-  TINT132_IRQn         = 548,
-  TINT133_IRQn         = 549,
-  TINT134_IRQn         = 550,
-  TINT135_IRQn         = 551,
-  TINT136_IRQn         = 552,
-  TINT137_IRQn         = 553,
-  TINT138_IRQn         = 554,
-  TINT139_IRQn         = 555,
-  TINT140_IRQn         = 556,
-  TINT141_IRQn         = 557,
-  TINT142_IRQn         = 558,
-  TINT143_IRQn         = 559,
-  TINT144_IRQn         = 560,
-  TINT145_IRQn         = 561,
-  TINT146_IRQn         = 562,
-  TINT147_IRQn         = 563,
-  TINT148_IRQn         = 564,
-  TINT149_IRQn         = 565,
-  TINT150_IRQn         = 566,
-  TINT151_IRQn         = 567,
-  TINT152_IRQn         = 568,
-  TINT153_IRQn         = 569,
-  TINT154_IRQn         = 570,
-  TINT155_IRQn         = 571,
-  TINT156_IRQn         = 572,
-  TINT157_IRQn         = 573,
-  TINT158_IRQn         = 574,
-  TINT159_IRQn         = 575,
-  TINT160_IRQn         = 576,
-  TINT161_IRQn         = 577,
-  TINT162_IRQn         = 578,
-  TINT163_IRQn         = 579,
-  TINT164_IRQn         = 580,
-  TINT165_IRQn         = 581,
-  TINT166_IRQn         = 582,
-  TINT167_IRQn         = 583,
-  TINT168_IRQn         = 584,
-  TINT169_IRQn         = 585,
-  TINT170_IRQn         = 586
-
-} IRQn_Type;
-
-#define Renesas_RZ_A1_IRQ_MAX  TINT170_IRQn
-
-/* --------  Configuration of the Cortex-A9 Processor and Core Peripherals  ------- */
-#define __CA9_REV                 0x0000    /*!< Core revision r0                                */
-
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-
-#define __FPU_PRESENT             1         /*!< FPU present or not                               */
-
-#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-#include <core_ca9.h>
-#include "system_MBRZA1H.h"
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral Section                          */
-/******************************************************************************/
-/** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
-  Renesas_RZ_A1 Device Specific Peripheral registers structures
-  @{
-*/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-#include "pl310.h"
-#include "gic.h"
-#include "nvic_wrapper.h"
-#include "cmsis_nvic.h"
-
-#include "ostm_iodefine.h"
-#include "gpio_iodefine.h"
-#include "cpg_iodefine.h"
-#include "l2c_iodefine.h"
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-/*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
-
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
-  @{
-*/
-
-/* R7S72100 CPU board  */
-#define Renesas_RZ_A1_NORFLASH_BASE0               (0x00000000UL)                        /*!< (FLASH0    ) Base Address */
-#define Renesas_RZ_A1_NORFLASH_BASE1               (0x04000000UL)                        /*!< (FLASH1    ) Base Address */
-#define Renesas_RZ_A1_SDRAM_BASE0                  (0x08000000UL)                        /*!< (SDRAM0    ) Base Address */
-#define Renesas_RZ_A1_SDRAM_BASE1                  (0x0C000000UL)                        /*!< (SDRAM1    ) Base Address */
-#define Renesas_RZ_A1_USER_AREA0                   (0x10000000UL)                        /*!< (USER0     ) Base Address */
-#define Renesas_RZ_A1_USER_AREA1                   (0x14000000UL)                        /*!< (USER1     ) Base Address */
-#define Renesas_RZ_A1_SPI_IO0                      (0x18000000UL)                        /*!< (SPI_IO0   ) Base Address */
-#define Renesas_RZ_A1_SPI_IO1                      (0x1C000000UL)                        /*!< (SPI_IO1   ) Base Address */
-#define Renesas_RZ_A1_ONCHIP_SRAM_BASE             (0x20000000UL)                        /*!< (SRAM_OC   ) Base Address */
-#define Renesas_RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
-#define Renesas_RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
-#define Renesas_RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
-#define Renesas_RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
-#define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE         (0xe8201000UL)                        /*!< (GIC DIST  ) Base Address */
-#define Renesas_RZ_A1_GIC_INTERFACE_BASE           (0xe8202000UL)                        /*!< (GIC CPU IF) Base Address */
-#define Renesas_RZ_A1_PL310_BASE                   (0x3ffff000UL)                        /*!< (PL310     ) Base Address */
-#define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE          (0x60000000UL)                        /*!< (SRAM_OC   ) Base Address */
-
-//Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
-//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
-#define section_normal(descriptor_l1, region)     region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = NON_SECURE; \
-                                   region.xn_t = EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-#define section_normal_nc(descriptor_l1, region)     region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
-#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = NON_SECURE; \
-                                   region.xn_t = EXECUTE; \
-                                   region.priv_t = READ; \
-                                   region.user_t = READ; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-//Sect_Normal_RO. Sect_Normal_Cod, but not executable
-#define section_normal_ro(descriptor_l1, region)  region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = NON_SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = READ; \
-                                   region.user_t = READ; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
-#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = NON_SECURE; \
-                                   region.xn_t = EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
-#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = STRONGLY_ORDERED; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
-#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = STRONGLY_ORDERED; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = READ; \
-                                   region.user_t = READ; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-    
-//Sect_Device_RW. Sect_Device_RO, but writeable
-#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = STRONGLY_ORDERED; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-//Page_4k_Device_RW.  Shared device, not executable, rw, domain 0
-#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = SHARED_DEVICE; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
-
-//Page_64k_Device_RW.  Shared device, not executable, rw, domain 0
-#define page64k_device_rw(descriptor_l1, descriptor_l2, region)  region.rg_t = PAGE_64k; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = SHARED_DEVICE; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
-    
-
-/*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
-
-/******************************************************************************/
-/*                         Clock Settings                                     */
-/******************************************************************************/
-/** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
-  @{
-*/
-
-/*
- * Clock Mode 0 settings
- * SW1-4(MD_CLK):ON
- * SW1-5(MD_CLKS):ON
- * FRQCR=0x1035
- *   CLKEN2    = 0b - unstable
- *   CLKEN[1:0]=01b - Output, Low, Low
- *   IFC[1:0]  =00b - CPU clock is 1/1 PLL clock
- * FRQCR2=0x0001
- *   GFC[1:0]  =01b - Graphic clock is 2/3 bus clock
- */
-#define CM0_RENESAS_RZ_A1_CLKIN  ( 13333333u)
-#define CM0_RENESAS_RZ_A1_CLKO   ( 66666666u)
-#define CM0_RENESAS_RZ_A1_I_CLK  (400000000u)
-#define CM0_RENESAS_RZ_A1_G_CLK  (266666666u)
-#define CM0_RENESAS_RZ_A1_B_CLK  (133333333u)
-#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
-#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
-
-/*
- * Clock Mode 1 settings
- * SW1-4(MD_CLK):OFF
- * SW1-5(MD_CLKS):ON
- * FRQCR=0x1335
- *   CLKEN2    = 0b - unstable
- *   CLKEN[1:0]=01b - Output, Low, Low
- *   IFC[1:0]  =11b - CPU clock is 1/3 PLL clock
- * FRQCR2=0x0003
- *   GFC[1:0]  =11b - graphic clock is 1/3 bus clock
- */
-#define CM1_RENESAS_RZ_A1_CLKIN  ( 48000000u)
-#define CM1_RENESAS_RZ_A1_CLKO   ( 64000000u)
-#define CM1_RENESAS_RZ_A1_I_CLK  (128000000u)
-#define CM1_RENESAS_RZ_A1_G_CLK  (128000000u)
-#define CM1_RENESAS_RZ_A1_B_CLK  (128000000u)
-#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
-#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
-
-/*@}*/ /* end of group Renesas_RZ_A1_Clocks */
-
-/******************************************************************************/
-/*                         CPG   Settings                                     */
-/******************************************************************************/
-/** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
-  @{
-*/
-
-#define CPG_FRQCR_SHIFT_CKOEN2  (14)
-#define CPG_FRQCR_BIT_CKOEN2    (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
-#define CPG_FRQCR_SHIFT_CKOEN0  (12)
-#define CPG_FRQCR_BITS_CKOEN0   (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
-#define CPG_FRQCR_SHIFT_IFC     (8)
-#define CPG_FRQCR_BITS_IFC      (0x3 << CPG_FRQCR_SHIFT_IFC)
-
-#define CPG_FRQCR2_SHIFT_GFC    (0)
-#define CPG_FRQCR2_BITS_GFC     (0x3 << CPG_FRQCR2_SHIFT_GFC)
-
-
-#define CPG_STBCR1_BIT_STBY     (0x80u)
-#define CPG_STBCR1_BIT_DEEP     (0x40u)
-#define CPG_STBCR2_BIT_HIZ      (0x80u)
-#define CPG_STBCR2_BIT_MSTP20   (0x01u) /* CoreSight */
-#define CPG_STBCR3_BIT_MSTP37   (0x80u) /* IEBus */
-#define CPG_STBCR3_BIT_MSTP36   (0x40u) /* IrDA */
-#define CPG_STBCR3_BIT_MSTP35   (0x20u) /* LIN0 */
-#define CPG_STBCR3_BIT_MSTP34   (0x10u) /* LIN1 */
-#define CPG_STBCR3_BIT_MSTP33   (0x08u) /* Multi-Function Timer */
-#define CPG_STBCR3_BIT_MSTP32   (0x04u) /* CAN */
-#define CPG_STBCR3_BIT_MSTP30   (0x01u) /* Motor Control PWM Timer */
-#define CPG_STBCR4_BIT_MSTP47   (0x80u) /* SCIF0 */
-#define CPG_STBCR4_BIT_MSTP46   (0x40u) /* SCIF1 */
-#define CPG_STBCR4_BIT_MSTP45   (0x20u) /* SCIF2 */
-#define CPG_STBCR4_BIT_MSTP44   (0x10u) /* SCIF3 */
-#define CPG_STBCR4_BIT_MSTP43   (0x08u) /* SCIF4 */
-#define CPG_STBCR4_BIT_MSTP42   (0x04u) /* SCIF5 */
-#define CPG_STBCR4_BIT_MSTP41   (0x02u) /* SCIF6 */
-#define CPG_STBCR4_BIT_MSTP40   (0x01u) /* SCIF7 */
-#define CPG_STBCR5_BIT_MSTP57   (0x80u) /* SCI0 */
-#define CPG_STBCR5_BIT_MSTP56   (0x40u) /* SCI1 */
-#define CPG_STBCR5_BIT_MSTP55   (0x20u) /* Sound Generator0 */
-#define CPG_STBCR5_BIT_MSTP54   (0x10u) /* Sound Generator1 */
-#define CPG_STBCR5_BIT_MSTP53   (0x08u) /* Sound Generator2 */
-#define CPG_STBCR5_BIT_MSTP52   (0x04u) /* Sound Generator3 */
-#define CPG_STBCR5_BIT_MSTP51   (0x02u) /* OSTM0 */
-#define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
-#define CPG_STBCR6_BIT_MSTP67   (0x80u) /* General A/D Comvertor */
-#define CPG_STBCR6_BIT_MSTP66   (0x40u) /* Capture Engine */
-#define CPG_STBCR6_BIT_MSTP65   (0x20u) /* Display out comparison0 */
-#define CPG_STBCR6_BIT_MSTP64   (0x10u) /* Display out comparison1 */   
-#define CPG_STBCR6_BIT_MSTP63   (0x08u) /* Dynamic Range Compalator0 */
-#define CPG_STBCR6_BIT_MSTP62   (0x04u) /* Dynamic Range Compalator1 */
-#define CPG_STBCR6_BIT_MSTP61   (0x02u) /* JPEG Decoder */
-#define CPG_STBCR6_BIT_MSTP60   (0x01u) /* Realtime Clock */
-#define CPG_STBCR7_BIT_MSTP77   (0x80u) /* Video Decoder0 */
-#define CPG_STBCR7_BIT_MSTP76   (0x40u) /* Video Decoder1 */
-#define CPG_STBCR7_BIT_MSTP74   (0x10u) /* Ether */
-#define CPG_STBCR7_BIT_MSTP73   (0x04u) /* NAND Flash Memory Controller */
-#define CPG_STBCR7_BIT_MSTP71   (0x02u) /* USB0 */
-#define CPG_STBCR7_BIT_MSTP70   (0x01u) /* USB1 */
-#define CPG_STBCR8_BIT_MSTP87   (0x80u) /* IMR-LS2_0 */
-#define CPG_STBCR8_BIT_MSTP86   (0x40u) /* IMR-LS2_1 */
-#define CPG_STBCR8_BIT_MSTP85   (0x20u) /* IMR-LSD */
-#define CPG_STBCR8_BIT_MSTP84   (0x10u) /* MMC Host Interface */
-#define CPG_STBCR8_BIT_MSTP83   (0x08u) /* MediaLB */
-#define CPG_STBCR8_BIT_MSTP81   (0x02u) /* SCUX */
-#define CPG_STBCR9_BIT_MSTP97   (0x80u) /* RIIC0 */
-#define CPG_STBCR9_BIT_MSTP96   (0x40u) /* RIIC1 */
-#define CPG_STBCR9_BIT_MSTP95   (0x20u) /* RIIC2 */
-#define CPG_STBCR9_BIT_MSTP94   (0x10u) /* RIIC3 */
-#define CPG_STBCR9_BIT_MSTP93   (0x08u) /* SPI Multi I/O Bus Controller0 */
-#define CPG_STBCR9_BIT_MSTP92   (0x04u) /* SPI Multi I/O Bus Controller1 */
-#define CPG_STBCR9_BIT_MSTP91   (0x02u) /* VDC5_0 */
-#define CPG_STBCR9_BIT_MSTP90   (0x01u) /* VDC5_1 */
-#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
-#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
-#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
-#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
-#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
-#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
-#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
-#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
-#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
-#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
-#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
-#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
-#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
-#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
-#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
-#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
-#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
-#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
-#define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
-#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
-#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
-#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
-#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
-#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
-#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
-#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
-#define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
-#define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
-#define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
-#define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
-#define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
-#define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
-#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
-#define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
-#define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
-#define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
-#define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
-#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
-#define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
-#define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
-#define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
-#define CPG_SYSCR1_BIT_VRAME4   (0x10u) /* VRAM E Page4 */
-#define CPG_SYSCR1_BIT_VRAME3   (0x08u) /* VRAM E Page3 */
-#define CPG_SYSCR1_BIT_VRAME2   (0x04u) /* VRAM E Page2 */
-#define CPG_SYSCR1_BIT_VRAME1   (0x02u) /* VRAM E Page1 */
-#define CPG_SYSCR1_BIT_VRAME0   (0x01u) /* VRAM E Page0 */
-#define CPG_SYSCR2_BIT_VRAMWE4  (0x10u) /* VRAM WE Page4 */
-#define CPG_SYSCR2_BIT_VRAMWE3  (0x08u) /* VRAM WE Page3 */
-#define CPG_SYSCR2_BIT_VRAMWE2  (0x04u) /* VRAM WE Page2 */
-#define CPG_SYSCR2_BIT_VRAMWE1  (0x02u) /* VRAM WE Page1 */
-#define CPG_SYSCR2_BIT_VRAMWE0  (0x01u) /* VRAM WE Page0 */
-#define CPG_SYSCR3_BIT_RRAMWE3  (0x08u) /* RRAM WE Page3 */
-#define CPG_SYSCR3_BIT_RRAMWE2  (0x04u) /* RRAM WE Page2 */
-#define CPG_SYSCR3_BIT_RRAMWE1  (0x02u) /* RRAM WE Page1 */
-#define CPG_SYSCR3_BIT_RRAMWE0  (0x01u) /* RRAM WE Page0 */
-
-/*@}*/ /* end of group Renesas_RZ_A1_CPG */
-
-/******************************************************************************/
-/*                        GPIO   Settings                                     */
-/******************************************************************************/
-/** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
-  @{
-*/
-
-#define GPIO_BIT_N0  (1u <<  0)
-#define GPIO_BIT_N1  (1u <<  1)
-#define GPIO_BIT_N2  (1u <<  2)
-#define GPIO_BIT_N3  (1u <<  3)
-#define GPIO_BIT_N4  (1u <<  4)
-#define GPIO_BIT_N5  (1u <<  5)
-#define GPIO_BIT_N6  (1u <<  6)
-#define GPIO_BIT_N7  (1u <<  7)
-#define GPIO_BIT_N8  (1u <<  8)
-#define GPIO_BIT_N9  (1u <<  9)
-#define GPIO_BIT_N10 (1u << 10)
-#define GPIO_BIT_N11 (1u << 11)
-#define GPIO_BIT_N12 (1u << 12)
-#define GPIO_BIT_N13 (1u << 13)
-#define GPIO_BIT_N14 (1u << 14)
-#define GPIO_BIT_N15 (1u << 15)
-
-
-#define MD_BOOT10_MASK    (0x3)
-
-#define MD_BOOT10_BM0     (0x0)
-#define MD_BOOT10_BM1     (0x2)
-#define MD_BOOT10_BM3     (0x1)
-#define MD_BOOT10_BM4_5   (0x3)
-
-#define MD_CLK        (1u << 2)
-#define MD_CLKS       (1u << 3)
-
-/*@}*/ /* end of group Renesas_RZ_A1_GPIO */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  // __MBRZA1H_H__
+#include "RZ_A1H.h"

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct	Wed Jan 17 15:23:54 2018 +0000
@@ -1,43 +1,57 @@
-
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
 
-LOAD_TTB    0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+#include "mem_RZ_A1H.h"
+
+LOAD_TTB    __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
 {
     TTB     +0 EMPTY 0x4000            
     { }                           ; Level-1 Translation Table for MMU
 }
 
-SFLASH 0x18000000 (0x08000000)
+SFLASH __ROM_BASE __ROM_SIZE       ; load region size_region
 {
-    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-    ; S-Flash ROM : Executable cached region
-    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+  BOOT_LOADER_BEGIN __ROM_BASE FIXED
+  {
+    * (BOOT_LOADER)
+  }
 
-    BOOT_LOADER_BEGIN 0x18000000 FIXED
-    {
-        *   ( BOOT_LOADER )
-    }
+  VECTORS __VECTOR_BASE FIXED
+  {
+    * (RESET, +FIRST)         ; Vector table and other startup code
+    * (InRoot$$Sections)      ; All (library) code that must be in a root region
+    * (+RO-CODE)              ; Application RO code (.text)
+  }
+
+  RO_DATA    +0
+  { * (+RO-DATA) }              ; Application RO data (.constdata)
 
-    VECTORS 0x18004000 FIXED
-    {
-        * (RESET, +FIRST)         ; Vector table and other (assembler) startup code
-        * (InRoot$$Sections)      ; All (library) code that must be in a root region
-        * (+RO-CODE)              ; Application RO code (.text)
-    }
+  RW_DATA 0x20020000
+  { * (+RW) }                   ; Application RW data (.data)
 
-    RO_DATA    +0
-    { * (+RO-DATA) }              ; Application RO data (.constdata)
+  RW_IRAM1    +0 ALIGN 0x10
+  { * (+ZI) }                   ; Application ZI data (.bss)
+
+  ARM_LIB_HEAP  +0
+  { * (HEAP) }                  ; Application heap area (HEAP)
 
-    RW_DATA    0x20020000
-    { * (+RW) }                   ; Application RW data (.data)
-
-    ZI_DATA    +0 ALIGN 0x400
-    { * (+ZI) }                   ; Application ZI data (.bss)
+  ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }
 
-    RW_DATA_NC 0x60900000 0x00100000
-    { * (NC_DATA) }              ; Application RW data Non cached area
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+  ; RAM-NC : Internal non-cached RAM region
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-    ZI_DATA_NC +0
-    { * (NC_BSS) }               ; Application ZI data Non cached area
+  RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE
+  { * (NC_DATA) }              ; Application RW data Non cached area
+
+  ZI_DATA_NC +0
+  { * (NC_BSS) }               ; Application ZI data Non cached area
 }
 
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,77 @@
+/**************************************************************************//**
+ * @file     mem_RZ_A1H.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_RZ_A1H_H
+#define __MEM_RZ_A1H_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x18000000
+#define __ROM_SIZE       0x08000000
+
+#define __VECTOR_BASE    0x18004000
+
+/*--------------------- RAM Configuration -----------------------------------
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x20000000
+#define __RAM_SIZE       0x00A00000
+#define __NC_RAM_SIZE    0x00100000
+#define __NM_RAM_SIZE    (__RAM_SIZE - __NC_RAM_SIZE)
+#define __DATA_NC_BASE   (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
+
+#define __UND_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00008000
+#define __ABT_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x0000F000
+#define __STACK_SIZE     (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x20000000
+#define __TTB_SIZE       0x00004000
+
+#endif /* __MEM_RZ_A1H_H */

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_MBRZA1H.S	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,454 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_MBRZA1H.s
-; * @purpose: CMSIS Cortex-A9 Core Device Startup File 
-; *           for the NXP MBRZA1H Device Series 
-; * @version: V1.02, modified for mbed
-; * @date:    27. July 2009, modified 3rd Aug 2009
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2009 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-GICI_BASE       EQU     0xe8202000
-ICCIAR_OFFSET   EQU     0x0000000C
-ICCEOIR_OFFSET  EQU     0x00000010
-ICCHPIR_OFFSET  EQU     0x00000018
-
-GICD_BASE       EQU     0xe8201000
-ICDISER0_OFFSET EQU     0x00000100
-ICDICER0_OFFSET EQU     0x00000180
-ICDISPR0_OFFSET EQU     0x00000200
-ICDABR0_OFFSET  EQU     0x00000300
-ICDIPR0_OFFSET  EQU     0x00000400
-
-Mode_USR        EQU     0x10
-Mode_FIQ        EQU     0x11
-Mode_IRQ        EQU     0x12
-Mode_SVC        EQU     0x13
-Mode_ABT        EQU     0x17
-Mode_UND        EQU     0x1B
-Mode_SYS        EQU     0x1F
-
-I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
-F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled
-T_Bit           EQU     0x20            ; when T bit is set, core is in Thumb state
-
-GIC_ERRATA_CHECK_1     EQU     0x000003FE
-GIC_ERRATA_CHECK_2     EQU     0x000003FF
-
-
-Sect_Normal     EQU     0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
-Sect_Normal_Cod EQU     0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
-Sect_Normal_RO  EQU     0x0000dc16 ;as Sect_Normal_Cod, but not executable
-Sect_Normal_RW  EQU     0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable
-Sect_SO         EQU     0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
-Sect_Device_RO  EQU     0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0
-Sect_Device_RW  EQU     0x00000c12 ;as Sect_Device_RO, but writeable
-Sect_Fault      EQU     0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored)
-
-RAM_BASE        EQU     0x80000000
-VRAM_BASE       EQU     0x18000000
-SRAM_BASE       EQU     0x2e000000
-ETHERNET        EQU     0x1a000000
-CS3_PERIPHERAL_BASE EQU 0x1c000000
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8>
-; </h>
-
-UND_Stack_Size  EQU     0x00000100
-SVC_Stack_Size  EQU     0x00008000
-ABT_Stack_Size  EQU     0x00000100
-FIQ_Stack_Size  EQU     0x00000100
-IRQ_Stack_Size  EQU     0x00008000
-USR_Stack_Size  EQU     0x00004000
-
-ISR_Stack_Size  EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
-                         FIQ_Stack_Size + IRQ_Stack_Size)
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   USR_Stack_Size
-__initial_sp    SPACE   ISR_Stack_Size
-
-Stack_Top
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00080000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                ARM
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, CODE, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       LDR     PC, Reset_Addr            ; Address of Reset Handler
-                LDR     PC, Undef_Addr            ; Address of Undef Handler
-                LDR     PC, SVC_Addr              ; Address of SVC Handler
-                LDR     PC, PAbt_Addr             ; Address of Prefetch Abort Handler
-                LDR     PC, DAbt_Addr             ; Address of Data Abort Handler
-                NOP                               ; Reserved Vector
-                LDR     PC, IRQ_Addr              ; Address of IRQ Handler
-                LDR     PC, FIQ_Addr              ; Address of FIQ Handler
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-Reset_Addr      DCD     Reset_Handler
-Undef_Addr      DCD     Undef_Handler
-SVC_Addr        DCD     SVC_Handler
-PAbt_Addr       DCD     PAbt_Handler
-DAbt_Addr       DCD     DAbt_Handler
-IRQ_Addr        DCD     IRQ_Handler
-FIQ_Addr        DCD     FIQ_Handler
-
-                AREA    |.text|, CODE, READONLY
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  InitMemorySubsystem
-                IMPORT  __main
-                IMPORT  RZ_A1_SetSramWriteEnable
-
-                ; Put any cores other than 0 to sleep
-                MRC     p15, 0, R0, c0, c0, 5     ; Read MPIDR
-                ANDS    R0, R0, #3
-goToSleep
-                WFINE
-                BNE     goToSleep
-
-; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
-; Enables Full Access i.e. in both privileged and non privileged modes
-                MRC     p15, 0, r0, c1, c0, 2       ; Read Coprocessor Access Control Register (CPACR)
-                ORR     r0, r0, #(0xF << 20)        ; Enable access to CP 10 & 11
-                MCR     p15, 0, r0, c1, c0, 2       ; Write Coprocessor Access Control Register (CPACR)
-                ISB
-
-; Switch on the VFP and NEON hardware
-                MOV     r0, #0x40000000
-                VMSR    FPEXC, r0                   ; Write FPEXC register, EN bit set
-
-                MRC     p15, 0, R0, c1, c0, 0       ; Read CP15 System Control register
-                BIC     R0, R0, #(0x1 << 12)        ; Clear I bit 12 to disable I Cache
-                BIC     R0, R0, #(0x1 <<  2)        ; Clear C bit  2 to disable D Cache
-                BIC     R0, R0, #0x1                ; Clear M bit  0 to disable MMU
-                BIC     R0, R0, #(0x1 << 11)        ; Clear Z bit 11 to disable branch prediction
-                BIC     R0, R0, #(0x1 << 13)        ; Clear V bit 13 to disable hivecs
-                MCR     p15, 0, R0, c1, c0, 0       ; Write value back to CP15 System Control register
-                ISB
-
-; Set Vector Base Address Register (VBAR) to point to this application's vector table
-                LDR     R0, =__Vectors
-                MCR     p15, 0, R0, c12, c0, 0
-
-;  Setup Stack for each exceptional mode
-                LDR     R0, =Stack_Top
-
-;  Enter Undefined Instruction Mode and set its Stack Pointer
-                MSR     CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-                SUB     R0, R0, #UND_Stack_Size
-
-;  Enter Abort Mode and set its Stack Pointer
-                MSR     CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-                SUB     R0, R0, #ABT_Stack_Size
-
-;  Enter FIQ Mode and set its Stack Pointer
-                MSR     CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-                SUB     R0, R0, #FIQ_Stack_Size
-
-;  Enter IRQ Mode and set its Stack Pointer
-                MSR     CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-                SUB     R0, R0, #IRQ_Stack_Size
-
-;  Enter Supervisor Mode and set its Stack Pointer
-                MSR     CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-
-;  Enter System Mode to complete initialization and enter kernel
-                MSR     CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-
-                ISB
-
-                LDR     R0, =RZ_A1_SetSramWriteEnable
-                BLX     R0
-
-                IMPORT  create_translation_table
-                BL      create_translation_table
-
-;  USR/SYS stack pointer will be set during kernel init
-
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =InitMemorySubsystem
-                BLX     R0
-                LDR     R0, =__main
-                BLX     R0
-
-                ENDP
-
-Undef_Handler\
-                PROC
-                EXPORT  Undef_Handler             [WEAK]
-                IMPORT  CUndefHandler
-                SRSFD   SP!, #Mode_UND
-                PUSH    {R0-R4, R12}              ; Save APCS corruptible registers to UND mode stack
-
-                MRS     R0, SPSR
-                TST     R0, #T_Bit                ; Check mode
-                MOVEQ   R1, #4                    ; R1 = 4 ARM mode
-                MOVNE   R1, #2                    ; R1 = 2 Thumb mode
-                SUB     R0, LR, R1
-                LDREQ   R0, [R0]                  ; ARM mode - R0 points to offending instruction
-                BEQ     undef_cont
-
-                ;Thumb instruction
-                ;Determine if it is a 32-bit Thumb instruction
-                LDRH    R0, [R0]
-                MOV     R2, #0x1c
-                CMP     R2, R0, LSR #11
-                BHS     undef_cont                ;16-bit Thumb instruction
-
-                ;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction.
-                LDRH    R2, [LR]
-                ORR     R0, R2, R0, LSL #16
-undef_cont
-                MOV     R2, LR                    ; Set LR to third argument
-                
-;               AND     R12, SP, #4               ; Ensure stack is 8-byte aligned
-                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               ; Adjust stack
-                PUSH    {R12, LR}                 ; Store stack adjustment and dummy LR
-
-                ;R0 Offending instruction
-                ;R1 =2 (Thumb) or =4 (ARM)
-                BL      CUndefHandler
-
-                POP     {R12, LR}                 ; Get stack adjustment & discard dummy LR
-                ADD     SP, SP, R12               ; Unadjust stack
-
-                LDR     LR, [SP, #24]             ; Restore stacked LR and possibly adjust for retry
-                SUB     LR, LR, R0
-                LDR     R0, [SP, #28]             ; Restore stacked SPSR
-                MSR     SPSR_CXSF, R0
-                POP     {R0-R4, R12}              ; Restore stacked APCS registers
-                ADD     SP, SP, #8                ; Adjust SP for already-restored banked registers
-                MOVS    PC, LR
-                ENDP
-
-PAbt_Handler\
-                PROC
-                EXPORT  PAbt_Handler              [WEAK]
-                IMPORT  CPAbtHandler
-                SUB     LR, LR, #4                ; Pre-adjust LR
-                SRSFD   SP!, #Mode_ABT            ; Save LR and SPRS to ABT mode stack
-                PUSH    {R0-R4, R12}              ; Save APCS corruptible registers to ABT mode stack
-                MRC     p15, 0, R0, c5, c0, 1     ; IFSR
-                MRC     p15, 0, R1, c6, c0, 2     ; IFAR
-
-                MOV     R2, LR                    ; Set LR to third argument
-
-;               AND     R12, SP, #4               ; Ensure stack is 8-byte aligned
-                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               ; Adjust stack
-                PUSH    {R12, LR}                 ; Store stack adjustment and dummy LR
-
-                BL      CPAbtHandler
-
-                POP     {R12, LR}                 ; Get stack adjustment & discard dummy LR
-                ADD     SP, SP, R12               ; Unadjust stack
-
-                POP     {R0-R4, R12}              ; Restore stack APCS registers
-                RFEFD   SP!                       ; Return from exception
-                ENDP
-
-
-DAbt_Handler\
-                PROC
-                EXPORT  DAbt_Handler              [WEAK]
-                IMPORT  CDAbtHandler
-                SUB     LR, LR, #8                ; Pre-adjust LR
-                SRSFD   SP!, #Mode_ABT            ; Save LR and SPRS to ABT mode stack
-                PUSH    {R0-R4, R12}              ; Save APCS corruptible registers to ABT mode stack
-                CLREX                             ; State of exclusive monitors unknown after taken data abort
-                MRC     p15, 0, R0, c5, c0, 0     ; DFSR
-                MRC     p15, 0, R1, c6, c0, 0     ; DFAR
-
-                MOV     R2, LR                    ; Set LR to third argument
-
-;               AND     R12, SP, #4               ; Ensure stack is 8-byte aligned
-                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               ; Adjust stack
-                PUSH    {R12, LR}                 ; Store stack adjustment and dummy LR
-
-                BL      CDAbtHandler
-
-                POP     {R12, LR}                 ; Get stack adjustment & discard dummy LR
-                ADD     SP, SP, R12               ; Unadjust stack
-
-                POP     {R0-R4, R12}              ; Restore stacked APCS registers
-                RFEFD   SP!                       ; Return from exception
-                ENDP
-
-FIQ_Handler\
-                PROC
-                EXPORT  FIQ_Handler               [WEAK]
-                ;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
-                ;; so if a real FIQ Handler is implemented, this will be needed before returning:
-                ;; LDR     R1, =GICI_BASE
-                ;; LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
-                B       .
-                ENDP
-
-SVC_Handler\
-                PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-
-IRQ_Handler\
-                PROC
-                EXPORT  IRQ_Handler                [WEAK]
-                IMPORT  IRQCount
-                IMPORT  IRQTable
-                IMPORT  IRQNestLevel
-
-                ;prologue
-                SUB     LR, LR, #4                  ; Pre-adjust LR
-                SRSFD   SP!, #Mode_SVC              ; Save LR_IRQ and SPRS_IRQ to SVC mode stack
-                CPS     #Mode_SVC                   ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL
-                PUSH    {R0-R3, R12}                ; Save remaining APCS corruptible registers to SVC stack
-
-;               AND     R1, SP, #4                  ; Ensure stack is 8-byte aligned
-                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
-                AND     R1, R3, #4
-                SUB     SP, SP, R1                  ; Adjust stack
-                PUSH    {R1, LR}                    ; Store stack adjustment and LR_SVC to SVC stack
-
-                LDR     R0, =IRQNestLevel           ; Get address of nesting counter
-                LDR     R1, [R0]
-                ADD     R1, R1, #1                  ; Increment nesting counter
-                STR     R1, [R0]
-
-                ;identify and acknowledge interrupt
-                LDR     R1, =GICI_BASE
-                LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
-                LDR     R0, [R1, #ICCIAR_OFFSET]    ; Read ICCIAR (GIC CPU Interface register)
-                DSB                                 ; Ensure that interrupt acknowledge completes before re-enabling interrupts
-
-                ; Workaround GIC 390 errata 733075
-                ; If the ID is not 0, then service the interrupt as normal.
-                ; If the ID is 0 and active, then service interrupt ID 0 as normal.
-                ; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
-                ;   with a dummy write to ICDIPR0.  This interrupt should be treated as spurious and not serviced.
-                ;
-                LDR     R2, =GICD_BASE
-                LDR     R3, =GIC_ERRATA_CHECK_1
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                LDR     R3, =GIC_ERRATA_CHECK_2
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                CMP     R0, #0
-                BNE     int_active					; If the ID is not 0, then service the interrupt
-                LDR     R3, [R2, #ICDABR0_OFFSET]   ; Get the interrupt state
-                TST     R3, #1
-                BNE     int_active                  ; If active, then service the interrupt
-unlock_cpu
-                LDR     R3, [R2, #ICDIPR0_OFFSET]   ; Not active, so unlock the CPU interface
-                STR     R3, [R2, #ICDIPR0_OFFSET]   ;   with a dummy write
-                DSB                                 ; Ensure the write completes before continuing
-                B       ret_irq                     ; Do not service the spurious interrupt
-                ; End workaround
-
-int_active
-                LDR     R2, =IRQCount               ; Read number of IRQs
-                LDR     R2, [R2]
-                CMP     R0, R2                      ; Clean up and return if no handler
-                BHS     ret_irq                     ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling
-                LDR     R2, =IRQTable               ; Get address of handler
-                LDR     R2, [R2, R0, LSL #2]
-                CMP     R2, #0                      ; Clean up and return if handler address is 0
-                BEQ     ret_irq
-                PUSH    {R0,R1}
-
-                CPSIE   i                           ; Now safe to re-enable interrupts
-                BLX     R2                          ; Call handler. R0 will be IRQ number
-                CPSID   i                           ; Disable interrupts again
-
-                ;write EOIR (GIC CPU Interface register)
-                POP     {R0,R1}
-                DSB                                 ; Ensure that interrupt source is cleared before we write the EOIR
-ret_irq
-                ;epilogue
-                STR     R0, [R1, #ICCEOIR_OFFSET]
-
-                LDR     R0, =IRQNestLevel           ; Get address of nesting counter
-                LDR     R1, [R0]
-                SUB     R1, R1, #1                  ; Decrement nesting counter
-                STR     R1, [R0]
-
-                POP     {R1, LR}                    ; Get stack adjustment and restore LR_SVC
-                ADD     SP, SP, R1                  ; Unadjust stack
-
-                POP     {R0-R3,R12}                 ; Restore stacked APCS registers
-                RFEFD   SP!                         ; Return from exception
-                ENDP
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-                
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + USR_Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-
-                ENDIF
-
-
-                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,162 @@
+/******************************************************************************
+ * @file     startup_RZ_A1H_H.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "MBRZA1H.h"
+#include "mem_RZ_A1H.h"
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((section("RESET")));
+void Reset_Handler(void);
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+__ASM void Vectors(void) {
+  IMPORT Undef_Handler
+  IMPORT SVC_Handler
+  IMPORT PAbt_Handler
+  IMPORT DAbt_Handler
+  IMPORT IRQ_Handler
+  IMPORT FIQ_Handler
+  LDR    PC, =Reset_Handler
+  LDR    PC, =Undef_Handler
+  LDR    PC, =SVC_Handler
+  LDR    PC, =PAbt_Handler
+  LDR    PC, =DAbt_Handler
+  NOP
+  LDR    PC, =IRQ_Handler
+  LDR    PC, =FIQ_Handler
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__ASM void Reset_Handler(void) {
+
+  // Mask interrupts
+  CPSID   if                           
+
+  // Put any cores other than 0 to sleep
+  MRC     p15, 0, R0, c0, c0, 5       // Read MPIDR
+  ANDS    R0, R0, #3
+goToSleep
+  WFINE
+  BNE     goToSleep
+
+  // Reset SCTLR Settings
+  MRC     p15, 0, R0, c1, c0, 0       // Read CP15 System Control register
+  BIC     R0, R0, #(0x1 << 12)        // Clear I bit 12 to disable I Cache
+  BIC     R0, R0, #(0x1 <<  2)        // Clear C bit  2 to disable D Cache
+  BIC     R0, R0, #0x1                // Clear M bit  0 to disable MMU
+  BIC     R0, R0, #(0x1 << 11)        // Clear Z bit 11 to disable branch prediction
+  BIC     R0, R0, #(0x1 << 13)        // Clear V bit 13 to disable hivecs
+  MCR     p15, 0, R0, c1, c0, 0       // Write value back to CP15 System Control register
+  ISB
+
+  // Configure ACTLR
+  MRC     p15, 0, r0, c1, c0, 1       // Read CP15 Auxiliary Control Register
+  ORR     r0, r0, #(1 <<  1)          // Enable L2 prefetch hint (UNK/WI since r4p1)
+  MCR     p15, 0, r0, c1, c0, 1       // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  LDR    R0, =Vectors
+  MCR    p15, 0, R0, c12, c0, 0
+
+  // Setup Stack for each exceptional mode
+  IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+  LDR    R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+  //Enter Undefined Instruction Mode and set its Stack Pointer 
+  CPS    #UND_MODE
+  MOV    SP, R0
+  SUB    R0, R0, #__UND_STACK_SIZE
+
+  // Enter Abort Mode and set its Stack Pointer 
+  CPS    #ABT_MODE
+  MOV    SP, R0
+  SUB    R0, R0, #__ABT_STACK_SIZE
+
+  // Enter FIQ Mode and set its Stack Pointer 
+  CPS    #FIQ_MODE
+  MOV    SP, R0
+  SUB    R0, R0, #__FIQ_STACK_SIZE
+
+  // Enter IRQ Mode and set its Stack Pointer 
+  CPS    #IRQ_MODE
+  MOV    SP, R0
+  SUB    R0, R0, #__IRQ_STACK_SIZE
+
+  // Enter Supervisor Mode and set its Stack Pointer 
+  CPS    #SVC_MODE
+  MOV    SP, R0
+  SUB    R0, R0, #__SVC_STACK_SIZE
+
+  // Enter System Mode to complete initialization and enter kernel 
+  CPS    #SYS_MODE
+  MOV    SP, R0
+
+  // Call SystemInit
+  IMPORT SystemInit
+  BL     SystemInit
+
+  // Unmask interrupts
+  CPSIE  if
+
+  // Call __main
+  IMPORT __main
+  BL     __main
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+	while(1);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2017 ARM Limited.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include <arm_compat.h>
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$ARM_LIB_HEAP$$Base[];
+extern char Image$$ARM_LIB_STACK$$Base[];
+
+extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
+    uint32_t sp_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base;
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld	Wed Jan 17 15:23:54 2018 +0000
@@ -7,7 +7,7 @@
   BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000 
   SFLASH (rx) : ORIGIN = 0x18004000, LENGTH = 0x07FFC000 
   L_TTB (rw)  : ORIGIN = 0x20000000, LENGTH = 0x00004000 
-  RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000
+  RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x008E0000
   RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000
 }
 
@@ -51,7 +51,6 @@
 
         Image$$VECTORS$$Base = .;
         * (RESET)
-        Image$$VECTORS$$Limit = .;
         . += 0x00000400;
 
         KEEP(*(.isr_vector))
@@ -74,6 +73,7 @@
         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
         *(SORT(.dtors.*))
         *(.dtors)
+        Image$$VECTORS$$Limit = .;
 
         Image$$RO_DATA$$Base = .;
         *(.rodata*)
@@ -163,34 +163,42 @@
 
     } > RAM
 
-    
-    .bss ALIGN(0x400):
+    .bss ALIGN(0x10):
     {
-        Image$$ZI_DATA$$Base = .;
+        Image$$RW_IRAM1$$Base = .;
         __bss_start__ = .;
         *(.bss*)
         *(COMMON)
         __bss_end__ = .;
-        Image$$ZI_DATA$$Limit = .;
+        Image$$RW_IRAM1$$Limit = .;
     } > RAM
 
-    
     .heap :
     {
         __end__ = .;
         end = __end__;
         *(.heap*)
-        __HeapLimit = .;
     } > RAM
 
     /* .stack_dummy section doesn't contains any symbols. It is only
      * used for linker to calculate size of stack sections, and assign
      * values to stack symbols later */
-    .stack_dummy :
+    .stack_dummy (COPY):
     {
-        *(.stack)
+        *(.stack*)
     } > RAM
 
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    __HeapLimit = __StackLimit;
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
     __etext2 = __etext + SIZEOF(.data);
     .nc_data : AT (__etext2)
     {
@@ -213,15 +221,4 @@
         __nc_bss_end = .;
         Image$$ZI_DATA_NC$$Limit = .;
     } > RAM_NC
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
-
 }

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S	Wed Jan 17 15:23:54 2018 +0000
@@ -19,26 +19,6 @@
     .extern _start
  
 @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
-    .equ    USR_MODE        ,   0x10
-    .equ    FIQ_MODE        ,   0x11
-    .equ    IRQ_MODE        ,   0x12
-    .equ    SVC_MODE        ,   0x13
-    .equ    ABT_MODE        ,   0x17
-    .equ    UND_MODE        ,   0x1b
-    .equ    SYS_MODE        ,   0x1f
-    .equ    Thum_bit        ,   0x20            @ CPSR/SPSR Thumb bit
-
-    .equ    GICI_BASE       ,   0xe8202000
-    .equ    ICCIAR_OFFSET   ,   0x0000000C
-    .equ    ICCEOIR_OFFSET  ,   0x00000010
-    .equ    ICCHPIR_OFFSET  ,   0x00000018
-    .equ    GICD_BASE       ,   0xe8201000
-    .equ    ICDISER0_OFFSET ,   0x00000100
-    .equ    ICDICER0_OFFSET ,   0x00000180
-    .equ    ICDISPR0_OFFSET ,   0x00000200
-    .equ    ICDABR0_OFFSET  ,   0x00000300
-    .equ    ICDIPR0_OFFSET  ,   0x00000400
-
     .equ    Mode_USR        ,   0x10
     .equ    Mode_FIQ        ,   0x11
     .equ    Mode_IRQ        ,   0x12
@@ -50,34 +30,14 @@
     .equ    I_Bit           ,   0x80            @ when I bit is set, IRQ is disabled 
     .equ    F_Bit           ,   0x40            @ when F bit is set, FIQ is disabled 
     .equ    T_Bit           ,   0x20            @ when T bit is set, core is in Thumb state 
-
-    .equ    GIC_ERRATA_CHECK_1, 0x000003FE 
-    .equ    GIC_ERRATA_CHECK_2, 0x000003FF 
-
-    .equ    Sect_Normal     , 0x00005c06        @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 
-    .equ    Sect_Normal_Cod , 0x0000dc06        @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 
-    .equ    Sect_Normal_RO  , 0x0000dc16        @ as Sect_Normal_Cod, but not executable 
-    .equ    Sect_Normal_RW  , 0x00005c16        @ as Sect_Normal_Cod, but writeable and not executable 
-    .equ    Sect_SO         , 0x00000c12        @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 
-    .equ    Sect_Device_RO  , 0x00008c12        @ device, non-shareable, non-executable, ro, domain 0, base addr 0 
-    .equ    Sect_Device_RW  , 0x00000c12        @ as Sect_Device_RO, but writeable 
-    .equ    Sect_Fault      , 0x00000000        @ this translation will fault (the bottom 2 bits are important, the rest are ignored) 
-
-    .equ    RAM_BASE        , 0x80000000
-    .equ    VRAM_BASE       , 0x18000000
-    .equ    SRAM_BASE       , 0x2e000000
-    .equ    ETHERNET        , 0x1a000000
-    .equ    CS3_PERIPHERAL_BASE, 0x1c000000
-
-
+ 
 @ Stack Configuration
 
     .EQU    UND_Stack_Size  , 0x00000100
     .EQU    SVC_Stack_Size  , 0x00008000
     .EQU    ABT_Stack_Size  , 0x00000100
     .EQU    FIQ_Stack_Size  , 0x00000100
-    .EQU    IRQ_Stack_Size  , 0x00008000
-    .EQU    USR_Stack_Size  , 0x00004000
+    .EQU    IRQ_Stack_Size  , 0x0000F000
 
     .EQU    ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
 
@@ -88,7 +48,6 @@
 __StackLimit:
     .space    ISR_Stack_Size
 __initial_sp:
-    .space    USR_Stack_Size
     .size __StackLimit, . - __StackLimit
 __StackTop:
     .size __StackTop, . - __StackTop
@@ -136,28 +95,20 @@
 
     .text
     .align 2
-    .globl          Reset_Handler
+    .globl         Reset_Handler
     .type          Reset_Handler, %function
 Reset_Handler:
+    @ Mask interrupts
+    CPSID   if                           
+
     @ Put any cores other than 0 to sleep
     mrc     p15, 0, r0, c0, c0, 5   @ Read MPIDR
     ands    r0, r0, #3
-
 goToSleep:
     wfine
     bne     goToSleep
 
-@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. 
-@ Enables Full Access i.e. in both privileged and non privileged modes 
-    mrc     p15, 0, r0, c1, c0, 2       @ Read Coprocessor Access Control Register (CPACR) 
-    orr     r0, r0, #(0xF << 20)        @ Enable access to CP 10 & 11 
-    mcr     p15, 0, r0, c1, c0, 2       @ Write Coprocessor Access Control Register (CPACR) 
-    isb
-
-@ Switch on the VFP and NEON hardware 
-    mov     r0, #0x40000000
-    vmsr    fpexc, r0                   @ Write FPEXC register, EN bit set 
-
+    @ Reset SCTLR Settings
     mrc     p15, 0, r0, c1, c0, 0       @ Read CP15 System Control register 
     bic     r0, r0, #(0x1 << 12)        @ Clear I bit 12 to disable I Cache 
     bic     r0, r0, #(0x1 <<  2)        @ Clear C bit  2 to disable D Cache 
@@ -167,13 +118,17 @@
     mcr     p15, 0, r0, c1, c0, 0       @ Write value back to CP15 System Control register 
     isb
 
-@ Set Vector Base Address Register (VBAR) to point to this application's vector table
+    @ Configure ACTLR
+    MRC     p15, 0, r0, c1, c0, 1       @ Read CP15 Auxiliary Control Register
+    ORR     r0, r0, #(1 <<  1)          @ Enable L2 prefetch hint (UNK/WI since r4p1)
+    MCR     p15, 0, r0, c1, c0, 1       @ Write CP15 Auxiliary Control Register
+
+    @ Set Vector Base Address Register (VBAR) to point to this application's vector table
     ldr     r0, =__isr_vector
     mcr     p15, 0, r0, c12, c0, 0
  
 @ Setup Stack for each exceptional mode 
-/*    ldr     r0, =__StackTop  */
-    ldr     r0, =(__StackTop - USR_Stack_Size)
+    ldr     r0, =__StackTop
 
 @ Enter Undefined Instruction Mode and set its Stack Pointer 
     msr     cpsr_c, #(Mode_UND | I_Bit | F_Bit)
@@ -203,23 +158,12 @@
     msr     cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
     mov     sp, r0 
 
-    isb
-    ldr     r0, =RZ_A1_SetSramWriteEnable
-    blx     r0
-
-    .extern  create_translation_table
-    bl      create_translation_table 
-
 @  USR/SYS stack pointer will be set during kernel init
     ldr     r0, =SystemInit
     blx     r0
-    ldr     r0, =InitMemorySubsystem
-    blx     r0
 
-@ fp_init
-    mov      r0, #0x3000000
-    vmsr     fpscr, r0
-
+    @ Unmask interrupts
+    CPSIE  if
 
 @ data sections copy
     ldr     r4, =__copy_table_start__
@@ -282,214 +226,6 @@
 
     .text
 
-Undef_Handler:
-                .global Undef_Handler
-                .func   Undef_Handler
-                .extern CUndefHandler
-                SRSDB   SP!, #Mode_UND
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to UND mode stack */
-
-                MRS     R0, SPSR
-                TST     R0, #T_Bit                /* Check mode */
-                MOVEQ   R1, #4                    /* R1 = 4 ARM mode */
-                MOVNE   R1, #2                    /* R1 = 2 Thumb mode */
-                SUB     R0, LR, R1
-                LDREQ   R0, [R0]                  /* ARM mode - R0 points to offending instruction */
-                BEQ     undef_cont
-
-                /* Thumb instruction */
-                /* Determine if it is a 32-bit Thumb instruction */
-                LDRH    R0, [R0]
-                MOV     R2, #0x1c
-                CMP     R2, R0, LSR #11
-                BHS     undef_cont                /* 16-bit Thumb instruction */
-
-                /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
-                LDRH    R2, [LR]
-                ORR     R0, R2, R0, LSL #16
-undef_cont:
-                MOV     R2, LR                    /* Set LR to third argument */
-                
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                /* R0 Offending instruction */
-                /* R1 =2 (Thumb) or =4 (ARM) */
-                BL      CUndefHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                LDR     LR, [SP, #24]             /* Restore stacked LR and possibly adjust for retry */
-                SUB     LR, LR, R0
-                LDR     R0, [SP, #28]             /* Restore stacked SPSR */
-                MSR     SPSR_cxsf, R0
-                POP     {R0-R4, R12}              /* Restore stacked APCS registers */
-                ADD     SP, SP, #8                /* Adjust SP for already-restored banked registers */
-                MOVS    PC, LR
-                .endfunc
- 
-PAbt_Handler:
-                .global PAbt_Handler
-                .func   PAbt_Handler
-                .extern CPAbtHandler
-                SUB     LR, LR, #4                /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
-                MRC     p15, 0, R0, c5, c0, 1     /* IFSR */
-                MRC     p15, 0, R1, c6, c0, 2     /* IFAR */
-
-                MOV     R2, LR                    /* Set LR to third argument */
-
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                BL      CPAbtHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                POP     {R0-R4, R12}              /* Restore stack APCS registers */
-                RFEFD   SP!                       /* Return from exception */
-                .endfunc
-
-DAbt_Handler:
-                .global DAbt_Handler
-                .func   DAbt_Handler
-                .extern CDAbtHandler
-                SUB     LR, LR, #8                /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
-                CLREX                             /* State of exclusive monitors unknown after taken data abort */
-                MRC     p15, 0, R0, c5, c0, 0     /* DFSR */
-                MRC     p15, 0, R1, c6, c0, 0     /* DFAR */
-
-                MOV     R2, LR                    /* Set LR to third argument */
-
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                BL      CDAbtHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                POP     {R0-R4, R12}              /* Restore stacked APCS registers */
-                RFEFD   SP!                       /* Return from exception */
-                .endfunc
- 
-FIQ_Handler:
-                .global FIQ_Handler
-                .func   FIQ_Handler
-                /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
-                 * so if a real FIQ Handler is implemented, this will be needed before returning:
-                 */
-                /* LDR     R1, =GICI_BASE
-                   LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
-                 */
-                B       .
-                .endfunc
- 
-                .extern SVC_Handler                 /* refer RTX function */
-
-IRQ_Handler: 
-                .global IRQ_Handler
-                .func   IRQ_Handler
-                .extern IRQCount
-                .extern IRQTable
-                .extern IRQNestLevel
-
-                /* prologue */
-                SUB     LR, LR, #4                  /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_SVC              /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
-                CPS     #Mode_SVC                   /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
-                PUSH    {R0-R3, R12}                /* Save remaining APCS corruptible registers to SVC stack */
-
-/*              AND     R1, SP, #4 */               /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                      /* Ensure stack is 8-byte aligned */
-                AND     R1, R3, #4
-                SUB     SP, SP, R1                  /* Adjust stack */
-                PUSH    {R1, LR}                    /* Store stack adjustment and LR_SVC to SVC stack */
-
-                LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
-                LDR     R1, [R0]
-                ADD     R1, R1, #1                  /* Increment nesting counter */
-                STR     R1, [R0]
-
-                /* identify and acknowledge interrupt */
-                LDR     R1, =GICI_BASE
-                LDR     R0, [R1, #ICCHPIR_OFFSET]   /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
-                LDR     R0, [R1, #ICCIAR_OFFSET]    /* Read ICCIAR (GIC CPU Interface register) */
-                DSB                                 /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
-
-                /* Workaround GIC 390 errata 733075
-                 * If the ID is not 0, then service the interrupt as normal.
-                 * If the ID is 0 and active, then service interrupt ID 0 as normal.
-                 * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
-                 *   with a dummy write to ICDIPR0.  This interrupt should be treated as spurious and not serviced.
-                 */
-                LDR     R2, =GICD_BASE
-                LDR     R3, =GIC_ERRATA_CHECK_1
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                LDR     R3, =GIC_ERRATA_CHECK_2
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                CMP     R0, #0
-                BNE     int_active                  /* If the ID is not 0, then service the interrupt */
-                LDR     R3, [R2, #ICDABR0_OFFSET]   /* Get the interrupt state */
-                TST     R3, #1
-                BNE     int_active                  /* If active, then service the interrupt */
-unlock_cpu:
-                LDR     R3, [R2, #ICDIPR0_OFFSET]   /* Not active, so unlock the CPU interface */
-                STR     R3, [R2, #ICDIPR0_OFFSET]   /*   with a dummy write */
-                DSB                                 /* Ensure the write completes before continuing */
-                B       ret_irq                     /* Do not service the spurious interrupt */
-                /* End workaround */
-
-int_active:
-                LDR     R2, =IRQCount               /* Read number of IRQs */
-                LDR     R2, [R2]
-                CMP     R0, R2                      /* Clean up and return if no handler */
-                BHS     ret_irq                     /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
-                LDR     R2, =IRQTable               /* Get address of handler */
-                LDR     R2, [R2, R0, LSL #2]
-                CMP     R2, #0                      /* Clean up and return if handler address is 0 */
-                BEQ     ret_irq
-                PUSH    {R0,R1}
-
-                CPSIE   i                           /* Now safe to re-enable interrupts */
-                BLX     R2                          /* Call handler. R0 will be IRQ number */
-                CPSID   i                           /* Disable interrupts again */
-
-                /* write EOIR (GIC CPU Interface register) */
-                POP     {R0,R1}
-                DSB                                 /* Ensure that interrupt source is cleared before we write the EOIR */
-ret_irq:
-                /* epilogue */
-                STR     R0, [R1, #ICCEOIR_OFFSET]
-
-                LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
-                LDR     R1, [R0]
-                SUB     R1, R1, #1                  /* Decrement nesting counter */
-                STR     R1, [R0]
-
-                POP     {R1, LR}                    /* Get stack adjustment and restore LR_SVC */
-                ADD     SP, SP, R1                  /* Unadjust stack */
-
-                POP     {R0-R3,R12}                 /* Restore stacked APCS registers */
-                RFEFD   SP!                         /* Return from exception */
-                .endfunc
-
 /*    Macro to define default handlers. Default handler
  *    will be weak symbol and just dead loops. They can be
  *    overwritten by other handlers */
@@ -503,30 +239,11 @@
                 .size    \handler_name, . - \handler_name
                 .endm
 
+                def_default_handler    Undef_Handler
                 def_default_handler    SVC_Handler
-
-
-/* User Initial Stack & Heap */
-
-                .ifdef __MICROLIB
-                
-                .global __initial_sp
-                .global __heap_base
-                .global __heap_limit
-
-                .else
-
-                .extern __use_two_region_memory
-                .global __user_initial_stackheap
-__user_initial_stackheap:
-
-                LDR     R0, =  __HeapBase
-                LDR     R1, =(__StackTop)
-                LDR     R2, = (__HeapBase +  Heap_Size)
-                LDR     R3, = (__StackTop - USR_Stack_Size)
-                BX      LR
-
-                .endif
-
+                def_default_handler    PAbt_Handler
+                def_default_handler    DAbt_Handler
+                def_default_handler    IRQ_Handler
+                def_default_handler    FIQ_Handler
 
                 .END

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.s	Wed Jan 17 15:23:54 2018 +0000
@@ -29,30 +29,21 @@
 
         SECTION .intvec:CODE:NOROOT(2)
 
-        PUBLIC  __vector_core_a9
+        PUBLIC  __vector_table
         PUBLIC  __RST_Handler
-        PUBLIC  Undefined_Handler
-        EXTERN  SWI_Handler
-        PUBLIC  Prefetch_Handler
-        PUBLIC  Abort_Handler
-        PUBLIC  IRQ_Handler
+        EXTERN  Undef_Handler
+        EXTERN  SVC_Handler
+        EXTERN  PAbt_Handler
+        EXTERN  DAbt_Handler
+        EXTERN  IRQ_Handler
         PUBLIC  FIQ_Handler
-        EXTERN  VbarInit
-        EXTERN  SetLowVectors
-        EXTERN  init_TTB
-        EXTERN  enable_mmu
-        EXTERN  Peripheral_BasicInit
-        EXTERN  initsct
-        EXTERN  PowerON_Reset
-        PUBLIC  FPUEnable
-        
 
         DATA
 
 __iar_init$$done:               ; The vector table is not needed
                                 ; until after copy initialization is done
 
-__vector_core_a9:               ; Make this a DATA label, so that stack usage
+__vector_table:                 ; Make this a DATA label, so that stack usage
                                 ; analysis doesn't consider it an uncalled fun
 
         ARM
@@ -72,10 +63,10 @@
         DATA
 
 Reset_Addr:     DCD   __RST_Handler
-Undefined_Addr: DCD   Undefined_Handler
-SWI_Addr:       DCD   SWI_Handler
-Prefetch_Addr:  DCD   Prefetch_Handler
-Abort_Addr:     DCD   Abort_Handler
+Undefined_Addr: DCD   Undef_Handler
+SWI_Addr:       DCD   SVC_Handler
+Prefetch_Addr:  DCD   PAbt_Handler
+Abort_Addr:     DCD   DAbt_Handler
 IRQ_Addr:       DCD   IRQ_Handler
 FIQ_Addr:       DCD   FIQ_Handler
 
@@ -90,12 +81,9 @@
 
 
         SECTION .text:CODE:NOROOT(2)
-        EXTERN  RZ_A1_SetSramWriteEnable
-        EXTERN  create_translation_table
         EXTERN  SystemInit
-        EXTERN  InitMemorySubsystem
         EXTERN  __iar_program_start
-        REQUIRE __vector_core_a9
+        REQUIRE __vector_table
         EXTWEAK __iar_init_core
         EXTWEAK __iar_init_vfp
 
@@ -105,28 +93,18 @@
 __RST_Handler:
 ?cstartup:
 
+;;;    @ Mask interrupts
+    CPSID   if   
 
 ;;;    @ Put any cores other than 0 to sleep
     mrc     p15, 0, r0, c0, c0, 5   ;;; @ Read MPIDR
     ands    r0, r0, #3
-    
+
 goToSleep:
     wfine
     bne     goToSleep
 
-
-//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. 
-//@ Enables Full Access i.e. in both privileged and non privileged modes 
-    mrc     p15, 0, r0, c1, c0, 2       ;@ Read Coprocessor Access Control Register (CPACR) 
-    orr     r0, r0, #(0xF << 20)        ;@ Enable access to CP 10 & 11 
-    mcr     p15, 0, r0, c1, c0, 2       ;@ Write Coprocessor Access Control Register (CPACR) 
-    isb
-   
-   
-;; Switch on the VFP and NEON hardware 
-    mov     r0, #0x40000000
-    vmsr    fpexc, r0                   ;@ Write FPEXC register, EN bit set 
-
+;;;    @ Reset SCTLR Settings
     mrc     p15, 0, r0, c1, c0, 0       ;@ Read CP15 System Control register 
     bic     r0, r0, #(0x1 << 12)        ;@ Clear I bit 12 to disable I Cache 
     bic     r0, r0, #(0x1 <<  2)        ;@ Clear C bit  2 to disable D Cache 
@@ -135,10 +113,14 @@
     bic     r0, r0, #(0x1 << 13)        ;@ Clear V bit 13 to disable hivecs 
     mcr     p15, 0, r0, c1, c0, 0       ;@ Write value back to CP15 System Control register 
     isb
-  
-  
+
+;;;    @ Configure ACTLR
+    MRC     p15, 0, r0, c1, c0, 1       ;@ Read CP15 Auxiliary Control Register
+    ORR     r0, r0, #(1 <<  1)          ;@ Enable L2 prefetch hint (UNK/WI since r4p1)
+    MCR     p15, 0, r0, c1, c0, 1       ;@ Write CP15 Auxiliary Control Register
+
 ;; Set Vector Base Address Register (VBAR) to point to this application's vector table
-    ldr     r0, =__vector_core_a9
+    ldr     r0, =__vector_table
     mcr     p15, 0, r0, c12, c0, 0
     
     
@@ -169,20 +151,6 @@
 #define UND_MODE 0x1B            ; Undefined Instruction mode
 #define SYS_MODE 0x1F            ; System mode
 
-#define Mode_SVC  0x13
-#define Mode_ABT  0x17
-#define Mode_UND  0x1B
-#define GICI_BASE 0xe8202000
-#define ICCIAR_OFFSET   0x0000000C
-#define ICCEOIR_OFFSET  0x00000010
-#define ICCHPIR_OFFSET  0x00000018
-#define GICD_BASE       0xe8201000
-#define GIC_ERRATA_CHECK_1 0x000003FE 
-#define GIC_ERRATA_CHECK_2 0x000003FF 
-#define ICDABR0_OFFSET  0x00000300
-#define ICDIPR0_OFFSET  0x00000400
-#define T_Bit           0x20     ; when T bit is set, core is in Thumb state 
-
         MRS     r0, cpsr                ; Original PSR value
 
         ;; Set up the SVC stack pointer.        
@@ -235,24 +203,9 @@
         BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
 
 ;;;
-
-    isb
-    ldr     r0, =RZ_A1_SetSramWriteEnable
-    blx     r0
-
-    bl      create_translation_table 
-
 ;  USR/SYS stack pointer will be set during kernel init
     ldr     r0, =SystemInit
     blx     r0
-    ldr     r0, =InitMemorySubsystem
-    blx     r0
-
-; fp_init
-    mov      r0, #0x3000000
-    vmsr     fpscr, r0
-    
-    
 
 ;;; Continue to __cmain for C-level initialization.
 
@@ -267,239 +220,7 @@
 sf_boot: 
     DC32   0x00000001
 
-Undefined_Handler:
-                EXTERN CUndefHandler
-                SRSDB   SP!, #Mode_UND
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to UND mode stack */
-
-                MRS     R0, SPSR
-                TST     R0, #T_Bit                /* Check mode */
-                MOVEQ   R1, #4                    /* R1 = 4 ARM mode */
-                MOVNE   R1, #2                    /* R1 = 2 Thumb mode */
-                SUB     R0, LR, R1
-                LDREQ   R0, [R0]                  /* ARM mode - R0 points to offending instruction */
-                BEQ     undef_cont
-
-                /* Thumb instruction */
-                /* Determine if it is a 32-bit Thumb instruction */
-                LDRH    R0, [R0]
-                MOV     R2, #0x1c
-                CMP     R2, R0, LSR #11
-                BHS     undef_cont                /* 16-bit Thumb instruction */
-
-                /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
-                LDRH    R2, [LR]
-                ORR     R0, R2, R0, LSL #16
-undef_cont:
-                MOV     R2, LR                    /* Set LR to third argument */
-                
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                /* R0 Offending instruction */
-                /* R1 =2 (Thumb) or =4 (ARM) */
-                BL      CUndefHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                LDR     LR, [SP, #24]             /* Restore stacked LR and possibly adjust for retry */
-                SUB     LR, LR, R0
-                LDR     R0, [SP, #28]             /* Restore stacked SPSR */
-                MSR     SPSR_cxsf, R0
-                POP     {R0-R4, R12}              /* Restore stacked APCS registers */
-                ADD     SP, SP, #8                /* Adjust SP for already-restored banked registers */
-                MOVS    PC, LR
- 
-Prefetch_Handler:
-                EXTERN CPAbtHandler
-                SUB     LR, LR, #4                /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
-                MRC     p15, 0, R0, c5, c0, 1     /* IFSR */
-                MRC     p15, 0, R1, c6, c0, 2     /* IFAR */
-
-                MOV     R2, LR                    /* Set LR to third argument */
-
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                BL      CPAbtHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                POP     {R0-R4, R12}              /* Restore stack APCS registers */
-                RFEFD   SP!                       /* Return from exception */
-
-Abort_Handler:
-                EXTERN CDAbtHandler
-                SUB     LR, LR, #8                /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
-                CLREX                             /* State of exclusive monitors unknown after taken data abort */
-                MRC     p15, 0, R0, c5, c0, 0     /* DFSR */
-                MRC     p15, 0, R1, c6, c0, 0     /* DFAR */
-
-                MOV     R2, LR                    /* Set LR to third argument */
-
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                BL      CDAbtHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                POP     {R0-R4, R12}              /* Restore stacked APCS registers */
-                RFEFD   SP!                       /* Return from exception */
-
 FIQ_Handler:
-    /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
-     * so if a real FIQ Handler is implemented, this will be needed before returning:
-     */
-    /* LDR     R1, =GICI_BASE
-    LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
-     */
     B       .
  
-    EXTERN SVC_Handler                 /* refer RTX function */
-
-IRQ_Handler: 
-                EXTERN IRQCount
-                EXTERN IRQTable
-                EXTERN IRQNestLevel
-
-                /* prologue */
-                SUB     LR, LR, #4                  /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_SVC              /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
-                CPS     #Mode_SVC                   /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
-                PUSH    {R0-R3, R12}                /* Save remaining APCS corruptible registers to SVC stack */
-
-/*              AND     R1, SP, #4 */               /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                      /* Ensure stack is 8-byte aligned */
-                AND     R1, R3, #4
-                SUB     SP, SP, R1                  /* Adjust stack */
-                PUSH    {R1, LR}                    /* Store stack adjustment and LR_SVC to SVC stack */
-
-                LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
-                LDR     R1, [R0]
-                ADD     R1, R1, #1                  /* Increment nesting counter */
-                STR     R1, [R0]
-
-                /* identify and acknowledge interrupt */
-                LDR     R1, =GICI_BASE
-                LDR     R0, [R1, #ICCHPIR_OFFSET]   /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
-                LDR     R0, [R1, #ICCIAR_OFFSET]    /* Read ICCIAR (GIC CPU Interface register) */
-                DSB                                 /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
-
-                /* Workaround GIC 390 errata 733075
-                 * If the ID is not 0, then service the interrupt as normal.
-                 * If the ID is 0 and active, then service interrupt ID 0 as normal.
-                 * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
-                 *   with a dummy write to ICDIPR0.  This interrupt should be treated as spurious and not serviced.
-                 */
-                LDR     R2, =GICD_BASE
-                LDR     R3, =GIC_ERRATA_CHECK_1
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                LDR     R3, =GIC_ERRATA_CHECK_2
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                CMP     R0, #0
-                BNE     int_active                  /* If the ID is not 0, then service the interrupt */
-                LDR     R3, [R2, #ICDABR0_OFFSET]   /* Get the interrupt state */
-                TST     R3, #1
-                BNE     int_active                  /* If active, then service the interrupt */
-unlock_cpu:
-                LDR     R3, [R2, #ICDIPR0_OFFSET]   /* Not active, so unlock the CPU interface */
-                STR     R3, [R2, #ICDIPR0_OFFSET]   /*   with a dummy write */
-                DSB                                 /* Ensure the write completes before continuing */
-                B       ret_irq                     /* Do not service the spurious interrupt */
-                /* End workaround */
-
-int_active:
-                LDR     R2, =IRQCount               /* Read number of IRQs */
-                LDR     R2, [R2]
-                CMP     R0, R2                      /* Clean up and return if no handler */
-                BHS     ret_irq                     /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
-                LDR     R2, =IRQTable               /* Get address of handler */
-                LDR     R2, [R2, R0, LSL #2]
-                CMP     R2, #0                      /* Clean up and return if handler address is 0 */
-                BEQ     ret_irq
-                PUSH    {R0,R1}
-
-                CPSIE   i                           /* Now safe to re-enable interrupts */
-                BLX     R2                          /* Call handler. R0 will be IRQ number */
-                CPSID   i                           /* Disable interrupts again */
-
-                /* write EOIR (GIC CPU Interface register) */
-                POP     {R0,R1}
-                DSB                                 /* Ensure that interrupt source is cleared before we write the EOIR */
-ret_irq:
-                /* epilogue */
-                STR     R0, [R1, #ICCEOIR_OFFSET]
-
-                LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
-                LDR     R1, [R0]
-                SUB     R1, R1, #1                  /* Decrement nesting counter */
-                STR     R1, [R0]
-
-                POP     {R1, LR}                    /* Get stack adjustment and restore LR_SVC */
-                ADD     SP, SP, R1                  /* Unadjust stack */
-
-                POP     {R0-R3,R12}                 /* Restore stacked APCS registers */
-                RFEFD   SP!                         /* Return from exception */
-;;;
-;;; Add more initialization here
-;;;
-FPUEnable:
-        ARM
-
-        //Permit access to VFP registers by modifying CPACR
-        MRC     p15,0,R1,c1,c0,2
-        ORR     R1,R1,#0x00F00000
-        MCR     p15,0,R1,c1,c0,2
-
-        //Enable VFP
-        VMRS    R1,FPEXC
-        ORR     R1,R1,#0x40000000
-        VMSR    FPEXC,R1
-
-        //Initialise VFP registers to 0
-        MOV     R2,#0
-        VMOV    D0, R2,R2
-        VMOV    D1, R2,R2
-        VMOV    D2, R2,R2
-        VMOV    D3, R2,R2
-        VMOV    D4, R2,R2
-        VMOV    D5, R2,R2
-        VMOV    D6, R2,R2
-        VMOV    D7, R2,R2
-        VMOV    D8, R2,R2
-        VMOV    D9, R2,R2
-        VMOV    D10,R2,R2
-        VMOV    D11,R2,R2
-        VMOV    D12,R2,R2
-        VMOV    D13,R2,R2
-        VMOV    D14,R2,R2
-        VMOV    D15,R2,R2
-
-        //Initialise FPSCR to a known state
-        VMRS    R2,FPSCR
-        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-        AND     R2,R2,R3
-        VMSR    FPSCR,R2
-
-        BX      LR
-
   END

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.c	Wed Jan 17 15:23:54 2018 +0000
@@ -29,14 +29,13 @@
  *******************************************************************************
  */
 #include "MBRZA1H.h"
-
-extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
+#include "irq_ctrl.h"
 
 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
     InterruptHandlerRegister(IRQn, (IRQHandler)vector);
 }
 
 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t vectors = (uint32_t)IRQTable[IRQn];
+    uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn);
     return vectors;
 }

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,305 +0,0 @@
-/**************************************************************************//**
- * @file     gic.c
- * @brief    Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date     19 Sept 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#include "MBRZA1H.h"
-
-#define GICDistributor      ((GICDistributor_Type      *)     Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
-#define GICInterface        ((GICInterface_Type        *)     Renesas_RZ_A1_GIC_INTERFACE_BASE )   /*!< GIC Interface configuration struct */
-
-/* Globals for use of post-scatterloading code that must access GIC */
-const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE;
-const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE;
-
-void GIC_EnableDistributor(void)
-{
-    GICDistributor->ICDDCR |= 1; //enable distributor
-}
-
-void GIC_DisableDistributor(void)
-{
-    GICDistributor->ICDDCR &=~1; //disable distributor
-}
-
-uint32_t GIC_DistributorInfo(void)
-{
-    return (uint32_t)(GICDistributor->ICDICTR);
-}
-
-uint32_t GIC_DistributorImplementer(void)
-{
-    return (uint32_t)(GICDistributor->ICDIIDR);
-}
-
-void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
-{
-    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
-    field += IRQn % 4;
-    *field = (uint8_t)cpu_target & 0xf;
-}
-
-void GIC_SetICDICFR (const uint32_t *ICDICFRn)
-{
-    uint32_t i, num_irq;
-
-    //Get the maximum number of interrupts that the GIC supports
-    num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
-
-    for (i = 0; i < (num_irq/16); i++)
-    {
-        GICDistributor->ICDISPR[i] = *ICDICFRn++;
-    }
-}
-
-uint32_t GIC_GetTarget(IRQn_Type IRQn)
-{
-    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
-    field += IRQn % 4;
-    return ((uint32_t)*field & 0xf);
-}
-
-void GIC_EnableInterface(void)
-{
-    GICInterface->ICCICR |= 1; //enable interface
-}
-
-void GIC_DisableInterface(void)
-{
-    GICInterface->ICCICR &=~1; //disable distributor
-}
-
-IRQn_Type GIC_AcknowledgePending(void)
-{
-    return (IRQn_Type)(GICInterface->ICCIAR);
-}
-
-void GIC_EndInterrupt(IRQn_Type IRQn)
-{
-    GICInterface->ICCEOIR = IRQn;
-}
-
-void GIC_EnableIRQ(IRQn_Type IRQn)
-{
-    GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-void GIC_DisableIRQ(IRQn_Type IRQn)
-{
-    GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-void GIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-void GIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
-{
-    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]);
-    int  bit_shift = (IRQn % 16)<<1;
-    uint8_t save_byte;
-
-    field += (bit_shift / 8);
-    bit_shift %= 8;
-
-    save_byte = *field;
-    save_byte &= ((uint8_t)~(3u << bit_shift));
-
-    *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift);
-}
-
-void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
-    field += (IRQn % 4);
-    *field = (uint8_t)priority;
-}
-
-uint32_t GIC_GetPriority(IRQn_Type IRQn)
-{
-    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
-    field += (IRQn % 4);
-    return (uint32_t)*field;
-}
-
-void GIC_InterfacePriorityMask(uint32_t priority)
-{
-    GICInterface->ICCPMR = priority & 0xff; //set priority mask
-}
-
-void GIC_SetBinaryPoint(uint32_t binary_point)
-{
-    GICInterface->ICCBPR = binary_point & 0x07; //set binary point
-}
-
-uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
-{
-    return (uint32_t)GICInterface->ICCBPR;
-}
-
-uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
-{
-    uint32_t pending, active;
-
-    active = ((GICDistributor->ICDABR[IRQn / 32])  >> (IRQn % 32)) & 0x1;
-    pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
-
-    return ((active<<1) | pending);
-}
-
-void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
-{
-    GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
-}
-
-void GIC_DistInit(void)
-{
-    //IRQn_Type i;
-    uint32_t i;
-    uint32_t num_irq = 0;
-    uint32_t priority_field;
-
-    //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
-    //configuring all of the interrupts as Secure.
-
-    //Disable interrupt forwarding
-    GIC_DisableDistributor();
-    //Get the maximum number of interrupts that the GIC supports
-    num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
-
-    /* Priority level is implementation defined.
-     To determine the number of priority bits implemented write 0xFF to an ICDIPR
-     priority field and read back the value stored.*/
-    GIC_SetPriority((IRQn_Type)0, 0xff);
-    priority_field = GIC_GetPriority((IRQn_Type)0);
-
-    for (i = 32; i < num_irq; i++)
-    {
-        //Disable all SPI the interrupts
-        GIC_DisableIRQ((IRQn_Type)i);
-        //Set level-sensitive and N-N model
-        //GIC_SetLevelModel(i, 0, 0);
-        //Set priority
-        GIC_SetPriority((IRQn_Type)i, priority_field/2);
-        //Set target list to "all cpus"
-        GIC_SetTarget((IRQn_Type)i, 0xff);
-    }
-    /* Set level-edge and 1-N model */
-    /* GICDistributor->ICDICFR[ 0] is read only */
-    GICDistributor->ICDICFR[ 1] = 0x00000055;
-    GICDistributor->ICDICFR[ 2] = 0xFFFD5555;
-    GICDistributor->ICDICFR[ 3] = 0x555FFFFF;
-    GICDistributor->ICDICFR[ 4] = 0x55555555;
-    GICDistributor->ICDICFR[ 5] = 0x55555555;
-    GICDistributor->ICDICFR[ 6] = 0x55555555;
-    GICDistributor->ICDICFR[ 7] = 0x55555555;
-    GICDistributor->ICDICFR[ 8] = 0x5555F555;
-    GICDistributor->ICDICFR[ 9] = 0x55555555;
-    GICDistributor->ICDICFR[10] = 0x55555555;
-    GICDistributor->ICDICFR[11] = 0xF5555555;
-    GICDistributor->ICDICFR[12] = 0xF555F555;
-    GICDistributor->ICDICFR[13] = 0x5555F555;
-    GICDistributor->ICDICFR[14] = 0x55555555;
-    GICDistributor->ICDICFR[15] = 0x55555555;
-    GICDistributor->ICDICFR[16] = 0x55555555;
-    GICDistributor->ICDICFR[17] = 0xFD555555;
-    GICDistributor->ICDICFR[18] = 0x55555557;
-    GICDistributor->ICDICFR[19] = 0x55555555;
-    GICDistributor->ICDICFR[20] = 0xFFD55555;
-    GICDistributor->ICDICFR[21] = 0x5F55557F;
-    GICDistributor->ICDICFR[22] = 0xFD55555F;
-    GICDistributor->ICDICFR[23] = 0x55555557;
-    GICDistributor->ICDICFR[24] = 0x55555555;
-    GICDistributor->ICDICFR[25] = 0x55555555;
-    GICDistributor->ICDICFR[26] = 0x55555555;
-    GICDistributor->ICDICFR[27] = 0x55555555;
-    GICDistributor->ICDICFR[28] = 0x55555555;
-    GICDistributor->ICDICFR[29] = 0x55555555;
-    GICDistributor->ICDICFR[30] = 0x55555555;
-    GICDistributor->ICDICFR[31] = 0x55555555;
-    GICDistributor->ICDICFR[32] = 0x55555555;
-    GICDistributor->ICDICFR[33] = 0x55555555;
-
-    //Enable distributor
-    GIC_EnableDistributor();
-}
-
-void GIC_CPUInterfaceInit(void)
-{
-    IRQn_Type i;
-    uint32_t priority_field;
-
-    //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
-    //configuring all of the interrupts as Secure.
-
-    //Disable interrupt forwarding
-    GIC_DisableInterface();
-
-    /* Priority level is implementation defined.
-     To determine the number of priority bits implemented write 0xFF to an ICDIPR
-     priority field and read back the value stored.*/
-    GIC_SetPriority((IRQn_Type)0, 0xff);
-    priority_field = GIC_GetPriority((IRQn_Type)0);
-
-    //SGI and PPI
-    for (i = (IRQn_Type)0; i < 32; i++)
-    {
-        //Set level-sensitive and N-N model for PPI
-        //if(i > 15)
-            //GIC_SetLevelModel(i, 0, 0);
-        //Disable SGI and PPI interrupts
-        GIC_DisableIRQ(i);
-        //Set priority
-        GIC_SetPriority(i, priority_field/2);
-    }
-    //Enable interface
-    GIC_EnableInterface();
-    //Set binary point to 0
-    GIC_SetBinaryPoint(0);
-    //Set priority mask
-    GIC_InterfacePriorityMask(0xff);
-}
-
-void GIC_Enable(void)
-{
-    GIC_DistInit();
-    GIC_CPUInterfaceInit(); //per CPU
-}
-

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,316 +0,0 @@
-/**************************************************************************//**
- * @file     gic.h
- * @brief    Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date     29 August 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#ifndef GIC_H_
-#define GIC_H_
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/** \brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)
- */
-typedef struct
-{
-  __IO uint32_t ICDDCR;
-  __I  uint32_t ICDICTR;
-  __I  uint32_t ICDIIDR;
-       uint32_t RESERVED0[29];
-  __IO uint32_t ICDISR[32];
-  __IO uint32_t ICDISER[32];
-  __IO uint32_t ICDICER[32];
-  __IO uint32_t ICDISPR[32];
-  __IO uint32_t ICDICPR[32];
-  __I  uint32_t ICDABR[32];
-       uint32_t RESERVED1[32];
-  __IO uint32_t ICDIPR[256];
-  __IO uint32_t ICDIPTR[256];
-  __IO uint32_t ICDICFR[64];
-       uint32_t RESERVED2[128];
-  __IO uint32_t ICDSGIR;
-}  GICDistributor_Type;
-
-/** \brief  Structure type to access the Controller Interface (GICC)
- */
-typedef struct
-{
-  __IO uint32_t ICCICR;          // +0x000 - RW - CPU Interface Control Register
-  __IO uint32_t ICCPMR;          // +0x004 - RW - Interrupt Priority Mask Register
-  __IO uint32_t ICCBPR;          // +0x008 - RW - Binary Point Register
-  __I  uint32_t ICCIAR;          // +0x00C - RO - Interrupt Acknowledge Register
-  __IO uint32_t ICCEOIR;         // +0x010 - WO - End of Interrupt Register
-  __I  uint32_t ICCRPR;          // +0x014 - RO - Running Priority Register
-  __I  uint32_t ICCHPIR;         // +0x018 - RO - Highest Pending Interrupt Register
-  __IO uint32_t ICCABPR;         // +0x01C - RW - Aliased Binary Point Register
-
-       uint32_t RESERVED[55];
-
-  __I  uint32_t ICCIIDR;         // +0x0FC - RO - CPU Interface Identification Register
-}  GICInterface_Type;
-
-/*@} end of GICD */
-
-/* ##########################   GIC functions  #################################### */
-/**  \brief      Functions that manage interrupts via the GIC.
-  @{
- */
-
-/** \brief  Enable DistributorGICInterface->ICCICR |= 1; //enable interface
-
-   Enables the forwarding of pending interrupts to the CPU interfaces.
-
- */
-void GIC_EnableDistributor(void);
-
-/** \brief  Disable Distributor
-
-   Disables the forwarding of pending interrupts to the CPU interfaces.
-
- */
-void GIC_DisableDistributor(void);
-
-/** \brief  Provides information about the configuration of the GIC.
-   Provides information about the configuration of the GIC.
-   - whether the GIC implements the Security Extensions
-   - the maximum number of interrupt IDs that the GIC supports
-   - the number of CPU interfaces implemented
-   - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
-
-   \return Distributor Information.
- */
-uint32_t GIC_DistributorInfo(void);
-
-/** \brief  Distributor Implementer Identification Register.
-
-   Distributor Implementer Identification Register
-
-   \return Implementer Information.
- */
-uint32_t GIC_DistributorImplementer(void);
-
-/** \brief  Set list of processors that the interrupt is sent to if it is asserted.
-
-    The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
-    This field stores the list of processors that the interrupt is sent to if it is asserted.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]    target  CPU target
- */
-void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
-
-/** \brief  Get list of processors that the interrupt is sent to if it is asserted.
-
-    The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
-    This field stores the list of processors that the interrupt is sent to if it is asserted.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]    target  CPU target
-*/
-uint32_t GIC_GetTarget(IRQn_Type IRQn);
-
-/** \brief  Enable Interface
-
-   Enables the signalling of interrupts to the target processors.
-
- */
-void GIC_EnableInterface(void);
-
-/** \brief  Disable Interface
-
-   Disables the signalling of interrupts to the target processors.
-
- */
-void GIC_DisableInterface(void);
-
-/** \brief  Acknowledge Interrupt
-
-    The function acknowledges the highest priority pending interrupt and returns its IRQ number.
-
-    \return             Interrupt number
- */
-IRQn_Type GIC_AcknowledgePending(void);
-
-/** \brief  End Interrupt
-
-    The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
-
-    \param [in]   IRQn  Interrupt number.
- */
-void GIC_EndInterrupt(IRQn_Type IRQn);
-
-
-/** \brief  Enable Interrupt
-
-    Set-enable bit for each interrupt supported by the GIC.
-
-    \param [in]      IRQn  External interrupt number.
- */
-void GIC_EnableIRQ(IRQn_Type IRQn);
-
-/** \brief  Disable Interrupt
-
-    Clear-enable bit for each interrupt supported by the GIC.
-
-    \param [in]      IRQn  Number of the external interrupt to disable
- */
-void GIC_DisableIRQ(IRQn_Type IRQn);
-
-/** \brief  Set Pending Interrupt
-
-    Set-pending bit for each interrupt supported by the GIC.
-
-    \param [in]      IRQn  Interrupt number.
- */
-void GIC_SetPendingIRQ(IRQn_Type IRQn);
-
-/** \brief  Clear Pending Interrupt
-
-    Clear-pending bit for each interrupt supported by the GIC
-
-    \param [in]      IRQn  Number of the interrupt for clear pending
- */
-void GIC_ClearPendingIRQ(IRQn_Type IRQn);
-
-/** \brief  Int_config field for each interrupt supported by the GIC.
-
-    This field identifies whether the corresponding interrupt is:
-    (1) edge-triggered or (0) level-sensitive
-    (1) 1-N model or (0) N-N model
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in] edge_level (1) edge-triggered or (0) level-sensitive
-    \param [in] model      (1) 1-N model or (0) N-N model
- */
-void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt.
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority.
- */
-uint32_t GIC_GetPriority(IRQn_Type IRQn);
-
-/** \brief  CPU Interface Priority Mask Register
-
-    The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
-    value indicated by this field, the interface signals the interrupt to the processor.
-
-    \param [in]   Mask.
- */
-void GIC_InterfacePriorityMask(uint32_t priority);
-
-/** \brief  Set the binary point.
-
-     Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
-
-    \param [in]   Mask.
- */
-void GIC_SetBinaryPoint(uint32_t binary_point);
-
-/** \brief  Get the binary point.
-
-     Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
-
-    \return  Binary point.
- */
-uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
-
-/** \brief  Get Interrupt state.
-
-     Get the interrupt state, whether pending and/or active
-
-    \return  0 - inactive, 1 - pending, 2 - active, 3 - pending and active
- */
-uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
-
-/** \brief  Send Software Generated interrupt
-
-    Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
-GIC_InterfacePriorityMask
-    \param [in]   IRQn         The Interrupt ID of the SGI.
-    \param [in]   target_list  CPUTargetList
-    \param [in]   filter_list  TargetListFilter
- */
-void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
-
-/** \brief  API call to initialise the interrupt distributor
-
-   API call to initialise the interrupt distributor
-
- */
-void GIC_DistInit(void);
-
-/** \brief  API call to initialise the CPU interface
-
-   API call to initialise the CPU interface
-
- */
-void GIC_CPUInterfaceInit(void);
-
-/** \brief  API call to set the Interrupt Configuration Registers
-
-   API call to initialise the Interrupt Configuration Registers
-
- */
-void GIC_SetICDICFR (const uint32_t *ICDICFRn);
-
-/** \brief  API call to  Enable the GIC
-
-   API call to  Enable the GIC
-
- */
-void GIC_Enable(void);
-
-#endif /* GIC_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/RZ_A1H.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,921 @@
+/******************************************************************************
+ * @file     RZ_A1H.h
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File 
+ * @version  V1.00
+ * @data     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __RZ_A1H_H__
+#define __RZ_A1H_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+/******  SGI Interrupts Numbers                 ****************************************/
+  SGI0_IRQn            =  0,
+  SGI1_IRQn            =  1,
+  SGI2_IRQn            =  2,
+  SGI3_IRQn            =  3,
+  SGI4_IRQn            =  4,
+  SGI5_IRQn            =  5,
+  SGI6_IRQn            =  6,
+  SGI7_IRQn            =  7,
+  SGI8_IRQn            =  8,
+  SGI9_IRQn            =  9,
+  SGI10_IRQn           = 10,
+  SGI11_IRQn           = 11,
+  SGI12_IRQn           = 12,
+  SGI13_IRQn           = 13,
+  SGI14_IRQn           = 14,
+  SGI15_IRQn           = 15,
+
+/******  Cortex-A9 Processor Exceptions Numbers ****************************************/
+  /* 16 - 578 */
+  PMUIRQ0_IRQn         = 16,
+  COMMRX0_IRQn         = 17,
+  COMMTX0_IRQn         = 18,
+  CTIIRQ0_IRQn         = 19,
+
+  IRQ0_IRQn            = 32,
+  IRQ1_IRQn            = 33,
+  IRQ2_IRQn            = 34,
+  IRQ3_IRQn            = 35,
+  IRQ4_IRQn            = 36,
+  IRQ5_IRQn            = 37,
+  IRQ6_IRQn            = 38,
+  IRQ7_IRQn            = 39,
+
+  PL310ERR_IRQn        = 40,
+
+  DMAINT0_IRQn         = 41,        /*!< DMAC Interrupt         */
+  DMAINT1_IRQn         = 42,        /*!< DMAC Interrupt         */
+  DMAINT2_IRQn         = 43,        /*!< DMAC Interrupt         */
+  DMAINT3_IRQn         = 44,        /*!< DMAC Interrupt         */
+  DMAINT4_IRQn         = 45,        /*!< DMAC Interrupt         */
+  DMAINT5_IRQn         = 46,        /*!< DMAC Interrupt         */
+  DMAINT6_IRQn         = 47,        /*!< DMAC Interrupt         */
+  DMAINT7_IRQn         = 48,        /*!< DMAC Interrupt         */
+  DMAINT8_IRQn         = 49,        /*!< DMAC Interrupt         */
+  DMAINT9_IRQn         = 50,        /*!< DMAC Interrupt         */
+  DMAINT10_IRQn        = 51,        /*!< DMAC Interrupt         */
+  DMAINT11_IRQn        = 52,        /*!< DMAC Interrupt         */
+  DMAINT12_IRQn        = 53,        /*!< DMAC Interrupt         */
+  DMAINT13_IRQn        = 54,        /*!< DMAC Interrupt         */
+  DMAINT14_IRQn        = 55,        /*!< DMAC Interrupt         */
+  DMAINT15_IRQn        = 56,        /*!< DMAC Interrupt         */
+  DMAERR_IRQn          = 57,        /*!< DMAC Interrupt         */
+
+  /* 58-72 Reserved */
+
+  USBI0_IRQn           = 73,
+  USBI1_IRQn           = 74,
+
+  S0_VI_VSYNC0_IRQn    = 75,
+  S0_LO_VSYNC0_IRQn    = 76,
+  S0_VSYNCERR0_IRQn    = 77,
+  GR3_VLINE0_IRQn      = 78,
+  S0_VFIELD0_IRQn      = 79,
+  IV1_VBUFERR0_IRQn    = 80,
+  IV3_VBUFERR0_IRQn    = 81,
+  IV5_VBUFERR0_IRQn    = 82,
+  IV6_VBUFERR0_IRQn    = 83,
+  S0_WLINE0_IRQn       = 84,
+  S1_VI_VSYNC0_IRQn    = 85,
+  S1_LO_VSYNC0_IRQn    = 86,
+  S1_VSYNCERR0_IRQn    = 87,
+  S1_VFIELD0_IRQn      = 88,
+  IV2_VBUFERR0_IRQn    = 89,
+  IV4_VBUFERR0_IRQn    = 90,
+  S1_WLINE0_IRQn       = 91,
+  OIR_VI_VSYNC0_IRQn   = 92,
+  OIR_LO_VSYNC0_IRQn   = 93,
+  OIR_VSYNCERR0_IRQn   = 94,
+  OIR_VFIELD0_IRQn     = 95,
+  IV7_VBUFERR0_IRQn    = 96,
+  IV8_VBUFERR0_IRQn    = 97,
+  /* 98 Reserved */
+  S0_VI_VSYNC1_IRQn    = 99,
+  S0_LO_VSYNC1_IRQn    = 100,
+  S0_VSYNCERR1_IRQn    = 101,
+  GR3_VLINE1_IRQn      = 102,
+  S0_VFIELD1_IRQn      = 103,
+  IV1_VBUFERR1_IRQn    = 104,
+  IV3_VBUFERR1_IRQn    = 105,
+  IV5_VBUFERR1_IRQn    = 106,
+  IV6_VBUFERR1_IRQn    = 107,
+  S0_WLINE1_IRQn       = 108,
+  S1_VI_VSYNC1_IRQn    = 109,
+  S1_LO_VSYNC1_IRQn    = 110,
+  S1_VSYNCERR1_IRQn    = 111,
+  S1_VFIELD1_IRQn      = 112,
+  IV2_VBUFERR1_IRQn    = 113,
+  IV4_VBUFERR1_IRQn    = 114,
+  S1_WLINE1_IRQn       = 115,
+  OIR_VI_VSYNC1_IRQn   = 116,
+  OIR_LO_VSYNC1_IRQn   = 117,
+  OIR_VSYNCERR1_IRQn   = 118,
+  OIR_VFIELD1_IRQn     = 119,
+  IV7_VBUFERR1_IRQn    = 120,
+  IV8_VBUFERR1_IRQn    = 121,
+  /* Reserved = 122 */
+
+  IMRDI_IRQn           = 123,
+  IMR2I0_IRQn          = 124,
+  IMR2I1_IRQn          = 125,
+
+  JEDI_IRQn            = 126,
+  JDTI_IRQn            = 127,
+
+  CMP0_IRQn            = 128,
+  CMP1_IRQn            = 129,
+
+  INT0_IRQn            = 130,
+  INT1_IRQn            = 131,
+  INT2_IRQn            = 132,
+  INT3_IRQn            = 133,
+
+  OSTMI0TINT_IRQn      = 134,       /*!< OSTM Interrupt         */
+  OSTMI1TINT_IRQn      = 135,       /*!< OSTM Interrupt         */
+
+  CMI_IRQn             = 136,
+  WTOUT_IRQn           = 137,
+
+  ITI_IRQn             = 138,
+
+  TGI0A_IRQn           = 139,
+  TGI0B_IRQn           = 140,
+  TGI0C_IRQn           = 141,
+  TGI0D_IRQn           = 142,
+  TGI0V_IRQn           = 143,
+  TGI0E_IRQn           = 144,
+  TGI0F_IRQn           = 145,
+  TGI1A_IRQn           = 146,
+  TGI1B_IRQn           = 147,
+  TGI1V_IRQn           = 148,
+  TGI1U_IRQn           = 149,
+  TGI2A_IRQn           = 150,
+  TGI2B_IRQn           = 151,
+  TGI2V_IRQn           = 152,
+  TGI2U_IRQn           = 153,
+  TGI3A_IRQn           = 154,
+  TGI3B_IRQn           = 155,
+  TGI3C_IRQn           = 156,
+  TGI3D_IRQn           = 157,
+  TGI3V_IRQn           = 158,
+  TGI4A_IRQn           = 159,
+  TGI4B_IRQn           = 160,
+  TGI4C_IRQn           = 161,
+  TGI4D_IRQn           = 162,
+  TGI4V_IRQn           = 163,
+
+  CMI1_IRQn            = 164,
+  CMI2_IRQn            = 165,
+
+  SGDEI0_IRQn          = 166,
+  SGDEI1_IRQn          = 167,
+  SGDEI2_IRQn          = 168,
+  SGDEI3_IRQn          = 169,
+
+  ADI_IRQn             = 170,
+  LMTI_IRQn            = 171,
+
+  SSII0_IRQn           = 172,       /*!< SSIF Interrupt         */
+  SSIRXI0_IRQn         = 173,       /*!< SSIF Interrupt         */
+  SSITXI0_IRQn         = 174,       /*!< SSIF Interrupt         */
+  SSII1_IRQn           = 175,       /*!< SSIF Interrupt         */
+  SSIRXI1_IRQn         = 176,       /*!< SSIF Interrupt         */
+  SSITXI1_IRQn         = 177,       /*!< SSIF Interrupt         */
+  SSII2_IRQn           = 178,       /*!< SSIF Interrupt         */
+  SSIRTI2_IRQn         = 179,       /*!< SSIF Interrupt         */
+  SSII3_IRQn           = 180,       /*!< SSIF Interrupt         */
+  SSIRXI3_IRQn         = 181,       /*!< SSIF Interrupt         */
+  SSITXI3_IRQn         = 182,       /*!< SSIF Interrupt         */
+  SSII4_IRQn           = 183,       /*!< SSIF Interrupt         */
+  SSIRTI4_IRQn         = 184,       /*!< SSIF Interrupt         */
+  SSII5_IRQn           = 185,       /*!< SSIF Interrupt         */
+  SSIRXI5_IRQn         = 186,       /*!< SSIF Interrupt         */
+  SSITXI5_IRQn         = 187,       /*!< SSIF Interrupt         */
+
+  SPDIFI_IRQn          = 188,
+
+  INTIICTEI0_IRQn      = 189,       /*!< RIIC Interrupt         */
+  INTIICRI0_IRQn       = 190,       /*!< RIIC Interrupt         */
+  INTIICTI0_IRQn       = 191,       /*!< RIIC Interrupt         */
+  INTIICSPI0_IRQn      = 192,       /*!< RIIC Interrupt         */
+  INTIICSTI0_IRQn      = 193,       /*!< RIIC Interrupt         */
+  INTIICNAKI0_IRQn     = 194,       /*!< RIIC Interrupt         */
+  INTIICALI0_IRQn      = 195,       /*!< RIIC Interrupt         */
+  INTIICTMOI0_IRQn     = 196,       /*!< RIIC Interrupt         */
+  INTIICTEI1_IRQn      = 197,       /*!< RIIC Interrupt         */
+  INTIICRI1_IRQn       = 198,       /*!< RIIC Interrupt         */
+  INTIICTI1_IRQn       = 199,       /*!< RIIC Interrupt         */
+  INTIICSPI1_IRQn      = 200,       /*!< RIIC Interrupt         */
+  INTIICSTI1_IRQn      = 201,       /*!< RIIC Interrupt         */
+  INTIICNAKI1_IRQn     = 202,       /*!< RIIC Interrupt         */
+  INTIICALI1_IRQn      = 203,       /*!< RIIC Interrupt         */
+  INTIICTMOI1_IRQn     = 204,       /*!< RIIC Interrupt         */
+  INTIICTEI2_IRQn      = 205,       /*!< RIIC Interrupt         */
+  INTIICRI2_IRQn       = 206,       /*!< RIIC Interrupt         */
+  INTIICTI2_IRQn       = 207,       /*!< RIIC Interrupt         */
+  INTIICSPI2_IRQn      = 208,       /*!< RIIC Interrupt         */
+  INTIICSTI2_IRQn      = 209,       /*!< RIIC Interrupt         */
+  INTIICNAKI2_IRQn     = 210,       /*!< RIIC Interrupt         */
+  INTIICALI2_IRQn      = 211,       /*!< RIIC Interrupt         */
+  INTIICTMOI2_IRQn     = 212,       /*!< RIIC Interrupt         */
+  INTIICTEI3_IRQn      = 213,       /*!< RIIC Interrupt         */
+  INTIICRI3_IRQn       = 214,       /*!< RIIC Interrupt         */
+  INTIICTI3_IRQn       = 215,       /*!< RIIC Interrupt         */
+  INTIICSPI3_IRQn      = 216,       /*!< RIIC Interrupt         */
+  INTIICSTI3_IRQn      = 217,       /*!< RIIC Interrupt         */
+  INTIICNAKI3_IRQn     = 218,       /*!< RIIC Interrupt         */
+  INTIICALI3_IRQn      = 219,       /*!< RIIC Interrupt         */
+  INTIICTMOI3_IRQn     = 220,       /*!< RIIC Interrupt         */
+
+  SCIFBRI0_IRQn        = 221,       /*!< SCIF Interrupt         */
+  SCIFERI0_IRQn        = 222,       /*!< SCIF Interrupt         */
+  SCIFRXI0_IRQn        = 223,       /*!< SCIF Interrupt         */
+  SCIFTXI0_IRQn        = 224,       /*!< SCIF Interrupt         */
+  SCIFBRI1_IRQn        = 225,       /*!< SCIF Interrupt         */
+  SCIFERI1_IRQn        = 226,       /*!< SCIF Interrupt         */
+  SCIFRXI1_IRQn        = 227,       /*!< SCIF Interrupt         */
+  SCIFTXI1_IRQn        = 228,       /*!< SCIF Interrupt         */
+  SCIFBRI2_IRQn        = 229,       /*!< SCIF Interrupt         */
+  SCIFERI2_IRQn        = 230,       /*!< SCIF Interrupt         */
+  SCIFRXI2_IRQn        = 231,       /*!< SCIF Interrupt         */
+  SCIFTXI2_IRQn        = 232,       /*!< SCIF Interrupt         */
+  SCIFBRI3_IRQn        = 233,       /*!< SCIF Interrupt         */
+  SCIFERI3_IRQn        = 234,       /*!< SCIF Interrupt         */
+  SCIFRXI3_IRQn        = 235,       /*!< SCIF Interrupt         */
+  SCIFTXI3_IRQn        = 236,       /*!< SCIF Interrupt         */
+  SCIFBRI4_IRQn        = 237,       /*!< SCIF Interrupt         */
+  SCIFERI4_IRQn        = 238,       /*!< SCIF Interrupt         */
+  SCIFRXI4_IRQn        = 239,       /*!< SCIF Interrupt         */
+  SCIFTXI4_IRQn        = 240,       /*!< SCIF Interrupt         */
+  SCIFBRI5_IRQn        = 241,       /*!< SCIF Interrupt         */
+  SCIFERI5_IRQn        = 242,       /*!< SCIF Interrupt         */
+  SCIFRXI5_IRQn        = 243,       /*!< SCIF Interrupt         */
+  SCIFTXI5_IRQn        = 244,       /*!< SCIF Interrupt         */
+  SCIFBRI6_IRQn        = 245,       /*!< SCIF Interrupt         */
+  SCIFERI6_IRQn        = 246,       /*!< SCIF Interrupt         */
+  SCIFRXI6_IRQn        = 247,       /*!< SCIF Interrupt         */
+  SCIFTXI6_IRQn        = 248,       /*!< SCIF Interrupt         */
+  SCIFBRI7_IRQn        = 249,       /*!< SCIF Interrupt         */
+  SCIFERI7_IRQn        = 250,       /*!< SCIF Interrupt         */
+  SCIFRXI7_IRQn        = 251,       /*!< SCIF Interrupt         */
+  SCIFTXI7_IRQn        = 252,       /*!< SCIF Interrupt         */
+
+  INTRCANGERR_IRQn     = 253,
+  INTRCANGRECC_IRQn    = 254,
+  INTRCAN0REC_IRQn     = 255,
+  INTRCAN0ERR_IRQn     = 256,
+  INTRCAN0TRX_IRQn     = 257,
+  INTRCAN1REC_IRQn     = 258,
+  INTRCAN1ERR_IRQn     = 259,
+  INTRCAN1TRX_IRQn     = 260,
+  INTRCAN2REC_IRQn     = 261,
+  INTRCAN2ERR_IRQn     = 262,
+  INTRCAN2TRX_IRQn     = 263,
+  INTRCAN3REC_IRQn     = 264,
+  INTRCAN3ERR_IRQn     = 265,
+  INTRCAN3TRX_IRQn     = 266,
+  INTRCAN4REC_IRQn     = 267,
+  INTRCAN4ERR_IRQn     = 268,
+  INTRCAN4TRX_IRQn     = 269,
+
+  RSPISPEI0_IRQn       = 270,       /*!< RSPI Interrupt         */
+  RSPISPRI0_IRQn       = 271,       /*!< RSPI Interrupt         */
+  RSPISPTI0_IRQn       = 272,       /*!< RSPI Interrupt         */
+  RSPISPEI1_IRQn       = 273,       /*!< RSPI Interrupt         */
+  RSPISPRI1_IRQn       = 274,       /*!< RSPI Interrupt         */
+  RSPISPTI1_IRQn       = 275,       /*!< RSPI Interrupt         */
+  RSPISPEI2_IRQn       = 276,       /*!< RSPI Interrupt         */
+  RSPISPRI2_IRQn       = 277,       /*!< RSPI Interrupt         */
+  RSPISPTI2_IRQn       = 278,       /*!< RSPI Interrupt         */
+  RSPISPEI3_IRQn       = 279,       /*!< RSPI Interrupt         */
+  RSPISPRI3_IRQn       = 280,       /*!< RSPI Interrupt         */
+  RSPISPTI3_IRQn       = 281,       /*!< RSPI Interrupt         */
+  RSPISPEI4_IRQn       = 282,       /*!< RSPI Interrupt         */
+  RSPISPRI4_IRQn       = 283,       /*!< RSPI Interrupt         */
+  RSPISPTI4_IRQn       = 284,       /*!< RSPI Interrupt         */
+
+  IEBBTD_IRQn          = 285,
+  IEBBTERR_IRQn        = 286,
+  IEBBTSTA_IRQn        = 287,
+  IEBBTV_IRQn          = 288,
+
+  ISY_IRQn             = 289,
+  IERR_IRQn            = 290,
+  ITARG_IRQn           = 291,
+  ISEC_IRQn            = 292,
+  IBUF_IRQn            = 293,
+  IREADY_IRQn          = 294,
+
+  STERB_IRQn           = 295,
+  FLTENDI_IRQn         = 296,
+  FLTREQ0I_IRQn        = 297,
+  FLTREQ1I_IRQn        = 298,
+
+  MMC0_IRQn            = 299,
+  MMC1_IRQn            = 300,
+  MMC2_IRQn            = 301,
+
+  SCHI0_3_IRQn         = 302,
+  SDHI0_0_IRQn         = 303,
+  SDHI0_1_IRQn         = 304,
+  SCHI1_3_IRQn         = 305,
+  SDHI1_0_IRQn         = 306,
+  SDHI1_1_IRQn         = 307,
+
+  ARM_IRQn             = 308,
+  PRD_IRQn             = 309,
+  CUP_IRQn             = 310,
+
+  SCUAI0_IRQn          = 311,
+  SCUAI1_IRQn          = 312,
+  SCUFDI0_IRQn         = 313,
+  SCUFDI1_IRQn         = 314,
+  SCUFDI2_IRQn         = 315,
+  SCUFDI3_IRQn         = 316,
+  SCUFUI0_IRQn         = 317,
+  SCUFUI1_IRQn         = 318,
+  SCUFUI2_IRQn         = 319,
+  SCUFUI3_IRQn         = 320,
+  SCUDVI0_IRQn         = 321,
+  SCUDVI1_IRQn         = 322,
+  SCUDVI2_IRQn         = 323,
+  SCUDVI3_IRQn         = 324,
+
+  MLB_CINT_IRQn        = 325,
+  MLB_SINT_IRQn        = 326,
+
+  DRC10_IRQn           = 327,
+  DRC11_IRQn           = 328,
+
+  /* 329-330 Reserved  */
+
+  LINI0_INT_T_IRQn     = 331,
+  LINI0_INT_R_IRQn     = 332,
+  LINI0_INT_S_IRQn     = 333,
+  LINI0_INT_M_IRQn     = 334,
+  LINI1_INT_T_IRQn     = 335,
+  LINI1_INT_R_IRQn     = 336,
+  LINI1_INT_S_IRQn     = 337,
+  LINI1_INT_M_IRQn     = 338,
+
+  /* 339-346 Reserved */
+
+  SCIERI0_IRQn         = 347,
+  SCIRXI0_IRQn         = 348,
+  SCITXI0_IRQn         = 349,
+  SCITEI0_IRQn         = 350,
+  SCIERI1_IRQn         = 351,
+  SCIRXI1_IRQn         = 352,
+  SCITXI1_IRQn         = 353,
+  SCITEI1_IRQn         = 354,
+
+  AVBI_DATA            = 355,
+  AVBI_ERROR           = 356,
+  AVBI_MANAGE          = 357,
+  AVBI_MAC             = 358,
+
+  ETHERI_IRQn          = 359,
+
+  /* 360-363 Reserved */
+
+  CEUI_IRQn            = 364,
+
+  /* 365-380 Reserved */
+
+  H2XMLB_ERRINT_IRQn   = 381,
+  H2XIC1_ERRINT_IRQn   = 382,
+  X2HPERI1_ERRINT_IRQn = 383,
+  X2HPERR2_ERRINT_IRQn = 384,
+  X2HPERR34_ERRINT_IRQn= 385,
+  X2HPERR5_ERRINT_IRQn = 386,
+  X2HPERR67_ERRINT_IRQn= 387,
+  X2HDBGR_ERRINT_IRQn  = 388,
+  X2HBSC_ERRINT_IRQn   = 389,   
+  X2HSPI1_ERRINT_IRQn  = 390,   
+  X2HSPI2_ERRINT_IRQn  = 391,   
+  PRRI_IRQn            = 392,
+
+  IFEI0_IRQn           = 393,
+  OFFI0_IRQn           = 394,
+  PFVEI0_IRQn          = 395,
+  IFEI1_IRQn           = 396,
+  OFFI1_IRQn           = 397,
+  PFVEI1_IRQn          = 398,
+
+  /* 399-415 Reserved */
+
+  TINT0_IRQn           = 416,
+  TINT1_IRQn           = 417,
+  TINT2_IRQn           = 418,
+  TINT3_IRQn           = 419,
+  TINT4_IRQn           = 420,
+  TINT5_IRQn           = 421,
+  TINT6_IRQn           = 422,
+  TINT7_IRQn           = 423,
+  TINT8_IRQn           = 424,
+  TINT9_IRQn           = 425,
+  TINT10_IRQn          = 426,
+  TINT11_IRQn          = 427,
+  TINT12_IRQn          = 428,
+  TINT13_IRQn          = 429,
+  TINT14_IRQn          = 430,
+  TINT15_IRQn          = 431,
+  TINT16_IRQn          = 432,
+  TINT17_IRQn          = 433,
+  TINT18_IRQn          = 434,
+  TINT19_IRQn          = 435,
+  TINT20_IRQn          = 436,
+  TINT21_IRQn          = 437,
+  TINT22_IRQn          = 438,
+  TINT23_IRQn          = 439,
+  TINT24_IRQn          = 440,
+  TINT25_IRQn          = 441,
+  TINT26_IRQn          = 442,
+  TINT27_IRQn          = 443,
+  TINT28_IRQn          = 444,
+  TINT29_IRQn          = 445,
+  TINT30_IRQn          = 446,
+  TINT31_IRQn          = 447,
+  TINT32_IRQn          = 448,
+  TINT33_IRQn          = 449,
+  TINT34_IRQn          = 450,
+  TINT35_IRQn          = 451,
+  TINT36_IRQn          = 452,
+  TINT37_IRQn          = 453,
+  TINT38_IRQn          = 454,
+  TINT39_IRQn          = 455,
+  TINT40_IRQn          = 456,
+  TINT41_IRQn          = 457,
+  TINT42_IRQn          = 458,
+  TINT43_IRQn          = 459,
+  TINT44_IRQn          = 460,
+  TINT45_IRQn          = 461,
+  TINT46_IRQn          = 462,
+  TINT47_IRQn          = 463,
+  TINT48_IRQn          = 464,
+  TINT49_IRQn          = 465,
+  TINT50_IRQn          = 466,
+  TINT51_IRQn          = 467,
+  TINT52_IRQn          = 468,
+  TINT53_IRQn          = 469,
+  TINT54_IRQn          = 470,
+  TINT55_IRQn          = 471,
+  TINT56_IRQn          = 472,
+  TINT57_IRQn          = 473,
+  TINT58_IRQn          = 474,
+  TINT59_IRQn          = 475,
+  TINT60_IRQn          = 476,
+  TINT61_IRQn          = 477,
+  TINT62_IRQn          = 478,
+  TINT63_IRQn          = 479,
+  TINT64_IRQn          = 480,
+  TINT65_IRQn          = 481,
+  TINT66_IRQn          = 482,
+  TINT67_IRQn          = 483,
+  TINT68_IRQn          = 484,
+  TINT69_IRQn          = 485,
+  TINT70_IRQn          = 486,
+  TINT71_IRQn          = 487,
+  TINT72_IRQn          = 488,
+  TINT73_IRQn          = 489,
+  TINT74_IRQn          = 490,
+  TINT75_IRQn          = 491,
+  TINT76_IRQn          = 492,
+  TINT77_IRQn          = 493,
+  TINT78_IRQn          = 494,
+  TINT79_IRQn          = 495,
+  TINT80_IRQn          = 496,
+  TINT81_IRQn          = 497,
+  TINT82_IRQn          = 498,
+  TINT83_IRQn          = 499,
+  TINT84_IRQn          = 500,
+  TINT85_IRQn          = 501,
+  TINT86_IRQn          = 502,
+  TINT87_IRQn          = 503,
+  TINT88_IRQn          = 504,
+  TINT89_IRQn          = 505,
+  TINT90_IRQn          = 506,
+  TINT91_IRQn          = 507,
+  TINT92_IRQn          = 508,
+  TINT93_IRQn          = 509,
+  TINT94_IRQn          = 510,
+  TINT95_IRQn          = 511,
+  TINT96_IRQn          = 512,
+  TINT97_IRQn          = 513,
+  TINT98_IRQn          = 514,
+  TINT99_IRQn          = 515,
+  TINT100_IRQn         = 516,
+  TINT101_IRQn         = 517,
+  TINT102_IRQn         = 518,
+  TINT103_IRQn         = 519,
+  TINT104_IRQn         = 520,
+  TINT105_IRQn         = 521,
+  TINT106_IRQn         = 522,
+  TINT107_IRQn         = 523,
+  TINT108_IRQn         = 524,
+  TINT109_IRQn         = 525,
+  TINT110_IRQn         = 526,
+  TINT111_IRQn         = 527,
+  TINT112_IRQn         = 528,
+  TINT113_IRQn         = 529,
+  TINT114_IRQn         = 530,
+  TINT115_IRQn         = 531,
+  TINT116_IRQn         = 532,
+  TINT117_IRQn         = 533,
+  TINT118_IRQn         = 534,
+  TINT119_IRQn         = 535,
+  TINT120_IRQn         = 536,
+  TINT121_IRQn         = 537,
+  TINT122_IRQn         = 538,
+  TINT123_IRQn         = 539,
+  TINT124_IRQn         = 540,
+  TINT125_IRQn         = 541,
+  TINT126_IRQn         = 542,
+  TINT127_IRQn         = 543,
+  TINT128_IRQn         = 544,
+  TINT129_IRQn         = 545,
+  TINT130_IRQn         = 546,
+  TINT131_IRQn         = 547,
+  TINT132_IRQn         = 548,
+  TINT133_IRQn         = 549,
+  TINT134_IRQn         = 550,
+  TINT135_IRQn         = 551,
+  TINT136_IRQn         = 552,
+  TINT137_IRQn         = 553,
+  TINT138_IRQn         = 554,
+  TINT139_IRQn         = 555,
+  TINT140_IRQn         = 556,
+  TINT141_IRQn         = 557,
+  TINT142_IRQn         = 558,
+  TINT143_IRQn         = 559,
+  TINT144_IRQn         = 560,
+  TINT145_IRQn         = 561,
+  TINT146_IRQn         = 562,
+  TINT147_IRQn         = 563,
+  TINT148_IRQn         = 564,
+  TINT149_IRQn         = 565,
+  TINT150_IRQn         = 566,
+  TINT151_IRQn         = 567,
+  TINT152_IRQn         = 568,
+  TINT153_IRQn         = 569,
+  TINT154_IRQn         = 570,
+  TINT155_IRQn         = 571,
+  TINT156_IRQn         = 572,
+  TINT157_IRQn         = 573,
+  TINT158_IRQn         = 574,
+  TINT159_IRQn         = 575,
+  TINT160_IRQn         = 576,
+  TINT161_IRQn         = 577,
+  TINT162_IRQn         = 578,
+  TINT163_IRQn         = 579,
+  TINT164_IRQn         = 580,
+  TINT165_IRQn         = 581,
+  TINT166_IRQn         = 582,
+  TINT167_IRQn         = 583,
+  TINT168_IRQn         = 584,
+  TINT169_IRQn         = 585,
+  TINT170_IRQn         = 586
+
+} IRQn_Type;
+
+#define RZ_A1_IRQ_MAX  TINT170_IRQn
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+
+#define RZ_A1_NORFLASH_BASE0               (0x00000000UL)                        /*!< (FLASH0    ) Base Address */
+#define RZ_A1_NORFLASH_BASE1               (0x04000000UL)                        /*!< (FLASH1    ) Base Address */
+#define RZ_A1_SDRAM_BASE0                  (0x08000000UL)                        /*!< (SDRAM0    ) Base Address */
+#define RZ_A1_SDRAM_BASE1                  (0x0C000000UL)                        /*!< (SDRAM1    ) Base Address */
+#define RZ_A1_USER_AREA0                   (0x10000000UL)                        /*!< (USER0     ) Base Address */
+#define RZ_A1_USER_AREA1                   (0x14000000UL)                        /*!< (USER1     ) Base Address */
+#define RZ_A1_SPI_IO0                      (0x18000000UL)                        /*!< (SPI_IO0   ) Base Address */
+#define RZ_A1_SPI_IO1                      (0x1C000000UL)                        /*!< (SPI_IO1   ) Base Address */
+#define RZ_A1_ONCHIP_SRAM_BASE             (0x20000000UL)                        /*!< (SRAM_OC   ) Base Address */
+#define RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
+#define RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
+#define RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
+#define RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
+#define RZ_A1_GIC_DISTRIBUTOR_BASE         (0xe8201000UL)                        /*!< (GIC DIST  ) Base Address */
+#define RZ_A1_GIC_INTERFACE_BASE           (0xe8202000UL)                        /*!< (GIC CPU IF) Base Address */
+#define RZ_A1_PL310_BASE                   (0x3ffff000UL)                        /*!< (PL310     ) Base Address */
+#define RZ_A1_ONCHIP_SRAM_NC_BASE          (0x60000000UL)                        /*!< (SRAM_OC   ) Base Address */
+#define RZ_A1_PRIVATE_TIMER                (0x00000600UL + 0x82000000UL)         /*!< (PTIM      ) Base Address */
+#define GIC_DISTRIBUTOR_BASE               RZ_A1_GIC_DISTRIBUTOR_BASE
+#define GIC_INTERFACE_BASE                 RZ_A1_GIC_INTERFACE_BASE
+#define L2C_310_BASE                       RZ_A1_PL310_BASE
+#define TIMER_BASE                         RZ_A1_PRIVATE_TIMER
+
+/* --------  Configuration of the Cortex-A9 Processor and Core Peripherals  ------- */
+#define __CA_REV        0x0000U    /*!< Core revision r0p0                          */
+#define __CORTEX_A           9U    /*!< Cortex-A9 Core                              */
+#if (__FPU_PRESENT != 1)
+#undef __FPU_PRESENT
+#define __FPU_PRESENT        1U    /* FPU present                                   */
+#endif
+#define __GIC_PRESENT        1U    /* GIC present                                   */
+#define __TIM_PRESENT        0U    /* TIM present                                   */
+#define __L2C_PRESENT        1U    /* L2C present                                   */
+
+#include "core_ca.h"
+#include <system_RZ_A1H.h>
+#include "iodefine.h"
+
+/******************************************************************************/
+/*                         Clock Settings                                     */
+/******************************************************************************/
+/*
+ * Clock Mode 0 settings
+ * SW1-4(MD_CLK):ON
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1035
+ *   CLKEN2    = 0b - unstable
+ *   CLKEN[1:0]=01b - Output, Low, Low
+ *   IFC[1:0]  =00b - CPU clock is 1/1 PLL clock
+ * FRQCR2=0x0001
+ *   GFC[1:0]  =01b - Graphic clock is 2/3 bus clock
+ */
+#define CM0_RENESAS_RZ_A1_CLKIN  ( 13333333u)
+#define CM0_RENESAS_RZ_A1_CLKO   ( 66666666u)
+#define CM0_RENESAS_RZ_A1_I_CLK  (400000000u)
+#define CM0_RENESAS_RZ_A1_G_CLK  (266666666u)
+#define CM0_RENESAS_RZ_A1_B_CLK  (133333333u)
+#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
+#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
+
+/*
+ * Clock Mode 1 settings
+ * SW1-4(MD_CLK):OFF
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1335
+ *   CLKEN2    = 0b - unstable
+ *   CLKEN[1:0]=01b - Output, Low, Low
+ *   IFC[1:0]  =11b - CPU clock is 1/3 PLL clock
+ * FRQCR2=0x0003
+ *   GFC[1:0]  =11b - graphic clock is 1/3 bus clock
+ */
+#define CM1_RENESAS_RZ_A1_CLKIN  ( 48000000u)
+#define CM1_RENESAS_RZ_A1_CLKO   ( 64000000u)
+#define CM1_RENESAS_RZ_A1_I_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_G_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_B_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
+#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
+
+/******************************************************************************/
+/*                         CPG   Settings                                     */
+/******************************************************************************/
+#define CPG_FRQCR_SHIFT_CKOEN2  (14)
+#define CPG_FRQCR_BIT_CKOEN2    (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
+#define CPG_FRQCR_SHIFT_CKOEN0  (12)
+#define CPG_FRQCR_BITS_CKOEN0   (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
+#define CPG_FRQCR_SHIFT_IFC     (8)
+#define CPG_FRQCR_BITS_IFC      (0x3 << CPG_FRQCR_SHIFT_IFC)
+
+#define CPG_FRQCR2_SHIFT_GFC    (0)
+#define CPG_FRQCR2_BITS_GFC     (0x3 << CPG_FRQCR2_SHIFT_GFC)
+
+
+#define CPG_STBCR1_BIT_STBY     (0x80u)
+#define CPG_STBCR1_BIT_DEEP     (0x40u)
+#define CPG_STBCR2_BIT_HIZ      (0x80u)
+#define CPG_STBCR2_BIT_MSTP20   (0x01u) /* CoreSight */
+#define CPG_STBCR3_BIT_MSTP37   (0x80u) /* IEBus */
+#define CPG_STBCR3_BIT_MSTP36   (0x40u) /* IrDA */
+#define CPG_STBCR3_BIT_MSTP35   (0x20u) /* LIN0 */
+#define CPG_STBCR3_BIT_MSTP34   (0x10u) /* LIN1 */
+#define CPG_STBCR3_BIT_MSTP33   (0x08u) /* Multi-Function Timer */
+#define CPG_STBCR3_BIT_MSTP32   (0x04u) /* CAN */
+#define CPG_STBCR3_BIT_MSTP31   (0x02u) /* A/D converter (analog voltage) */
+#define CPG_STBCR3_BIT_MSTP30   (0x01u) /* Motor Control PWM Timer */
+#define CPG_STBCR4_BIT_MSTP47   (0x80u) /* SCIF0 */
+#define CPG_STBCR4_BIT_MSTP46   (0x40u) /* SCIF1 */
+#define CPG_STBCR4_BIT_MSTP45   (0x20u) /* SCIF2 */
+#define CPG_STBCR4_BIT_MSTP44   (0x10u) /* SCIF3 */
+#define CPG_STBCR4_BIT_MSTP43   (0x08u) /* SCIF4 */
+#define CPG_STBCR4_BIT_MSTP42   (0x04u) /* SCIF5 */
+#define CPG_STBCR4_BIT_MSTP41   (0x02u) /* SCIF6 */
+#define CPG_STBCR4_BIT_MSTP40   (0x01u) /* SCIF7 */
+#define CPG_STBCR5_BIT_MSTP57   (0x80u) /* SCI0 */
+#define CPG_STBCR5_BIT_MSTP56   (0x40u) /* SCI1 */
+#define CPG_STBCR5_BIT_MSTP55   (0x20u) /* Sound Generator0 */
+#define CPG_STBCR5_BIT_MSTP54   (0x10u) /* Sound Generator1 */
+#define CPG_STBCR5_BIT_MSTP53   (0x08u) /* Sound Generator2 */
+#define CPG_STBCR5_BIT_MSTP52   (0x04u) /* Sound Generator3 */
+#define CPG_STBCR5_BIT_MSTP51   (0x02u) /* OSTM0 */
+#define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
+#define CPG_STBCR6_BIT_MSTP67   (0x80u) /* A/D converter (clock) */
+#define CPG_STBCR6_BIT_MSTP66   (0x40u) /* Capture Engine */
+#define CPG_STBCR6_BIT_MSTP65   (0x20u) /* Display out comparison0 */
+#define CPG_STBCR6_BIT_MSTP64   (0x10u) /* Display out comparison1 */   
+#define CPG_STBCR6_BIT_MSTP63   (0x08u) /* Dynamic Range compression0 */
+#define CPG_STBCR6_BIT_MSTP62   (0x04u) /* Dynamic Range compression1 */
+#define CPG_STBCR6_BIT_MSTP61   (0x02u) /* JPEG Decoder */
+#define CPG_STBCR6_BIT_MSTP60   (0x01u) /* Realtime Clock */
+#define CPG_STBCR7_BIT_MSTP77   (0x80u) /* Video Decoder0 */
+#define CPG_STBCR7_BIT_MSTP76   (0x40u) /* Video Decoder1 */
+#define CPG_STBCR7_BIT_MSTP74   (0x10u) /* Ethernet */
+#define CPG_STBCR7_BIT_MSTP73   (0x04u) /* NAND Flash Memory Controller */
+#define CPG_STBCR7_BIT_MSTP71   (0x02u) /* USB0 */
+#define CPG_STBCR7_BIT_MSTP70   (0x01u) /* USB1 */
+#define CPG_STBCR8_BIT_MSTP87   (0x80u) /* IMR-LS2_0 */
+#define CPG_STBCR8_BIT_MSTP86   (0x40u) /* IMR-LS2_1 */
+#define CPG_STBCR8_BIT_MSTP85   (0x20u) /* IMR-LSD */
+#define CPG_STBCR8_BIT_MSTP84   (0x10u) /* MMC Host Interface */
+#define CPG_STBCR8_BIT_MSTP83   (0x08u) /* MediaLB */
+#define CPG_STBCR8_BIT_MSTP82   (0x04u) /* EthernetAVB */
+#define CPG_STBCR8_BIT_MSTP81   (0x02u) /* SCUX */
+#define CPG_STBCR9_BIT_MSTP97   (0x80u) /* RIIC0 */
+#define CPG_STBCR9_BIT_MSTP96   (0x40u) /* RIIC1 */
+#define CPG_STBCR9_BIT_MSTP95   (0x20u) /* RIIC2 */
+#define CPG_STBCR9_BIT_MSTP94   (0x10u) /* RIIC3 */
+#define CPG_STBCR9_BIT_MSTP93   (0x08u) /* SPI Multi I/O Bus Controller0 */
+#define CPG_STBCR9_BIT_MSTP92   (0x04u) /* SPI Multi I/O Bus Controller1 */
+#define CPG_STBCR9_BIT_MSTP91   (0x02u) /* VDC5_0 */
+#define CPG_STBCR9_BIT_MSTP90   (0x01u) /* VDC5_1 */
+#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
+#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
+#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
+#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
+#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
+#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
+#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
+#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
+#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
+#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
+#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
+#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
+#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
+#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
+#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
+#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
+#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
+#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
+#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */
+#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */
+#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
+#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
+#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
+#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
+#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
+#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
+#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
+#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
+#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
+#define CPG_SYSCR1_BIT_VRAME4   (0x10u) /* VRAM E Page4 */
+#define CPG_SYSCR1_BIT_VRAME3   (0x08u) /* VRAM E Page3 */
+#define CPG_SYSCR1_BIT_VRAME2   (0x04u) /* VRAM E Page2 */
+#define CPG_SYSCR1_BIT_VRAME1   (0x02u) /* VRAM E Page1 */
+#define CPG_SYSCR1_BIT_VRAME0   (0x01u) /* VRAM E Page0 */
+#define CPG_SYSCR2_BIT_VRAMWE4  (0x10u) /* VRAM WE Page4 */
+#define CPG_SYSCR2_BIT_VRAMWE3  (0x08u) /* VRAM WE Page3 */
+#define CPG_SYSCR2_BIT_VRAMWE2  (0x04u) /* VRAM WE Page2 */
+#define CPG_SYSCR2_BIT_VRAMWE1  (0x02u) /* VRAM WE Page1 */
+#define CPG_SYSCR2_BIT_VRAMWE0  (0x01u) /* VRAM WE Page0 */
+#define CPG_SYSCR3_BIT_RRAMWE3  (0x08u) /* RRAM WE Page3 */
+#define CPG_SYSCR3_BIT_RRAMWE2  (0x04u) /* RRAM WE Page2 */
+#define CPG_SYSCR3_BIT_RRAMWE1  (0x02u) /* RRAM WE Page1 */
+#define CPG_SYSCR3_BIT_RRAMWE0  (0x01u) /* RRAM WE Page0 */
+#define CPG_CPUSTS_BIT_ISBUSY   (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */
+#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */
+#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */
+#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */
+#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */
+#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */
+#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */
+#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */
+#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */
+#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */
+#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */
+#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */
+#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */
+#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */
+#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */
+#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */
+#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */
+#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */
+#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */
+#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */
+#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */
+#define CPG_RRAMKP_BIT_RRAMKP3  (0x08u) /* RRAM KP Page3 */
+#define CPG_RRAMKP_BIT_RRAMKP2  (0x04u) /* RRAM KP Page2 */
+#define CPG_RRAMKP_BIT_RRAMKP1  (0x02u) /* RRAM KP Page1 */
+#define CPG_RRAMKP_BIT_RRAMKP0  (0x01u) /* RRAM KP Page0 */
+#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */
+#define CPG_DSCTR_BIT_RAMBOOT   (0x40u) /* Selection of Method after Returning from Deep Standby Mode */
+#define CPG_DSSSR_BIT_P6_2      (0x4000u) /* P6_2 */
+#define CPG_DSSSR_BIT_P3_9      (0x2000u) /* P3_9 */
+#define CPG_DSSSR_BIT_P3_1      (0x1000u) /* P3_1 */
+#define CPG_DSSSR_BIT_P2_12     (0x0800u) /* P2_12 */
+#define CPG_DSSSR_BIT_P8_7      (0x0400u) /* P8_7 */
+#define CPG_DSSSR_BIT_P3_3      (0x0200u) /* P3_3 */
+#define CPG_DSSSR_BIT_NMI       (0x0100u) /* NMI */
+#define CPG_DSSSR_BIT_RTCAR     (0x0040u) /* RTCAR */
+#define CPG_DSSSR_BIT_P6_4      (0x0020u) /* P6_4 */
+#define CPG_DSSSR_BIT_P5_9      (0x0010u) /* P5_9 */
+#define CPG_DSSSR_BIT_P7_8      (0x0008u) /* P7_8 */
+#define CPG_DSSSR_BIT_P2_15     (0x0004u) /* P2_15 */
+#define CPG_DSSSR_BIT_P9_1      (0x0002u) /* P9_1 */
+#define CPG_DSSSR_BIT_P8_2      (0x0001u) /* P8_2 */
+#define CPG_DSESR_BIT_P6_2E     (0x4000u) /* P6_2 */
+#define CPG_DSESR_BIT_P3_9E     (0x2000u) /* P3_9 */
+#define CPG_DSESR_BIT_P3_1E     (0x1000u) /* P3_1 */
+#define CPG_DSESR_BIT_P2_12E    (0x0800u) /* P2_12 */
+#define CPG_DSESR_BIT_P8_7E     (0x0400u) /* P8_7 */
+#define CPG_DSESR_BIT_P3_3E     (0x0200u) /* P3_3 */
+#define CPG_DSESR_BIT_NMIE      (0x0100u) /* NMI */
+#define CPG_DSESR_BIT_P6_4E     (0x0020u) /* P6_4 */
+#define CPG_DSESR_BIT_P5_9E     (0x0010u) /* P5_9 */
+#define CPG_DSESR_BIT_P7_8E     (0x0008u) /* P7_8 */
+#define CPG_DSESR_BIT_P2_15E    (0x0004u) /* P2_15 */
+#define CPG_DSESR_BIT_P9_1E     (0x0002u) /* P9_1 */
+#define CPG_DSESR_BIT_P8_2E     (0x0001u) /* P8_2 */
+#define CPG_DSFR_BIT_IOKEEP     (0x8000u) /* Release of Pin State Retention */
+#define CPG_DSFR_BIT_P6_2F      (0x4000u) /* P6_2 */
+#define CPG_DSFR_BIT_P3_9F      (0x2000u) /* P3_9 */
+#define CPG_DSFR_BIT_P3_1F      (0x1000u) /* P3_1 */
+#define CPG_DSFR_BIT_P2_12F     (0x0800u) /* P2_12 */
+#define CPG_DSFR_BIT_P8_7F      (0x0400u) /* P8_7 */
+#define CPG_DSFR_BIT_P3_3F      (0x0200u) /* P3_3 */
+#define CPG_DSFR_BIT_NMIF       (0x0100u) /* NMI */
+#define CPG_DSFR_BIT_RTCARF     (0x0040u) /* RTCAR */
+#define CPG_DSFR_BIT_P6_4F      (0x0020u) /* P6_4 */
+#define CPG_DSFR_BIT_P5_9F      (0x0010u) /* P5_9 */
+#define CPG_DSFR_BIT_P7_8F      (0x0008u) /* P7_8 */
+#define CPG_DSFR_BIT_P2_15F     (0x0004u) /* P2_15 */
+#define CPG_DSFR_BIT_P9_1F      (0x0002u) /* P9_1 */
+#define CPG_DSFR_BIT_P8_2F      (0x0001u) /* P8_2 */
+#define CPG_XTALCTR_BIT_GAIN1   (0x02u)   /* RTC_X3, RTC_X4 */
+#define CPG_XTALCTR_BIT_GAIN0   (0x01u)   /* EXTAL, XTAL */
+
+/******************************************************************************/
+/*                        GPIO   Settings                                     */
+/******************************************************************************/
+#define GPIO_BIT_N0  (1u <<  0)
+#define GPIO_BIT_N1  (1u <<  1)
+#define GPIO_BIT_N2  (1u <<  2)
+#define GPIO_BIT_N3  (1u <<  3)
+#define GPIO_BIT_N4  (1u <<  4)
+#define GPIO_BIT_N5  (1u <<  5)
+#define GPIO_BIT_N6  (1u <<  6)
+#define GPIO_BIT_N7  (1u <<  7)
+#define GPIO_BIT_N8  (1u <<  8)
+#define GPIO_BIT_N9  (1u <<  9)
+#define GPIO_BIT_N10 (1u << 10)
+#define GPIO_BIT_N11 (1u << 11)
+#define GPIO_BIT_N12 (1u << 12)
+#define GPIO_BIT_N13 (1u << 13)
+#define GPIO_BIT_N14 (1u << 14)
+#define GPIO_BIT_N15 (1u << 15)
+
+#define MD_BOOT10_MASK    (0x3)
+
+#define MD_BOOT10_BM0     (0x0)
+#define MD_BOOT10_BM1     (0x2)
+#define MD_BOOT10_BM3     (0x1)
+#define MD_BOOT10_BM4_5   (0x3)
+
+#define MD_CLK        (1u << 2)
+#define MD_CLKS       (1u << 3)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __RZ_A1H_H__

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,119 +18,56 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
-#ifndef R7S72100_IODEFINE_H
-#define R7S72100_IODEFINE_H
-#define IODEFINE_H_VERSION  100
-
-enum iodefine_byte_select_t
-{
-    L = 0, H = 1,
-    LL= 0, LH = 1, HL = 2, HH = 3
-};
+#ifndef R7S721000_IODEFINE_H
+#define R7S721000_IODEFINE_H
 
-/***********************************************************************
-  <<< [iodefine_reg32_t] >>> 
-- Padding : sizeof(iodefine_reg32_t) == 4
-- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
--                     &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
-- Endian : Independent (Same as CPU endian as register endian)
-- Bit-Order : Independent
-************************************************************************/
-/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
-/* ->SEC M1.10.1 : Not magic number */
-union iodefine_reg32_t
-{
-    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
-    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
-    volatile uint8_t   UINT8[4];                                /*  8-bit Access    */
-};
-/* <-SEC M1.10.1 */
-/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
-
-/***********************************************************************
-  <<< [iodefine_reg32_16_t] >>> 
-- Padding : sizeof(iodefine_reg32_16_t) == 4
-- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
-- Endian : Independent (Same as CPU endian as register endian)
-- Bit-Order : Independent
-************************************************************************/
-/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
-/* ->SEC M1.10.1 : Not magic number */
-union iodefine_reg32_16_t
-{
-    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
-    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
-};
-/* <-SEC M1.10.1 */
-/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+#include "iodefines/iodefine_typedef.h"                         /* (V2.00h) */
 
-/***********************************************************************
-  <<< [iodefine_reg16_8_t] >>> 
-- Padding : sizeof(iodefine_reg16_8_t) == 2
-- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
-- Endian : Independent (Same as CPU endian as register endian)
-- Bit-Order : Independent
-************************************************************************/
-/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
-/* ->SEC M1.10.1 : Not magic number */
-union iodefine_reg16_8_t
-{
-    volatile uint16_t  UINT16;                                  /*  16-bit Access   */
-    volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
-};
-/* <-SEC M1.10.1 */
-/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
-
-
-
-
-
-
-#include "adc_iodefine.h"                             /* (V1.00a) */
-#include "bsc_iodefine.h"                             /* (V1.00a) */
-#include "ceu_iodefine.h"                             /* (V1.00a) */
-#include "cpg_iodefine.h"                             /* (V1.00a) */
-#include "disc_iodefine.h"                            /* (V1.00a) */
-#include "dmac_iodefine.h"                            /* (V1.00a) */
-#include "dvdec_iodefine.h"                           /* (V1.00a) */
-#include "ether_iodefine.h"                           /* (V1.00a) */
-#include "flctl_iodefine.h"                           /* (V1.00a) */
-#include "gpio_iodefine.h"                            /* (V1.00a) */
-#include "ieb_iodefine.h"                             /* (V1.00a) */
-#include "inb_iodefine.h"                             /* (V1.00a) */
-#include "intc_iodefine.h"                            /* (V1.00a) */
-#include "irda_iodefine.h"                            /* (V1.00a) */
-#include "jcu_iodefine.h"                             /* (V1.00a) */
-#include "l2c_iodefine.h"                             /* (V1.00a) */
-#include "lin_iodefine.h"                             /* (V1.00a) */
-#include "lvds_iodefine.h"                            /* (V1.00a) */
-#include "mlb_iodefine.h"                             /* (V1.00a) */
-#include "mmc_iodefine.h"                             /* (V1.00a) */
-#include "mtu2_iodefine.h"                            /* (V1.00a) */
-#include "ostm_iodefine.h"                            /* (V1.00a) */
-#include "pfv_iodefine.h"                             /* (V1.00a) */
-#include "pwm_iodefine.h"                             /* (V1.00a) */
-#include "riic_iodefine.h"                            /* (V1.00a) */
-#include "romdec_iodefine.h"                          /* (V1.00a) */
-#include "rscan0_iodefine.h"                          /* (V1.00a) */
-#include "rspi_iodefine.h"                            /* (V1.00a) */
-#include "rtc_iodefine.h"                             /* (V1.00a) */
-#include "scif_iodefine.h"                            /* (V1.00a) */
-#include "scim_iodefine.h"                            /* (V1.00a) */
-#include "scux_iodefine.h"                            /* (V1.00a) */
-#include "sdg_iodefine.h"                             /* (V1.00a) */
-#include "spdif_iodefine.h"                           /* (V1.00a) */
-#include "spibsc_iodefine.h"                          /* (V1.00a) */
-#include "ssif_iodefine.h"                            /* (V1.00a) */
-#include "usb20_iodefine.h"                           /* (V1.00a) */
-#include "vdc5_iodefine.h"                            /* (V1.00a) */
-#include "wdt_iodefine.h"                             /* (V1.00a) */
+#include "iodefines/adc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/bsc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/ceu_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/cpg_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/disc_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/dmac_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/dvdec_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/ether_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/flctl_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/gpio_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/ieb_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/inb_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/intc_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/irda_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/jcu_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/l2c_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/lin_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/lvds_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/mlb_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/mmc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/mtu2_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/ostm_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/pfv_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/pwm_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/riic_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/romdec_iodefine.h"                          /* (V2.00h) */
+#include "iodefines/rscan0_iodefine.h"                          /* (V2.00h) */
+#include "iodefines/rspi_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/rtc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/scif_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/scim_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/scux_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/sdg_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/spdif_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/spibsc_iodefine.h"                          /* (V2.00h) */
+#include "iodefines/ssif_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/usb20_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/vdc5_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/wdt_iodefine.h"                             /* (V2.00h) */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,56 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : adc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef ADC_IODEFINE_H
 #define ADC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_adc
-{                                                          /* ADC              */
+#define ADC     (*(struct st_adc     *)0xE8005800uL) /* ADC */
+
+
+#define ADCADDRA (ADC.ADDRA)
+#define ADCADDRB (ADC.ADDRB)
+#define ADCADDRC (ADC.ADDRC)
+#define ADCADDRD (ADC.ADDRD)
+#define ADCADDRE (ADC.ADDRE)
+#define ADCADDRF (ADC.ADDRF)
+#define ADCADDRG (ADC.ADDRG)
+#define ADCADDRH (ADC.ADDRH)
+#define ADCADCMPHA (ADC.ADCMPHA)
+#define ADCADCMPLA (ADC.ADCMPLA)
+#define ADCADCMPHB (ADC.ADCMPHB)
+#define ADCADCMPLB (ADC.ADCMPLB)
+#define ADCADCMPHC (ADC.ADCMPHC)
+#define ADCADCMPLC (ADC.ADCMPLC)
+#define ADCADCMPHD (ADC.ADCMPHD)
+#define ADCADCMPLD (ADC.ADCMPLD)
+#define ADCADCMPHE (ADC.ADCMPHE)
+#define ADCADCMPLE (ADC.ADCMPLE)
+#define ADCADCMPHF (ADC.ADCMPHF)
+#define ADCADCMPLF (ADC.ADCMPLF)
+#define ADCADCMPHG (ADC.ADCMPHG)
+#define ADCADCMPLG (ADC.ADCMPLG)
+#define ADCADCMPHH (ADC.ADCMPHH)
+#define ADCADCMPLH (ADC.ADCMPLH)
+#define ADCADCSR (ADC.ADCSR)
+#define ADCADCMPER (ADC.ADCMPER)
+#define ADCADCMPSR (ADC.ADCMPSR)
+
+
+typedef struct st_adc
+{
+                                                           /* ADC              */
     volatile uint16_t ADDRA;                                  /*  ADDRA           */
     volatile uint16_t ADDRB;                                  /*  ADDRB           */
     volatile uint16_t ADDRC;                                  /*  ADDRC           */
@@ -61,38 +97,11 @@
     volatile uint16_t ADCSR;                                  /*  ADCSR           */
     volatile uint16_t ADCMPER;                                /*  ADCMPER         */
     volatile uint16_t ADCMPSR;                                /*  ADCMPSR         */
-};
-
-
-#define ADC     (*(struct st_adc     *)0xE8005800uL) /* ADC */
+} r_io_adc_t;
 
 
-#define ADCADDRA ADC.ADDRA
-#define ADCADDRB ADC.ADDRB
-#define ADCADDRC ADC.ADDRC
-#define ADCADDRD ADC.ADDRD
-#define ADCADDRE ADC.ADDRE
-#define ADCADDRF ADC.ADDRF
-#define ADCADDRG ADC.ADDRG
-#define ADCADDRH ADC.ADDRH
-#define ADCADCMPHA ADC.ADCMPHA
-#define ADCADCMPLA ADC.ADCMPLA
-#define ADCADCMPHB ADC.ADCMPHB
-#define ADCADCMPLB ADC.ADCMPLB
-#define ADCADCMPHC ADC.ADCMPHC
-#define ADCADCMPLC ADC.ADCMPLC
-#define ADCADCMPHD ADC.ADCMPHD
-#define ADCADCMPLD ADC.ADCMPLD
-#define ADCADCMPHE ADC.ADCMPHE
-#define ADCADCMPLE ADC.ADCMPLE
-#define ADCADCMPHF ADC.ADCMPHF
-#define ADCADCMPLF ADC.ADCMPLF
-#define ADCADCMPHG ADC.ADCMPHG
-#define ADCADCMPLG ADC.ADCMPLG
-#define ADCADCMPHH ADC.ADCMPHH
-#define ADCADCMPLH ADC.ADCMPLH
-#define ADCADCSR ADC.ADCSR
-#define ADCADCMPER ADC.ADCMPER
-#define ADCADCMPSR ADC.ADCMPSR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,22 +18,61 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : bsc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef BSC_IODEFINE_H
 #define BSC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_bsc
-{                                                          /* BSC              */
+#define BSC     (*(struct st_bsc     *)0x3FFFC000uL) /* BSC */
+
+
+#define BSCCMNCR (BSC.CMNCR)
+#define BSCCS0BCR (BSC.CS0BCR)
+#define BSCCS1BCR (BSC.CS1BCR)
+#define BSCCS2BCR (BSC.CS2BCR)
+#define BSCCS3BCR (BSC.CS3BCR)
+#define BSCCS4BCR (BSC.CS4BCR)
+#define BSCCS5BCR (BSC.CS5BCR)
+#define BSCCS0WCR (BSC.CS0WCR)
+#define BSCCS1WCR (BSC.CS1WCR)
+#define BSCCS2WCR (BSC.CS2WCR)
+#define BSCCS3WCR (BSC.CS3WCR)
+#define BSCCS4WCR (BSC.CS4WCR)
+#define BSCCS5WCR (BSC.CS5WCR)
+#define BSCSDCR (BSC.SDCR)
+#define BSCRTCSR (BSC.RTCSR)
+#define BSCRTCNT (BSC.RTCNT)
+#define BSCRTCOR (BSC.RTCOR)
+#define BSCTOSCOR0 (BSC.TOSCOR0)
+#define BSCTOSCOR1 (BSC.TOSCOR1)
+#define BSCTOSCOR2 (BSC.TOSCOR2)
+#define BSCTOSCOR3 (BSC.TOSCOR3)
+#define BSCTOSCOR4 (BSC.TOSCOR4)
+#define BSCTOSCOR5 (BSC.TOSCOR5)
+#define BSCTOSTR (BSC.TOSTR)
+#define BSCTOENR (BSC.TOENR)
+
+#define BSC_CSnBCR_COUNT (6)
+#define BSC_CSnWCR_COUNT (6)
+#define BSC_TOSCORn_COUNT (6)
+
+
+typedef struct st_bsc
+{
+                                                           /* BSC              */
     volatile uint32_t  CMNCR;                                  /*  CMNCR           */
-#define BSC_CSnBCR_COUNT 6
+
+/* #define BSC_CSnBCR_COUNT (6) */
     volatile uint32_t  CS0BCR;                                 /*  CS0BCR          */
     volatile uint32_t  CS1BCR;                                 /*  CS1BCR          */
     volatile uint32_t  CS2BCR;                                 /*  CS2BCR          */
@@ -41,7 +80,8 @@
     volatile uint32_t  CS4BCR;                                 /*  CS4BCR          */
     volatile uint32_t  CS5BCR;                                 /*  CS5BCR          */
     volatile uint8_t   dummy4[12];                             /*                  */
-#define BSC_CSnWCR_COUNT 6
+
+/* #define BSC_CSnWCR_COUNT (6) */
     volatile uint32_t  CS0WCR;                                 /*  CS0WCR          */
     volatile uint32_t  CS1WCR;                                 /*  CS1WCR          */
     volatile uint32_t  CS2WCR;                                 /*  CS2WCR          */
@@ -54,7 +94,8 @@
     volatile uint32_t  RTCNT;                                  /*  RTCNT           */
     volatile uint32_t  RTCOR;                                  /*  RTCOR           */
     volatile uint8_t   dummy6[4];                              /*                  */
-#define BSC_TOSCORn_COUNT 6
+
+/* #define BSC_TOSCORn_COUNT (6) */
     volatile uint32_t  TOSCOR0;                                /*  TOSCOR0         */
     volatile uint32_t  TOSCOR1;                                /*  TOSCOR1         */
     volatile uint32_t  TOSCOR2;                                /*  TOSCOR2         */
@@ -64,36 +105,11 @@
     volatile uint8_t   dummy7[8];                              /*                  */
     volatile uint32_t  TOSTR;                                  /*  TOSTR           */
     volatile uint32_t  TOENR;                                  /*  TOENR           */
-};
-
-
-#define BSC     (*(struct st_bsc     *)0x3FFFC000uL) /* BSC */
+} r_io_bsc_t;
 
 
-#define BSCCMNCR BSC.CMNCR
-#define BSCCS0BCR BSC.CS0BCR
-#define BSCCS1BCR BSC.CS1BCR
-#define BSCCS2BCR BSC.CS2BCR
-#define BSCCS3BCR BSC.CS3BCR
-#define BSCCS4BCR BSC.CS4BCR
-#define BSCCS5BCR BSC.CS5BCR
-#define BSCCS0WCR BSC.CS0WCR
-#define BSCCS1WCR BSC.CS1WCR
-#define BSCCS2WCR BSC.CS2WCR
-#define BSCCS3WCR BSC.CS3WCR
-#define BSCCS4WCR BSC.CS4WCR
-#define BSCCS5WCR BSC.CS5WCR
-#define BSCSDCR BSC.SDCR
-#define BSCRTCSR BSC.RTCSR
-#define BSCRTCNT BSC.RTCNT
-#define BSCRTCOR BSC.RTCOR
-#define BSCTOSCOR0 BSC.TOSCOR0
-#define BSCTOSCOR1 BSC.TOSCOR1
-#define BSCTOSCOR2 BSC.TOSCOR2
-#define BSCTOSCOR3 BSC.TOSCOR3
-#define BSCTOSCOR4 BSC.TOSCOR4
-#define BSCTOSCOR5 BSC.TOSCOR5
-#define BSCTOSTR BSC.TOSTR
-#define BSCTOENR BSC.TOENR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,108 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : ceu_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef CEU_IODEFINE_H
 #define CEU_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_ceu
-{                                                          /* CEU              */
+#define CEU     (*(struct st_ceu     *)0xE8210000uL) /* CEU */
+
+
+/* Start of channel array defines of CEU */
+
+/* Channel array defines of CEUn */
+/*(Sample) value = CEUn[ channel ]->CAMOR; */
+#define CEUn_COUNT  (3)
+#define CEUn_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    (volatile struct st_ceu_n*)&CEU_A, \
+    (volatile struct st_ceu_n*)&CEU_B, \
+    (volatile struct st_ceu_n*)&CEU_M \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CEU_A   (*(struct st_ceu_n *)&CEU.CAPSR)                 /* CEU_A */
+#define CEU_B   (*(struct st_ceu_n *)&CEU.dummy3111)             /* CEU_B */
+#define CEU_M   (*(struct st_ceu_n *)&CEU.dummy3151)             /* CEU_M */
+
+/* End of channel array defines of CEU */
+
+
+#define CEUCAPSR (CEU.CAPSR)
+#define CEUCAPCR (CEU.CAPCR)
+#define CEUCAMCR (CEU.CAMCR)
+#define CEUCMCYR (CEU.CMCYR)
+#define CEUCAMOR_A (CEU.CAMOR_A)
+#define CEUCAPWR_A (CEU.CAPWR_A)
+#define CEUCAIFR (CEU.CAIFR)
+#define CEUCRCNTR (CEU.CRCNTR)
+#define CEUCRCMPR (CEU.CRCMPR)
+#define CEUCFLCR_A (CEU.CFLCR_A)
+#define CEUCFSZR_A (CEU.CFSZR_A)
+#define CEUCDWDR_A (CEU.CDWDR_A)
+#define CEUCDAYR_A (CEU.CDAYR_A)
+#define CEUCDACR_A (CEU.CDACR_A)
+#define CEUCDBYR_A (CEU.CDBYR_A)
+#define CEUCDBCR_A (CEU.CDBCR_A)
+#define CEUCBDSR_A (CEU.CBDSR_A)
+#define CEUCFWCR (CEU.CFWCR)
+#define CEUCLFCR_A (CEU.CLFCR_A)
+#define CEUCDOCR_A (CEU.CDOCR_A)
+#define CEUCEIER (CEU.CEIER)
+#define CEUCETCR (CEU.CETCR)
+#define CEUCSTSR (CEU.CSTSR)
+#define CEUCDSSR (CEU.CDSSR)
+#define CEUCDAYR2_A (CEU.CDAYR2_A)
+#define CEUCDACR2_A (CEU.CDACR2_A)
+#define CEUCDBYR2_A (CEU.CDBYR2_A)
+#define CEUCDBCR2_A (CEU.CDBCR2_A)
+#define CEUCAMOR_B (CEU.CAMOR_B)
+#define CEUCAPWR_B (CEU.CAPWR_B)
+#define CEUCFLCR_B (CEU.CFLCR_B)
+#define CEUCFSZR_B (CEU.CFSZR_B)
+#define CEUCDWDR_B (CEU.CDWDR_B)
+#define CEUCDAYR_B (CEU.CDAYR_B)
+#define CEUCDACR_B (CEU.CDACR_B)
+#define CEUCDBYR_B (CEU.CDBYR_B)
+#define CEUCDBCR_B (CEU.CDBCR_B)
+#define CEUCBDSR_B (CEU.CBDSR_B)
+#define CEUCLFCR_B (CEU.CLFCR_B)
+#define CEUCDOCR_B (CEU.CDOCR_B)
+#define CEUCDAYR2_B (CEU.CDAYR2_B)
+#define CEUCDACR2_B (CEU.CDACR2_B)
+#define CEUCDBYR2_B (CEU.CDBYR2_B)
+#define CEUCDBCR2_B (CEU.CDBCR2_B)
+#define CEUCAMOR_M (CEU.CAMOR_M)
+#define CEUCAPWR_M (CEU.CAPWR_M)
+#define CEUCFLCR_M (CEU.CFLCR_M)
+#define CEUCFSZR_M (CEU.CFSZR_M)
+#define CEUCDWDR_M (CEU.CDWDR_M)
+#define CEUCDAYR_M (CEU.CDAYR_M)
+#define CEUCDACR_M (CEU.CDACR_M)
+#define CEUCDBYR_M (CEU.CDBYR_M)
+#define CEUCDBCR_M (CEU.CDBCR_M)
+#define CEUCBDSR_M (CEU.CBDSR_M)
+#define CEUCLFCR_M (CEU.CLFCR_M)
+#define CEUCDOCR_M (CEU.CDOCR_M)
+#define CEUCDAYR2_M (CEU.CDAYR2_M)
+#define CEUCDACR2_M (CEU.CDACR2_M)
+#define CEUCDBYR2_M (CEU.CDBYR2_M)
+#define CEUCDBCR2_M (CEU.CDBCR2_M)
+
+
+typedef struct st_ceu
+{
+                                                           /* CEU              */
+
 /* start of struct st_ceu_n */
     volatile uint32_t  CAPSR;                                  /*  CAPSR           */
     volatile uint32_t  CAPCR;                                  /*  CAPCR           */
@@ -67,8 +155,10 @@
     volatile uint32_t  CDACR2_A;                               /*  CDACR2_A        */
     volatile uint32_t  CDBYR2_A;                               /*  CDBYR2_A        */
     volatile uint32_t  CDBCR2_A;                               /*  CDBCR2_A        */
+
 /* end of struct st_ceu_n */
     volatile uint8_t   dummy3110[3936];                        /*                  */
+
 /* start of struct st_ceu_n */
     volatile uint8_t   dummy3111[4];                           /*                  */
     volatile uint8_t   dummy3112[4];                           /*                  */
@@ -104,8 +194,10 @@
     volatile uint32_t  CDACR2_B;                               /*  CDACR2_B        */
     volatile uint32_t  CDBYR2_B;                               /*  CDBYR2_B        */
     volatile uint32_t  CDBCR2_B;                               /*  CDBCR2_B        */
+
 /* end of struct st_ceu_n */
     volatile uint8_t   dummy3150[3936];                        /*                  */
+
 /* start of struct st_ceu_n */
     volatile uint8_t   dummy3151[4];                           /*                  */
     volatile uint8_t   dummy3152[4];                           /*                  */
@@ -141,12 +233,14 @@
     volatile uint32_t  CDACR2_M;                               /*  CDACR2_M        */
     volatile uint32_t  CDBYR2_M;                               /*  CDBYR2_M        */
     volatile uint32_t  CDBCR2_M;                               /*  CDBCR2_M        */
+
 /* end of struct st_ceu_n */
-};
+} r_io_ceu_t;
 
 
-struct st_ceu_n
+typedef struct st_ceu_n
 {
+ 
     volatile uint32_t  not_common1;                            /*                  */
     volatile uint32_t  not_common2;                            /*                  */
     volatile uint32_t  not_common3;                            /*                  */
@@ -181,89 +275,21 @@
     volatile uint32_t  CDACR2;                                 /*  CDACR2          */
     volatile uint32_t  CDBYR2;                                 /*  CDBYR2          */
     volatile uint32_t  CDBCR2;                                 /*  CDBCR2          */
-};
-
-
-#define CEU     (*(struct st_ceu     *)0xE8210000uL) /* CEU */
-
-
-/* Start of channnel array defines of CEU */
-
-/* Channnel array defines of CEUn */
-/*(Sample) value = CEUn[ channel ]->CAMOR; */
-#define CEUn_COUNT  3
-#define CEUn_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    (volatile struct st_ceu_n*)&CEU_A, \
-    (volatile struct st_ceu_n*)&CEU_B, \
-    (volatile struct st_ceu_n*)&CEU_M \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define CEU_A   (*(struct st_ceu_n *)&CEU.CAPSR)                 /* CEU_A */
-#define CEU_B   (*(struct st_ceu_n *)&CEU.dummy3111)             /* CEU_B */
-#define CEU_M   (*(struct st_ceu_n *)&CEU.dummy3151)             /* CEU_M */
-
-/* End of channnel array defines of CEU */
+} r_io_ceu_n_t;
 
 
-#define CEUCAPSR CEU.CAPSR
-#define CEUCAPCR CEU.CAPCR
-#define CEUCAMCR CEU.CAMCR
-#define CEUCMCYR CEU.CMCYR
-#define CEUCAMOR_A CEU.CAMOR_A
-#define CEUCAPWR_A CEU.CAPWR_A
-#define CEUCAIFR CEU.CAIFR
-#define CEUCRCNTR CEU.CRCNTR
-#define CEUCRCMPR CEU.CRCMPR
-#define CEUCFLCR_A CEU.CFLCR_A
-#define CEUCFSZR_A CEU.CFSZR_A
-#define CEUCDWDR_A CEU.CDWDR_A
-#define CEUCDAYR_A CEU.CDAYR_A
-#define CEUCDACR_A CEU.CDACR_A
-#define CEUCDBYR_A CEU.CDBYR_A
-#define CEUCDBCR_A CEU.CDBCR_A
-#define CEUCBDSR_A CEU.CBDSR_A
-#define CEUCFWCR CEU.CFWCR
-#define CEUCLFCR_A CEU.CLFCR_A
-#define CEUCDOCR_A CEU.CDOCR_A
-#define CEUCEIER CEU.CEIER
-#define CEUCETCR CEU.CETCR
-#define CEUCSTSR CEU.CSTSR
-#define CEUCDSSR CEU.CDSSR
-#define CEUCDAYR2_A CEU.CDAYR2_A
-#define CEUCDACR2_A CEU.CDACR2_A
-#define CEUCDBYR2_A CEU.CDBYR2_A
-#define CEUCDBCR2_A CEU.CDBCR2_A
-#define CEUCAMOR_B CEU.CAMOR_B
-#define CEUCAPWR_B CEU.CAPWR_B
-#define CEUCFLCR_B CEU.CFLCR_B
-#define CEUCFSZR_B CEU.CFSZR_B
-#define CEUCDWDR_B CEU.CDWDR_B
-#define CEUCDAYR_B CEU.CDAYR_B
-#define CEUCDACR_B CEU.CDACR_B
-#define CEUCDBYR_B CEU.CDBYR_B
-#define CEUCDBCR_B CEU.CDBCR_B
-#define CEUCBDSR_B CEU.CBDSR_B
-#define CEUCLFCR_B CEU.CLFCR_B
-#define CEUCDOCR_B CEU.CDOCR_B
-#define CEUCDAYR2_B CEU.CDAYR2_B
-#define CEUCDACR2_B CEU.CDACR2_B
-#define CEUCDBYR2_B CEU.CDBYR2_B
-#define CEUCDBCR2_B CEU.CDBCR2_B
-#define CEUCAMOR_M CEU.CAMOR_M
-#define CEUCAPWR_M CEU.CAPWR_M
-#define CEUCFLCR_M CEU.CFLCR_M
-#define CEUCFSZR_M CEU.CFSZR_M
-#define CEUCDWDR_M CEU.CDWDR_M
-#define CEUCDAYR_M CEU.CDAYR_M
-#define CEUCDACR_M CEU.CDACR_M
-#define CEUCDBYR_M CEU.CDBYR_M
-#define CEUCDBCR_M CEU.CDBCR_M
-#define CEUCBDSR_M CEU.CBDSR_M
-#define CEUCLFCR_M CEU.CLFCR_M
-#define CEUCDOCR_M CEU.CDOCR_M
-#define CEUCDAYR2_M CEU.CDAYR2_M
-#define CEUCDACR2_M CEU.CDACR2_M
-#define CEUCDBYR2_M CEU.CDBYR2_M
-#define CEUCDBCR2_M CEU.CDBCR2_M
+/* Channel array defines of CEUn (2)*/
+#ifdef  DECLARE_CEUn_CHANNELS
+volatile struct st_ceu_n*  CEUn[ CEUn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CEUn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CEUn_CHANNELS */
+/* End of channel array defines of CEUn (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,109 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : cpg_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef CPG_IODEFINE_H
 #define CPG_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_cpg
-{                                                          /* CPG              */
+#define CPG     (*(struct st_cpg     *)0xFCFE0010uL) /* CPG */
+
+
+/* Start of channel array defines of CPG */
+
+/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
+#define CPG_FROM_SWRSTCR1_ARRAY_COUNT  (3)
+#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
+#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
+#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
+
+
+/* Channel array defines of CPG_FROM_STBCR3_ARRAY */
+/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
+#define CPG_FROM_STBCR3_ARRAY_COUNT  (10)
+#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
+    &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
+#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
+#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
+#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
+#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
+#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
+#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
+#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
+#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
+#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
+
+
+/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
+#define CPG_FROM_SYSCR1_ARRAY_COUNT  (3)
+#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
+#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
+#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
+
+/* End of channel array defines of CPG */
+
+
+#define CPGFRQCR (CPG.FRQCR)
+#define CPGFRQCR2 (CPG.FRQCR2)
+#define CPGCPUSTS (CPG.CPUSTS)
+#define CPGSTBCR1 (CPG.STBCR1)
+#define CPGSTBCR2 (CPG.STBCR2)
+#define CPGSTBREQ1 (CPG.STBREQ1)
+#define CPGSTBREQ2 (CPG.STBREQ2)
+#define CPGSTBACK1 (CPG.STBACK1)
+#define CPGSTBACK2 (CPG.STBACK2)
+#define CPGSYSCR1 (CPG.SYSCR1)
+#define CPGSYSCR2 (CPG.SYSCR2)
+#define CPGSYSCR3 (CPG.SYSCR3)
+#define CPGSTBCR3 (CPG.STBCR3)
+#define CPGSTBCR4 (CPG.STBCR4)
+#define CPGSTBCR5 (CPG.STBCR5)
+#define CPGSTBCR6 (CPG.STBCR6)
+#define CPGSTBCR7 (CPG.STBCR7)
+#define CPGSTBCR8 (CPG.STBCR8)
+#define CPGSTBCR9 (CPG.STBCR9)
+#define CPGSTBCR10 (CPG.STBCR10)
+#define CPGSTBCR11 (CPG.STBCR11)
+#define CPGSTBCR12 (CPG.STBCR12)
+#define CPGSWRSTCR1 (CPG.SWRSTCR1)
+#define CPGSWRSTCR2 (CPG.SWRSTCR2)
+#define CPGSWRSTCR3 (CPG.SWRSTCR3)
+#define CPGSTBCR13 (CPG.STBCR13)
+#define CPGRRAMKP (CPG.RRAMKP)
+#define CPGDSCTR (CPG.DSCTR)
+#define CPGDSSSR (CPG.DSSSR)
+#define CPGDSESR (CPG.DSESR)
+#define CPGDSFR (CPG.DSFR)
+#define CPGXTALCTR (CPG.XTALCTR)
+
+
+typedef struct st_cpg
+{
+                                                           /* CPG              */
     volatile uint16_t FRQCR;                                  /*  FRQCR           */
     volatile uint8_t   dummy319[2];                            /*                  */
     volatile uint16_t FRQCR2;                                 /*  FRQCR2          */
@@ -50,71 +139,103 @@
     volatile uint8_t   dummy326[3];                            /*                  */
     volatile uint8_t   STBACK2;                                /*  STBACK2         */
     volatile uint8_t   dummy327[955];                          /*                  */
+
 /* start of struct st_cpg_from_syscr1 */
     volatile uint8_t   SYSCR1;                                 /*  SYSCR1          */
     volatile uint8_t   dummy328[3];                            /*                  */
+
 /* end of struct st_cpg_from_syscr1 */
+
 /* start of struct st_cpg_from_syscr1 */
     volatile uint8_t   SYSCR2;                                 /*  SYSCR2          */
     volatile uint8_t   dummy329[3];                            /*                  */
+
 /* end of struct st_cpg_from_syscr1 */
+
 /* start of struct st_cpg_from_syscr1 */
     volatile uint8_t   SYSCR3;                                 /*  SYSCR3          */
     volatile uint8_t   dummy3300[3];                           /*                  */
+
 /* end of struct st_cpg_from_syscr1 */
     volatile uint8_t   dummy3301[20];                          /*                  */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR3;                                 /*  STBCR3          */
     volatile uint8_t   dummy331[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR4;                                 /*  STBCR4          */
     volatile uint8_t   dummy332[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR5;                                 /*  STBCR5          */
     volatile uint8_t   dummy333[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR6;                                 /*  STBCR6          */
     volatile uint8_t   dummy334[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR7;                                 /*  STBCR7          */
     volatile uint8_t   dummy335[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR8;                                 /*  STBCR8          */
     volatile uint8_t   dummy336[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR9;                                 /*  STBCR9          */
     volatile uint8_t   dummy337[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR10;                                /*  STBCR10         */
     volatile uint8_t   dummy338[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR11;                                /*  STBCR11         */
     volatile uint8_t   dummy339[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR12;                                /*  STBCR12         */
     volatile uint8_t   dummy3400[3];                           /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
     volatile uint8_t   dummy3401[24];                          /*                  */
+
 /* start of struct st_cpg_from_swrstcr1 */
     volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
     volatile uint8_t   dummy341[3];                            /*                  */
+
 /* end of struct st_cpg_from_swrstcr1 */
+
 /* start of struct st_cpg_from_swrstcr1 */
     volatile uint8_t   SWRSTCR2;                               /*  SWRSTCR2        */
     volatile uint8_t   dummy342[3];                            /*                  */
+
 /* end of struct st_cpg_from_swrstcr1 */
+
 /* start of struct st_cpg_from_swrstcr1 */
     volatile uint8_t   SWRSTCR3;                               /*  SWRSTCR3        */
     volatile uint8_t   dummy3430[3];                           /*                  */
+
 /* end of struct st_cpg_from_swrstcr1 */
     volatile uint8_t   dummy3431[4];                           /*                  */
     volatile uint8_t   STBCR13;                                /*  STBCR13         */
@@ -128,112 +249,59 @@
     volatile uint16_t DSFR;                                   /*  DSFR            */
     volatile uint8_t   dummy347[6];                            /*                  */
     volatile uint8_t   XTALCTR;                                /*  XTALCTR         */
-};
+} r_io_cpg_t;
 
 
-struct st_cpg_from_syscr1
+typedef struct st_cpg_from_syscr1
 {
+ 
     volatile uint8_t   SYSCR1;                                 /*  SYSCR1          */
     volatile uint8_t   dummy1[3];                              /*                  */
-};
-
-
-struct st_cpg_from_stbcr3
-{
-    volatile uint8_t   STBCR3;                                 /*  STBCR3          */
-    volatile uint8_t   dummy1[3];                              /*                  */
-};
+} r_io_cpg_from_syscr1_t;
 
 
-struct st_cpg_from_swrstcr1
+typedef struct st_cpg_from_stbcr3
 {
-    volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
+ 
+    volatile uint8_t   STBCR3;                                 /*  STBCR3          */
     volatile uint8_t   dummy1[3];                              /*                  */
-};
-
-
-#define CPG     (*(struct st_cpg     *)0xFCFE0010uL) /* CPG */
+} r_io_cpg_from_stbcr3_t;
 
 
-/* Start of channnel array defines of CPG */
-
-/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */
-/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
-#define CPG_FROM_SWRSTCR1_ARRAY_COUNT  3
-#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
-#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
-#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
+typedef struct st_cpg_from_swrstcr1
+{
+ 
+    volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
+    volatile uint8_t   dummy1[3];                              /*                  */
+} r_io_cpg_from_swrstcr1_t;
 
 
-/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */
-/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
-#define CPG_FROM_STBCR3_ARRAY_COUNT  10
-#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
-    &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
-#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
-#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
-#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
-#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
-#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
-#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
-#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
-#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
-#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
+/* Channel array defines of CPG (2)*/
+#ifdef  DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS
+volatile struct st_cpg_from_swrstcr1*  CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */
 
+#ifdef  DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS
+volatile struct st_cpg_from_stbcr3*  CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */
 
-/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */
-/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
-#define CPG_FROM_SYSCR1_ARRAY_COUNT  3
-#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
-#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
-#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
-
-/* End of channnel array defines of CPG */
+#ifdef  DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS
+volatile struct st_cpg_from_syscr1*  CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */
+/* End of channel array defines of CPG (2)*/
 
 
-#define CPGFRQCR CPG.FRQCR
-#define CPGFRQCR2 CPG.FRQCR2
-#define CPGCPUSTS CPG.CPUSTS
-#define CPGSTBCR1 CPG.STBCR1
-#define CPGSTBCR2 CPG.STBCR2
-#define CPGSTBREQ1 CPG.STBREQ1
-#define CPGSTBREQ2 CPG.STBREQ2
-#define CPGSTBACK1 CPG.STBACK1
-#define CPGSTBACK2 CPG.STBACK2
-#define CPGSYSCR1 CPG.SYSCR1
-#define CPGSYSCR2 CPG.SYSCR2
-#define CPGSYSCR3 CPG.SYSCR3
-#define CPGSTBCR3 CPG.STBCR3
-#define CPGSTBCR4 CPG.STBCR4
-#define CPGSTBCR5 CPG.STBCR5
-#define CPGSTBCR6 CPG.STBCR6
-#define CPGSTBCR7 CPG.STBCR7
-#define CPGSTBCR8 CPG.STBCR8
-#define CPGSTBCR9 CPG.STBCR9
-#define CPGSTBCR10 CPG.STBCR10
-#define CPGSTBCR11 CPG.STBCR11
-#define CPGSTBCR12 CPG.STBCR12
-#define CPGSWRSTCR1 CPG.SWRSTCR1
-#define CPGSWRSTCR2 CPG.SWRSTCR2
-#define CPGSWRSTCR3 CPG.SWRSTCR3
-#define CPGSTBCR13 CPG.STBCR13
-#define CPGRRAMKP CPG.RRAMKP
-#define CPGDSCTR CPG.DSCTR
-#define CPGDSSSR CPG.DSSSR
-#define CPGDSESR CPG.DSESR
-#define CPGDSFR CPG.DSFR
-#define CPGXTALCTR CPG.XTALCTR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,67 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : disc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef DISC_IODEFINE_H
 #define DISC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_disc
-{                                                          /* DISC             */
+#define DISC0   (*(struct st_disc    *)0xFCFFA800uL) /* DISC0 */
+#define DISC1   (*(struct st_disc    *)0xFCFFB000uL) /* DISC1 */
+
+
+/* Start of channel array defines of DISC */
+
+/* Channel array defines of DISC */
+/*(Sample) value = DISC[ channel ]->DOCMCR; */
+#define DISC_COUNT  (2)
+#define DISC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DISC0, &DISC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of DISC */
+
+
+#define DISC0DOCMCR (DISC0.DOCMCR)
+#define DISC0DOCMSTR (DISC0.DOCMSTR)
+#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR)
+#define DISC0DOCMIENR (DISC0.DOCMIENR)
+#define DISC0DOCMPMR (DISC0.DOCMPMR)
+#define DISC0DOCMECRCR (DISC0.DOCMECRCR)
+#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR)
+#define DISC0DOCMSPXR (DISC0.DOCMSPXR)
+#define DISC0DOCMSPYR (DISC0.DOCMSPYR)
+#define DISC0DOCMSZXR (DISC0.DOCMSZXR)
+#define DISC0DOCMSZYR (DISC0.DOCMSZYR)
+#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR)
+#define DISC1DOCMCR (DISC1.DOCMCR)
+#define DISC1DOCMSTR (DISC1.DOCMSTR)
+#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR)
+#define DISC1DOCMIENR (DISC1.DOCMIENR)
+#define DISC1DOCMPMR (DISC1.DOCMPMR)
+#define DISC1DOCMECRCR (DISC1.DOCMECRCR)
+#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR)
+#define DISC1DOCMSPXR (DISC1.DOCMSPXR)
+#define DISC1DOCMSPYR (DISC1.DOCMSPYR)
+#define DISC1DOCMSZXR (DISC1.DOCMSZXR)
+#define DISC1DOCMSZYR (DISC1.DOCMSZYR)
+#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR)
+
+
+typedef struct st_disc
+{
+                                                           /* DISC             */
     volatile uint32_t  DOCMCR;                                 /*  DOCMCR          */
     volatile uint32_t  DOCMSTR;                                /*  DOCMSTR         */
     volatile uint32_t  DOCMCLSTR;                              /*  DOCMCLSTR       */
@@ -45,49 +92,21 @@
     volatile uint32_t  DOCMSZXR;                               /*  DOCMSZXR        */
     volatile uint32_t  DOCMSZYR;                               /*  DOCMSZYR        */
     volatile uint32_t  DOCMCRCIR;                              /*  DOCMCRCIR       */
-};
-
-
-#define DISC0   (*(struct st_disc    *)0xFCFFA800uL) /* DISC0 */
-#define DISC1   (*(struct st_disc    *)0xFCFFB000uL) /* DISC1 */
-
-
-/* Start of channnel array defines of DISC */
-
-/* Channnel array defines of DISC */
-/*(Sample) value = DISC[ channel ]->DOCMCR; */
-#define DISC_COUNT  2
-#define DISC_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &DISC0, &DISC1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of DISC */
+} r_io_disc_t;
 
 
-#define DISC0DOCMCR DISC0.DOCMCR
-#define DISC0DOCMSTR DISC0.DOCMSTR
-#define DISC0DOCMCLSTR DISC0.DOCMCLSTR
-#define DISC0DOCMIENR DISC0.DOCMIENR
-#define DISC0DOCMPMR DISC0.DOCMPMR
-#define DISC0DOCMECRCR DISC0.DOCMECRCR
-#define DISC0DOCMCCRCR DISC0.DOCMCCRCR
-#define DISC0DOCMSPXR DISC0.DOCMSPXR
-#define DISC0DOCMSPYR DISC0.DOCMSPYR
-#define DISC0DOCMSZXR DISC0.DOCMSZXR
-#define DISC0DOCMSZYR DISC0.DOCMSZYR
-#define DISC0DOCMCRCIR DISC0.DOCMCRCIR
-#define DISC1DOCMCR DISC1.DOCMCR
-#define DISC1DOCMSTR DISC1.DOCMSTR
-#define DISC1DOCMCLSTR DISC1.DOCMCLSTR
-#define DISC1DOCMIENR DISC1.DOCMIENR
-#define DISC1DOCMPMR DISC1.DOCMPMR
-#define DISC1DOCMECRCR DISC1.DOCMECRCR
-#define DISC1DOCMCCRCR DISC1.DOCMCCRCR
-#define DISC1DOCMSPXR DISC1.DOCMSPXR
-#define DISC1DOCMSPYR DISC1.DOCMSPYR
-#define DISC1DOCMSZXR DISC1.DOCMSZXR
-#define DISC1DOCMSZYR DISC1.DOCMSZYR
-#define DISC1DOCMCRCIR DISC1.DOCMCRCIR
+/* Channel array defines of DISC (2)*/
+#ifdef  DECLARE_DISC_CHANNELS
+volatile struct st_disc*  DISC[ DISC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DISC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DISC_CHANNELS */
+/* End of channel array defines of DISC (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,383 +18,48 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : dmac_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef DMAC_IODEFINE_H
 #define DMAC_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_dmac
-{                                                          /* DMAC             */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_0;                                 /*  N0SA_0          */
-    volatile uint32_t  N0DA_0;                                 /*  N0DA_0          */
-    volatile uint32_t  N0TB_0;                                 /*  N0TB_0          */
-    volatile uint32_t  N1SA_0;                                 /*  N1SA_0          */
-    volatile uint32_t  N1DA_0;                                 /*  N1DA_0          */
-    volatile uint32_t  N1TB_0;                                 /*  N1TB_0          */
-    volatile uint32_t  CRSA_0;                                 /*  CRSA_0          */
-    volatile uint32_t  CRDA_0;                                 /*  CRDA_0          */
-    volatile uint32_t  CRTB_0;                                 /*  CRTB_0          */
-    volatile uint32_t  CHSTAT_0;                               /*  CHSTAT_0        */
-    volatile uint32_t  CHCTRL_0;                               /*  CHCTRL_0        */
-    volatile uint32_t  CHCFG_0;                                /*  CHCFG_0         */
-    volatile uint32_t  CHITVL_0;                               /*  CHITVL_0        */
-    volatile uint32_t  CHEXT_0;                                /*  CHEXT_0         */
-    volatile uint32_t  NXLA_0;                                 /*  NXLA_0          */
-    volatile uint32_t  CRLA_0;                                 /*  CRLA_0          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_1;                                 /*  N0SA_1          */
-    volatile uint32_t  N0DA_1;                                 /*  N0DA_1          */
-    volatile uint32_t  N0TB_1;                                 /*  N0TB_1          */
-    volatile uint32_t  N1SA_1;                                 /*  N1SA_1          */
-    volatile uint32_t  N1DA_1;                                 /*  N1DA_1          */
-    volatile uint32_t  N1TB_1;                                 /*  N1TB_1          */
-    volatile uint32_t  CRSA_1;                                 /*  CRSA_1          */
-    volatile uint32_t  CRDA_1;                                 /*  CRDA_1          */
-    volatile uint32_t  CRTB_1;                                 /*  CRTB_1          */
-    volatile uint32_t  CHSTAT_1;                               /*  CHSTAT_1        */
-    volatile uint32_t  CHCTRL_1;                               /*  CHCTRL_1        */
-    volatile uint32_t  CHCFG_1;                                /*  CHCFG_1         */
-    volatile uint32_t  CHITVL_1;                               /*  CHITVL_1        */
-    volatile uint32_t  CHEXT_1;                                /*  CHEXT_1         */
-    volatile uint32_t  NXLA_1;                                 /*  NXLA_1          */
-    volatile uint32_t  CRLA_1;                                 /*  CRLA_1          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_2;                                 /*  N0SA_2          */
-    volatile uint32_t  N0DA_2;                                 /*  N0DA_2          */
-    volatile uint32_t  N0TB_2;                                 /*  N0TB_2          */
-    volatile uint32_t  N1SA_2;                                 /*  N1SA_2          */
-    volatile uint32_t  N1DA_2;                                 /*  N1DA_2          */
-    volatile uint32_t  N1TB_2;                                 /*  N1TB_2          */
-    volatile uint32_t  CRSA_2;                                 /*  CRSA_2          */
-    volatile uint32_t  CRDA_2;                                 /*  CRDA_2          */
-    volatile uint32_t  CRTB_2;                                 /*  CRTB_2          */
-    volatile uint32_t  CHSTAT_2;                               /*  CHSTAT_2        */
-    volatile uint32_t  CHCTRL_2;                               /*  CHCTRL_2        */
-    volatile uint32_t  CHCFG_2;                                /*  CHCFG_2         */
-    volatile uint32_t  CHITVL_2;                               /*  CHITVL_2        */
-    volatile uint32_t  CHEXT_2;                                /*  CHEXT_2         */
-    volatile uint32_t  NXLA_2;                                 /*  NXLA_2          */
-    volatile uint32_t  CRLA_2;                                 /*  CRLA_2          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_3;                                 /*  N0SA_3          */
-    volatile uint32_t  N0DA_3;                                 /*  N0DA_3          */
-    volatile uint32_t  N0TB_3;                                 /*  N0TB_3          */
-    volatile uint32_t  N1SA_3;                                 /*  N1SA_3          */
-    volatile uint32_t  N1DA_3;                                 /*  N1DA_3          */
-    volatile uint32_t  N1TB_3;                                 /*  N1TB_3          */
-    volatile uint32_t  CRSA_3;                                 /*  CRSA_3          */
-    volatile uint32_t  CRDA_3;                                 /*  CRDA_3          */
-    volatile uint32_t  CRTB_3;                                 /*  CRTB_3          */
-    volatile uint32_t  CHSTAT_3;                               /*  CHSTAT_3        */
-    volatile uint32_t  CHCTRL_3;                               /*  CHCTRL_3        */
-    volatile uint32_t  CHCFG_3;                                /*  CHCFG_3         */
-    volatile uint32_t  CHITVL_3;                               /*  CHITVL_3        */
-    volatile uint32_t  CHEXT_3;                                /*  CHEXT_3         */
-    volatile uint32_t  NXLA_3;                                 /*  NXLA_3          */
-    volatile uint32_t  CRLA_3;                                 /*  CRLA_3          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_4;                                 /*  N0SA_4          */
-    volatile uint32_t  N0DA_4;                                 /*  N0DA_4          */
-    volatile uint32_t  N0TB_4;                                 /*  N0TB_4          */
-    volatile uint32_t  N1SA_4;                                 /*  N1SA_4          */
-    volatile uint32_t  N1DA_4;                                 /*  N1DA_4          */
-    volatile uint32_t  N1TB_4;                                 /*  N1TB_4          */
-    volatile uint32_t  CRSA_4;                                 /*  CRSA_4          */
-    volatile uint32_t  CRDA_4;                                 /*  CRDA_4          */
-    volatile uint32_t  CRTB_4;                                 /*  CRTB_4          */
-    volatile uint32_t  CHSTAT_4;                               /*  CHSTAT_4        */
-    volatile uint32_t  CHCTRL_4;                               /*  CHCTRL_4        */
-    volatile uint32_t  CHCFG_4;                                /*  CHCFG_4         */
-    volatile uint32_t  CHITVL_4;                               /*  CHITVL_4        */
-    volatile uint32_t  CHEXT_4;                                /*  CHEXT_4         */
-    volatile uint32_t  NXLA_4;                                 /*  NXLA_4          */
-    volatile uint32_t  CRLA_4;                                 /*  CRLA_4          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_5;                                 /*  N0SA_5          */
-    volatile uint32_t  N0DA_5;                                 /*  N0DA_5          */
-    volatile uint32_t  N0TB_5;                                 /*  N0TB_5          */
-    volatile uint32_t  N1SA_5;                                 /*  N1SA_5          */
-    volatile uint32_t  N1DA_5;                                 /*  N1DA_5          */
-    volatile uint32_t  N1TB_5;                                 /*  N1TB_5          */
-    volatile uint32_t  CRSA_5;                                 /*  CRSA_5          */
-    volatile uint32_t  CRDA_5;                                 /*  CRDA_5          */
-    volatile uint32_t  CRTB_5;                                 /*  CRTB_5          */
-    volatile uint32_t  CHSTAT_5;                               /*  CHSTAT_5        */
-    volatile uint32_t  CHCTRL_5;                               /*  CHCTRL_5        */
-    volatile uint32_t  CHCFG_5;                                /*  CHCFG_5         */
-    volatile uint32_t  CHITVL_5;                               /*  CHITVL_5        */
-    volatile uint32_t  CHEXT_5;                                /*  CHEXT_5         */
-    volatile uint32_t  NXLA_5;                                 /*  NXLA_5          */
-    volatile uint32_t  CRLA_5;                                 /*  CRLA_5          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_6;                                 /*  N0SA_6          */
-    volatile uint32_t  N0DA_6;                                 /*  N0DA_6          */
-    volatile uint32_t  N0TB_6;                                 /*  N0TB_6          */
-    volatile uint32_t  N1SA_6;                                 /*  N1SA_6          */
-    volatile uint32_t  N1DA_6;                                 /*  N1DA_6          */
-    volatile uint32_t  N1TB_6;                                 /*  N1TB_6          */
-    volatile uint32_t  CRSA_6;                                 /*  CRSA_6          */
-    volatile uint32_t  CRDA_6;                                 /*  CRDA_6          */
-    volatile uint32_t  CRTB_6;                                 /*  CRTB_6          */
-    volatile uint32_t  CHSTAT_6;                               /*  CHSTAT_6        */
-    volatile uint32_t  CHCTRL_6;                               /*  CHCTRL_6        */
-    volatile uint32_t  CHCFG_6;                                /*  CHCFG_6         */
-    volatile uint32_t  CHITVL_6;                               /*  CHITVL_6        */
-    volatile uint32_t  CHEXT_6;                                /*  CHEXT_6         */
-    volatile uint32_t  NXLA_6;                                 /*  NXLA_6          */
-    volatile uint32_t  CRLA_6;                                 /*  CRLA_6          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_7;                                 /*  N0SA_7          */
-    volatile uint32_t  N0DA_7;                                 /*  N0DA_7          */
-    volatile uint32_t  N0TB_7;                                 /*  N0TB_7          */
-    volatile uint32_t  N1SA_7;                                 /*  N1SA_7          */
-    volatile uint32_t  N1DA_7;                                 /*  N1DA_7          */
-    volatile uint32_t  N1TB_7;                                 /*  N1TB_7          */
-    volatile uint32_t  CRSA_7;                                 /*  CRSA_7          */
-    volatile uint32_t  CRDA_7;                                 /*  CRDA_7          */
-    volatile uint32_t  CRTB_7;                                 /*  CRTB_7          */
-    volatile uint32_t  CHSTAT_7;                               /*  CHSTAT_7        */
-    volatile uint32_t  CHCTRL_7;                               /*  CHCTRL_7        */
-    volatile uint32_t  CHCFG_7;                                /*  CHCFG_7         */
-    volatile uint32_t  CHITVL_7;                               /*  CHITVL_7        */
-    volatile uint32_t  CHEXT_7;                                /*  CHEXT_7         */
-    volatile uint32_t  NXLA_7;                                 /*  NXLA_7          */
-    volatile uint32_t  CRLA_7;                                 /*  CRLA_7          */
-/* end of struct st_dmac_n */
-    volatile uint8_t   dummy187[256];                          /*                  */
-/* start of struct st_dmaccommon_n */
-    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
-    volatile uint8_t   dummy188[12];                           /*                  */
-    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
-    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
-    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
-    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
-    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
-/* end of struct st_dmaccommon_n */
-    volatile uint8_t   dummy189[220];                          /*                  */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_8;                                 /*  N0SA_8          */
-    volatile uint32_t  N0DA_8;                                 /*  N0DA_8          */
-    volatile uint32_t  N0TB_8;                                 /*  N0TB_8          */
-    volatile uint32_t  N1SA_8;                                 /*  N1SA_8          */
-    volatile uint32_t  N1DA_8;                                 /*  N1DA_8          */
-    volatile uint32_t  N1TB_8;                                 /*  N1TB_8          */
-    volatile uint32_t  CRSA_8;                                 /*  CRSA_8          */
-    volatile uint32_t  CRDA_8;                                 /*  CRDA_8          */
-    volatile uint32_t  CRTB_8;                                 /*  CRTB_8          */
-    volatile uint32_t  CHSTAT_8;                               /*  CHSTAT_8        */
-    volatile uint32_t  CHCTRL_8;                               /*  CHCTRL_8        */
-    volatile uint32_t  CHCFG_8;                                /*  CHCFG_8         */
-    volatile uint32_t  CHITVL_8;                               /*  CHITVL_8        */
-    volatile uint32_t  CHEXT_8;                                /*  CHEXT_8         */
-    volatile uint32_t  NXLA_8;                                 /*  NXLA_8          */
-    volatile uint32_t  CRLA_8;                                 /*  CRLA_8          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_9;                                 /*  N0SA_9          */
-    volatile uint32_t  N0DA_9;                                 /*  N0DA_9          */
-    volatile uint32_t  N0TB_9;                                 /*  N0TB_9          */
-    volatile uint32_t  N1SA_9;                                 /*  N1SA_9          */
-    volatile uint32_t  N1DA_9;                                 /*  N1DA_9          */
-    volatile uint32_t  N1TB_9;                                 /*  N1TB_9          */
-    volatile uint32_t  CRSA_9;                                 /*  CRSA_9          */
-    volatile uint32_t  CRDA_9;                                 /*  CRDA_9          */
-    volatile uint32_t  CRTB_9;                                 /*  CRTB_9          */
-    volatile uint32_t  CHSTAT_9;                               /*  CHSTAT_9        */
-    volatile uint32_t  CHCTRL_9;                               /*  CHCTRL_9        */
-    volatile uint32_t  CHCFG_9;                                /*  CHCFG_9         */
-    volatile uint32_t  CHITVL_9;                               /*  CHITVL_9        */
-    volatile uint32_t  CHEXT_9;                                /*  CHEXT_9         */
-    volatile uint32_t  NXLA_9;                                 /*  NXLA_9          */
-    volatile uint32_t  CRLA_9;                                 /*  CRLA_9          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_10;                                /*  N0SA_10         */
-    volatile uint32_t  N0DA_10;                                /*  N0DA_10         */
-    volatile uint32_t  N0TB_10;                                /*  N0TB_10         */
-    volatile uint32_t  N1SA_10;                                /*  N1SA_10         */
-    volatile uint32_t  N1DA_10;                                /*  N1DA_10         */
-    volatile uint32_t  N1TB_10;                                /*  N1TB_10         */
-    volatile uint32_t  CRSA_10;                                /*  CRSA_10         */
-    volatile uint32_t  CRDA_10;                                /*  CRDA_10         */
-    volatile uint32_t  CRTB_10;                                /*  CRTB_10         */
-    volatile uint32_t  CHSTAT_10;                              /*  CHSTAT_10       */
-    volatile uint32_t  CHCTRL_10;                              /*  CHCTRL_10       */
-    volatile uint32_t  CHCFG_10;                               /*  CHCFG_10        */
-    volatile uint32_t  CHITVL_10;                              /*  CHITVL_10       */
-    volatile uint32_t  CHEXT_10;                               /*  CHEXT_10        */
-    volatile uint32_t  NXLA_10;                                /*  NXLA_10         */
-    volatile uint32_t  CRLA_10;                                /*  CRLA_10         */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_11;                                /*  N0SA_11         */
-    volatile uint32_t  N0DA_11;                                /*  N0DA_11         */
-    volatile uint32_t  N0TB_11;                                /*  N0TB_11         */
-    volatile uint32_t  N1SA_11;                                /*  N1SA_11         */
-    volatile uint32_t  N1DA_11;                                /*  N1DA_11         */
-    volatile uint32_t  N1TB_11;                                /*  N1TB_11         */
-    volatile uint32_t  CRSA_11;                                /*  CRSA_11         */
-    volatile uint32_t  CRDA_11;                                /*  CRDA_11         */
-    volatile uint32_t  CRTB_11;                                /*  CRTB_11         */
-    volatile uint32_t  CHSTAT_11;                              /*  CHSTAT_11       */
-    volatile uint32_t  CHCTRL_11;                              /*  CHCTRL_11       */
-    volatile uint32_t  CHCFG_11;                               /*  CHCFG_11        */
-    volatile uint32_t  CHITVL_11;                              /*  CHITVL_11       */
-    volatile uint32_t  CHEXT_11;                               /*  CHEXT_11        */
-    volatile uint32_t  NXLA_11;                                /*  NXLA_11         */
-    volatile uint32_t  CRLA_11;                                /*  CRLA_11         */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_12;                                /*  N0SA_12         */
-    volatile uint32_t  N0DA_12;                                /*  N0DA_12         */
-    volatile uint32_t  N0TB_12;                                /*  N0TB_12         */
-    volatile uint32_t  N1SA_12;                                /*  N1SA_12         */
-    volatile uint32_t  N1DA_12;                                /*  N1DA_12         */
-    volatile uint32_t  N1TB_12;                                /*  N1TB_12         */
-    volatile uint32_t  CRSA_12;                                /*  CRSA_12         */
-    volatile uint32_t  CRDA_12;                                /*  CRDA_12         */
-    volatile uint32_t  CRTB_12;                                /*  CRTB_12         */
-    volatile uint32_t  CHSTAT_12;                              /*  CHSTAT_12       */
-    volatile uint32_t  CHCTRL_12;                              /*  CHCTRL_12       */
-    volatile uint32_t  CHCFG_12;                               /*  CHCFG_12        */
-    volatile uint32_t  CHITVL_12;                              /*  CHITVL_12       */
-    volatile uint32_t  CHEXT_12;                               /*  CHEXT_12        */
-    volatile uint32_t  NXLA_12;                                /*  NXLA_12         */
-    volatile uint32_t  CRLA_12;                                /*  CRLA_12         */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_13;                                /*  N0SA_13         */
-    volatile uint32_t  N0DA_13;                                /*  N0DA_13         */
-    volatile uint32_t  N0TB_13;                                /*  N0TB_13         */
-    volatile uint32_t  N1SA_13;                                /*  N1SA_13         */
-    volatile uint32_t  N1DA_13;                                /*  N1DA_13         */
-    volatile uint32_t  N1TB_13;                                /*  N1TB_13         */
-    volatile uint32_t  CRSA_13;                                /*  CRSA_13         */
-    volatile uint32_t  CRDA_13;                                /*  CRDA_13         */
-    volatile uint32_t  CRTB_13;                                /*  CRTB_13         */
-    volatile uint32_t  CHSTAT_13;                              /*  CHSTAT_13       */
-    volatile uint32_t  CHCTRL_13;                              /*  CHCTRL_13       */
-    volatile uint32_t  CHCFG_13;                               /*  CHCFG_13        */
-    volatile uint32_t  CHITVL_13;                              /*  CHITVL_13       */
-    volatile uint32_t  CHEXT_13;                               /*  CHEXT_13        */
-    volatile uint32_t  NXLA_13;                                /*  NXLA_13         */
-    volatile uint32_t  CRLA_13;                                /*  CRLA_13         */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_14;                                /*  N0SA_14         */
-    volatile uint32_t  N0DA_14;                                /*  N0DA_14         */
-    volatile uint32_t  N0TB_14;                                /*  N0TB_14         */
-    volatile uint32_t  N1SA_14;                                /*  N1SA_14         */
-    volatile uint32_t  N1DA_14;                                /*  N1DA_14         */
-    volatile uint32_t  N1TB_14;                                /*  N1TB_14         */
-    volatile uint32_t  CRSA_14;                                /*  CRSA_14         */
-    volatile uint32_t  CRDA_14;                                /*  CRDA_14         */
-    volatile uint32_t  CRTB_14;                                /*  CRTB_14         */
-    volatile uint32_t  CHSTAT_14;                              /*  CHSTAT_14       */
-    volatile uint32_t  CHCTRL_14;                              /*  CHCTRL_14       */
-    volatile uint32_t  CHCFG_14;                               /*  CHCFG_14        */
-    volatile uint32_t  CHITVL_14;                              /*  CHITVL_14       */
-    volatile uint32_t  CHEXT_14;                               /*  CHEXT_14        */
-    volatile uint32_t  NXLA_14;                                /*  NXLA_14         */
-    volatile uint32_t  CRLA_14;                                /*  CRLA_14         */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_15;                                /*  N0SA_15         */
-    volatile uint32_t  N0DA_15;                                /*  N0DA_15         */
-    volatile uint32_t  N0TB_15;                                /*  N0TB_15         */
-    volatile uint32_t  N1SA_15;                                /*  N1SA_15         */
-    volatile uint32_t  N1DA_15;                                /*  N1DA_15         */
-    volatile uint32_t  N1TB_15;                                /*  N1TB_15         */
-    volatile uint32_t  CRSA_15;                                /*  CRSA_15         */
-    volatile uint32_t  CRDA_15;                                /*  CRDA_15         */
-    volatile uint32_t  CRTB_15;                                /*  CRTB_15         */
-    volatile uint32_t  CHSTAT_15;                              /*  CHSTAT_15       */
-    volatile uint32_t  CHCTRL_15;                              /*  CHCTRL_15       */
-    volatile uint32_t  CHCFG_15;                               /*  CHCFG_15        */
-    volatile uint32_t  CHITVL_15;                              /*  CHITVL_15       */
-    volatile uint32_t  CHEXT_15;                               /*  CHEXT_15        */
-    volatile uint32_t  NXLA_15;                                /*  NXLA_15         */
-    volatile uint32_t  CRLA_15;                                /*  CRLA_15         */
-/* end of struct st_dmac_n */
-    volatile uint8_t   dummy190[256];                          /*                  */
-/* start of struct st_dmaccommon_n */
-    volatile uint32_t  DCTRL_8_15;                             /*  DCTRL_8_15      */
-    volatile uint8_t   dummy191[12];                           /*                  */
-    volatile uint32_t  DSTAT_EN_8_15;                          /*  DSTAT_EN_8_15   */
-    volatile uint32_t  DSTAT_ER_8_15;                          /*  DSTAT_ER_8_15   */
-    volatile uint32_t  DSTAT_END_8_15;                         /*  DSTAT_END_8_15  */
-    volatile uint32_t  DSTAT_TC_8_15;                          /*  DSTAT_TC_8_15   */
-    volatile uint32_t  DSTAT_SUS_8_15;                         /*  DSTAT_SUS_8_15  */
-/* end of struct st_dmaccommon_n */
-    volatile uint8_t   dummy192[350095580];                    /*                  */
-    volatile uint32_t  DMARS0;                                 /*  DMARS0          */
-    volatile uint32_t  DMARS1;                                 /*  DMARS1          */
-    volatile uint32_t  DMARS2;                                 /*  DMARS2          */
-    volatile uint32_t  DMARS3;                                 /*  DMARS3          */
-    volatile uint32_t  DMARS4;                                 /*  DMARS4          */
-    volatile uint32_t  DMARS5;                                 /*  DMARS5          */
-    volatile uint32_t  DMARS6;                                 /*  DMARS6          */
-    volatile uint32_t  DMARS7;                                 /*  DMARS7          */
-};
 
 
-struct st_dmaccommon_n
-{
-    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
-    volatile uint8_t   dummy1[12];                             /*                  */
-    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
-    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
-    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
-    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
-    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
-};
+/* Channel array defines of DMACmm */
+#define DMACmm_COUNT  (8)
+#define DMACmm_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC01    (*(struct st_dmars_mm *)&DMAC.DMARS0)  /* DMAC0-1   */
+#define DMAC23    (*(struct st_dmars_mm *)&DMAC.DMARS1)  /* DMAC2-3   */
+#define DMAC45    (*(struct st_dmars_mm *)&DMAC.DMARS2)  /* DMAC4-5   */
+#define DMAC67    (*(struct st_dmars_mm *)&DMAC.DMARS3)  /* DMAC6-7   */
+#define DMAC89    (*(struct st_dmars_mm *)&DMAC.DMARS4)  /* DMAC8-9   */
+#define DMAC1011  (*(struct st_dmars_mm *)&DMAC.DMARS5)  /* DMAC10-11 */
+#define DMAC1213  (*(struct st_dmars_mm *)&DMAC.DMARS6)  /* DMAC12-13 */
+#define DMAC1415  (*(struct st_dmars_mm *)&DMAC.DMARS7)  /* DMAC14-15 */
 
 
-struct st_dmac_n
-{
-    volatile uint32_t  N0SA_n;                                 /*  N0SA_n          */
-    volatile uint32_t  N0DA_n;                                 /*  N0DA_n          */
-    volatile uint32_t  N0TB_n;                                 /*  N0TB_n          */
-    volatile uint32_t  N1SA_n;                                 /*  N1SA_n          */
-    volatile uint32_t  N1DA_n;                                 /*  N1DA_n          */
-    volatile uint32_t  N1TB_n;                                 /*  N1TB_n          */
-    volatile uint32_t  CRSA_n;                                 /*  CRSA_n          */
-    volatile uint32_t  CRDA_n;                                 /*  CRDA_n          */
-    volatile uint32_t  CRTB_n;                                 /*  CRTB_n          */
-    volatile uint32_t  CHSTAT_n;                               /*  CHSTAT_n        */
-    volatile uint32_t  CHCTRL_n;                               /*  CHCTRL_n        */
-    volatile uint32_t  CHCFG_n;                                /*  CHCFG_n         */
-    volatile uint32_t  CHITVL_n;                               /*  CHITVL_n        */
-    volatile uint32_t  CHEXT_n;                                /*  CHEXT_n         */
-    volatile uint32_t  NXLA_n;                                 /*  NXLA_n          */
-    volatile uint32_t  CRLA_n;                                 /*  CRLA_n          */
-};
-
-
+/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
 #define DMAC    (*(struct st_dmac    *)0xE8200000uL) /* DMAC */
 
 
-/* Start of channnel array defines of DMAC */
+/* Start of channel array defines of DMAC */
 
-/* Channnel array defines of DMACn */
+/* Channel array defines of DMACn */
 /*(Sample) value = DMACn[ channel ]->N0SA_n; */
-#define DMACn_COUNT  16
+#define DMACn_COUNT  (16)
 #define DMACn_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \
@@ -418,9 +83,9 @@
 #define DMAC15  (*(struct st_dmac_n *)&DMAC.N0SA_15)             /* DMAC15 */
 
 
-/* Channnel array defines of DMACnn */
+/* Channel array defines of DMACnn */
 /*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
-#define DMACnn_COUNT  2
+#define DMACnn_COUNT  (2)
 #define DMACnn_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &DMAC07, &DMAC815 \
@@ -428,306 +93,715 @@
 #define DMAC07  (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7)     /* DMAC07 */
 #define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15)    /* DMAC815 */
 
+/* End of channel array defines of DMAC */
 
-/* Channnel array defines of DMACmm */
-/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
-struct st_dmars_mm
+
+#define DMACN0SA_0 (DMAC.N0SA_0)
+#define DMACN0DA_0 (DMAC.N0DA_0)
+#define DMACN0TB_0 (DMAC.N0TB_0)
+#define DMACN1SA_0 (DMAC.N1SA_0)
+#define DMACN1DA_0 (DMAC.N1DA_0)
+#define DMACN1TB_0 (DMAC.N1TB_0)
+#define DMACCRSA_0 (DMAC.CRSA_0)
+#define DMACCRDA_0 (DMAC.CRDA_0)
+#define DMACCRTB_0 (DMAC.CRTB_0)
+#define DMACCHSTAT_0 (DMAC.CHSTAT_0)
+#define DMACCHCTRL_0 (DMAC.CHCTRL_0)
+#define DMACCHCFG_0 (DMAC.CHCFG_0)
+#define DMACCHITVL_0 (DMAC.CHITVL_0)
+#define DMACCHEXT_0 (DMAC.CHEXT_0)
+#define DMACNXLA_0 (DMAC.NXLA_0)
+#define DMACCRLA_0 (DMAC.CRLA_0)
+#define DMACN0SA_1 (DMAC.N0SA_1)
+#define DMACN0DA_1 (DMAC.N0DA_1)
+#define DMACN0TB_1 (DMAC.N0TB_1)
+#define DMACN1SA_1 (DMAC.N1SA_1)
+#define DMACN1DA_1 (DMAC.N1DA_1)
+#define DMACN1TB_1 (DMAC.N1TB_1)
+#define DMACCRSA_1 (DMAC.CRSA_1)
+#define DMACCRDA_1 (DMAC.CRDA_1)
+#define DMACCRTB_1 (DMAC.CRTB_1)
+#define DMACCHSTAT_1 (DMAC.CHSTAT_1)
+#define DMACCHCTRL_1 (DMAC.CHCTRL_1)
+#define DMACCHCFG_1 (DMAC.CHCFG_1)
+#define DMACCHITVL_1 (DMAC.CHITVL_1)
+#define DMACCHEXT_1 (DMAC.CHEXT_1)
+#define DMACNXLA_1 (DMAC.NXLA_1)
+#define DMACCRLA_1 (DMAC.CRLA_1)
+#define DMACN0SA_2 (DMAC.N0SA_2)
+#define DMACN0DA_2 (DMAC.N0DA_2)
+#define DMACN0TB_2 (DMAC.N0TB_2)
+#define DMACN1SA_2 (DMAC.N1SA_2)
+#define DMACN1DA_2 (DMAC.N1DA_2)
+#define DMACN1TB_2 (DMAC.N1TB_2)
+#define DMACCRSA_2 (DMAC.CRSA_2)
+#define DMACCRDA_2 (DMAC.CRDA_2)
+#define DMACCRTB_2 (DMAC.CRTB_2)
+#define DMACCHSTAT_2 (DMAC.CHSTAT_2)
+#define DMACCHCTRL_2 (DMAC.CHCTRL_2)
+#define DMACCHCFG_2 (DMAC.CHCFG_2)
+#define DMACCHITVL_2 (DMAC.CHITVL_2)
+#define DMACCHEXT_2 (DMAC.CHEXT_2)
+#define DMACNXLA_2 (DMAC.NXLA_2)
+#define DMACCRLA_2 (DMAC.CRLA_2)
+#define DMACN0SA_3 (DMAC.N0SA_3)
+#define DMACN0DA_3 (DMAC.N0DA_3)
+#define DMACN0TB_3 (DMAC.N0TB_3)
+#define DMACN1SA_3 (DMAC.N1SA_3)
+#define DMACN1DA_3 (DMAC.N1DA_3)
+#define DMACN1TB_3 (DMAC.N1TB_3)
+#define DMACCRSA_3 (DMAC.CRSA_3)
+#define DMACCRDA_3 (DMAC.CRDA_3)
+#define DMACCRTB_3 (DMAC.CRTB_3)
+#define DMACCHSTAT_3 (DMAC.CHSTAT_3)
+#define DMACCHCTRL_3 (DMAC.CHCTRL_3)
+#define DMACCHCFG_3 (DMAC.CHCFG_3)
+#define DMACCHITVL_3 (DMAC.CHITVL_3)
+#define DMACCHEXT_3 (DMAC.CHEXT_3)
+#define DMACNXLA_3 (DMAC.NXLA_3)
+#define DMACCRLA_3 (DMAC.CRLA_3)
+#define DMACN0SA_4 (DMAC.N0SA_4)
+#define DMACN0DA_4 (DMAC.N0DA_4)
+#define DMACN0TB_4 (DMAC.N0TB_4)
+#define DMACN1SA_4 (DMAC.N1SA_4)
+#define DMACN1DA_4 (DMAC.N1DA_4)
+#define DMACN1TB_4 (DMAC.N1TB_4)
+#define DMACCRSA_4 (DMAC.CRSA_4)
+#define DMACCRDA_4 (DMAC.CRDA_4)
+#define DMACCRTB_4 (DMAC.CRTB_4)
+#define DMACCHSTAT_4 (DMAC.CHSTAT_4)
+#define DMACCHCTRL_4 (DMAC.CHCTRL_4)
+#define DMACCHCFG_4 (DMAC.CHCFG_4)
+#define DMACCHITVL_4 (DMAC.CHITVL_4)
+#define DMACCHEXT_4 (DMAC.CHEXT_4)
+#define DMACNXLA_4 (DMAC.NXLA_4)
+#define DMACCRLA_4 (DMAC.CRLA_4)
+#define DMACN0SA_5 (DMAC.N0SA_5)
+#define DMACN0DA_5 (DMAC.N0DA_5)
+#define DMACN0TB_5 (DMAC.N0TB_5)
+#define DMACN1SA_5 (DMAC.N1SA_5)
+#define DMACN1DA_5 (DMAC.N1DA_5)
+#define DMACN1TB_5 (DMAC.N1TB_5)
+#define DMACCRSA_5 (DMAC.CRSA_5)
+#define DMACCRDA_5 (DMAC.CRDA_5)
+#define DMACCRTB_5 (DMAC.CRTB_5)
+#define DMACCHSTAT_5 (DMAC.CHSTAT_5)
+#define DMACCHCTRL_5 (DMAC.CHCTRL_5)
+#define DMACCHCFG_5 (DMAC.CHCFG_5)
+#define DMACCHITVL_5 (DMAC.CHITVL_5)
+#define DMACCHEXT_5 (DMAC.CHEXT_5)
+#define DMACNXLA_5 (DMAC.NXLA_5)
+#define DMACCRLA_5 (DMAC.CRLA_5)
+#define DMACN0SA_6 (DMAC.N0SA_6)
+#define DMACN0DA_6 (DMAC.N0DA_6)
+#define DMACN0TB_6 (DMAC.N0TB_6)
+#define DMACN1SA_6 (DMAC.N1SA_6)
+#define DMACN1DA_6 (DMAC.N1DA_6)
+#define DMACN1TB_6 (DMAC.N1TB_6)
+#define DMACCRSA_6 (DMAC.CRSA_6)
+#define DMACCRDA_6 (DMAC.CRDA_6)
+#define DMACCRTB_6 (DMAC.CRTB_6)
+#define DMACCHSTAT_6 (DMAC.CHSTAT_6)
+#define DMACCHCTRL_6 (DMAC.CHCTRL_6)
+#define DMACCHCFG_6 (DMAC.CHCFG_6)
+#define DMACCHITVL_6 (DMAC.CHITVL_6)
+#define DMACCHEXT_6 (DMAC.CHEXT_6)
+#define DMACNXLA_6 (DMAC.NXLA_6)
+#define DMACCRLA_6 (DMAC.CRLA_6)
+#define DMACN0SA_7 (DMAC.N0SA_7)
+#define DMACN0DA_7 (DMAC.N0DA_7)
+#define DMACN0TB_7 (DMAC.N0TB_7)
+#define DMACN1SA_7 (DMAC.N1SA_7)
+#define DMACN1DA_7 (DMAC.N1DA_7)
+#define DMACN1TB_7 (DMAC.N1TB_7)
+#define DMACCRSA_7 (DMAC.CRSA_7)
+#define DMACCRDA_7 (DMAC.CRDA_7)
+#define DMACCRTB_7 (DMAC.CRTB_7)
+#define DMACCHSTAT_7 (DMAC.CHSTAT_7)
+#define DMACCHCTRL_7 (DMAC.CHCTRL_7)
+#define DMACCHCFG_7 (DMAC.CHCFG_7)
+#define DMACCHITVL_7 (DMAC.CHITVL_7)
+#define DMACCHEXT_7 (DMAC.CHEXT_7)
+#define DMACNXLA_7 (DMAC.NXLA_7)
+#define DMACCRLA_7 (DMAC.CRLA_7)
+#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7)
+#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7)
+#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7)
+#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7)
+#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7)
+#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7)
+#define DMACN0SA_8 (DMAC.N0SA_8)
+#define DMACN0DA_8 (DMAC.N0DA_8)
+#define DMACN0TB_8 (DMAC.N0TB_8)
+#define DMACN1SA_8 (DMAC.N1SA_8)
+#define DMACN1DA_8 (DMAC.N1DA_8)
+#define DMACN1TB_8 (DMAC.N1TB_8)
+#define DMACCRSA_8 (DMAC.CRSA_8)
+#define DMACCRDA_8 (DMAC.CRDA_8)
+#define DMACCRTB_8 (DMAC.CRTB_8)
+#define DMACCHSTAT_8 (DMAC.CHSTAT_8)
+#define DMACCHCTRL_8 (DMAC.CHCTRL_8)
+#define DMACCHCFG_8 (DMAC.CHCFG_8)
+#define DMACCHITVL_8 (DMAC.CHITVL_8)
+#define DMACCHEXT_8 (DMAC.CHEXT_8)
+#define DMACNXLA_8 (DMAC.NXLA_8)
+#define DMACCRLA_8 (DMAC.CRLA_8)
+#define DMACN0SA_9 (DMAC.N0SA_9)
+#define DMACN0DA_9 (DMAC.N0DA_9)
+#define DMACN0TB_9 (DMAC.N0TB_9)
+#define DMACN1SA_9 (DMAC.N1SA_9)
+#define DMACN1DA_9 (DMAC.N1DA_9)
+#define DMACN1TB_9 (DMAC.N1TB_9)
+#define DMACCRSA_9 (DMAC.CRSA_9)
+#define DMACCRDA_9 (DMAC.CRDA_9)
+#define DMACCRTB_9 (DMAC.CRTB_9)
+#define DMACCHSTAT_9 (DMAC.CHSTAT_9)
+#define DMACCHCTRL_9 (DMAC.CHCTRL_9)
+#define DMACCHCFG_9 (DMAC.CHCFG_9)
+#define DMACCHITVL_9 (DMAC.CHITVL_9)
+#define DMACCHEXT_9 (DMAC.CHEXT_9)
+#define DMACNXLA_9 (DMAC.NXLA_9)
+#define DMACCRLA_9 (DMAC.CRLA_9)
+#define DMACN0SA_10 (DMAC.N0SA_10)
+#define DMACN0DA_10 (DMAC.N0DA_10)
+#define DMACN0TB_10 (DMAC.N0TB_10)
+#define DMACN1SA_10 (DMAC.N1SA_10)
+#define DMACN1DA_10 (DMAC.N1DA_10)
+#define DMACN1TB_10 (DMAC.N1TB_10)
+#define DMACCRSA_10 (DMAC.CRSA_10)
+#define DMACCRDA_10 (DMAC.CRDA_10)
+#define DMACCRTB_10 (DMAC.CRTB_10)
+#define DMACCHSTAT_10 (DMAC.CHSTAT_10)
+#define DMACCHCTRL_10 (DMAC.CHCTRL_10)
+#define DMACCHCFG_10 (DMAC.CHCFG_10)
+#define DMACCHITVL_10 (DMAC.CHITVL_10)
+#define DMACCHEXT_10 (DMAC.CHEXT_10)
+#define DMACNXLA_10 (DMAC.NXLA_10)
+#define DMACCRLA_10 (DMAC.CRLA_10)
+#define DMACN0SA_11 (DMAC.N0SA_11)
+#define DMACN0DA_11 (DMAC.N0DA_11)
+#define DMACN0TB_11 (DMAC.N0TB_11)
+#define DMACN1SA_11 (DMAC.N1SA_11)
+#define DMACN1DA_11 (DMAC.N1DA_11)
+#define DMACN1TB_11 (DMAC.N1TB_11)
+#define DMACCRSA_11 (DMAC.CRSA_11)
+#define DMACCRDA_11 (DMAC.CRDA_11)
+#define DMACCRTB_11 (DMAC.CRTB_11)
+#define DMACCHSTAT_11 (DMAC.CHSTAT_11)
+#define DMACCHCTRL_11 (DMAC.CHCTRL_11)
+#define DMACCHCFG_11 (DMAC.CHCFG_11)
+#define DMACCHITVL_11 (DMAC.CHITVL_11)
+#define DMACCHEXT_11 (DMAC.CHEXT_11)
+#define DMACNXLA_11 (DMAC.NXLA_11)
+#define DMACCRLA_11 (DMAC.CRLA_11)
+#define DMACN0SA_12 (DMAC.N0SA_12)
+#define DMACN0DA_12 (DMAC.N0DA_12)
+#define DMACN0TB_12 (DMAC.N0TB_12)
+#define DMACN1SA_12 (DMAC.N1SA_12)
+#define DMACN1DA_12 (DMAC.N1DA_12)
+#define DMACN1TB_12 (DMAC.N1TB_12)
+#define DMACCRSA_12 (DMAC.CRSA_12)
+#define DMACCRDA_12 (DMAC.CRDA_12)
+#define DMACCRTB_12 (DMAC.CRTB_12)
+#define DMACCHSTAT_12 (DMAC.CHSTAT_12)
+#define DMACCHCTRL_12 (DMAC.CHCTRL_12)
+#define DMACCHCFG_12 (DMAC.CHCFG_12)
+#define DMACCHITVL_12 (DMAC.CHITVL_12)
+#define DMACCHEXT_12 (DMAC.CHEXT_12)
+#define DMACNXLA_12 (DMAC.NXLA_12)
+#define DMACCRLA_12 (DMAC.CRLA_12)
+#define DMACN0SA_13 (DMAC.N0SA_13)
+#define DMACN0DA_13 (DMAC.N0DA_13)
+#define DMACN0TB_13 (DMAC.N0TB_13)
+#define DMACN1SA_13 (DMAC.N1SA_13)
+#define DMACN1DA_13 (DMAC.N1DA_13)
+#define DMACN1TB_13 (DMAC.N1TB_13)
+#define DMACCRSA_13 (DMAC.CRSA_13)
+#define DMACCRDA_13 (DMAC.CRDA_13)
+#define DMACCRTB_13 (DMAC.CRTB_13)
+#define DMACCHSTAT_13 (DMAC.CHSTAT_13)
+#define DMACCHCTRL_13 (DMAC.CHCTRL_13)
+#define DMACCHCFG_13 (DMAC.CHCFG_13)
+#define DMACCHITVL_13 (DMAC.CHITVL_13)
+#define DMACCHEXT_13 (DMAC.CHEXT_13)
+#define DMACNXLA_13 (DMAC.NXLA_13)
+#define DMACCRLA_13 (DMAC.CRLA_13)
+#define DMACN0SA_14 (DMAC.N0SA_14)
+#define DMACN0DA_14 (DMAC.N0DA_14)
+#define DMACN0TB_14 (DMAC.N0TB_14)
+#define DMACN1SA_14 (DMAC.N1SA_14)
+#define DMACN1DA_14 (DMAC.N1DA_14)
+#define DMACN1TB_14 (DMAC.N1TB_14)
+#define DMACCRSA_14 (DMAC.CRSA_14)
+#define DMACCRDA_14 (DMAC.CRDA_14)
+#define DMACCRTB_14 (DMAC.CRTB_14)
+#define DMACCHSTAT_14 (DMAC.CHSTAT_14)
+#define DMACCHCTRL_14 (DMAC.CHCTRL_14)
+#define DMACCHCFG_14 (DMAC.CHCFG_14)
+#define DMACCHITVL_14 (DMAC.CHITVL_14)
+#define DMACCHEXT_14 (DMAC.CHEXT_14)
+#define DMACNXLA_14 (DMAC.NXLA_14)
+#define DMACCRLA_14 (DMAC.CRLA_14)
+#define DMACN0SA_15 (DMAC.N0SA_15)
+#define DMACN0DA_15 (DMAC.N0DA_15)
+#define DMACN0TB_15 (DMAC.N0TB_15)
+#define DMACN1SA_15 (DMAC.N1SA_15)
+#define DMACN1DA_15 (DMAC.N1DA_15)
+#define DMACN1TB_15 (DMAC.N1TB_15)
+#define DMACCRSA_15 (DMAC.CRSA_15)
+#define DMACCRDA_15 (DMAC.CRDA_15)
+#define DMACCRTB_15 (DMAC.CRTB_15)
+#define DMACCHSTAT_15 (DMAC.CHSTAT_15)
+#define DMACCHCTRL_15 (DMAC.CHCTRL_15)
+#define DMACCHCFG_15 (DMAC.CHCFG_15)
+#define DMACCHITVL_15 (DMAC.CHITVL_15)
+#define DMACCHEXT_15 (DMAC.CHEXT_15)
+#define DMACNXLA_15 (DMAC.NXLA_15)
+#define DMACCRLA_15 (DMAC.CRLA_15)
+#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15)
+#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15)
+#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15)
+#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15)
+#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15)
+#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15)
+#define DMACDMARS0 (DMAC.DMARS0)
+#define DMACDMARS1 (DMAC.DMARS1)
+#define DMACDMARS2 (DMAC.DMARS2)
+#define DMACDMARS3 (DMAC.DMARS3)
+#define DMACDMARS4 (DMAC.DMARS4)
+#define DMACDMARS5 (DMAC.DMARS5)
+#define DMACDMARS6 (DMAC.DMARS6)
+#define DMACDMARS7 (DMAC.DMARS7)
+
+
+typedef struct st_dmars_mm
 {
-    uint32_t       DMARS;                                        /*  DMARS     */
-};
-#define DMACmm_COUNT  8
-#define DMACmm_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define DMAC01    (*(struct st_dmars_mm *)&DMAC.DMARS0)  /* DMAC0-1   */
-#define DMAC23    (*(struct st_dmars_mm *)&DMAC.DMARS1)  /* DMAC2-3   */
-#define DMAC45    (*(struct st_dmars_mm *)&DMAC.DMARS2)  /* DMAC4-5   */
-#define DMAC67    (*(struct st_dmars_mm *)&DMAC.DMARS3)  /* DMAC6-7   */
-#define DMAC89    (*(struct st_dmars_mm *)&DMAC.DMARS4)  /* DMAC8-9   */
-#define DMAC1011  (*(struct st_dmars_mm *)&DMAC.DMARS5)  /* DMAC10-11 */
-#define DMAC1213  (*(struct st_dmars_mm *)&DMAC.DMARS6)  /* DMAC12-13 */
-#define DMAC1415  (*(struct st_dmars_mm *)&DMAC.DMARS7)  /* DMAC14-15 */
-
-/* End of channnel array defines of DMAC */
+ 
+    volatile uint32_t  DMARS;                                    /*  DMARS     */
+} r_io_dmars_mm_t;
 
 
-#define DMACN0SA_0 DMAC.N0SA_0
-#define DMACN0DA_0 DMAC.N0DA_0
-#define DMACN0TB_0 DMAC.N0TB_0
-#define DMACN1SA_0 DMAC.N1SA_0
-#define DMACN1DA_0 DMAC.N1DA_0
-#define DMACN1TB_0 DMAC.N1TB_0
-#define DMACCRSA_0 DMAC.CRSA_0
-#define DMACCRDA_0 DMAC.CRDA_0
-#define DMACCRTB_0 DMAC.CRTB_0
-#define DMACCHSTAT_0 DMAC.CHSTAT_0
-#define DMACCHCTRL_0 DMAC.CHCTRL_0
-#define DMACCHCFG_0 DMAC.CHCFG_0
-#define DMACCHITVL_0 DMAC.CHITVL_0
-#define DMACCHEXT_0 DMAC.CHEXT_0
-#define DMACNXLA_0 DMAC.NXLA_0
-#define DMACCRLA_0 DMAC.CRLA_0
-#define DMACN0SA_1 DMAC.N0SA_1
-#define DMACN0DA_1 DMAC.N0DA_1
-#define DMACN0TB_1 DMAC.N0TB_1
-#define DMACN1SA_1 DMAC.N1SA_1
-#define DMACN1DA_1 DMAC.N1DA_1
-#define DMACN1TB_1 DMAC.N1TB_1
-#define DMACCRSA_1 DMAC.CRSA_1
-#define DMACCRDA_1 DMAC.CRDA_1
-#define DMACCRTB_1 DMAC.CRTB_1
-#define DMACCHSTAT_1 DMAC.CHSTAT_1
-#define DMACCHCTRL_1 DMAC.CHCTRL_1
-#define DMACCHCFG_1 DMAC.CHCFG_1
-#define DMACCHITVL_1 DMAC.CHITVL_1
-#define DMACCHEXT_1 DMAC.CHEXT_1
-#define DMACNXLA_1 DMAC.NXLA_1
-#define DMACCRLA_1 DMAC.CRLA_1
-#define DMACN0SA_2 DMAC.N0SA_2
-#define DMACN0DA_2 DMAC.N0DA_2
-#define DMACN0TB_2 DMAC.N0TB_2
-#define DMACN1SA_2 DMAC.N1SA_2
-#define DMACN1DA_2 DMAC.N1DA_2
-#define DMACN1TB_2 DMAC.N1TB_2
-#define DMACCRSA_2 DMAC.CRSA_2
-#define DMACCRDA_2 DMAC.CRDA_2
-#define DMACCRTB_2 DMAC.CRTB_2
-#define DMACCHSTAT_2 DMAC.CHSTAT_2
-#define DMACCHCTRL_2 DMAC.CHCTRL_2
-#define DMACCHCFG_2 DMAC.CHCFG_2
-#define DMACCHITVL_2 DMAC.CHITVL_2
-#define DMACCHEXT_2 DMAC.CHEXT_2
-#define DMACNXLA_2 DMAC.NXLA_2
-#define DMACCRLA_2 DMAC.CRLA_2
-#define DMACN0SA_3 DMAC.N0SA_3
-#define DMACN0DA_3 DMAC.N0DA_3
-#define DMACN0TB_3 DMAC.N0TB_3
-#define DMACN1SA_3 DMAC.N1SA_3
-#define DMACN1DA_3 DMAC.N1DA_3
-#define DMACN1TB_3 DMAC.N1TB_3
-#define DMACCRSA_3 DMAC.CRSA_3
-#define DMACCRDA_3 DMAC.CRDA_3
-#define DMACCRTB_3 DMAC.CRTB_3
-#define DMACCHSTAT_3 DMAC.CHSTAT_3
-#define DMACCHCTRL_3 DMAC.CHCTRL_3
-#define DMACCHCFG_3 DMAC.CHCFG_3
-#define DMACCHITVL_3 DMAC.CHITVL_3
-#define DMACCHEXT_3 DMAC.CHEXT_3
-#define DMACNXLA_3 DMAC.NXLA_3
-#define DMACCRLA_3 DMAC.CRLA_3
-#define DMACN0SA_4 DMAC.N0SA_4
-#define DMACN0DA_4 DMAC.N0DA_4
-#define DMACN0TB_4 DMAC.N0TB_4
-#define DMACN1SA_4 DMAC.N1SA_4
-#define DMACN1DA_4 DMAC.N1DA_4
-#define DMACN1TB_4 DMAC.N1TB_4
-#define DMACCRSA_4 DMAC.CRSA_4
-#define DMACCRDA_4 DMAC.CRDA_4
-#define DMACCRTB_4 DMAC.CRTB_4
-#define DMACCHSTAT_4 DMAC.CHSTAT_4
-#define DMACCHCTRL_4 DMAC.CHCTRL_4
-#define DMACCHCFG_4 DMAC.CHCFG_4
-#define DMACCHITVL_4 DMAC.CHITVL_4
-#define DMACCHEXT_4 DMAC.CHEXT_4
-#define DMACNXLA_4 DMAC.NXLA_4
-#define DMACCRLA_4 DMAC.CRLA_4
-#define DMACN0SA_5 DMAC.N0SA_5
-#define DMACN0DA_5 DMAC.N0DA_5
-#define DMACN0TB_5 DMAC.N0TB_5
-#define DMACN1SA_5 DMAC.N1SA_5
-#define DMACN1DA_5 DMAC.N1DA_5
-#define DMACN1TB_5 DMAC.N1TB_5
-#define DMACCRSA_5 DMAC.CRSA_5
-#define DMACCRDA_5 DMAC.CRDA_5
-#define DMACCRTB_5 DMAC.CRTB_5
-#define DMACCHSTAT_5 DMAC.CHSTAT_5
-#define DMACCHCTRL_5 DMAC.CHCTRL_5
-#define DMACCHCFG_5 DMAC.CHCFG_5
-#define DMACCHITVL_5 DMAC.CHITVL_5
-#define DMACCHEXT_5 DMAC.CHEXT_5
-#define DMACNXLA_5 DMAC.NXLA_5
-#define DMACCRLA_5 DMAC.CRLA_5
-#define DMACN0SA_6 DMAC.N0SA_6
-#define DMACN0DA_6 DMAC.N0DA_6
-#define DMACN0TB_6 DMAC.N0TB_6
-#define DMACN1SA_6 DMAC.N1SA_6
-#define DMACN1DA_6 DMAC.N1DA_6
-#define DMACN1TB_6 DMAC.N1TB_6
-#define DMACCRSA_6 DMAC.CRSA_6
-#define DMACCRDA_6 DMAC.CRDA_6
-#define DMACCRTB_6 DMAC.CRTB_6
-#define DMACCHSTAT_6 DMAC.CHSTAT_6
-#define DMACCHCTRL_6 DMAC.CHCTRL_6
-#define DMACCHCFG_6 DMAC.CHCFG_6
-#define DMACCHITVL_6 DMAC.CHITVL_6
-#define DMACCHEXT_6 DMAC.CHEXT_6
-#define DMACNXLA_6 DMAC.NXLA_6
-#define DMACCRLA_6 DMAC.CRLA_6
-#define DMACN0SA_7 DMAC.N0SA_7
-#define DMACN0DA_7 DMAC.N0DA_7
-#define DMACN0TB_7 DMAC.N0TB_7
-#define DMACN1SA_7 DMAC.N1SA_7
-#define DMACN1DA_7 DMAC.N1DA_7
-#define DMACN1TB_7 DMAC.N1TB_7
-#define DMACCRSA_7 DMAC.CRSA_7
-#define DMACCRDA_7 DMAC.CRDA_7
-#define DMACCRTB_7 DMAC.CRTB_7
-#define DMACCHSTAT_7 DMAC.CHSTAT_7
-#define DMACCHCTRL_7 DMAC.CHCTRL_7
-#define DMACCHCFG_7 DMAC.CHCFG_7
-#define DMACCHITVL_7 DMAC.CHITVL_7
-#define DMACCHEXT_7 DMAC.CHEXT_7
-#define DMACNXLA_7 DMAC.NXLA_7
-#define DMACCRLA_7 DMAC.CRLA_7
-#define DMACDCTRL_0_7 DMAC.DCTRL_0_7
-#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7
-#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7
-#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7
-#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7
-#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7
-#define DMACN0SA_8 DMAC.N0SA_8
-#define DMACN0DA_8 DMAC.N0DA_8
-#define DMACN0TB_8 DMAC.N0TB_8
-#define DMACN1SA_8 DMAC.N1SA_8
-#define DMACN1DA_8 DMAC.N1DA_8
-#define DMACN1TB_8 DMAC.N1TB_8
-#define DMACCRSA_8 DMAC.CRSA_8
-#define DMACCRDA_8 DMAC.CRDA_8
-#define DMACCRTB_8 DMAC.CRTB_8
-#define DMACCHSTAT_8 DMAC.CHSTAT_8
-#define DMACCHCTRL_8 DMAC.CHCTRL_8
-#define DMACCHCFG_8 DMAC.CHCFG_8
-#define DMACCHITVL_8 DMAC.CHITVL_8
-#define DMACCHEXT_8 DMAC.CHEXT_8
-#define DMACNXLA_8 DMAC.NXLA_8
-#define DMACCRLA_8 DMAC.CRLA_8
-#define DMACN0SA_9 DMAC.N0SA_9
-#define DMACN0DA_9 DMAC.N0DA_9
-#define DMACN0TB_9 DMAC.N0TB_9
-#define DMACN1SA_9 DMAC.N1SA_9
-#define DMACN1DA_9 DMAC.N1DA_9
-#define DMACN1TB_9 DMAC.N1TB_9
-#define DMACCRSA_9 DMAC.CRSA_9
-#define DMACCRDA_9 DMAC.CRDA_9
-#define DMACCRTB_9 DMAC.CRTB_9
-#define DMACCHSTAT_9 DMAC.CHSTAT_9
-#define DMACCHCTRL_9 DMAC.CHCTRL_9
-#define DMACCHCFG_9 DMAC.CHCFG_9
-#define DMACCHITVL_9 DMAC.CHITVL_9
-#define DMACCHEXT_9 DMAC.CHEXT_9
-#define DMACNXLA_9 DMAC.NXLA_9
-#define DMACCRLA_9 DMAC.CRLA_9
-#define DMACN0SA_10 DMAC.N0SA_10
-#define DMACN0DA_10 DMAC.N0DA_10
-#define DMACN0TB_10 DMAC.N0TB_10
-#define DMACN1SA_10 DMAC.N1SA_10
-#define DMACN1DA_10 DMAC.N1DA_10
-#define DMACN1TB_10 DMAC.N1TB_10
-#define DMACCRSA_10 DMAC.CRSA_10
-#define DMACCRDA_10 DMAC.CRDA_10
-#define DMACCRTB_10 DMAC.CRTB_10
-#define DMACCHSTAT_10 DMAC.CHSTAT_10
-#define DMACCHCTRL_10 DMAC.CHCTRL_10
-#define DMACCHCFG_10 DMAC.CHCFG_10
-#define DMACCHITVL_10 DMAC.CHITVL_10
-#define DMACCHEXT_10 DMAC.CHEXT_10
-#define DMACNXLA_10 DMAC.NXLA_10
-#define DMACCRLA_10 DMAC.CRLA_10
-#define DMACN0SA_11 DMAC.N0SA_11
-#define DMACN0DA_11 DMAC.N0DA_11
-#define DMACN0TB_11 DMAC.N0TB_11
-#define DMACN1SA_11 DMAC.N1SA_11
-#define DMACN1DA_11 DMAC.N1DA_11
-#define DMACN1TB_11 DMAC.N1TB_11
-#define DMACCRSA_11 DMAC.CRSA_11
-#define DMACCRDA_11 DMAC.CRDA_11
-#define DMACCRTB_11 DMAC.CRTB_11
-#define DMACCHSTAT_11 DMAC.CHSTAT_11
-#define DMACCHCTRL_11 DMAC.CHCTRL_11
-#define DMACCHCFG_11 DMAC.CHCFG_11
-#define DMACCHITVL_11 DMAC.CHITVL_11
-#define DMACCHEXT_11 DMAC.CHEXT_11
-#define DMACNXLA_11 DMAC.NXLA_11
-#define DMACCRLA_11 DMAC.CRLA_11
-#define DMACN0SA_12 DMAC.N0SA_12
-#define DMACN0DA_12 DMAC.N0DA_12
-#define DMACN0TB_12 DMAC.N0TB_12
-#define DMACN1SA_12 DMAC.N1SA_12
-#define DMACN1DA_12 DMAC.N1DA_12
-#define DMACN1TB_12 DMAC.N1TB_12
-#define DMACCRSA_12 DMAC.CRSA_12
-#define DMACCRDA_12 DMAC.CRDA_12
-#define DMACCRTB_12 DMAC.CRTB_12
-#define DMACCHSTAT_12 DMAC.CHSTAT_12
-#define DMACCHCTRL_12 DMAC.CHCTRL_12
-#define DMACCHCFG_12 DMAC.CHCFG_12
-#define DMACCHITVL_12 DMAC.CHITVL_12
-#define DMACCHEXT_12 DMAC.CHEXT_12
-#define DMACNXLA_12 DMAC.NXLA_12
-#define DMACCRLA_12 DMAC.CRLA_12
-#define DMACN0SA_13 DMAC.N0SA_13
-#define DMACN0DA_13 DMAC.N0DA_13
-#define DMACN0TB_13 DMAC.N0TB_13
-#define DMACN1SA_13 DMAC.N1SA_13
-#define DMACN1DA_13 DMAC.N1DA_13
-#define DMACN1TB_13 DMAC.N1TB_13
-#define DMACCRSA_13 DMAC.CRSA_13
-#define DMACCRDA_13 DMAC.CRDA_13
-#define DMACCRTB_13 DMAC.CRTB_13
-#define DMACCHSTAT_13 DMAC.CHSTAT_13
-#define DMACCHCTRL_13 DMAC.CHCTRL_13
-#define DMACCHCFG_13 DMAC.CHCFG_13
-#define DMACCHITVL_13 DMAC.CHITVL_13
-#define DMACCHEXT_13 DMAC.CHEXT_13
-#define DMACNXLA_13 DMAC.NXLA_13
-#define DMACCRLA_13 DMAC.CRLA_13
-#define DMACN0SA_14 DMAC.N0SA_14
-#define DMACN0DA_14 DMAC.N0DA_14
-#define DMACN0TB_14 DMAC.N0TB_14
-#define DMACN1SA_14 DMAC.N1SA_14
-#define DMACN1DA_14 DMAC.N1DA_14
-#define DMACN1TB_14 DMAC.N1TB_14
-#define DMACCRSA_14 DMAC.CRSA_14
-#define DMACCRDA_14 DMAC.CRDA_14
-#define DMACCRTB_14 DMAC.CRTB_14
-#define DMACCHSTAT_14 DMAC.CHSTAT_14
-#define DMACCHCTRL_14 DMAC.CHCTRL_14
-#define DMACCHCFG_14 DMAC.CHCFG_14
-#define DMACCHITVL_14 DMAC.CHITVL_14
-#define DMACCHEXT_14 DMAC.CHEXT_14
-#define DMACNXLA_14 DMAC.NXLA_14
-#define DMACCRLA_14 DMAC.CRLA_14
-#define DMACN0SA_15 DMAC.N0SA_15
-#define DMACN0DA_15 DMAC.N0DA_15
-#define DMACN0TB_15 DMAC.N0TB_15
-#define DMACN1SA_15 DMAC.N1SA_15
-#define DMACN1DA_15 DMAC.N1DA_15
-#define DMACN1TB_15 DMAC.N1TB_15
-#define DMACCRSA_15 DMAC.CRSA_15
-#define DMACCRDA_15 DMAC.CRDA_15
-#define DMACCRTB_15 DMAC.CRTB_15
-#define DMACCHSTAT_15 DMAC.CHSTAT_15
-#define DMACCHCTRL_15 DMAC.CHCTRL_15
-#define DMACCHCFG_15 DMAC.CHCFG_15
-#define DMACCHITVL_15 DMAC.CHITVL_15
-#define DMACCHEXT_15 DMAC.CHEXT_15
-#define DMACNXLA_15 DMAC.NXLA_15
-#define DMACCRLA_15 DMAC.CRLA_15
-#define DMACDCTRL_8_15 DMAC.DCTRL_8_15
-#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15
-#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15
-#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15
-#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15
-#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15
-#define DMACDMARS0 DMAC.DMARS0
-#define DMACDMARS1 DMAC.DMARS1
-#define DMACDMARS2 DMAC.DMARS2
-#define DMACDMARS3 DMAC.DMARS3
-#define DMACDMARS4 DMAC.DMARS4
-#define DMACDMARS5 DMAC.DMARS5
-#define DMACDMARS6 DMAC.DMARS6
-#define DMACDMARS7 DMAC.DMARS7
+typedef struct st_dmac
+{
+                                                           /* DMAC             */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_0;                                 /*  N0SA_0          */
+    volatile uint32_t  N0DA_0;                                 /*  N0DA_0          */
+    volatile uint32_t  N0TB_0;                                 /*  N0TB_0          */
+    volatile uint32_t  N1SA_0;                                 /*  N1SA_0          */
+    volatile uint32_t  N1DA_0;                                 /*  N1DA_0          */
+    volatile uint32_t  N1TB_0;                                 /*  N1TB_0          */
+    volatile uint32_t  CRSA_0;                                 /*  CRSA_0          */
+    volatile uint32_t  CRDA_0;                                 /*  CRDA_0          */
+    volatile uint32_t  CRTB_0;                                 /*  CRTB_0          */
+    volatile uint32_t  CHSTAT_0;                               /*  CHSTAT_0        */
+    volatile uint32_t  CHCTRL_0;                               /*  CHCTRL_0        */
+    volatile uint32_t  CHCFG_0;                                /*  CHCFG_0         */
+    volatile uint32_t  CHITVL_0;                               /*  CHITVL_0        */
+    volatile uint32_t  CHEXT_0;                                /*  CHEXT_0         */
+    volatile uint32_t  NXLA_0;                                 /*  NXLA_0          */
+    volatile uint32_t  CRLA_0;                                 /*  CRLA_0          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_1;                                 /*  N0SA_1          */
+    volatile uint32_t  N0DA_1;                                 /*  N0DA_1          */
+    volatile uint32_t  N0TB_1;                                 /*  N0TB_1          */
+    volatile uint32_t  N1SA_1;                                 /*  N1SA_1          */
+    volatile uint32_t  N1DA_1;                                 /*  N1DA_1          */
+    volatile uint32_t  N1TB_1;                                 /*  N1TB_1          */
+    volatile uint32_t  CRSA_1;                                 /*  CRSA_1          */
+    volatile uint32_t  CRDA_1;                                 /*  CRDA_1          */
+    volatile uint32_t  CRTB_1;                                 /*  CRTB_1          */
+    volatile uint32_t  CHSTAT_1;                               /*  CHSTAT_1        */
+    volatile uint32_t  CHCTRL_1;                               /*  CHCTRL_1        */
+    volatile uint32_t  CHCFG_1;                                /*  CHCFG_1         */
+    volatile uint32_t  CHITVL_1;                               /*  CHITVL_1        */
+    volatile uint32_t  CHEXT_1;                                /*  CHEXT_1         */
+    volatile uint32_t  NXLA_1;                                 /*  NXLA_1          */
+    volatile uint32_t  CRLA_1;                                 /*  CRLA_1          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_2;                                 /*  N0SA_2          */
+    volatile uint32_t  N0DA_2;                                 /*  N0DA_2          */
+    volatile uint32_t  N0TB_2;                                 /*  N0TB_2          */
+    volatile uint32_t  N1SA_2;                                 /*  N1SA_2          */
+    volatile uint32_t  N1DA_2;                                 /*  N1DA_2          */
+    volatile uint32_t  N1TB_2;                                 /*  N1TB_2          */
+    volatile uint32_t  CRSA_2;                                 /*  CRSA_2          */
+    volatile uint32_t  CRDA_2;                                 /*  CRDA_2          */
+    volatile uint32_t  CRTB_2;                                 /*  CRTB_2          */
+    volatile uint32_t  CHSTAT_2;                               /*  CHSTAT_2        */
+    volatile uint32_t  CHCTRL_2;                               /*  CHCTRL_2        */
+    volatile uint32_t  CHCFG_2;                                /*  CHCFG_2         */
+    volatile uint32_t  CHITVL_2;                               /*  CHITVL_2        */
+    volatile uint32_t  CHEXT_2;                                /*  CHEXT_2         */
+    volatile uint32_t  NXLA_2;                                 /*  NXLA_2          */
+    volatile uint32_t  CRLA_2;                                 /*  CRLA_2          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_3;                                 /*  N0SA_3          */
+    volatile uint32_t  N0DA_3;                                 /*  N0DA_3          */
+    volatile uint32_t  N0TB_3;                                 /*  N0TB_3          */
+    volatile uint32_t  N1SA_3;                                 /*  N1SA_3          */
+    volatile uint32_t  N1DA_3;                                 /*  N1DA_3          */
+    volatile uint32_t  N1TB_3;                                 /*  N1TB_3          */
+    volatile uint32_t  CRSA_3;                                 /*  CRSA_3          */
+    volatile uint32_t  CRDA_3;                                 /*  CRDA_3          */
+    volatile uint32_t  CRTB_3;                                 /*  CRTB_3          */
+    volatile uint32_t  CHSTAT_3;                               /*  CHSTAT_3        */
+    volatile uint32_t  CHCTRL_3;                               /*  CHCTRL_3        */
+    volatile uint32_t  CHCFG_3;                                /*  CHCFG_3         */
+    volatile uint32_t  CHITVL_3;                               /*  CHITVL_3        */
+    volatile uint32_t  CHEXT_3;                                /*  CHEXT_3         */
+    volatile uint32_t  NXLA_3;                                 /*  NXLA_3          */
+    volatile uint32_t  CRLA_3;                                 /*  CRLA_3          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_4;                                 /*  N0SA_4          */
+    volatile uint32_t  N0DA_4;                                 /*  N0DA_4          */
+    volatile uint32_t  N0TB_4;                                 /*  N0TB_4          */
+    volatile uint32_t  N1SA_4;                                 /*  N1SA_4          */
+    volatile uint32_t  N1DA_4;                                 /*  N1DA_4          */
+    volatile uint32_t  N1TB_4;                                 /*  N1TB_4          */
+    volatile uint32_t  CRSA_4;                                 /*  CRSA_4          */
+    volatile uint32_t  CRDA_4;                                 /*  CRDA_4          */
+    volatile uint32_t  CRTB_4;                                 /*  CRTB_4          */
+    volatile uint32_t  CHSTAT_4;                               /*  CHSTAT_4        */
+    volatile uint32_t  CHCTRL_4;                               /*  CHCTRL_4        */
+    volatile uint32_t  CHCFG_4;                                /*  CHCFG_4         */
+    volatile uint32_t  CHITVL_4;                               /*  CHITVL_4        */
+    volatile uint32_t  CHEXT_4;                                /*  CHEXT_4         */
+    volatile uint32_t  NXLA_4;                                 /*  NXLA_4          */
+    volatile uint32_t  CRLA_4;                                 /*  CRLA_4          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_5;                                 /*  N0SA_5          */
+    volatile uint32_t  N0DA_5;                                 /*  N0DA_5          */
+    volatile uint32_t  N0TB_5;                                 /*  N0TB_5          */
+    volatile uint32_t  N1SA_5;                                 /*  N1SA_5          */
+    volatile uint32_t  N1DA_5;                                 /*  N1DA_5          */
+    volatile uint32_t  N1TB_5;                                 /*  N1TB_5          */
+    volatile uint32_t  CRSA_5;                                 /*  CRSA_5          */
+    volatile uint32_t  CRDA_5;                                 /*  CRDA_5          */
+    volatile uint32_t  CRTB_5;                                 /*  CRTB_5          */
+    volatile uint32_t  CHSTAT_5;                               /*  CHSTAT_5        */
+    volatile uint32_t  CHCTRL_5;                               /*  CHCTRL_5        */
+    volatile uint32_t  CHCFG_5;                                /*  CHCFG_5         */
+    volatile uint32_t  CHITVL_5;                               /*  CHITVL_5        */
+    volatile uint32_t  CHEXT_5;                                /*  CHEXT_5         */
+    volatile uint32_t  NXLA_5;                                 /*  NXLA_5          */
+    volatile uint32_t  CRLA_5;                                 /*  CRLA_5          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_6;                                 /*  N0SA_6          */
+    volatile uint32_t  N0DA_6;                                 /*  N0DA_6          */
+    volatile uint32_t  N0TB_6;                                 /*  N0TB_6          */
+    volatile uint32_t  N1SA_6;                                 /*  N1SA_6          */
+    volatile uint32_t  N1DA_6;                                 /*  N1DA_6          */
+    volatile uint32_t  N1TB_6;                                 /*  N1TB_6          */
+    volatile uint32_t  CRSA_6;                                 /*  CRSA_6          */
+    volatile uint32_t  CRDA_6;                                 /*  CRDA_6          */
+    volatile uint32_t  CRTB_6;                                 /*  CRTB_6          */
+    volatile uint32_t  CHSTAT_6;                               /*  CHSTAT_6        */
+    volatile uint32_t  CHCTRL_6;                               /*  CHCTRL_6        */
+    volatile uint32_t  CHCFG_6;                                /*  CHCFG_6         */
+    volatile uint32_t  CHITVL_6;                               /*  CHITVL_6        */
+    volatile uint32_t  CHEXT_6;                                /*  CHEXT_6         */
+    volatile uint32_t  NXLA_6;                                 /*  NXLA_6          */
+    volatile uint32_t  CRLA_6;                                 /*  CRLA_6          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_7;                                 /*  N0SA_7          */
+    volatile uint32_t  N0DA_7;                                 /*  N0DA_7          */
+    volatile uint32_t  N0TB_7;                                 /*  N0TB_7          */
+    volatile uint32_t  N1SA_7;                                 /*  N1SA_7          */
+    volatile uint32_t  N1DA_7;                                 /*  N1DA_7          */
+    volatile uint32_t  N1TB_7;                                 /*  N1TB_7          */
+    volatile uint32_t  CRSA_7;                                 /*  CRSA_7          */
+    volatile uint32_t  CRDA_7;                                 /*  CRDA_7          */
+    volatile uint32_t  CRTB_7;                                 /*  CRTB_7          */
+    volatile uint32_t  CHSTAT_7;                               /*  CHSTAT_7        */
+    volatile uint32_t  CHCTRL_7;                               /*  CHCTRL_7        */
+    volatile uint32_t  CHCFG_7;                                /*  CHCFG_7         */
+    volatile uint32_t  CHITVL_7;                               /*  CHITVL_7        */
+    volatile uint32_t  CHEXT_7;                                /*  CHEXT_7         */
+    volatile uint32_t  NXLA_7;                                 /*  NXLA_7          */
+    volatile uint32_t  CRLA_7;                                 /*  CRLA_7          */
+
+/* end of struct st_dmac_n */
+    volatile uint8_t   dummy187[256];                          /*                  */
+
+/* start of struct st_dmaccommon_n */
+    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
+    volatile uint8_t   dummy188[12];                           /*                  */
+    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
+    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
+    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
+    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
+    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
+
+/* end of struct st_dmaccommon_n */
+    volatile uint8_t   dummy189[220];                          /*                  */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_8;                                 /*  N0SA_8          */
+    volatile uint32_t  N0DA_8;                                 /*  N0DA_8          */
+    volatile uint32_t  N0TB_8;                                 /*  N0TB_8          */
+    volatile uint32_t  N1SA_8;                                 /*  N1SA_8          */
+    volatile uint32_t  N1DA_8;                                 /*  N1DA_8          */
+    volatile uint32_t  N1TB_8;                                 /*  N1TB_8          */
+    volatile uint32_t  CRSA_8;                                 /*  CRSA_8          */
+    volatile uint32_t  CRDA_8;                                 /*  CRDA_8          */
+    volatile uint32_t  CRTB_8;                                 /*  CRTB_8          */
+    volatile uint32_t  CHSTAT_8;                               /*  CHSTAT_8        */
+    volatile uint32_t  CHCTRL_8;                               /*  CHCTRL_8        */
+    volatile uint32_t  CHCFG_8;                                /*  CHCFG_8         */
+    volatile uint32_t  CHITVL_8;                               /*  CHITVL_8        */
+    volatile uint32_t  CHEXT_8;                                /*  CHEXT_8         */
+    volatile uint32_t  NXLA_8;                                 /*  NXLA_8          */
+    volatile uint32_t  CRLA_8;                                 /*  CRLA_8          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_9;                                 /*  N0SA_9          */
+    volatile uint32_t  N0DA_9;                                 /*  N0DA_9          */
+    volatile uint32_t  N0TB_9;                                 /*  N0TB_9          */
+    volatile uint32_t  N1SA_9;                                 /*  N1SA_9          */
+    volatile uint32_t  N1DA_9;                                 /*  N1DA_9          */
+    volatile uint32_t  N1TB_9;                                 /*  N1TB_9          */
+    volatile uint32_t  CRSA_9;                                 /*  CRSA_9          */
+    volatile uint32_t  CRDA_9;                                 /*  CRDA_9          */
+    volatile uint32_t  CRTB_9;                                 /*  CRTB_9          */
+    volatile uint32_t  CHSTAT_9;                               /*  CHSTAT_9        */
+    volatile uint32_t  CHCTRL_9;                               /*  CHCTRL_9        */
+    volatile uint32_t  CHCFG_9;                                /*  CHCFG_9         */
+    volatile uint32_t  CHITVL_9;                               /*  CHITVL_9        */
+    volatile uint32_t  CHEXT_9;                                /*  CHEXT_9         */
+    volatile uint32_t  NXLA_9;                                 /*  NXLA_9          */
+    volatile uint32_t  CRLA_9;                                 /*  CRLA_9          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_10;                                /*  N0SA_10         */
+    volatile uint32_t  N0DA_10;                                /*  N0DA_10         */
+    volatile uint32_t  N0TB_10;                                /*  N0TB_10         */
+    volatile uint32_t  N1SA_10;                                /*  N1SA_10         */
+    volatile uint32_t  N1DA_10;                                /*  N1DA_10         */
+    volatile uint32_t  N1TB_10;                                /*  N1TB_10         */
+    volatile uint32_t  CRSA_10;                                /*  CRSA_10         */
+    volatile uint32_t  CRDA_10;                                /*  CRDA_10         */
+    volatile uint32_t  CRTB_10;                                /*  CRTB_10         */
+    volatile uint32_t  CHSTAT_10;                              /*  CHSTAT_10       */
+    volatile uint32_t  CHCTRL_10;                              /*  CHCTRL_10       */
+    volatile uint32_t  CHCFG_10;                               /*  CHCFG_10        */
+    volatile uint32_t  CHITVL_10;                              /*  CHITVL_10       */
+    volatile uint32_t  CHEXT_10;                               /*  CHEXT_10        */
+    volatile uint32_t  NXLA_10;                                /*  NXLA_10         */
+    volatile uint32_t  CRLA_10;                                /*  CRLA_10         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_11;                                /*  N0SA_11         */
+    volatile uint32_t  N0DA_11;                                /*  N0DA_11         */
+    volatile uint32_t  N0TB_11;                                /*  N0TB_11         */
+    volatile uint32_t  N1SA_11;                                /*  N1SA_11         */
+    volatile uint32_t  N1DA_11;                                /*  N1DA_11         */
+    volatile uint32_t  N1TB_11;                                /*  N1TB_11         */
+    volatile uint32_t  CRSA_11;                                /*  CRSA_11         */
+    volatile uint32_t  CRDA_11;                                /*  CRDA_11         */
+    volatile uint32_t  CRTB_11;                                /*  CRTB_11         */
+    volatile uint32_t  CHSTAT_11;                              /*  CHSTAT_11       */
+    volatile uint32_t  CHCTRL_11;                              /*  CHCTRL_11       */
+    volatile uint32_t  CHCFG_11;                               /*  CHCFG_11        */
+    volatile uint32_t  CHITVL_11;                              /*  CHITVL_11       */
+    volatile uint32_t  CHEXT_11;                               /*  CHEXT_11        */
+    volatile uint32_t  NXLA_11;                                /*  NXLA_11         */
+    volatile uint32_t  CRLA_11;                                /*  CRLA_11         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_12;                                /*  N0SA_12         */
+    volatile uint32_t  N0DA_12;                                /*  N0DA_12         */
+    volatile uint32_t  N0TB_12;                                /*  N0TB_12         */
+    volatile uint32_t  N1SA_12;                                /*  N1SA_12         */
+    volatile uint32_t  N1DA_12;                                /*  N1DA_12         */
+    volatile uint32_t  N1TB_12;                                /*  N1TB_12         */
+    volatile uint32_t  CRSA_12;                                /*  CRSA_12         */
+    volatile uint32_t  CRDA_12;                                /*  CRDA_12         */
+    volatile uint32_t  CRTB_12;                                /*  CRTB_12         */
+    volatile uint32_t  CHSTAT_12;                              /*  CHSTAT_12       */
+    volatile uint32_t  CHCTRL_12;                              /*  CHCTRL_12       */
+    volatile uint32_t  CHCFG_12;                               /*  CHCFG_12        */
+    volatile uint32_t  CHITVL_12;                              /*  CHITVL_12       */
+    volatile uint32_t  CHEXT_12;                               /*  CHEXT_12        */
+    volatile uint32_t  NXLA_12;                                /*  NXLA_12         */
+    volatile uint32_t  CRLA_12;                                /*  CRLA_12         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_13;                                /*  N0SA_13         */
+    volatile uint32_t  N0DA_13;                                /*  N0DA_13         */
+    volatile uint32_t  N0TB_13;                                /*  N0TB_13         */
+    volatile uint32_t  N1SA_13;                                /*  N1SA_13         */
+    volatile uint32_t  N1DA_13;                                /*  N1DA_13         */
+    volatile uint32_t  N1TB_13;                                /*  N1TB_13         */
+    volatile uint32_t  CRSA_13;                                /*  CRSA_13         */
+    volatile uint32_t  CRDA_13;                                /*  CRDA_13         */
+    volatile uint32_t  CRTB_13;                                /*  CRTB_13         */
+    volatile uint32_t  CHSTAT_13;                              /*  CHSTAT_13       */
+    volatile uint32_t  CHCTRL_13;                              /*  CHCTRL_13       */
+    volatile uint32_t  CHCFG_13;                               /*  CHCFG_13        */
+    volatile uint32_t  CHITVL_13;                              /*  CHITVL_13       */
+    volatile uint32_t  CHEXT_13;                               /*  CHEXT_13        */
+    volatile uint32_t  NXLA_13;                                /*  NXLA_13         */
+    volatile uint32_t  CRLA_13;                                /*  CRLA_13         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_14;                                /*  N0SA_14         */
+    volatile uint32_t  N0DA_14;                                /*  N0DA_14         */
+    volatile uint32_t  N0TB_14;                                /*  N0TB_14         */
+    volatile uint32_t  N1SA_14;                                /*  N1SA_14         */
+    volatile uint32_t  N1DA_14;                                /*  N1DA_14         */
+    volatile uint32_t  N1TB_14;                                /*  N1TB_14         */
+    volatile uint32_t  CRSA_14;                                /*  CRSA_14         */
+    volatile uint32_t  CRDA_14;                                /*  CRDA_14         */
+    volatile uint32_t  CRTB_14;                                /*  CRTB_14         */
+    volatile uint32_t  CHSTAT_14;                              /*  CHSTAT_14       */
+    volatile uint32_t  CHCTRL_14;                              /*  CHCTRL_14       */
+    volatile uint32_t  CHCFG_14;                               /*  CHCFG_14        */
+    volatile uint32_t  CHITVL_14;                              /*  CHITVL_14       */
+    volatile uint32_t  CHEXT_14;                               /*  CHEXT_14        */
+    volatile uint32_t  NXLA_14;                                /*  NXLA_14         */
+    volatile uint32_t  CRLA_14;                                /*  CRLA_14         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_15;                                /*  N0SA_15         */
+    volatile uint32_t  N0DA_15;                                /*  N0DA_15         */
+    volatile uint32_t  N0TB_15;                                /*  N0TB_15         */
+    volatile uint32_t  N1SA_15;                                /*  N1SA_15         */
+    volatile uint32_t  N1DA_15;                                /*  N1DA_15         */
+    volatile uint32_t  N1TB_15;                                /*  N1TB_15         */
+    volatile uint32_t  CRSA_15;                                /*  CRSA_15         */
+    volatile uint32_t  CRDA_15;                                /*  CRDA_15         */
+    volatile uint32_t  CRTB_15;                                /*  CRTB_15         */
+    volatile uint32_t  CHSTAT_15;                              /*  CHSTAT_15       */
+    volatile uint32_t  CHCTRL_15;                              /*  CHCTRL_15       */
+    volatile uint32_t  CHCFG_15;                               /*  CHCFG_15        */
+    volatile uint32_t  CHITVL_15;                              /*  CHITVL_15       */
+    volatile uint32_t  CHEXT_15;                               /*  CHEXT_15        */
+    volatile uint32_t  NXLA_15;                                /*  NXLA_15         */
+    volatile uint32_t  CRLA_15;                                /*  CRLA_15         */
+
+/* end of struct st_dmac_n */
+    volatile uint8_t   dummy190[256];                          /*                  */
+
+/* start of struct st_dmaccommon_n */
+    volatile uint32_t  DCTRL_8_15;                             /*  DCTRL_8_15      */
+    volatile uint8_t   dummy191[12];                           /*                  */
+    volatile uint32_t  DSTAT_EN_8_15;                          /*  DSTAT_EN_8_15   */
+    volatile uint32_t  DSTAT_ER_8_15;                          /*  DSTAT_ER_8_15   */
+    volatile uint32_t  DSTAT_END_8_15;                         /*  DSTAT_END_8_15  */
+    volatile uint32_t  DSTAT_TC_8_15;                          /*  DSTAT_TC_8_15   */
+    volatile uint32_t  DSTAT_SUS_8_15;                         /*  DSTAT_SUS_8_15  */
+
+/* end of struct st_dmaccommon_n */
+    volatile uint8_t   dummy192[350095580];                    /*                  */
+    volatile uint32_t  DMARS0;                                 /*  DMARS0          */
+    volatile uint32_t  DMARS1;                                 /*  DMARS1          */
+    volatile uint32_t  DMARS2;                                 /*  DMARS2          */
+    volatile uint32_t  DMARS3;                                 /*  DMARS3          */
+    volatile uint32_t  DMARS4;                                 /*  DMARS4          */
+    volatile uint32_t  DMARS5;                                 /*  DMARS5          */
+    volatile uint32_t  DMARS6;                                 /*  DMARS6          */
+    volatile uint32_t  DMARS7;                                 /*  DMARS7          */
+} r_io_dmac_t;
+
+
+typedef struct st_dmaccommon_n
+{
+ 
+    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
+    volatile uint8_t   dummy1[12];                             /*                  */
+    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
+    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
+    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
+    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
+    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
+} r_io_dmaccommon_n_t;
+
+
+typedef struct st_dmac_n
+{
+ 
+    volatile uint32_t  N0SA_n;                                 /*  N0SA_n          */
+    volatile uint32_t  N0DA_n;                                 /*  N0DA_n          */
+    volatile uint32_t  N0TB_n;                                 /*  N0TB_n          */
+    volatile uint32_t  N1SA_n;                                 /*  N1SA_n          */
+    volatile uint32_t  N1DA_n;                                 /*  N1DA_n          */
+    volatile uint32_t  N1TB_n;                                 /*  N1TB_n          */
+    volatile uint32_t  CRSA_n;                                 /*  CRSA_n          */
+    volatile uint32_t  CRDA_n;                                 /*  CRDA_n          */
+    volatile uint32_t  CRTB_n;                                 /*  CRTB_n          */
+    volatile uint32_t  CHSTAT_n;                               /*  CHSTAT_n        */
+    volatile uint32_t  CHCTRL_n;                               /*  CHCTRL_n        */
+    volatile uint32_t  CHCFG_n;                                /*  CHCFG_n         */
+    volatile uint32_t  CHITVL_n;                               /*  CHITVL_n        */
+    volatile uint32_t  CHEXT_n;                                /*  CHEXT_n         */
+    volatile uint32_t  NXLA_n;                                 /*  NXLA_n          */
+    volatile uint32_t  CRLA_n;                                 /*  CRLA_n          */
+} r_io_dmac_n_t;
+
+
+/* Channel array defines of DMAC (2)*/
+#ifdef  DECLARE_DMACmm_CHANNELS
+volatile struct st_dmars_mm*  DMACmm[ DMACmm_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DMACmm_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DMACmm_CHANNELS */
+
+#ifdef  DECLARE_DMACn_CHANNELS
+volatile struct st_dmac_n*  DMACn[ DMACn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DMACn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DMACn_CHANNELS */
+
+#ifdef  DECLARE_DMACnn_CHANNELS
+volatile struct st_dmaccommon_n*  DMACnn[ DMACnn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DMACnn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DMACnn_CHANNELS */
+/* End of channel array defines of DMAC (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,40 +18,289 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : dvdec_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef DVDEC_IODEFINE_H
 #define DVDEC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_dvdec
-{                                                          /* DVDEC            */
+#define DVDEC1  (*(struct st_dvdec   *)0xFCFFA008uL) /* DVDEC1 */
+#define DVDEC0  (*(struct st_dvdec   *)0xFCFFB808uL) /* DVDEC0 */
+
+
+/* Start of channel array defines of DVDEC */
+
+/* Channel array defines of DVDEC */
+/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
+#define DVDEC_COUNT  (2)
+#define DVDEC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DVDEC0, &DVDEC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of DVDEC */
+
+
+#define ADCCR1_1 (DVDEC1.ADCCR1)
+#define TGCR1_1 (DVDEC1.TGCR1)
+#define TGCR2_1 (DVDEC1.TGCR2)
+#define TGCR3_1 (DVDEC1.TGCR3)
+#define SYNSCR1_1 (DVDEC1.SYNSCR1)
+#define SYNSCR2_1 (DVDEC1.SYNSCR2)
+#define SYNSCR3_1 (DVDEC1.SYNSCR3)
+#define SYNSCR4_1 (DVDEC1.SYNSCR4)
+#define SYNSCR5_1 (DVDEC1.SYNSCR5)
+#define HAFCCR1_1 (DVDEC1.HAFCCR1)
+#define HAFCCR2_1 (DVDEC1.HAFCCR2)
+#define HAFCCR3_1 (DVDEC1.HAFCCR3)
+#define VCDWCR1_1 (DVDEC1.VCDWCR1)
+#define DCPCR1_1 (DVDEC1.DCPCR1)
+#define DCPCR2_1 (DVDEC1.DCPCR2)
+#define DCPCR3_1 (DVDEC1.DCPCR3)
+#define DCPCR4_1 (DVDEC1.DCPCR4)
+#define DCPCR5_1 (DVDEC1.DCPCR5)
+#define DCPCR6_1 (DVDEC1.DCPCR6)
+#define DCPCR7_1 (DVDEC1.DCPCR7)
+#define DCPCR8_1 (DVDEC1.DCPCR8)
+#define NSDCR_1 (DVDEC1.NSDCR)
+#define BTLCR_1 (DVDEC1.BTLCR)
+#define BTGPCR_1 (DVDEC1.BTGPCR)
+#define ACCCR1_1 (DVDEC1.ACCCR1)
+#define ACCCR2_1 (DVDEC1.ACCCR2)
+#define ACCCR3_1 (DVDEC1.ACCCR3)
+#define TINTCR_1 (DVDEC1.TINTCR)
+#define YCDCR_1 (DVDEC1.YCDCR)
+#define AGCCR1_1 (DVDEC1.AGCCR1)
+#define AGCCR2_1 (DVDEC1.AGCCR2)
+#define PKLIMITCR_1 (DVDEC1.PKLIMITCR)
+#define RGORCR1_1 (DVDEC1.RGORCR1)
+#define RGORCR2_1 (DVDEC1.RGORCR2)
+#define RGORCR3_1 (DVDEC1.RGORCR3)
+#define RGORCR4_1 (DVDEC1.RGORCR4)
+#define RGORCR5_1 (DVDEC1.RGORCR5)
+#define RGORCR6_1 (DVDEC1.RGORCR6)
+#define RGORCR7_1 (DVDEC1.RGORCR7)
+#define AFCPFCR_1 (DVDEC1.AFCPFCR)
+#define RUPDCR_1 (DVDEC1.RUPDCR)
+#define VSYNCSR_1 (DVDEC1.VSYNCSR)
+#define HSYNCSR_1 (DVDEC1.HSYNCSR)
+#define DCPSR1_1 (DVDEC1.DCPSR1)
+#define DCPSR2_1 (DVDEC1.DCPSR2)
+#define NSDSR_1 (DVDEC1.NSDSR)
+#define CROMASR1_1 (DVDEC1.CROMASR1)
+#define CROMASR2_1 (DVDEC1.CROMASR2)
+#define SYNCSSR_1 (DVDEC1.SYNCSSR)
+#define AGCCSR1_1 (DVDEC1.AGCCSR1)
+#define AGCCSR2_1 (DVDEC1.AGCCSR2)
+#define YCSCR3_1 (DVDEC1.YCSCR3)
+#define YCSCR4_1 (DVDEC1.YCSCR4)
+#define YCSCR5_1 (DVDEC1.YCSCR5)
+#define YCSCR6_1 (DVDEC1.YCSCR6)
+#define YCSCR7_1 (DVDEC1.YCSCR7)
+#define YCSCR8_1 (DVDEC1.YCSCR8)
+#define YCSCR9_1 (DVDEC1.YCSCR9)
+#define YCSCR11_1 (DVDEC1.YCSCR11)
+#define YCSCR12_1 (DVDEC1.YCSCR12)
+#define DCPCR9_1 (DVDEC1.DCPCR9)
+#define YCTWA_F0_1 (DVDEC1.YCTWA_F0)
+#define YCTWA_F1_1 (DVDEC1.YCTWA_F1)
+#define YCTWA_F2_1 (DVDEC1.YCTWA_F2)
+#define YCTWA_F3_1 (DVDEC1.YCTWA_F3)
+#define YCTWA_F4_1 (DVDEC1.YCTWA_F4)
+#define YCTWA_F5_1 (DVDEC1.YCTWA_F5)
+#define YCTWA_F6_1 (DVDEC1.YCTWA_F6)
+#define YCTWA_F7_1 (DVDEC1.YCTWA_F7)
+#define YCTWA_F8_1 (DVDEC1.YCTWA_F8)
+#define YCTWB_F0_1 (DVDEC1.YCTWB_F0)
+#define YCTWB_F1_1 (DVDEC1.YCTWB_F1)
+#define YCTWB_F2_1 (DVDEC1.YCTWB_F2)
+#define YCTWB_F3_1 (DVDEC1.YCTWB_F3)
+#define YCTWB_F4_1 (DVDEC1.YCTWB_F4)
+#define YCTWB_F5_1 (DVDEC1.YCTWB_F5)
+#define YCTWB_F6_1 (DVDEC1.YCTWB_F6)
+#define YCTWB_F7_1 (DVDEC1.YCTWB_F7)
+#define YCTWB_F8_1 (DVDEC1.YCTWB_F8)
+#define YCTNA_F0_1 (DVDEC1.YCTNA_F0)
+#define YCTNA_F1_1 (DVDEC1.YCTNA_F1)
+#define YCTNA_F2_1 (DVDEC1.YCTNA_F2)
+#define YCTNA_F3_1 (DVDEC1.YCTNA_F3)
+#define YCTNA_F4_1 (DVDEC1.YCTNA_F4)
+#define YCTNA_F5_1 (DVDEC1.YCTNA_F5)
+#define YCTNA_F6_1 (DVDEC1.YCTNA_F6)
+#define YCTNA_F7_1 (DVDEC1.YCTNA_F7)
+#define YCTNA_F8_1 (DVDEC1.YCTNA_F8)
+#define YCTNB_F0_1 (DVDEC1.YCTNB_F0)
+#define YCTNB_F1_1 (DVDEC1.YCTNB_F1)
+#define YCTNB_F2_1 (DVDEC1.YCTNB_F2)
+#define YCTNB_F3_1 (DVDEC1.YCTNB_F3)
+#define YCTNB_F4_1 (DVDEC1.YCTNB_F4)
+#define YCTNB_F5_1 (DVDEC1.YCTNB_F5)
+#define YCTNB_F6_1 (DVDEC1.YCTNB_F6)
+#define YCTNB_F7_1 (DVDEC1.YCTNB_F7)
+#define YCTNB_F8_1 (DVDEC1.YCTNB_F8)
+#define YGAINCR_1 (DVDEC1.YGAINCR)
+#define CBGAINCR_1 (DVDEC1.CBGAINCR)
+#define CRGAINCR_1 (DVDEC1.CRGAINCR)
+#define PGA_UPDATE_1 (DVDEC1.PGA_UPDATE)
+#define PGACR_1 (DVDEC1.PGACR)
+#define ADCCR2_1 (DVDEC1.ADCCR2)
+#define ADCCR1_0 (DVDEC0.ADCCR1)
+#define TGCR1_0 (DVDEC0.TGCR1)
+#define TGCR2_0 (DVDEC0.TGCR2)
+#define TGCR3_0 (DVDEC0.TGCR3)
+#define SYNSCR1_0 (DVDEC0.SYNSCR1)
+#define SYNSCR2_0 (DVDEC0.SYNSCR2)
+#define SYNSCR3_0 (DVDEC0.SYNSCR3)
+#define SYNSCR4_0 (DVDEC0.SYNSCR4)
+#define SYNSCR5_0 (DVDEC0.SYNSCR5)
+#define HAFCCR1_0 (DVDEC0.HAFCCR1)
+#define HAFCCR2_0 (DVDEC0.HAFCCR2)
+#define HAFCCR3_0 (DVDEC0.HAFCCR3)
+#define VCDWCR1_0 (DVDEC0.VCDWCR1)
+#define DCPCR1_0 (DVDEC0.DCPCR1)
+#define DCPCR2_0 (DVDEC0.DCPCR2)
+#define DCPCR3_0 (DVDEC0.DCPCR3)
+#define DCPCR4_0 (DVDEC0.DCPCR4)
+#define DCPCR5_0 (DVDEC0.DCPCR5)
+#define DCPCR6_0 (DVDEC0.DCPCR6)
+#define DCPCR7_0 (DVDEC0.DCPCR7)
+#define DCPCR8_0 (DVDEC0.DCPCR8)
+#define NSDCR_0 (DVDEC0.NSDCR)
+#define BTLCR_0 (DVDEC0.BTLCR)
+#define BTGPCR_0 (DVDEC0.BTGPCR)
+#define ACCCR1_0 (DVDEC0.ACCCR1)
+#define ACCCR2_0 (DVDEC0.ACCCR2)
+#define ACCCR3_0 (DVDEC0.ACCCR3)
+#define TINTCR_0 (DVDEC0.TINTCR)
+#define YCDCR_0 (DVDEC0.YCDCR)
+#define AGCCR1_0 (DVDEC0.AGCCR1)
+#define AGCCR2_0 (DVDEC0.AGCCR2)
+#define PKLIMITCR_0 (DVDEC0.PKLIMITCR)
+#define RGORCR1_0 (DVDEC0.RGORCR1)
+#define RGORCR2_0 (DVDEC0.RGORCR2)
+#define RGORCR3_0 (DVDEC0.RGORCR3)
+#define RGORCR4_0 (DVDEC0.RGORCR4)
+#define RGORCR5_0 (DVDEC0.RGORCR5)
+#define RGORCR6_0 (DVDEC0.RGORCR6)
+#define RGORCR7_0 (DVDEC0.RGORCR7)
+#define AFCPFCR_0 (DVDEC0.AFCPFCR)
+#define RUPDCR_0 (DVDEC0.RUPDCR)
+#define VSYNCSR_0 (DVDEC0.VSYNCSR)
+#define HSYNCSR_0 (DVDEC0.HSYNCSR)
+#define DCPSR1_0 (DVDEC0.DCPSR1)
+#define DCPSR2_0 (DVDEC0.DCPSR2)
+#define NSDSR_0 (DVDEC0.NSDSR)
+#define CROMASR1_0 (DVDEC0.CROMASR1)
+#define CROMASR2_0 (DVDEC0.CROMASR2)
+#define SYNCSSR_0 (DVDEC0.SYNCSSR)
+#define AGCCSR1_0 (DVDEC0.AGCCSR1)
+#define AGCCSR2_0 (DVDEC0.AGCCSR2)
+#define YCSCR3_0 (DVDEC0.YCSCR3)
+#define YCSCR4_0 (DVDEC0.YCSCR4)
+#define YCSCR5_0 (DVDEC0.YCSCR5)
+#define YCSCR6_0 (DVDEC0.YCSCR6)
+#define YCSCR7_0 (DVDEC0.YCSCR7)
+#define YCSCR8_0 (DVDEC0.YCSCR8)
+#define YCSCR9_0 (DVDEC0.YCSCR9)
+#define YCSCR11_0 (DVDEC0.YCSCR11)
+#define YCSCR12_0 (DVDEC0.YCSCR12)
+#define DCPCR9_0 (DVDEC0.DCPCR9)
+#define YCTWA_F0_0 (DVDEC0.YCTWA_F0)
+#define YCTWA_F1_0 (DVDEC0.YCTWA_F1)
+#define YCTWA_F2_0 (DVDEC0.YCTWA_F2)
+#define YCTWA_F3_0 (DVDEC0.YCTWA_F3)
+#define YCTWA_F4_0 (DVDEC0.YCTWA_F4)
+#define YCTWA_F5_0 (DVDEC0.YCTWA_F5)
+#define YCTWA_F6_0 (DVDEC0.YCTWA_F6)
+#define YCTWA_F7_0 (DVDEC0.YCTWA_F7)
+#define YCTWA_F8_0 (DVDEC0.YCTWA_F8)
+#define YCTWB_F0_0 (DVDEC0.YCTWB_F0)
+#define YCTWB_F1_0 (DVDEC0.YCTWB_F1)
+#define YCTWB_F2_0 (DVDEC0.YCTWB_F2)
+#define YCTWB_F3_0 (DVDEC0.YCTWB_F3)
+#define YCTWB_F4_0 (DVDEC0.YCTWB_F4)
+#define YCTWB_F5_0 (DVDEC0.YCTWB_F5)
+#define YCTWB_F6_0 (DVDEC0.YCTWB_F6)
+#define YCTWB_F7_0 (DVDEC0.YCTWB_F7)
+#define YCTWB_F8_0 (DVDEC0.YCTWB_F8)
+#define YCTNA_F0_0 (DVDEC0.YCTNA_F0)
+#define YCTNA_F1_0 (DVDEC0.YCTNA_F1)
+#define YCTNA_F2_0 (DVDEC0.YCTNA_F2)
+#define YCTNA_F3_0 (DVDEC0.YCTNA_F3)
+#define YCTNA_F4_0 (DVDEC0.YCTNA_F4)
+#define YCTNA_F5_0 (DVDEC0.YCTNA_F5)
+#define YCTNA_F6_0 (DVDEC0.YCTNA_F6)
+#define YCTNA_F7_0 (DVDEC0.YCTNA_F7)
+#define YCTNA_F8_0 (DVDEC0.YCTNA_F8)
+#define YCTNB_F0_0 (DVDEC0.YCTNB_F0)
+#define YCTNB_F1_0 (DVDEC0.YCTNB_F1)
+#define YCTNB_F2_0 (DVDEC0.YCTNB_F2)
+#define YCTNB_F3_0 (DVDEC0.YCTNB_F3)
+#define YCTNB_F4_0 (DVDEC0.YCTNB_F4)
+#define YCTNB_F5_0 (DVDEC0.YCTNB_F5)
+#define YCTNB_F6_0 (DVDEC0.YCTNB_F6)
+#define YCTNB_F7_0 (DVDEC0.YCTNB_F7)
+#define YCTNB_F8_0 (DVDEC0.YCTNB_F8)
+#define YGAINCR_0 (DVDEC0.YGAINCR)
+#define CBGAINCR_0 (DVDEC0.CBGAINCR)
+#define CRGAINCR_0 (DVDEC0.CRGAINCR)
+#define PGA_UPDATE_0 (DVDEC0.PGA_UPDATE)
+#define PGACR_0 (DVDEC0.PGACR)
+#define ADCCR2_0 (DVDEC0.ADCCR2)
+
+#define DVDEC_TGCRn_COUNT (3)
+#define DVDEC_SYNSCRn_COUNT (5)
+#define DVDEC_HAFCCRn_COUNT (3)
+#define DVDEC_DCPCRn_COUNT (8)
+#define DVDEC_ACCCRn_COUNT (3)
+#define DVDEC_AGCCRn_COUNT (2)
+#define DVDEC_RGORCRn_COUNT (7)
+#define DVDEC_DCPSRn_COUNT (2)
+#define DVDEC_CROMASRn_COUNT (2)
+#define DVDEC_AGCCSRn_COUNT (2)
+#define DVDEC_YCSCRn_COUNT (7)
+#define DVDEC_YCTWA_Fn_COUNT (9)
+#define DVDEC_YCTWB_Fn_COUNT (9)
+#define DVDEC_YCTNA_Fn_COUNT (9)
+#define DVDEC_YCTNB_Fn_COUNT (9)
+
+
+typedef struct st_dvdec
+{
+                                                           /* DVDEC            */
     volatile uint16_t ADCCR1;                                 /*  ADCCR1          */
     volatile uint8_t   dummy1[4];                              /*                  */
-#define DVDEC_TGCRn_COUNT 3
+
+/* #define DVDEC_TGCRn_COUNT (3) */
     volatile uint16_t TGCR1;                                  /*  TGCR1           */
     volatile uint16_t TGCR2;                                  /*  TGCR2           */
     volatile uint16_t TGCR3;                                  /*  TGCR3           */
     volatile uint8_t   dummy2[6];                              /*                  */
-#define DVDEC_SYNSCRn_COUNT 5
+
+/* #define DVDEC_SYNSCRn_COUNT (5) */
     volatile uint16_t SYNSCR1;                                /*  SYNSCR1         */
     volatile uint16_t SYNSCR2;                                /*  SYNSCR2         */
     volatile uint16_t SYNSCR3;                                /*  SYNSCR3         */
     volatile uint16_t SYNSCR4;                                /*  SYNSCR4         */
     volatile uint16_t SYNSCR5;                                /*  SYNSCR5         */
-#define DVDEC_HAFCCRn_COUNT 3
+
+/* #define DVDEC_HAFCCRn_COUNT (3) */
     volatile uint16_t HAFCCR1;                                /*  HAFCCR1         */
     volatile uint16_t HAFCCR2;                                /*  HAFCCR2         */
     volatile uint16_t HAFCCR3;                                /*  HAFCCR3         */
     volatile uint16_t VCDWCR1;                                /*  VCDWCR1         */
     volatile uint8_t   dummy3[4];                              /*                  */
-#define DVDEC_DCPCRn_COUNT 8
+
+/* #define DVDEC_DCPCRn_COUNT (8) */
     volatile uint16_t DCPCR1;                                 /*  DCPCR1          */
     volatile uint16_t DCPCR2;                                 /*  DCPCR2          */
     volatile uint16_t DCPCR3;                                 /*  DCPCR3          */
@@ -63,17 +312,20 @@
     volatile uint16_t NSDCR;                                  /*  NSDCR           */
     volatile uint16_t BTLCR;                                  /*  BTLCR           */
     volatile uint16_t BTGPCR;                                 /*  BTGPCR          */
-#define DVDEC_ACCCRn_COUNT 3
+
+/* #define DVDEC_ACCCRn_COUNT (3) */
     volatile uint16_t ACCCR1;                                 /*  ACCCR1          */
     volatile uint16_t ACCCR2;                                 /*  ACCCR2          */
     volatile uint16_t ACCCR3;                                 /*  ACCCR3          */
     volatile uint16_t TINTCR;                                 /*  TINTCR          */
     volatile uint16_t YCDCR;                                  /*  YCDCR           */
-#define DVDEC_AGCCRn_COUNT 2
+
+/* #define DVDEC_AGCCRn_COUNT (2) */
     volatile uint16_t AGCCR1;                                 /*  AGCCR1          */
     volatile uint16_t AGCCR2;                                 /*  AGCCR2          */
     volatile uint16_t PKLIMITCR;                              /*  PKLIMITCR       */
-#define DVDEC_RGORCRn_COUNT 7
+
+/* #define DVDEC_RGORCRn_COUNT (7) */
     volatile uint16_t RGORCR1;                                /*  RGORCR1         */
     volatile uint16_t RGORCR2;                                /*  RGORCR2         */
     volatile uint16_t RGORCR3;                                /*  RGORCR3         */
@@ -86,20 +338,24 @@
     volatile uint16_t RUPDCR;                                 /*  RUPDCR          */
     volatile uint16_t VSYNCSR;                                /*  VSYNCSR         */
     volatile uint16_t HSYNCSR;                                /*  HSYNCSR         */
-#define DVDEC_DCPSRn_COUNT 2
+
+/* #define DVDEC_DCPSRn_COUNT (2) */
     volatile uint16_t DCPSR1;                                 /*  DCPSR1          */
     volatile uint16_t DCPSR2;                                 /*  DCPSR2          */
     volatile uint8_t   dummy5[4];                              /*                  */
     volatile uint16_t NSDSR;                                  /*  NSDSR           */
-#define DVDEC_CROMASRn_COUNT 2
+
+/* #define DVDEC_CROMASRn_COUNT (2) */
     volatile uint16_t CROMASR1;                               /*  CROMASR1        */
     volatile uint16_t CROMASR2;                               /*  CROMASR2        */
     volatile uint16_t SYNCSSR;                                /*  SYNCSSR         */
-#define DVDEC_AGCCSRn_COUNT 2
+
+/* #define DVDEC_AGCCSRn_COUNT (2) */
     volatile uint16_t AGCCSR1;                                /*  AGCCSR1         */
     volatile uint16_t AGCCSR2;                                /*  AGCCSR2         */
     volatile uint8_t   dummy6[108];                            /*                  */
-#define DVDEC_YCSCRn_COUNT 7
+
+/* #define DVDEC_YCSCRn_COUNT (7) */
     volatile uint16_t YCSCR3;                                 /*  YCSCR3          */
     volatile uint16_t YCSCR4;                                 /*  YCSCR4          */
     volatile uint16_t YCSCR5;                                 /*  YCSCR5          */
@@ -113,7 +369,8 @@
     volatile uint8_t   dummy8[104];                            /*                  */
     volatile uint16_t DCPCR9;                                 /*  DCPCR9          */
     volatile uint8_t   dummy9[16];                             /*                  */
-#define DVDEC_YCTWA_Fn_COUNT 9
+
+/* #define DVDEC_YCTWA_Fn_COUNT (9) */
     volatile uint16_t YCTWA_F0;                               /*  YCTWA_F0        */
     volatile uint16_t YCTWA_F1;                               /*  YCTWA_F1        */
     volatile uint16_t YCTWA_F2;                               /*  YCTWA_F2        */
@@ -123,7 +380,8 @@
     volatile uint16_t YCTWA_F6;                               /*  YCTWA_F6        */
     volatile uint16_t YCTWA_F7;                               /*  YCTWA_F7        */
     volatile uint16_t YCTWA_F8;                               /*  YCTWA_F8        */
-#define DVDEC_YCTWB_Fn_COUNT 9
+
+/* #define DVDEC_YCTWB_Fn_COUNT (9) */
     volatile uint16_t YCTWB_F0;                               /*  YCTWB_F0        */
     volatile uint16_t YCTWB_F1;                               /*  YCTWB_F1        */
     volatile uint16_t YCTWB_F2;                               /*  YCTWB_F2        */
@@ -133,7 +391,8 @@
     volatile uint16_t YCTWB_F6;                               /*  YCTWB_F6        */
     volatile uint16_t YCTWB_F7;                               /*  YCTWB_F7        */
     volatile uint16_t YCTWB_F8;                               /*  YCTWB_F8        */
-#define DVDEC_YCTNA_Fn_COUNT 9
+
+/* #define DVDEC_YCTNA_Fn_COUNT (9) */
     volatile uint16_t YCTNA_F0;                               /*  YCTNA_F0        */
     volatile uint16_t YCTNA_F1;                               /*  YCTNA_F1        */
     volatile uint16_t YCTNA_F2;                               /*  YCTNA_F2        */
@@ -143,7 +402,8 @@
     volatile uint16_t YCTNA_F6;                               /*  YCTNA_F6        */
     volatile uint16_t YCTNA_F7;                               /*  YCTNA_F7        */
     volatile uint16_t YCTNA_F8;                               /*  YCTNA_F8        */
-#define DVDEC_YCTNB_Fn_COUNT 9
+
+/* #define DVDEC_YCTNB_Fn_COUNT (9) */
     volatile uint16_t YCTNB_F0;                               /*  YCTNB_F0        */
     volatile uint16_t YCTNB_F1;                               /*  YCTNB_F1        */
     volatile uint16_t YCTNB_F2;                               /*  YCTNB_F2        */
@@ -161,231 +421,21 @@
     volatile uint16_t PGA_UPDATE;                             /*  PGA_UPDATE      */
     volatile uint16_t PGACR;                                  /*  PGACR           */
     volatile uint16_t ADCCR2;                                 /*  ADCCR2          */
-};
-
-
-#define DVDEC1  (*(struct st_dvdec   *)0xFCFFA008uL) /* DVDEC1 */
-#define DVDEC0  (*(struct st_dvdec   *)0xFCFFB808uL) /* DVDEC0 */
-
-
-/* Start of channnel array defines of DVDEC */
-
-/* Channnel array defines of DVDEC */
-/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
-#define DVDEC_COUNT  2
-#define DVDEC_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &DVDEC0, &DVDEC1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of DVDEC */
+} r_io_dvdec_t;
 
 
-#define ADCCR1_1 DVDEC1.ADCCR1
-#define TGCR1_1 DVDEC1.TGCR1
-#define TGCR2_1 DVDEC1.TGCR2
-#define TGCR3_1 DVDEC1.TGCR3
-#define SYNSCR1_1 DVDEC1.SYNSCR1
-#define SYNSCR2_1 DVDEC1.SYNSCR2
-#define SYNSCR3_1 DVDEC1.SYNSCR3
-#define SYNSCR4_1 DVDEC1.SYNSCR4
-#define SYNSCR5_1 DVDEC1.SYNSCR5
-#define HAFCCR1_1 DVDEC1.HAFCCR1
-#define HAFCCR2_1 DVDEC1.HAFCCR2
-#define HAFCCR3_1 DVDEC1.HAFCCR3
-#define VCDWCR1_1 DVDEC1.VCDWCR1
-#define DCPCR1_1 DVDEC1.DCPCR1
-#define DCPCR2_1 DVDEC1.DCPCR2
-#define DCPCR3_1 DVDEC1.DCPCR3
-#define DCPCR4_1 DVDEC1.DCPCR4
-#define DCPCR5_1 DVDEC1.DCPCR5
-#define DCPCR6_1 DVDEC1.DCPCR6
-#define DCPCR7_1 DVDEC1.DCPCR7
-#define DCPCR8_1 DVDEC1.DCPCR8
-#define NSDCR_1 DVDEC1.NSDCR
-#define BTLCR_1 DVDEC1.BTLCR
-#define BTGPCR_1 DVDEC1.BTGPCR
-#define ACCCR1_1 DVDEC1.ACCCR1
-#define ACCCR2_1 DVDEC1.ACCCR2
-#define ACCCR3_1 DVDEC1.ACCCR3
-#define TINTCR_1 DVDEC1.TINTCR
-#define YCDCR_1 DVDEC1.YCDCR
-#define AGCCR1_1 DVDEC1.AGCCR1
-#define AGCCR2_1 DVDEC1.AGCCR2
-#define PKLIMITCR_1 DVDEC1.PKLIMITCR
-#define RGORCR1_1 DVDEC1.RGORCR1
-#define RGORCR2_1 DVDEC1.RGORCR2
-#define RGORCR3_1 DVDEC1.RGORCR3
-#define RGORCR4_1 DVDEC1.RGORCR4
-#define RGORCR5_1 DVDEC1.RGORCR5
-#define RGORCR6_1 DVDEC1.RGORCR6
-#define RGORCR7_1 DVDEC1.RGORCR7
-#define AFCPFCR_1 DVDEC1.AFCPFCR
-#define RUPDCR_1 DVDEC1.RUPDCR
-#define VSYNCSR_1 DVDEC1.VSYNCSR
-#define HSYNCSR_1 DVDEC1.HSYNCSR
-#define DCPSR1_1 DVDEC1.DCPSR1
-#define DCPSR2_1 DVDEC1.DCPSR2
-#define NSDSR_1 DVDEC1.NSDSR
-#define CROMASR1_1 DVDEC1.CROMASR1
-#define CROMASR2_1 DVDEC1.CROMASR2
-#define SYNCSSR_1 DVDEC1.SYNCSSR
-#define AGCCSR1_1 DVDEC1.AGCCSR1
-#define AGCCSR2_1 DVDEC1.AGCCSR2
-#define YCSCR3_1 DVDEC1.YCSCR3
-#define YCSCR4_1 DVDEC1.YCSCR4
-#define YCSCR5_1 DVDEC1.YCSCR5
-#define YCSCR6_1 DVDEC1.YCSCR6
-#define YCSCR7_1 DVDEC1.YCSCR7
-#define YCSCR8_1 DVDEC1.YCSCR8
-#define YCSCR9_1 DVDEC1.YCSCR9
-#define YCSCR11_1 DVDEC1.YCSCR11
-#define YCSCR12_1 DVDEC1.YCSCR12
-#define DCPCR9_1 DVDEC1.DCPCR9
-#define YCTWA_F0_1 DVDEC1.YCTWA_F0
-#define YCTWA_F1_1 DVDEC1.YCTWA_F1
-#define YCTWA_F2_1 DVDEC1.YCTWA_F2
-#define YCTWA_F3_1 DVDEC1.YCTWA_F3
-#define YCTWA_F4_1 DVDEC1.YCTWA_F4
-#define YCTWA_F5_1 DVDEC1.YCTWA_F5
-#define YCTWA_F6_1 DVDEC1.YCTWA_F6
-#define YCTWA_F7_1 DVDEC1.YCTWA_F7
-#define YCTWA_F8_1 DVDEC1.YCTWA_F8
-#define YCTWB_F0_1 DVDEC1.YCTWB_F0
-#define YCTWB_F1_1 DVDEC1.YCTWB_F1
-#define YCTWB_F2_1 DVDEC1.YCTWB_F2
-#define YCTWB_F3_1 DVDEC1.YCTWB_F3
-#define YCTWB_F4_1 DVDEC1.YCTWB_F4
-#define YCTWB_F5_1 DVDEC1.YCTWB_F5
-#define YCTWB_F6_1 DVDEC1.YCTWB_F6
-#define YCTWB_F7_1 DVDEC1.YCTWB_F7
-#define YCTWB_F8_1 DVDEC1.YCTWB_F8
-#define YCTNA_F0_1 DVDEC1.YCTNA_F0
-#define YCTNA_F1_1 DVDEC1.YCTNA_F1
-#define YCTNA_F2_1 DVDEC1.YCTNA_F2
-#define YCTNA_F3_1 DVDEC1.YCTNA_F3
-#define YCTNA_F4_1 DVDEC1.YCTNA_F4
-#define YCTNA_F5_1 DVDEC1.YCTNA_F5
-#define YCTNA_F6_1 DVDEC1.YCTNA_F6
-#define YCTNA_F7_1 DVDEC1.YCTNA_F7
-#define YCTNA_F8_1 DVDEC1.YCTNA_F8
-#define YCTNB_F0_1 DVDEC1.YCTNB_F0
-#define YCTNB_F1_1 DVDEC1.YCTNB_F1
-#define YCTNB_F2_1 DVDEC1.YCTNB_F2
-#define YCTNB_F3_1 DVDEC1.YCTNB_F3
-#define YCTNB_F4_1 DVDEC1.YCTNB_F4
-#define YCTNB_F5_1 DVDEC1.YCTNB_F5
-#define YCTNB_F6_1 DVDEC1.YCTNB_F6
-#define YCTNB_F7_1 DVDEC1.YCTNB_F7
-#define YCTNB_F8_1 DVDEC1.YCTNB_F8
-#define YGAINCR_1 DVDEC1.YGAINCR
-#define CBGAINCR_1 DVDEC1.CBGAINCR
-#define CRGAINCR_1 DVDEC1.CRGAINCR
-#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE
-#define PGACR_1 DVDEC1.PGACR
-#define ADCCR2_1 DVDEC1.ADCCR2
-#define ADCCR1_0 DVDEC0.ADCCR1
-#define TGCR1_0 DVDEC0.TGCR1
-#define TGCR2_0 DVDEC0.TGCR2
-#define TGCR3_0 DVDEC0.TGCR3
-#define SYNSCR1_0 DVDEC0.SYNSCR1
-#define SYNSCR2_0 DVDEC0.SYNSCR2
-#define SYNSCR3_0 DVDEC0.SYNSCR3
-#define SYNSCR4_0 DVDEC0.SYNSCR4
-#define SYNSCR5_0 DVDEC0.SYNSCR5
-#define HAFCCR1_0 DVDEC0.HAFCCR1
-#define HAFCCR2_0 DVDEC0.HAFCCR2
-#define HAFCCR3_0 DVDEC0.HAFCCR3
-#define VCDWCR1_0 DVDEC0.VCDWCR1
-#define DCPCR1_0 DVDEC0.DCPCR1
-#define DCPCR2_0 DVDEC0.DCPCR2
-#define DCPCR3_0 DVDEC0.DCPCR3
-#define DCPCR4_0 DVDEC0.DCPCR4
-#define DCPCR5_0 DVDEC0.DCPCR5
-#define DCPCR6_0 DVDEC0.DCPCR6
-#define DCPCR7_0 DVDEC0.DCPCR7
-#define DCPCR8_0 DVDEC0.DCPCR8
-#define NSDCR_0 DVDEC0.NSDCR
-#define BTLCR_0 DVDEC0.BTLCR
-#define BTGPCR_0 DVDEC0.BTGPCR
-#define ACCCR1_0 DVDEC0.ACCCR1
-#define ACCCR2_0 DVDEC0.ACCCR2
-#define ACCCR3_0 DVDEC0.ACCCR3
-#define TINTCR_0 DVDEC0.TINTCR
-#define YCDCR_0 DVDEC0.YCDCR
-#define AGCCR1_0 DVDEC0.AGCCR1
-#define AGCCR2_0 DVDEC0.AGCCR2
-#define PKLIMITCR_0 DVDEC0.PKLIMITCR
-#define RGORCR1_0 DVDEC0.RGORCR1
-#define RGORCR2_0 DVDEC0.RGORCR2
-#define RGORCR3_0 DVDEC0.RGORCR3
-#define RGORCR4_0 DVDEC0.RGORCR4
-#define RGORCR5_0 DVDEC0.RGORCR5
-#define RGORCR6_0 DVDEC0.RGORCR6
-#define RGORCR7_0 DVDEC0.RGORCR7
-#define AFCPFCR_0 DVDEC0.AFCPFCR
-#define RUPDCR_0 DVDEC0.RUPDCR
-#define VSYNCSR_0 DVDEC0.VSYNCSR
-#define HSYNCSR_0 DVDEC0.HSYNCSR
-#define DCPSR1_0 DVDEC0.DCPSR1
-#define DCPSR2_0 DVDEC0.DCPSR2
-#define NSDSR_0 DVDEC0.NSDSR
-#define CROMASR1_0 DVDEC0.CROMASR1
-#define CROMASR2_0 DVDEC0.CROMASR2
-#define SYNCSSR_0 DVDEC0.SYNCSSR
-#define AGCCSR1_0 DVDEC0.AGCCSR1
-#define AGCCSR2_0 DVDEC0.AGCCSR2
-#define YCSCR3_0 DVDEC0.YCSCR3
-#define YCSCR4_0 DVDEC0.YCSCR4
-#define YCSCR5_0 DVDEC0.YCSCR5
-#define YCSCR6_0 DVDEC0.YCSCR6
-#define YCSCR7_0 DVDEC0.YCSCR7
-#define YCSCR8_0 DVDEC0.YCSCR8
-#define YCSCR9_0 DVDEC0.YCSCR9
-#define YCSCR11_0 DVDEC0.YCSCR11
-#define YCSCR12_0 DVDEC0.YCSCR12
-#define DCPCR9_0 DVDEC0.DCPCR9
-#define YCTWA_F0_0 DVDEC0.YCTWA_F0
-#define YCTWA_F1_0 DVDEC0.YCTWA_F1
-#define YCTWA_F2_0 DVDEC0.YCTWA_F2
-#define YCTWA_F3_0 DVDEC0.YCTWA_F3
-#define YCTWA_F4_0 DVDEC0.YCTWA_F4
-#define YCTWA_F5_0 DVDEC0.YCTWA_F5
-#define YCTWA_F6_0 DVDEC0.YCTWA_F6
-#define YCTWA_F7_0 DVDEC0.YCTWA_F7
-#define YCTWA_F8_0 DVDEC0.YCTWA_F8
-#define YCTWB_F0_0 DVDEC0.YCTWB_F0
-#define YCTWB_F1_0 DVDEC0.YCTWB_F1
-#define YCTWB_F2_0 DVDEC0.YCTWB_F2
-#define YCTWB_F3_0 DVDEC0.YCTWB_F3
-#define YCTWB_F4_0 DVDEC0.YCTWB_F4
-#define YCTWB_F5_0 DVDEC0.YCTWB_F5
-#define YCTWB_F6_0 DVDEC0.YCTWB_F6
-#define YCTWB_F7_0 DVDEC0.YCTWB_F7
-#define YCTWB_F8_0 DVDEC0.YCTWB_F8
-#define YCTNA_F0_0 DVDEC0.YCTNA_F0
-#define YCTNA_F1_0 DVDEC0.YCTNA_F1
-#define YCTNA_F2_0 DVDEC0.YCTNA_F2
-#define YCTNA_F3_0 DVDEC0.YCTNA_F3
-#define YCTNA_F4_0 DVDEC0.YCTNA_F4
-#define YCTNA_F5_0 DVDEC0.YCTNA_F5
-#define YCTNA_F6_0 DVDEC0.YCTNA_F6
-#define YCTNA_F7_0 DVDEC0.YCTNA_F7
-#define YCTNA_F8_0 DVDEC0.YCTNA_F8
-#define YCTNB_F0_0 DVDEC0.YCTNB_F0
-#define YCTNB_F1_0 DVDEC0.YCTNB_F1
-#define YCTNB_F2_0 DVDEC0.YCTNB_F2
-#define YCTNB_F3_0 DVDEC0.YCTNB_F3
-#define YCTNB_F4_0 DVDEC0.YCTNB_F4
-#define YCTNB_F5_0 DVDEC0.YCTNB_F5
-#define YCTNB_F6_0 DVDEC0.YCTNB_F6
-#define YCTNB_F7_0 DVDEC0.YCTNB_F7
-#define YCTNB_F8_0 DVDEC0.YCTNB_F8
-#define YGAINCR_0 DVDEC0.YGAINCR
-#define CBGAINCR_0 DVDEC0.CBGAINCR
-#define CRGAINCR_0 DVDEC0.CRGAINCR
-#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE
-#define PGACR_0 DVDEC0.PGACR
-#define ADCCR2_0 DVDEC0.ADCCR2
+/* Channel array defines of DVDEC (2)*/
+#ifdef  DECLARE_DVDEC_CHANNELS
+volatile struct st_dvdec*  DVDEC[ DVDEC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DVDEC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DVDEC_CHANNELS */
+/* End of channel array defines of DVDEC (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,21 +18,192 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : ether_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef ETHER_IODEFINE_H
 #define ETHER_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_ether
-{                                                          /* ETHER            */
+#define ETHER   (*(struct st_ether   *)0xE8203000uL) /* ETHER */
+
+
+/* Start of channel array defines of ETHER */
+
+/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
+/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
+#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT  (32)
+#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
+    &ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
+    &ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
+    &ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
+#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
+#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
+#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
+#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
+#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
+#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
+#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
+#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
+#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
+#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
+#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
+#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
+#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
+#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
+#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
+#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
+#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
+#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
+#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
+#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
+#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
+#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
+#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
+#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
+#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
+#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
+#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
+#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
+#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
+#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
+#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
+
+/* End of channel array defines of ETHER */
+
+
+#define ETHEREDSR0 (ETHER.EDSR0)
+#define ETHERTDLAR0 (ETHER.TDLAR0)
+#define ETHERTDFAR0 (ETHER.TDFAR0)
+#define ETHERTDFXR0 (ETHER.TDFXR0)
+#define ETHERTDFFR0 (ETHER.TDFFR0)
+#define ETHERRDLAR0 (ETHER.RDLAR0)
+#define ETHERRDFAR0 (ETHER.RDFAR0)
+#define ETHERRDFXR0 (ETHER.RDFXR0)
+#define ETHERRDFFR0 (ETHER.RDFFR0)
+#define ETHEREDMR0 (ETHER.EDMR0)
+#define ETHEREDTRR0 (ETHER.EDTRR0)
+#define ETHEREDRRR0 (ETHER.EDRRR0)
+#define ETHEREESR0 (ETHER.EESR0)
+#define ETHEREESIPR0 (ETHER.EESIPR0)
+#define ETHERTRSCER0 (ETHER.TRSCER0)
+#define ETHERRMFCR0 (ETHER.RMFCR0)
+#define ETHERTFTR0 (ETHER.TFTR0)
+#define ETHERFDR0 (ETHER.FDR0)
+#define ETHERRMCR0 (ETHER.RMCR0)
+#define ETHERRPADIR0 (ETHER.RPADIR0)
+#define ETHERFCFTR0 (ETHER.FCFTR0)
+#define ETHERCSMR (ETHER.CSMR)
+#define ETHERCSSBM (ETHER.CSSBM)
+#define ETHERCSSMR (ETHER.CSSMR)
+#define ETHERECMR0 (ETHER.ECMR0)
+#define ETHERRFLR0 (ETHER.RFLR0)
+#define ETHERECSR0 (ETHER.ECSR0)
+#define ETHERECSIPR0 (ETHER.ECSIPR0)
+#define ETHERPIR0 (ETHER.PIR0)
+#define ETHERAPR0 (ETHER.APR0)
+#define ETHERMPR0 (ETHER.MPR0)
+#define ETHERPFTCR0 (ETHER.PFTCR0)
+#define ETHERPFRCR0 (ETHER.PFRCR0)
+#define ETHERTPAUSER0 (ETHER.TPAUSER0)
+#define ETHERMAHR0 (ETHER.MAHR0)
+#define ETHERMALR0 (ETHER.MALR0)
+#define ETHERCEFCR0 (ETHER.CEFCR0)
+#define ETHERFRECR0 (ETHER.FRECR0)
+#define ETHERTSFRCR0 (ETHER.TSFRCR0)
+#define ETHERTLFRCR0 (ETHER.TLFRCR0)
+#define ETHERRFCR0 (ETHER.RFCR0)
+#define ETHERMAFCR0 (ETHER.MAFCR0)
+#define ETHERARSTR (ETHER.ARSTR)
+#define ETHERTSU_CTRST (ETHER.TSU_CTRST)
+#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0)
+#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY)
+#define ETHERTSU_TEN (ETHER.TSU_TEN)
+#define ETHERTXNLCR0 (ETHER.TXNLCR0)
+#define ETHERTXALCR0 (ETHER.TXALCR0)
+#define ETHERRXNLCR0 (ETHER.RXNLCR0)
+#define ETHERRXALCR0 (ETHER.RXALCR0)
+#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0)
+#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0)
+#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1)
+#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1)
+#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2)
+#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2)
+#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3)
+#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3)
+#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4)
+#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4)
+#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5)
+#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5)
+#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6)
+#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6)
+#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7)
+#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7)
+#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8)
+#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8)
+#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9)
+#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9)
+#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10)
+#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10)
+#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11)
+#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11)
+#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12)
+#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12)
+#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13)
+#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13)
+#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14)
+#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14)
+#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15)
+#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15)
+#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16)
+#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16)
+#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17)
+#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17)
+#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18)
+#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18)
+#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19)
+#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19)
+#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20)
+#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20)
+#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21)
+#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21)
+#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22)
+#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22)
+#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23)
+#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23)
+#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24)
+#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24)
+#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25)
+#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25)
+#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26)
+#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26)
+#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27)
+#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27)
+#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28)
+#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28)
+#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29)
+#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29)
+#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30)
+#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30)
+#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31)
+#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31)
+
+
+typedef struct st_ether
+{
+                                                           /* ETHER            */
     volatile uint32_t  EDSR0;                                  /*  EDSR0           */
     volatile uint8_t   dummy207[12];                           /*                  */
     volatile uint32_t  TDLAR0;                                 /*  TDLAR0          */
@@ -118,310 +289,221 @@
     volatile uint32_t  RXNLCR0;                                /*  RXNLCR0         */
     volatile uint32_t  RXALCR0;                                /*  RXALCR0         */
     volatile uint8_t   dummy240[112];                          /*                  */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
     volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH1;                              /*  TSU_ADRH1       */
     volatile uint32_t  TSU_ADRL1;                              /*  TSU_ADRL1       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH2;                              /*  TSU_ADRH2       */
     volatile uint32_t  TSU_ADRL2;                              /*  TSU_ADRL2       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH3;                              /*  TSU_ADRH3       */
     volatile uint32_t  TSU_ADRL3;                              /*  TSU_ADRL3       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH4;                              /*  TSU_ADRH4       */
     volatile uint32_t  TSU_ADRL4;                              /*  TSU_ADRL4       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH5;                              /*  TSU_ADRH5       */
     volatile uint32_t  TSU_ADRL5;                              /*  TSU_ADRL5       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH6;                              /*  TSU_ADRH6       */
     volatile uint32_t  TSU_ADRL6;                              /*  TSU_ADRL6       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH7;                              /*  TSU_ADRH7       */
     volatile uint32_t  TSU_ADRL7;                              /*  TSU_ADRL7       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH8;                              /*  TSU_ADRH8       */
     volatile uint32_t  TSU_ADRL8;                              /*  TSU_ADRL8       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH9;                              /*  TSU_ADRH9       */
     volatile uint32_t  TSU_ADRL9;                              /*  TSU_ADRL9       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH10;                             /*  TSU_ADRH10      */
     volatile uint32_t  TSU_ADRL10;                             /*  TSU_ADRL10      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH11;                             /*  TSU_ADRH11      */
     volatile uint32_t  TSU_ADRL11;                             /*  TSU_ADRL11      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH12;                             /*  TSU_ADRH12      */
     volatile uint32_t  TSU_ADRL12;                             /*  TSU_ADRL12      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH13;                             /*  TSU_ADRH13      */
     volatile uint32_t  TSU_ADRL13;                             /*  TSU_ADRL13      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH14;                             /*  TSU_ADRH14      */
     volatile uint32_t  TSU_ADRL14;                             /*  TSU_ADRL14      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH15;                             /*  TSU_ADRH15      */
     volatile uint32_t  TSU_ADRL15;                             /*  TSU_ADRL15      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH16;                             /*  TSU_ADRH16      */
     volatile uint32_t  TSU_ADRL16;                             /*  TSU_ADRL16      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH17;                             /*  TSU_ADRH17      */
     volatile uint32_t  TSU_ADRL17;                             /*  TSU_ADRL17      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH18;                             /*  TSU_ADRH18      */
     volatile uint32_t  TSU_ADRL18;                             /*  TSU_ADRL18      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH19;                             /*  TSU_ADRH19      */
     volatile uint32_t  TSU_ADRL19;                             /*  TSU_ADRL19      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH20;                             /*  TSU_ADRH20      */
     volatile uint32_t  TSU_ADRL20;                             /*  TSU_ADRL20      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH21;                             /*  TSU_ADRH21      */
     volatile uint32_t  TSU_ADRL21;                             /*  TSU_ADRL21      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH22;                             /*  TSU_ADRH22      */
     volatile uint32_t  TSU_ADRL22;                             /*  TSU_ADRL22      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH23;                             /*  TSU_ADRH23      */
     volatile uint32_t  TSU_ADRL23;                             /*  TSU_ADRL23      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH24;                             /*  TSU_ADRH24      */
     volatile uint32_t  TSU_ADRL24;                             /*  TSU_ADRL24      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH25;                             /*  TSU_ADRH25      */
     volatile uint32_t  TSU_ADRL25;                             /*  TSU_ADRL25      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH26;                             /*  TSU_ADRH26      */
     volatile uint32_t  TSU_ADRL26;                             /*  TSU_ADRL26      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH27;                             /*  TSU_ADRH27      */
     volatile uint32_t  TSU_ADRL27;                             /*  TSU_ADRL27      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH28;                             /*  TSU_ADRH28      */
     volatile uint32_t  TSU_ADRL28;                             /*  TSU_ADRL28      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH29;                             /*  TSU_ADRH29      */
     volatile uint32_t  TSU_ADRL29;                             /*  TSU_ADRL29      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH30;                             /*  TSU_ADRH30      */
     volatile uint32_t  TSU_ADRL30;                             /*  TSU_ADRL30      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH31;                             /*  TSU_ADRH31      */
     volatile uint32_t  TSU_ADRL31;                             /*  TSU_ADRL31      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
-};
-
-
-struct st_ether_from_tsu_adrh0
-{
-    volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
-    volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
-};
-
-
-#define ETHER   (*(struct st_ether   *)0xE8203000uL) /* ETHER */
+} r_io_ether_t;
 
 
-/* Start of channnel array defines of ETHER */
-
-/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
-/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
-#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT  32
-#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
-    &ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
-    &ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
-    &ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
-#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
-#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
-#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
-#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
-#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
-#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
-#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
-#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
-#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
-#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
-#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
-#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
-#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
-#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
-#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
-#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
-#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
-#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
-#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
-#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
-#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
-#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
-#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
-#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
-#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
-#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
-#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
-#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
-#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
-#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
-#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
-
-/* End of channnel array defines of ETHER */
+typedef struct st_ether_from_tsu_adrh0
+{
+ 
+    volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
+    volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
+} r_io_ether_from_tsu_adrh0_t;
 
 
-#define ETHEREDSR0 ETHER.EDSR0
-#define ETHERTDLAR0 ETHER.TDLAR0
-#define ETHERTDFAR0 ETHER.TDFAR0
-#define ETHERTDFXR0 ETHER.TDFXR0
-#define ETHERTDFFR0 ETHER.TDFFR0
-#define ETHERRDLAR0 ETHER.RDLAR0
-#define ETHERRDFAR0 ETHER.RDFAR0
-#define ETHERRDFXR0 ETHER.RDFXR0
-#define ETHERRDFFR0 ETHER.RDFFR0
-#define ETHEREDMR0 ETHER.EDMR0
-#define ETHEREDTRR0 ETHER.EDTRR0
-#define ETHEREDRRR0 ETHER.EDRRR0
-#define ETHEREESR0 ETHER.EESR0
-#define ETHEREESIPR0 ETHER.EESIPR0
-#define ETHERTRSCER0 ETHER.TRSCER0
-#define ETHERRMFCR0 ETHER.RMFCR0
-#define ETHERTFTR0 ETHER.TFTR0
-#define ETHERFDR0 ETHER.FDR0
-#define ETHERRMCR0 ETHER.RMCR0
-#define ETHERRPADIR0 ETHER.RPADIR0
-#define ETHERFCFTR0 ETHER.FCFTR0
-#define ETHERCSMR ETHER.CSMR
-#define ETHERCSSBM ETHER.CSSBM
-#define ETHERCSSMR ETHER.CSSMR
-#define ETHERECMR0 ETHER.ECMR0
-#define ETHERRFLR0 ETHER.RFLR0
-#define ETHERECSR0 ETHER.ECSR0
-#define ETHERECSIPR0 ETHER.ECSIPR0
-#define ETHERPIR0 ETHER.PIR0
-#define ETHERAPR0 ETHER.APR0
-#define ETHERMPR0 ETHER.MPR0
-#define ETHERPFTCR0 ETHER.PFTCR0
-#define ETHERPFRCR0 ETHER.PFRCR0
-#define ETHERTPAUSER0 ETHER.TPAUSER0
-#define ETHERMAHR0 ETHER.MAHR0
-#define ETHERMALR0 ETHER.MALR0
-#define ETHERCEFCR0 ETHER.CEFCR0
-#define ETHERFRECR0 ETHER.FRECR0
-#define ETHERTSFRCR0 ETHER.TSFRCR0
-#define ETHERTLFRCR0 ETHER.TLFRCR0
-#define ETHERRFCR0 ETHER.RFCR0
-#define ETHERMAFCR0 ETHER.MAFCR0
-#define ETHERARSTR ETHER.ARSTR
-#define ETHERTSU_CTRST ETHER.TSU_CTRST
-#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0
-#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY
-#define ETHERTSU_TEN ETHER.TSU_TEN
-#define ETHERTXNLCR0 ETHER.TXNLCR0
-#define ETHERTXALCR0 ETHER.TXALCR0
-#define ETHERRXNLCR0 ETHER.RXNLCR0
-#define ETHERRXALCR0 ETHER.RXALCR0
-#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0
-#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0
-#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1
-#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1
-#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2
-#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2
-#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3
-#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3
-#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4
-#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4
-#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5
-#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5
-#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6
-#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6
-#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7
-#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7
-#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8
-#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8
-#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9
-#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9
-#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10
-#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10
-#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11
-#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11
-#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12
-#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12
-#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13
-#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13
-#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14
-#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14
-#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15
-#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15
-#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16
-#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16
-#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17
-#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17
-#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18
-#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18
-#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19
-#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19
-#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20
-#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20
-#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21
-#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21
-#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22
-#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22
-#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23
-#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23
-#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24
-#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24
-#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25
-#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25
-#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26
-#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26
-#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27
-#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27
-#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28
-#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28
-#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29
-#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29
-#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30
-#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30
-#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31
-#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31
+/* Channel array defines of ETHER (2)*/
+#ifdef  DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS
+volatile struct st_ether_from_tsu_adrh0*  ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */
+/* End of channel array defines of ETHER (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,41 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : flctl_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef FLCTL_IODEFINE_H
 #define FLCTL_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_flctl
-{                                                          /* FLCTL            */
+#define FLCTL   (*(struct st_flctl   *)0xFCFF4000uL) /* FLCTL */
+
+
+#define FLCTLFLCMNCR (FLCTL.FLCMNCR)
+#define FLCTLFLCMDCR (FLCTL.FLCMDCR)
+#define FLCTLFLCMCDR (FLCTL.FLCMCDR)
+#define FLCTLFLADR (FLCTL.FLADR)
+#define FLCTLFLDATAR (FLCTL.FLDATAR)
+#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR)
+#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR)
+#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR)
+#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT)
+#define FLCTLFLTRCR (FLCTL.FLTRCR)
+#define FLCTLFLADR2 (FLCTL.FLADR2)
+#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO)
+
+
+typedef struct st_flctl
+{
+                                                           /* FLCTL            */
     volatile uint32_t  FLCMNCR;                                /*  FLCMNCR         */
     volatile uint32_t  FLCMDCR;                                /*  FLCMDCR         */
     volatile uint32_t  FLCMCDR;                                /*  FLCMCDR         */
@@ -47,26 +68,11 @@
     volatile uint32_t  FLADR2;                                 /*  FLADR2          */
     volatile uint8_t   dummy557[16];                           /*                  */
     volatile uint32_t  FLDTFIFO;                               /*  FLDTFIFO        */
-    volatile uint8_t   dummy558[12];                           /*                  */
-    volatile uint32_t  FLECFIFO;                               /*  FLECFIFO        */
-};
-
-
-#define FLCTL   (*(struct st_flctl   *)0xFCFF4000uL) /* FLCTL */
+} r_io_flctl_t;
 
 
-#define FLCTLFLCMNCR FLCTL.FLCMNCR
-#define FLCTLFLCMDCR FLCTL.FLCMDCR
-#define FLCTLFLCMCDR FLCTL.FLCMCDR
-#define FLCTLFLADR FLCTL.FLADR
-#define FLCTLFLDATAR FLCTL.FLDATAR
-#define FLCTLFLDTCNTR FLCTL.FLDTCNTR
-#define FLCTLFLINTDMACR FLCTL.FLINTDMACR
-#define FLCTLFLBSYTMR FLCTL.FLBSYTMR
-#define FLCTLFLBSYCNT FLCTL.FLBSYCNT
-#define FLCTLFLTRCR FLCTL.FLTRCR
-#define FLCTLFLADR2 FLCTL.FLADR2
-#define FLCTLFLDTFIFO FLCTL.FLDTFIFO
-#define FLCTLFLECFIFO FLCTL.FLECFIFO
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,662 +18,29 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : gpio_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef GPIO_IODEFINE_H
 #define GPIO_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_gpio
-{                                                          /* GPIO             */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P1;                                     /*  P1              */
-    volatile uint8_t   dummy348[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P2;                                     /*  P2              */
-    volatile uint8_t   dummy349[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P3;                                     /*  P3              */
-    volatile uint8_t   dummy350[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P4;                                     /*  P4              */
-    volatile uint8_t   dummy351[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P5;                                     /*  P5              */
-    volatile uint8_t   dummy352[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P6;                                     /*  P6              */
-    volatile uint8_t   dummy353[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P7;                                     /*  P7              */
-    volatile uint8_t   dummy354[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P8;                                     /*  P8              */
-    volatile uint8_t   dummy355[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P9;                                     /*  P9              */
-    volatile uint8_t   dummy356[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P10;                                    /*  P10             */
-    volatile uint8_t   dummy357[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P11;                                    /*  P11             */
-    volatile uint8_t   dummy3580[2];                           /*                  */
-/* end of struct st_gpio_from_p1 */
-    volatile uint8_t   dummy3581[212];                         /*                  */
-#define GPIO_PSRn_COUNT 11
-    volatile uint32_t  PSR1;                                   /*  PSR1            */
-    volatile uint32_t  PSR2;                                   /*  PSR2            */
-    volatile uint32_t  PSR3;                                   /*  PSR3            */
-    volatile uint32_t  PSR4;                                   /*  PSR4            */
-    volatile uint32_t  PSR5;                                   /*  PSR5            */
-    volatile uint32_t  PSR6;                                   /*  PSR6            */
-    volatile uint32_t  PSR7;                                   /*  PSR7            */
-    volatile uint32_t  PSR8;                                   /*  PSR8            */
-    volatile uint32_t  PSR9;                                   /*  PSR9            */
-    volatile uint32_t  PSR10;                                  /*  PSR10           */
-    volatile uint32_t  PSR11;                                  /*  PSR11           */
-    volatile uint8_t   dummy359[208];                          /*                  */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR0;                                   /*  PPR0            */
-    volatile uint8_t   dummy360[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR1;                                   /*  PPR1            */
-    volatile uint8_t   dummy361[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR2;                                   /*  PPR2            */
-    volatile uint8_t   dummy362[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR3;                                   /*  PPR3            */
-    volatile uint8_t   dummy363[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR4;                                   /*  PPR4            */
-    volatile uint8_t   dummy364[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR5;                                   /*  PPR5            */
-    volatile uint8_t   dummy365[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR6;                                   /*  PPR6            */
-    volatile uint8_t   dummy366[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR7;                                   /*  PPR7            */
-    volatile uint8_t   dummy367[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR8;                                   /*  PPR8            */
-    volatile uint8_t   dummy368[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR9;                                   /*  PPR9            */
-    volatile uint8_t   dummy369[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR10;                                  /*  PPR10           */
-    volatile uint8_t   dummy370[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR11;                                  /*  PPR11           */
-    volatile uint8_t   dummy3710[2];                           /*                  */
-/* end of struct st_gpio_from_ppr0 */
-    volatile uint8_t   dummy3711[212];                         /*                  */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM1;                                    /*  PM1             */
-    volatile uint8_t   dummy372[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM2;                                    /*  PM2             */
-    volatile uint8_t   dummy373[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM3;                                    /*  PM3             */
-    volatile uint8_t   dummy374[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM4;                                    /*  PM4             */
-    volatile uint8_t   dummy375[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM5;                                    /*  PM5             */
-    volatile uint8_t   dummy376[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM6;                                    /*  PM6             */
-    volatile uint8_t   dummy377[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM7;                                    /*  PM7             */
-    volatile uint8_t   dummy378[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM8;                                    /*  PM8             */
-    volatile uint8_t   dummy379[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM9;                                    /*  PM9             */
-    volatile uint8_t   dummy380[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM10;                                   /*  PM10            */
-    volatile uint8_t   dummy381[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM11;                                   /*  PM11            */
-    volatile uint8_t   dummy3820[2];                           /*                  */
-/* end of struct st_gpio_from_pm1 */
-    volatile uint8_t   dummy3821[208];                         /*                  */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC0;                                   /*  PMC0            */
-    volatile uint8_t   dummy383[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC1;                                   /*  PMC1            */
-    volatile uint8_t   dummy384[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC2;                                   /*  PMC2            */
-    volatile uint8_t   dummy385[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC3;                                   /*  PMC3            */
-    volatile uint8_t   dummy386[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC4;                                   /*  PMC4            */
-    volatile uint8_t   dummy387[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC5;                                   /*  PMC5            */
-    volatile uint8_t   dummy388[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC6;                                   /*  PMC6            */
-    volatile uint8_t   dummy389[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC7;                                   /*  PMC7            */
-    volatile uint8_t   dummy390[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC8;                                   /*  PMC8            */
-    volatile uint8_t   dummy391[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC9;                                   /*  PMC9            */
-    volatile uint8_t   dummy392[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC10;                                  /*  PMC10           */
-    volatile uint8_t   dummy393[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC11;                                  /*  PMC11           */
-    volatile uint8_t   dummy3940[2];                           /*                  */
-/* end of struct st_gpio_from_pmc0 */
-    volatile uint8_t   dummy3941[212];                         /*                  */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC1;                                   /*  PFC1            */
-    volatile uint8_t   dummy395[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC2;                                   /*  PFC2            */
-    volatile uint8_t   dummy396[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC3;                                   /*  PFC3            */
-    volatile uint8_t   dummy397[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC4;                                   /*  PFC4            */
-    volatile uint8_t   dummy398[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC5;                                   /*  PFC5            */
-    volatile uint8_t   dummy399[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC6;                                   /*  PFC6            */
-    volatile uint8_t   dummy400[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC7;                                   /*  PFC7            */
-    volatile uint8_t   dummy401[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC8;                                   /*  PFC8            */
-    volatile uint8_t   dummy402[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC9;                                   /*  PFC9            */
-    volatile uint8_t   dummy403[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC10;                                  /*  PFC10           */
-    volatile uint8_t   dummy404[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC11;                                  /*  PFC11           */
-    volatile uint8_t   dummy4050[2];                           /*                  */
-/* end of struct st_gpio_from_pfc1 */
-    volatile uint8_t   dummy4051[212];                         /*                  */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE1;                                  /*  PFCE1           */
-    volatile uint8_t   dummy406[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE2;                                  /*  PFCE2           */
-    volatile uint8_t   dummy407[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE3;                                  /*  PFCE3           */
-    volatile uint8_t   dummy408[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE4;                                  /*  PFCE4           */
-    volatile uint8_t   dummy409[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE5;                                  /*  PFCE5           */
-    volatile uint8_t   dummy410[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE6;                                  /*  PFCE6           */
-    volatile uint8_t   dummy411[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE7;                                  /*  PFCE7           */
-    volatile uint8_t   dummy412[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE8;                                  /*  PFCE8           */
-    volatile uint8_t   dummy413[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE9;                                  /*  PFCE9           */
-    volatile uint8_t   dummy414[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE10;                                 /*  PFCE10          */
-    volatile uint8_t   dummy415[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE11;                                 /*  PFCE11          */
-    volatile uint8_t   dummy4160[2];                           /*                  */
-/* end of struct st_gpio_from_pfce1 */
-    volatile uint8_t   dummy4161[212];                         /*                  */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT1;                                  /*  PNOT1           */
-    volatile uint8_t   dummy417[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT2;                                  /*  PNOT2           */
-    volatile uint8_t   dummy418[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT3;                                  /*  PNOT3           */
-    volatile uint8_t   dummy419[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT4;                                  /*  PNOT4           */
-    volatile uint8_t   dummy420[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT5;                                  /*  PNOT5           */
-    volatile uint8_t   dummy421[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT6;                                  /*  PNOT6           */
-    volatile uint8_t   dummy422[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT7;                                  /*  PNOT7           */
-    volatile uint8_t   dummy423[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT8;                                  /*  PNOT8           */
-    volatile uint8_t   dummy424[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT9;                                  /*  PNOT9           */
-    volatile uint8_t   dummy425[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT10;                                 /*  PNOT10          */
-    volatile uint8_t   dummy426[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT11;                                 /*  PNOT11          */
-    volatile uint8_t   dummy4270[2];                           /*                  */
-/* end of struct st_gpio_from_pnot1 */
-    volatile uint8_t   dummy4271[212];                         /*                  */
-#define GPIO_PMSRn_COUNT 11
-    volatile uint32_t  PMSR1;                                  /*  PMSR1           */
-    volatile uint32_t  PMSR2;                                  /*  PMSR2           */
-    volatile uint32_t  PMSR3;                                  /*  PMSR3           */
-    volatile uint32_t  PMSR4;                                  /*  PMSR4           */
-    volatile uint32_t  PMSR5;                                  /*  PMSR5           */
-    volatile uint32_t  PMSR6;                                  /*  PMSR6           */
-    volatile uint32_t  PMSR7;                                  /*  PMSR7           */
-    volatile uint32_t  PMSR8;                                  /*  PMSR8           */
-    volatile uint32_t  PMSR9;                                  /*  PMSR9           */
-    volatile uint32_t  PMSR10;                                 /*  PMSR10          */
-    volatile uint32_t  PMSR11;                                 /*  PMSR11          */
-    volatile uint8_t   dummy428[208];                          /*                  */
-#define GPIO_PMCSRn_COUNT 12
-    volatile uint32_t  PMCSR0;                                 /*  PMCSR0          */
-    volatile uint32_t  PMCSR1;                                 /*  PMCSR1          */
-    volatile uint32_t  PMCSR2;                                 /*  PMCSR2          */
-    volatile uint32_t  PMCSR3;                                 /*  PMCSR3          */
-    volatile uint32_t  PMCSR4;                                 /*  PMCSR4          */
-    volatile uint32_t  PMCSR5;                                 /*  PMCSR5          */
-    volatile uint32_t  PMCSR6;                                 /*  PMCSR6          */
-    volatile uint32_t  PMCSR7;                                 /*  PMCSR7          */
-    volatile uint32_t  PMCSR8;                                 /*  PMCSR8          */
-    volatile uint32_t  PMCSR9;                                 /*  PMCSR9          */
-    volatile uint32_t  PMCSR10;                                /*  PMCSR10         */
-    volatile uint32_t  PMCSR11;                                /*  PMCSR11         */
-    volatile uint8_t   dummy429[212];                          /*                  */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
-    volatile uint8_t   dummy430[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE2;                                 /*  PFCAE2          */
-    volatile uint8_t   dummy431[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE3;                                 /*  PFCAE3          */
-    volatile uint8_t   dummy432[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE4;                                 /*  PFCAE4          */
-    volatile uint8_t   dummy433[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE5;                                 /*  PFCAE5          */
-    volatile uint8_t   dummy434[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE6;                                 /*  PFCAE6          */
-    volatile uint8_t   dummy435[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE7;                                 /*  PFCAE7          */
-    volatile uint8_t   dummy436[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE8;                                 /*  PFCAE8          */
-    volatile uint8_t   dummy437[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE9;                                 /*  PFCAE9          */
-    volatile uint8_t   dummy438[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE10;                                /*  PFCAE10         */
-    volatile uint8_t   dummy439[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE11;                                /*  PFCAE11         */
-    volatile uint8_t   dummy4400[2];                           /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-    volatile uint8_t   dummy4401[464];                         /*                  */
-    volatile uint32_t  SNCR;                                   /*  SNCR            */
-    volatile uint8_t   dummy441[13308];                        /*                  */
-    volatile uint16_t PIBC0;                                  /*  PIBC0           */
-    volatile uint8_t   dummy442[2];                            /*                  */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC1;                                  /*  PIBC1           */
-    volatile uint8_t   dummy443[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC2;                                  /*  PIBC2           */
-    volatile uint8_t   dummy444[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC3;                                  /*  PIBC3           */
-    volatile uint8_t   dummy445[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC4;                                  /*  PIBC4           */
-    volatile uint8_t   dummy446[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC5;                                  /*  PIBC5           */
-    volatile uint8_t   dummy447[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC6;                                  /*  PIBC6           */
-    volatile uint8_t   dummy448[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC7;                                  /*  PIBC7           */
-    volatile uint8_t   dummy449[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC8;                                  /*  PIBC8           */
-    volatile uint8_t   dummy450[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC9;                                  /*  PIBC9           */
-    volatile uint8_t   dummy451[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC10;                                 /*  PIBC10          */
-    volatile uint8_t   dummy452[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC11;                                 /*  PIBC11          */
-    volatile uint8_t   dummy4530[2];                           /*                  */
-/* end of struct st_gpio_from_pibc1 */
-    volatile uint8_t   dummy4531[212];                         /*                  */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC1;                                  /*  PBDC1           */
-    volatile uint8_t   dummy454[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC2;                                  /*  PBDC2           */
-    volatile uint8_t   dummy455[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC3;                                  /*  PBDC3           */
-    volatile uint8_t   dummy456[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC4;                                  /*  PBDC4           */
-    volatile uint8_t   dummy457[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC5;                                  /*  PBDC5           */
-    volatile uint8_t   dummy458[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC6;                                  /*  PBDC6           */
-    volatile uint8_t   dummy459[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC7;                                  /*  PBDC7           */
-    volatile uint8_t   dummy460[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC8;                                  /*  PBDC8           */
-    volatile uint8_t   dummy461[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC9;                                  /*  PBDC9           */
-    volatile uint8_t   dummy462[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC10;                                 /*  PBDC10          */
-    volatile uint8_t   dummy463[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC11;                                 /*  PBDC11          */
-    volatile uint8_t   dummy4640[2];                           /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-    volatile uint8_t   dummy4641[212];                         /*                  */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC1;                                  /*  PIPC1           */
-    volatile uint8_t   dummy465[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC2;                                  /*  PIPC2           */
-    volatile uint8_t   dummy466[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC3;                                  /*  PIPC3           */
-    volatile uint8_t   dummy467[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC4;                                  /*  PIPC4           */
-    volatile uint8_t   dummy468[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC5;                                  /*  PIPC5           */
-    volatile uint8_t   dummy469[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC6;                                  /*  PIPC6           */
-    volatile uint8_t   dummy470[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC7;                                  /*  PIPC7           */
-    volatile uint8_t   dummy471[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC8;                                  /*  PIPC8           */
-    volatile uint8_t   dummy472[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC9;                                  /*  PIPC9           */
-    volatile uint8_t   dummy473[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC10;                                 /*  PIPC10          */
-    volatile uint8_t   dummy474[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC11;                                 /*  PIPC11          */
-    volatile uint8_t   dummy4750[2];                           /*                  */
-/* end of struct st_gpio_from_pipc1 */
-    volatile uint8_t   dummy4751[2288];                        /*                  */
-    volatile uint16_t JPPR0;                                  /*  JPPR0           */
-    volatile uint8_t   dummy476[30];                           /*                  */
-    volatile uint16_t JPMC0;                                  /*  JPMC0           */
-    volatile uint8_t   dummy477[78];                           /*                  */
-    volatile uint32_t  JPMCSR0;                                /*  JPMCSR0         */
-    volatile uint8_t   dummy478[876];                          /*                  */
-    volatile uint16_t JPIBC0;                                 /*  JPIBC0          */
-};
-
-
-struct st_gpio_from_p1
-{
-    volatile uint16_t P1;                                     /*  P1              */
-    volatile uint8_t   dummy1[3];                              /*                  */
-};
-
-
-struct st_gpio_from_ppr0
-{
-    volatile uint16_t PPR0;                                   /*  PPR0            */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pm1
-{
-    volatile uint16_t PM1;                                    /*  PM1             */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pmc0
-{
-    volatile uint16_t PMC0;                                   /*  PMC0            */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pfc1
-{
-    volatile uint16_t PFC1;                                   /*  PFC1            */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pfce1
-{
-    volatile uint16_t PFCE1;                                  /*  PFCE1           */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pnot1
-{
-    volatile uint16_t PNOT1;                                  /*  PNOT1           */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pfcae1
-{
-    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pibc1
-{
-    volatile uint16_t PIBC1;                                  /*  PIBC1           */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pbdc1
-{
-    volatile uint16_t PBDC1;                                  /*  PBDC1           */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pipc1
-{
-    volatile uint16_t PIPC1;                                  /*  PIPC1           */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
 #define GPIO    (*(struct st_gpio    *)0xFCFE3004uL) /* GPIO */
 
-/* Start of channnel array defines of GPIO */
+
+/* Start of channel array defines of GPIO */
 
-/* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */
+/* Channel array defines of GPIO_FROM_PIPC1_ARRAY */
 /*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */
-#define GPIO_FROM_PIPC1_ARRAY_COUNT  11
+#define GPIO_FROM_PIPC1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \
@@ -692,9 +59,9 @@
 #define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */
 
 
-/* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */
+/* Channel array defines of GPIO_FROM_PBDC1_ARRAY */
 /*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */
-#define GPIO_FROM_PBDC1_ARRAY_COUNT  11
+#define GPIO_FROM_PBDC1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \
@@ -713,14 +80,15 @@
 #define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */
 
 
-/* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */
+/* Channel array defines of GPIO_FROM_PIBC1_ARRAY */
 /*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */
-#define GPIO_FROM_PIBC1_ARRAY_COUNT  11
+#define GPIO_FROM_PIBC1_ARRAY_COUNT  (12)
 #define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \
-    &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
+    &GPIO_FROM_PIBC0, &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, \
+    &GPIO_FROM_PIBC8, &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PIBC0 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC0) /* GPIO_FROM_PIBC0 */
 #define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */
 #define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */
 #define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */
@@ -734,9 +102,9 @@
 #define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */
 
 
-/* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */
+/* Channel array defines of GPIO_FROM_PFCAE1_ARRAY */
 /*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */
-#define GPIO_FROM_PFCAE1_ARRAY_COUNT  11
+#define GPIO_FROM_PFCAE1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \
@@ -755,9 +123,9 @@
 #define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */
 
 
-/* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */
+/* Channel array defines of GPIO_FROM_PNOT1_ARRAY */
 /*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */
-#define GPIO_FROM_PNOT1_ARRAY_COUNT  11
+#define GPIO_FROM_PNOT1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \
@@ -776,9 +144,9 @@
 #define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */
 
 
-/* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */
+/* Channel array defines of GPIO_FROM_PFCE1_ARRAY */
 /*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */
-#define GPIO_FROM_PFCE1_ARRAY_COUNT  11
+#define GPIO_FROM_PFCE1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \
@@ -797,9 +165,9 @@
 #define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */
 
 
-/* Channnel array defines of GPIO_FROM_PFC1_ARRAY */
+/* Channel array defines of GPIO_FROM_PFC1_ARRAY */
 /*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */
-#define GPIO_FROM_PFC1_ARRAY_COUNT  11
+#define GPIO_FROM_PFC1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \
@@ -818,9 +186,9 @@
 #define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */
 
 
-/* Channnel array defines of GPIO_FROM_PMC0_ARRAY */
+/* Channel array defines of GPIO_FROM_PMC0_ARRAY */
 /*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */
-#define GPIO_FROM_PMC0_ARRAY_COUNT  12
+#define GPIO_FROM_PMC0_ARRAY_COUNT  (12)
 #define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \
@@ -840,9 +208,9 @@
 #define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */
 
 
-/* Channnel array defines of GPIO_FROM_PM1_ARRAY */
+/* Channel array defines of GPIO_FROM_PM1_ARRAY */
 /*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */
-#define GPIO_FROM_PM1_ARRAY_COUNT  11
+#define GPIO_FROM_PM1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \
@@ -861,9 +229,9 @@
 #define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11)  /* GPIO_FROM_PM11 */
 
 
-/* Channnel array defines of GPIO_FROM_PPR0_ARRAY */
+/* Channel array defines of GPIO_FROM_PPR0_ARRAY */
 /*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */
-#define GPIO_FROM_PPR0_ARRAY_COUNT  12
+#define GPIO_FROM_PPR0_ARRAY_COUNT  (12)
 #define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \
@@ -883,9 +251,9 @@
 #define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */
 
 
-/* Channnel array defines of GPIO_FROM_P1_ARRAY */
+/* Channel array defines of GPIO_FROM_P1_ARRAY */
 /*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */
-#define GPIO_FROM_P1_ARRAY_COUNT  11
+#define GPIO_FROM_P1_ARRAY_COUNT  (11)
 #define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \
@@ -903,172 +271,1161 @@
 #define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10)     /* GPIO_FROM_P10 */
 #define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11)     /* GPIO_FROM_P11 */
 
-/* End of channnel array defines of GPIO */
+/* End of channel array defines of GPIO */
+
+
+#define GPIOP1 (GPIO.P1)
+#define GPIOP2 (GPIO.P2)
+#define GPIOP3 (GPIO.P3)
+#define GPIOP4 (GPIO.P4)
+#define GPIOP5 (GPIO.P5)
+#define GPIOP6 (GPIO.P6)
+#define GPIOP7 (GPIO.P7)
+#define GPIOP8 (GPIO.P8)
+#define GPIOP9 (GPIO.P9)
+#define GPIOP10 (GPIO.P10)
+#define GPIOP11 (GPIO.P11)
+#define GPIOPSR1 (GPIO.PSR1)
+#define GPIOPSR2 (GPIO.PSR2)
+#define GPIOPSR3 (GPIO.PSR3)
+#define GPIOPSR4 (GPIO.PSR4)
+#define GPIOPSR5 (GPIO.PSR5)
+#define GPIOPSR6 (GPIO.PSR6)
+#define GPIOPSR7 (GPIO.PSR7)
+#define GPIOPSR8 (GPIO.PSR8)
+#define GPIOPSR9 (GPIO.PSR9)
+#define GPIOPSR10 (GPIO.PSR10)
+#define GPIOPSR11 (GPIO.PSR11)
+#define GPIOPPR0 (GPIO.PPR0)
+#define GPIOPPR1 (GPIO.PPR1)
+#define GPIOPPR2 (GPIO.PPR2)
+#define GPIOPPR3 (GPIO.PPR3)
+#define GPIOPPR4 (GPIO.PPR4)
+#define GPIOPPR5 (GPIO.PPR5)
+#define GPIOPPR6 (GPIO.PPR6)
+#define GPIOPPR7 (GPIO.PPR7)
+#define GPIOPPR8 (GPIO.PPR8)
+#define GPIOPPR9 (GPIO.PPR9)
+#define GPIOPPR10 (GPIO.PPR10)
+#define GPIOPPR11 (GPIO.PPR11)
+#define GPIOPM1 (GPIO.PM1)
+#define GPIOPM2 (GPIO.PM2)
+#define GPIOPM3 (GPIO.PM3)
+#define GPIOPM4 (GPIO.PM4)
+#define GPIOPM5 (GPIO.PM5)
+#define GPIOPM6 (GPIO.PM6)
+#define GPIOPM7 (GPIO.PM7)
+#define GPIOPM8 (GPIO.PM8)
+#define GPIOPM9 (GPIO.PM9)
+#define GPIOPM10 (GPIO.PM10)
+#define GPIOPM11 (GPIO.PM11)
+#define GPIOPMC0 (GPIO.PMC0)
+#define GPIOPMC1 (GPIO.PMC1)
+#define GPIOPMC2 (GPIO.PMC2)
+#define GPIOPMC3 (GPIO.PMC3)
+#define GPIOPMC4 (GPIO.PMC4)
+#define GPIOPMC5 (GPIO.PMC5)
+#define GPIOPMC6 (GPIO.PMC6)
+#define GPIOPMC7 (GPIO.PMC7)
+#define GPIOPMC8 (GPIO.PMC8)
+#define GPIOPMC9 (GPIO.PMC9)
+#define GPIOPMC10 (GPIO.PMC10)
+#define GPIOPMC11 (GPIO.PMC11)
+#define GPIOPFC1 (GPIO.PFC1)
+#define GPIOPFC2 (GPIO.PFC2)
+#define GPIOPFC3 (GPIO.PFC3)
+#define GPIOPFC4 (GPIO.PFC4)
+#define GPIOPFC5 (GPIO.PFC5)
+#define GPIOPFC6 (GPIO.PFC6)
+#define GPIOPFC7 (GPIO.PFC7)
+#define GPIOPFC8 (GPIO.PFC8)
+#define GPIOPFC9 (GPIO.PFC9)
+#define GPIOPFC10 (GPIO.PFC10)
+#define GPIOPFC11 (GPIO.PFC11)
+#define GPIOPFCE1 (GPIO.PFCE1)
+#define GPIOPFCE2 (GPIO.PFCE2)
+#define GPIOPFCE3 (GPIO.PFCE3)
+#define GPIOPFCE4 (GPIO.PFCE4)
+#define GPIOPFCE5 (GPIO.PFCE5)
+#define GPIOPFCE6 (GPIO.PFCE6)
+#define GPIOPFCE7 (GPIO.PFCE7)
+#define GPIOPFCE8 (GPIO.PFCE8)
+#define GPIOPFCE9 (GPIO.PFCE9)
+#define GPIOPFCE10 (GPIO.PFCE10)
+#define GPIOPFCE11 (GPIO.PFCE11)
+#define GPIOPNOT1 (GPIO.PNOT1)
+#define GPIOPNOT2 (GPIO.PNOT2)
+#define GPIOPNOT3 (GPIO.PNOT3)
+#define GPIOPNOT4 (GPIO.PNOT4)
+#define GPIOPNOT5 (GPIO.PNOT5)
+#define GPIOPNOT6 (GPIO.PNOT6)
+#define GPIOPNOT7 (GPIO.PNOT7)
+#define GPIOPNOT8 (GPIO.PNOT8)
+#define GPIOPNOT9 (GPIO.PNOT9)
+#define GPIOPNOT10 (GPIO.PNOT10)
+#define GPIOPNOT11 (GPIO.PNOT11)
+#define GPIOPMSR1 (GPIO.PMSR1)
+#define GPIOPMSR2 (GPIO.PMSR2)
+#define GPIOPMSR3 (GPIO.PMSR3)
+#define GPIOPMSR4 (GPIO.PMSR4)
+#define GPIOPMSR5 (GPIO.PMSR5)
+#define GPIOPMSR6 (GPIO.PMSR6)
+#define GPIOPMSR7 (GPIO.PMSR7)
+#define GPIOPMSR8 (GPIO.PMSR8)
+#define GPIOPMSR9 (GPIO.PMSR9)
+#define GPIOPMSR10 (GPIO.PMSR10)
+#define GPIOPMSR11 (GPIO.PMSR11)
+#define GPIOPMCSR0 (GPIO.PMCSR0)
+#define GPIOPMCSR1 (GPIO.PMCSR1)
+#define GPIOPMCSR2 (GPIO.PMCSR2)
+#define GPIOPMCSR3 (GPIO.PMCSR3)
+#define GPIOPMCSR4 (GPIO.PMCSR4)
+#define GPIOPMCSR5 (GPIO.PMCSR5)
+#define GPIOPMCSR6 (GPIO.PMCSR6)
+#define GPIOPMCSR7 (GPIO.PMCSR7)
+#define GPIOPMCSR8 (GPIO.PMCSR8)
+#define GPIOPMCSR9 (GPIO.PMCSR9)
+#define GPIOPMCSR10 (GPIO.PMCSR10)
+#define GPIOPMCSR11 (GPIO.PMCSR11)
+#define GPIOPFCAE1 (GPIO.PFCAE1)
+#define GPIOPFCAE2 (GPIO.PFCAE2)
+#define GPIOPFCAE3 (GPIO.PFCAE3)
+#define GPIOPFCAE4 (GPIO.PFCAE4)
+#define GPIOPFCAE5 (GPIO.PFCAE5)
+#define GPIOPFCAE6 (GPIO.PFCAE6)
+#define GPIOPFCAE7 (GPIO.PFCAE7)
+#define GPIOPFCAE8 (GPIO.PFCAE8)
+#define GPIOPFCAE9 (GPIO.PFCAE9)
+#define GPIOPFCAE10 (GPIO.PFCAE10)
+#define GPIOPFCAE11 (GPIO.PFCAE11)
+#define GPIOSNCR (GPIO.SNCR)
+#define GPIOPIBC0 (GPIO.PIBC0)
+#define GPIOPIBC1 (GPIO.PIBC1)
+#define GPIOPIBC2 (GPIO.PIBC2)
+#define GPIOPIBC3 (GPIO.PIBC3)
+#define GPIOPIBC4 (GPIO.PIBC4)
+#define GPIOPIBC5 (GPIO.PIBC5)
+#define GPIOPIBC6 (GPIO.PIBC6)
+#define GPIOPIBC7 (GPIO.PIBC7)
+#define GPIOPIBC8 (GPIO.PIBC8)
+#define GPIOPIBC9 (GPIO.PIBC9)
+#define GPIOPIBC10 (GPIO.PIBC10)
+#define GPIOPIBC11 (GPIO.PIBC11)
+#define GPIOPBDC1 (GPIO.PBDC1)
+#define GPIOPBDC2 (GPIO.PBDC2)
+#define GPIOPBDC3 (GPIO.PBDC3)
+#define GPIOPBDC4 (GPIO.PBDC4)
+#define GPIOPBDC5 (GPIO.PBDC5)
+#define GPIOPBDC6 (GPIO.PBDC6)
+#define GPIOPBDC7 (GPIO.PBDC7)
+#define GPIOPBDC8 (GPIO.PBDC8)
+#define GPIOPBDC9 (GPIO.PBDC9)
+#define GPIOPBDC10 (GPIO.PBDC10)
+#define GPIOPBDC11 (GPIO.PBDC11)
+#define GPIOPIPC1 (GPIO.PIPC1)
+#define GPIOPIPC2 (GPIO.PIPC2)
+#define GPIOPIPC3 (GPIO.PIPC3)
+#define GPIOPIPC4 (GPIO.PIPC4)
+#define GPIOPIPC5 (GPIO.PIPC5)
+#define GPIOPIPC6 (GPIO.PIPC6)
+#define GPIOPIPC7 (GPIO.PIPC7)
+#define GPIOPIPC8 (GPIO.PIPC8)
+#define GPIOPIPC9 (GPIO.PIPC9)
+#define GPIOPIPC10 (GPIO.PIPC10)
+#define GPIOPIPC11 (GPIO.PIPC11)
+#define GPIOJPPR0 (GPIO.JPPR0)
+#define GPIOJPMC0 (GPIO.JPMC0)
+#define GPIOJPMCSR0 (GPIO.JPMCSR0)
+#define GPIOJPIBC0 (GPIO.JPIBC0)
+
+#define GPIO_PSRn_COUNT (11)
+#define GPIO_PMSRn_COUNT (11)
+#define GPIO_PMCSRn_COUNT (12)
 
 
-#define GPIOP1 GPIO.P1
-#define GPIOP2 GPIO.P2
-#define GPIOP3 GPIO.P3
-#define GPIOP4 GPIO.P4
-#define GPIOP5 GPIO.P5
-#define GPIOP6 GPIO.P6
-#define GPIOP7 GPIO.P7
-#define GPIOP8 GPIO.P8
-#define GPIOP9 GPIO.P9
-#define GPIOP10 GPIO.P10
-#define GPIOP11 GPIO.P11
-#define GPIOPSR1 GPIO.PSR1
-#define GPIOPSR2 GPIO.PSR2
-#define GPIOPSR3 GPIO.PSR3
-#define GPIOPSR4 GPIO.PSR4
-#define GPIOPSR5 GPIO.PSR5
-#define GPIOPSR6 GPIO.PSR6
-#define GPIOPSR7 GPIO.PSR7
-#define GPIOPSR8 GPIO.PSR8
-#define GPIOPSR9 GPIO.PSR9
-#define GPIOPSR10 GPIO.PSR10
-#define GPIOPSR11 GPIO.PSR11
-#define GPIOPPR0 GPIO.PPR0
-#define GPIOPPR1 GPIO.PPR1
-#define GPIOPPR2 GPIO.PPR2
-#define GPIOPPR3 GPIO.PPR3
-#define GPIOPPR4 GPIO.PPR4
-#define GPIOPPR5 GPIO.PPR5
-#define GPIOPPR6 GPIO.PPR6
-#define GPIOPPR7 GPIO.PPR7
-#define GPIOPPR8 GPIO.PPR8
-#define GPIOPPR9 GPIO.PPR9
-#define GPIOPPR10 GPIO.PPR10
-#define GPIOPPR11 GPIO.PPR11
-#define GPIOPM1 GPIO.PM1
-#define GPIOPM2 GPIO.PM2
-#define GPIOPM3 GPIO.PM3
-#define GPIOPM4 GPIO.PM4
-#define GPIOPM5 GPIO.PM5
-#define GPIOPM6 GPIO.PM6
-#define GPIOPM7 GPIO.PM7
-#define GPIOPM8 GPIO.PM8
-#define GPIOPM9 GPIO.PM9
-#define GPIOPM10 GPIO.PM10
-#define GPIOPM11 GPIO.PM11
-#define GPIOPMC0 GPIO.PMC0
-#define GPIOPMC1 GPIO.PMC1
-#define GPIOPMC2 GPIO.PMC2
-#define GPIOPMC3 GPIO.PMC3
-#define GPIOPMC4 GPIO.PMC4
-#define GPIOPMC5 GPIO.PMC5
-#define GPIOPMC6 GPIO.PMC6
-#define GPIOPMC7 GPIO.PMC7
-#define GPIOPMC8 GPIO.PMC8
-#define GPIOPMC9 GPIO.PMC9
-#define GPIOPMC10 GPIO.PMC10
-#define GPIOPMC11 GPIO.PMC11
-#define GPIOPFC1 GPIO.PFC1
-#define GPIOPFC2 GPIO.PFC2
-#define GPIOPFC3 GPIO.PFC3
-#define GPIOPFC4 GPIO.PFC4
-#define GPIOPFC5 GPIO.PFC5
-#define GPIOPFC6 GPIO.PFC6
-#define GPIOPFC7 GPIO.PFC7
-#define GPIOPFC8 GPIO.PFC8
-#define GPIOPFC9 GPIO.PFC9
-#define GPIOPFC10 GPIO.PFC10
-#define GPIOPFC11 GPIO.PFC11
-#define GPIOPFCE1 GPIO.PFCE1
-#define GPIOPFCE2 GPIO.PFCE2
-#define GPIOPFCE3 GPIO.PFCE3
-#define GPIOPFCE4 GPIO.PFCE4
-#define GPIOPFCE5 GPIO.PFCE5
-#define GPIOPFCE6 GPIO.PFCE6
-#define GPIOPFCE7 GPIO.PFCE7
-#define GPIOPFCE8 GPIO.PFCE8
-#define GPIOPFCE9 GPIO.PFCE9
-#define GPIOPFCE10 GPIO.PFCE10
-#define GPIOPFCE11 GPIO.PFCE11
-#define GPIOPNOT1 GPIO.PNOT1
-#define GPIOPNOT2 GPIO.PNOT2
-#define GPIOPNOT3 GPIO.PNOT3
-#define GPIOPNOT4 GPIO.PNOT4
-#define GPIOPNOT5 GPIO.PNOT5
-#define GPIOPNOT6 GPIO.PNOT6
-#define GPIOPNOT7 GPIO.PNOT7
-#define GPIOPNOT8 GPIO.PNOT8
-#define GPIOPNOT9 GPIO.PNOT9
-#define GPIOPNOT10 GPIO.PNOT10
-#define GPIOPNOT11 GPIO.PNOT11
-#define GPIOPMSR1 GPIO.PMSR1
-#define GPIOPMSR2 GPIO.PMSR2
-#define GPIOPMSR3 GPIO.PMSR3
-#define GPIOPMSR4 GPIO.PMSR4
-#define GPIOPMSR5 GPIO.PMSR5
-#define GPIOPMSR6 GPIO.PMSR6
-#define GPIOPMSR7 GPIO.PMSR7
-#define GPIOPMSR8 GPIO.PMSR8
-#define GPIOPMSR9 GPIO.PMSR9
-#define GPIOPMSR10 GPIO.PMSR10
-#define GPIOPMSR11 GPIO.PMSR11
-#define GPIOPMCSR0 GPIO.PMCSR0
-#define GPIOPMCSR1 GPIO.PMCSR1
-#define GPIOPMCSR2 GPIO.PMCSR2
-#define GPIOPMCSR3 GPIO.PMCSR3
-#define GPIOPMCSR4 GPIO.PMCSR4
-#define GPIOPMCSR5 GPIO.PMCSR5
-#define GPIOPMCSR6 GPIO.PMCSR6
-#define GPIOPMCSR7 GPIO.PMCSR7
-#define GPIOPMCSR8 GPIO.PMCSR8
-#define GPIOPMCSR9 GPIO.PMCSR9
-#define GPIOPMCSR10 GPIO.PMCSR10
-#define GPIOPMCSR11 GPIO.PMCSR11
-#define GPIOPFCAE1 GPIO.PFCAE1
-#define GPIOPFCAE2 GPIO.PFCAE2
-#define GPIOPFCAE3 GPIO.PFCAE3
-#define GPIOPFCAE4 GPIO.PFCAE4
-#define GPIOPFCAE5 GPIO.PFCAE5
-#define GPIOPFCAE6 GPIO.PFCAE6
-#define GPIOPFCAE7 GPIO.PFCAE7
-#define GPIOPFCAE8 GPIO.PFCAE8
-#define GPIOPFCAE9 GPIO.PFCAE9
-#define GPIOPFCAE10 GPIO.PFCAE10
-#define GPIOPFCAE11 GPIO.PFCAE11
-#define GPIOSNCR GPIO.SNCR
-#define GPIOPIBC0 GPIO.PIBC0
-#define GPIOPIBC1 GPIO.PIBC1
-#define GPIOPIBC2 GPIO.PIBC2
-#define GPIOPIBC3 GPIO.PIBC3
-#define GPIOPIBC4 GPIO.PIBC4
-#define GPIOPIBC5 GPIO.PIBC5
-#define GPIOPIBC6 GPIO.PIBC6
-#define GPIOPIBC7 GPIO.PIBC7
-#define GPIOPIBC8 GPIO.PIBC8
-#define GPIOPIBC9 GPIO.PIBC9
-#define GPIOPIBC10 GPIO.PIBC10
-#define GPIOPIBC11 GPIO.PIBC11
-#define GPIOPBDC1 GPIO.PBDC1
-#define GPIOPBDC2 GPIO.PBDC2
-#define GPIOPBDC3 GPIO.PBDC3
-#define GPIOPBDC4 GPIO.PBDC4
-#define GPIOPBDC5 GPIO.PBDC5
-#define GPIOPBDC6 GPIO.PBDC6
-#define GPIOPBDC7 GPIO.PBDC7
-#define GPIOPBDC8 GPIO.PBDC8
-#define GPIOPBDC9 GPIO.PBDC9
-#define GPIOPBDC10 GPIO.PBDC10
-#define GPIOPBDC11 GPIO.PBDC11
-#define GPIOPIPC1 GPIO.PIPC1
-#define GPIOPIPC2 GPIO.PIPC2
-#define GPIOPIPC3 GPIO.PIPC3
-#define GPIOPIPC4 GPIO.PIPC4
-#define GPIOPIPC5 GPIO.PIPC5
-#define GPIOPIPC6 GPIO.PIPC6
-#define GPIOPIPC7 GPIO.PIPC7
-#define GPIOPIPC8 GPIO.PIPC8
-#define GPIOPIPC9 GPIO.PIPC9
-#define GPIOPIPC10 GPIO.PIPC10
-#define GPIOPIPC11 GPIO.PIPC11
-#define GPIOJPPR0 GPIO.JPPR0
-#define GPIOJPMC0 GPIO.JPMC0
-#define GPIOJPMCSR0 GPIO.JPMCSR0
-#define GPIOJPIBC0 GPIO.JPIBC0
+typedef struct st_gpio
+{
+                                                           /* GPIO             */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P1;                                     /*  P1              */
+    volatile uint8_t   dummy348[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P2;                                     /*  P2              */
+    volatile uint8_t   dummy349[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P3;                                     /*  P3              */
+    volatile uint8_t   dummy350[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P4;                                     /*  P4              */
+    volatile uint8_t   dummy351[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P5;                                     /*  P5              */
+    volatile uint8_t   dummy352[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P6;                                     /*  P6              */
+    volatile uint8_t   dummy353[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P7;                                     /*  P7              */
+    volatile uint8_t   dummy354[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P8;                                     /*  P8              */
+    volatile uint8_t   dummy355[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P9;                                     /*  P9              */
+    volatile uint8_t   dummy356[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P10;                                    /*  P10             */
+    volatile uint8_t   dummy357[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P11;                                    /*  P11             */
+    volatile uint8_t   dummy3580[2];                           /*                  */
+
+/* end of struct st_gpio_from_p1 */
+    volatile uint8_t   dummy3581[212];                         /*                  */
+
+/* #define GPIO_PSRn_COUNT (11) */
+    volatile uint32_t  PSR1;                                   /*  PSR1            */
+    volatile uint32_t  PSR2;                                   /*  PSR2            */
+    volatile uint32_t  PSR3;                                   /*  PSR3            */
+    volatile uint32_t  PSR4;                                   /*  PSR4            */
+    volatile uint32_t  PSR5;                                   /*  PSR5            */
+    volatile uint32_t  PSR6;                                   /*  PSR6            */
+    volatile uint32_t  PSR7;                                   /*  PSR7            */
+    volatile uint32_t  PSR8;                                   /*  PSR8            */
+    volatile uint32_t  PSR9;                                   /*  PSR9            */
+    volatile uint32_t  PSR10;                                  /*  PSR10           */
+    volatile uint32_t  PSR11;                                  /*  PSR11           */
+    volatile uint8_t   dummy359[208];                          /*                  */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR0;                                   /*  PPR0            */
+    volatile uint8_t   dummy360[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR1;                                   /*  PPR1            */
+    volatile uint8_t   dummy361[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR2;                                   /*  PPR2            */
+    volatile uint8_t   dummy362[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR3;                                   /*  PPR3            */
+    volatile uint8_t   dummy363[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR4;                                   /*  PPR4            */
+    volatile uint8_t   dummy364[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR5;                                   /*  PPR5            */
+    volatile uint8_t   dummy365[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR6;                                   /*  PPR6            */
+    volatile uint8_t   dummy366[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR7;                                   /*  PPR7            */
+    volatile uint8_t   dummy367[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR8;                                   /*  PPR8            */
+    volatile uint8_t   dummy368[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR9;                                   /*  PPR9            */
+    volatile uint8_t   dummy369[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR10;                                  /*  PPR10           */
+    volatile uint8_t   dummy370[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR11;                                  /*  PPR11           */
+    volatile uint8_t   dummy3710[2];                           /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+    volatile uint8_t   dummy3711[212];                         /*                  */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM1;                                    /*  PM1             */
+    volatile uint8_t   dummy372[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM2;                                    /*  PM2             */
+    volatile uint8_t   dummy373[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM3;                                    /*  PM3             */
+    volatile uint8_t   dummy374[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM4;                                    /*  PM4             */
+    volatile uint8_t   dummy375[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM5;                                    /*  PM5             */
+    volatile uint8_t   dummy376[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM6;                                    /*  PM6             */
+    volatile uint8_t   dummy377[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM7;                                    /*  PM7             */
+    volatile uint8_t   dummy378[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM8;                                    /*  PM8             */
+    volatile uint8_t   dummy379[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM9;                                    /*  PM9             */
+    volatile uint8_t   dummy380[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM10;                                   /*  PM10            */
+    volatile uint8_t   dummy381[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM11;                                   /*  PM11            */
+    volatile uint8_t   dummy3820[2];                           /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+    volatile uint8_t   dummy3821[208];                         /*                  */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC0;                                   /*  PMC0            */
+    volatile uint8_t   dummy383[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC1;                                   /*  PMC1            */
+    volatile uint8_t   dummy384[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC2;                                   /*  PMC2            */
+    volatile uint8_t   dummy385[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC3;                                   /*  PMC3            */
+    volatile uint8_t   dummy386[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC4;                                   /*  PMC4            */
+    volatile uint8_t   dummy387[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC5;                                   /*  PMC5            */
+    volatile uint8_t   dummy388[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC6;                                   /*  PMC6            */
+    volatile uint8_t   dummy389[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC7;                                   /*  PMC7            */
+    volatile uint8_t   dummy390[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC8;                                   /*  PMC8            */
+    volatile uint8_t   dummy391[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC9;                                   /*  PMC9            */
+    volatile uint8_t   dummy392[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC10;                                  /*  PMC10           */
+    volatile uint8_t   dummy393[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC11;                                  /*  PMC11           */
+    volatile uint8_t   dummy3940[2];                           /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+    volatile uint8_t   dummy3941[212];                         /*                  */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC1;                                   /*  PFC1            */
+    volatile uint8_t   dummy395[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC2;                                   /*  PFC2            */
+    volatile uint8_t   dummy396[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC3;                                   /*  PFC3            */
+    volatile uint8_t   dummy397[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC4;                                   /*  PFC4            */
+    volatile uint8_t   dummy398[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC5;                                   /*  PFC5            */
+    volatile uint8_t   dummy399[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC6;                                   /*  PFC6            */
+    volatile uint8_t   dummy400[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC7;                                   /*  PFC7            */
+    volatile uint8_t   dummy401[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC8;                                   /*  PFC8            */
+    volatile uint8_t   dummy402[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC9;                                   /*  PFC9            */
+    volatile uint8_t   dummy403[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC10;                                  /*  PFC10           */
+    volatile uint8_t   dummy404[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC11;                                  /*  PFC11           */
+    volatile uint8_t   dummy4050[2];                           /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+    volatile uint8_t   dummy4051[212];                         /*                  */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE1;                                  /*  PFCE1           */
+    volatile uint8_t   dummy406[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE2;                                  /*  PFCE2           */
+    volatile uint8_t   dummy407[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE3;                                  /*  PFCE3           */
+    volatile uint8_t   dummy408[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE4;                                  /*  PFCE4           */
+    volatile uint8_t   dummy409[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE5;                                  /*  PFCE5           */
+    volatile uint8_t   dummy410[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE6;                                  /*  PFCE6           */
+    volatile uint8_t   dummy411[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE7;                                  /*  PFCE7           */
+    volatile uint8_t   dummy412[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE8;                                  /*  PFCE8           */
+    volatile uint8_t   dummy413[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE9;                                  /*  PFCE9           */
+    volatile uint8_t   dummy414[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE10;                                 /*  PFCE10          */
+    volatile uint8_t   dummy415[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE11;                                 /*  PFCE11          */
+    volatile uint8_t   dummy4160[2];                           /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+    volatile uint8_t   dummy4161[212];                         /*                  */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT1;                                  /*  PNOT1           */
+    volatile uint8_t   dummy417[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT2;                                  /*  PNOT2           */
+    volatile uint8_t   dummy418[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT3;                                  /*  PNOT3           */
+    volatile uint8_t   dummy419[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT4;                                  /*  PNOT4           */
+    volatile uint8_t   dummy420[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT5;                                  /*  PNOT5           */
+    volatile uint8_t   dummy421[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT6;                                  /*  PNOT6           */
+    volatile uint8_t   dummy422[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT7;                                  /*  PNOT7           */
+    volatile uint8_t   dummy423[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT8;                                  /*  PNOT8           */
+    volatile uint8_t   dummy424[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT9;                                  /*  PNOT9           */
+    volatile uint8_t   dummy425[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT10;                                 /*  PNOT10          */
+    volatile uint8_t   dummy426[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT11;                                 /*  PNOT11          */
+    volatile uint8_t   dummy4270[2];                           /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+    volatile uint8_t   dummy4271[212];                         /*                  */
+
+/* #define GPIO_PMSRn_COUNT (11) */
+    volatile uint32_t  PMSR1;                                  /*  PMSR1           */
+    volatile uint32_t  PMSR2;                                  /*  PMSR2           */
+    volatile uint32_t  PMSR3;                                  /*  PMSR3           */
+    volatile uint32_t  PMSR4;                                  /*  PMSR4           */
+    volatile uint32_t  PMSR5;                                  /*  PMSR5           */
+    volatile uint32_t  PMSR6;                                  /*  PMSR6           */
+    volatile uint32_t  PMSR7;                                  /*  PMSR7           */
+    volatile uint32_t  PMSR8;                                  /*  PMSR8           */
+    volatile uint32_t  PMSR9;                                  /*  PMSR9           */
+    volatile uint32_t  PMSR10;                                 /*  PMSR10          */
+    volatile uint32_t  PMSR11;                                 /*  PMSR11          */
+    volatile uint8_t   dummy428[208];                          /*                  */
+
+/* #define GPIO_PMCSRn_COUNT (12) */
+    volatile uint32_t  PMCSR0;                                 /*  PMCSR0          */
+    volatile uint32_t  PMCSR1;                                 /*  PMCSR1          */
+    volatile uint32_t  PMCSR2;                                 /*  PMCSR2          */
+    volatile uint32_t  PMCSR3;                                 /*  PMCSR3          */
+    volatile uint32_t  PMCSR4;                                 /*  PMCSR4          */
+    volatile uint32_t  PMCSR5;                                 /*  PMCSR5          */
+    volatile uint32_t  PMCSR6;                                 /*  PMCSR6          */
+    volatile uint32_t  PMCSR7;                                 /*  PMCSR7          */
+    volatile uint32_t  PMCSR8;                                 /*  PMCSR8          */
+    volatile uint32_t  PMCSR9;                                 /*  PMCSR9          */
+    volatile uint32_t  PMCSR10;                                /*  PMCSR10         */
+    volatile uint32_t  PMCSR11;                                /*  PMCSR11         */
+    volatile uint8_t   dummy429[212];                          /*                  */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
+    volatile uint8_t   dummy430[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE2;                                 /*  PFCAE2          */
+    volatile uint8_t   dummy431[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE3;                                 /*  PFCAE3          */
+    volatile uint8_t   dummy432[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE4;                                 /*  PFCAE4          */
+    volatile uint8_t   dummy433[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE5;                                 /*  PFCAE5          */
+    volatile uint8_t   dummy434[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE6;                                 /*  PFCAE6          */
+    volatile uint8_t   dummy435[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE7;                                 /*  PFCAE7          */
+    volatile uint8_t   dummy436[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE8;                                 /*  PFCAE8          */
+    volatile uint8_t   dummy437[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE9;                                 /*  PFCAE9          */
+    volatile uint8_t   dummy438[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE10;                                /*  PFCAE10         */
+    volatile uint8_t   dummy439[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE11;                                /*  PFCAE11         */
+    volatile uint8_t   dummy4400[2];                           /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+    volatile uint8_t   dummy4401[464];                         /*                  */
+    volatile uint32_t  SNCR;                                   /*  SNCR            */
+    volatile uint8_t   dummy441[13308];                        /*                  */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC0;                                  /*  PIBC0           */
+    volatile uint8_t   dummy442[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC1;                                  /*  PIBC1           */
+    volatile uint8_t   dummy443[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC2;                                  /*  PIBC2           */
+    volatile uint8_t   dummy444[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC3;                                  /*  PIBC3           */
+    volatile uint8_t   dummy445[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC4;                                  /*  PIBC4           */
+    volatile uint8_t   dummy446[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC5;                                  /*  PIBC5           */
+    volatile uint8_t   dummy447[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC6;                                  /*  PIBC6           */
+    volatile uint8_t   dummy448[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC7;                                  /*  PIBC7           */
+    volatile uint8_t   dummy449[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC8;                                  /*  PIBC8           */
+    volatile uint8_t   dummy450[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC9;                                  /*  PIBC9           */
+    volatile uint8_t   dummy451[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC10;                                 /*  PIBC10          */
+    volatile uint8_t   dummy452[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC11;                                 /*  PIBC11          */
+    volatile uint8_t   dummy4530[2];                           /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+    volatile uint8_t   dummy4531[212];                         /*                  */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC1;                                  /*  PBDC1           */
+    volatile uint8_t   dummy454[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC2;                                  /*  PBDC2           */
+    volatile uint8_t   dummy455[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC3;                                  /*  PBDC3           */
+    volatile uint8_t   dummy456[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC4;                                  /*  PBDC4           */
+    volatile uint8_t   dummy457[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC5;                                  /*  PBDC5           */
+    volatile uint8_t   dummy458[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC6;                                  /*  PBDC6           */
+    volatile uint8_t   dummy459[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC7;                                  /*  PBDC7           */
+    volatile uint8_t   dummy460[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC8;                                  /*  PBDC8           */
+    volatile uint8_t   dummy461[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC9;                                  /*  PBDC9           */
+    volatile uint8_t   dummy462[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC10;                                 /*  PBDC10          */
+    volatile uint8_t   dummy463[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC11;                                 /*  PBDC11          */
+    volatile uint8_t   dummy4640[2];                           /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+    volatile uint8_t   dummy4641[212];                         /*                  */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC1;                                  /*  PIPC1           */
+    volatile uint8_t   dummy465[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC2;                                  /*  PIPC2           */
+    volatile uint8_t   dummy466[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC3;                                  /*  PIPC3           */
+    volatile uint8_t   dummy467[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC4;                                  /*  PIPC4           */
+    volatile uint8_t   dummy468[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC5;                                  /*  PIPC5           */
+    volatile uint8_t   dummy469[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC6;                                  /*  PIPC6           */
+    volatile uint8_t   dummy470[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC7;                                  /*  PIPC7           */
+    volatile uint8_t   dummy471[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC8;                                  /*  PIPC8           */
+    volatile uint8_t   dummy472[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC9;                                  /*  PIPC9           */
+    volatile uint8_t   dummy473[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC10;                                 /*  PIPC10          */
+    volatile uint8_t   dummy474[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC11;                                 /*  PIPC11          */
+    volatile uint8_t   dummy4750[2];                           /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+    volatile uint8_t   dummy4751[2288];                        /*                  */
+    volatile uint16_t JPPR0;                                  /*  JPPR0           */
+    volatile uint8_t   dummy476[30];                           /*                  */
+    volatile uint16_t JPMC0;                                  /*  JPMC0           */
+    volatile uint8_t   dummy477[78];                           /*                  */
+    volatile uint32_t  JPMCSR0;                                /*  JPMCSR0         */
+    volatile uint8_t   dummy478[876];                          /*                  */
+    volatile uint16_t JPIBC0;                                 /*  JPIBC0          */
+} r_io_gpio_t;
+
+
+typedef struct st_gpio_from_p1
+{
+ 
+    volatile uint16_t P1;                                     /*  P1              */
+    volatile uint8_t   dummy1[3];                              /*                  */
+} r_io_gpio_from_p1_t;
+
+
+typedef struct st_gpio_from_ppr0
+{
+ 
+    volatile uint16_t PPR0;                                   /*  PPR0            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_ppr0_t;
+
+
+typedef struct st_gpio_from_pm1
+{
+ 
+    volatile uint16_t PM1;                                    /*  PM1             */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pm1_t;
+
+
+typedef struct st_gpio_from_pmc0
+{
+ 
+    volatile uint16_t PMC0;                                   /*  PMC0            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pmc0_t;
+
+
+typedef struct st_gpio_from_pfc1
+{
+ 
+    volatile uint16_t PFC1;                                   /*  PFC1            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pfc1_t;
+
+
+typedef struct st_gpio_from_pfce1
+{
+ 
+    volatile uint16_t PFCE1;                                  /*  PFCE1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pfce1_t;
+
+
+typedef struct st_gpio_from_pnot1
+{
+ 
+    volatile uint16_t PNOT1;                                  /*  PNOT1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pnot1_t;
+
+
+typedef struct st_gpio_from_pfcae1
+{
+ 
+    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pfcae1_t;
+
+
+typedef struct st_gpio_from_pibc1
+{
+ 
+    volatile uint16_t PIBC1;                                  /*  PIBC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pibc1_t;
+
+
+typedef struct st_gpio_from_pbdc1
+{
+ 
+    volatile uint16_t PBDC1;                                  /*  PBDC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pbdc1_t;
+
+
+typedef struct st_gpio_from_pipc1
+{
+ 
+    volatile uint16_t PIPC1;                                  /*  PIPC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pipc1_t;
+
+
+/* Channel array defines of GPIO (2)*/
+#ifdef  DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pipc1*  GPIO_FROM_PIPC1_ARRAY[ GPIO_FROM_PIPC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pbdc1*  GPIO_FROM_PBDC1_ARRAY[ GPIO_FROM_PBDC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pibc1*  GPIO_FROM_PIBC1_ARRAY[ GPIO_FROM_PIBC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pfcae1*  GPIO_FROM_PFCAE1_ARRAY[ GPIO_FROM_PFCAE1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pnot1*  GPIO_FROM_PNOT1_ARRAY[ GPIO_FROM_PNOT1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pfce1*  GPIO_FROM_PFCE1_ARRAY[ GPIO_FROM_PFCE1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pfc1*  GPIO_FROM_PFC1_ARRAY[ GPIO_FROM_PFC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS
+volatile struct st_gpio_from_pmc0*  GPIO_FROM_PMC0_ARRAY[ GPIO_FROM_PMC0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pm1*  GPIO_FROM_PM1_ARRAY[ GPIO_FROM_PM1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PM1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS
+volatile struct st_gpio_from_ppr0*  GPIO_FROM_PPR0_ARRAY[ GPIO_FROM_PPR0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS
+volatile struct st_gpio_from_p1*  GPIO_FROM_P1_ARRAY[ GPIO_FROM_P1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_P1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS */
+/* End of channel array defines of GPIO (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,55 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : ieb_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef IEB_IODEFINE_H
 #define IEB_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_ieb
-{                                                          /* IEB              */
+#define IEB     (*(struct st_ieb     *)0xFCFEF000uL) /* IEB */
+
+
+#define IEBB0BCR (IEB.B0BCR)
+#define IEBB0PSR (IEB.B0PSR)
+#define IEBB0UAR (IEB.B0UAR)
+#define IEBB0SAR (IEB.B0SAR)
+#define IEBB0PAR (IEB.B0PAR)
+#define IEBB0RSA (IEB.B0RSA)
+#define IEBB0CDR (IEB.B0CDR)
+#define IEBB0TCD (IEB.B0TCD)
+#define IEBB0RCD (IEB.B0RCD)
+#define IEBB0DLR (IEB.B0DLR)
+#define IEBB0TDL (IEB.B0TDL)
+#define IEBB0RDL (IEB.B0RDL)
+#define IEBB0CKS (IEB.B0CKS)
+#define IEBB0TMS (IEB.B0TMS)
+#define IEBB0PCR (IEB.B0PCR)
+#define IEBB0BSR (IEB.B0BSR)
+#define IEBB0SSR (IEB.B0SSR)
+#define IEBB0USR (IEB.B0USR)
+#define IEBB0ISR (IEB.B0ISR)
+#define IEBB0ESR (IEB.B0ESR)
+#define IEBB0FSR (IEB.B0FSR)
+#define IEBB0SCR (IEB.B0SCR)
+#define IEBB0CCR (IEB.B0CCR)
+#define IEBB0STC0 (IEB.B0STC0)
+#define IEBB0STC1 (IEB.B0STC1)
+#define IEBB0DR (IEB.B0DR)
+
+
+typedef struct st_ieb
+{
+                                                           /* IEB              */
     volatile uint8_t   B0BCR;                                  /*  B0BCR           */
     volatile uint8_t   dummy495[3];                            /*                  */
     volatile uint8_t   B0PSR;                                  /*  B0PSR           */
@@ -83,37 +118,11 @@
     volatile uint8_t   B0STC1;                                 /*  B0STC1          */
     volatile uint8_t   dummy519[3];                            /*                  */
     volatile uint8_t   B0DR;                                   /*  B0DR            */
-};
-
-
-#define IEB     (*(struct st_ieb     *)0xFCFEF000uL) /* IEB */
+} r_io_ieb_t;
 
 
-#define IEBB0BCR IEB.B0BCR
-#define IEBB0PSR IEB.B0PSR
-#define IEBB0UAR IEB.B0UAR
-#define IEBB0SAR IEB.B0SAR
-#define IEBB0PAR IEB.B0PAR
-#define IEBB0RSA IEB.B0RSA
-#define IEBB0CDR IEB.B0CDR
-#define IEBB0TCD IEB.B0TCD
-#define IEBB0RCD IEB.B0RCD
-#define IEBB0DLR IEB.B0DLR
-#define IEBB0TDL IEB.B0TDL
-#define IEBB0RDL IEB.B0RDL
-#define IEBB0CKS IEB.B0CKS
-#define IEBB0TMS IEB.B0TMS
-#define IEBB0PCR IEB.B0PCR
-#define IEBB0BSR IEB.B0BSR
-#define IEBB0SSR IEB.B0SSR
-#define IEBB0USR IEB.B0USR
-#define IEBB0ISR IEB.B0ISR
-#define IEBB0ESR IEB.B0ESR
-#define IEBB0FSR IEB.B0FSR
-#define IEBB0SCR IEB.B0SCR
-#define IEBB0CCR IEB.B0CCR
-#define IEBB0STC0 IEB.B0STC0
-#define IEBB0STC1 IEB.B0STC1
-#define IEBB0DR IEB.B0DR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,21 +18,61 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : inb_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef INB_IODEFINE_H
 #define INB_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
-struct st_inb
-{                                                          /* INB              */
+#define INB     (*(struct st_inb     *)0xFCFE1A00uL) /* INB */
+
+
+#define INBRMPR (INB.RMPR)
+#define INBAXIBUSCTL0 (INB.AXIBUSCTL0)
+#define INBAXIBUSCTL1 (INB.AXIBUSCTL1)
+#define INBAXIBUSCTL2 (INB.AXIBUSCTL2)
+#define INBAXIBUSCTL3 (INB.AXIBUSCTL3)
+#define INBAXIBUSCTL4 (INB.AXIBUSCTL4)
+#define INBAXIBUSCTL5 (INB.AXIBUSCTL5)
+#define INBAXIBUSCTL6 (INB.AXIBUSCTL6)
+#define INBAXIBUSCTL7 (INB.AXIBUSCTL7)
+#define INBAXIBUSCTL8 (INB.AXIBUSCTL8)
+#define INBAXIBUSCTL9 (INB.AXIBUSCTL9)
+#define INBAXIBUSCTL10 (INB.AXIBUSCTL10)
+#define INBAXIRERRCTL0 (INB.AXIRERRCTL0)
+#define INBAXIRERRCTL1 (INB.AXIRERRCTL1)
+#define INBAXIRERRCTL2 (INB.AXIRERRCTL2)
+#define INBAXIRERRCTL3 (INB.AXIRERRCTL3)
+#define INBAXIRERRST0 (INB.AXIRERRST0)
+#define INBAXIRERRST1 (INB.AXIRERRST1)
+#define INBAXIRERRST2 (INB.AXIRERRST2)
+#define INBAXIRERRST3 (INB.AXIRERRST3)
+#define INBAXIRERRCLR0 (INB.AXIRERRCLR0)
+#define INBAXIRERRCLR1 (INB.AXIRERRCLR1)
+#define INBAXIRERRCLR2 (INB.AXIRERRCLR2)
+#define INBAXIRERRCLR3 (INB.AXIRERRCLR3)
+
+#define INB_AXIBUSCTLn_COUNT (11)
+#define INB_AXIRERRCTLn_COUNT (4)
+#define INB_AXIRERRSTn_COUNT (4)
+#define INB_AXIRERRCLRn_COUNT (4)
+
+
+typedef struct st_inb
+{
+                                                           /* INB              */
     volatile uint32_t  RMPR;                                   /*  RMPR            */
-#define INB_AXIBUSCTLn_COUNT 11
+
+/* #define INB_AXIBUSCTLn_COUNT (11) */
     volatile uint32_t  AXIBUSCTL0;                             /*  AXIBUSCTL0      */
     volatile uint32_t  AXIBUSCTL1;                             /*  AXIBUSCTL1      */
     volatile uint32_t  AXIBUSCTL2;                             /*  AXIBUSCTL2      */
@@ -44,49 +84,29 @@
     volatile uint32_t  AXIBUSCTL8;                             /*  AXIBUSCTL8      */
     volatile uint32_t  AXIBUSCTL9;                             /*  AXIBUSCTL9      */
     volatile uint32_t  AXIBUSCTL10;                            /*  AXIBUSCTL10     */
-#define INB_AXIRERRCTLn_COUNT 4
+
+/* #define INB_AXIRERRCTLn_COUNT (4) */
     volatile uint32_t  AXIRERRCTL0;                            /*  AXIRERRCTL0     */
     volatile uint32_t  AXIRERRCTL1;                            /*  AXIRERRCTL1     */
     volatile uint32_t  AXIRERRCTL2;                            /*  AXIRERRCTL2     */
     volatile uint32_t  AXIRERRCTL3;                            /*  AXIRERRCTL3     */
-#define INB_AXIRERRSTn_COUNT 4
+
+/* #define INB_AXIRERRSTn_COUNT (4) */
     volatile uint32_t  AXIRERRST0;                             /*  AXIRERRST0      */
     volatile uint32_t  AXIRERRST1;                             /*  AXIRERRST1      */
     volatile uint32_t  AXIRERRST2;                             /*  AXIRERRST2      */
     volatile uint32_t  AXIRERRST3;                             /*  AXIRERRST3      */
-#define INB_AXIRERRCLRn_COUNT 4
+
+/* #define INB_AXIRERRCLRn_COUNT (4) */
     volatile uint32_t  AXIRERRCLR0;                            /*  AXIRERRCLR0     */
     volatile uint32_t  AXIRERRCLR1;                            /*  AXIRERRCLR1     */
     volatile uint32_t  AXIRERRCLR2;                            /*  AXIRERRCLR2     */
     volatile uint32_t  AXIRERRCLR3;                            /*  AXIRERRCLR3     */
-};
-
-
-#define INB     (*(struct st_inb     *)0xFCFE1A00uL) /* INB */
+} r_io_inb_t;
 
 
-#define INBRMPR INB.RMPR
-#define INBAXIBUSCTL0 INB.AXIBUSCTL0
-#define INBAXIBUSCTL1 INB.AXIBUSCTL1
-#define INBAXIBUSCTL2 INB.AXIBUSCTL2
-#define INBAXIBUSCTL3 INB.AXIBUSCTL3
-#define INBAXIBUSCTL4 INB.AXIBUSCTL4
-#define INBAXIBUSCTL5 INB.AXIBUSCTL5
-#define INBAXIBUSCTL6 INB.AXIBUSCTL6
-#define INBAXIBUSCTL7 INB.AXIBUSCTL7
-#define INBAXIBUSCTL8 INB.AXIBUSCTL8
-#define INBAXIBUSCTL9 INB.AXIBUSCTL9
-#define INBAXIBUSCTL10 INB.AXIBUSCTL10
-#define INBAXIRERRCTL0 INB.AXIRERRCTL0
-#define INBAXIRERRCTL1 INB.AXIRERRCTL1
-#define INBAXIRERRCTL2 INB.AXIRERRCTL2
-#define INBAXIRERRCTL3 INB.AXIRERRCTL3
-#define INBAXIRERRST0 INB.AXIRERRST0
-#define INBAXIRERRST1 INB.AXIRERRST1
-#define INBAXIRERRST2 INB.AXIRERRST2
-#define INBAXIRERRST3 INB.AXIRERRST3
-#define INBAXIRERRCLR0 INB.AXIRERRCLR0
-#define INBAXIRERRCLR1 INB.AXIRERRCLR1
-#define INBAXIRERRCLR2 INB.AXIRERRCLR2
-#define INBAXIRERRCLR3 INB.AXIRERRCLR3
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,26 +18,525 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : intc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef INTC_IODEFINE_H
 #define INTC_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_intc
-{                                                          /* INTC             */
+#define INTC    (*(struct st_intc    *)0xE8201000uL) /* INTC */
+
+
+#define INTCICDDCR (INTC.ICDDCR)
+#define INTCICDICTR (INTC.ICDICTR)
+#define INTCICDIIDR (INTC.ICDIIDR)
+#define INTCICDISR0 (INTC.ICDISR0)
+#define INTCICDISR1 (INTC.ICDISR1)
+#define INTCICDISR2 (INTC.ICDISR2)
+#define INTCICDISR3 (INTC.ICDISR3)
+#define INTCICDISR4 (INTC.ICDISR4)
+#define INTCICDISR5 (INTC.ICDISR5)
+#define INTCICDISR6 (INTC.ICDISR6)
+#define INTCICDISR7 (INTC.ICDISR7)
+#define INTCICDISR8 (INTC.ICDISR8)
+#define INTCICDISR9 (INTC.ICDISR9)
+#define INTCICDISR10 (INTC.ICDISR10)
+#define INTCICDISR11 (INTC.ICDISR11)
+#define INTCICDISR12 (INTC.ICDISR12)
+#define INTCICDISR13 (INTC.ICDISR13)
+#define INTCICDISR14 (INTC.ICDISR14)
+#define INTCICDISR15 (INTC.ICDISR15)
+#define INTCICDISR16 (INTC.ICDISR16)
+#define INTCICDISR17 (INTC.ICDISR17)
+#define INTCICDISR18 (INTC.ICDISR18)
+#define INTCICDISER0 (INTC.ICDISER0)
+#define INTCICDISER1 (INTC.ICDISER1)
+#define INTCICDISER2 (INTC.ICDISER2)
+#define INTCICDISER3 (INTC.ICDISER3)
+#define INTCICDISER4 (INTC.ICDISER4)
+#define INTCICDISER5 (INTC.ICDISER5)
+#define INTCICDISER6 (INTC.ICDISER6)
+#define INTCICDISER7 (INTC.ICDISER7)
+#define INTCICDISER8 (INTC.ICDISER8)
+#define INTCICDISER9 (INTC.ICDISER9)
+#define INTCICDISER10 (INTC.ICDISER10)
+#define INTCICDISER11 (INTC.ICDISER11)
+#define INTCICDISER12 (INTC.ICDISER12)
+#define INTCICDISER13 (INTC.ICDISER13)
+#define INTCICDISER14 (INTC.ICDISER14)
+#define INTCICDISER15 (INTC.ICDISER15)
+#define INTCICDISER16 (INTC.ICDISER16)
+#define INTCICDISER17 (INTC.ICDISER17)
+#define INTCICDISER18 (INTC.ICDISER18)
+#define INTCICDICER0 (INTC.ICDICER0)
+#define INTCICDICER1 (INTC.ICDICER1)
+#define INTCICDICER2 (INTC.ICDICER2)
+#define INTCICDICER3 (INTC.ICDICER3)
+#define INTCICDICER4 (INTC.ICDICER4)
+#define INTCICDICER5 (INTC.ICDICER5)
+#define INTCICDICER6 (INTC.ICDICER6)
+#define INTCICDICER7 (INTC.ICDICER7)
+#define INTCICDICER8 (INTC.ICDICER8)
+#define INTCICDICER9 (INTC.ICDICER9)
+#define INTCICDICER10 (INTC.ICDICER10)
+#define INTCICDICER11 (INTC.ICDICER11)
+#define INTCICDICER12 (INTC.ICDICER12)
+#define INTCICDICER13 (INTC.ICDICER13)
+#define INTCICDICER14 (INTC.ICDICER14)
+#define INTCICDICER15 (INTC.ICDICER15)
+#define INTCICDICER16 (INTC.ICDICER16)
+#define INTCICDICER17 (INTC.ICDICER17)
+#define INTCICDICER18 (INTC.ICDICER18)
+#define INTCICDISPR0 (INTC.ICDISPR0)
+#define INTCICDISPR1 (INTC.ICDISPR1)
+#define INTCICDISPR2 (INTC.ICDISPR2)
+#define INTCICDISPR3 (INTC.ICDISPR3)
+#define INTCICDISPR4 (INTC.ICDISPR4)
+#define INTCICDISPR5 (INTC.ICDISPR5)
+#define INTCICDISPR6 (INTC.ICDISPR6)
+#define INTCICDISPR7 (INTC.ICDISPR7)
+#define INTCICDISPR8 (INTC.ICDISPR8)
+#define INTCICDISPR9 (INTC.ICDISPR9)
+#define INTCICDISPR10 (INTC.ICDISPR10)
+#define INTCICDISPR11 (INTC.ICDISPR11)
+#define INTCICDISPR12 (INTC.ICDISPR12)
+#define INTCICDISPR13 (INTC.ICDISPR13)
+#define INTCICDISPR14 (INTC.ICDISPR14)
+#define INTCICDISPR15 (INTC.ICDISPR15)
+#define INTCICDISPR16 (INTC.ICDISPR16)
+#define INTCICDISPR17 (INTC.ICDISPR17)
+#define INTCICDISPR18 (INTC.ICDISPR18)
+#define INTCICDICPR0 (INTC.ICDICPR0)
+#define INTCICDICPR1 (INTC.ICDICPR1)
+#define INTCICDICPR2 (INTC.ICDICPR2)
+#define INTCICDICPR3 (INTC.ICDICPR3)
+#define INTCICDICPR4 (INTC.ICDICPR4)
+#define INTCICDICPR5 (INTC.ICDICPR5)
+#define INTCICDICPR6 (INTC.ICDICPR6)
+#define INTCICDICPR7 (INTC.ICDICPR7)
+#define INTCICDICPR8 (INTC.ICDICPR8)
+#define INTCICDICPR9 (INTC.ICDICPR9)
+#define INTCICDICPR10 (INTC.ICDICPR10)
+#define INTCICDICPR11 (INTC.ICDICPR11)
+#define INTCICDICPR12 (INTC.ICDICPR12)
+#define INTCICDICPR13 (INTC.ICDICPR13)
+#define INTCICDICPR14 (INTC.ICDICPR14)
+#define INTCICDICPR15 (INTC.ICDICPR15)
+#define INTCICDICPR16 (INTC.ICDICPR16)
+#define INTCICDICPR17 (INTC.ICDICPR17)
+#define INTCICDICPR18 (INTC.ICDICPR18)
+#define INTCICDABR0 (INTC.ICDABR0)
+#define INTCICDABR1 (INTC.ICDABR1)
+#define INTCICDABR2 (INTC.ICDABR2)
+#define INTCICDABR3 (INTC.ICDABR3)
+#define INTCICDABR4 (INTC.ICDABR4)
+#define INTCICDABR5 (INTC.ICDABR5)
+#define INTCICDABR6 (INTC.ICDABR6)
+#define INTCICDABR7 (INTC.ICDABR7)
+#define INTCICDABR8 (INTC.ICDABR8)
+#define INTCICDABR9 (INTC.ICDABR9)
+#define INTCICDABR10 (INTC.ICDABR10)
+#define INTCICDABR11 (INTC.ICDABR11)
+#define INTCICDABR12 (INTC.ICDABR12)
+#define INTCICDABR13 (INTC.ICDABR13)
+#define INTCICDABR14 (INTC.ICDABR14)
+#define INTCICDABR15 (INTC.ICDABR15)
+#define INTCICDABR16 (INTC.ICDABR16)
+#define INTCICDABR17 (INTC.ICDABR17)
+#define INTCICDABR18 (INTC.ICDABR18)
+#define INTCICDIPR0 (INTC.ICDIPR0)
+#define INTCICDIPR1 (INTC.ICDIPR1)
+#define INTCICDIPR2 (INTC.ICDIPR2)
+#define INTCICDIPR3 (INTC.ICDIPR3)
+#define INTCICDIPR4 (INTC.ICDIPR4)
+#define INTCICDIPR5 (INTC.ICDIPR5)
+#define INTCICDIPR6 (INTC.ICDIPR6)
+#define INTCICDIPR7 (INTC.ICDIPR7)
+#define INTCICDIPR8 (INTC.ICDIPR8)
+#define INTCICDIPR9 (INTC.ICDIPR9)
+#define INTCICDIPR10 (INTC.ICDIPR10)
+#define INTCICDIPR11 (INTC.ICDIPR11)
+#define INTCICDIPR12 (INTC.ICDIPR12)
+#define INTCICDIPR13 (INTC.ICDIPR13)
+#define INTCICDIPR14 (INTC.ICDIPR14)
+#define INTCICDIPR15 (INTC.ICDIPR15)
+#define INTCICDIPR16 (INTC.ICDIPR16)
+#define INTCICDIPR17 (INTC.ICDIPR17)
+#define INTCICDIPR18 (INTC.ICDIPR18)
+#define INTCICDIPR19 (INTC.ICDIPR19)
+#define INTCICDIPR20 (INTC.ICDIPR20)
+#define INTCICDIPR21 (INTC.ICDIPR21)
+#define INTCICDIPR22 (INTC.ICDIPR22)
+#define INTCICDIPR23 (INTC.ICDIPR23)
+#define INTCICDIPR24 (INTC.ICDIPR24)
+#define INTCICDIPR25 (INTC.ICDIPR25)
+#define INTCICDIPR26 (INTC.ICDIPR26)
+#define INTCICDIPR27 (INTC.ICDIPR27)
+#define INTCICDIPR28 (INTC.ICDIPR28)
+#define INTCICDIPR29 (INTC.ICDIPR29)
+#define INTCICDIPR30 (INTC.ICDIPR30)
+#define INTCICDIPR31 (INTC.ICDIPR31)
+#define INTCICDIPR32 (INTC.ICDIPR32)
+#define INTCICDIPR33 (INTC.ICDIPR33)
+#define INTCICDIPR34 (INTC.ICDIPR34)
+#define INTCICDIPR35 (INTC.ICDIPR35)
+#define INTCICDIPR36 (INTC.ICDIPR36)
+#define INTCICDIPR37 (INTC.ICDIPR37)
+#define INTCICDIPR38 (INTC.ICDIPR38)
+#define INTCICDIPR39 (INTC.ICDIPR39)
+#define INTCICDIPR40 (INTC.ICDIPR40)
+#define INTCICDIPR41 (INTC.ICDIPR41)
+#define INTCICDIPR42 (INTC.ICDIPR42)
+#define INTCICDIPR43 (INTC.ICDIPR43)
+#define INTCICDIPR44 (INTC.ICDIPR44)
+#define INTCICDIPR45 (INTC.ICDIPR45)
+#define INTCICDIPR46 (INTC.ICDIPR46)
+#define INTCICDIPR47 (INTC.ICDIPR47)
+#define INTCICDIPR48 (INTC.ICDIPR48)
+#define INTCICDIPR49 (INTC.ICDIPR49)
+#define INTCICDIPR50 (INTC.ICDIPR50)
+#define INTCICDIPR51 (INTC.ICDIPR51)
+#define INTCICDIPR52 (INTC.ICDIPR52)
+#define INTCICDIPR53 (INTC.ICDIPR53)
+#define INTCICDIPR54 (INTC.ICDIPR54)
+#define INTCICDIPR55 (INTC.ICDIPR55)
+#define INTCICDIPR56 (INTC.ICDIPR56)
+#define INTCICDIPR57 (INTC.ICDIPR57)
+#define INTCICDIPR58 (INTC.ICDIPR58)
+#define INTCICDIPR59 (INTC.ICDIPR59)
+#define INTCICDIPR60 (INTC.ICDIPR60)
+#define INTCICDIPR61 (INTC.ICDIPR61)
+#define INTCICDIPR62 (INTC.ICDIPR62)
+#define INTCICDIPR63 (INTC.ICDIPR63)
+#define INTCICDIPR64 (INTC.ICDIPR64)
+#define INTCICDIPR65 (INTC.ICDIPR65)
+#define INTCICDIPR66 (INTC.ICDIPR66)
+#define INTCICDIPR67 (INTC.ICDIPR67)
+#define INTCICDIPR68 (INTC.ICDIPR68)
+#define INTCICDIPR69 (INTC.ICDIPR69)
+#define INTCICDIPR70 (INTC.ICDIPR70)
+#define INTCICDIPR71 (INTC.ICDIPR71)
+#define INTCICDIPR72 (INTC.ICDIPR72)
+#define INTCICDIPR73 (INTC.ICDIPR73)
+#define INTCICDIPR74 (INTC.ICDIPR74)
+#define INTCICDIPR75 (INTC.ICDIPR75)
+#define INTCICDIPR76 (INTC.ICDIPR76)
+#define INTCICDIPR77 (INTC.ICDIPR77)
+#define INTCICDIPR78 (INTC.ICDIPR78)
+#define INTCICDIPR79 (INTC.ICDIPR79)
+#define INTCICDIPR80 (INTC.ICDIPR80)
+#define INTCICDIPR81 (INTC.ICDIPR81)
+#define INTCICDIPR82 (INTC.ICDIPR82)
+#define INTCICDIPR83 (INTC.ICDIPR83)
+#define INTCICDIPR84 (INTC.ICDIPR84)
+#define INTCICDIPR85 (INTC.ICDIPR85)
+#define INTCICDIPR86 (INTC.ICDIPR86)
+#define INTCICDIPR87 (INTC.ICDIPR87)
+#define INTCICDIPR88 (INTC.ICDIPR88)
+#define INTCICDIPR89 (INTC.ICDIPR89)
+#define INTCICDIPR90 (INTC.ICDIPR90)
+#define INTCICDIPR91 (INTC.ICDIPR91)
+#define INTCICDIPR92 (INTC.ICDIPR92)
+#define INTCICDIPR93 (INTC.ICDIPR93)
+#define INTCICDIPR94 (INTC.ICDIPR94)
+#define INTCICDIPR95 (INTC.ICDIPR95)
+#define INTCICDIPR96 (INTC.ICDIPR96)
+#define INTCICDIPR97 (INTC.ICDIPR97)
+#define INTCICDIPR98 (INTC.ICDIPR98)
+#define INTCICDIPR99 (INTC.ICDIPR99)
+#define INTCICDIPR100 (INTC.ICDIPR100)
+#define INTCICDIPR101 (INTC.ICDIPR101)
+#define INTCICDIPR102 (INTC.ICDIPR102)
+#define INTCICDIPR103 (INTC.ICDIPR103)
+#define INTCICDIPR104 (INTC.ICDIPR104)
+#define INTCICDIPR105 (INTC.ICDIPR105)
+#define INTCICDIPR106 (INTC.ICDIPR106)
+#define INTCICDIPR107 (INTC.ICDIPR107)
+#define INTCICDIPR108 (INTC.ICDIPR108)
+#define INTCICDIPR109 (INTC.ICDIPR109)
+#define INTCICDIPR110 (INTC.ICDIPR110)
+#define INTCICDIPR111 (INTC.ICDIPR111)
+#define INTCICDIPR112 (INTC.ICDIPR112)
+#define INTCICDIPR113 (INTC.ICDIPR113)
+#define INTCICDIPR114 (INTC.ICDIPR114)
+#define INTCICDIPR115 (INTC.ICDIPR115)
+#define INTCICDIPR116 (INTC.ICDIPR116)
+#define INTCICDIPR117 (INTC.ICDIPR117)
+#define INTCICDIPR118 (INTC.ICDIPR118)
+#define INTCICDIPR119 (INTC.ICDIPR119)
+#define INTCICDIPR120 (INTC.ICDIPR120)
+#define INTCICDIPR121 (INTC.ICDIPR121)
+#define INTCICDIPR122 (INTC.ICDIPR122)
+#define INTCICDIPR123 (INTC.ICDIPR123)
+#define INTCICDIPR124 (INTC.ICDIPR124)
+#define INTCICDIPR125 (INTC.ICDIPR125)
+#define INTCICDIPR126 (INTC.ICDIPR126)
+#define INTCICDIPR127 (INTC.ICDIPR127)
+#define INTCICDIPR128 (INTC.ICDIPR128)
+#define INTCICDIPR129 (INTC.ICDIPR129)
+#define INTCICDIPR130 (INTC.ICDIPR130)
+#define INTCICDIPR131 (INTC.ICDIPR131)
+#define INTCICDIPR132 (INTC.ICDIPR132)
+#define INTCICDIPR133 (INTC.ICDIPR133)
+#define INTCICDIPR134 (INTC.ICDIPR134)
+#define INTCICDIPR135 (INTC.ICDIPR135)
+#define INTCICDIPR136 (INTC.ICDIPR136)
+#define INTCICDIPR137 (INTC.ICDIPR137)
+#define INTCICDIPR138 (INTC.ICDIPR138)
+#define INTCICDIPR139 (INTC.ICDIPR139)
+#define INTCICDIPR140 (INTC.ICDIPR140)
+#define INTCICDIPR141 (INTC.ICDIPR141)
+#define INTCICDIPR142 (INTC.ICDIPR142)
+#define INTCICDIPR143 (INTC.ICDIPR143)
+#define INTCICDIPR144 (INTC.ICDIPR144)
+#define INTCICDIPR145 (INTC.ICDIPR145)
+#define INTCICDIPR146 (INTC.ICDIPR146)
+#define INTCICDIPTR0 (INTC.ICDIPTR0)
+#define INTCICDIPTR1 (INTC.ICDIPTR1)
+#define INTCICDIPTR2 (INTC.ICDIPTR2)
+#define INTCICDIPTR3 (INTC.ICDIPTR3)
+#define INTCICDIPTR4 (INTC.ICDIPTR4)
+#define INTCICDIPTR5 (INTC.ICDIPTR5)
+#define INTCICDIPTR6 (INTC.ICDIPTR6)
+#define INTCICDIPTR7 (INTC.ICDIPTR7)
+#define INTCICDIPTR8 (INTC.ICDIPTR8)
+#define INTCICDIPTR9 (INTC.ICDIPTR9)
+#define INTCICDIPTR10 (INTC.ICDIPTR10)
+#define INTCICDIPTR11 (INTC.ICDIPTR11)
+#define INTCICDIPTR12 (INTC.ICDIPTR12)
+#define INTCICDIPTR13 (INTC.ICDIPTR13)
+#define INTCICDIPTR14 (INTC.ICDIPTR14)
+#define INTCICDIPTR15 (INTC.ICDIPTR15)
+#define INTCICDIPTR16 (INTC.ICDIPTR16)
+#define INTCICDIPTR17 (INTC.ICDIPTR17)
+#define INTCICDIPTR18 (INTC.ICDIPTR18)
+#define INTCICDIPTR19 (INTC.ICDIPTR19)
+#define INTCICDIPTR20 (INTC.ICDIPTR20)
+#define INTCICDIPTR21 (INTC.ICDIPTR21)
+#define INTCICDIPTR22 (INTC.ICDIPTR22)
+#define INTCICDIPTR23 (INTC.ICDIPTR23)
+#define INTCICDIPTR24 (INTC.ICDIPTR24)
+#define INTCICDIPTR25 (INTC.ICDIPTR25)
+#define INTCICDIPTR26 (INTC.ICDIPTR26)
+#define INTCICDIPTR27 (INTC.ICDIPTR27)
+#define INTCICDIPTR28 (INTC.ICDIPTR28)
+#define INTCICDIPTR29 (INTC.ICDIPTR29)
+#define INTCICDIPTR30 (INTC.ICDIPTR30)
+#define INTCICDIPTR31 (INTC.ICDIPTR31)
+#define INTCICDIPTR32 (INTC.ICDIPTR32)
+#define INTCICDIPTR33 (INTC.ICDIPTR33)
+#define INTCICDIPTR34 (INTC.ICDIPTR34)
+#define INTCICDIPTR35 (INTC.ICDIPTR35)
+#define INTCICDIPTR36 (INTC.ICDIPTR36)
+#define INTCICDIPTR37 (INTC.ICDIPTR37)
+#define INTCICDIPTR38 (INTC.ICDIPTR38)
+#define INTCICDIPTR39 (INTC.ICDIPTR39)
+#define INTCICDIPTR40 (INTC.ICDIPTR40)
+#define INTCICDIPTR41 (INTC.ICDIPTR41)
+#define INTCICDIPTR42 (INTC.ICDIPTR42)
+#define INTCICDIPTR43 (INTC.ICDIPTR43)
+#define INTCICDIPTR44 (INTC.ICDIPTR44)
+#define INTCICDIPTR45 (INTC.ICDIPTR45)
+#define INTCICDIPTR46 (INTC.ICDIPTR46)
+#define INTCICDIPTR47 (INTC.ICDIPTR47)
+#define INTCICDIPTR48 (INTC.ICDIPTR48)
+#define INTCICDIPTR49 (INTC.ICDIPTR49)
+#define INTCICDIPTR50 (INTC.ICDIPTR50)
+#define INTCICDIPTR51 (INTC.ICDIPTR51)
+#define INTCICDIPTR52 (INTC.ICDIPTR52)
+#define INTCICDIPTR53 (INTC.ICDIPTR53)
+#define INTCICDIPTR54 (INTC.ICDIPTR54)
+#define INTCICDIPTR55 (INTC.ICDIPTR55)
+#define INTCICDIPTR56 (INTC.ICDIPTR56)
+#define INTCICDIPTR57 (INTC.ICDIPTR57)
+#define INTCICDIPTR58 (INTC.ICDIPTR58)
+#define INTCICDIPTR59 (INTC.ICDIPTR59)
+#define INTCICDIPTR60 (INTC.ICDIPTR60)
+#define INTCICDIPTR61 (INTC.ICDIPTR61)
+#define INTCICDIPTR62 (INTC.ICDIPTR62)
+#define INTCICDIPTR63 (INTC.ICDIPTR63)
+#define INTCICDIPTR64 (INTC.ICDIPTR64)
+#define INTCICDIPTR65 (INTC.ICDIPTR65)
+#define INTCICDIPTR66 (INTC.ICDIPTR66)
+#define INTCICDIPTR67 (INTC.ICDIPTR67)
+#define INTCICDIPTR68 (INTC.ICDIPTR68)
+#define INTCICDIPTR69 (INTC.ICDIPTR69)
+#define INTCICDIPTR70 (INTC.ICDIPTR70)
+#define INTCICDIPTR71 (INTC.ICDIPTR71)
+#define INTCICDIPTR72 (INTC.ICDIPTR72)
+#define INTCICDIPTR73 (INTC.ICDIPTR73)
+#define INTCICDIPTR74 (INTC.ICDIPTR74)
+#define INTCICDIPTR75 (INTC.ICDIPTR75)
+#define INTCICDIPTR76 (INTC.ICDIPTR76)
+#define INTCICDIPTR77 (INTC.ICDIPTR77)
+#define INTCICDIPTR78 (INTC.ICDIPTR78)
+#define INTCICDIPTR79 (INTC.ICDIPTR79)
+#define INTCICDIPTR80 (INTC.ICDIPTR80)
+#define INTCICDIPTR81 (INTC.ICDIPTR81)
+#define INTCICDIPTR82 (INTC.ICDIPTR82)
+#define INTCICDIPTR83 (INTC.ICDIPTR83)
+#define INTCICDIPTR84 (INTC.ICDIPTR84)
+#define INTCICDIPTR85 (INTC.ICDIPTR85)
+#define INTCICDIPTR86 (INTC.ICDIPTR86)
+#define INTCICDIPTR87 (INTC.ICDIPTR87)
+#define INTCICDIPTR88 (INTC.ICDIPTR88)
+#define INTCICDIPTR89 (INTC.ICDIPTR89)
+#define INTCICDIPTR90 (INTC.ICDIPTR90)
+#define INTCICDIPTR91 (INTC.ICDIPTR91)
+#define INTCICDIPTR92 (INTC.ICDIPTR92)
+#define INTCICDIPTR93 (INTC.ICDIPTR93)
+#define INTCICDIPTR94 (INTC.ICDIPTR94)
+#define INTCICDIPTR95 (INTC.ICDIPTR95)
+#define INTCICDIPTR96 (INTC.ICDIPTR96)
+#define INTCICDIPTR97 (INTC.ICDIPTR97)
+#define INTCICDIPTR98 (INTC.ICDIPTR98)
+#define INTCICDIPTR99 (INTC.ICDIPTR99)
+#define INTCICDIPTR100 (INTC.ICDIPTR100)
+#define INTCICDIPTR101 (INTC.ICDIPTR101)
+#define INTCICDIPTR102 (INTC.ICDIPTR102)
+#define INTCICDIPTR103 (INTC.ICDIPTR103)
+#define INTCICDIPTR104 (INTC.ICDIPTR104)
+#define INTCICDIPTR105 (INTC.ICDIPTR105)
+#define INTCICDIPTR106 (INTC.ICDIPTR106)
+#define INTCICDIPTR107 (INTC.ICDIPTR107)
+#define INTCICDIPTR108 (INTC.ICDIPTR108)
+#define INTCICDIPTR109 (INTC.ICDIPTR109)
+#define INTCICDIPTR110 (INTC.ICDIPTR110)
+#define INTCICDIPTR111 (INTC.ICDIPTR111)
+#define INTCICDIPTR112 (INTC.ICDIPTR112)
+#define INTCICDIPTR113 (INTC.ICDIPTR113)
+#define INTCICDIPTR114 (INTC.ICDIPTR114)
+#define INTCICDIPTR115 (INTC.ICDIPTR115)
+#define INTCICDIPTR116 (INTC.ICDIPTR116)
+#define INTCICDIPTR117 (INTC.ICDIPTR117)
+#define INTCICDIPTR118 (INTC.ICDIPTR118)
+#define INTCICDIPTR119 (INTC.ICDIPTR119)
+#define INTCICDIPTR120 (INTC.ICDIPTR120)
+#define INTCICDIPTR121 (INTC.ICDIPTR121)
+#define INTCICDIPTR122 (INTC.ICDIPTR122)
+#define INTCICDIPTR123 (INTC.ICDIPTR123)
+#define INTCICDIPTR124 (INTC.ICDIPTR124)
+#define INTCICDIPTR125 (INTC.ICDIPTR125)
+#define INTCICDIPTR126 (INTC.ICDIPTR126)
+#define INTCICDIPTR127 (INTC.ICDIPTR127)
+#define INTCICDIPTR128 (INTC.ICDIPTR128)
+#define INTCICDIPTR129 (INTC.ICDIPTR129)
+#define INTCICDIPTR130 (INTC.ICDIPTR130)
+#define INTCICDIPTR131 (INTC.ICDIPTR131)
+#define INTCICDIPTR132 (INTC.ICDIPTR132)
+#define INTCICDIPTR133 (INTC.ICDIPTR133)
+#define INTCICDIPTR134 (INTC.ICDIPTR134)
+#define INTCICDIPTR135 (INTC.ICDIPTR135)
+#define INTCICDIPTR136 (INTC.ICDIPTR136)
+#define INTCICDIPTR137 (INTC.ICDIPTR137)
+#define INTCICDIPTR138 (INTC.ICDIPTR138)
+#define INTCICDIPTR139 (INTC.ICDIPTR139)
+#define INTCICDIPTR140 (INTC.ICDIPTR140)
+#define INTCICDIPTR141 (INTC.ICDIPTR141)
+#define INTCICDIPTR142 (INTC.ICDIPTR142)
+#define INTCICDIPTR143 (INTC.ICDIPTR143)
+#define INTCICDIPTR144 (INTC.ICDIPTR144)
+#define INTCICDIPTR145 (INTC.ICDIPTR145)
+#define INTCICDIPTR146 (INTC.ICDIPTR146)
+#define INTCICDICFR0 (INTC.ICDICFR0)
+#define INTCICDICFR1 (INTC.ICDICFR1)
+#define INTCICDICFR2 (INTC.ICDICFR2)
+#define INTCICDICFR3 (INTC.ICDICFR3)
+#define INTCICDICFR4 (INTC.ICDICFR4)
+#define INTCICDICFR5 (INTC.ICDICFR5)
+#define INTCICDICFR6 (INTC.ICDICFR6)
+#define INTCICDICFR7 (INTC.ICDICFR7)
+#define INTCICDICFR8 (INTC.ICDICFR8)
+#define INTCICDICFR9 (INTC.ICDICFR9)
+#define INTCICDICFR10 (INTC.ICDICFR10)
+#define INTCICDICFR11 (INTC.ICDICFR11)
+#define INTCICDICFR12 (INTC.ICDICFR12)
+#define INTCICDICFR13 (INTC.ICDICFR13)
+#define INTCICDICFR14 (INTC.ICDICFR14)
+#define INTCICDICFR15 (INTC.ICDICFR15)
+#define INTCICDICFR16 (INTC.ICDICFR16)
+#define INTCICDICFR17 (INTC.ICDICFR17)
+#define INTCICDICFR18 (INTC.ICDICFR18)
+#define INTCICDICFR19 (INTC.ICDICFR19)
+#define INTCICDICFR20 (INTC.ICDICFR20)
+#define INTCICDICFR21 (INTC.ICDICFR21)
+#define INTCICDICFR22 (INTC.ICDICFR22)
+#define INTCICDICFR23 (INTC.ICDICFR23)
+#define INTCICDICFR24 (INTC.ICDICFR24)
+#define INTCICDICFR25 (INTC.ICDICFR25)
+#define INTCICDICFR26 (INTC.ICDICFR26)
+#define INTCICDICFR27 (INTC.ICDICFR27)
+#define INTCICDICFR28 (INTC.ICDICFR28)
+#define INTCICDICFR29 (INTC.ICDICFR29)
+#define INTCICDICFR30 (INTC.ICDICFR30)
+#define INTCICDICFR31 (INTC.ICDICFR31)
+#define INTCICDICFR32 (INTC.ICDICFR32)
+#define INTCICDICFR33 (INTC.ICDICFR33)
+#define INTCICDICFR34 (INTC.ICDICFR34)
+#define INTCICDICFR35 (INTC.ICDICFR35)
+#define INTCICDICFR36 (INTC.ICDICFR36)
+#define INTCPPI_STATUS (INTC.PPI_STATUS)
+#define INTCSPI_STATUS0 (INTC.SPI_STATUS0)
+#define INTCSPI_STATUS1 (INTC.SPI_STATUS1)
+#define INTCSPI_STATUS2 (INTC.SPI_STATUS2)
+#define INTCSPI_STATUS3 (INTC.SPI_STATUS3)
+#define INTCSPI_STATUS4 (INTC.SPI_STATUS4)
+#define INTCSPI_STATUS5 (INTC.SPI_STATUS5)
+#define INTCSPI_STATUS6 (INTC.SPI_STATUS6)
+#define INTCSPI_STATUS7 (INTC.SPI_STATUS7)
+#define INTCSPI_STATUS8 (INTC.SPI_STATUS8)
+#define INTCSPI_STATUS9 (INTC.SPI_STATUS9)
+#define INTCSPI_STATUS10 (INTC.SPI_STATUS10)
+#define INTCSPI_STATUS11 (INTC.SPI_STATUS11)
+#define INTCSPI_STATUS12 (INTC.SPI_STATUS12)
+#define INTCSPI_STATUS13 (INTC.SPI_STATUS13)
+#define INTCSPI_STATUS14 (INTC.SPI_STATUS14)
+#define INTCSPI_STATUS15 (INTC.SPI_STATUS15)
+#define INTCSPI_STATUS16 (INTC.SPI_STATUS16)
+#define INTCICDSGIR (INTC.ICDSGIR)
+#define INTCICCICR (INTC.ICCICR)
+#define INTCICCPMR (INTC.ICCPMR)
+#define INTCICCBPR (INTC.ICCBPR)
+#define INTCICCIAR (INTC.ICCIAR)
+#define INTCICCEOIR (INTC.ICCEOIR)
+#define INTCICCRPR (INTC.ICCRPR)
+#define INTCICCHPIR (INTC.ICCHPIR)
+#define INTCICCABPR (INTC.ICCABPR)
+#define INTCICCIIDR (INTC.ICCIIDR)
+#define INTCICR0 (INTC.ICR0)
+#define INTCICR1 (INTC.ICR1)
+#define INTCIRQRR (INTC.IRQRR)
+
+#define INTC_ICDISR0_COUNT (19)
+#define INTC_ICDISER0_COUNT (19)
+#define INTC_ICDICER0_COUNT (19)
+#define INTC_ICDISPR0_COUNT (19)
+#define INTC_ICDICPR0_COUNT (19)
+#define INTC_ICDABR0_COUNT (19)
+#define INTC_ICDIPR0_COUNT (147)
+#define INTC_ICDIPTR0_COUNT (147)
+#define INTC_ICDICFR0_COUNT (37)
+#define INTC_SPI_STATUS0_COUNT (17)
+
+
+typedef struct st_intc
+{
+                                                           /* INTC             */
     volatile uint32_t  ICDDCR;                                 /*  ICDDCR          */
     volatile uint32_t  ICDICTR;                                /*  ICDICTR         */
     volatile uint32_t  ICDIIDR;                                /*  ICDIIDR         */
     volatile uint8_t   dummy193[116];                          /*                  */
-#define INTC_ICDISR0_COUNT 19
+
+/* #define INTC_ICDISR0_COUNT (19) */
     volatile uint32_t  ICDISR0;                                /*  ICDISR0         */
     volatile uint32_t  ICDISR1;                                /*  ICDISR1         */
     volatile uint32_t  ICDISR2;                                /*  ICDISR2         */
@@ -58,7 +557,8 @@
     volatile uint32_t  ICDISR17;                               /*  ICDISR17        */
     volatile uint32_t  ICDISR18;                               /*  ICDISR18        */
     volatile uint8_t   dummy194[52];                           /*                  */
-#define INTC_ICDISER0_COUNT 19
+
+/* #define INTC_ICDISER0_COUNT (19) */
     volatile uint32_t  ICDISER0;                               /*  ICDISER0        */
     volatile uint32_t  ICDISER1;                               /*  ICDISER1        */
     volatile uint32_t  ICDISER2;                               /*  ICDISER2        */
@@ -79,7 +579,8 @@
     volatile uint32_t  ICDISER17;                              /*  ICDISER17       */
     volatile uint32_t  ICDISER18;                              /*  ICDISER18       */
     volatile uint8_t   dummy195[52];                           /*                  */
-#define INTC_ICDICER0_COUNT 19
+
+/* #define INTC_ICDICER0_COUNT (19) */
     volatile uint32_t  ICDICER0;                               /*  ICDICER0        */
     volatile uint32_t  ICDICER1;                               /*  ICDICER1        */
     volatile uint32_t  ICDICER2;                               /*  ICDICER2        */
@@ -100,7 +601,8 @@
     volatile uint32_t  ICDICER17;                              /*  ICDICER17       */
     volatile uint32_t  ICDICER18;                              /*  ICDICER18       */
     volatile uint8_t   dummy196[52];                           /*                  */
-#define INTC_ICDISPR0_COUNT 19
+
+/* #define INTC_ICDISPR0_COUNT (19) */
     volatile uint32_t  ICDISPR0;                               /*  ICDISPR0        */
     volatile uint32_t  ICDISPR1;                               /*  ICDISPR1        */
     volatile uint32_t  ICDISPR2;                               /*  ICDISPR2        */
@@ -121,7 +623,8 @@
     volatile uint32_t  ICDISPR17;                              /*  ICDISPR17       */
     volatile uint32_t  ICDISPR18;                              /*  ICDISPR18       */
     volatile uint8_t   dummy197[52];                           /*                  */
-#define INTC_ICDICPR0_COUNT 19
+
+/* #define INTC_ICDICPR0_COUNT (19) */
     volatile uint32_t  ICDICPR0;                               /*  ICDICPR0        */
     volatile uint32_t  ICDICPR1;                               /*  ICDICPR1        */
     volatile uint32_t  ICDICPR2;                               /*  ICDICPR2        */
@@ -142,7 +645,8 @@
     volatile uint32_t  ICDICPR17;                              /*  ICDICPR17       */
     volatile uint32_t  ICDICPR18;                              /*  ICDICPR18       */
     volatile uint8_t   dummy198[52];                           /*                  */
-#define INTC_ICDABR0_COUNT 19
+
+/* #define INTC_ICDABR0_COUNT (19) */
     volatile uint32_t  ICDABR0;                                /*  ICDABR0         */
     volatile uint32_t  ICDABR1;                                /*  ICDABR1         */
     volatile uint32_t  ICDABR2;                                /*  ICDABR2         */
@@ -163,7 +667,8 @@
     volatile uint32_t  ICDABR17;                               /*  ICDABR17        */
     volatile uint32_t  ICDABR18;                               /*  ICDABR18        */
     volatile uint8_t   dummy199[180];                          /*                  */
-#define INTC_ICDIPR0_COUNT 147
+
+/* #define INTC_ICDIPR0_COUNT (147) */
     volatile uint32_t  ICDIPR0;                                /*  ICDIPR0         */
     volatile uint32_t  ICDIPR1;                                /*  ICDIPR1         */
     volatile uint32_t  ICDIPR2;                                /*  ICDIPR2         */
@@ -312,7 +817,8 @@
     volatile uint32_t  ICDIPR145;                              /*  ICDIPR145       */
     volatile uint32_t  ICDIPR146;                              /*  ICDIPR146       */
     volatile uint8_t   dummy200[436];                          /*                  */
-#define INTC_ICDIPTR0_COUNT 147
+
+/* #define INTC_ICDIPTR0_COUNT (147) */
     volatile uint32_t  ICDIPTR0;                               /*  ICDIPTR0        */
     volatile uint32_t  ICDIPTR1;                               /*  ICDIPTR1        */
     volatile uint32_t  ICDIPTR2;                               /*  ICDIPTR2        */
@@ -461,7 +967,8 @@
     volatile uint32_t  ICDIPTR145;                             /*  ICDIPTR145      */
     volatile uint32_t  ICDIPTR146;                             /*  ICDIPTR146      */
     volatile uint8_t   dummy201[436];                          /*                  */
-#define INTC_ICDICFR0_COUNT 37
+
+/* #define INTC_ICDICFR0_COUNT (37) */
     volatile uint32_t  ICDICFR0;                               /*  ICDICFR0        */
     volatile uint32_t  ICDICFR1;                               /*  ICDICFR1        */
     volatile uint32_t  ICDICFR2;                               /*  ICDICFR2        */
@@ -501,7 +1008,8 @@
     volatile uint32_t  ICDICFR36;                              /*  ICDICFR36       */
     volatile uint8_t   dummy202[108];                          /*                  */
     volatile uint32_t  PPI_STATUS;                             /*  PPI_STATUS      */
-#define INTC_SPI_STATUS0_COUNT 17
+
+/* #define INTC_SPI_STATUS0_COUNT (17) */
     volatile uint32_t  SPI_STATUS0;                            /*  SPI_STATUS0     */
     volatile uint32_t  SPI_STATUS1;                            /*  SPI_STATUS1     */
     volatile uint32_t  SPI_STATUS2;                            /*  SPI_STATUS2     */
@@ -536,491 +1044,11 @@
     volatile uint16_t ICR0;                                   /*  ICR0            */
     volatile uint16_t ICR1;                                   /*  ICR1            */
     volatile uint16_t IRQRR;                                  /*  IRQRR           */
-};
-
-
-#define INTC    (*(struct st_intc    *)0xE8201000uL) /* INTC */
+} r_io_intc_t;
 
 
-#define INTCICDDCR INTC.ICDDCR
-#define INTCICDICTR INTC.ICDICTR
-#define INTCICDIIDR INTC.ICDIIDR
-#define INTCICDISR0 INTC.ICDISR0
-#define INTCICDISR1 INTC.ICDISR1
-#define INTCICDISR2 INTC.ICDISR2
-#define INTCICDISR3 INTC.ICDISR3
-#define INTCICDISR4 INTC.ICDISR4
-#define INTCICDISR5 INTC.ICDISR5
-#define INTCICDISR6 INTC.ICDISR6
-#define INTCICDISR7 INTC.ICDISR7
-#define INTCICDISR8 INTC.ICDISR8
-#define INTCICDISR9 INTC.ICDISR9
-#define INTCICDISR10 INTC.ICDISR10
-#define INTCICDISR11 INTC.ICDISR11
-#define INTCICDISR12 INTC.ICDISR12
-#define INTCICDISR13 INTC.ICDISR13
-#define INTCICDISR14 INTC.ICDISR14
-#define INTCICDISR15 INTC.ICDISR15
-#define INTCICDISR16 INTC.ICDISR16
-#define INTCICDISR17 INTC.ICDISR17
-#define INTCICDISR18 INTC.ICDISR18
-#define INTCICDISER0 INTC.ICDISER0
-#define INTCICDISER1 INTC.ICDISER1
-#define INTCICDISER2 INTC.ICDISER2
-#define INTCICDISER3 INTC.ICDISER3
-#define INTCICDISER4 INTC.ICDISER4
-#define INTCICDISER5 INTC.ICDISER5
-#define INTCICDISER6 INTC.ICDISER6
-#define INTCICDISER7 INTC.ICDISER7
-#define INTCICDISER8 INTC.ICDISER8
-#define INTCICDISER9 INTC.ICDISER9
-#define INTCICDISER10 INTC.ICDISER10
-#define INTCICDISER11 INTC.ICDISER11
-#define INTCICDISER12 INTC.ICDISER12
-#define INTCICDISER13 INTC.ICDISER13
-#define INTCICDISER14 INTC.ICDISER14
-#define INTCICDISER15 INTC.ICDISER15
-#define INTCICDISER16 INTC.ICDISER16
-#define INTCICDISER17 INTC.ICDISER17
-#define INTCICDISER18 INTC.ICDISER18
-#define INTCICDICER0 INTC.ICDICER0
-#define INTCICDICER1 INTC.ICDICER1
-#define INTCICDICER2 INTC.ICDICER2
-#define INTCICDICER3 INTC.ICDICER3
-#define INTCICDICER4 INTC.ICDICER4
-#define INTCICDICER5 INTC.ICDICER5
-#define INTCICDICER6 INTC.ICDICER6
-#define INTCICDICER7 INTC.ICDICER7
-#define INTCICDICER8 INTC.ICDICER8
-#define INTCICDICER9 INTC.ICDICER9
-#define INTCICDICER10 INTC.ICDICER10
-#define INTCICDICER11 INTC.ICDICER11
-#define INTCICDICER12 INTC.ICDICER12
-#define INTCICDICER13 INTC.ICDICER13
-#define INTCICDICER14 INTC.ICDICER14
-#define INTCICDICER15 INTC.ICDICER15
-#define INTCICDICER16 INTC.ICDICER16
-#define INTCICDICER17 INTC.ICDICER17
-#define INTCICDICER18 INTC.ICDICER18
-#define INTCICDISPR0 INTC.ICDISPR0
-#define INTCICDISPR1 INTC.ICDISPR1
-#define INTCICDISPR2 INTC.ICDISPR2
-#define INTCICDISPR3 INTC.ICDISPR3
-#define INTCICDISPR4 INTC.ICDISPR4
-#define INTCICDISPR5 INTC.ICDISPR5
-#define INTCICDISPR6 INTC.ICDISPR6
-#define INTCICDISPR7 INTC.ICDISPR7
-#define INTCICDISPR8 INTC.ICDISPR8
-#define INTCICDISPR9 INTC.ICDISPR9
-#define INTCICDISPR10 INTC.ICDISPR10
-#define INTCICDISPR11 INTC.ICDISPR11
-#define INTCICDISPR12 INTC.ICDISPR12
-#define INTCICDISPR13 INTC.ICDISPR13
-#define INTCICDISPR14 INTC.ICDISPR14
-#define INTCICDISPR15 INTC.ICDISPR15
-#define INTCICDISPR16 INTC.ICDISPR16
-#define INTCICDISPR17 INTC.ICDISPR17
-#define INTCICDISPR18 INTC.ICDISPR18
-#define INTCICDICPR0 INTC.ICDICPR0
-#define INTCICDICPR1 INTC.ICDICPR1
-#define INTCICDICPR2 INTC.ICDICPR2
-#define INTCICDICPR3 INTC.ICDICPR3
-#define INTCICDICPR4 INTC.ICDICPR4
-#define INTCICDICPR5 INTC.ICDICPR5
-#define INTCICDICPR6 INTC.ICDICPR6
-#define INTCICDICPR7 INTC.ICDICPR7
-#define INTCICDICPR8 INTC.ICDICPR8
-#define INTCICDICPR9 INTC.ICDICPR9
-#define INTCICDICPR10 INTC.ICDICPR10
-#define INTCICDICPR11 INTC.ICDICPR11
-#define INTCICDICPR12 INTC.ICDICPR12
-#define INTCICDICPR13 INTC.ICDICPR13
-#define INTCICDICPR14 INTC.ICDICPR14
-#define INTCICDICPR15 INTC.ICDICPR15
-#define INTCICDICPR16 INTC.ICDICPR16
-#define INTCICDICPR17 INTC.ICDICPR17
-#define INTCICDICPR18 INTC.ICDICPR18
-#define INTCICDABR0 INTC.ICDABR0
-#define INTCICDABR1 INTC.ICDABR1
-#define INTCICDABR2 INTC.ICDABR2
-#define INTCICDABR3 INTC.ICDABR3
-#define INTCICDABR4 INTC.ICDABR4
-#define INTCICDABR5 INTC.ICDABR5
-#define INTCICDABR6 INTC.ICDABR6
-#define INTCICDABR7 INTC.ICDABR7
-#define INTCICDABR8 INTC.ICDABR8
-#define INTCICDABR9 INTC.ICDABR9
-#define INTCICDABR10 INTC.ICDABR10
-#define INTCICDABR11 INTC.ICDABR11
-#define INTCICDABR12 INTC.ICDABR12
-#define INTCICDABR13 INTC.ICDABR13
-#define INTCICDABR14 INTC.ICDABR14
-#define INTCICDABR15 INTC.ICDABR15
-#define INTCICDABR16 INTC.ICDABR16
-#define INTCICDABR17 INTC.ICDABR17
-#define INTCICDABR18 INTC.ICDABR18
-#define INTCICDIPR0 INTC.ICDIPR0
-#define INTCICDIPR1 INTC.ICDIPR1
-#define INTCICDIPR2 INTC.ICDIPR2
-#define INTCICDIPR3 INTC.ICDIPR3
-#define INTCICDIPR4 INTC.ICDIPR4
-#define INTCICDIPR5 INTC.ICDIPR5
-#define INTCICDIPR6 INTC.ICDIPR6
-#define INTCICDIPR7 INTC.ICDIPR7
-#define INTCICDIPR8 INTC.ICDIPR8
-#define INTCICDIPR9 INTC.ICDIPR9
-#define INTCICDIPR10 INTC.ICDIPR10
-#define INTCICDIPR11 INTC.ICDIPR11
-#define INTCICDIPR12 INTC.ICDIPR12
-#define INTCICDIPR13 INTC.ICDIPR13
-#define INTCICDIPR14 INTC.ICDIPR14
-#define INTCICDIPR15 INTC.ICDIPR15
-#define INTCICDIPR16 INTC.ICDIPR16
-#define INTCICDIPR17 INTC.ICDIPR17
-#define INTCICDIPR18 INTC.ICDIPR18
-#define INTCICDIPR19 INTC.ICDIPR19
-#define INTCICDIPR20 INTC.ICDIPR20
-#define INTCICDIPR21 INTC.ICDIPR21
-#define INTCICDIPR22 INTC.ICDIPR22
-#define INTCICDIPR23 INTC.ICDIPR23
-#define INTCICDIPR24 INTC.ICDIPR24
-#define INTCICDIPR25 INTC.ICDIPR25
-#define INTCICDIPR26 INTC.ICDIPR26
-#define INTCICDIPR27 INTC.ICDIPR27
-#define INTCICDIPR28 INTC.ICDIPR28
-#define INTCICDIPR29 INTC.ICDIPR29
-#define INTCICDIPR30 INTC.ICDIPR30
-#define INTCICDIPR31 INTC.ICDIPR31
-#define INTCICDIPR32 INTC.ICDIPR32
-#define INTCICDIPR33 INTC.ICDIPR33
-#define INTCICDIPR34 INTC.ICDIPR34
-#define INTCICDIPR35 INTC.ICDIPR35
-#define INTCICDIPR36 INTC.ICDIPR36
-#define INTCICDIPR37 INTC.ICDIPR37
-#define INTCICDIPR38 INTC.ICDIPR38
-#define INTCICDIPR39 INTC.ICDIPR39
-#define INTCICDIPR40 INTC.ICDIPR40
-#define INTCICDIPR41 INTC.ICDIPR41
-#define INTCICDIPR42 INTC.ICDIPR42
-#define INTCICDIPR43 INTC.ICDIPR43
-#define INTCICDIPR44 INTC.ICDIPR44
-#define INTCICDIPR45 INTC.ICDIPR45
-#define INTCICDIPR46 INTC.ICDIPR46
-#define INTCICDIPR47 INTC.ICDIPR47
-#define INTCICDIPR48 INTC.ICDIPR48
-#define INTCICDIPR49 INTC.ICDIPR49
-#define INTCICDIPR50 INTC.ICDIPR50
-#define INTCICDIPR51 INTC.ICDIPR51
-#define INTCICDIPR52 INTC.ICDIPR52
-#define INTCICDIPR53 INTC.ICDIPR53
-#define INTCICDIPR54 INTC.ICDIPR54
-#define INTCICDIPR55 INTC.ICDIPR55
-#define INTCICDIPR56 INTC.ICDIPR56
-#define INTCICDIPR57 INTC.ICDIPR57
-#define INTCICDIPR58 INTC.ICDIPR58
-#define INTCICDIPR59 INTC.ICDIPR59
-#define INTCICDIPR60 INTC.ICDIPR60
-#define INTCICDIPR61 INTC.ICDIPR61
-#define INTCICDIPR62 INTC.ICDIPR62
-#define INTCICDIPR63 INTC.ICDIPR63
-#define INTCICDIPR64 INTC.ICDIPR64
-#define INTCICDIPR65 INTC.ICDIPR65
-#define INTCICDIPR66 INTC.ICDIPR66
-#define INTCICDIPR67 INTC.ICDIPR67
-#define INTCICDIPR68 INTC.ICDIPR68
-#define INTCICDIPR69 INTC.ICDIPR69
-#define INTCICDIPR70 INTC.ICDIPR70
-#define INTCICDIPR71 INTC.ICDIPR71
-#define INTCICDIPR72 INTC.ICDIPR72
-#define INTCICDIPR73 INTC.ICDIPR73
-#define INTCICDIPR74 INTC.ICDIPR74
-#define INTCICDIPR75 INTC.ICDIPR75
-#define INTCICDIPR76 INTC.ICDIPR76
-#define INTCICDIPR77 INTC.ICDIPR77
-#define INTCICDIPR78 INTC.ICDIPR78
-#define INTCICDIPR79 INTC.ICDIPR79
-#define INTCICDIPR80 INTC.ICDIPR80
-#define INTCICDIPR81 INTC.ICDIPR81
-#define INTCICDIPR82 INTC.ICDIPR82
-#define INTCICDIPR83 INTC.ICDIPR83
-#define INTCICDIPR84 INTC.ICDIPR84
-#define INTCICDIPR85 INTC.ICDIPR85
-#define INTCICDIPR86 INTC.ICDIPR86
-#define INTCICDIPR87 INTC.ICDIPR87
-#define INTCICDIPR88 INTC.ICDIPR88
-#define INTCICDIPR89 INTC.ICDIPR89
-#define INTCICDIPR90 INTC.ICDIPR90
-#define INTCICDIPR91 INTC.ICDIPR91
-#define INTCICDIPR92 INTC.ICDIPR92
-#define INTCICDIPR93 INTC.ICDIPR93
-#define INTCICDIPR94 INTC.ICDIPR94
-#define INTCICDIPR95 INTC.ICDIPR95
-#define INTCICDIPR96 INTC.ICDIPR96
-#define INTCICDIPR97 INTC.ICDIPR97
-#define INTCICDIPR98 INTC.ICDIPR98
-#define INTCICDIPR99 INTC.ICDIPR99
-#define INTCICDIPR100 INTC.ICDIPR100
-#define INTCICDIPR101 INTC.ICDIPR101
-#define INTCICDIPR102 INTC.ICDIPR102
-#define INTCICDIPR103 INTC.ICDIPR103
-#define INTCICDIPR104 INTC.ICDIPR104
-#define INTCICDIPR105 INTC.ICDIPR105
-#define INTCICDIPR106 INTC.ICDIPR106
-#define INTCICDIPR107 INTC.ICDIPR107
-#define INTCICDIPR108 INTC.ICDIPR108
-#define INTCICDIPR109 INTC.ICDIPR109
-#define INTCICDIPR110 INTC.ICDIPR110
-#define INTCICDIPR111 INTC.ICDIPR111
-#define INTCICDIPR112 INTC.ICDIPR112
-#define INTCICDIPR113 INTC.ICDIPR113
-#define INTCICDIPR114 INTC.ICDIPR114
-#define INTCICDIPR115 INTC.ICDIPR115
-#define INTCICDIPR116 INTC.ICDIPR116
-#define INTCICDIPR117 INTC.ICDIPR117
-#define INTCICDIPR118 INTC.ICDIPR118
-#define INTCICDIPR119 INTC.ICDIPR119
-#define INTCICDIPR120 INTC.ICDIPR120
-#define INTCICDIPR121 INTC.ICDIPR121
-#define INTCICDIPR122 INTC.ICDIPR122
-#define INTCICDIPR123 INTC.ICDIPR123
-#define INTCICDIPR124 INTC.ICDIPR124
-#define INTCICDIPR125 INTC.ICDIPR125
-#define INTCICDIPR126 INTC.ICDIPR126
-#define INTCICDIPR127 INTC.ICDIPR127
-#define INTCICDIPR128 INTC.ICDIPR128
-#define INTCICDIPR129 INTC.ICDIPR129
-#define INTCICDIPR130 INTC.ICDIPR130
-#define INTCICDIPR131 INTC.ICDIPR131
-#define INTCICDIPR132 INTC.ICDIPR132
-#define INTCICDIPR133 INTC.ICDIPR133
-#define INTCICDIPR134 INTC.ICDIPR134
-#define INTCICDIPR135 INTC.ICDIPR135
-#define INTCICDIPR136 INTC.ICDIPR136
-#define INTCICDIPR137 INTC.ICDIPR137
-#define INTCICDIPR138 INTC.ICDIPR138
-#define INTCICDIPR139 INTC.ICDIPR139
-#define INTCICDIPR140 INTC.ICDIPR140
-#define INTCICDIPR141 INTC.ICDIPR141
-#define INTCICDIPR142 INTC.ICDIPR142
-#define INTCICDIPR143 INTC.ICDIPR143
-#define INTCICDIPR144 INTC.ICDIPR144
-#define INTCICDIPR145 INTC.ICDIPR145
-#define INTCICDIPR146 INTC.ICDIPR146
-#define INTCICDIPTR0 INTC.ICDIPTR0
-#define INTCICDIPTR1 INTC.ICDIPTR1
-#define INTCICDIPTR2 INTC.ICDIPTR2
-#define INTCICDIPTR3 INTC.ICDIPTR3
-#define INTCICDIPTR4 INTC.ICDIPTR4
-#define INTCICDIPTR5 INTC.ICDIPTR5
-#define INTCICDIPTR6 INTC.ICDIPTR6
-#define INTCICDIPTR7 INTC.ICDIPTR7
-#define INTCICDIPTR8 INTC.ICDIPTR8
-#define INTCICDIPTR9 INTC.ICDIPTR9
-#define INTCICDIPTR10 INTC.ICDIPTR10
-#define INTCICDIPTR11 INTC.ICDIPTR11
-#define INTCICDIPTR12 INTC.ICDIPTR12
-#define INTCICDIPTR13 INTC.ICDIPTR13
-#define INTCICDIPTR14 INTC.ICDIPTR14
-#define INTCICDIPTR15 INTC.ICDIPTR15
-#define INTCICDIPTR16 INTC.ICDIPTR16
-#define INTCICDIPTR17 INTC.ICDIPTR17
-#define INTCICDIPTR18 INTC.ICDIPTR18
-#define INTCICDIPTR19 INTC.ICDIPTR19
-#define INTCICDIPTR20 INTC.ICDIPTR20
-#define INTCICDIPTR21 INTC.ICDIPTR21
-#define INTCICDIPTR22 INTC.ICDIPTR22
-#define INTCICDIPTR23 INTC.ICDIPTR23
-#define INTCICDIPTR24 INTC.ICDIPTR24
-#define INTCICDIPTR25 INTC.ICDIPTR25
-#define INTCICDIPTR26 INTC.ICDIPTR26
-#define INTCICDIPTR27 INTC.ICDIPTR27
-#define INTCICDIPTR28 INTC.ICDIPTR28
-#define INTCICDIPTR29 INTC.ICDIPTR29
-#define INTCICDIPTR30 INTC.ICDIPTR30
-#define INTCICDIPTR31 INTC.ICDIPTR31
-#define INTCICDIPTR32 INTC.ICDIPTR32
-#define INTCICDIPTR33 INTC.ICDIPTR33
-#define INTCICDIPTR34 INTC.ICDIPTR34
-#define INTCICDIPTR35 INTC.ICDIPTR35
-#define INTCICDIPTR36 INTC.ICDIPTR36
-#define INTCICDIPTR37 INTC.ICDIPTR37
-#define INTCICDIPTR38 INTC.ICDIPTR38
-#define INTCICDIPTR39 INTC.ICDIPTR39
-#define INTCICDIPTR40 INTC.ICDIPTR40
-#define INTCICDIPTR41 INTC.ICDIPTR41
-#define INTCICDIPTR42 INTC.ICDIPTR42
-#define INTCICDIPTR43 INTC.ICDIPTR43
-#define INTCICDIPTR44 INTC.ICDIPTR44
-#define INTCICDIPTR45 INTC.ICDIPTR45
-#define INTCICDIPTR46 INTC.ICDIPTR46
-#define INTCICDIPTR47 INTC.ICDIPTR47
-#define INTCICDIPTR48 INTC.ICDIPTR48
-#define INTCICDIPTR49 INTC.ICDIPTR49
-#define INTCICDIPTR50 INTC.ICDIPTR50
-#define INTCICDIPTR51 INTC.ICDIPTR51
-#define INTCICDIPTR52 INTC.ICDIPTR52
-#define INTCICDIPTR53 INTC.ICDIPTR53
-#define INTCICDIPTR54 INTC.ICDIPTR54
-#define INTCICDIPTR55 INTC.ICDIPTR55
-#define INTCICDIPTR56 INTC.ICDIPTR56
-#define INTCICDIPTR57 INTC.ICDIPTR57
-#define INTCICDIPTR58 INTC.ICDIPTR58
-#define INTCICDIPTR59 INTC.ICDIPTR59
-#define INTCICDIPTR60 INTC.ICDIPTR60
-#define INTCICDIPTR61 INTC.ICDIPTR61
-#define INTCICDIPTR62 INTC.ICDIPTR62
-#define INTCICDIPTR63 INTC.ICDIPTR63
-#define INTCICDIPTR64 INTC.ICDIPTR64
-#define INTCICDIPTR65 INTC.ICDIPTR65
-#define INTCICDIPTR66 INTC.ICDIPTR66
-#define INTCICDIPTR67 INTC.ICDIPTR67
-#define INTCICDIPTR68 INTC.ICDIPTR68
-#define INTCICDIPTR69 INTC.ICDIPTR69
-#define INTCICDIPTR70 INTC.ICDIPTR70
-#define INTCICDIPTR71 INTC.ICDIPTR71
-#define INTCICDIPTR72 INTC.ICDIPTR72
-#define INTCICDIPTR73 INTC.ICDIPTR73
-#define INTCICDIPTR74 INTC.ICDIPTR74
-#define INTCICDIPTR75 INTC.ICDIPTR75
-#define INTCICDIPTR76 INTC.ICDIPTR76
-#define INTCICDIPTR77 INTC.ICDIPTR77
-#define INTCICDIPTR78 INTC.ICDIPTR78
-#define INTCICDIPTR79 INTC.ICDIPTR79
-#define INTCICDIPTR80 INTC.ICDIPTR80
-#define INTCICDIPTR81 INTC.ICDIPTR81
-#define INTCICDIPTR82 INTC.ICDIPTR82
-#define INTCICDIPTR83 INTC.ICDIPTR83
-#define INTCICDIPTR84 INTC.ICDIPTR84
-#define INTCICDIPTR85 INTC.ICDIPTR85
-#define INTCICDIPTR86 INTC.ICDIPTR86
-#define INTCICDIPTR87 INTC.ICDIPTR87
-#define INTCICDIPTR88 INTC.ICDIPTR88
-#define INTCICDIPTR89 INTC.ICDIPTR89
-#define INTCICDIPTR90 INTC.ICDIPTR90
-#define INTCICDIPTR91 INTC.ICDIPTR91
-#define INTCICDIPTR92 INTC.ICDIPTR92
-#define INTCICDIPTR93 INTC.ICDIPTR93
-#define INTCICDIPTR94 INTC.ICDIPTR94
-#define INTCICDIPTR95 INTC.ICDIPTR95
-#define INTCICDIPTR96 INTC.ICDIPTR96
-#define INTCICDIPTR97 INTC.ICDIPTR97
-#define INTCICDIPTR98 INTC.ICDIPTR98
-#define INTCICDIPTR99 INTC.ICDIPTR99
-#define INTCICDIPTR100 INTC.ICDIPTR100
-#define INTCICDIPTR101 INTC.ICDIPTR101
-#define INTCICDIPTR102 INTC.ICDIPTR102
-#define INTCICDIPTR103 INTC.ICDIPTR103
-#define INTCICDIPTR104 INTC.ICDIPTR104
-#define INTCICDIPTR105 INTC.ICDIPTR105
-#define INTCICDIPTR106 INTC.ICDIPTR106
-#define INTCICDIPTR107 INTC.ICDIPTR107
-#define INTCICDIPTR108 INTC.ICDIPTR108
-#define INTCICDIPTR109 INTC.ICDIPTR109
-#define INTCICDIPTR110 INTC.ICDIPTR110
-#define INTCICDIPTR111 INTC.ICDIPTR111
-#define INTCICDIPTR112 INTC.ICDIPTR112
-#define INTCICDIPTR113 INTC.ICDIPTR113
-#define INTCICDIPTR114 INTC.ICDIPTR114
-#define INTCICDIPTR115 INTC.ICDIPTR115
-#define INTCICDIPTR116 INTC.ICDIPTR116
-#define INTCICDIPTR117 INTC.ICDIPTR117
-#define INTCICDIPTR118 INTC.ICDIPTR118
-#define INTCICDIPTR119 INTC.ICDIPTR119
-#define INTCICDIPTR120 INTC.ICDIPTR120
-#define INTCICDIPTR121 INTC.ICDIPTR121
-#define INTCICDIPTR122 INTC.ICDIPTR122
-#define INTCICDIPTR123 INTC.ICDIPTR123
-#define INTCICDIPTR124 INTC.ICDIPTR124
-#define INTCICDIPTR125 INTC.ICDIPTR125
-#define INTCICDIPTR126 INTC.ICDIPTR126
-#define INTCICDIPTR127 INTC.ICDIPTR127
-#define INTCICDIPTR128 INTC.ICDIPTR128
-#define INTCICDIPTR129 INTC.ICDIPTR129
-#define INTCICDIPTR130 INTC.ICDIPTR130
-#define INTCICDIPTR131 INTC.ICDIPTR131
-#define INTCICDIPTR132 INTC.ICDIPTR132
-#define INTCICDIPTR133 INTC.ICDIPTR133
-#define INTCICDIPTR134 INTC.ICDIPTR134
-#define INTCICDIPTR135 INTC.ICDIPTR135
-#define INTCICDIPTR136 INTC.ICDIPTR136
-#define INTCICDIPTR137 INTC.ICDIPTR137
-#define INTCICDIPTR138 INTC.ICDIPTR138
-#define INTCICDIPTR139 INTC.ICDIPTR139
-#define INTCICDIPTR140 INTC.ICDIPTR140
-#define INTCICDIPTR141 INTC.ICDIPTR141
-#define INTCICDIPTR142 INTC.ICDIPTR142
-#define INTCICDIPTR143 INTC.ICDIPTR143
-#define INTCICDIPTR144 INTC.ICDIPTR144
-#define INTCICDIPTR145 INTC.ICDIPTR145
-#define INTCICDIPTR146 INTC.ICDIPTR146
-#define INTCICDICFR0 INTC.ICDICFR0
-#define INTCICDICFR1 INTC.ICDICFR1
-#define INTCICDICFR2 INTC.ICDICFR2
-#define INTCICDICFR3 INTC.ICDICFR3
-#define INTCICDICFR4 INTC.ICDICFR4
-#define INTCICDICFR5 INTC.ICDICFR5
-#define INTCICDICFR6 INTC.ICDICFR6
-#define INTCICDICFR7 INTC.ICDICFR7
-#define INTCICDICFR8 INTC.ICDICFR8
-#define INTCICDICFR9 INTC.ICDICFR9
-#define INTCICDICFR10 INTC.ICDICFR10
-#define INTCICDICFR11 INTC.ICDICFR11
-#define INTCICDICFR12 INTC.ICDICFR12
-#define INTCICDICFR13 INTC.ICDICFR13
-#define INTCICDICFR14 INTC.ICDICFR14
-#define INTCICDICFR15 INTC.ICDICFR15
-#define INTCICDICFR16 INTC.ICDICFR16
-#define INTCICDICFR17 INTC.ICDICFR17
-#define INTCICDICFR18 INTC.ICDICFR18
-#define INTCICDICFR19 INTC.ICDICFR19
-#define INTCICDICFR20 INTC.ICDICFR20
-#define INTCICDICFR21 INTC.ICDICFR21
-#define INTCICDICFR22 INTC.ICDICFR22
-#define INTCICDICFR23 INTC.ICDICFR23
-#define INTCICDICFR24 INTC.ICDICFR24
-#define INTCICDICFR25 INTC.ICDICFR25
-#define INTCICDICFR26 INTC.ICDICFR26
-#define INTCICDICFR27 INTC.ICDICFR27
-#define INTCICDICFR28 INTC.ICDICFR28
-#define INTCICDICFR29 INTC.ICDICFR29
-#define INTCICDICFR30 INTC.ICDICFR30
-#define INTCICDICFR31 INTC.ICDICFR31
-#define INTCICDICFR32 INTC.ICDICFR32
-#define INTCICDICFR33 INTC.ICDICFR33
-#define INTCICDICFR34 INTC.ICDICFR34
-#define INTCICDICFR35 INTC.ICDICFR35
-#define INTCICDICFR36 INTC.ICDICFR36
-#define INTCPPI_STATUS INTC.PPI_STATUS
-#define INTCSPI_STATUS0 INTC.SPI_STATUS0
-#define INTCSPI_STATUS1 INTC.SPI_STATUS1
-#define INTCSPI_STATUS2 INTC.SPI_STATUS2
-#define INTCSPI_STATUS3 INTC.SPI_STATUS3
-#define INTCSPI_STATUS4 INTC.SPI_STATUS4
-#define INTCSPI_STATUS5 INTC.SPI_STATUS5
-#define INTCSPI_STATUS6 INTC.SPI_STATUS6
-#define INTCSPI_STATUS7 INTC.SPI_STATUS7
-#define INTCSPI_STATUS8 INTC.SPI_STATUS8
-#define INTCSPI_STATUS9 INTC.SPI_STATUS9
-#define INTCSPI_STATUS10 INTC.SPI_STATUS10
-#define INTCSPI_STATUS11 INTC.SPI_STATUS11
-#define INTCSPI_STATUS12 INTC.SPI_STATUS12
-#define INTCSPI_STATUS13 INTC.SPI_STATUS13
-#define INTCSPI_STATUS14 INTC.SPI_STATUS14
-#define INTCSPI_STATUS15 INTC.SPI_STATUS15
-#define INTCSPI_STATUS16 INTC.SPI_STATUS16
-#define INTCICDSGIR INTC.ICDSGIR
-#define INTCICCICR INTC.ICCICR
-#define INTCICCPMR INTC.ICCPMR
-#define INTCICCBPR INTC.ICCBPR
-#define INTCICCIAR INTC.ICCIAR
-#define INTCICCEOIR INTC.ICCEOIR
-#define INTCICCRPR INTC.ICCRPR
-#define INTCICCHPIR INTC.ICCHPIR
-#define INTCICCABPR INTC.ICCABPR
-#define INTCICCIIDR INTC.ICCIIDR
-#define INTCICR0 INTC.ICR0
-#define INTCICR1 INTC.ICR1
-#define INTCIRQRR INTC.IRQRR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,116 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : iodefine_typedef.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef IODEFINE_TYPEDEF_H
+#define IODEFINE_TYPEDEF_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+/* Shared types and macros for iodefine.h */
+
+/***********************************************************************
+* Macro: IODEFINE_H_VERSION
+************************************************************************/
+#define IODEFINE_H_VERSION  (200)
+
+
+/***********************************************************************
+* Enum: iodefine_byte_select_t
+*
+*   R_IO_L - Low 16bit or Low 8 bit
+*   R_IO_H - High 16bit or Low 8 bit
+*   R_IO_LL - Low 8 bit
+*   R_IO_LH - Middle Low 8 bit
+*   R_IO_HL - Middle High 8 bit
+*   R_IO_HH - High 8 bit
+************************************************************************/
+typedef enum iodefine_byte_select_t
+{
+    R_IO_L = 0, R_IO_H = 1,
+    R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3
+} iodefine_byte_select_t;
+
+
+/***********************************************************************
+* Type: iodefine_reg32_t
+*   32/16/8 bit access register
+*
+* - Padding : sizeof(iodefine_reg32_t) == 4
+* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+*                       &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
+* - Endian : Independent (Same as CPU endian as register endian)
+* - Bit-Order : Independent
+************************************************************************/
+typedef union iodefine_reg32_t
+{
+    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
+    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
+    volatile uint8_t   UINT8[4];                                /*  8-bit Access    */
+} iodefine_reg32_t;
+
+
+/***********************************************************************
+* Type: iodefine_reg32_16_t
+*   32/16 bit access register
+* 
+* - Padding : sizeof(iodefine_reg32_16_t) == 4
+* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+* - Endian : Independent (Same as CPU endian as register endian)
+* - Bit-Order : Independent
+************************************************************************/
+typedef union iodefine_reg32_16_t
+{
+    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
+    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
+} iodefine_reg32_16_t;
+
+
+/***********************************************************************
+* Type: iodefine_reg16_8_t
+*   16/8 bit access register
+* 
+* - Padding : sizeof(iodefine_reg16_8_t) == 2
+* - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
+* - Endian : Independent (Same as CPU endian as register endian)
+* - Bit-Order : Independent
+************************************************************************/
+typedef union iodefine_reg16_8_t
+{
+    volatile uint16_t  UINT16;                                  /*  16-bit Access   */
+    volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
+} iodefine_reg16_8_t;
+
+
+/* End of shared types and macros for iodefine.h */
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,25 +18,36 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : irda_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef IRDA_IODEFINE_H
 #define IRDA_IODEFINE_H
-
-struct st_irda
-{                                                          /* IRDA             */
-    volatile uint8_t   IRCR;                                   /*  IRCR            */
-};
-
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
 #define IRDA    (*(struct st_irda    *)0xE8014000uL) /* IRDA */
 
 
-#define IRDAIRCR IRDA.IRCR
+#define IRDAIRCR (IRDA.IRCR)
+
+
+typedef struct st_irda
+{
+                                                           /* IRDA             */
+    volatile uint8_t   IRCR;                                   /*  IRCR            */
+} r_io_irda_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,88 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : jcu_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef JCU_IODEFINE_H
 #define JCU_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_jcu
-{                                                          /* JCU              */
+#define JCU     (*(struct st_jcu     *)0xE8017000uL) /* JCU */
+
+
+/* Start of channel array defines of JCU */
+
+/* Channel array defines of JCU_JCQTBL0 */
+/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
+#define JCU_JCQTBL0_COUNT  (4)
+#define JCU_JCQTBL0_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
+#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
+#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
+#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
+
+/* End of channel array defines of JCU */
+
+
+#define JCUJCMOD (JCU.JCMOD)
+#define JCUJCCMD (JCU.JCCMD)
+#define JCUJCQTN (JCU.JCQTN)
+#define JCUJCHTN (JCU.JCHTN)
+#define JCUJCDRIU (JCU.JCDRIU)
+#define JCUJCDRID (JCU.JCDRID)
+#define JCUJCVSZU (JCU.JCVSZU)
+#define JCUJCVSZD (JCU.JCVSZD)
+#define JCUJCHSZU (JCU.JCHSZU)
+#define JCUJCHSZD (JCU.JCHSZD)
+#define JCUJCDTCU (JCU.JCDTCU)
+#define JCUJCDTCM (JCU.JCDTCM)
+#define JCUJCDTCD (JCU.JCDTCD)
+#define JCUJINTE0 (JCU.JINTE0)
+#define JCUJINTS0 (JCU.JINTS0)
+#define JCUJCDERR (JCU.JCDERR)
+#define JCUJCRST (JCU.JCRST)
+#define JCUJIFECNT (JCU.JIFECNT)
+#define JCUJIFESA (JCU.JIFESA)
+#define JCUJIFESOFST (JCU.JIFESOFST)
+#define JCUJIFEDA (JCU.JIFEDA)
+#define JCUJIFESLC (JCU.JIFESLC)
+#define JCUJIFEDDC (JCU.JIFEDDC)
+#define JCUJIFDCNT (JCU.JIFDCNT)
+#define JCUJIFDSA (JCU.JIFDSA)
+#define JCUJIFDDOFST (JCU.JIFDDOFST)
+#define JCUJIFDDA (JCU.JIFDDA)
+#define JCUJIFDSDC (JCU.JIFDSDC)
+#define JCUJIFDDLC (JCU.JIFDDLC)
+#define JCUJIFDADT (JCU.JIFDADT)
+#define JCUJINTE1 (JCU.JINTE1)
+#define JCUJINTS1 (JCU.JINTS1)
+#define JCUJIFESVSZ (JCU.JIFESVSZ)
+#define JCUJIFESHSZ (JCU.JIFESHSZ)
+#define JCUJCQTBL0 (JCU.JCQTBL0)
+#define JCUJCQTBL1 (JCU.JCQTBL1)
+#define JCUJCQTBL2 (JCU.JCQTBL2)
+#define JCUJCQTBL3 (JCU.JCQTBL3)
+#define JCUJCHTBD0 (JCU.JCHTBD0)
+#define JCUJCHTBA0 (JCU.JCHTBA0)
+#define JCUJCHTBD1 (JCU.JCHTBD1)
+#define JCUJCHTBA1 (JCU.JCHTBA1)
+
+
+typedef struct st_jcu
+{
+                                                           /* JCU              */
     volatile uint8_t   JCMOD;                                  /*  JCMOD           */
     volatile uint8_t   JCCMD;                                  /*  JCCMD           */
     volatile uint8_t   dummy145[1];                            /*                  */
@@ -70,21 +138,29 @@
     volatile uint32_t  JIFESVSZ;                               /*  JIFESVSZ        */
     volatile uint32_t  JIFESHSZ;                               /*  JIFESHSZ        */
     volatile uint8_t   dummy148[100];                          /*                  */
+
 /* start of struct st_jcu_from_jcqtbl0 */
     volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
     volatile uint8_t   dummy149[63];                           /*                  */
+
 /* end of struct st_jcu_from_jcqtbl0 */
+
 /* start of struct st_jcu_from_jcqtbl0 */
     volatile uint8_t   JCQTBL1;                                /*  JCQTBL1         */
     volatile uint8_t   dummy150[63];                           /*                  */
+
 /* end of struct st_jcu_from_jcqtbl0 */
+
 /* start of struct st_jcu_from_jcqtbl0 */
     volatile uint8_t   JCQTBL2;                                /*  JCQTBL2         */
     volatile uint8_t   dummy151[63];                           /*                  */
+
 /* end of struct st_jcu_from_jcqtbl0 */
+
 /* start of struct st_jcu_from_jcqtbl0 */
     volatile uint8_t   JCQTBL3;                                /*  JCQTBL3         */
     volatile uint8_t   dummy152[63];                           /*                  */
+
 /* end of struct st_jcu_from_jcqtbl0 */
     volatile uint8_t   JCHTBD0;                                /*  JCHTBD0         */
     volatile uint8_t   dummy153[31];                           /*                  */
@@ -93,77 +169,29 @@
     volatile uint8_t   JCHTBD1;                                /*  JCHTBD1         */
     volatile uint8_t   dummy155[31];                           /*                  */
     volatile uint8_t   JCHTBA1;                                /*  JCHTBA1         */
-};
-
-
-struct st_jcu_from_jcqtbl0
-{
-    volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
-    volatile uint8_t   dummy1[63];                             /*                  */
-};
-
-
-#define JCU     (*(struct st_jcu     *)0xE8017000uL) /* JCU */
+} r_io_jcu_t;
 
 
-/* Start of channnel array defines of JCU */
-
-/* Channnel array defines of JCU_JCQTBL0 */
-/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
-#define JCU_JCQTBL0_COUNT  4
-#define JCU_JCQTBL0_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
-#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
-#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
-#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
-
-/* End of channnel array defines of JCU */
+typedef struct st_jcu_from_jcqtbl0
+{
+ 
+    volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
+    volatile uint8_t   dummy1[63];                             /*                  */
+} r_io_jcu_from_jcqtbl0_t;
 
 
-#define JCUJCMOD JCU.JCMOD
-#define JCUJCCMD JCU.JCCMD
-#define JCUJCQTN JCU.JCQTN
-#define JCUJCHTN JCU.JCHTN
-#define JCUJCDRIU JCU.JCDRIU
-#define JCUJCDRID JCU.JCDRID
-#define JCUJCVSZU JCU.JCVSZU
-#define JCUJCVSZD JCU.JCVSZD
-#define JCUJCHSZU JCU.JCHSZU
-#define JCUJCHSZD JCU.JCHSZD
-#define JCUJCDTCU JCU.JCDTCU
-#define JCUJCDTCM JCU.JCDTCM
-#define JCUJCDTCD JCU.JCDTCD
-#define JCUJINTE0 JCU.JINTE0
-#define JCUJINTS0 JCU.JINTS0
-#define JCUJCDERR JCU.JCDERR
-#define JCUJCRST JCU.JCRST
-#define JCUJIFECNT JCU.JIFECNT
-#define JCUJIFESA JCU.JIFESA
-#define JCUJIFESOFST JCU.JIFESOFST
-#define JCUJIFEDA JCU.JIFEDA
-#define JCUJIFESLC JCU.JIFESLC
-#define JCUJIFEDDC JCU.JIFEDDC
-#define JCUJIFDCNT JCU.JIFDCNT
-#define JCUJIFDSA JCU.JIFDSA
-#define JCUJIFDDOFST JCU.JIFDDOFST
-#define JCUJIFDDA JCU.JIFDDA
-#define JCUJIFDSDC JCU.JIFDSDC
-#define JCUJIFDDLC JCU.JIFDDLC
-#define JCUJIFDADT JCU.JIFDADT
-#define JCUJINTE1 JCU.JINTE1
-#define JCUJINTS1 JCU.JINTS1
-#define JCUJIFESVSZ JCU.JIFESVSZ
-#define JCUJIFESHSZ JCU.JIFESHSZ
-#define JCUJCQTBL0 JCU.JCQTBL0
-#define JCUJCQTBL1 JCU.JCQTBL1
-#define JCUJCQTBL2 JCU.JCQTBL2
-#define JCUJCQTBL3 JCU.JCQTBL3
-#define JCUJCHTBD0 JCU.JCHTBD0
-#define JCUJCHTBA0 JCU.JCHTBA0
-#define JCUJCHTBD1 JCU.JCHTBD1
-#define JCUJCHTBA1 JCU.JCHTBA1
+/* Channel array defines of JCU (2)*/
+#ifdef  DECLARE_JCU_JCQTBL0_CHANNELS
+volatile struct st_jcu_from_jcqtbl0*  JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    JCU_JCQTBL0_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_JCU_JCQTBL0_CHANNELS */
+/* End of channel array defines of JCU (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,97 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : l2c_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef L2C_IODEFINE_H
 #define L2C_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_l2c
-{                                                          /* L2C              */
+#define L2C     (*(struct st_l2c     *)0x3FFFF000uL) /* L2C */
+
+
+/* Start of channel array defines of L2C */
+
+/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
+/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT  (8)
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
+#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
+#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
+#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
+#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
+#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
+#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
+#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
+
+/* End of channel array defines of L2C */
+
+
+#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID)
+#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE)
+#define L2CREG1_CONTROL (L2C.REG1_CONTROL)
+#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL)
+#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL)
+#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL)
+#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL)
+#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG)
+#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG)
+#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1)
+#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0)
+#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK)
+#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS)
+#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS)
+#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR)
+#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC)
+#define L2CREG7_INV_PA (L2C.REG7_INV_PA)
+#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY)
+#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA)
+#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX)
+#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY)
+#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA)
+#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX)
+#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY)
+#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0)
+#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0)
+#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1)
+#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1)
+#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2)
+#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2)
+#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3)
+#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3)
+#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4)
+#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4)
+#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5)
+#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5)
+#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6)
+#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6)
+#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7)
+#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7)
+#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN)
+#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY)
+#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START)
+#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END)
+#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL)
+#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL)
+#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL)
+
+
+typedef struct st_l2c
+{
+                                                           /* L2C              */
     volatile uint32_t  REG0_CACHE_ID;                          /*  REG0_CACHE_ID   */
     volatile uint32_t  REG0_CACHE_TYPE;                        /*  REG0_CACHE_TYPE */
     volatile uint8_t   dummy8[248];                            /*                  */
@@ -66,37 +143,53 @@
     volatile uint32_t  REG7_CLEAN_INV_INDEX;                   /*  REG7_CLEAN_INV_INDEX */
     volatile uint32_t  REG7_CLEAN_INV_WAY;                     /*  REG7_CLEAN_INV_WAY */
     volatile uint8_t   dummy17[256];                           /*                  */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
     volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN1;                       /*  REG9_D_LOCKDOWN1 */
     volatile uint32_t  REG9_I_LOCKDOWN1;                       /*  REG9_I_LOCKDOWN1 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN2;                       /*  REG9_D_LOCKDOWN2 */
     volatile uint32_t  REG9_I_LOCKDOWN2;                       /*  REG9_I_LOCKDOWN2 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN3;                       /*  REG9_D_LOCKDOWN3 */
     volatile uint32_t  REG9_I_LOCKDOWN3;                       /*  REG9_I_LOCKDOWN3 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN4;                       /*  REG9_D_LOCKDOWN4 */
     volatile uint32_t  REG9_I_LOCKDOWN4;                       /*  REG9_I_LOCKDOWN4 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN5;                       /*  REG9_D_LOCKDOWN5 */
     volatile uint32_t  REG9_I_LOCKDOWN5;                       /*  REG9_I_LOCKDOWN5 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN6;                       /*  REG9_D_LOCKDOWN6 */
     volatile uint32_t  REG9_I_LOCKDOWN6;                       /*  REG9_I_LOCKDOWN6 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN7;                       /*  REG9_D_LOCKDOWN7 */
     volatile uint32_t  REG9_I_LOCKDOWN7;                       /*  REG9_I_LOCKDOWN7 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint8_t   dummy18[16];                            /*                  */
     volatile uint32_t  REG9_LOCK_LINE_EN;                      /*  REG9_LOCK_LINE_EN */
@@ -110,86 +203,29 @@
     volatile uint32_t  REG15_PREFETCH_CTRL;                    /*  REG15_PREFETCH_CTRL */
     volatile uint8_t   dummy22[28];                            /*                  */
     volatile uint32_t  REG15_POWER_CTRL;                       /*  REG15_POWER_CTRL */
-};
-
-
-struct st_l2c_from_reg9_d_lockdown0
-{
-    volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
-    volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
-};
-
-
-#define L2C     (*(struct st_l2c     *)0x3FFFF000uL) /* L2C */
+} r_io_l2c_t;
 
 
-/* Start of channnel array defines of L2C */
-
-/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
-/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
-#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT  8
-#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
-#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
-#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
-#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
-#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
-#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
-#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
-#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
-
-/* End of channnel array defines of L2C */
+typedef struct st_l2c_from_reg9_d_lockdown0
+{
+ 
+    volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
+    volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
+} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */;
 
 
-#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID
-#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE
-#define L2CREG1_CONTROL L2C.REG1_CONTROL
-#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL
-#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL
-#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL
-#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL
-#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG
-#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG
-#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1
-#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0
-#define L2CREG2_INT_MASK L2C.REG2_INT_MASK
-#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS
-#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS
-#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR
-#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC
-#define L2CREG7_INV_PA L2C.REG7_INV_PA
-#define L2CREG7_INV_WAY L2C.REG7_INV_WAY
-#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA
-#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX
-#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY
-#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA
-#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX
-#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY
-#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0
-#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0
-#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1
-#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1
-#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2
-#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2
-#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3
-#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3
-#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4
-#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4
-#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5
-#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5
-#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6
-#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6
-#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7
-#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7
-#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN
-#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY
-#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START
-#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END
-#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL
-#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL
-#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL
+/* Channel array defines of L2C (2)*/
+#ifdef  DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS
+volatile struct st_l2c_from_reg9_d_lockdown0*  L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */
+/* End of channel array defines of L2C (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,25 +18,101 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : lin_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef LIN_IODEFINE_H
 #define LIN_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_lin
-{                                                          /* LIN              */
+#define LIN0    (*(struct st_lin     *)0xFCFE9000uL) /* LIN0 */
+#define LIN1    (*(struct st_lin     *)0xFCFE9800uL) /* LIN1 */
+
+
+/* Start of channel array defines of LIN */
+
+/* Channel array defines of LIN */
+/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
+#define LIN_COUNT  (2)
+#define LIN_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &LIN0, &LIN1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of LIN */
+
+
+#define LIN0RLN30LWBR (LIN0.RLN3nLWBR)
+#define LIN0RLN30LBRP0 (LIN0.RLN3nLBRP0)
+#define LIN0RLN30LBRP1 (LIN0.RLN3nLBRP1)
+#define LIN0RLN30LSTC (LIN0.RLN3nLSTC)
+#define LIN0RLN30LMD (LIN0.RLN3nLMD)
+#define LIN0RLN30LBFC (LIN0.RLN3nLBFC)
+#define LIN0RLN30LSC (LIN0.RLN3nLSC)
+#define LIN0RLN30LWUP (LIN0.RLN3nLWUP)
+#define LIN0RLN30LIE (LIN0.RLN3nLIE)
+#define LIN0RLN30LEDE (LIN0.RLN3nLEDE)
+#define LIN0RLN30LCUC (LIN0.RLN3nLCUC)
+#define LIN0RLN30LTRC (LIN0.RLN3nLTRC)
+#define LIN0RLN30LMST (LIN0.RLN3nLMST)
+#define LIN0RLN30LST (LIN0.RLN3nLST)
+#define LIN0RLN30LEST (LIN0.RLN3nLEST)
+#define LIN0RLN30LDFC (LIN0.RLN3nLDFC)
+#define LIN0RLN30LIDB (LIN0.RLN3nLIDB)
+#define LIN0RLN30LCBR (LIN0.RLN3nLCBR)
+#define LIN0RLN30LDBR1 (LIN0.RLN3nLDBR1)
+#define LIN0RLN30LDBR2 (LIN0.RLN3nLDBR2)
+#define LIN0RLN30LDBR3 (LIN0.RLN3nLDBR3)
+#define LIN0RLN30LDBR4 (LIN0.RLN3nLDBR4)
+#define LIN0RLN30LDBR5 (LIN0.RLN3nLDBR5)
+#define LIN0RLN30LDBR6 (LIN0.RLN3nLDBR6)
+#define LIN0RLN30LDBR7 (LIN0.RLN3nLDBR7)
+#define LIN0RLN30LDBR8 (LIN0.RLN3nLDBR8)
+#define LIN1RLN31LWBR (LIN1.RLN3nLWBR)
+#define LIN1RLN31LBRP0 (LIN1.RLN3nLBRP0)
+#define LIN1RLN31LBRP1 (LIN1.RLN3nLBRP1)
+#define LIN1RLN31LSTC (LIN1.RLN3nLSTC)
+#define LIN1RLN31LMD (LIN1.RLN3nLMD)
+#define LIN1RLN31LBFC (LIN1.RLN3nLBFC)
+#define LIN1RLN31LSC (LIN1.RLN3nLSC)
+#define LIN1RLN31LWUP (LIN1.RLN3nLWUP)
+#define LIN1RLN31LIE (LIN1.RLN3nLIE)
+#define LIN1RLN31LEDE (LIN1.RLN3nLEDE)
+#define LIN1RLN31LCUC (LIN1.RLN3nLCUC)
+#define LIN1RLN31LTRC (LIN1.RLN3nLTRC)
+#define LIN1RLN31LMST (LIN1.RLN3nLMST)
+#define LIN1RLN31LST (LIN1.RLN3nLST)
+#define LIN1RLN31LEST (LIN1.RLN3nLEST)
+#define LIN1RLN31LDFC (LIN1.RLN3nLDFC)
+#define LIN1RLN31LIDB (LIN1.RLN3nLIDB)
+#define LIN1RLN31LCBR (LIN1.RLN3nLCBR)
+#define LIN1RLN31LDBR1 (LIN1.RLN3nLDBR1)
+#define LIN1RLN31LDBR2 (LIN1.RLN3nLDBR2)
+#define LIN1RLN31LDBR3 (LIN1.RLN3nLDBR3)
+#define LIN1RLN31LDBR4 (LIN1.RLN3nLDBR4)
+#define LIN1RLN31LDBR5 (LIN1.RLN3nLDBR5)
+#define LIN1RLN31LDBR6 (LIN1.RLN3nLDBR6)
+#define LIN1RLN31LDBR7 (LIN1.RLN3nLDBR7)
+#define LIN1RLN31LDBR8 (LIN1.RLN3nLDBR8)
+
+#define LIN_LDBn_COUNT (8)
+
+
+typedef struct st_lin
+{
+                                                           /* LIN              */
     volatile uint8_t   dummy1[1];                              /*                  */
     volatile uint8_t   RLN3nLWBR;                              /*  RLN3nLWBR       */
-    union iodefine_reg16_8_t  RLN3nLBRP01;                     /*  RLN3nLBRP01 */
-    
+    volatile uint8_t   RLN3nLBRP0;                             /*  RLN3nLBRP0      */
+    volatile uint8_t   RLN3nLBRP1;                             /*  RLN3nLBRP1      */
     volatile uint8_t   RLN3nLSTC;                              /*  RLN3nLSTC       */
     volatile uint8_t   dummy2[3];                              /*                  */
     volatile uint8_t   RLN3nLMD;                               /*  RLN3nLMD        */
@@ -54,8 +130,9 @@
     volatile uint8_t   RLN3nLDFC;                              /*  RLN3nLDFC       */
     volatile uint8_t   RLN3nLIDB;                              /*  RLN3nLIDB       */
     volatile uint8_t   RLN3nLCBR;                              /*  RLN3nLCBR       */
-    volatile uint8_t   RLN3nLUDB0;                             /*  RLN3nLUDB0      */
-#define LIN_LDBn_COUNT 8
+    volatile uint8_t   dummy4[1];                              /*                  */
+
+/* #define LIN_LDBn_COUNT (8) */
     volatile uint8_t   RLN3nLDBR1;                             /*  RLN3nLDBR1      */
     volatile uint8_t   RLN3nLDBR2;                             /*  RLN3nLDBR2      */
     volatile uint8_t   RLN3nLDBR3;                             /*  RLN3nLDBR3      */
@@ -64,111 +141,21 @@
     volatile uint8_t   RLN3nLDBR6;                             /*  RLN3nLDBR6      */
     volatile uint8_t   RLN3nLDBR7;                             /*  RLN3nLDBR7      */
     volatile uint8_t   RLN3nLDBR8;                             /*  RLN3nLDBR8      */
-    volatile uint8_t   RLN3nLUOER;                             /*  RLN3nLUOER      */
-    volatile uint8_t   RLN3nLUOR1;                             /*  RLN3nLUOR1      */
-    volatile uint8_t   dummy4[2];                              /*                  */
-    union iodefine_reg16_8_t  RLN3nLUTDR;                      /*  RLN3nLUTDR  */
-    union iodefine_reg16_8_t  RLN3nLURDR;                      /*  RLN3nLURDR  */
-    union iodefine_reg16_8_t  RLN3nLUWTDR;                     /*  RLN3nLUWTDR */
-    
-};
-
-
-#define LIN0    (*(struct st_lin     *)0xFCFE9000uL) /* LIN0 */
-#define LIN1    (*(struct st_lin     *)0xFCFE9800uL) /* LIN1 */
-
-
-/* Start of channnel array defines of LIN */
-
-/* Channnel array defines of LIN */
-/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
-#define LIN_COUNT  2
-#define LIN_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &LIN0, &LIN1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of LIN */
+} r_io_lin_t;
 
 
-#define LIN0RLN30LWBR LIN0.RLN3nLWBR
-#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16
-#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L]
-#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H]
-#define LIN0RLN30LSTC LIN0.RLN3nLSTC
-#define LIN0RLN30LMD LIN0.RLN3nLMD
-#define LIN0RLN30LBFC LIN0.RLN3nLBFC
-#define LIN0RLN30LSC LIN0.RLN3nLSC
-#define LIN0RLN30LWUP LIN0.RLN3nLWUP
-#define LIN0RLN30LIE LIN0.RLN3nLIE
-#define LIN0RLN30LEDE LIN0.RLN3nLEDE
-#define LIN0RLN30LCUC LIN0.RLN3nLCUC
-#define LIN0RLN30LTRC LIN0.RLN3nLTRC
-#define LIN0RLN30LMST LIN0.RLN3nLMST
-#define LIN0RLN30LST LIN0.RLN3nLST
-#define LIN0RLN30LEST LIN0.RLN3nLEST
-#define LIN0RLN30LDFC LIN0.RLN3nLDFC
-#define LIN0RLN30LIDB LIN0.RLN3nLIDB
-#define LIN0RLN30LCBR LIN0.RLN3nLCBR
-#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0
-#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1
-#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2
-#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3
-#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4
-#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5
-#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6
-#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7
-#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8
-#define LIN0RLN30LUOER LIN0.RLN3nLUOER
-#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1
-#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16
-#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L]
-#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H]
-#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16
-#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L]
-#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H]
-#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16
-#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L]
-#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H]
-#define LIN1RLN31LWBR LIN1.RLN3nLWBR
-#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16
-#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L]
-#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H]
-#define LIN1RLN31LSTC LIN1.RLN3nLSTC
-#define LIN1RLN31LMD LIN1.RLN3nLMD
-#define LIN1RLN31LBFC LIN1.RLN3nLBFC
-#define LIN1RLN31LSC LIN1.RLN3nLSC
-#define LIN1RLN31LWUP LIN1.RLN3nLWUP
-#define LIN1RLN31LIE LIN1.RLN3nLIE
-#define LIN1RLN31LEDE LIN1.RLN3nLEDE
-#define LIN1RLN31LCUC LIN1.RLN3nLCUC
-#define LIN1RLN31LTRC LIN1.RLN3nLTRC
-#define LIN1RLN31LMST LIN1.RLN3nLMST
-#define LIN1RLN31LST LIN1.RLN3nLST
-#define LIN1RLN31LEST LIN1.RLN3nLEST
-#define LIN1RLN31LDFC LIN1.RLN3nLDFC
-#define LIN1RLN31LIDB LIN1.RLN3nLIDB
-#define LIN1RLN31LCBR LIN1.RLN3nLCBR
-#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0
-#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1
-#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2
-#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3
-#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4
-#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5
-#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6
-#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7
-#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8
-#define LIN1RLN31LUOER LIN1.RLN3nLUOER
-#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1
-#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16
-#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L]
-#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H]
-#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16
-#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L]
-#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H]
-#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16
-#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L]
-#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H]
+/* Channel array defines of LIN (2)*/
+#ifdef  DECLARE_LIN_CHANNELS
+volatile struct st_lin*  LIN[ LIN_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    LIN_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_LIN_CHANNELS */
+/* End of channel array defines of LIN (2)*/
+
+
 /* <-SEC M1.10.1 */
 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,34 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : lvds_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.01a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef LVDS_IODEFINE_H
 #define LVDS_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_lvds
-{                                                          /* LVDS             */
+#define LVDS    (*(struct st_lvds    *)0xFCFF7A30uL) /* LVDS */
+
+
+#define LVDSLVDS_UPDATE (LVDS.LVDS_UPDATE)
+#define LVDSLVDSFCL (LVDS.LVDSFCL)
+#define LVDSLCLKSELR (LVDS.LCLKSELR)
+#define LVDSLPLLSETR (LVDS.LPLLSETR)
+#define LVDSLPHYACC (LVDS.LPHYACC)
+
+
+typedef struct st_lvds
+{
+                                                           /* LVDS             */
     volatile uint32_t  LVDS_UPDATE;                            /*  LVDS_UPDATE     */
     volatile uint32_t  LVDSFCL;                                /*  LVDSFCL         */
     volatile uint8_t   dummy608[24];                           /*                  */
@@ -39,16 +53,11 @@
     volatile uint32_t  LPLLSETR;                               /*  LPLLSETR        */
     volatile uint8_t   dummy609[4];                            /*                  */
     volatile uint32_t  LPHYACC;                                /*  LPHYACC         */
-};
-
-
-#define LVDS    (*(struct st_lvds    *)0xFCFF7A30uL) /* LVDS */
+} r_io_lvds_t;
 
 
-#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE
-#define LVDSLVDSFCL LVDS.LVDSFCL
-#define LVDSLCLKSELR LVDS.LCLKSELR
-#define LVDSLPLLSETR LVDS.LPLLSETR
-#define LVDSLPHYACC LVDS.LPHYACC
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,273 +18,29 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : mlb_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef MLB_IODEFINE_H
 #define MLB_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
 /* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_mlb
-{                                                          /* MLB              */
-    volatile uint32_t  DCCR;                                   /*  DCCR            */
-    volatile uint32_t  SSCR;                                   /*  SSCR            */
-    volatile uint32_t  SDCR;                                   /*  SDCR            */
-    volatile uint32_t  SMCR;                                   /*  SMCR            */
-    volatile uint8_t   dummy156[12];                           /*                  */
-    volatile uint32_t  VCCR;                                   /*  VCCR            */
-    volatile uint32_t  SBCR;                                   /*  SBCR            */
-    volatile uint32_t  ABCR;                                   /*  ABCR            */
-    volatile uint32_t  CBCR;                                   /*  CBCR            */
-    volatile uint32_t  IBCR;                                   /*  IBCR            */
-    volatile uint32_t  CICR;                                   /*  CICR            */
-    volatile uint8_t   dummy157[12];                           /*                  */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR0;                                  /*  CECR0           */
-    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
-    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
-    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR1;                                  /*  CECR1           */
-    volatile uint32_t  CSCR1;                                  /*  CSCR1           */
-    volatile uint32_t  CCBCR1;                                 /*  CCBCR1          */
-    volatile uint32_t  CNBCR1;                                 /*  CNBCR1          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR2;                                  /*  CECR2           */
-    volatile uint32_t  CSCR2;                                  /*  CSCR2           */
-    volatile uint32_t  CCBCR2;                                 /*  CCBCR2          */
-    volatile uint32_t  CNBCR2;                                 /*  CNBCR2          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR3;                                  /*  CECR3           */
-    volatile uint32_t  CSCR3;                                  /*  CSCR3           */
-    volatile uint32_t  CCBCR3;                                 /*  CCBCR3          */
-    volatile uint32_t  CNBCR3;                                 /*  CNBCR3          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR4;                                  /*  CECR4           */
-    volatile uint32_t  CSCR4;                                  /*  CSCR4           */
-    volatile uint32_t  CCBCR4;                                 /*  CCBCR4          */
-    volatile uint32_t  CNBCR4;                                 /*  CNBCR4          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR5;                                  /*  CECR5           */
-    volatile uint32_t  CSCR5;                                  /*  CSCR5           */
-    volatile uint32_t  CCBCR5;                                 /*  CCBCR5          */
-    volatile uint32_t  CNBCR5;                                 /*  CNBCR5          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR6;                                  /*  CECR6           */
-    volatile uint32_t  CSCR6;                                  /*  CSCR6           */
-    volatile uint32_t  CCBCR6;                                 /*  CCBCR6          */
-    volatile uint32_t  CNBCR6;                                 /*  CNBCR6          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR7;                                  /*  CECR7           */
-    volatile uint32_t  CSCR7;                                  /*  CSCR7           */
-    volatile uint32_t  CCBCR7;                                 /*  CCBCR7          */
-    volatile uint32_t  CNBCR7;                                 /*  CNBCR7          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR8;                                  /*  CECR8           */
-    volatile uint32_t  CSCR8;                                  /*  CSCR8           */
-    volatile uint32_t  CCBCR8;                                 /*  CCBCR8          */
-    volatile uint32_t  CNBCR8;                                 /*  CNBCR8          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR9;                                  /*  CECR9           */
-    volatile uint32_t  CSCR9;                                  /*  CSCR9           */
-    volatile uint32_t  CCBCR9;                                 /*  CCBCR9          */
-    volatile uint32_t  CNBCR9;                                 /*  CNBCR9          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR10;                                 /*  CECR10          */
-    volatile uint32_t  CSCR10;                                 /*  CSCR10          */
-    volatile uint32_t  CCBCR10;                                /*  CCBCR10         */
-    volatile uint32_t  CNBCR10;                                /*  CNBCR10         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR11;                                 /*  CECR11          */
-    volatile uint32_t  CSCR11;                                 /*  CSCR11          */
-    volatile uint32_t  CCBCR11;                                /*  CCBCR11         */
-    volatile uint32_t  CNBCR11;                                /*  CNBCR11         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR12;                                 /*  CECR12          */
-    volatile uint32_t  CSCR12;                                 /*  CSCR12          */
-    volatile uint32_t  CCBCR12;                                /*  CCBCR12         */
-    volatile uint32_t  CNBCR12;                                /*  CNBCR12         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR13;                                 /*  CECR13          */
-    volatile uint32_t  CSCR13;                                 /*  CSCR13          */
-    volatile uint32_t  CCBCR13;                                /*  CCBCR13         */
-    volatile uint32_t  CNBCR13;                                /*  CNBCR13         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR14;                                 /*  CECR14          */
-    volatile uint32_t  CSCR14;                                 /*  CSCR14          */
-    volatile uint32_t  CCBCR14;                                /*  CCBCR14         */
-    volatile uint32_t  CNBCR14;                                /*  CNBCR14         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR15;                                 /*  CECR15          */
-    volatile uint32_t  CSCR15;                                 /*  CSCR15          */
-    volatile uint32_t  CCBCR15;                                /*  CCBCR15         */
-    volatile uint32_t  CNBCR15;                                /*  CNBCR15         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR16;                                 /*  CECR16          */
-    volatile uint32_t  CSCR16;                                 /*  CSCR16          */
-    volatile uint32_t  CCBCR16;                                /*  CCBCR16         */
-    volatile uint32_t  CNBCR16;                                /*  CNBCR16         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR17;                                 /*  CECR17          */
-    volatile uint32_t  CSCR17;                                 /*  CSCR17          */
-    volatile uint32_t  CCBCR17;                                /*  CCBCR17         */
-    volatile uint32_t  CNBCR17;                                /*  CNBCR17         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR18;                                 /*  CECR18          */
-    volatile uint32_t  CSCR18;                                 /*  CSCR18          */
-    volatile uint32_t  CCBCR18;                                /*  CCBCR18         */
-    volatile uint32_t  CNBCR18;                                /*  CNBCR18         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR19;                                 /*  CECR19          */
-    volatile uint32_t  CSCR19;                                 /*  CSCR19          */
-    volatile uint32_t  CCBCR19;                                /*  CCBCR19         */
-    volatile uint32_t  CNBCR19;                                /*  CNBCR19         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR20;                                 /*  CECR20          */
-    volatile uint32_t  CSCR20;                                 /*  CSCR20          */
-    volatile uint32_t  CCBCR20;                                /*  CCBCR20         */
-    volatile uint32_t  CNBCR20;                                /*  CNBCR20         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR21;                                 /*  CECR21          */
-    volatile uint32_t  CSCR21;                                 /*  CSCR21          */
-    volatile uint32_t  CCBCR21;                                /*  CCBCR21         */
-    volatile uint32_t  CNBCR21;                                /*  CNBCR21         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR22;                                 /*  CECR22          */
-    volatile uint32_t  CSCR22;                                 /*  CSCR22          */
-    volatile uint32_t  CCBCR22;                                /*  CCBCR22         */
-    volatile uint32_t  CNBCR22;                                /*  CNBCR22         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR23;                                 /*  CECR23          */
-    volatile uint32_t  CSCR23;                                 /*  CSCR23          */
-    volatile uint32_t  CCBCR23;                                /*  CCBCR23         */
-    volatile uint32_t  CNBCR23;                                /*  CNBCR23         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR24;                                 /*  CECR24          */
-    volatile uint32_t  CSCR24;                                 /*  CSCR24          */
-    volatile uint32_t  CCBCR24;                                /*  CCBCR24         */
-    volatile uint32_t  CNBCR24;                                /*  CNBCR24         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR25;                                 /*  CECR25          */
-    volatile uint32_t  CSCR25;                                 /*  CSCR25          */
-    volatile uint32_t  CCBCR25;                                /*  CCBCR25         */
-    volatile uint32_t  CNBCR25;                                /*  CNBCR25         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR26;                                 /*  CECR26          */
-    volatile uint32_t  CSCR26;                                 /*  CSCR26          */
-    volatile uint32_t  CCBCR26;                                /*  CCBCR26         */
-    volatile uint32_t  CNBCR26;                                /*  CNBCR26         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR27;                                 /*  CECR27          */
-    volatile uint32_t  CSCR27;                                 /*  CSCR27          */
-    volatile uint32_t  CCBCR27;                                /*  CCBCR27         */
-    volatile uint32_t  CNBCR27;                                /*  CNBCR27         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR28;                                 /*  CECR28          */
-    volatile uint32_t  CSCR28;                                 /*  CSCR28          */
-    volatile uint32_t  CCBCR28;                                /*  CCBCR28         */
-    volatile uint32_t  CNBCR28;                                /*  CNBCR28         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR29;                                 /*  CECR29          */
-    volatile uint32_t  CSCR29;                                 /*  CSCR29          */
-    volatile uint32_t  CCBCR29;                                /*  CCBCR29         */
-    volatile uint32_t  CNBCR29;                                /*  CNBCR29         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR30;                                 /*  CECR30          */
-    volatile uint32_t  CSCR30;                                 /*  CSCR30          */
-    volatile uint32_t  CCBCR30;                                /*  CCBCR30         */
-    volatile uint32_t  CNBCR30;                                /*  CNBCR30         */
-/* end of struct st_mlb_from_cecr0 */
-    volatile uint8_t   dummy158[80];                           /*                  */
-#define MLB_LCBCR0_COUNT 31
-    volatile uint32_t  LCBCR0;                                 /*  LCBCR0          */
-    volatile uint32_t  LCBCR1;                                 /*  LCBCR1          */
-    volatile uint32_t  LCBCR2;                                 /*  LCBCR2          */
-    volatile uint32_t  LCBCR3;                                 /*  LCBCR3          */
-    volatile uint32_t  LCBCR4;                                 /*  LCBCR4          */
-    volatile uint32_t  LCBCR5;                                 /*  LCBCR5          */
-    volatile uint32_t  LCBCR6;                                 /*  LCBCR6          */
-    volatile uint32_t  LCBCR7;                                 /*  LCBCR7          */
-    volatile uint32_t  LCBCR8;                                 /*  LCBCR8          */
-    volatile uint32_t  LCBCR9;                                 /*  LCBCR9          */
-    volatile uint32_t  LCBCR10;                                /*  LCBCR10         */
-    volatile uint32_t  LCBCR11;                                /*  LCBCR11         */
-    volatile uint32_t  LCBCR12;                                /*  LCBCR12         */
-    volatile uint32_t  LCBCR13;                                /*  LCBCR13         */
-    volatile uint32_t  LCBCR14;                                /*  LCBCR14         */
-    volatile uint32_t  LCBCR15;                                /*  LCBCR15         */
-    volatile uint32_t  LCBCR16;                                /*  LCBCR16         */
-    volatile uint32_t  LCBCR17;                                /*  LCBCR17         */
-    volatile uint32_t  LCBCR18;                                /*  LCBCR18         */
-    volatile uint32_t  LCBCR19;                                /*  LCBCR19         */
-    volatile uint32_t  LCBCR20;                                /*  LCBCR20         */
-    volatile uint32_t  LCBCR21;                                /*  LCBCR21         */
-    volatile uint32_t  LCBCR22;                                /*  LCBCR22         */
-    volatile uint32_t  LCBCR23;                                /*  LCBCR23         */
-    volatile uint32_t  LCBCR24;                                /*  LCBCR24         */
-    volatile uint32_t  LCBCR25;                                /*  LCBCR25         */
-    volatile uint32_t  LCBCR26;                                /*  LCBCR26         */
-    volatile uint32_t  LCBCR27;                                /*  LCBCR27         */
-    volatile uint32_t  LCBCR28;                                /*  LCBCR28         */
-    volatile uint32_t  LCBCR29;                                /*  LCBCR29         */
-    volatile uint32_t  LCBCR30;                                /*  LCBCR30         */
-};
-
-
-struct st_mlb_from_cecr0
-{
-    volatile uint32_t  CECR0;                                  /*  CECR0           */
-    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
-    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
-    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
-};
-
-
 #define MLB     (*(struct st_mlb     *)0xE8034000uL) /* MLB */
 
 
-/* Start of channnel array defines of MLB */
+/* Start of channel array defines of MLB */
 
-/* Channnel array defines of MLB_FROM_CECR0_ARRAY */
+/* Channel array defines of MLB_FROM_CECR0_ARRAY */
 /*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */
-#define MLB_FROM_CECR0_ARRAY_COUNT  31
+#define MLB_FROM_CECR0_ARRAY_COUNT  (31)
 #define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \
@@ -324,175 +80,500 @@
 #define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */
 #define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */
 
-/* End of channnel array defines of MLB */
+/* End of channel array defines of MLB */
+
+
+#define MLBDCCR (MLB.DCCR)
+#define MLBSSCR (MLB.SSCR)
+#define MLBSDCR (MLB.SDCR)
+#define MLBSMCR (MLB.SMCR)
+#define MLBVCCR (MLB.VCCR)
+#define MLBSBCR (MLB.SBCR)
+#define MLBABCR (MLB.ABCR)
+#define MLBCBCR (MLB.CBCR)
+#define MLBIBCR (MLB.IBCR)
+#define MLBCICR (MLB.CICR)
+#define MLBCECR0 (MLB.CECR0)
+#define MLBCSCR0 (MLB.CSCR0)
+#define MLBCCBCR0 (MLB.CCBCR0)
+#define MLBCNBCR0 (MLB.CNBCR0)
+#define MLBCECR1 (MLB.CECR1)
+#define MLBCSCR1 (MLB.CSCR1)
+#define MLBCCBCR1 (MLB.CCBCR1)
+#define MLBCNBCR1 (MLB.CNBCR1)
+#define MLBCECR2 (MLB.CECR2)
+#define MLBCSCR2 (MLB.CSCR2)
+#define MLBCCBCR2 (MLB.CCBCR2)
+#define MLBCNBCR2 (MLB.CNBCR2)
+#define MLBCECR3 (MLB.CECR3)
+#define MLBCSCR3 (MLB.CSCR3)
+#define MLBCCBCR3 (MLB.CCBCR3)
+#define MLBCNBCR3 (MLB.CNBCR3)
+#define MLBCECR4 (MLB.CECR4)
+#define MLBCSCR4 (MLB.CSCR4)
+#define MLBCCBCR4 (MLB.CCBCR4)
+#define MLBCNBCR4 (MLB.CNBCR4)
+#define MLBCECR5 (MLB.CECR5)
+#define MLBCSCR5 (MLB.CSCR5)
+#define MLBCCBCR5 (MLB.CCBCR5)
+#define MLBCNBCR5 (MLB.CNBCR5)
+#define MLBCECR6 (MLB.CECR6)
+#define MLBCSCR6 (MLB.CSCR6)
+#define MLBCCBCR6 (MLB.CCBCR6)
+#define MLBCNBCR6 (MLB.CNBCR6)
+#define MLBCECR7 (MLB.CECR7)
+#define MLBCSCR7 (MLB.CSCR7)
+#define MLBCCBCR7 (MLB.CCBCR7)
+#define MLBCNBCR7 (MLB.CNBCR7)
+#define MLBCECR8 (MLB.CECR8)
+#define MLBCSCR8 (MLB.CSCR8)
+#define MLBCCBCR8 (MLB.CCBCR8)
+#define MLBCNBCR8 (MLB.CNBCR8)
+#define MLBCECR9 (MLB.CECR9)
+#define MLBCSCR9 (MLB.CSCR9)
+#define MLBCCBCR9 (MLB.CCBCR9)
+#define MLBCNBCR9 (MLB.CNBCR9)
+#define MLBCECR10 (MLB.CECR10)
+#define MLBCSCR10 (MLB.CSCR10)
+#define MLBCCBCR10 (MLB.CCBCR10)
+#define MLBCNBCR10 (MLB.CNBCR10)
+#define MLBCECR11 (MLB.CECR11)
+#define MLBCSCR11 (MLB.CSCR11)
+#define MLBCCBCR11 (MLB.CCBCR11)
+#define MLBCNBCR11 (MLB.CNBCR11)
+#define MLBCECR12 (MLB.CECR12)
+#define MLBCSCR12 (MLB.CSCR12)
+#define MLBCCBCR12 (MLB.CCBCR12)
+#define MLBCNBCR12 (MLB.CNBCR12)
+#define MLBCECR13 (MLB.CECR13)
+#define MLBCSCR13 (MLB.CSCR13)
+#define MLBCCBCR13 (MLB.CCBCR13)
+#define MLBCNBCR13 (MLB.CNBCR13)
+#define MLBCECR14 (MLB.CECR14)
+#define MLBCSCR14 (MLB.CSCR14)
+#define MLBCCBCR14 (MLB.CCBCR14)
+#define MLBCNBCR14 (MLB.CNBCR14)
+#define MLBCECR15 (MLB.CECR15)
+#define MLBCSCR15 (MLB.CSCR15)
+#define MLBCCBCR15 (MLB.CCBCR15)
+#define MLBCNBCR15 (MLB.CNBCR15)
+#define MLBCECR16 (MLB.CECR16)
+#define MLBCSCR16 (MLB.CSCR16)
+#define MLBCCBCR16 (MLB.CCBCR16)
+#define MLBCNBCR16 (MLB.CNBCR16)
+#define MLBCECR17 (MLB.CECR17)
+#define MLBCSCR17 (MLB.CSCR17)
+#define MLBCCBCR17 (MLB.CCBCR17)
+#define MLBCNBCR17 (MLB.CNBCR17)
+#define MLBCECR18 (MLB.CECR18)
+#define MLBCSCR18 (MLB.CSCR18)
+#define MLBCCBCR18 (MLB.CCBCR18)
+#define MLBCNBCR18 (MLB.CNBCR18)
+#define MLBCECR19 (MLB.CECR19)
+#define MLBCSCR19 (MLB.CSCR19)
+#define MLBCCBCR19 (MLB.CCBCR19)
+#define MLBCNBCR19 (MLB.CNBCR19)
+#define MLBCECR20 (MLB.CECR20)
+#define MLBCSCR20 (MLB.CSCR20)
+#define MLBCCBCR20 (MLB.CCBCR20)
+#define MLBCNBCR20 (MLB.CNBCR20)
+#define MLBCECR21 (MLB.CECR21)
+#define MLBCSCR21 (MLB.CSCR21)
+#define MLBCCBCR21 (MLB.CCBCR21)
+#define MLBCNBCR21 (MLB.CNBCR21)
+#define MLBCECR22 (MLB.CECR22)
+#define MLBCSCR22 (MLB.CSCR22)
+#define MLBCCBCR22 (MLB.CCBCR22)
+#define MLBCNBCR22 (MLB.CNBCR22)
+#define MLBCECR23 (MLB.CECR23)
+#define MLBCSCR23 (MLB.CSCR23)
+#define MLBCCBCR23 (MLB.CCBCR23)
+#define MLBCNBCR23 (MLB.CNBCR23)
+#define MLBCECR24 (MLB.CECR24)
+#define MLBCSCR24 (MLB.CSCR24)
+#define MLBCCBCR24 (MLB.CCBCR24)
+#define MLBCNBCR24 (MLB.CNBCR24)
+#define MLBCECR25 (MLB.CECR25)
+#define MLBCSCR25 (MLB.CSCR25)
+#define MLBCCBCR25 (MLB.CCBCR25)
+#define MLBCNBCR25 (MLB.CNBCR25)
+#define MLBCECR26 (MLB.CECR26)
+#define MLBCSCR26 (MLB.CSCR26)
+#define MLBCCBCR26 (MLB.CCBCR26)
+#define MLBCNBCR26 (MLB.CNBCR26)
+#define MLBCECR27 (MLB.CECR27)
+#define MLBCSCR27 (MLB.CSCR27)
+#define MLBCCBCR27 (MLB.CCBCR27)
+#define MLBCNBCR27 (MLB.CNBCR27)
+#define MLBCECR28 (MLB.CECR28)
+#define MLBCSCR28 (MLB.CSCR28)
+#define MLBCCBCR28 (MLB.CCBCR28)
+#define MLBCNBCR28 (MLB.CNBCR28)
+#define MLBCECR29 (MLB.CECR29)
+#define MLBCSCR29 (MLB.CSCR29)
+#define MLBCCBCR29 (MLB.CCBCR29)
+#define MLBCNBCR29 (MLB.CNBCR29)
+#define MLBCECR30 (MLB.CECR30)
+#define MLBCSCR30 (MLB.CSCR30)
+#define MLBCCBCR30 (MLB.CCBCR30)
+#define MLBCNBCR30 (MLB.CNBCR30)
+#define MLBLCBCR0 (MLB.LCBCR0)
+#define MLBLCBCR1 (MLB.LCBCR1)
+#define MLBLCBCR2 (MLB.LCBCR2)
+#define MLBLCBCR3 (MLB.LCBCR3)
+#define MLBLCBCR4 (MLB.LCBCR4)
+#define MLBLCBCR5 (MLB.LCBCR5)
+#define MLBLCBCR6 (MLB.LCBCR6)
+#define MLBLCBCR7 (MLB.LCBCR7)
+#define MLBLCBCR8 (MLB.LCBCR8)
+#define MLBLCBCR9 (MLB.LCBCR9)
+#define MLBLCBCR10 (MLB.LCBCR10)
+#define MLBLCBCR11 (MLB.LCBCR11)
+#define MLBLCBCR12 (MLB.LCBCR12)
+#define MLBLCBCR13 (MLB.LCBCR13)
+#define MLBLCBCR14 (MLB.LCBCR14)
+#define MLBLCBCR15 (MLB.LCBCR15)
+#define MLBLCBCR16 (MLB.LCBCR16)
+#define MLBLCBCR17 (MLB.LCBCR17)
+#define MLBLCBCR18 (MLB.LCBCR18)
+#define MLBLCBCR19 (MLB.LCBCR19)
+#define MLBLCBCR20 (MLB.LCBCR20)
+#define MLBLCBCR21 (MLB.LCBCR21)
+#define MLBLCBCR22 (MLB.LCBCR22)
+#define MLBLCBCR23 (MLB.LCBCR23)
+#define MLBLCBCR24 (MLB.LCBCR24)
+#define MLBLCBCR25 (MLB.LCBCR25)
+#define MLBLCBCR26 (MLB.LCBCR26)
+#define MLBLCBCR27 (MLB.LCBCR27)
+#define MLBLCBCR28 (MLB.LCBCR28)
+#define MLBLCBCR29 (MLB.LCBCR29)
+#define MLBLCBCR30 (MLB.LCBCR30)
+
+#define MLB_LCBCR0_COUNT (31)
 
 
-#define MLBDCCR MLB.DCCR
-#define MLBSSCR MLB.SSCR
-#define MLBSDCR MLB.SDCR
-#define MLBSMCR MLB.SMCR
-#define MLBVCCR MLB.VCCR
-#define MLBSBCR MLB.SBCR
-#define MLBABCR MLB.ABCR
-#define MLBCBCR MLB.CBCR
-#define MLBIBCR MLB.IBCR
-#define MLBCICR MLB.CICR
-#define MLBCECR0 MLB.CECR0
-#define MLBCSCR0 MLB.CSCR0
-#define MLBCCBCR0 MLB.CCBCR0
-#define MLBCNBCR0 MLB.CNBCR0
-#define MLBCECR1 MLB.CECR1
-#define MLBCSCR1 MLB.CSCR1
-#define MLBCCBCR1 MLB.CCBCR1
-#define MLBCNBCR1 MLB.CNBCR1
-#define MLBCECR2 MLB.CECR2
-#define MLBCSCR2 MLB.CSCR2
-#define MLBCCBCR2 MLB.CCBCR2
-#define MLBCNBCR2 MLB.CNBCR2
-#define MLBCECR3 MLB.CECR3
-#define MLBCSCR3 MLB.CSCR3
-#define MLBCCBCR3 MLB.CCBCR3
-#define MLBCNBCR3 MLB.CNBCR3
-#define MLBCECR4 MLB.CECR4
-#define MLBCSCR4 MLB.CSCR4
-#define MLBCCBCR4 MLB.CCBCR4
-#define MLBCNBCR4 MLB.CNBCR4
-#define MLBCECR5 MLB.CECR5
-#define MLBCSCR5 MLB.CSCR5
-#define MLBCCBCR5 MLB.CCBCR5
-#define MLBCNBCR5 MLB.CNBCR5
-#define MLBCECR6 MLB.CECR6
-#define MLBCSCR6 MLB.CSCR6
-#define MLBCCBCR6 MLB.CCBCR6
-#define MLBCNBCR6 MLB.CNBCR6
-#define MLBCECR7 MLB.CECR7
-#define MLBCSCR7 MLB.CSCR7
-#define MLBCCBCR7 MLB.CCBCR7
-#define MLBCNBCR7 MLB.CNBCR7
-#define MLBCECR8 MLB.CECR8
-#define MLBCSCR8 MLB.CSCR8
-#define MLBCCBCR8 MLB.CCBCR8
-#define MLBCNBCR8 MLB.CNBCR8
-#define MLBCECR9 MLB.CECR9
-#define MLBCSCR9 MLB.CSCR9
-#define MLBCCBCR9 MLB.CCBCR9
-#define MLBCNBCR9 MLB.CNBCR9
-#define MLBCECR10 MLB.CECR10
-#define MLBCSCR10 MLB.CSCR10
-#define MLBCCBCR10 MLB.CCBCR10
-#define MLBCNBCR10 MLB.CNBCR10
-#define MLBCECR11 MLB.CECR11
-#define MLBCSCR11 MLB.CSCR11
-#define MLBCCBCR11 MLB.CCBCR11
-#define MLBCNBCR11 MLB.CNBCR11
-#define MLBCECR12 MLB.CECR12
-#define MLBCSCR12 MLB.CSCR12
-#define MLBCCBCR12 MLB.CCBCR12
-#define MLBCNBCR12 MLB.CNBCR12
-#define MLBCECR13 MLB.CECR13
-#define MLBCSCR13 MLB.CSCR13
-#define MLBCCBCR13 MLB.CCBCR13
-#define MLBCNBCR13 MLB.CNBCR13
-#define MLBCECR14 MLB.CECR14
-#define MLBCSCR14 MLB.CSCR14
-#define MLBCCBCR14 MLB.CCBCR14
-#define MLBCNBCR14 MLB.CNBCR14
-#define MLBCECR15 MLB.CECR15
-#define MLBCSCR15 MLB.CSCR15
-#define MLBCCBCR15 MLB.CCBCR15
-#define MLBCNBCR15 MLB.CNBCR15
-#define MLBCECR16 MLB.CECR16
-#define MLBCSCR16 MLB.CSCR16
-#define MLBCCBCR16 MLB.CCBCR16
-#define MLBCNBCR16 MLB.CNBCR16
-#define MLBCECR17 MLB.CECR17
-#define MLBCSCR17 MLB.CSCR17
-#define MLBCCBCR17 MLB.CCBCR17
-#define MLBCNBCR17 MLB.CNBCR17
-#define MLBCECR18 MLB.CECR18
-#define MLBCSCR18 MLB.CSCR18
-#define MLBCCBCR18 MLB.CCBCR18
-#define MLBCNBCR18 MLB.CNBCR18
-#define MLBCECR19 MLB.CECR19
-#define MLBCSCR19 MLB.CSCR19
-#define MLBCCBCR19 MLB.CCBCR19
-#define MLBCNBCR19 MLB.CNBCR19
-#define MLBCECR20 MLB.CECR20
-#define MLBCSCR20 MLB.CSCR20
-#define MLBCCBCR20 MLB.CCBCR20
-#define MLBCNBCR20 MLB.CNBCR20
-#define MLBCECR21 MLB.CECR21
-#define MLBCSCR21 MLB.CSCR21
-#define MLBCCBCR21 MLB.CCBCR21
-#define MLBCNBCR21 MLB.CNBCR21
-#define MLBCECR22 MLB.CECR22
-#define MLBCSCR22 MLB.CSCR22
-#define MLBCCBCR22 MLB.CCBCR22
-#define MLBCNBCR22 MLB.CNBCR22
-#define MLBCECR23 MLB.CECR23
-#define MLBCSCR23 MLB.CSCR23
-#define MLBCCBCR23 MLB.CCBCR23
-#define MLBCNBCR23 MLB.CNBCR23
-#define MLBCECR24 MLB.CECR24
-#define MLBCSCR24 MLB.CSCR24
-#define MLBCCBCR24 MLB.CCBCR24
-#define MLBCNBCR24 MLB.CNBCR24
-#define MLBCECR25 MLB.CECR25
-#define MLBCSCR25 MLB.CSCR25
-#define MLBCCBCR25 MLB.CCBCR25
-#define MLBCNBCR25 MLB.CNBCR25
-#define MLBCECR26 MLB.CECR26
-#define MLBCSCR26 MLB.CSCR26
-#define MLBCCBCR26 MLB.CCBCR26
-#define MLBCNBCR26 MLB.CNBCR26
-#define MLBCECR27 MLB.CECR27
-#define MLBCSCR27 MLB.CSCR27
-#define MLBCCBCR27 MLB.CCBCR27
-#define MLBCNBCR27 MLB.CNBCR27
-#define MLBCECR28 MLB.CECR28
-#define MLBCSCR28 MLB.CSCR28
-#define MLBCCBCR28 MLB.CCBCR28
-#define MLBCNBCR28 MLB.CNBCR28
-#define MLBCECR29 MLB.CECR29
-#define MLBCSCR29 MLB.CSCR29
-#define MLBCCBCR29 MLB.CCBCR29
-#define MLBCNBCR29 MLB.CNBCR29
-#define MLBCECR30 MLB.CECR30
-#define MLBCSCR30 MLB.CSCR30
-#define MLBCCBCR30 MLB.CCBCR30
-#define MLBCNBCR30 MLB.CNBCR30
-#define MLBLCBCR0 MLB.LCBCR0
-#define MLBLCBCR1 MLB.LCBCR1
-#define MLBLCBCR2 MLB.LCBCR2
-#define MLBLCBCR3 MLB.LCBCR3
-#define MLBLCBCR4 MLB.LCBCR4
-#define MLBLCBCR5 MLB.LCBCR5
-#define MLBLCBCR6 MLB.LCBCR6
-#define MLBLCBCR7 MLB.LCBCR7
-#define MLBLCBCR8 MLB.LCBCR8
-#define MLBLCBCR9 MLB.LCBCR9
-#define MLBLCBCR10 MLB.LCBCR10
-#define MLBLCBCR11 MLB.LCBCR11
-#define MLBLCBCR12 MLB.LCBCR12
-#define MLBLCBCR13 MLB.LCBCR13
-#define MLBLCBCR14 MLB.LCBCR14
-#define MLBLCBCR15 MLB.LCBCR15
-#define MLBLCBCR16 MLB.LCBCR16
-#define MLBLCBCR17 MLB.LCBCR17
-#define MLBLCBCR18 MLB.LCBCR18
-#define MLBLCBCR19 MLB.LCBCR19
-#define MLBLCBCR20 MLB.LCBCR20
-#define MLBLCBCR21 MLB.LCBCR21
-#define MLBLCBCR22 MLB.LCBCR22
-#define MLBLCBCR23 MLB.LCBCR23
-#define MLBLCBCR24 MLB.LCBCR24
-#define MLBLCBCR25 MLB.LCBCR25
-#define MLBLCBCR26 MLB.LCBCR26
-#define MLBLCBCR27 MLB.LCBCR27
-#define MLBLCBCR28 MLB.LCBCR28
-#define MLBLCBCR29 MLB.LCBCR29
-#define MLBLCBCR30 MLB.LCBCR30
+typedef struct st_mlb
+{
+                                                           /* MLB              */
+    volatile uint32_t  DCCR;                                   /*  DCCR            */
+    volatile uint32_t  SSCR;                                   /*  SSCR            */
+    volatile uint32_t  SDCR;                                   /*  SDCR            */
+    volatile uint32_t  SMCR;                                   /*  SMCR            */
+    volatile uint8_t   dummy156[12];                           /*                  */
+    volatile uint32_t  VCCR;                                   /*  VCCR            */
+    volatile uint32_t  SBCR;                                   /*  SBCR            */
+    volatile uint32_t  ABCR;                                   /*  ABCR            */
+    volatile uint32_t  CBCR;                                   /*  CBCR            */
+    volatile uint32_t  IBCR;                                   /*  IBCR            */
+    volatile uint32_t  CICR;                                   /*  CICR            */
+    volatile uint8_t   dummy157[12];                           /*                  */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR0;                                  /*  CECR0           */
+    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
+    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
+    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR1;                                  /*  CECR1           */
+    volatile uint32_t  CSCR1;                                  /*  CSCR1           */
+    volatile uint32_t  CCBCR1;                                 /*  CCBCR1          */
+    volatile uint32_t  CNBCR1;                                 /*  CNBCR1          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR2;                                  /*  CECR2           */
+    volatile uint32_t  CSCR2;                                  /*  CSCR2           */
+    volatile uint32_t  CCBCR2;                                 /*  CCBCR2          */
+    volatile uint32_t  CNBCR2;                                 /*  CNBCR2          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR3;                                  /*  CECR3           */
+    volatile uint32_t  CSCR3;                                  /*  CSCR3           */
+    volatile uint32_t  CCBCR3;                                 /*  CCBCR3          */
+    volatile uint32_t  CNBCR3;                                 /*  CNBCR3          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR4;                                  /*  CECR4           */
+    volatile uint32_t  CSCR4;                                  /*  CSCR4           */
+    volatile uint32_t  CCBCR4;                                 /*  CCBCR4          */
+    volatile uint32_t  CNBCR4;                                 /*  CNBCR4          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR5;                                  /*  CECR5           */
+    volatile uint32_t  CSCR5;                                  /*  CSCR5           */
+    volatile uint32_t  CCBCR5;                                 /*  CCBCR5          */
+    volatile uint32_t  CNBCR5;                                 /*  CNBCR5          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR6;                                  /*  CECR6           */
+    volatile uint32_t  CSCR6;                                  /*  CSCR6           */
+    volatile uint32_t  CCBCR6;                                 /*  CCBCR6          */
+    volatile uint32_t  CNBCR6;                                 /*  CNBCR6          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR7;                                  /*  CECR7           */
+    volatile uint32_t  CSCR7;                                  /*  CSCR7           */
+    volatile uint32_t  CCBCR7;                                 /*  CCBCR7          */
+    volatile uint32_t  CNBCR7;                                 /*  CNBCR7          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR8;                                  /*  CECR8           */
+    volatile uint32_t  CSCR8;                                  /*  CSCR8           */
+    volatile uint32_t  CCBCR8;                                 /*  CCBCR8          */
+    volatile uint32_t  CNBCR8;                                 /*  CNBCR8          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR9;                                  /*  CECR9           */
+    volatile uint32_t  CSCR9;                                  /*  CSCR9           */
+    volatile uint32_t  CCBCR9;                                 /*  CCBCR9          */
+    volatile uint32_t  CNBCR9;                                 /*  CNBCR9          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR10;                                 /*  CECR10          */
+    volatile uint32_t  CSCR10;                                 /*  CSCR10          */
+    volatile uint32_t  CCBCR10;                                /*  CCBCR10         */
+    volatile uint32_t  CNBCR10;                                /*  CNBCR10         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR11;                                 /*  CECR11          */
+    volatile uint32_t  CSCR11;                                 /*  CSCR11          */
+    volatile uint32_t  CCBCR11;                                /*  CCBCR11         */
+    volatile uint32_t  CNBCR11;                                /*  CNBCR11         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR12;                                 /*  CECR12          */
+    volatile uint32_t  CSCR12;                                 /*  CSCR12          */
+    volatile uint32_t  CCBCR12;                                /*  CCBCR12         */
+    volatile uint32_t  CNBCR12;                                /*  CNBCR12         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR13;                                 /*  CECR13          */
+    volatile uint32_t  CSCR13;                                 /*  CSCR13          */
+    volatile uint32_t  CCBCR13;                                /*  CCBCR13         */
+    volatile uint32_t  CNBCR13;                                /*  CNBCR13         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR14;                                 /*  CECR14          */
+    volatile uint32_t  CSCR14;                                 /*  CSCR14          */
+    volatile uint32_t  CCBCR14;                                /*  CCBCR14         */
+    volatile uint32_t  CNBCR14;                                /*  CNBCR14         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR15;                                 /*  CECR15          */
+    volatile uint32_t  CSCR15;                                 /*  CSCR15          */
+    volatile uint32_t  CCBCR15;                                /*  CCBCR15         */
+    volatile uint32_t  CNBCR15;                                /*  CNBCR15         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR16;                                 /*  CECR16          */
+    volatile uint32_t  CSCR16;                                 /*  CSCR16          */
+    volatile uint32_t  CCBCR16;                                /*  CCBCR16         */
+    volatile uint32_t  CNBCR16;                                /*  CNBCR16         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR17;                                 /*  CECR17          */
+    volatile uint32_t  CSCR17;                                 /*  CSCR17          */
+    volatile uint32_t  CCBCR17;                                /*  CCBCR17         */
+    volatile uint32_t  CNBCR17;                                /*  CNBCR17         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR18;                                 /*  CECR18          */
+    volatile uint32_t  CSCR18;                                 /*  CSCR18          */
+    volatile uint32_t  CCBCR18;                                /*  CCBCR18         */
+    volatile uint32_t  CNBCR18;                                /*  CNBCR18         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR19;                                 /*  CECR19          */
+    volatile uint32_t  CSCR19;                                 /*  CSCR19          */
+    volatile uint32_t  CCBCR19;                                /*  CCBCR19         */
+    volatile uint32_t  CNBCR19;                                /*  CNBCR19         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR20;                                 /*  CECR20          */
+    volatile uint32_t  CSCR20;                                 /*  CSCR20          */
+    volatile uint32_t  CCBCR20;                                /*  CCBCR20         */
+    volatile uint32_t  CNBCR20;                                /*  CNBCR20         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR21;                                 /*  CECR21          */
+    volatile uint32_t  CSCR21;                                 /*  CSCR21          */
+    volatile uint32_t  CCBCR21;                                /*  CCBCR21         */
+    volatile uint32_t  CNBCR21;                                /*  CNBCR21         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR22;                                 /*  CECR22          */
+    volatile uint32_t  CSCR22;                                 /*  CSCR22          */
+    volatile uint32_t  CCBCR22;                                /*  CCBCR22         */
+    volatile uint32_t  CNBCR22;                                /*  CNBCR22         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR23;                                 /*  CECR23          */
+    volatile uint32_t  CSCR23;                                 /*  CSCR23          */
+    volatile uint32_t  CCBCR23;                                /*  CCBCR23         */
+    volatile uint32_t  CNBCR23;                                /*  CNBCR23         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR24;                                 /*  CECR24          */
+    volatile uint32_t  CSCR24;                                 /*  CSCR24          */
+    volatile uint32_t  CCBCR24;                                /*  CCBCR24         */
+    volatile uint32_t  CNBCR24;                                /*  CNBCR24         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR25;                                 /*  CECR25          */
+    volatile uint32_t  CSCR25;                                 /*  CSCR25          */
+    volatile uint32_t  CCBCR25;                                /*  CCBCR25         */
+    volatile uint32_t  CNBCR25;                                /*  CNBCR25         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR26;                                 /*  CECR26          */
+    volatile uint32_t  CSCR26;                                 /*  CSCR26          */
+    volatile uint32_t  CCBCR26;                                /*  CCBCR26         */
+    volatile uint32_t  CNBCR26;                                /*  CNBCR26         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR27;                                 /*  CECR27          */
+    volatile uint32_t  CSCR27;                                 /*  CSCR27          */
+    volatile uint32_t  CCBCR27;                                /*  CCBCR27         */
+    volatile uint32_t  CNBCR27;                                /*  CNBCR27         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR28;                                 /*  CECR28          */
+    volatile uint32_t  CSCR28;                                 /*  CSCR28          */
+    volatile uint32_t  CCBCR28;                                /*  CCBCR28         */
+    volatile uint32_t  CNBCR28;                                /*  CNBCR28         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR29;                                 /*  CECR29          */
+    volatile uint32_t  CSCR29;                                 /*  CSCR29          */
+    volatile uint32_t  CCBCR29;                                /*  CCBCR29         */
+    volatile uint32_t  CNBCR29;                                /*  CNBCR29         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR30;                                 /*  CECR30          */
+    volatile uint32_t  CSCR30;                                 /*  CSCR30          */
+    volatile uint32_t  CCBCR30;                                /*  CCBCR30         */
+    volatile uint32_t  CNBCR30;                                /*  CNBCR30         */
+
+/* end of struct st_mlb_from_cecr0 */
+    volatile uint8_t   dummy158[80];                           /*                  */
+
+/* #define MLB_LCBCR0_COUNT (31) */
+    volatile uint32_t  LCBCR0;                                 /*  LCBCR0          */
+    volatile uint32_t  LCBCR1;                                 /*  LCBCR1          */
+    volatile uint32_t  LCBCR2;                                 /*  LCBCR2          */
+    volatile uint32_t  LCBCR3;                                 /*  LCBCR3          */
+    volatile uint32_t  LCBCR4;                                 /*  LCBCR4          */
+    volatile uint32_t  LCBCR5;                                 /*  LCBCR5          */
+    volatile uint32_t  LCBCR6;                                 /*  LCBCR6          */
+    volatile uint32_t  LCBCR7;                                 /*  LCBCR7          */
+    volatile uint32_t  LCBCR8;                                 /*  LCBCR8          */
+    volatile uint32_t  LCBCR9;                                 /*  LCBCR9          */
+    volatile uint32_t  LCBCR10;                                /*  LCBCR10         */
+    volatile uint32_t  LCBCR11;                                /*  LCBCR11         */
+    volatile uint32_t  LCBCR12;                                /*  LCBCR12         */
+    volatile uint32_t  LCBCR13;                                /*  LCBCR13         */
+    volatile uint32_t  LCBCR14;                                /*  LCBCR14         */
+    volatile uint32_t  LCBCR15;                                /*  LCBCR15         */
+    volatile uint32_t  LCBCR16;                                /*  LCBCR16         */
+    volatile uint32_t  LCBCR17;                                /*  LCBCR17         */
+    volatile uint32_t  LCBCR18;                                /*  LCBCR18         */
+    volatile uint32_t  LCBCR19;                                /*  LCBCR19         */
+    volatile uint32_t  LCBCR20;                                /*  LCBCR20         */
+    volatile uint32_t  LCBCR21;                                /*  LCBCR21         */
+    volatile uint32_t  LCBCR22;                                /*  LCBCR22         */
+    volatile uint32_t  LCBCR23;                                /*  LCBCR23         */
+    volatile uint32_t  LCBCR24;                                /*  LCBCR24         */
+    volatile uint32_t  LCBCR25;                                /*  LCBCR25         */
+    volatile uint32_t  LCBCR26;                                /*  LCBCR26         */
+    volatile uint32_t  LCBCR27;                                /*  LCBCR27         */
+    volatile uint32_t  LCBCR28;                                /*  LCBCR28         */
+    volatile uint32_t  LCBCR29;                                /*  LCBCR29         */
+    volatile uint32_t  LCBCR30;                                /*  LCBCR30         */
+} r_io_mlb_t;
+
+
+typedef struct st_mlb_from_cecr0
+{
+ 
+    volatile uint32_t  CECR0;                                  /*  CECR0           */
+    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
+    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
+    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
+} r_io_mlb_from_cecr0_t;
+
+
+/* Channel array defines of MLB (2)*/
+#ifdef  DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS
+volatile struct st_mlb_from_cecr0*  MLB_FROM_CECR0_ARRAY[ MLB_FROM_CECR0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    MLB_FROM_CECR0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS */
+/* End of channel array defines of MLB (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
 /* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,53 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : mmc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef MMC_IODEFINE_H
 #define MMC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_mmc
-{                                                          /* MMC              */
+#define MMC     (*(struct st_mmc     *)0xE804C800uL) /* MMC */
+
+
+#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH)
+#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL)
+#define MMCCE_ARG (MMC.CE_ARG)
+#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12)
+#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL)
+#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET)
+#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL)
+#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC)
+#define MMCCE_RESP3 (MMC.CE_RESP3)
+#define MMCCE_RESP2 (MMC.CE_RESP2)
+#define MMCCE_RESP1 (MMC.CE_RESP1)
+#define MMCCE_RESP0 (MMC.CE_RESP0)
+#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12)
+#define MMCCE_DATA (MMC.CE_DATA)
+#define MMCCE_INT (MMC.CE_INT)
+#define MMCCE_INT_EN (MMC.CE_INT_EN)
+#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1)
+#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2)
+#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE)
+#define MMCCE_DETECT (MMC.CE_DETECT)
+#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE)
+#define MMCCE_VERSION (MMC.CE_VERSION)
+
+#define MMC_CE_RESPn_COUNT (4)
+
+
+typedef struct st_mmc
+{
+                                                           /* MMC              */
     volatile uint16_t CE_CMD_SETH;                      /*  CE_CMD_SETH */
     volatile uint16_t CE_CMD_SETL;                      /*  CE_CMD_SETL */
     volatile uint8_t   dummy182[4];                            /*                  */
@@ -41,7 +74,8 @@
     volatile uint32_t  CE_BLOCK_SET;                           /*  CE_BLOCK_SET    */
     volatile uint32_t  CE_CLK_CTRL;                            /*  CE_CLK_CTRL     */
     volatile uint32_t  CE_BUF_ACC;                             /*  CE_BUF_ACC      */
-#define MMC_CE_RESPn_COUNT 4
+
+/* #define MMC_CE_RESPn_COUNT (4) */
     volatile uint32_t  CE_RESP3;                               /*  CE_RESP3        */
     volatile uint32_t  CE_RESP2;                               /*  CE_RESP2        */
     volatile uint32_t  CE_RESP1;                               /*  CE_RESP1        */
@@ -60,33 +94,11 @@
     volatile uint32_t  CE_ADD_MODE;                            /*  CE_ADD_MODE     */
     volatile uint8_t   dummy186[4];                            /*                  */
     volatile uint32_t  CE_VERSION;                             /*  CE_VERSION      */
-};
-
-
-#define MMC     (*(struct st_mmc     *)0xE804C800uL) /* MMC */
+} r_io_mmc_t;
 
 
-#define MMCCE_CMD_SETH MMC.CE_CMD_SETH
-#define MMCCE_CMD_SETL MMC.CE_CMD_SETL
-#define MMCCE_ARG MMC.CE_ARG
-#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12
-#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL
-#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET
-#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL
-#define MMCCE_BUF_ACC MMC.CE_BUF_ACC
-#define MMCCE_RESP3 MMC.CE_RESP3
-#define MMCCE_RESP2 MMC.CE_RESP2
-#define MMCCE_RESP1 MMC.CE_RESP1
-#define MMCCE_RESP0 MMC.CE_RESP0
-#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12
-#define MMCCE_DATA MMC.CE_DATA
-#define MMCCE_INT MMC.CE_INT
-#define MMCCE_INT_EN MMC.CE_INT_EN
-#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1
-#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2
-#define MMCCE_DMA_MODE MMC.CE_DMA_MODE
-#define MMCCE_DETECT MMC.CE_DETECT
-#define MMCCE_ADD_MODE MMC.CE_ADD_MODE
-#define MMCCE_VERSION MMC.CE_VERSION
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,108 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : mtu2_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef MTU2_IODEFINE_H
 #define MTU2_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_mtu2
-{                                                          /* MTU2             */
+#define MTU2    (*(struct st_mtu2    *)0xFCFF0000uL) /* MTU2 */
+
+
+#define MTU2TCR_2 (MTU2.TCR_2)
+#define MTU2TMDR_2 (MTU2.TMDR_2)
+#define MTU2TIOR_2 (MTU2.TIOR_2)
+#define MTU2TIER_2 (MTU2.TIER_2)
+#define MTU2TSR_2 (MTU2.TSR_2)
+#define MTU2TCNT_2 (MTU2.TCNT_2)
+#define MTU2TGRA_2 (MTU2.TGRA_2)
+#define MTU2TGRB_2 (MTU2.TGRB_2)
+#define MTU2TCR_3 (MTU2.TCR_3)
+#define MTU2TCR_4 (MTU2.TCR_4)
+#define MTU2TMDR_3 (MTU2.TMDR_3)
+#define MTU2TMDR_4 (MTU2.TMDR_4)
+#define MTU2TIORH_3 (MTU2.TIORH_3)
+#define MTU2TIORL_3 (MTU2.TIORL_3)
+#define MTU2TIORH_4 (MTU2.TIORH_4)
+#define MTU2TIORL_4 (MTU2.TIORL_4)
+#define MTU2TIER_3 (MTU2.TIER_3)
+#define MTU2TIER_4 (MTU2.TIER_4)
+#define MTU2TOER (MTU2.TOER)
+#define MTU2TGCR (MTU2.TGCR)
+#define MTU2TOCR1 (MTU2.TOCR1)
+#define MTU2TOCR2 (MTU2.TOCR2)
+#define MTU2TCNT_3 (MTU2.TCNT_3)
+#define MTU2TCNT_4 (MTU2.TCNT_4)
+#define MTU2TCDR (MTU2.TCDR)
+#define MTU2TDDR (MTU2.TDDR)
+#define MTU2TGRA_3 (MTU2.TGRA_3)
+#define MTU2TGRB_3 (MTU2.TGRB_3)
+#define MTU2TGRA_4 (MTU2.TGRA_4)
+#define MTU2TGRB_4 (MTU2.TGRB_4)
+#define MTU2TCNTS (MTU2.TCNTS)
+#define MTU2TCBR (MTU2.TCBR)
+#define MTU2TGRC_3 (MTU2.TGRC_3)
+#define MTU2TGRD_3 (MTU2.TGRD_3)
+#define MTU2TGRC_4 (MTU2.TGRC_4)
+#define MTU2TGRD_4 (MTU2.TGRD_4)
+#define MTU2TSR_3 (MTU2.TSR_3)
+#define MTU2TSR_4 (MTU2.TSR_4)
+#define MTU2TITCR (MTU2.TITCR)
+#define MTU2TITCNT (MTU2.TITCNT)
+#define MTU2TBTER (MTU2.TBTER)
+#define MTU2TDER (MTU2.TDER)
+#define MTU2TOLBR (MTU2.TOLBR)
+#define MTU2TBTM_3 (MTU2.TBTM_3)
+#define MTU2TBTM_4 (MTU2.TBTM_4)
+#define MTU2TADCR (MTU2.TADCR)
+#define MTU2TADCORA_4 (MTU2.TADCORA_4)
+#define MTU2TADCORB_4 (MTU2.TADCORB_4)
+#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4)
+#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4)
+#define MTU2TWCR (MTU2.TWCR)
+#define MTU2TSTR (MTU2.TSTR)
+#define MTU2TSYR (MTU2.TSYR)
+#define MTU2TRWER (MTU2.TRWER)
+#define MTU2TCR_0 (MTU2.TCR_0)
+#define MTU2TMDR_0 (MTU2.TMDR_0)
+#define MTU2TIORH_0 (MTU2.TIORH_0)
+#define MTU2TIORL_0 (MTU2.TIORL_0)
+#define MTU2TIER_0 (MTU2.TIER_0)
+#define MTU2TSR_0 (MTU2.TSR_0)
+#define MTU2TCNT_0 (MTU2.TCNT_0)
+#define MTU2TGRA_0 (MTU2.TGRA_0)
+#define MTU2TGRB_0 (MTU2.TGRB_0)
+#define MTU2TGRC_0 (MTU2.TGRC_0)
+#define MTU2TGRD_0 (MTU2.TGRD_0)
+#define MTU2TGRE_0 (MTU2.TGRE_0)
+#define MTU2TGRF_0 (MTU2.TGRF_0)
+#define MTU2TIER2_0 (MTU2.TIER2_0)
+#define MTU2TSR2_0 (MTU2.TSR2_0)
+#define MTU2TBTM_0 (MTU2.TBTM_0)
+#define MTU2TCR_1 (MTU2.TCR_1)
+#define MTU2TMDR_1 (MTU2.TMDR_1)
+#define MTU2TIOR_1 (MTU2.TIOR_1)
+#define MTU2TIER_1 (MTU2.TIER_1)
+#define MTU2TSR_1 (MTU2.TSR_1)
+#define MTU2TCNT_1 (MTU2.TCNT_1)
+#define MTU2TGRA_1 (MTU2.TGRA_1)
+#define MTU2TGRB_1 (MTU2.TGRB_1)
+#define MTU2TICCR (MTU2.TICCR)
+
+
+typedef struct st_mtu2
+{
+                                                           /* MTU2             */
     volatile uint8_t   TCR_2;                                  /*  TCR_2           */
     volatile uint8_t   TMDR_2;                                 /*  TMDR_2          */
     volatile uint8_t   TIOR_2;                                 /*  TIOR_2          */
@@ -128,90 +216,11 @@
     volatile uint16_t TGRB_1;                                 /*  TGRB_1          */
     volatile uint8_t   dummy536[4];                            /*                  */
     volatile uint8_t   TICCR;                                  /*  TICCR           */
-};
-
-
-#define MTU2    (*(struct st_mtu2    *)0xFCFF0000uL) /* MTU2 */
+} r_io_mtu2_t;
 
 
-#define MTU2TCR_2 MTU2.TCR_2
-#define MTU2TMDR_2 MTU2.TMDR_2
-#define MTU2TIOR_2 MTU2.TIOR_2
-#define MTU2TIER_2 MTU2.TIER_2
-#define MTU2TSR_2 MTU2.TSR_2
-#define MTU2TCNT_2 MTU2.TCNT_2
-#define MTU2TGRA_2 MTU2.TGRA_2
-#define MTU2TGRB_2 MTU2.TGRB_2
-#define MTU2TCR_3 MTU2.TCR_3
-#define MTU2TCR_4 MTU2.TCR_4
-#define MTU2TMDR_3 MTU2.TMDR_3
-#define MTU2TMDR_4 MTU2.TMDR_4
-#define MTU2TIORH_3 MTU2.TIORH_3
-#define MTU2TIORL_3 MTU2.TIORL_3
-#define MTU2TIORH_4 MTU2.TIORH_4
-#define MTU2TIORL_4 MTU2.TIORL_4
-#define MTU2TIER_3 MTU2.TIER_3
-#define MTU2TIER_4 MTU2.TIER_4
-#define MTU2TOER MTU2.TOER
-#define MTU2TGCR MTU2.TGCR
-#define MTU2TOCR1 MTU2.TOCR1
-#define MTU2TOCR2 MTU2.TOCR2
-#define MTU2TCNT_3 MTU2.TCNT_3
-#define MTU2TCNT_4 MTU2.TCNT_4
-#define MTU2TCDR MTU2.TCDR
-#define MTU2TDDR MTU2.TDDR
-#define MTU2TGRA_3 MTU2.TGRA_3
-#define MTU2TGRB_3 MTU2.TGRB_3
-#define MTU2TGRA_4 MTU2.TGRA_4
-#define MTU2TGRB_4 MTU2.TGRB_4
-#define MTU2TCNTS MTU2.TCNTS
-#define MTU2TCBR MTU2.TCBR
-#define MTU2TGRC_3 MTU2.TGRC_3
-#define MTU2TGRD_3 MTU2.TGRD_3
-#define MTU2TGRC_4 MTU2.TGRC_4
-#define MTU2TGRD_4 MTU2.TGRD_4
-#define MTU2TSR_3 MTU2.TSR_3
-#define MTU2TSR_4 MTU2.TSR_4
-#define MTU2TITCR MTU2.TITCR
-#define MTU2TITCNT MTU2.TITCNT
-#define MTU2TBTER MTU2.TBTER
-#define MTU2TDER MTU2.TDER
-#define MTU2TOLBR MTU2.TOLBR
-#define MTU2TBTM_3 MTU2.TBTM_3
-#define MTU2TBTM_4 MTU2.TBTM_4
-#define MTU2TADCR MTU2.TADCR
-#define MTU2TADCORA_4 MTU2.TADCORA_4
-#define MTU2TADCORB_4 MTU2.TADCORB_4
-#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4
-#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4
-#define MTU2TWCR MTU2.TWCR
-#define MTU2TSTR MTU2.TSTR
-#define MTU2TSYR MTU2.TSYR
-#define MTU2TRWER MTU2.TRWER
-#define MTU2TCR_0 MTU2.TCR_0
-#define MTU2TMDR_0 MTU2.TMDR_0
-#define MTU2TIORH_0 MTU2.TIORH_0
-#define MTU2TIORL_0 MTU2.TIORL_0
-#define MTU2TIER_0 MTU2.TIER_0
-#define MTU2TSR_0 MTU2.TSR_0
-#define MTU2TCNT_0 MTU2.TCNT_0
-#define MTU2TGRA_0 MTU2.TGRA_0
-#define MTU2TGRB_0 MTU2.TGRB_0
-#define MTU2TGRC_0 MTU2.TGRC_0
-#define MTU2TGRD_0 MTU2.TGRD_0
-#define MTU2TGRE_0 MTU2.TGRE_0
-#define MTU2TGRF_0 MTU2.TGRF_0
-#define MTU2TIER2_0 MTU2.TIER2_0
-#define MTU2TSR2_0 MTU2.TSR2_0
-#define MTU2TBTM_0 MTU2.TBTM_0
-#define MTU2TCR_1 MTU2.TCR_1
-#define MTU2TMDR_1 MTU2.TMDR_1
-#define MTU2TIOR_1 MTU2.TIOR_1
-#define MTU2TIER_1 MTU2.TIER_1
-#define MTU2TSR_1 MTU2.TSR_1
-#define MTU2TCNT_1 MTU2.TCNT_1
-#define MTU2TGRA_1 MTU2.TGRA_1
-#define MTU2TGRB_1 MTU2.TGRB_1
-#define MTU2TICCR MTU2.TICCR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,55 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : ostm_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef OSTM_IODEFINE_H
 #define OSTM_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_ostm
-{                                                          /* OSTM             */
+#define OSTM0   (*(struct st_ostm    *)0xFCFEC000uL) /* OSTM0 */
+#define OSTM1   (*(struct st_ostm    *)0xFCFEC400uL) /* OSTM1 */
+
+
+/* Start of channel array defines of OSTM */
+
+/* Channel array defines of OSTM */
+/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
+#define OSTM_COUNT  (2)
+#define OSTM_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &OSTM0, &OSTM1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of OSTM */
+
+
+#define OSTM0CMP (OSTM0.OSTMnCMP)
+#define OSTM0CNT (OSTM0.OSTMnCNT)
+#define OSTM0TE (OSTM0.OSTMnTE)
+#define OSTM0TS (OSTM0.OSTMnTS)
+#define OSTM0TT (OSTM0.OSTMnTT)
+#define OSTM0CTL (OSTM0.OSTMnCTL)
+#define OSTM1CMP (OSTM1.OSTMnCMP)
+#define OSTM1CNT (OSTM1.OSTMnCNT)
+#define OSTM1TE (OSTM1.OSTMnTE)
+#define OSTM1TS (OSTM1.OSTMnTS)
+#define OSTM1TT (OSTM1.OSTMnTT)
+#define OSTM1CTL (OSTM1.OSTMnCTL)
+
+
+typedef struct st_ostm
+{
+                                                           /* OSTM             */
     volatile uint32_t  OSTMnCMP;                               /*  OSTMnCMP        */
     volatile uint32_t  OSTMnCNT;                               /*  OSTMnCNT        */
     volatile uint8_t   dummy1[8];                              /*                  */
@@ -42,37 +77,21 @@
     volatile uint8_t   OSTMnTT;                                /*  OSTMnTT         */
     volatile uint8_t   dummy4[7];                              /*                  */
     volatile uint8_t   OSTMnCTL;                               /*  OSTMnCTL        */
-};
-
-
-#define OSTM0   (*(struct st_ostm    *)0xFCFEC000uL) /* OSTM0 */
-#define OSTM1   (*(struct st_ostm    *)0xFCFEC400uL) /* OSTM1 */
+} r_io_ostm_t;
 
 
-/* Start of channnel array defines of OSTM */
-
-/* Channnel array defines of OSTM */
-/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
-#define OSTM_COUNT  2
-#define OSTM_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &OSTM0, &OSTM1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of OSTM */
+/* Channel array defines of OSTM (2)*/
+#ifdef  DECLARE_OSTM_CHANNELS
+volatile struct st_ostm*  OSTM[ OSTM_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    OSTM_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_OSTM_CHANNELS */
+/* End of channel array defines of OSTM (2)*/
 
 
-#define OSTM0CMP OSTM0.OSTMnCMP
-#define OSTM0CNT OSTM0.OSTMnCNT
-#define OSTM0TE OSTM0.OSTMnTE
-#define OSTM0TS OSTM0.OSTMnTS
-#define OSTM0TT OSTM0.OSTMnTT
-#define OSTM0CTL OSTM0.OSTMnCTL
-#define OSTM1CMP OSTM1.OSTMnCMP
-#define OSTM1CNT OSTM1.OSTMnCNT
-#define OSTM1TE OSTM1.OSTMnTE
-#define OSTM1TS OSTM1.OSTMnTS
-#define OSTM1TT OSTM1.OSTMnTT
-#define OSTM1CTL OSTM1.OSTMnCTL
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,25 +18,112 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : pfv_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef PFV_IODEFINE_H
 #define PFV_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_pfv
-{                                                          /* PFV              */
+#define PFV0    (*(struct st_pfv     *)0xE8205000uL) /* PFV0 */
+#define PFV1    (*(struct st_pfv     *)0xE8205800uL) /* PFV1 */
+
+
+/* Start of channel array defines of PFV */
+
+/* Channel array defines of PFV */
+/*(Sample) value = PFV[ channel ]->PFVCR; */
+#define PFV_COUNT  (2)
+#define PFV_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &PFV0, &PFV1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of PFV */
+
+
+#define PFV0PFVCR (PFV0.PFVCR)
+#define PFV0PFVICR (PFV0.PFVICR)
+#define PFV0PFVISR (PFV0.PFVISR)
+#define PFV0PFVID0 (PFV0.PFVID0)
+#define PFV0PFVID1 (PFV0.PFVID1)
+#define PFV0PFVID2 (PFV0.PFVID2)
+#define PFV0PFVID3 (PFV0.PFVID3)
+#define PFV0PFVID4 (PFV0.PFVID4)
+#define PFV0PFVID5 (PFV0.PFVID5)
+#define PFV0PFVID6 (PFV0.PFVID6)
+#define PFV0PFVID7 (PFV0.PFVID7)
+#define PFV0PFVOD0 (PFV0.PFVOD0)
+#define PFV0PFVOD1 (PFV0.PFVOD1)
+#define PFV0PFVOD2 (PFV0.PFVOD2)
+#define PFV0PFVOD3 (PFV0.PFVOD3)
+#define PFV0PFVOD4 (PFV0.PFVOD4)
+#define PFV0PFVOD5 (PFV0.PFVOD5)
+#define PFV0PFVOD6 (PFV0.PFVOD6)
+#define PFV0PFVOD7 (PFV0.PFVOD7)
+#define PFV0PFVIFSR (PFV0.PFVIFSR)
+#define PFV0PFVOFSR (PFV0.PFVOFSR)
+#define PFV0PFVACR (PFV0.PFVACR)
+#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE)
+#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0)
+#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1)
+#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0)
+#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1)
+#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0)
+#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1)
+#define PFV0PFVSZR (PFV0.PFVSZR)
+#define PFV1PFVCR (PFV1.PFVCR)
+#define PFV1PFVICR (PFV1.PFVICR)
+#define PFV1PFVISR (PFV1.PFVISR)
+#define PFV1PFVID0 (PFV1.PFVID0)
+#define PFV1PFVID1 (PFV1.PFVID1)
+#define PFV1PFVID2 (PFV1.PFVID2)
+#define PFV1PFVID3 (PFV1.PFVID3)
+#define PFV1PFVID4 (PFV1.PFVID4)
+#define PFV1PFVID5 (PFV1.PFVID5)
+#define PFV1PFVID6 (PFV1.PFVID6)
+#define PFV1PFVID7 (PFV1.PFVID7)
+#define PFV1PFVOD0 (PFV1.PFVOD0)
+#define PFV1PFVOD1 (PFV1.PFVOD1)
+#define PFV1PFVOD2 (PFV1.PFVOD2)
+#define PFV1PFVOD3 (PFV1.PFVOD3)
+#define PFV1PFVOD4 (PFV1.PFVOD4)
+#define PFV1PFVOD5 (PFV1.PFVOD5)
+#define PFV1PFVOD6 (PFV1.PFVOD6)
+#define PFV1PFVOD7 (PFV1.PFVOD7)
+#define PFV1PFVIFSR (PFV1.PFVIFSR)
+#define PFV1PFVOFSR (PFV1.PFVOFSR)
+#define PFV1PFVACR (PFV1.PFVACR)
+#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE)
+#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0)
+#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1)
+#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0)
+#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1)
+#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0)
+#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1)
+#define PFV1PFVSZR (PFV1.PFVSZR)
+
+#define PFVID_COUNT (8)
+#define PFVOD_COUNT (8)
+
+
+typedef struct st_pfv
+{
+                                                           /* PFV              */
     volatile uint32_t  PFVCR;                                  /*  PFVCR           */
     volatile uint32_t  PFVICR;                                 /*  PFVICR          */
     volatile uint32_t  PFVISR;                                 /*  PFVISR          */
     volatile uint8_t   dummy1[20];                             /*                  */
-#define PFVID_COUNT 8
+
+/* #define PFVID_COUNT (8) */
     volatile uint32_t  PFVID0;                                 /*  PFVID0          */
     volatile uint32_t  PFVID1;                                 /*  PFVID1          */
     volatile uint32_t  PFVID2;                                 /*  PFVID2          */
@@ -45,7 +132,8 @@
     volatile uint32_t  PFVID5;                                 /*  PFVID5          */
     volatile uint32_t  PFVID6;                                 /*  PFVID6          */
     volatile uint32_t  PFVID7;                                 /*  PFVID7          */
-#define PFVOD_COUNT 8
+
+/* #define PFVOD_COUNT (8) */
     volatile uint32_t  PFVOD0;                                 /*  PFVOD0          */
     volatile uint32_t  PFVOD1;                                 /*  PFVOD1          */
     volatile uint32_t  PFVOD2;                                 /*  PFVOD2          */
@@ -66,85 +154,21 @@
     volatile uint32_t  PFV_MTX_CRR_ADJ0;                       /*  PFV_MTX_CRR_ADJ0 */
     volatile uint32_t  PFV_MTX_CRR_ADJ1;                       /*  PFV_MTX_CRR_ADJ1 */
     volatile uint32_t  PFVSZR;                                 /*  PFVSZR          */
-};
-
-
-#define PFV0    (*(struct st_pfv     *)0xE8205000uL) /* PFV0 */
-#define PFV1    (*(struct st_pfv     *)0xE8205800uL) /* PFV1 */
-
-
-/* Start of channnel array defines of PFV */
-
-/* Channnel array defines of PFV */
-/*(Sample) value = PFV[ channel ]->PFVCR; */
-#define PFV_COUNT  2
-#define PFV_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &PFV0, &PFV1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of PFV */
+} r_io_pfv_t;
 
 
-#define PFV0PFVCR PFV0.PFVCR
-#define PFV0PFVICR PFV0.PFVICR
-#define PFV0PFVISR PFV0.PFVISR
-#define PFV0PFVID0 PFV0.PFVID0
-#define PFV0PFVID1 PFV0.PFVID1
-#define PFV0PFVID2 PFV0.PFVID2
-#define PFV0PFVID3 PFV0.PFVID3
-#define PFV0PFVID4 PFV0.PFVID4
-#define PFV0PFVID5 PFV0.PFVID5
-#define PFV0PFVID6 PFV0.PFVID6
-#define PFV0PFVID7 PFV0.PFVID7
-#define PFV0PFVOD0 PFV0.PFVOD0
-#define PFV0PFVOD1 PFV0.PFVOD1
-#define PFV0PFVOD2 PFV0.PFVOD2
-#define PFV0PFVOD3 PFV0.PFVOD3
-#define PFV0PFVOD4 PFV0.PFVOD4
-#define PFV0PFVOD5 PFV0.PFVOD5
-#define PFV0PFVOD6 PFV0.PFVOD6
-#define PFV0PFVOD7 PFV0.PFVOD7
-#define PFV0PFVIFSR PFV0.PFVIFSR
-#define PFV0PFVOFSR PFV0.PFVOFSR
-#define PFV0PFVACR PFV0.PFVACR
-#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
-#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
-#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
-#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
-#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
-#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
-#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
-#define PFV0PFVSZR PFV0.PFVSZR
-#define PFV1PFVCR PFV1.PFVCR
-#define PFV1PFVICR PFV1.PFVICR
-#define PFV1PFVISR PFV1.PFVISR
-#define PFV1PFVID0 PFV1.PFVID0
-#define PFV1PFVID1 PFV1.PFVID1
-#define PFV1PFVID2 PFV1.PFVID2
-#define PFV1PFVID3 PFV1.PFVID3
-#define PFV1PFVID4 PFV1.PFVID4
-#define PFV1PFVID5 PFV1.PFVID5
-#define PFV1PFVID6 PFV1.PFVID6
-#define PFV1PFVID7 PFV1.PFVID7
-#define PFV1PFVOD0 PFV1.PFVOD0
-#define PFV1PFVOD1 PFV1.PFVOD1
-#define PFV1PFVOD2 PFV1.PFVOD2
-#define PFV1PFVOD3 PFV1.PFVOD3
-#define PFV1PFVOD4 PFV1.PFVOD4
-#define PFV1PFVOD5 PFV1.PFVOD5
-#define PFV1PFVOD6 PFV1.PFVOD6
-#define PFV1PFVOD7 PFV1.PFVOD7
-#define PFV1PFVIFSR PFV1.PFVIFSR
-#define PFV1PFVOFSR PFV1.PFVOFSR
-#define PFV1PFVACR PFV1.PFVACR
-#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
-#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
-#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
-#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
-#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
-#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
-#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
-#define PFV1PFVSZR PFV1.PFVSZR
+/* Channel array defines of PFV (2)*/
+#ifdef  DECLARE_PFV_CHANNELS
+volatile struct st_pfv*  PFV[ PFV_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    PFV_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_PFV_CHANNELS */
+/* End of channel array defines of PFV (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,83 +18,29 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : pwm_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef PWM_IODEFINE_H
 #define PWM_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-union reg16_8_t
-{
-    volatile uint16_t  UINT16;                                  /*  16-bit Access   */
-    volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
-};
-
-struct st_pwm
-{                                                          /* PWM              */
-    volatile uint8_t   dummy559[2];                            /*                  */
-    union reg16_8_t  PWBTCR;                          /*  PWBTCR      */
-    
-    volatile uint8_t   dummy560[216];                          /*                  */
-    
-/* start of struct st_pwm_common */
-    union reg16_8_t  PWCR_1;                          /*  PWCR_1      */
-    
-    volatile uint8_t   dummy561[2];                            /*                  */
-    union reg16_8_t  PWPR_1;                          /*  PWPR_1      */
-    
-    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
-    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
-    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
-    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
-    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
-/* end of struct st_pwm_common */
-    
-/* start of struct st_pwm_common */
-    union reg16_8_t  PWCR_2;                          /*  PWCR_2      */
-    
-    volatile uint8_t   dummy562[2];                            /*                  */
-    union reg16_8_t  PWPR_2;                          /*  PWPR_2      */
-    
-    volatile uint16_t PWCYR_2;                                /*  PWCYR_2         */
-    volatile uint16_t PWBFR_2A;                               /*  PWBFR_2A        */
-    volatile uint16_t PWBFR_2C;                               /*  PWBFR_2C        */
-    volatile uint16_t PWBFR_2E;                               /*  PWBFR_2E        */
-    volatile uint16_t PWBFR_2G;                               /*  PWBFR_2G        */
-/* end of struct st_pwm_common */
-};
-
-
-struct st_pwm_common
-{
-    union reg16_8_t  PWCR_1;                          /*  PWCR_1      */
-    
-    volatile uint8_t   dummy572[2];                            /*                  */
-    union reg16_8_t  PWPR_1;                          /*  PWPR_1      */
-    
-    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
-    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
-    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
-    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
-    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
-};
-
-
 #define PWM     (*(struct st_pwm     *)0xFCFF5004uL) /* PWM */
 
 
-/* Start of channnel array defines of PWM */
+/* Start of channel array defines of PWM */
 
-/* Channnel array defines of PWMn */
-/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
-#define PWMn_COUNT  2
+/* Channel array defines of PWMn */
+/*(Sample) value = PWMn[ channel ]->PWCR_1; */
+#define PWMn_COUNT  (2)
 #define PWMn_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &PWM1, &PWM2 \
@@ -102,34 +48,88 @@
 #define PWM1    (*(struct st_pwm_common *)&PWM.PWCR_1)           /* PWM1 */
 #define PWM2    (*(struct st_pwm_common *)&PWM.PWCR_2)           /* PWM2 */
 
-/* End of channnel array defines of PWM */
+/* End of channel array defines of PWM */
+
+
+#define PWMPWBTCR (PWM.PWBTCR)
+#define PWMPWCR_1 (PWM.PWCR_1)
+#define PWMPWPR_1 (PWM.PWPR_1)
+#define PWMPWCYR_1 (PWM.PWCYR_1)
+#define PWMPWBFR_1A (PWM.PWBFR_1A)
+#define PWMPWBFR_1C (PWM.PWBFR_1C)
+#define PWMPWBFR_1E (PWM.PWBFR_1E)
+#define PWMPWBFR_1G (PWM.PWBFR_1G)
+#define PWMPWCR_2 (PWM.PWCR_2)
+#define PWMPWPR_2 (PWM.PWPR_2)
+#define PWMPWCYR_2 (PWM.PWCYR_2)
+#define PWMPWBFR_2A (PWM.PWBFR_2A)
+#define PWMPWBFR_2C (PWM.PWBFR_2C)
+#define PWMPWBFR_2E (PWM.PWBFR_2E)
+#define PWMPWBFR_2G (PWM.PWBFR_2G)
 
 
-#define PWMPWBTCR PWM.PWBTCR.UINT16
-#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
-#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
-#define PWMPWCR_1 PWM.PWCR_1.UINT16
-#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
-#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
-#define PWMPWPR_1 PWM.PWPR_1.UINT16
-#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
-#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
-#define PWMPWCYR_1 PWM.PWCYR_1
-#define PWMPWBFR_1A PWM.PWBFR_1A
-#define PWMPWBFR_1C PWM.PWBFR_1C
-#define PWMPWBFR_1E PWM.PWBFR_1E
-#define PWMPWBFR_1G PWM.PWBFR_1G
-#define PWMPWCR_2 PWM.PWCR_2.UINT16
-#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
-#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
-#define PWMPWPR_2 PWM.PWPR_2.UINT16
-#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
-#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
-#define PWMPWCYR_2 PWM.PWCYR_2
-#define PWMPWBFR_2A PWM.PWBFR_2A
-#define PWMPWBFR_2C PWM.PWBFR_2C
-#define PWMPWBFR_2E PWM.PWBFR_2E
-#define PWMPWBFR_2G PWM.PWBFR_2G
+typedef struct st_pwm
+{
+                                                           /* PWM              */
+    volatile uint8_t   dummy559[2];                            /*                  */
+    volatile uint8_t   PWBTCR;                                 /*  PWBTCR          */
+    volatile uint8_t   dummy560[217];                          /*                  */
+
+/* start of struct st_pwm_common */
+    volatile uint8_t   PWCR_1;                                 /*  PWCR_1          */
+    volatile uint8_t   dummy561[3];                            /*                  */
+    volatile uint8_t   PWPR_1;                                 /*  PWPR_1          */
+    volatile uint8_t   dummy562[1];                            /*                  */
+    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
+    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
+    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
+    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
+    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
+
+/* end of struct st_pwm_common */
+
+/* start of struct st_pwm_common */
+    volatile uint8_t   PWCR_2;                                 /*  PWCR_2          */
+    volatile uint8_t   dummy563[3];                            /*                  */
+    volatile uint8_t   PWPR_2;                                 /*  PWPR_2          */
+    volatile uint8_t   dummy564[1];                            /*                  */
+    volatile uint16_t PWCYR_2;                                /*  PWCYR_2         */
+    volatile uint16_t PWBFR_2A;                               /*  PWBFR_2A        */
+    volatile uint16_t PWBFR_2C;                               /*  PWBFR_2C        */
+    volatile uint16_t PWBFR_2E;                               /*  PWBFR_2E        */
+    volatile uint16_t PWBFR_2G;                               /*  PWBFR_2G        */
+
+/* end of struct st_pwm_common */
+} r_io_pwm_t;
+
+
+typedef struct st_pwm_common
+{
+ 
+    volatile uint8_t   PWCR_1;                                 /*  PWCR_1          */
+    volatile uint8_t   dummy562[3];                            /*                  */
+    volatile uint8_t   PWPR_1;                                 /*  PWPR_1          */
+    volatile uint8_t   dummy563[1];                            /*                  */
+    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
+    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
+    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
+    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
+    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
+} r_io_pwm_common_t;
+
+
+/* Channel array defines of PWMn (2)*/
+#ifdef  DECLARE_PWMn_CHANNELS
+volatile struct st_pwm_common*  PWMn[ PWMn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    PWMn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_PWMn_CHANNELS */
+/* End of channel array defines of PWMn (2)*/
+
+
 /* <-SEC M1.10.1 */
 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,45 +18,20 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : riic_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef RIIC_IODEFINE_H
 #define RIIC_IODEFINE_H
-
-#include "reg32_t.h"
-
-struct st_riic
-{                                                          /* RIIC             */
-#define RIICnCRm_COUNT 2
-    union reg32_t  RIICnCR1;                      /*  RIICnCR1        */
-    union reg32_t  RIICnCR2;                      /*  RIICnCR2        */
-#define RIICnMRm_COUNT 3
-    union reg32_t  RIICnMR1;                      /*  RIICnMR1        */
-    union reg32_t  RIICnMR2;                      /*  RIICnMR2        */
-    union reg32_t  RIICnMR3;                      /*  RIICnMR3        */
-    union reg32_t  RIICnFER;                      /*  RIICnFER        */
-    union reg32_t  RIICnSER;                      /*  RIICnSER        */
-    union reg32_t  RIICnIER;                      /*  RIICnIER        */
-#define RIICnSRm_COUNT 2
-    union reg32_t  RIICnSR1;                      /*  RIICnSR1        */
-    union reg32_t  RIICnSR2;                      /*  RIICnSR2        */
-#define RIICnSARm_COUNT 3
-    union reg32_t  RIICnSAR0;                     /*  RIICnSAR0       */
-    union reg32_t  RIICnSAR1;                     /*  RIICnSAR1       */
-    union reg32_t  RIICnSAR2;                     /*  RIICnSAR2       */
-    union reg32_t  RIICnBRL;                      /*  RIICnBRL        */
-    union reg32_t  RIICnBRH;                      /*  RIICnBRH        */
-    union reg32_t  RIICnDRT;                      /*  RIICnDRT        */
-    union reg32_t  RIICnDRR;                      /*  RIICnDRR        */
-    
-};
-
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
 #define RIIC0   (*(struct st_riic    *)0xFCFEE000uL) /* RIIC0 */
 #define RIIC1   (*(struct st_riic    *)0xFCFEE400uL) /* RIIC1 */
@@ -64,493 +39,546 @@
 #define RIIC3   (*(struct st_riic    *)0xFCFEEC00uL) /* RIIC3 */
 
 
-/* Start of channnel array defines of RIIC */
+/* Start of channel array defines of RIIC */
 
-/* Channnel array defines of RIIC */
+/* Channel array defines of RIIC */
 /*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */
-#define RIIC_COUNT  4
+#define RIIC_COUNT  (4)
 #define RIIC_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RIIC0, &RIIC1, &RIIC2, &RIIC3 \
 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
 
-/* End of channnel array defines of RIIC */
+/* End of channel array defines of RIIC */
 
 
-#define RIIC0CR1 RIIC0.RIICnCR1.UINT32
-#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L]
-#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL]
-#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH]
-#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H]
-#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL]
-#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH]
-#define RIIC0CR2 RIIC0.RIICnCR2.UINT32
-#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L]
-#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL]
-#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH]
-#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H]
-#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL]
-#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH]
-#define RIIC0MR1 RIIC0.RIICnMR1.UINT32
-#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L]
-#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL]
-#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH]
-#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H]
-#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL]
-#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH]
-#define RIIC0MR2 RIIC0.RIICnMR2.UINT32
-#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L]
-#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL]
-#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH]
-#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H]
-#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL]
-#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH]
-#define RIIC0MR3 RIIC0.RIICnMR3.UINT32
-#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L]
-#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL]
-#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH]
-#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H]
-#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL]
-#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH]
-#define RIIC0FER RIIC0.RIICnFER.UINT32
-#define RIIC0FERL RIIC0.RIICnFER.UINT16[L]
-#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL]
-#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH]
-#define RIIC0FERH RIIC0.RIICnFER.UINT16[H]
-#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL]
-#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH]
-#define RIIC0SER RIIC0.RIICnSER.UINT32
-#define RIIC0SERL RIIC0.RIICnSER.UINT16[L]
-#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL]
-#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH]
-#define RIIC0SERH RIIC0.RIICnSER.UINT16[H]
-#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL]
-#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH]
-#define RIIC0IER RIIC0.RIICnIER.UINT32
-#define RIIC0IERL RIIC0.RIICnIER.UINT16[L]
-#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL]
-#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH]
-#define RIIC0IERH RIIC0.RIICnIER.UINT16[H]
-#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL]
-#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH]
-#define RIIC0SR1 RIIC0.RIICnSR1.UINT32
-#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L]
-#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL]
-#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH]
-#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H]
-#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL]
-#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH]
-#define RIIC0SR2 RIIC0.RIICnSR2.UINT32
-#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L]
-#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL]
-#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH]
-#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H]
-#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL]
-#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH]
-#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32
-#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L]
-#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL]
-#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH]
-#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H]
-#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL]
-#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH]
-#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32
-#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L]
-#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL]
-#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH]
-#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H]
-#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL]
-#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH]
-#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32
-#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L]
-#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL]
-#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH]
-#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H]
-#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL]
-#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH]
-#define RIIC0BRL RIIC0.RIICnBRL.UINT32
-#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L]
-#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL]
-#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH]
-#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H]
-#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL]
-#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH]
-#define RIIC0BRH RIIC0.RIICnBRH.UINT32
-#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L]
-#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL]
-#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH]
-#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H]
-#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL]
-#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH]
-#define RIIC0DRT RIIC0.RIICnDRT.UINT32
-#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L]
-#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL]
-#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH]
-#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H]
-#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL]
-#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH]
-#define RIIC0DRR RIIC0.RIICnDRR.UINT32
-#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L]
-#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL]
-#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH]
-#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H]
-#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL]
-#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH]
-#define RIIC1CR1 RIIC1.RIICnCR1.UINT32
-#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L]
-#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL]
-#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH]
-#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H]
-#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL]
-#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH]
-#define RIIC1CR2 RIIC1.RIICnCR2.UINT32
-#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L]
-#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL]
-#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH]
-#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H]
-#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL]
-#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH]
-#define RIIC1MR1 RIIC1.RIICnMR1.UINT32
-#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L]
-#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL]
-#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH]
-#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H]
-#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL]
-#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH]
-#define RIIC1MR2 RIIC1.RIICnMR2.UINT32
-#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L]
-#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL]
-#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH]
-#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H]
-#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL]
-#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH]
-#define RIIC1MR3 RIIC1.RIICnMR3.UINT32
-#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L]
-#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL]
-#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH]
-#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H]
-#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL]
-#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH]
-#define RIIC1FER RIIC1.RIICnFER.UINT32
-#define RIIC1FERL RIIC1.RIICnFER.UINT16[L]
-#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL]
-#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH]
-#define RIIC1FERH RIIC1.RIICnFER.UINT16[H]
-#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL]
-#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH]
-#define RIIC1SER RIIC1.RIICnSER.UINT32
-#define RIIC1SERL RIIC1.RIICnSER.UINT16[L]
-#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL]
-#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH]
-#define RIIC1SERH RIIC1.RIICnSER.UINT16[H]
-#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL]
-#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH]
-#define RIIC1IER RIIC1.RIICnIER.UINT32
-#define RIIC1IERL RIIC1.RIICnIER.UINT16[L]
-#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL]
-#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH]
-#define RIIC1IERH RIIC1.RIICnIER.UINT16[H]
-#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL]
-#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH]
-#define RIIC1SR1 RIIC1.RIICnSR1.UINT32
-#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L]
-#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL]
-#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH]
-#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H]
-#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL]
-#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH]
-#define RIIC1SR2 RIIC1.RIICnSR2.UINT32
-#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L]
-#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL]
-#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH]
-#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H]
-#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL]
-#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH]
-#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32
-#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L]
-#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL]
-#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH]
-#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H]
-#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL]
-#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH]
-#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32
-#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L]
-#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL]
-#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH]
-#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H]
-#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL]
-#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH]
-#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32
-#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L]
-#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL]
-#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH]
-#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H]
-#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL]
-#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH]
-#define RIIC1BRL RIIC1.RIICnBRL.UINT32
-#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L]
-#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL]
-#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH]
-#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H]
-#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL]
-#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH]
-#define RIIC1BRH RIIC1.RIICnBRH.UINT32
-#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L]
-#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL]
-#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH]
-#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H]
-#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL]
-#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH]
-#define RIIC1DRT RIIC1.RIICnDRT.UINT32
-#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L]
-#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL]
-#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH]
-#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H]
-#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL]
-#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH]
-#define RIIC1DRR RIIC1.RIICnDRR.UINT32
-#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L]
-#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL]
-#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH]
-#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H]
-#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL]
-#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH]
-#define RIIC2CR1 RIIC2.RIICnCR1.UINT32
-#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L]
-#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL]
-#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH]
-#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H]
-#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL]
-#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH]
-#define RIIC2CR2 RIIC2.RIICnCR2.UINT32
-#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L]
-#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL]
-#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH]
-#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H]
-#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL]
-#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH]
-#define RIIC2MR1 RIIC2.RIICnMR1.UINT32
-#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L]
-#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL]
-#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH]
-#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H]
-#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL]
-#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH]
-#define RIIC2MR2 RIIC2.RIICnMR2.UINT32
-#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L]
-#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL]
-#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH]
-#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H]
-#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL]
-#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH]
-#define RIIC2MR3 RIIC2.RIICnMR3.UINT32
-#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L]
-#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL]
-#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH]
-#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H]
-#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL]
-#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH]
-#define RIIC2FER RIIC2.RIICnFER.UINT32
-#define RIIC2FERL RIIC2.RIICnFER.UINT16[L]
-#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL]
-#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH]
-#define RIIC2FERH RIIC2.RIICnFER.UINT16[H]
-#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL]
-#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH]
-#define RIIC2SER RIIC2.RIICnSER.UINT32
-#define RIIC2SERL RIIC2.RIICnSER.UINT16[L]
-#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL]
-#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH]
-#define RIIC2SERH RIIC2.RIICnSER.UINT16[H]
-#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL]
-#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH]
-#define RIIC2IER RIIC2.RIICnIER.UINT32
-#define RIIC2IERL RIIC2.RIICnIER.UINT16[L]
-#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL]
-#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH]
-#define RIIC2IERH RIIC2.RIICnIER.UINT16[H]
-#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL]
-#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH]
-#define RIIC2SR1 RIIC2.RIICnSR1.UINT32
-#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L]
-#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL]
-#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH]
-#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H]
-#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL]
-#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH]
-#define RIIC2SR2 RIIC2.RIICnSR2.UINT32
-#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L]
-#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL]
-#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH]
-#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H]
-#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL]
-#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH]
-#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32
-#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L]
-#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL]
-#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH]
-#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H]
-#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL]
-#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH]
-#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32
-#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L]
-#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL]
-#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH]
-#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H]
-#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL]
-#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH]
-#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32
-#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L]
-#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL]
-#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH]
-#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H]
-#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL]
-#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH]
-#define RIIC2BRL RIIC2.RIICnBRL.UINT32
-#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L]
-#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL]
-#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH]
-#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H]
-#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL]
-#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH]
-#define RIIC2BRH RIIC2.RIICnBRH.UINT32
-#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L]
-#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL]
-#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH]
-#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H]
-#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL]
-#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH]
-#define RIIC2DRT RIIC2.RIICnDRT.UINT32
-#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L]
-#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL]
-#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH]
-#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H]
-#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL]
-#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH]
-#define RIIC2DRR RIIC2.RIICnDRR.UINT32
-#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L]
-#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL]
-#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH]
-#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H]
-#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL]
-#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH]
-#define RIIC3CR1 RIIC3.RIICnCR1.UINT32
-#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L]
-#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL]
-#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH]
-#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H]
-#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL]
-#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH]
-#define RIIC3CR2 RIIC3.RIICnCR2.UINT32
-#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L]
-#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL]
-#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH]
-#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H]
-#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL]
-#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH]
-#define RIIC3MR1 RIIC3.RIICnMR1.UINT32
-#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L]
-#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL]
-#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH]
-#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H]
-#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL]
-#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH]
-#define RIIC3MR2 RIIC3.RIICnMR2.UINT32
-#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L]
-#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL]
-#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH]
-#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H]
-#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL]
-#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH]
-#define RIIC3MR3 RIIC3.RIICnMR3.UINT32
-#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L]
-#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL]
-#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH]
-#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H]
-#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL]
-#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH]
-#define RIIC3FER RIIC3.RIICnFER.UINT32
-#define RIIC3FERL RIIC3.RIICnFER.UINT16[L]
-#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL]
-#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH]
-#define RIIC3FERH RIIC3.RIICnFER.UINT16[H]
-#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL]
-#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH]
-#define RIIC3SER RIIC3.RIICnSER.UINT32
-#define RIIC3SERL RIIC3.RIICnSER.UINT16[L]
-#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL]
-#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH]
-#define RIIC3SERH RIIC3.RIICnSER.UINT16[H]
-#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL]
-#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH]
-#define RIIC3IER RIIC3.RIICnIER.UINT32
-#define RIIC3IERL RIIC3.RIICnIER.UINT16[L]
-#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL]
-#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH]
-#define RIIC3IERH RIIC3.RIICnIER.UINT16[H]
-#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL]
-#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH]
-#define RIIC3SR1 RIIC3.RIICnSR1.UINT32
-#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L]
-#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL]
-#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH]
-#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H]
-#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL]
-#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH]
-#define RIIC3SR2 RIIC3.RIICnSR2.UINT32
-#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L]
-#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL]
-#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH]
-#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H]
-#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL]
-#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH]
-#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32
-#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L]
-#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL]
-#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH]
-#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H]
-#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL]
-#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH]
-#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32
-#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L]
-#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL]
-#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH]
-#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H]
-#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL]
-#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH]
-#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32
-#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L]
-#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL]
-#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH]
-#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H]
-#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL]
-#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH]
-#define RIIC3BRL RIIC3.RIICnBRL.UINT32
-#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L]
-#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL]
-#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH]
-#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H]
-#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL]
-#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH]
-#define RIIC3BRH RIIC3.RIICnBRH.UINT32
-#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L]
-#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL]
-#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH]
-#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H]
-#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL]
-#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH]
-#define RIIC3DRT RIIC3.RIICnDRT.UINT32
-#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L]
-#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL]
-#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH]
-#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H]
-#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL]
-#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH]
-#define RIIC3DRR RIIC3.RIICnDRR.UINT32
-#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L]
-#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL]
-#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH]
-#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H]
-#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL]
-#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH]
+#define RIIC0CR1 (RIIC0.RIICnCR1.UINT32)
+#define RIIC0CR1L (RIIC0.RIICnCR1.UINT16[R_IO_L])
+#define RIIC0CR1LL (RIIC0.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC0CR1LH (RIIC0.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC0CR1H (RIIC0.RIICnCR1.UINT16[R_IO_H])
+#define RIIC0CR1HL (RIIC0.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC0CR1HH (RIIC0.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC0CR2 (RIIC0.RIICnCR2.UINT32)
+#define RIIC0CR2L (RIIC0.RIICnCR2.UINT16[R_IO_L])
+#define RIIC0CR2LL (RIIC0.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC0CR2LH (RIIC0.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC0CR2H (RIIC0.RIICnCR2.UINT16[R_IO_H])
+#define RIIC0CR2HL (RIIC0.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC0CR2HH (RIIC0.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC0MR1 (RIIC0.RIICnMR1.UINT32)
+#define RIIC0MR1L (RIIC0.RIICnMR1.UINT16[R_IO_L])
+#define RIIC0MR1LL (RIIC0.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC0MR1LH (RIIC0.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC0MR1H (RIIC0.RIICnMR1.UINT16[R_IO_H])
+#define RIIC0MR1HL (RIIC0.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC0MR1HH (RIIC0.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC0MR2 (RIIC0.RIICnMR2.UINT32)
+#define RIIC0MR2L (RIIC0.RIICnMR2.UINT16[R_IO_L])
+#define RIIC0MR2LL (RIIC0.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC0MR2LH (RIIC0.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC0MR2H (RIIC0.RIICnMR2.UINT16[R_IO_H])
+#define RIIC0MR2HL (RIIC0.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC0MR2HH (RIIC0.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC0MR3 (RIIC0.RIICnMR3.UINT32)
+#define RIIC0MR3L (RIIC0.RIICnMR3.UINT16[R_IO_L])
+#define RIIC0MR3LL (RIIC0.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC0MR3LH (RIIC0.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC0MR3H (RIIC0.RIICnMR3.UINT16[R_IO_H])
+#define RIIC0MR3HL (RIIC0.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC0MR3HH (RIIC0.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC0FER (RIIC0.RIICnFER.UINT32)
+#define RIIC0FERL (RIIC0.RIICnFER.UINT16[R_IO_L])
+#define RIIC0FERLL (RIIC0.RIICnFER.UINT8[R_IO_LL])
+#define RIIC0FERLH (RIIC0.RIICnFER.UINT8[R_IO_LH])
+#define RIIC0FERH (RIIC0.RIICnFER.UINT16[R_IO_H])
+#define RIIC0FERHL (RIIC0.RIICnFER.UINT8[R_IO_HL])
+#define RIIC0FERHH (RIIC0.RIICnFER.UINT8[R_IO_HH])
+#define RIIC0SER (RIIC0.RIICnSER.UINT32)
+#define RIIC0SERL (RIIC0.RIICnSER.UINT16[R_IO_L])
+#define RIIC0SERLL (RIIC0.RIICnSER.UINT8[R_IO_LL])
+#define RIIC0SERLH (RIIC0.RIICnSER.UINT8[R_IO_LH])
+#define RIIC0SERH (RIIC0.RIICnSER.UINT16[R_IO_H])
+#define RIIC0SERHL (RIIC0.RIICnSER.UINT8[R_IO_HL])
+#define RIIC0SERHH (RIIC0.RIICnSER.UINT8[R_IO_HH])
+#define RIIC0IER (RIIC0.RIICnIER.UINT32)
+#define RIIC0IERL (RIIC0.RIICnIER.UINT16[R_IO_L])
+#define RIIC0IERLL (RIIC0.RIICnIER.UINT8[R_IO_LL])
+#define RIIC0IERLH (RIIC0.RIICnIER.UINT8[R_IO_LH])
+#define RIIC0IERH (RIIC0.RIICnIER.UINT16[R_IO_H])
+#define RIIC0IERHL (RIIC0.RIICnIER.UINT8[R_IO_HL])
+#define RIIC0IERHH (RIIC0.RIICnIER.UINT8[R_IO_HH])
+#define RIIC0SR1 (RIIC0.RIICnSR1.UINT32)
+#define RIIC0SR1L (RIIC0.RIICnSR1.UINT16[R_IO_L])
+#define RIIC0SR1LL (RIIC0.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC0SR1LH (RIIC0.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC0SR1H (RIIC0.RIICnSR1.UINT16[R_IO_H])
+#define RIIC0SR1HL (RIIC0.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC0SR1HH (RIIC0.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC0SR2 (RIIC0.RIICnSR2.UINT32)
+#define RIIC0SR2L (RIIC0.RIICnSR2.UINT16[R_IO_L])
+#define RIIC0SR2LL (RIIC0.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC0SR2LH (RIIC0.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC0SR2H (RIIC0.RIICnSR2.UINT16[R_IO_H])
+#define RIIC0SR2HL (RIIC0.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC0SR2HH (RIIC0.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC0SAR0 (RIIC0.RIICnSAR0.UINT32)
+#define RIIC0SAR0L (RIIC0.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC0SAR0LL (RIIC0.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC0SAR0LH (RIIC0.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC0SAR0H (RIIC0.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC0SAR0HL (RIIC0.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC0SAR0HH (RIIC0.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC0SAR1 (RIIC0.RIICnSAR1.UINT32)
+#define RIIC0SAR1L (RIIC0.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC0SAR1LL (RIIC0.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC0SAR1LH (RIIC0.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC0SAR1H (RIIC0.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC0SAR1HL (RIIC0.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC0SAR1HH (RIIC0.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC0SAR2 (RIIC0.RIICnSAR2.UINT32)
+#define RIIC0SAR2L (RIIC0.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC0SAR2LL (RIIC0.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC0SAR2LH (RIIC0.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC0SAR2H (RIIC0.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC0SAR2HL (RIIC0.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC0SAR2HH (RIIC0.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC0BRL (RIIC0.RIICnBRL.UINT32)
+#define RIIC0BRLL (RIIC0.RIICnBRL.UINT16[R_IO_L])
+#define RIIC0BRLLL (RIIC0.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC0BRLLH (RIIC0.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC0BRLH (RIIC0.RIICnBRL.UINT16[R_IO_H])
+#define RIIC0BRLHL (RIIC0.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC0BRLHH (RIIC0.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC0BRH (RIIC0.RIICnBRH.UINT32)
+#define RIIC0BRHL (RIIC0.RIICnBRH.UINT16[R_IO_L])
+#define RIIC0BRHLL (RIIC0.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC0BRHLH (RIIC0.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC0BRHH (RIIC0.RIICnBRH.UINT16[R_IO_H])
+#define RIIC0BRHHL (RIIC0.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC0BRHHH (RIIC0.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC0DRT (RIIC0.RIICnDRT.UINT32)
+#define RIIC0DRTL (RIIC0.RIICnDRT.UINT16[R_IO_L])
+#define RIIC0DRTLL (RIIC0.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC0DRTLH (RIIC0.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC0DRTH (RIIC0.RIICnDRT.UINT16[R_IO_H])
+#define RIIC0DRTHL (RIIC0.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC0DRTHH (RIIC0.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC0DRR (RIIC0.RIICnDRR.UINT32)
+#define RIIC0DRRL (RIIC0.RIICnDRR.UINT16[R_IO_L])
+#define RIIC0DRRLL (RIIC0.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC0DRRLH (RIIC0.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC0DRRH (RIIC0.RIICnDRR.UINT16[R_IO_H])
+#define RIIC0DRRHL (RIIC0.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC0DRRHH (RIIC0.RIICnDRR.UINT8[R_IO_HH])
+#define RIIC1CR1 (RIIC1.RIICnCR1.UINT32)
+#define RIIC1CR1L (RIIC1.RIICnCR1.UINT16[R_IO_L])
+#define RIIC1CR1LL (RIIC1.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC1CR1LH (RIIC1.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC1CR1H (RIIC1.RIICnCR1.UINT16[R_IO_H])
+#define RIIC1CR1HL (RIIC1.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC1CR1HH (RIIC1.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC1CR2 (RIIC1.RIICnCR2.UINT32)
+#define RIIC1CR2L (RIIC1.RIICnCR2.UINT16[R_IO_L])
+#define RIIC1CR2LL (RIIC1.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC1CR2LH (RIIC1.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC1CR2H (RIIC1.RIICnCR2.UINT16[R_IO_H])
+#define RIIC1CR2HL (RIIC1.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC1CR2HH (RIIC1.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC1MR1 (RIIC1.RIICnMR1.UINT32)
+#define RIIC1MR1L (RIIC1.RIICnMR1.UINT16[R_IO_L])
+#define RIIC1MR1LL (RIIC1.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC1MR1LH (RIIC1.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC1MR1H (RIIC1.RIICnMR1.UINT16[R_IO_H])
+#define RIIC1MR1HL (RIIC1.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC1MR1HH (RIIC1.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC1MR2 (RIIC1.RIICnMR2.UINT32)
+#define RIIC1MR2L (RIIC1.RIICnMR2.UINT16[R_IO_L])
+#define RIIC1MR2LL (RIIC1.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC1MR2LH (RIIC1.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC1MR2H (RIIC1.RIICnMR2.UINT16[R_IO_H])
+#define RIIC1MR2HL (RIIC1.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC1MR2HH (RIIC1.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC1MR3 (RIIC1.RIICnMR3.UINT32)
+#define RIIC1MR3L (RIIC1.RIICnMR3.UINT16[R_IO_L])
+#define RIIC1MR3LL (RIIC1.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC1MR3LH (RIIC1.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC1MR3H (RIIC1.RIICnMR3.UINT16[R_IO_H])
+#define RIIC1MR3HL (RIIC1.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC1MR3HH (RIIC1.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC1FER (RIIC1.RIICnFER.UINT32)
+#define RIIC1FERL (RIIC1.RIICnFER.UINT16[R_IO_L])
+#define RIIC1FERLL (RIIC1.RIICnFER.UINT8[R_IO_LL])
+#define RIIC1FERLH (RIIC1.RIICnFER.UINT8[R_IO_LH])
+#define RIIC1FERH (RIIC1.RIICnFER.UINT16[R_IO_H])
+#define RIIC1FERHL (RIIC1.RIICnFER.UINT8[R_IO_HL])
+#define RIIC1FERHH (RIIC1.RIICnFER.UINT8[R_IO_HH])
+#define RIIC1SER (RIIC1.RIICnSER.UINT32)
+#define RIIC1SERL (RIIC1.RIICnSER.UINT16[R_IO_L])
+#define RIIC1SERLL (RIIC1.RIICnSER.UINT8[R_IO_LL])
+#define RIIC1SERLH (RIIC1.RIICnSER.UINT8[R_IO_LH])
+#define RIIC1SERH (RIIC1.RIICnSER.UINT16[R_IO_H])
+#define RIIC1SERHL (RIIC1.RIICnSER.UINT8[R_IO_HL])
+#define RIIC1SERHH (RIIC1.RIICnSER.UINT8[R_IO_HH])
+#define RIIC1IER (RIIC1.RIICnIER.UINT32)
+#define RIIC1IERL (RIIC1.RIICnIER.UINT16[R_IO_L])
+#define RIIC1IERLL (RIIC1.RIICnIER.UINT8[R_IO_LL])
+#define RIIC1IERLH (RIIC1.RIICnIER.UINT8[R_IO_LH])
+#define RIIC1IERH (RIIC1.RIICnIER.UINT16[R_IO_H])
+#define RIIC1IERHL (RIIC1.RIICnIER.UINT8[R_IO_HL])
+#define RIIC1IERHH (RIIC1.RIICnIER.UINT8[R_IO_HH])
+#define RIIC1SR1 (RIIC1.RIICnSR1.UINT32)
+#define RIIC1SR1L (RIIC1.RIICnSR1.UINT16[R_IO_L])
+#define RIIC1SR1LL (RIIC1.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC1SR1LH (RIIC1.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC1SR1H (RIIC1.RIICnSR1.UINT16[R_IO_H])
+#define RIIC1SR1HL (RIIC1.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC1SR1HH (RIIC1.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC1SR2 (RIIC1.RIICnSR2.UINT32)
+#define RIIC1SR2L (RIIC1.RIICnSR2.UINT16[R_IO_L])
+#define RIIC1SR2LL (RIIC1.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC1SR2LH (RIIC1.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC1SR2H (RIIC1.RIICnSR2.UINT16[R_IO_H])
+#define RIIC1SR2HL (RIIC1.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC1SR2HH (RIIC1.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC1SAR0 (RIIC1.RIICnSAR0.UINT32)
+#define RIIC1SAR0L (RIIC1.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC1SAR0LL (RIIC1.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC1SAR0LH (RIIC1.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC1SAR0H (RIIC1.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC1SAR0HL (RIIC1.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC1SAR0HH (RIIC1.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC1SAR1 (RIIC1.RIICnSAR1.UINT32)
+#define RIIC1SAR1L (RIIC1.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC1SAR1LL (RIIC1.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC1SAR1LH (RIIC1.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC1SAR1H (RIIC1.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC1SAR1HL (RIIC1.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC1SAR1HH (RIIC1.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC1SAR2 (RIIC1.RIICnSAR2.UINT32)
+#define RIIC1SAR2L (RIIC1.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC1SAR2LL (RIIC1.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC1SAR2LH (RIIC1.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC1SAR2H (RIIC1.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC1SAR2HL (RIIC1.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC1SAR2HH (RIIC1.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC1BRL (RIIC1.RIICnBRL.UINT32)
+#define RIIC1BRLL (RIIC1.RIICnBRL.UINT16[R_IO_L])
+#define RIIC1BRLLL (RIIC1.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC1BRLLH (RIIC1.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC1BRLH (RIIC1.RIICnBRL.UINT16[R_IO_H])
+#define RIIC1BRLHL (RIIC1.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC1BRLHH (RIIC1.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC1BRH (RIIC1.RIICnBRH.UINT32)
+#define RIIC1BRHL (RIIC1.RIICnBRH.UINT16[R_IO_L])
+#define RIIC1BRHLL (RIIC1.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC1BRHLH (RIIC1.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC1BRHH (RIIC1.RIICnBRH.UINT16[R_IO_H])
+#define RIIC1BRHHL (RIIC1.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC1BRHHH (RIIC1.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC1DRT (RIIC1.RIICnDRT.UINT32)
+#define RIIC1DRTL (RIIC1.RIICnDRT.UINT16[R_IO_L])
+#define RIIC1DRTLL (RIIC1.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC1DRTLH (RIIC1.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC1DRTH (RIIC1.RIICnDRT.UINT16[R_IO_H])
+#define RIIC1DRTHL (RIIC1.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC1DRTHH (RIIC1.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC1DRR (RIIC1.RIICnDRR.UINT32)
+#define RIIC1DRRL (RIIC1.RIICnDRR.UINT16[R_IO_L])
+#define RIIC1DRRLL (RIIC1.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC1DRRLH (RIIC1.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC1DRRH (RIIC1.RIICnDRR.UINT16[R_IO_H])
+#define RIIC1DRRHL (RIIC1.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC1DRRHH (RIIC1.RIICnDRR.UINT8[R_IO_HH])
+#define RIIC2CR1 (RIIC2.RIICnCR1.UINT32)
+#define RIIC2CR1L (RIIC2.RIICnCR1.UINT16[R_IO_L])
+#define RIIC2CR1LL (RIIC2.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC2CR1LH (RIIC2.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC2CR1H (RIIC2.RIICnCR1.UINT16[R_IO_H])
+#define RIIC2CR1HL (RIIC2.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC2CR1HH (RIIC2.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC2CR2 (RIIC2.RIICnCR2.UINT32)
+#define RIIC2CR2L (RIIC2.RIICnCR2.UINT16[R_IO_L])
+#define RIIC2CR2LL (RIIC2.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC2CR2LH (RIIC2.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC2CR2H (RIIC2.RIICnCR2.UINT16[R_IO_H])
+#define RIIC2CR2HL (RIIC2.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC2CR2HH (RIIC2.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC2MR1 (RIIC2.RIICnMR1.UINT32)
+#define RIIC2MR1L (RIIC2.RIICnMR1.UINT16[R_IO_L])
+#define RIIC2MR1LL (RIIC2.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC2MR1LH (RIIC2.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC2MR1H (RIIC2.RIICnMR1.UINT16[R_IO_H])
+#define RIIC2MR1HL (RIIC2.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC2MR1HH (RIIC2.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC2MR2 (RIIC2.RIICnMR2.UINT32)
+#define RIIC2MR2L (RIIC2.RIICnMR2.UINT16[R_IO_L])
+#define RIIC2MR2LL (RIIC2.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC2MR2LH (RIIC2.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC2MR2H (RIIC2.RIICnMR2.UINT16[R_IO_H])
+#define RIIC2MR2HL (RIIC2.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC2MR2HH (RIIC2.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC2MR3 (RIIC2.RIICnMR3.UINT32)
+#define RIIC2MR3L (RIIC2.RIICnMR3.UINT16[R_IO_L])
+#define RIIC2MR3LL (RIIC2.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC2MR3LH (RIIC2.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC2MR3H (RIIC2.RIICnMR3.UINT16[R_IO_H])
+#define RIIC2MR3HL (RIIC2.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC2MR3HH (RIIC2.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC2FER (RIIC2.RIICnFER.UINT32)
+#define RIIC2FERL (RIIC2.RIICnFER.UINT16[R_IO_L])
+#define RIIC2FERLL (RIIC2.RIICnFER.UINT8[R_IO_LL])
+#define RIIC2FERLH (RIIC2.RIICnFER.UINT8[R_IO_LH])
+#define RIIC2FERH (RIIC2.RIICnFER.UINT16[R_IO_H])
+#define RIIC2FERHL (RIIC2.RIICnFER.UINT8[R_IO_HL])
+#define RIIC2FERHH (RIIC2.RIICnFER.UINT8[R_IO_HH])
+#define RIIC2SER (RIIC2.RIICnSER.UINT32)
+#define RIIC2SERL (RIIC2.RIICnSER.UINT16[R_IO_L])
+#define RIIC2SERLL (RIIC2.RIICnSER.UINT8[R_IO_LL])
+#define RIIC2SERLH (RIIC2.RIICnSER.UINT8[R_IO_LH])
+#define RIIC2SERH (RIIC2.RIICnSER.UINT16[R_IO_H])
+#define RIIC2SERHL (RIIC2.RIICnSER.UINT8[R_IO_HL])
+#define RIIC2SERHH (RIIC2.RIICnSER.UINT8[R_IO_HH])
+#define RIIC2IER (RIIC2.RIICnIER.UINT32)
+#define RIIC2IERL (RIIC2.RIICnIER.UINT16[R_IO_L])
+#define RIIC2IERLL (RIIC2.RIICnIER.UINT8[R_IO_LL])
+#define RIIC2IERLH (RIIC2.RIICnIER.UINT8[R_IO_LH])
+#define RIIC2IERH (RIIC2.RIICnIER.UINT16[R_IO_H])
+#define RIIC2IERHL (RIIC2.RIICnIER.UINT8[R_IO_HL])
+#define RIIC2IERHH (RIIC2.RIICnIER.UINT8[R_IO_HH])
+#define RIIC2SR1 (RIIC2.RIICnSR1.UINT32)
+#define RIIC2SR1L (RIIC2.RIICnSR1.UINT16[R_IO_L])
+#define RIIC2SR1LL (RIIC2.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC2SR1LH (RIIC2.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC2SR1H (RIIC2.RIICnSR1.UINT16[R_IO_H])
+#define RIIC2SR1HL (RIIC2.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC2SR1HH (RIIC2.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC2SR2 (RIIC2.RIICnSR2.UINT32)
+#define RIIC2SR2L (RIIC2.RIICnSR2.UINT16[R_IO_L])
+#define RIIC2SR2LL (RIIC2.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC2SR2LH (RIIC2.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC2SR2H (RIIC2.RIICnSR2.UINT16[R_IO_H])
+#define RIIC2SR2HL (RIIC2.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC2SR2HH (RIIC2.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC2SAR0 (RIIC2.RIICnSAR0.UINT32)
+#define RIIC2SAR0L (RIIC2.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC2SAR0LL (RIIC2.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC2SAR0LH (RIIC2.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC2SAR0H (RIIC2.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC2SAR0HL (RIIC2.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC2SAR0HH (RIIC2.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC2SAR1 (RIIC2.RIICnSAR1.UINT32)
+#define RIIC2SAR1L (RIIC2.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC2SAR1LL (RIIC2.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC2SAR1LH (RIIC2.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC2SAR1H (RIIC2.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC2SAR1HL (RIIC2.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC2SAR1HH (RIIC2.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC2SAR2 (RIIC2.RIICnSAR2.UINT32)
+#define RIIC2SAR2L (RIIC2.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC2SAR2LL (RIIC2.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC2SAR2LH (RIIC2.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC2SAR2H (RIIC2.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC2SAR2HL (RIIC2.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC2SAR2HH (RIIC2.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC2BRL (RIIC2.RIICnBRL.UINT32)
+#define RIIC2BRLL (RIIC2.RIICnBRL.UINT16[R_IO_L])
+#define RIIC2BRLLL (RIIC2.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC2BRLLH (RIIC2.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC2BRLH (RIIC2.RIICnBRL.UINT16[R_IO_H])
+#define RIIC2BRLHL (RIIC2.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC2BRLHH (RIIC2.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC2BRH (RIIC2.RIICnBRH.UINT32)
+#define RIIC2BRHL (RIIC2.RIICnBRH.UINT16[R_IO_L])
+#define RIIC2BRHLL (RIIC2.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC2BRHLH (RIIC2.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC2BRHH (RIIC2.RIICnBRH.UINT16[R_IO_H])
+#define RIIC2BRHHL (RIIC2.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC2BRHHH (RIIC2.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC2DRT (RIIC2.RIICnDRT.UINT32)
+#define RIIC2DRTL (RIIC2.RIICnDRT.UINT16[R_IO_L])
+#define RIIC2DRTLL (RIIC2.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC2DRTLH (RIIC2.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC2DRTH (RIIC2.RIICnDRT.UINT16[R_IO_H])
+#define RIIC2DRTHL (RIIC2.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC2DRTHH (RIIC2.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC2DRR (RIIC2.RIICnDRR.UINT32)
+#define RIIC2DRRL (RIIC2.RIICnDRR.UINT16[R_IO_L])
+#define RIIC2DRRLL (RIIC2.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC2DRRLH (RIIC2.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC2DRRH (RIIC2.RIICnDRR.UINT16[R_IO_H])
+#define RIIC2DRRHL (RIIC2.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC2DRRHH (RIIC2.RIICnDRR.UINT8[R_IO_HH])
+#define RIIC3CR1 (RIIC3.RIICnCR1.UINT32)
+#define RIIC3CR1L (RIIC3.RIICnCR1.UINT16[R_IO_L])
+#define RIIC3CR1LL (RIIC3.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC3CR1LH (RIIC3.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC3CR1H (RIIC3.RIICnCR1.UINT16[R_IO_H])
+#define RIIC3CR1HL (RIIC3.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC3CR1HH (RIIC3.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC3CR2 (RIIC3.RIICnCR2.UINT32)
+#define RIIC3CR2L (RIIC3.RIICnCR2.UINT16[R_IO_L])
+#define RIIC3CR2LL (RIIC3.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC3CR2LH (RIIC3.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC3CR2H (RIIC3.RIICnCR2.UINT16[R_IO_H])
+#define RIIC3CR2HL (RIIC3.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC3CR2HH (RIIC3.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC3MR1 (RIIC3.RIICnMR1.UINT32)
+#define RIIC3MR1L (RIIC3.RIICnMR1.UINT16[R_IO_L])
+#define RIIC3MR1LL (RIIC3.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC3MR1LH (RIIC3.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC3MR1H (RIIC3.RIICnMR1.UINT16[R_IO_H])
+#define RIIC3MR1HL (RIIC3.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC3MR1HH (RIIC3.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC3MR2 (RIIC3.RIICnMR2.UINT32)
+#define RIIC3MR2L (RIIC3.RIICnMR2.UINT16[R_IO_L])
+#define RIIC3MR2LL (RIIC3.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC3MR2LH (RIIC3.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC3MR2H (RIIC3.RIICnMR2.UINT16[R_IO_H])
+#define RIIC3MR2HL (RIIC3.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC3MR2HH (RIIC3.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC3MR3 (RIIC3.RIICnMR3.UINT32)
+#define RIIC3MR3L (RIIC3.RIICnMR3.UINT16[R_IO_L])
+#define RIIC3MR3LL (RIIC3.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC3MR3LH (RIIC3.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC3MR3H (RIIC3.RIICnMR3.UINT16[R_IO_H])
+#define RIIC3MR3HL (RIIC3.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC3MR3HH (RIIC3.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC3FER (RIIC3.RIICnFER.UINT32)
+#define RIIC3FERL (RIIC3.RIICnFER.UINT16[R_IO_L])
+#define RIIC3FERLL (RIIC3.RIICnFER.UINT8[R_IO_LL])
+#define RIIC3FERLH (RIIC3.RIICnFER.UINT8[R_IO_LH])
+#define RIIC3FERH (RIIC3.RIICnFER.UINT16[R_IO_H])
+#define RIIC3FERHL (RIIC3.RIICnFER.UINT8[R_IO_HL])
+#define RIIC3FERHH (RIIC3.RIICnFER.UINT8[R_IO_HH])
+#define RIIC3SER (RIIC3.RIICnSER.UINT32)
+#define RIIC3SERL (RIIC3.RIICnSER.UINT16[R_IO_L])
+#define RIIC3SERLL (RIIC3.RIICnSER.UINT8[R_IO_LL])
+#define RIIC3SERLH (RIIC3.RIICnSER.UINT8[R_IO_LH])
+#define RIIC3SERH (RIIC3.RIICnSER.UINT16[R_IO_H])
+#define RIIC3SERHL (RIIC3.RIICnSER.UINT8[R_IO_HL])
+#define RIIC3SERHH (RIIC3.RIICnSER.UINT8[R_IO_HH])
+#define RIIC3IER (RIIC3.RIICnIER.UINT32)
+#define RIIC3IERL (RIIC3.RIICnIER.UINT16[R_IO_L])
+#define RIIC3IERLL (RIIC3.RIICnIER.UINT8[R_IO_LL])
+#define RIIC3IERLH (RIIC3.RIICnIER.UINT8[R_IO_LH])
+#define RIIC3IERH (RIIC3.RIICnIER.UINT16[R_IO_H])
+#define RIIC3IERHL (RIIC3.RIICnIER.UINT8[R_IO_HL])
+#define RIIC3IERHH (RIIC3.RIICnIER.UINT8[R_IO_HH])
+#define RIIC3SR1 (RIIC3.RIICnSR1.UINT32)
+#define RIIC3SR1L (RIIC3.RIICnSR1.UINT16[R_IO_L])
+#define RIIC3SR1LL (RIIC3.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC3SR1LH (RIIC3.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC3SR1H (RIIC3.RIICnSR1.UINT16[R_IO_H])
+#define RIIC3SR1HL (RIIC3.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC3SR1HH (RIIC3.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC3SR2 (RIIC3.RIICnSR2.UINT32)
+#define RIIC3SR2L (RIIC3.RIICnSR2.UINT16[R_IO_L])
+#define RIIC3SR2LL (RIIC3.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC3SR2LH (RIIC3.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC3SR2H (RIIC3.RIICnSR2.UINT16[R_IO_H])
+#define RIIC3SR2HL (RIIC3.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC3SR2HH (RIIC3.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC3SAR0 (RIIC3.RIICnSAR0.UINT32)
+#define RIIC3SAR0L (RIIC3.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC3SAR0LL (RIIC3.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC3SAR0LH (RIIC3.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC3SAR0H (RIIC3.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC3SAR0HL (RIIC3.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC3SAR0HH (RIIC3.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC3SAR1 (RIIC3.RIICnSAR1.UINT32)
+#define RIIC3SAR1L (RIIC3.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC3SAR1LL (RIIC3.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC3SAR1LH (RIIC3.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC3SAR1H (RIIC3.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC3SAR1HL (RIIC3.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC3SAR1HH (RIIC3.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC3SAR2 (RIIC3.RIICnSAR2.UINT32)
+#define RIIC3SAR2L (RIIC3.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC3SAR2LL (RIIC3.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC3SAR2LH (RIIC3.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC3SAR2H (RIIC3.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC3SAR2HL (RIIC3.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC3SAR2HH (RIIC3.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC3BRL (RIIC3.RIICnBRL.UINT32)
+#define RIIC3BRLL (RIIC3.RIICnBRL.UINT16[R_IO_L])
+#define RIIC3BRLLL (RIIC3.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC3BRLLH (RIIC3.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC3BRLH (RIIC3.RIICnBRL.UINT16[R_IO_H])
+#define RIIC3BRLHL (RIIC3.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC3BRLHH (RIIC3.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC3BRH (RIIC3.RIICnBRH.UINT32)
+#define RIIC3BRHL (RIIC3.RIICnBRH.UINT16[R_IO_L])
+#define RIIC3BRHLL (RIIC3.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC3BRHLH (RIIC3.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC3BRHH (RIIC3.RIICnBRH.UINT16[R_IO_H])
+#define RIIC3BRHHL (RIIC3.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC3BRHHH (RIIC3.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC3DRT (RIIC3.RIICnDRT.UINT32)
+#define RIIC3DRTL (RIIC3.RIICnDRT.UINT16[R_IO_L])
+#define RIIC3DRTLL (RIIC3.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC3DRTLH (RIIC3.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC3DRTH (RIIC3.RIICnDRT.UINT16[R_IO_H])
+#define RIIC3DRTHL (RIIC3.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC3DRTHH (RIIC3.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC3DRR (RIIC3.RIICnDRR.UINT32)
+#define RIIC3DRRL (RIIC3.RIICnDRR.UINT16[R_IO_L])
+#define RIIC3DRRLL (RIIC3.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC3DRRLH (RIIC3.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC3DRRH (RIIC3.RIICnDRR.UINT16[R_IO_H])
+#define RIIC3DRRHL (RIIC3.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC3DRRHH (RIIC3.RIICnDRR.UINT8[R_IO_HH])
+
+#define RIICnCRm_COUNT (2)
+#define RIICnMRm_COUNT (3)
+#define RIICnSRm_COUNT (2)
+#define RIICnSARm_COUNT (3)
+
+
+typedef struct st_riic
+{
+                                                           /* RIIC             */
+
+/* #define RIICnCRm_COUNT (2) */
+    union iodefine_reg32_t  RIICnCR1;                      /*  RIICnCR1        */
+    union iodefine_reg32_t  RIICnCR2;                      /*  RIICnCR2        */
+
+/* #define RIICnMRm_COUNT (3) */
+    union iodefine_reg32_t  RIICnMR1;                      /*  RIICnMR1        */
+    union iodefine_reg32_t  RIICnMR2;                      /*  RIICnMR2        */
+    union iodefine_reg32_t  RIICnMR3;                      /*  RIICnMR3        */
+    union iodefine_reg32_t  RIICnFER;                      /*  RIICnFER        */
+    union iodefine_reg32_t  RIICnSER;                      /*  RIICnSER        */
+    union iodefine_reg32_t  RIICnIER;                      /*  RIICnIER        */
+
+/* #define RIICnSRm_COUNT (2) */
+    union iodefine_reg32_t  RIICnSR1;                      /*  RIICnSR1        */
+    union iodefine_reg32_t  RIICnSR2;                      /*  RIICnSR2        */
+
+/* #define RIICnSARm_COUNT (3) */
+    union iodefine_reg32_t  RIICnSAR0;                     /*  RIICnSAR0       */
+    union iodefine_reg32_t  RIICnSAR1;                     /*  RIICnSAR1       */
+    union iodefine_reg32_t  RIICnSAR2;                     /*  RIICnSAR2       */
+    union iodefine_reg32_t  RIICnBRL;                      /*  RIICnBRL        */
+    union iodefine_reg32_t  RIICnBRH;                      /*  RIICnBRH        */
+    union iodefine_reg32_t  RIICnDRT;                      /*  RIICnDRT        */
+    union iodefine_reg32_t  RIICnDRR;                      /*  RIICnDRR        */
+    
+} r_io_riic_t;
+
+
+/* Channel array defines of RIIC (2)*/
+#ifdef  DECLARE_RIIC_CHANNELS
+volatile struct st_riic*  RIIC[ RIIC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RIIC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RIIC_CHANNELS */
+/* End of channel array defines of RIIC (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,30 +18,104 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : romdec_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef ROMDEC_IODEFINE_H
 #define ROMDEC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_romdec
-{                                                          /* ROMDEC           */
+#define ROMDEC  (*(struct st_romdec  *)0xE8005000uL) /* ROMDEC */
+
+
+#define ROMDECCROMEN (ROMDEC.CROMEN)
+#define ROMDECCROMSY0 (ROMDEC.CROMSY0)
+#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0)
+#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1)
+#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3)
+#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4)
+#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5)
+#define ROMDECCROMST0 (ROMDEC.CROMST0)
+#define ROMDECCROMST1 (ROMDEC.CROMST1)
+#define ROMDECCROMST3 (ROMDEC.CROMST3)
+#define ROMDECCROMST4 (ROMDEC.CROMST4)
+#define ROMDECCROMST5 (ROMDEC.CROMST5)
+#define ROMDECCROMST6 (ROMDEC.CROMST6)
+#define ROMDECCBUFST0 (ROMDEC.CBUFST0)
+#define ROMDECCBUFST1 (ROMDEC.CBUFST1)
+#define ROMDECCBUFST2 (ROMDEC.CBUFST2)
+#define ROMDECHEAD00 (ROMDEC.HEAD00)
+#define ROMDECHEAD01 (ROMDEC.HEAD01)
+#define ROMDECHEAD02 (ROMDEC.HEAD02)
+#define ROMDECHEAD03 (ROMDEC.HEAD03)
+#define ROMDECSHEAD00 (ROMDEC.SHEAD00)
+#define ROMDECSHEAD01 (ROMDEC.SHEAD01)
+#define ROMDECSHEAD02 (ROMDEC.SHEAD02)
+#define ROMDECSHEAD03 (ROMDEC.SHEAD03)
+#define ROMDECSHEAD04 (ROMDEC.SHEAD04)
+#define ROMDECSHEAD05 (ROMDEC.SHEAD05)
+#define ROMDECSHEAD06 (ROMDEC.SHEAD06)
+#define ROMDECSHEAD07 (ROMDEC.SHEAD07)
+#define ROMDECHEAD20 (ROMDEC.HEAD20)
+#define ROMDECHEAD21 (ROMDEC.HEAD21)
+#define ROMDECHEAD22 (ROMDEC.HEAD22)
+#define ROMDECHEAD23 (ROMDEC.HEAD23)
+#define ROMDECSHEAD20 (ROMDEC.SHEAD20)
+#define ROMDECSHEAD21 (ROMDEC.SHEAD21)
+#define ROMDECSHEAD22 (ROMDEC.SHEAD22)
+#define ROMDECSHEAD23 (ROMDEC.SHEAD23)
+#define ROMDECSHEAD24 (ROMDEC.SHEAD24)
+#define ROMDECSHEAD25 (ROMDEC.SHEAD25)
+#define ROMDECSHEAD26 (ROMDEC.SHEAD26)
+#define ROMDECSHEAD27 (ROMDEC.SHEAD27)
+#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0)
+#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1)
+#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2)
+#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3)
+#define ROMDECCROMST0M (ROMDEC.CROMST0M)
+#define ROMDECROMDECRST (ROMDEC.ROMDECRST)
+#define ROMDECRSTSTAT (ROMDEC.RSTSTAT)
+#define ROMDECSSI (ROMDEC.SSI)
+#define ROMDECINTHOLD (ROMDEC.INTHOLD)
+#define ROMDECINHINT (ROMDEC.INHINT)
+#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0)
+#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2)
+#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0)
+
+#define ROMDEC_CROMCTL0_COUNT (2)
+#define ROMDEC_CROMST0_COUNT (2)
+#define ROMDEC_CBUFST0_COUNT (3)
+#define ROMDEC_HEAD00_COUNT (4)
+#define ROMDEC_SHEAD00_COUNT (8)
+#define ROMDEC_HEAD20_COUNT (4)
+#define ROMDEC_SHEAD20_COUNT (8)
+#define ROMDEC_CBUFCTL0_COUNT (4)
+#define ROMDEC_STRMDIN0_COUNT (2)
+
+
+typedef struct st_romdec
+{
+                                                           /* ROMDEC           */
     volatile uint8_t   CROMEN;                                 /*  CROMEN          */
     volatile uint8_t   CROMSY0;                                /*  CROMSY0         */
-#define ROMDEC_CROMCTL0_COUNT 2
+
+/* #define ROMDEC_CROMCTL0_COUNT (2) */
     volatile uint8_t   CROMCTL0;                               /*  CROMCTL0        */
     volatile uint8_t   CROMCTL1;                               /*  CROMCTL1        */
     volatile uint8_t   dummy23[1];                             /*                  */
     volatile uint8_t   CROMCTL3;                               /*  CROMCTL3        */
     volatile uint8_t   CROMCTL4;                               /*  CROMCTL4        */
     volatile uint8_t   CROMCTL5;                               /*  CROMCTL5        */
-#define ROMDEC_CROMST0_COUNT 2
+
+/* #define ROMDEC_CROMST0_COUNT (2) */
     volatile uint8_t   CROMST0;                                /*  CROMST0         */
     volatile uint8_t   CROMST1;                                /*  CROMST1         */
     volatile uint8_t   dummy24[1];                             /*                  */
@@ -50,17 +124,20 @@
     volatile uint8_t   CROMST5;                                /*  CROMST5         */
     volatile uint8_t   CROMST6;                                /*  CROMST6         */
     volatile uint8_t   dummy25[5];                             /*                  */
-#define ROMDEC_CBUFST0_COUNT 3
+
+/* #define ROMDEC_CBUFST0_COUNT (3) */
     volatile uint8_t   CBUFST0;                                /*  CBUFST0         */
     volatile uint8_t   CBUFST1;                                /*  CBUFST1         */
     volatile uint8_t   CBUFST2;                                /*  CBUFST2         */
     volatile uint8_t   dummy26[1];                             /*                  */
-#define ROMDEC_HEAD00_COUNT 4
+
+/* #define ROMDEC_HEAD00_COUNT (4) */
     volatile uint8_t   HEAD00;                                 /*  HEAD00          */
     volatile uint8_t   HEAD01;                                 /*  HEAD01          */
     volatile uint8_t   HEAD02;                                 /*  HEAD02          */
     volatile uint8_t   HEAD03;                                 /*  HEAD03          */
-#define ROMDEC_SHEAD00_COUNT 8
+
+/* #define ROMDEC_SHEAD00_COUNT (8) */
     volatile uint8_t   SHEAD00;                                /*  SHEAD00         */
     volatile uint8_t   SHEAD01;                                /*  SHEAD01         */
     volatile uint8_t   SHEAD02;                                /*  SHEAD02         */
@@ -69,12 +146,14 @@
     volatile uint8_t   SHEAD05;                                /*  SHEAD05         */
     volatile uint8_t   SHEAD06;                                /*  SHEAD06         */
     volatile uint8_t   SHEAD07;                                /*  SHEAD07         */
-#define ROMDEC_HEAD20_COUNT 4
+
+/* #define ROMDEC_HEAD20_COUNT (4) */
     volatile uint8_t   HEAD20;                                 /*  HEAD20          */
     volatile uint8_t   HEAD21;                                 /*  HEAD21          */
     volatile uint8_t   HEAD22;                                 /*  HEAD22          */
     volatile uint8_t   HEAD23;                                 /*  HEAD23          */
-#define ROMDEC_SHEAD20_COUNT 8
+
+/* #define ROMDEC_SHEAD20_COUNT (8) */
     volatile uint8_t   SHEAD20;                                /*  SHEAD20         */
     volatile uint8_t   SHEAD21;                                /*  SHEAD21         */
     volatile uint8_t   SHEAD22;                                /*  SHEAD22         */
@@ -84,7 +163,8 @@
     volatile uint8_t   SHEAD26;                                /*  SHEAD26         */
     volatile uint8_t   SHEAD27;                                /*  SHEAD27         */
     volatile uint8_t   dummy27[16];                            /*                  */
-#define ROMDEC_CBUFCTL0_COUNT 4
+
+/* #define ROMDEC_CBUFCTL0_COUNT (4) */
     volatile uint8_t   CBUFCTL0;                               /*  CBUFCTL0        */
     volatile uint8_t   CBUFCTL1;                               /*  CBUFCTL1        */
     volatile uint8_t   CBUFCTL2;                               /*  CBUFCTL2        */
@@ -99,68 +179,16 @@
     volatile uint8_t   INTHOLD;                                /*  INTHOLD         */
     volatile uint8_t   INHINT;                                 /*  INHINT          */
     volatile uint8_t   dummy31[246];                           /*                  */
-#define ROMDEC_STRMDIN0_COUNT 2
+
+/* #define ROMDEC_STRMDIN0_COUNT (2) */
     volatile uint16_t STRMDIN0;                               /*  STRMDIN0        */
     volatile uint16_t STRMDIN2;                               /*  STRMDIN2        */
     volatile uint16_t STRMDOUT0;                              /*  STRMDOUT0       */
-};
-
-
-#define ROMDEC  (*(struct st_romdec  *)0xE8005000uL) /* ROMDEC */
+} r_io_romdec_t;
 
 
-#define ROMDECCROMEN ROMDEC.CROMEN
-#define ROMDECCROMSY0 ROMDEC.CROMSY0
-#define ROMDECCROMCTL0 ROMDEC.CROMCTL0
-#define ROMDECCROMCTL1 ROMDEC.CROMCTL1
-#define ROMDECCROMCTL3 ROMDEC.CROMCTL3
-#define ROMDECCROMCTL4 ROMDEC.CROMCTL4
-#define ROMDECCROMCTL5 ROMDEC.CROMCTL5
-#define ROMDECCROMST0 ROMDEC.CROMST0
-#define ROMDECCROMST1 ROMDEC.CROMST1
-#define ROMDECCROMST3 ROMDEC.CROMST3
-#define ROMDECCROMST4 ROMDEC.CROMST4
-#define ROMDECCROMST5 ROMDEC.CROMST5
-#define ROMDECCROMST6 ROMDEC.CROMST6
-#define ROMDECCBUFST0 ROMDEC.CBUFST0
-#define ROMDECCBUFST1 ROMDEC.CBUFST1
-#define ROMDECCBUFST2 ROMDEC.CBUFST2
-#define ROMDECHEAD00 ROMDEC.HEAD00
-#define ROMDECHEAD01 ROMDEC.HEAD01
-#define ROMDECHEAD02 ROMDEC.HEAD02
-#define ROMDECHEAD03 ROMDEC.HEAD03
-#define ROMDECSHEAD00 ROMDEC.SHEAD00
-#define ROMDECSHEAD01 ROMDEC.SHEAD01
-#define ROMDECSHEAD02 ROMDEC.SHEAD02
-#define ROMDECSHEAD03 ROMDEC.SHEAD03
-#define ROMDECSHEAD04 ROMDEC.SHEAD04
-#define ROMDECSHEAD05 ROMDEC.SHEAD05
-#define ROMDECSHEAD06 ROMDEC.SHEAD06
-#define ROMDECSHEAD07 ROMDEC.SHEAD07
-#define ROMDECHEAD20 ROMDEC.HEAD20
-#define ROMDECHEAD21 ROMDEC.HEAD21
-#define ROMDECHEAD22 ROMDEC.HEAD22
-#define ROMDECHEAD23 ROMDEC.HEAD23
-#define ROMDECSHEAD20 ROMDEC.SHEAD20
-#define ROMDECSHEAD21 ROMDEC.SHEAD21
-#define ROMDECSHEAD22 ROMDEC.SHEAD22
-#define ROMDECSHEAD23 ROMDEC.SHEAD23
-#define ROMDECSHEAD24 ROMDEC.SHEAD24
-#define ROMDECSHEAD25 ROMDEC.SHEAD25
-#define ROMDECSHEAD26 ROMDEC.SHEAD26
-#define ROMDECSHEAD27 ROMDEC.SHEAD27
-#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0
-#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1
-#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2
-#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3
-#define ROMDECCROMST0M ROMDEC.CROMST0M
-#define ROMDECROMDECRST ROMDEC.ROMDECRST
-#define ROMDECRSTSTAT ROMDEC.RSTSTAT
-#define ROMDECSSI ROMDEC.SSI
-#define ROMDECINTHOLD ROMDEC.INTHOLD
-#define ROMDECINHINT ROMDEC.INHINT
-#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0
-#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2
-#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,1886 +18,30 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : rscan0_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef RSCAN0_IODEFINE_H
 #define RSCAN0_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
 /* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_rscan0
-{                                                          /* RSCAN0           */
-/* start of struct st_rscan_from_rscan0cncfg */
-    union iodefine_reg32_t  C0CFG;                         /*  C0CFG           */
-    union iodefine_reg32_t  C0CTR;                         /*  C0CTR           */
-    union iodefine_reg32_t  C0STS;                         /*  C0STS           */
-    union iodefine_reg32_t  C0ERFL;                        /*  C0ERFL          */
-/* end of struct st_rscan_from_rscan0cncfg */
-    
-/* start of struct st_rscan_from_rscan0cncfg */
-    union iodefine_reg32_t  C1CFG;                         /*  C1CFG           */
-    union iodefine_reg32_t  C1CTR;                         /*  C1CTR           */
-    union iodefine_reg32_t  C1STS;                         /*  C1STS           */
-    union iodefine_reg32_t  C1ERFL;                        /*  C1ERFL          */
-/* end of struct st_rscan_from_rscan0cncfg */
-    
-/* start of struct st_rscan_from_rscan0cncfg */
-    union iodefine_reg32_t  C2CFG;                         /*  C2CFG           */
-    union iodefine_reg32_t  C2CTR;                         /*  C2CTR           */
-    union iodefine_reg32_t  C2STS;                         /*  C2STS           */
-    union iodefine_reg32_t  C2ERFL;                        /*  C2ERFL          */
-/* end of struct st_rscan_from_rscan0cncfg */
-    
-/* start of struct st_rscan_from_rscan0cncfg */
-    union iodefine_reg32_t  C3CFG;                         /*  C3CFG           */
-    union iodefine_reg32_t  C3CTR;                         /*  C3CTR           */
-    union iodefine_reg32_t  C3STS;                         /*  C3STS           */
-    union iodefine_reg32_t  C3ERFL;                        /*  C3ERFL          */
-/* end of struct st_rscan_from_rscan0cncfg */
-    
-/* start of struct st_rscan_from_rscan0cncfg */
-    union iodefine_reg32_t  C4CFG;                         /*  C4CFG           */
-    union iodefine_reg32_t  C4CTR;                         /*  C4CTR           */
-    union iodefine_reg32_t  C4STS;                         /*  C4STS           */
-    union iodefine_reg32_t  C4ERFL;                        /*  C4ERFL          */
-/* end of struct st_rscan_from_rscan0cncfg */
-    
-    volatile uint8_t   dummy159[52];                           /*                  */
-    union iodefine_reg32_t  GCFG;                          /*  GCFG            */
-    union iodefine_reg32_t  GCTR;                          /*  GCTR            */
-    union iodefine_reg32_t  GSTS;                          /*  GSTS            */
-    union iodefine_reg32_t  GERFL;                         /*  GERFL           */
-    union iodefine_reg32_16_t  GTSC;                       /*  GTSC            */
-    union iodefine_reg32_t  GAFLECTR;                      /*  GAFLECTR        */
-#define RSCAN0_GAFLCFG0_COUNT 2
-    union iodefine_reg32_t  GAFLCFG0;                      /*  GAFLCFG0        */
-    union iodefine_reg32_t  GAFLCFG1;                      /*  GAFLCFG1        */
-    union iodefine_reg32_t  RMNB;                          /*  RMNB            */
-#define RSCAN0_RMND0_COUNT 3
-    union iodefine_reg32_t  RMND0;                         /*  RMND0           */
-    union iodefine_reg32_t  RMND1;                         /*  RMND1           */
-    union iodefine_reg32_t  RMND2;                         /*  RMND2           */
-    
-    volatile uint8_t   dummy160[4];                            /*                  */
-#define RSCAN0_RFCC0_COUNT 8
-    union iodefine_reg32_t  RFCC0;                         /*  RFCC0           */
-    union iodefine_reg32_t  RFCC1;                         /*  RFCC1           */
-    union iodefine_reg32_t  RFCC2;                         /*  RFCC2           */
-    union iodefine_reg32_t  RFCC3;                         /*  RFCC3           */
-    union iodefine_reg32_t  RFCC4;                         /*  RFCC4           */
-    union iodefine_reg32_t  RFCC5;                         /*  RFCC5           */
-    union iodefine_reg32_t  RFCC6;                         /*  RFCC6           */
-    union iodefine_reg32_t  RFCC7;                         /*  RFCC7           */
-#define RSCAN0_RFSTS0_COUNT 8
-    union iodefine_reg32_t  RFSTS0;                        /*  RFSTS0          */
-    union iodefine_reg32_t  RFSTS1;                        /*  RFSTS1          */
-    union iodefine_reg32_t  RFSTS2;                        /*  RFSTS2          */
-    union iodefine_reg32_t  RFSTS3;                        /*  RFSTS3          */
-    union iodefine_reg32_t  RFSTS4;                        /*  RFSTS4          */
-    union iodefine_reg32_t  RFSTS5;                        /*  RFSTS5          */
-    union iodefine_reg32_t  RFSTS6;                        /*  RFSTS6          */
-    union iodefine_reg32_t  RFSTS7;                        /*  RFSTS7          */
-#define RSCAN0_RFPCTR0_COUNT 8
-    union iodefine_reg32_t  RFPCTR0;                       /*  RFPCTR0         */
-    union iodefine_reg32_t  RFPCTR1;                       /*  RFPCTR1         */
-    union iodefine_reg32_t  RFPCTR2;                       /*  RFPCTR2         */
-    union iodefine_reg32_t  RFPCTR3;                       /*  RFPCTR3         */
-    union iodefine_reg32_t  RFPCTR4;                       /*  RFPCTR4         */
-    union iodefine_reg32_t  RFPCTR5;                       /*  RFPCTR5         */
-    union iodefine_reg32_t  RFPCTR6;                       /*  RFPCTR6         */
-    union iodefine_reg32_t  RFPCTR7;                       /*  RFPCTR7         */
-#define RSCAN0_CFCC0_COUNT 15
-    union iodefine_reg32_t  CFCC0;                         /*  CFCC0           */
-    union iodefine_reg32_t  CFCC1;                         /*  CFCC1           */
-    union iodefine_reg32_t  CFCC2;                         /*  CFCC2           */
-    union iodefine_reg32_t  CFCC3;                         /*  CFCC3           */
-    union iodefine_reg32_t  CFCC4;                         /*  CFCC4           */
-    union iodefine_reg32_t  CFCC5;                         /*  CFCC5           */
-    union iodefine_reg32_t  CFCC6;                         /*  CFCC6           */
-    union iodefine_reg32_t  CFCC7;                         /*  CFCC7           */
-    union iodefine_reg32_t  CFCC8;                         /*  CFCC8           */
-    union iodefine_reg32_t  CFCC9;                         /*  CFCC9           */
-    union iodefine_reg32_t  CFCC10;                        /*  CFCC10          */
-    union iodefine_reg32_t  CFCC11;                        /*  CFCC11          */
-    union iodefine_reg32_t  CFCC12;                        /*  CFCC12          */
-    union iodefine_reg32_t  CFCC13;                        /*  CFCC13          */
-    union iodefine_reg32_t  CFCC14;                        /*  CFCC14          */
-    
-    volatile uint8_t   dummy161[36];                           /*                  */
-#define RSCAN0_CFSTS0_COUNT 15
-    union iodefine_reg32_t  CFSTS0;                        /*  CFSTS0          */
-    union iodefine_reg32_t  CFSTS1;                        /*  CFSTS1          */
-    union iodefine_reg32_t  CFSTS2;                        /*  CFSTS2          */
-    union iodefine_reg32_t  CFSTS3;                        /*  CFSTS3          */
-    union iodefine_reg32_t  CFSTS4;                        /*  CFSTS4          */
-    union iodefine_reg32_t  CFSTS5;                        /*  CFSTS5          */
-    union iodefine_reg32_t  CFSTS6;                        /*  CFSTS6          */
-    union iodefine_reg32_t  CFSTS7;                        /*  CFSTS7          */
-    union iodefine_reg32_t  CFSTS8;                        /*  CFSTS8          */
-    union iodefine_reg32_t  CFSTS9;                        /*  CFSTS9          */
-    union iodefine_reg32_t  CFSTS10;                       /*  CFSTS10         */
-    union iodefine_reg32_t  CFSTS11;                       /*  CFSTS11         */
-    union iodefine_reg32_t  CFSTS12;                       /*  CFSTS12         */
-    union iodefine_reg32_t  CFSTS13;                       /*  CFSTS13         */
-    union iodefine_reg32_t  CFSTS14;                       /*  CFSTS14         */
-    
-    volatile uint8_t   dummy162[36];                           /*                  */
-#define RSCAN0_CFPCTR0_COUNT 15
-    union iodefine_reg32_t  CFPCTR0;                       /*  CFPCTR0         */
-    union iodefine_reg32_t  CFPCTR1;                       /*  CFPCTR1         */
-    union iodefine_reg32_t  CFPCTR2;                       /*  CFPCTR2         */
-    union iodefine_reg32_t  CFPCTR3;                       /*  CFPCTR3         */
-    union iodefine_reg32_t  CFPCTR4;                       /*  CFPCTR4         */
-    union iodefine_reg32_t  CFPCTR5;                       /*  CFPCTR5         */
-    union iodefine_reg32_t  CFPCTR6;                       /*  CFPCTR6         */
-    union iodefine_reg32_t  CFPCTR7;                       /*  CFPCTR7         */
-    union iodefine_reg32_t  CFPCTR8;                       /*  CFPCTR8         */
-    union iodefine_reg32_t  CFPCTR9;                       /*  CFPCTR9         */
-    union iodefine_reg32_t  CFPCTR10;                      /*  CFPCTR10        */
-    union iodefine_reg32_t  CFPCTR11;                      /*  CFPCTR11        */
-    union iodefine_reg32_t  CFPCTR12;                      /*  CFPCTR12        */
-    union iodefine_reg32_t  CFPCTR13;                      /*  CFPCTR13        */
-    union iodefine_reg32_t  CFPCTR14;                      /*  CFPCTR14        */
-    
-    volatile uint8_t   dummy163[36];                           /*                  */
-    union iodefine_reg32_t  FESTS;                         /*  FESTS           */
-    union iodefine_reg32_t  FFSTS;                         /*  FFSTS           */
-    union iodefine_reg32_t  FMSTS;                         /*  FMSTS           */
-    union iodefine_reg32_t  RFISTS;                        /*  RFISTS          */
-    union iodefine_reg32_t  CFRISTS;                       /*  CFRISTS         */
-    union iodefine_reg32_t  CFTISTS;                       /*  CFTISTS         */
-    
-#define RSCAN0_TMC0_COUNT 80
-    volatile uint8_t   TMC0;                                   /*  TMC0            */
-    volatile uint8_t   TMC1;                                   /*  TMC1            */
-    volatile uint8_t   TMC2;                                   /*  TMC2            */
-    volatile uint8_t   TMC3;                                   /*  TMC3            */
-    volatile uint8_t   TMC4;                                   /*  TMC4            */
-    volatile uint8_t   TMC5;                                   /*  TMC5            */
-    volatile uint8_t   TMC6;                                   /*  TMC6            */
-    volatile uint8_t   TMC7;                                   /*  TMC7            */
-    volatile uint8_t   TMC8;                                   /*  TMC8            */
-    volatile uint8_t   TMC9;                                   /*  TMC9            */
-    volatile uint8_t   TMC10;                                  /*  TMC10           */
-    volatile uint8_t   TMC11;                                  /*  TMC11           */
-    volatile uint8_t   TMC12;                                  /*  TMC12           */
-    volatile uint8_t   TMC13;                                  /*  TMC13           */
-    volatile uint8_t   TMC14;                                  /*  TMC14           */
-    volatile uint8_t   TMC15;                                  /*  TMC15           */
-    volatile uint8_t   TMC16;                                  /*  TMC16           */
-    volatile uint8_t   TMC17;                                  /*  TMC17           */
-    volatile uint8_t   TMC18;                                  /*  TMC18           */
-    volatile uint8_t   TMC19;                                  /*  TMC19           */
-    volatile uint8_t   TMC20;                                  /*  TMC20           */
-    volatile uint8_t   TMC21;                                  /*  TMC21           */
-    volatile uint8_t   TMC22;                                  /*  TMC22           */
-    volatile uint8_t   TMC23;                                  /*  TMC23           */
-    volatile uint8_t   TMC24;                                  /*  TMC24           */
-    volatile uint8_t   TMC25;                                  /*  TMC25           */
-    volatile uint8_t   TMC26;                                  /*  TMC26           */
-    volatile uint8_t   TMC27;                                  /*  TMC27           */
-    volatile uint8_t   TMC28;                                  /*  TMC28           */
-    volatile uint8_t   TMC29;                                  /*  TMC29           */
-    volatile uint8_t   TMC30;                                  /*  TMC30           */
-    volatile uint8_t   TMC31;                                  /*  TMC31           */
-    volatile uint8_t   TMC32;                                  /*  TMC32           */
-    volatile uint8_t   TMC33;                                  /*  TMC33           */
-    volatile uint8_t   TMC34;                                  /*  TMC34           */
-    volatile uint8_t   TMC35;                                  /*  TMC35           */
-    volatile uint8_t   TMC36;                                  /*  TMC36           */
-    volatile uint8_t   TMC37;                                  /*  TMC37           */
-    volatile uint8_t   TMC38;                                  /*  TMC38           */
-    volatile uint8_t   TMC39;                                  /*  TMC39           */
-    volatile uint8_t   TMC40;                                  /*  TMC40           */
-    volatile uint8_t   TMC41;                                  /*  TMC41           */
-    volatile uint8_t   TMC42;                                  /*  TMC42           */
-    volatile uint8_t   TMC43;                                  /*  TMC43           */
-    volatile uint8_t   TMC44;                                  /*  TMC44           */
-    volatile uint8_t   TMC45;                                  /*  TMC45           */
-    volatile uint8_t   TMC46;                                  /*  TMC46           */
-    volatile uint8_t   TMC47;                                  /*  TMC47           */
-    volatile uint8_t   TMC48;                                  /*  TMC48           */
-    volatile uint8_t   TMC49;                                  /*  TMC49           */
-    volatile uint8_t   TMC50;                                  /*  TMC50           */
-    volatile uint8_t   TMC51;                                  /*  TMC51           */
-    volatile uint8_t   TMC52;                                  /*  TMC52           */
-    volatile uint8_t   TMC53;                                  /*  TMC53           */
-    volatile uint8_t   TMC54;                                  /*  TMC54           */
-    volatile uint8_t   TMC55;                                  /*  TMC55           */
-    volatile uint8_t   TMC56;                                  /*  TMC56           */
-    volatile uint8_t   TMC57;                                  /*  TMC57           */
-    volatile uint8_t   TMC58;                                  /*  TMC58           */
-    volatile uint8_t   TMC59;                                  /*  TMC59           */
-    volatile uint8_t   TMC60;                                  /*  TMC60           */
-    volatile uint8_t   TMC61;                                  /*  TMC61           */
-    volatile uint8_t   TMC62;                                  /*  TMC62           */
-    volatile uint8_t   TMC63;                                  /*  TMC63           */
-    volatile uint8_t   TMC64;                                  /*  TMC64           */
-    volatile uint8_t   TMC65;                                  /*  TMC65           */
-    volatile uint8_t   TMC66;                                  /*  TMC66           */
-    volatile uint8_t   TMC67;                                  /*  TMC67           */
-    volatile uint8_t   TMC68;                                  /*  TMC68           */
-    volatile uint8_t   TMC69;                                  /*  TMC69           */
-    volatile uint8_t   TMC70;                                  /*  TMC70           */
-    volatile uint8_t   TMC71;                                  /*  TMC71           */
-    volatile uint8_t   TMC72;                                  /*  TMC72           */
-    volatile uint8_t   TMC73;                                  /*  TMC73           */
-    volatile uint8_t   TMC74;                                  /*  TMC74           */
-    volatile uint8_t   TMC75;                                  /*  TMC75           */
-    volatile uint8_t   TMC76;                                  /*  TMC76           */
-    volatile uint8_t   TMC77;                                  /*  TMC77           */
-    volatile uint8_t   TMC78;                                  /*  TMC78           */
-    volatile uint8_t   TMC79;                                  /*  TMC79           */
-    volatile uint8_t   dummy164[48];                           /*                  */
-#define RSCAN0_TMSTS0_COUNT 80
-    volatile uint8_t   TMSTS0;                                 /*  TMSTS0          */
-    volatile uint8_t   TMSTS1;                                 /*  TMSTS1          */
-    volatile uint8_t   TMSTS2;                                 /*  TMSTS2          */
-    volatile uint8_t   TMSTS3;                                 /*  TMSTS3          */
-    volatile uint8_t   TMSTS4;                                 /*  TMSTS4          */
-    volatile uint8_t   TMSTS5;                                 /*  TMSTS5          */
-    volatile uint8_t   TMSTS6;                                 /*  TMSTS6          */
-    volatile uint8_t   TMSTS7;                                 /*  TMSTS7          */
-    volatile uint8_t   TMSTS8;                                 /*  TMSTS8          */
-    volatile uint8_t   TMSTS9;                                 /*  TMSTS9          */
-    volatile uint8_t   TMSTS10;                                /*  TMSTS10         */
-    volatile uint8_t   TMSTS11;                                /*  TMSTS11         */
-    volatile uint8_t   TMSTS12;                                /*  TMSTS12         */
-    volatile uint8_t   TMSTS13;                                /*  TMSTS13         */
-    volatile uint8_t   TMSTS14;                                /*  TMSTS14         */
-    volatile uint8_t   TMSTS15;                                /*  TMSTS15         */
-    volatile uint8_t   TMSTS16;                                /*  TMSTS16         */
-    volatile uint8_t   TMSTS17;                                /*  TMSTS17         */
-    volatile uint8_t   TMSTS18;                                /*  TMSTS18         */
-    volatile uint8_t   TMSTS19;                                /*  TMSTS19         */
-    volatile uint8_t   TMSTS20;                                /*  TMSTS20         */
-    volatile uint8_t   TMSTS21;                                /*  TMSTS21         */
-    volatile uint8_t   TMSTS22;                                /*  TMSTS22         */
-    volatile uint8_t   TMSTS23;                                /*  TMSTS23         */
-    volatile uint8_t   TMSTS24;                                /*  TMSTS24         */
-    volatile uint8_t   TMSTS25;                                /*  TMSTS25         */
-    volatile uint8_t   TMSTS26;                                /*  TMSTS26         */
-    volatile uint8_t   TMSTS27;                                /*  TMSTS27         */
-    volatile uint8_t   TMSTS28;                                /*  TMSTS28         */
-    volatile uint8_t   TMSTS29;                                /*  TMSTS29         */
-    volatile uint8_t   TMSTS30;                                /*  TMSTS30         */
-    volatile uint8_t   TMSTS31;                                /*  TMSTS31         */
-    volatile uint8_t   TMSTS32;                                /*  TMSTS32         */
-    volatile uint8_t   TMSTS33;                                /*  TMSTS33         */
-    volatile uint8_t   TMSTS34;                                /*  TMSTS34         */
-    volatile uint8_t   TMSTS35;                                /*  TMSTS35         */
-    volatile uint8_t   TMSTS36;                                /*  TMSTS36         */
-    volatile uint8_t   TMSTS37;                                /*  TMSTS37         */
-    volatile uint8_t   TMSTS38;                                /*  TMSTS38         */
-    volatile uint8_t   TMSTS39;                                /*  TMSTS39         */
-    volatile uint8_t   TMSTS40;                                /*  TMSTS40         */
-    volatile uint8_t   TMSTS41;                                /*  TMSTS41         */
-    volatile uint8_t   TMSTS42;                                /*  TMSTS42         */
-    volatile uint8_t   TMSTS43;                                /*  TMSTS43         */
-    volatile uint8_t   TMSTS44;                                /*  TMSTS44         */
-    volatile uint8_t   TMSTS45;                                /*  TMSTS45         */
-    volatile uint8_t   TMSTS46;                                /*  TMSTS46         */
-    volatile uint8_t   TMSTS47;                                /*  TMSTS47         */
-    volatile uint8_t   TMSTS48;                                /*  TMSTS48         */
-    volatile uint8_t   TMSTS49;                                /*  TMSTS49         */
-    volatile uint8_t   TMSTS50;                                /*  TMSTS50         */
-    volatile uint8_t   TMSTS51;                                /*  TMSTS51         */
-    volatile uint8_t   TMSTS52;                                /*  TMSTS52         */
-    volatile uint8_t   TMSTS53;                                /*  TMSTS53         */
-    volatile uint8_t   TMSTS54;                                /*  TMSTS54         */
-    volatile uint8_t   TMSTS55;                                /*  TMSTS55         */
-    volatile uint8_t   TMSTS56;                                /*  TMSTS56         */
-    volatile uint8_t   TMSTS57;                                /*  TMSTS57         */
-    volatile uint8_t   TMSTS58;                                /*  TMSTS58         */
-    volatile uint8_t   TMSTS59;                                /*  TMSTS59         */
-    volatile uint8_t   TMSTS60;                                /*  TMSTS60         */
-    volatile uint8_t   TMSTS61;                                /*  TMSTS61         */
-    volatile uint8_t   TMSTS62;                                /*  TMSTS62         */
-    volatile uint8_t   TMSTS63;                                /*  TMSTS63         */
-    volatile uint8_t   TMSTS64;                                /*  TMSTS64         */
-    volatile uint8_t   TMSTS65;                                /*  TMSTS65         */
-    volatile uint8_t   TMSTS66;                                /*  TMSTS66         */
-    volatile uint8_t   TMSTS67;                                /*  TMSTS67         */
-    volatile uint8_t   TMSTS68;                                /*  TMSTS68         */
-    volatile uint8_t   TMSTS69;                                /*  TMSTS69         */
-    volatile uint8_t   TMSTS70;                                /*  TMSTS70         */
-    volatile uint8_t   TMSTS71;                                /*  TMSTS71         */
-    volatile uint8_t   TMSTS72;                                /*  TMSTS72         */
-    volatile uint8_t   TMSTS73;                                /*  TMSTS73         */
-    volatile uint8_t   TMSTS74;                                /*  TMSTS74         */
-    volatile uint8_t   TMSTS75;                                /*  TMSTS75         */
-    volatile uint8_t   TMSTS76;                                /*  TMSTS76         */
-    volatile uint8_t   TMSTS77;                                /*  TMSTS77         */
-    volatile uint8_t   TMSTS78;                                /*  TMSTS78         */
-    volatile uint8_t   TMSTS79;                                /*  TMSTS79         */
-    volatile uint8_t   dummy165[48];                           /*                  */
-#define RSCAN0_TMTRSTS0_COUNT 3
-    union iodefine_reg32_t  TMTRSTS0;                      /*  TMTRSTS0        */
-    union iodefine_reg32_t  TMTRSTS1;                      /*  TMTRSTS1        */
-    union iodefine_reg32_t  TMTRSTS2;                      /*  TMTRSTS2        */
-    
-    volatile uint8_t   dummy166[4];                            /*                  */
-#define RSCAN0_TMTARSTS0_COUNT 3
-    union iodefine_reg32_t  TMTARSTS0;                     /*  TMTARSTS0       */
-    union iodefine_reg32_t  TMTARSTS1;                     /*  TMTARSTS1       */
-    union iodefine_reg32_t  TMTARSTS2;                     /*  TMTARSTS2       */
-    
-    volatile uint8_t   dummy167[4];                            /*                  */
-#define RSCAN0_TMTCSTS0_COUNT 3
-    union iodefine_reg32_t  TMTCSTS0;                      /*  TMTCSTS0        */
-    union iodefine_reg32_t  TMTCSTS1;                      /*  TMTCSTS1        */
-    union iodefine_reg32_t  TMTCSTS2;                      /*  TMTCSTS2        */
-    
-    volatile uint8_t   dummy168[4];                            /*                  */
-#define RSCAN0_TMTASTS0_COUNT 3
-    union iodefine_reg32_t  TMTASTS0;                      /*  TMTASTS0        */
-    union iodefine_reg32_t  TMTASTS1;                      /*  TMTASTS1        */
-    union iodefine_reg32_t  TMTASTS2;                      /*  TMTASTS2        */
-    
-    volatile uint8_t   dummy169[4];                            /*                  */
-#define RSCAN0_TMIEC0_COUNT 3
-    union iodefine_reg32_t  TMIEC0;                        /*  TMIEC0          */
-    union iodefine_reg32_t  TMIEC1;                        /*  TMIEC1          */
-    union iodefine_reg32_t  TMIEC2;                        /*  TMIEC2          */
-    
-    volatile uint8_t   dummy170[4];                            /*                  */
-#define RSCAN0_TXQCC0_COUNT 5
-    union iodefine_reg32_t  TXQCC0;                        /*  TXQCC0          */
-    union iodefine_reg32_t  TXQCC1;                        /*  TXQCC1          */
-    union iodefine_reg32_t  TXQCC2;                        /*  TXQCC2          */
-    union iodefine_reg32_t  TXQCC3;                        /*  TXQCC3          */
-    union iodefine_reg32_t  TXQCC4;                        /*  TXQCC4          */
-    
-    volatile uint8_t   dummy171[12];                           /*                  */
-#define RSCAN0_TXQSTS0_COUNT 5
-    union iodefine_reg32_t  TXQSTS0;                       /*  TXQSTS0         */
-    union iodefine_reg32_t  TXQSTS1;                       /*  TXQSTS1         */
-    union iodefine_reg32_t  TXQSTS2;                       /*  TXQSTS2         */
-    union iodefine_reg32_t  TXQSTS3;                       /*  TXQSTS3         */
-    union iodefine_reg32_t  TXQSTS4;                       /*  TXQSTS4         */
-    
-    volatile uint8_t   dummy172[12];                           /*                  */
-#define RSCAN0_TXQPCTR0_COUNT 5
-    union iodefine_reg32_t  TXQPCTR0;                      /*  TXQPCTR0        */
-    union iodefine_reg32_t  TXQPCTR1;                      /*  TXQPCTR1        */
-    union iodefine_reg32_t  TXQPCTR2;                      /*  TXQPCTR2        */
-    union iodefine_reg32_t  TXQPCTR3;                      /*  TXQPCTR3        */
-    union iodefine_reg32_t  TXQPCTR4;                      /*  TXQPCTR4        */
-    
-    volatile uint8_t   dummy173[12];                           /*                  */
-#define RSCAN0_THLCC0_COUNT 5
-    union iodefine_reg32_t  THLCC0;                        /*  THLCC0          */
-    union iodefine_reg32_t  THLCC1;                        /*  THLCC1          */
-    union iodefine_reg32_t  THLCC2;                        /*  THLCC2          */
-    union iodefine_reg32_t  THLCC3;                        /*  THLCC3          */
-    union iodefine_reg32_t  THLCC4;                        /*  THLCC4          */
-    
-    volatile uint8_t   dummy174[12];                           /*                  */
-#define RSCAN0_THLSTS0_COUNT 5
-    union iodefine_reg32_t  THLSTS0;                       /*  THLSTS0         */
-    union iodefine_reg32_t  THLSTS1;                       /*  THLSTS1         */
-    union iodefine_reg32_t  THLSTS2;                       /*  THLSTS2         */
-    union iodefine_reg32_t  THLSTS3;                       /*  THLSTS3         */
-    union iodefine_reg32_t  THLSTS4;                       /*  THLSTS4         */
-    
-    volatile uint8_t   dummy175[12];                           /*                  */
-#define RSCAN0_THLPCTR0_COUNT 5
-    union iodefine_reg32_t  THLPCTR0;                      /*  THLPCTR0        */
-    union iodefine_reg32_t  THLPCTR1;                      /*  THLPCTR1        */
-    union iodefine_reg32_t  THLPCTR2;                      /*  THLPCTR2        */
-    union iodefine_reg32_t  THLPCTR3;                      /*  THLPCTR3        */
-    union iodefine_reg32_t  THLPCTR4;                      /*  THLPCTR4        */
-    
-    volatile uint8_t   dummy176[12];                           /*                  */
-#define RSCAN0_GTINTSTS0_COUNT 2
-    union iodefine_reg32_t  GTINTSTS0;                     /*  GTINTSTS0       */
-    union iodefine_reg32_t  GTINTSTS1;                     /*  GTINTSTS1       */
-    union iodefine_reg32_t  GTSTCFG;                       /*  GTSTCFG         */
-    union iodefine_reg32_t  GTSTCTR;                       /*  GTSTCTR         */
-    
-    volatile uint8_t   dummy177[12];                           /*                  */
-    union iodefine_reg32_16_t  GLOCKK;                     /*  GLOCKK          */
-    
-    volatile uint8_t   dummy178[128];                          /*                  */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID0;                       /*  GAFLID0         */
-    union iodefine_reg32_t  GAFLM0;                        /*  GAFLM0          */
-    union iodefine_reg32_t  GAFLP00;                       /*  GAFLP00         */
-    union iodefine_reg32_t  GAFLP10;                       /*  GAFLP10         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID1;                       /*  GAFLID1         */
-    union iodefine_reg32_t  GAFLM1;                        /*  GAFLM1          */
-    union iodefine_reg32_t  GAFLP01;                       /*  GAFLP01         */
-    union iodefine_reg32_t  GAFLP11;                       /*  GAFLP11         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID2;                       /*  GAFLID2         */
-    union iodefine_reg32_t  GAFLM2;                        /*  GAFLM2          */
-    union iodefine_reg32_t  GAFLP02;                       /*  GAFLP02         */
-    union iodefine_reg32_t  GAFLP12;                       /*  GAFLP12         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID3;                       /*  GAFLID3         */
-    union iodefine_reg32_t  GAFLM3;                        /*  GAFLM3          */
-    union iodefine_reg32_t  GAFLP03;                       /*  GAFLP03         */
-    union iodefine_reg32_t  GAFLP13;                       /*  GAFLP13         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID4;                       /*  GAFLID4         */
-    union iodefine_reg32_t  GAFLM4;                        /*  GAFLM4          */
-    union iodefine_reg32_t  GAFLP04;                       /*  GAFLP04         */
-    union iodefine_reg32_t  GAFLP14;                       /*  GAFLP14         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID5;                       /*  GAFLID5         */
-    union iodefine_reg32_t  GAFLM5;                        /*  GAFLM5          */
-    union iodefine_reg32_t  GAFLP05;                       /*  GAFLP05         */
-    union iodefine_reg32_t  GAFLP15;                       /*  GAFLP15         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID6;                       /*  GAFLID6         */
-    union iodefine_reg32_t  GAFLM6;                        /*  GAFLM6          */
-    union iodefine_reg32_t  GAFLP06;                       /*  GAFLP06         */
-    union iodefine_reg32_t  GAFLP16;                       /*  GAFLP16         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID7;                       /*  GAFLID7         */
-    union iodefine_reg32_t  GAFLM7;                        /*  GAFLM7          */
-    union iodefine_reg32_t  GAFLP07;                       /*  GAFLP07         */
-    union iodefine_reg32_t  GAFLP17;                       /*  GAFLP17         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID8;                       /*  GAFLID8         */
-    union iodefine_reg32_t  GAFLM8;                        /*  GAFLM8          */
-    union iodefine_reg32_t  GAFLP08;                       /*  GAFLP08         */
-    union iodefine_reg32_t  GAFLP18;                       /*  GAFLP18         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID9;                       /*  GAFLID9         */
-    union iodefine_reg32_t  GAFLM9;                        /*  GAFLM9          */
-    union iodefine_reg32_t  GAFLP09;                       /*  GAFLP09         */
-    union iodefine_reg32_t  GAFLP19;                       /*  GAFLP19         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID10;                      /*  GAFLID10        */
-    union iodefine_reg32_t  GAFLM10;                       /*  GAFLM10         */
-    union iodefine_reg32_t  GAFLP010;                      /*  GAFLP010        */
-    union iodefine_reg32_t  GAFLP110;                      /*  GAFLP110        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID11;                      /*  GAFLID11        */
-    union iodefine_reg32_t  GAFLM11;                       /*  GAFLM11         */
-    union iodefine_reg32_t  GAFLP011;                      /*  GAFLP011        */
-    union iodefine_reg32_t  GAFLP111;                      /*  GAFLP111        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID12;                      /*  GAFLID12        */
-    union iodefine_reg32_t  GAFLM12;                       /*  GAFLM12         */
-    union iodefine_reg32_t  GAFLP012;                      /*  GAFLP012        */
-    union iodefine_reg32_t  GAFLP112;                      /*  GAFLP112        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID13;                      /*  GAFLID13        */
-    union iodefine_reg32_t  GAFLM13;                       /*  GAFLM13         */
-    union iodefine_reg32_t  GAFLP013;                      /*  GAFLP013        */
-    union iodefine_reg32_t  GAFLP113;                      /*  GAFLP113        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID14;                      /*  GAFLID14        */
-    union iodefine_reg32_t  GAFLM14;                       /*  GAFLM14         */
-    union iodefine_reg32_t  GAFLP014;                      /*  GAFLP014        */
-    union iodefine_reg32_t  GAFLP114;                      /*  GAFLP114        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID15;                      /*  GAFLID15        */
-    union iodefine_reg32_t  GAFLM15;                       /*  GAFLM15         */
-    union iodefine_reg32_t  GAFLP015;                      /*  GAFLP015        */
-    union iodefine_reg32_t  GAFLP115;                      /*  GAFLP115        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID0;                         /*  RMID0           */
-    union iodefine_reg32_t  RMPTR0;                        /*  RMPTR0          */
-    union iodefine_reg32_t  RMDF00;                        /*  RMDF00          */
-    union iodefine_reg32_t  RMDF10;                        /*  RMDF10          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID1;                         /*  RMID1           */
-    union iodefine_reg32_t  RMPTR1;                        /*  RMPTR1          */
-    union iodefine_reg32_t  RMDF01;                        /*  RMDF01          */
-    union iodefine_reg32_t  RMDF11;                        /*  RMDF11          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID2;                         /*  RMID2           */
-    union iodefine_reg32_t  RMPTR2;                        /*  RMPTR2          */
-    union iodefine_reg32_t  RMDF02;                        /*  RMDF02          */
-    union iodefine_reg32_t  RMDF12;                        /*  RMDF12          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID3;                         /*  RMID3           */
-    union iodefine_reg32_t  RMPTR3;                        /*  RMPTR3          */
-    union iodefine_reg32_t  RMDF03;                        /*  RMDF03          */
-    union iodefine_reg32_t  RMDF13;                        /*  RMDF13          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID4;                         /*  RMID4           */
-    union iodefine_reg32_t  RMPTR4;                        /*  RMPTR4          */
-    union iodefine_reg32_t  RMDF04;                        /*  RMDF04          */
-    union iodefine_reg32_t  RMDF14;                        /*  RMDF14          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID5;                         /*  RMID5           */
-    union iodefine_reg32_t  RMPTR5;                        /*  RMPTR5          */
-    union iodefine_reg32_t  RMDF05;                        /*  RMDF05          */
-    union iodefine_reg32_t  RMDF15;                        /*  RMDF15          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID6;                         /*  RMID6           */
-    union iodefine_reg32_t  RMPTR6;                        /*  RMPTR6          */
-    union iodefine_reg32_t  RMDF06;                        /*  RMDF06          */
-    union iodefine_reg32_t  RMDF16;                        /*  RMDF16          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID7;                         /*  RMID7           */
-    union iodefine_reg32_t  RMPTR7;                        /*  RMPTR7          */
-    union iodefine_reg32_t  RMDF07;                        /*  RMDF07          */
-    union iodefine_reg32_t  RMDF17;                        /*  RMDF17          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID8;                         /*  RMID8           */
-    union iodefine_reg32_t  RMPTR8;                        /*  RMPTR8          */
-    union iodefine_reg32_t  RMDF08;                        /*  RMDF08          */
-    union iodefine_reg32_t  RMDF18;                        /*  RMDF18          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID9;                         /*  RMID9           */
-    union iodefine_reg32_t  RMPTR9;                        /*  RMPTR9          */
-    union iodefine_reg32_t  RMDF09;                        /*  RMDF09          */
-    union iodefine_reg32_t  RMDF19;                        /*  RMDF19          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID10;                        /*  RMID10          */
-    union iodefine_reg32_t  RMPTR10;                       /*  RMPTR10         */
-    union iodefine_reg32_t  RMDF010;                       /*  RMDF010         */
-    union iodefine_reg32_t  RMDF110;                       /*  RMDF110         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID11;                        /*  RMID11          */
-    union iodefine_reg32_t  RMPTR11;                       /*  RMPTR11         */
-    union iodefine_reg32_t  RMDF011;                       /*  RMDF011         */
-    union iodefine_reg32_t  RMDF111;                       /*  RMDF111         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID12;                        /*  RMID12          */
-    union iodefine_reg32_t  RMPTR12;                       /*  RMPTR12         */
-    union iodefine_reg32_t  RMDF012;                       /*  RMDF012         */
-    union iodefine_reg32_t  RMDF112;                       /*  RMDF112         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID13;                        /*  RMID13          */
-    union iodefine_reg32_t  RMPTR13;                       /*  RMPTR13         */
-    union iodefine_reg32_t  RMDF013;                       /*  RMDF013         */
-    union iodefine_reg32_t  RMDF113;                       /*  RMDF113         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID14;                        /*  RMID14          */
-    union iodefine_reg32_t  RMPTR14;                       /*  RMPTR14         */
-    union iodefine_reg32_t  RMDF014;                       /*  RMDF014         */
-    union iodefine_reg32_t  RMDF114;                       /*  RMDF114         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID15;                        /*  RMID15          */
-    union iodefine_reg32_t  RMPTR15;                       /*  RMPTR15         */
-    union iodefine_reg32_t  RMDF015;                       /*  RMDF015         */
-    union iodefine_reg32_t  RMDF115;                       /*  RMDF115         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID16;                        /*  RMID16          */
-    union iodefine_reg32_t  RMPTR16;                       /*  RMPTR16         */
-    union iodefine_reg32_t  RMDF016;                       /*  RMDF016         */
-    union iodefine_reg32_t  RMDF116;                       /*  RMDF116         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID17;                        /*  RMID17          */
-    union iodefine_reg32_t  RMPTR17;                       /*  RMPTR17         */
-    union iodefine_reg32_t  RMDF017;                       /*  RMDF017         */
-    union iodefine_reg32_t  RMDF117;                       /*  RMDF117         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID18;                        /*  RMID18          */
-    union iodefine_reg32_t  RMPTR18;                       /*  RMPTR18         */
-    union iodefine_reg32_t  RMDF018;                       /*  RMDF018         */
-    union iodefine_reg32_t  RMDF118;                       /*  RMDF118         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID19;                        /*  RMID19          */
-    union iodefine_reg32_t  RMPTR19;                       /*  RMPTR19         */
-    union iodefine_reg32_t  RMDF019;                       /*  RMDF019         */
-    union iodefine_reg32_t  RMDF119;                       /*  RMDF119         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID20;                        /*  RMID20          */
-    union iodefine_reg32_t  RMPTR20;                       /*  RMPTR20         */
-    union iodefine_reg32_t  RMDF020;                       /*  RMDF020         */
-    union iodefine_reg32_t  RMDF120;                       /*  RMDF120         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID21;                        /*  RMID21          */
-    union iodefine_reg32_t  RMPTR21;                       /*  RMPTR21         */
-    union iodefine_reg32_t  RMDF021;                       /*  RMDF021         */
-    union iodefine_reg32_t  RMDF121;                       /*  RMDF121         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID22;                        /*  RMID22          */
-    union iodefine_reg32_t  RMPTR22;                       /*  RMPTR22         */
-    union iodefine_reg32_t  RMDF022;                       /*  RMDF022         */
-    union iodefine_reg32_t  RMDF122;                       /*  RMDF122         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID23;                        /*  RMID23          */
-    union iodefine_reg32_t  RMPTR23;                       /*  RMPTR23         */
-    union iodefine_reg32_t  RMDF023;                       /*  RMDF023         */
-    union iodefine_reg32_t  RMDF123;                       /*  RMDF123         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID24;                        /*  RMID24          */
-    union iodefine_reg32_t  RMPTR24;                       /*  RMPTR24         */
-    union iodefine_reg32_t  RMDF024;                       /*  RMDF024         */
-    union iodefine_reg32_t  RMDF124;                       /*  RMDF124         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID25;                        /*  RMID25          */
-    union iodefine_reg32_t  RMPTR25;                       /*  RMPTR25         */
-    union iodefine_reg32_t  RMDF025;                       /*  RMDF025         */
-    union iodefine_reg32_t  RMDF125;                       /*  RMDF125         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID26;                        /*  RMID26          */
-    union iodefine_reg32_t  RMPTR26;                       /*  RMPTR26         */
-    union iodefine_reg32_t  RMDF026;                       /*  RMDF026         */
-    union iodefine_reg32_t  RMDF126;                       /*  RMDF126         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID27;                        /*  RMID27          */
-    union iodefine_reg32_t  RMPTR27;                       /*  RMPTR27         */
-    union iodefine_reg32_t  RMDF027;                       /*  RMDF027         */
-    union iodefine_reg32_t  RMDF127;                       /*  RMDF127         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID28;                        /*  RMID28          */
-    union iodefine_reg32_t  RMPTR28;                       /*  RMPTR28         */
-    union iodefine_reg32_t  RMDF028;                       /*  RMDF028         */
-    union iodefine_reg32_t  RMDF128;                       /*  RMDF128         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID29;                        /*  RMID29          */
-    union iodefine_reg32_t  RMPTR29;                       /*  RMPTR29         */
-    union iodefine_reg32_t  RMDF029;                       /*  RMDF029         */
-    union iodefine_reg32_t  RMDF129;                       /*  RMDF129         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID30;                        /*  RMID30          */
-    union iodefine_reg32_t  RMPTR30;                       /*  RMPTR30         */
-    union iodefine_reg32_t  RMDF030;                       /*  RMDF030         */
-    union iodefine_reg32_t  RMDF130;                       /*  RMDF130         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID31;                        /*  RMID31          */
-    union iodefine_reg32_t  RMPTR31;                       /*  RMPTR31         */
-    union iodefine_reg32_t  RMDF031;                       /*  RMDF031         */
-    union iodefine_reg32_t  RMDF131;                       /*  RMDF131         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID32;                        /*  RMID32          */
-    union iodefine_reg32_t  RMPTR32;                       /*  RMPTR32         */
-    union iodefine_reg32_t  RMDF032;                       /*  RMDF032         */
-    union iodefine_reg32_t  RMDF132;                       /*  RMDF132         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID33;                        /*  RMID33          */
-    union iodefine_reg32_t  RMPTR33;                       /*  RMPTR33         */
-    union iodefine_reg32_t  RMDF033;                       /*  RMDF033         */
-    union iodefine_reg32_t  RMDF133;                       /*  RMDF133         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID34;                        /*  RMID34          */
-    union iodefine_reg32_t  RMPTR34;                       /*  RMPTR34         */
-    union iodefine_reg32_t  RMDF034;                       /*  RMDF034         */
-    union iodefine_reg32_t  RMDF134;                       /*  RMDF134         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID35;                        /*  RMID35          */
-    union iodefine_reg32_t  RMPTR35;                       /*  RMPTR35         */
-    union iodefine_reg32_t  RMDF035;                       /*  RMDF035         */
-    union iodefine_reg32_t  RMDF135;                       /*  RMDF135         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID36;                        /*  RMID36          */
-    union iodefine_reg32_t  RMPTR36;                       /*  RMPTR36         */
-    union iodefine_reg32_t  RMDF036;                       /*  RMDF036         */
-    union iodefine_reg32_t  RMDF136;                       /*  RMDF136         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID37;                        /*  RMID37          */
-    union iodefine_reg32_t  RMPTR37;                       /*  RMPTR37         */
-    union iodefine_reg32_t  RMDF037;                       /*  RMDF037         */
-    union iodefine_reg32_t  RMDF137;                       /*  RMDF137         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID38;                        /*  RMID38          */
-    union iodefine_reg32_t  RMPTR38;                       /*  RMPTR38         */
-    union iodefine_reg32_t  RMDF038;                       /*  RMDF038         */
-    union iodefine_reg32_t  RMDF138;                       /*  RMDF138         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID39;                        /*  RMID39          */
-    union iodefine_reg32_t  RMPTR39;                       /*  RMPTR39         */
-    union iodefine_reg32_t  RMDF039;                       /*  RMDF039         */
-    union iodefine_reg32_t  RMDF139;                       /*  RMDF139         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID40;                        /*  RMID40          */
-    union iodefine_reg32_t  RMPTR40;                       /*  RMPTR40         */
-    union iodefine_reg32_t  RMDF040;                       /*  RMDF040         */
-    union iodefine_reg32_t  RMDF140;                       /*  RMDF140         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID41;                        /*  RMID41          */
-    union iodefine_reg32_t  RMPTR41;                       /*  RMPTR41         */
-    union iodefine_reg32_t  RMDF041;                       /*  RMDF041         */
-    union iodefine_reg32_t  RMDF141;                       /*  RMDF141         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID42;                        /*  RMID42          */
-    union iodefine_reg32_t  RMPTR42;                       /*  RMPTR42         */
-    union iodefine_reg32_t  RMDF042;                       /*  RMDF042         */
-    union iodefine_reg32_t  RMDF142;                       /*  RMDF142         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID43;                        /*  RMID43          */
-    union iodefine_reg32_t  RMPTR43;                       /*  RMPTR43         */
-    union iodefine_reg32_t  RMDF043;                       /*  RMDF043         */
-    union iodefine_reg32_t  RMDF143;                       /*  RMDF143         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID44;                        /*  RMID44          */
-    union iodefine_reg32_t  RMPTR44;                       /*  RMPTR44         */
-    union iodefine_reg32_t  RMDF044;                       /*  RMDF044         */
-    union iodefine_reg32_t  RMDF144;                       /*  RMDF144         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID45;                        /*  RMID45          */
-    union iodefine_reg32_t  RMPTR45;                       /*  RMPTR45         */
-    union iodefine_reg32_t  RMDF045;                       /*  RMDF045         */
-    union iodefine_reg32_t  RMDF145;                       /*  RMDF145         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID46;                        /*  RMID46          */
-    union iodefine_reg32_t  RMPTR46;                       /*  RMPTR46         */
-    union iodefine_reg32_t  RMDF046;                       /*  RMDF046         */
-    union iodefine_reg32_t  RMDF146;                       /*  RMDF146         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID47;                        /*  RMID47          */
-    union iodefine_reg32_t  RMPTR47;                       /*  RMPTR47         */
-    union iodefine_reg32_t  RMDF047;                       /*  RMDF047         */
-    union iodefine_reg32_t  RMDF147;                       /*  RMDF147         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID48;                        /*  RMID48          */
-    union iodefine_reg32_t  RMPTR48;                       /*  RMPTR48         */
-    union iodefine_reg32_t  RMDF048;                       /*  RMDF048         */
-    union iodefine_reg32_t  RMDF148;                       /*  RMDF148         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID49;                        /*  RMID49          */
-    union iodefine_reg32_t  RMPTR49;                       /*  RMPTR49         */
-    union iodefine_reg32_t  RMDF049;                       /*  RMDF049         */
-    union iodefine_reg32_t  RMDF149;                       /*  RMDF149         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID50;                        /*  RMID50          */
-    union iodefine_reg32_t  RMPTR50;                       /*  RMPTR50         */
-    union iodefine_reg32_t  RMDF050;                       /*  RMDF050         */
-    union iodefine_reg32_t  RMDF150;                       /*  RMDF150         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID51;                        /*  RMID51          */
-    union iodefine_reg32_t  RMPTR51;                       /*  RMPTR51         */
-    union iodefine_reg32_t  RMDF051;                       /*  RMDF051         */
-    union iodefine_reg32_t  RMDF151;                       /*  RMDF151         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID52;                        /*  RMID52          */
-    union iodefine_reg32_t  RMPTR52;                       /*  RMPTR52         */
-    union iodefine_reg32_t  RMDF052;                       /*  RMDF052         */
-    union iodefine_reg32_t  RMDF152;                       /*  RMDF152         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID53;                        /*  RMID53          */
-    union iodefine_reg32_t  RMPTR53;                       /*  RMPTR53         */
-    union iodefine_reg32_t  RMDF053;                       /*  RMDF053         */
-    union iodefine_reg32_t  RMDF153;                       /*  RMDF153         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID54;                        /*  RMID54          */
-    union iodefine_reg32_t  RMPTR54;                       /*  RMPTR54         */
-    union iodefine_reg32_t  RMDF054;                       /*  RMDF054         */
-    union iodefine_reg32_t  RMDF154;                       /*  RMDF154         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID55;                        /*  RMID55          */
-    union iodefine_reg32_t  RMPTR55;                       /*  RMPTR55         */
-    union iodefine_reg32_t  RMDF055;                       /*  RMDF055         */
-    union iodefine_reg32_t  RMDF155;                       /*  RMDF155         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID56;                        /*  RMID56          */
-    union iodefine_reg32_t  RMPTR56;                       /*  RMPTR56         */
-    union iodefine_reg32_t  RMDF056;                       /*  RMDF056         */
-    union iodefine_reg32_t  RMDF156;                       /*  RMDF156         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID57;                        /*  RMID57          */
-    union iodefine_reg32_t  RMPTR57;                       /*  RMPTR57         */
-    union iodefine_reg32_t  RMDF057;                       /*  RMDF057         */
-    union iodefine_reg32_t  RMDF157;                       /*  RMDF157         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID58;                        /*  RMID58          */
-    union iodefine_reg32_t  RMPTR58;                       /*  RMPTR58         */
-    union iodefine_reg32_t  RMDF058;                       /*  RMDF058         */
-    union iodefine_reg32_t  RMDF158;                       /*  RMDF158         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID59;                        /*  RMID59          */
-    union iodefine_reg32_t  RMPTR59;                       /*  RMPTR59         */
-    union iodefine_reg32_t  RMDF059;                       /*  RMDF059         */
-    union iodefine_reg32_t  RMDF159;                       /*  RMDF159         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID60;                        /*  RMID60          */
-    union iodefine_reg32_t  RMPTR60;                       /*  RMPTR60         */
-    union iodefine_reg32_t  RMDF060;                       /*  RMDF060         */
-    union iodefine_reg32_t  RMDF160;                       /*  RMDF160         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID61;                        /*  RMID61          */
-    union iodefine_reg32_t  RMPTR61;                       /*  RMPTR61         */
-    union iodefine_reg32_t  RMDF061;                       /*  RMDF061         */
-    union iodefine_reg32_t  RMDF161;                       /*  RMDF161         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID62;                        /*  RMID62          */
-    union iodefine_reg32_t  RMPTR62;                       /*  RMPTR62         */
-    union iodefine_reg32_t  RMDF062;                       /*  RMDF062         */
-    union iodefine_reg32_t  RMDF162;                       /*  RMDF162         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID63;                        /*  RMID63          */
-    union iodefine_reg32_t  RMPTR63;                       /*  RMPTR63         */
-    union iodefine_reg32_t  RMDF063;                       /*  RMDF063         */
-    union iodefine_reg32_t  RMDF163;                       /*  RMDF163         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID64;                        /*  RMID64          */
-    union iodefine_reg32_t  RMPTR64;                       /*  RMPTR64         */
-    union iodefine_reg32_t  RMDF064;                       /*  RMDF064         */
-    union iodefine_reg32_t  RMDF164;                       /*  RMDF164         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID65;                        /*  RMID65          */
-    union iodefine_reg32_t  RMPTR65;                       /*  RMPTR65         */
-    union iodefine_reg32_t  RMDF065;                       /*  RMDF065         */
-    union iodefine_reg32_t  RMDF165;                       /*  RMDF165         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID66;                        /*  RMID66          */
-    union iodefine_reg32_t  RMPTR66;                       /*  RMPTR66         */
-    union iodefine_reg32_t  RMDF066;                       /*  RMDF066         */
-    union iodefine_reg32_t  RMDF166;                       /*  RMDF166         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID67;                        /*  RMID67          */
-    union iodefine_reg32_t  RMPTR67;                       /*  RMPTR67         */
-    union iodefine_reg32_t  RMDF067;                       /*  RMDF067         */
-    union iodefine_reg32_t  RMDF167;                       /*  RMDF167         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID68;                        /*  RMID68          */
-    union iodefine_reg32_t  RMPTR68;                       /*  RMPTR68         */
-    union iodefine_reg32_t  RMDF068;                       /*  RMDF068         */
-    union iodefine_reg32_t  RMDF168;                       /*  RMDF168         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID69;                        /*  RMID69          */
-    union iodefine_reg32_t  RMPTR69;                       /*  RMPTR69         */
-    union iodefine_reg32_t  RMDF069;                       /*  RMDF069         */
-    union iodefine_reg32_t  RMDF169;                       /*  RMDF169         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID70;                        /*  RMID70          */
-    union iodefine_reg32_t  RMPTR70;                       /*  RMPTR70         */
-    union iodefine_reg32_t  RMDF070;                       /*  RMDF070         */
-    union iodefine_reg32_t  RMDF170;                       /*  RMDF170         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID71;                        /*  RMID71          */
-    union iodefine_reg32_t  RMPTR71;                       /*  RMPTR71         */
-    union iodefine_reg32_t  RMDF071;                       /*  RMDF071         */
-    union iodefine_reg32_t  RMDF171;                       /*  RMDF171         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID72;                        /*  RMID72          */
-    union iodefine_reg32_t  RMPTR72;                       /*  RMPTR72         */
-    union iodefine_reg32_t  RMDF072;                       /*  RMDF072         */
-    union iodefine_reg32_t  RMDF172;                       /*  RMDF172         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID73;                        /*  RMID73          */
-    union iodefine_reg32_t  RMPTR73;                       /*  RMPTR73         */
-    union iodefine_reg32_t  RMDF073;                       /*  RMDF073         */
-    union iodefine_reg32_t  RMDF173;                       /*  RMDF173         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID74;                        /*  RMID74          */
-    union iodefine_reg32_t  RMPTR74;                       /*  RMPTR74         */
-    union iodefine_reg32_t  RMDF074;                       /*  RMDF074         */
-    union iodefine_reg32_t  RMDF174;                       /*  RMDF174         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID75;                        /*  RMID75          */
-    union iodefine_reg32_t  RMPTR75;                       /*  RMPTR75         */
-    union iodefine_reg32_t  RMDF075;                       /*  RMDF075         */
-    union iodefine_reg32_t  RMDF175;                       /*  RMDF175         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID76;                        /*  RMID76          */
-    union iodefine_reg32_t  RMPTR76;                       /*  RMPTR76         */
-    union iodefine_reg32_t  RMDF076;                       /*  RMDF076         */
-    union iodefine_reg32_t  RMDF176;                       /*  RMDF176         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID77;                        /*  RMID77          */
-    union iodefine_reg32_t  RMPTR77;                       /*  RMPTR77         */
-    union iodefine_reg32_t  RMDF077;                       /*  RMDF077         */
-    union iodefine_reg32_t  RMDF177;                       /*  RMDF177         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID78;                        /*  RMID78          */
-    union iodefine_reg32_t  RMPTR78;                       /*  RMPTR78         */
-    union iodefine_reg32_t  RMDF078;                       /*  RMDF078         */
-    union iodefine_reg32_t  RMDF178;                       /*  RMDF178         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID79;                        /*  RMID79          */
-    union iodefine_reg32_t  RMPTR79;                       /*  RMPTR79         */
-    union iodefine_reg32_t  RMDF079;                       /*  RMDF079         */
-    union iodefine_reg32_t  RMDF179;                       /*  RMDF179         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-    volatile uint8_t   dummy179[768];                          /*                  */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID0;                         /*  RFID0           */
-    union iodefine_reg32_t  RFPTR0;                        /*  RFPTR0          */
-    union iodefine_reg32_t  RFDF00;                        /*  RFDF00          */
-    union iodefine_reg32_t  RFDF10;                        /*  RFDF10          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID1;                         /*  RFID1           */
-    union iodefine_reg32_t  RFPTR1;                        /*  RFPTR1          */
-    union iodefine_reg32_t  RFDF01;                        /*  RFDF01          */
-    union iodefine_reg32_t  RFDF11;                        /*  RFDF11          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID2;                         /*  RFID2           */
-    union iodefine_reg32_t  RFPTR2;                        /*  RFPTR2          */
-    union iodefine_reg32_t  RFDF02;                        /*  RFDF02          */
-    union iodefine_reg32_t  RFDF12;                        /*  RFDF12          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID3;                         /*  RFID3           */
-    union iodefine_reg32_t  RFPTR3;                        /*  RFPTR3          */
-    union iodefine_reg32_t  RFDF03;                        /*  RFDF03          */
-    union iodefine_reg32_t  RFDF13;                        /*  RFDF13          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID4;                         /*  RFID4           */
-    union iodefine_reg32_t  RFPTR4;                        /*  RFPTR4          */
-    union iodefine_reg32_t  RFDF04;                        /*  RFDF04          */
-    union iodefine_reg32_t  RFDF14;                        /*  RFDF14          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID5;                         /*  RFID5           */
-    union iodefine_reg32_t  RFPTR5;                        /*  RFPTR5          */
-    union iodefine_reg32_t  RFDF05;                        /*  RFDF05          */
-    union iodefine_reg32_t  RFDF15;                        /*  RFDF15          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID6;                         /*  RFID6           */
-    union iodefine_reg32_t  RFPTR6;                        /*  RFPTR6          */
-    union iodefine_reg32_t  RFDF06;                        /*  RFDF06          */
-    union iodefine_reg32_t  RFDF16;                        /*  RFDF16          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID7;                         /*  RFID7           */
-    union iodefine_reg32_t  RFPTR7;                        /*  RFPTR7          */
-    union iodefine_reg32_t  RFDF07;                        /*  RFDF07          */
-    union iodefine_reg32_t  RFDF17;                        /*  RFDF17          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID0;                         /*  CFID0           */
-    union iodefine_reg32_t  CFPTR0;                        /*  CFPTR0          */
-    union iodefine_reg32_t  CFDF00;                        /*  CFDF00          */
-    union iodefine_reg32_t  CFDF10;                        /*  CFDF10          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID1;                         /*  CFID1           */
-    union iodefine_reg32_t  CFPTR1;                        /*  CFPTR1          */
-    union iodefine_reg32_t  CFDF01;                        /*  CFDF01          */
-    union iodefine_reg32_t  CFDF11;                        /*  CFDF11          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID2;                         /*  CFID2           */
-    union iodefine_reg32_t  CFPTR2;                        /*  CFPTR2          */
-    union iodefine_reg32_t  CFDF02;                        /*  CFDF02          */
-    union iodefine_reg32_t  CFDF12;                        /*  CFDF12          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID3;                         /*  CFID3           */
-    union iodefine_reg32_t  CFPTR3;                        /*  CFPTR3          */
-    union iodefine_reg32_t  CFDF03;                        /*  CFDF03          */
-    union iodefine_reg32_t  CFDF13;                        /*  CFDF13          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID4;                         /*  CFID4           */
-    union iodefine_reg32_t  CFPTR4;                        /*  CFPTR4          */
-    union iodefine_reg32_t  CFDF04;                        /*  CFDF04          */
-    union iodefine_reg32_t  CFDF14;                        /*  CFDF14          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID5;                         /*  CFID5           */
-    union iodefine_reg32_t  CFPTR5;                        /*  CFPTR5          */
-    union iodefine_reg32_t  CFDF05;                        /*  CFDF05          */
-    union iodefine_reg32_t  CFDF15;                        /*  CFDF15          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID6;                         /*  CFID6           */
-    union iodefine_reg32_t  CFPTR6;                        /*  CFPTR6          */
-    union iodefine_reg32_t  CFDF06;                        /*  CFDF06          */
-    union iodefine_reg32_t  CFDF16;                        /*  CFDF16          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID7;                         /*  CFID7           */
-    union iodefine_reg32_t  CFPTR7;                        /*  CFPTR7          */
-    union iodefine_reg32_t  CFDF07;                        /*  CFDF07          */
-    union iodefine_reg32_t  CFDF17;                        /*  CFDF17          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID8;                         /*  CFID8           */
-    union iodefine_reg32_t  CFPTR8;                        /*  CFPTR8          */
-    union iodefine_reg32_t  CFDF08;                        /*  CFDF08          */
-    union iodefine_reg32_t  CFDF18;                        /*  CFDF18          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID9;                         /*  CFID9           */
-    union iodefine_reg32_t  CFPTR9;                        /*  CFPTR9          */
-    union iodefine_reg32_t  CFDF09;                        /*  CFDF09          */
-    union iodefine_reg32_t  CFDF19;                        /*  CFDF19          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID10;                        /*  CFID10          */
-    union iodefine_reg32_t  CFPTR10;                       /*  CFPTR10         */
-    union iodefine_reg32_t  CFDF010;                       /*  CFDF010         */
-    union iodefine_reg32_t  CFDF110;                       /*  CFDF110         */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID11;                        /*  CFID11          */
-    union iodefine_reg32_t  CFPTR11;                       /*  CFPTR11         */
-    union iodefine_reg32_t  CFDF011;                       /*  CFDF011         */
-    union iodefine_reg32_t  CFDF111;                       /*  CFDF111         */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID12;                        /*  CFID12          */
-    union iodefine_reg32_t  CFPTR12;                       /*  CFPTR12         */
-    union iodefine_reg32_t  CFDF012;                       /*  CFDF012         */
-    union iodefine_reg32_t  CFDF112;                       /*  CFDF112         */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID13;                        /*  CFID13          */
-    union iodefine_reg32_t  CFPTR13;                       /*  CFPTR13         */
-    union iodefine_reg32_t  CFDF013;                       /*  CFDF013         */
-    union iodefine_reg32_t  CFDF113;                       /*  CFDF113         */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID14;                        /*  CFID14          */
-    union iodefine_reg32_t  CFPTR14;                       /*  CFPTR14         */
-    union iodefine_reg32_t  CFDF014;                       /*  CFDF014         */
-    union iodefine_reg32_t  CFDF114;                       /*  CFDF114         */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-    volatile uint8_t   dummy180[144];                          /*                  */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID0;                         /*  TMID0           */
-    union iodefine_reg32_t  TMPTR0;                        /*  TMPTR0          */
-    union iodefine_reg32_t  TMDF00;                        /*  TMDF00          */
-    union iodefine_reg32_t  TMDF10;                        /*  TMDF10          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID1;                         /*  TMID1           */
-    union iodefine_reg32_t  TMPTR1;                        /*  TMPTR1          */
-    union iodefine_reg32_t  TMDF01;                        /*  TMDF01          */
-    union iodefine_reg32_t  TMDF11;                        /*  TMDF11          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID2;                         /*  TMID2           */
-    union iodefine_reg32_t  TMPTR2;                        /*  TMPTR2          */
-    union iodefine_reg32_t  TMDF02;                        /*  TMDF02          */
-    union iodefine_reg32_t  TMDF12;                        /*  TMDF12          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID3;                         /*  TMID3           */
-    union iodefine_reg32_t  TMPTR3;                        /*  TMPTR3          */
-    union iodefine_reg32_t  TMDF03;                        /*  TMDF03          */
-    union iodefine_reg32_t  TMDF13;                        /*  TMDF13          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID4;                         /*  TMID4           */
-    union iodefine_reg32_t  TMPTR4;                        /*  TMPTR4          */
-    union iodefine_reg32_t  TMDF04;                        /*  TMDF04          */
-    union iodefine_reg32_t  TMDF14;                        /*  TMDF14          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID5;                         /*  TMID5           */
-    union iodefine_reg32_t  TMPTR5;                        /*  TMPTR5          */
-    union iodefine_reg32_t  TMDF05;                        /*  TMDF05          */
-    union iodefine_reg32_t  TMDF15;                        /*  TMDF15          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID6;                         /*  TMID6           */
-    union iodefine_reg32_t  TMPTR6;                        /*  TMPTR6          */
-    union iodefine_reg32_t  TMDF06;                        /*  TMDF06          */
-    union iodefine_reg32_t  TMDF16;                        /*  TMDF16          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID7;                         /*  TMID7           */
-    union iodefine_reg32_t  TMPTR7;                        /*  TMPTR7          */
-    union iodefine_reg32_t  TMDF07;                        /*  TMDF07          */
-    union iodefine_reg32_t  TMDF17;                        /*  TMDF17          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID8;                         /*  TMID8           */
-    union iodefine_reg32_t  TMPTR8;                        /*  TMPTR8          */
-    union iodefine_reg32_t  TMDF08;                        /*  TMDF08          */
-    union iodefine_reg32_t  TMDF18;                        /*  TMDF18          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID9;                         /*  TMID9           */
-    union iodefine_reg32_t  TMPTR9;                        /*  TMPTR9          */
-    union iodefine_reg32_t  TMDF09;                        /*  TMDF09          */
-    union iodefine_reg32_t  TMDF19;                        /*  TMDF19          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID10;                        /*  TMID10          */
-    union iodefine_reg32_t  TMPTR10;                       /*  TMPTR10         */
-    union iodefine_reg32_t  TMDF010;                       /*  TMDF010         */
-    union iodefine_reg32_t  TMDF110;                       /*  TMDF110         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID11;                        /*  TMID11          */
-    union iodefine_reg32_t  TMPTR11;                       /*  TMPTR11         */
-    union iodefine_reg32_t  TMDF011;                       /*  TMDF011         */
-    union iodefine_reg32_t  TMDF111;                       /*  TMDF111         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID12;                        /*  TMID12          */
-    union iodefine_reg32_t  TMPTR12;                       /*  TMPTR12         */
-    union iodefine_reg32_t  TMDF012;                       /*  TMDF012         */
-    union iodefine_reg32_t  TMDF112;                       /*  TMDF112         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID13;                        /*  TMID13          */
-    union iodefine_reg32_t  TMPTR13;                       /*  TMPTR13         */
-    union iodefine_reg32_t  TMDF013;                       /*  TMDF013         */
-    union iodefine_reg32_t  TMDF113;                       /*  TMDF113         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID14;                        /*  TMID14          */
-    union iodefine_reg32_t  TMPTR14;                       /*  TMPTR14         */
-    union iodefine_reg32_t  TMDF014;                       /*  TMDF014         */
-    union iodefine_reg32_t  TMDF114;                       /*  TMDF114         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID15;                        /*  TMID15          */
-    union iodefine_reg32_t  TMPTR15;                       /*  TMPTR15         */
-    union iodefine_reg32_t  TMDF015;                       /*  TMDF015         */
-    union iodefine_reg32_t  TMDF115;                       /*  TMDF115         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID16;                        /*  TMID16          */
-    union iodefine_reg32_t  TMPTR16;                       /*  TMPTR16         */
-    union iodefine_reg32_t  TMDF016;                       /*  TMDF016         */
-    union iodefine_reg32_t  TMDF116;                       /*  TMDF116         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID17;                        /*  TMID17          */
-    union iodefine_reg32_t  TMPTR17;                       /*  TMPTR17         */
-    union iodefine_reg32_t  TMDF017;                       /*  TMDF017         */
-    union iodefine_reg32_t  TMDF117;                       /*  TMDF117         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID18;                        /*  TMID18          */
-    union iodefine_reg32_t  TMPTR18;                       /*  TMPTR18         */
-    union iodefine_reg32_t  TMDF018;                       /*  TMDF018         */
-    union iodefine_reg32_t  TMDF118;                       /*  TMDF118         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID19;                        /*  TMID19          */
-    union iodefine_reg32_t  TMPTR19;                       /*  TMPTR19         */
-    union iodefine_reg32_t  TMDF019;                       /*  TMDF019         */
-    union iodefine_reg32_t  TMDF119;                       /*  TMDF119         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID20;                        /*  TMID20          */
-    union iodefine_reg32_t  TMPTR20;                       /*  TMPTR20         */
-    union iodefine_reg32_t  TMDF020;                       /*  TMDF020         */
-    union iodefine_reg32_t  TMDF120;                       /*  TMDF120         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID21;                        /*  TMID21          */
-    union iodefine_reg32_t  TMPTR21;                       /*  TMPTR21         */
-    union iodefine_reg32_t  TMDF021;                       /*  TMDF021         */
-    union iodefine_reg32_t  TMDF121;                       /*  TMDF121         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID22;                        /*  TMID22          */
-    union iodefine_reg32_t  TMPTR22;                       /*  TMPTR22         */
-    union iodefine_reg32_t  TMDF022;                       /*  TMDF022         */
-    union iodefine_reg32_t  TMDF122;                       /*  TMDF122         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID23;                        /*  TMID23          */
-    union iodefine_reg32_t  TMPTR23;                       /*  TMPTR23         */
-    union iodefine_reg32_t  TMDF023;                       /*  TMDF023         */
-    union iodefine_reg32_t  TMDF123;                       /*  TMDF123         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID24;                        /*  TMID24          */
-    union iodefine_reg32_t  TMPTR24;                       /*  TMPTR24         */
-    union iodefine_reg32_t  TMDF024;                       /*  TMDF024         */
-    union iodefine_reg32_t  TMDF124;                       /*  TMDF124         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID25;                        /*  TMID25          */
-    union iodefine_reg32_t  TMPTR25;                       /*  TMPTR25         */
-    union iodefine_reg32_t  TMDF025;                       /*  TMDF025         */
-    union iodefine_reg32_t  TMDF125;                       /*  TMDF125         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID26;                        /*  TMID26          */
-    union iodefine_reg32_t  TMPTR26;                       /*  TMPTR26         */
-    union iodefine_reg32_t  TMDF026;                       /*  TMDF026         */
-    union iodefine_reg32_t  TMDF126;                       /*  TMDF126         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID27;                        /*  TMID27          */
-    union iodefine_reg32_t  TMPTR27;                       /*  TMPTR27         */
-    union iodefine_reg32_t  TMDF027;                       /*  TMDF027         */
-    union iodefine_reg32_t  TMDF127;                       /*  TMDF127         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID28;                        /*  TMID28          */
-    union iodefine_reg32_t  TMPTR28;                       /*  TMPTR28         */
-    union iodefine_reg32_t  TMDF028;                       /*  TMDF028         */
-    union iodefine_reg32_t  TMDF128;                       /*  TMDF128         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID29;                        /*  TMID29          */
-    union iodefine_reg32_t  TMPTR29;                       /*  TMPTR29         */
-    union iodefine_reg32_t  TMDF029;                       /*  TMDF029         */
-    union iodefine_reg32_t  TMDF129;                       /*  TMDF129         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID30;                        /*  TMID30          */
-    union iodefine_reg32_t  TMPTR30;                       /*  TMPTR30         */
-    union iodefine_reg32_t  TMDF030;                       /*  TMDF030         */
-    union iodefine_reg32_t  TMDF130;                       /*  TMDF130         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID31;                        /*  TMID31          */
-    union iodefine_reg32_t  TMPTR31;                       /*  TMPTR31         */
-    union iodefine_reg32_t  TMDF031;                       /*  TMDF031         */
-    union iodefine_reg32_t  TMDF131;                       /*  TMDF131         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID32;                        /*  TMID32          */
-    union iodefine_reg32_t  TMPTR32;                       /*  TMPTR32         */
-    union iodefine_reg32_t  TMDF032;                       /*  TMDF032         */
-    union iodefine_reg32_t  TMDF132;                       /*  TMDF132         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID33;                        /*  TMID33          */
-    union iodefine_reg32_t  TMPTR33;                       /*  TMPTR33         */
-    union iodefine_reg32_t  TMDF033;                       /*  TMDF033         */
-    union iodefine_reg32_t  TMDF133;                       /*  TMDF133         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID34;                        /*  TMID34          */
-    union iodefine_reg32_t  TMPTR34;                       /*  TMPTR34         */
-    union iodefine_reg32_t  TMDF034;                       /*  TMDF034         */
-    union iodefine_reg32_t  TMDF134;                       /*  TMDF134         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID35;                        /*  TMID35          */
-    union iodefine_reg32_t  TMPTR35;                       /*  TMPTR35         */
-    union iodefine_reg32_t  TMDF035;                       /*  TMDF035         */
-    union iodefine_reg32_t  TMDF135;                       /*  TMDF135         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID36;                        /*  TMID36          */
-    union iodefine_reg32_t  TMPTR36;                       /*  TMPTR36         */
-    union iodefine_reg32_t  TMDF036;                       /*  TMDF036         */
-    union iodefine_reg32_t  TMDF136;                       /*  TMDF136         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID37;                        /*  TMID37          */
-    union iodefine_reg32_t  TMPTR37;                       /*  TMPTR37         */
-    union iodefine_reg32_t  TMDF037;                       /*  TMDF037         */
-    union iodefine_reg32_t  TMDF137;                       /*  TMDF137         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID38;                        /*  TMID38          */
-    union iodefine_reg32_t  TMPTR38;                       /*  TMPTR38         */
-    union iodefine_reg32_t  TMDF038;                       /*  TMDF038         */
-    union iodefine_reg32_t  TMDF138;                       /*  TMDF138         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID39;                        /*  TMID39          */
-    union iodefine_reg32_t  TMPTR39;                       /*  TMPTR39         */
-    union iodefine_reg32_t  TMDF039;                       /*  TMDF039         */
-    union iodefine_reg32_t  TMDF139;                       /*  TMDF139         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID40;                        /*  TMID40          */
-    union iodefine_reg32_t  TMPTR40;                       /*  TMPTR40         */
-    union iodefine_reg32_t  TMDF040;                       /*  TMDF040         */
-    union iodefine_reg32_t  TMDF140;                       /*  TMDF140         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID41;                        /*  TMID41          */
-    union iodefine_reg32_t  TMPTR41;                       /*  TMPTR41         */
-    union iodefine_reg32_t  TMDF041;                       /*  TMDF041         */
-    union iodefine_reg32_t  TMDF141;                       /*  TMDF141         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID42;                        /*  TMID42          */
-    union iodefine_reg32_t  TMPTR42;                       /*  TMPTR42         */
-    union iodefine_reg32_t  TMDF042;                       /*  TMDF042         */
-    union iodefine_reg32_t  TMDF142;                       /*  TMDF142         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID43;                        /*  TMID43          */
-    union iodefine_reg32_t  TMPTR43;                       /*  TMPTR43         */
-    union iodefine_reg32_t  TMDF043;                       /*  TMDF043         */
-    union iodefine_reg32_t  TMDF143;                       /*  TMDF143         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID44;                        /*  TMID44          */
-    union iodefine_reg32_t  TMPTR44;                       /*  TMPTR44         */
-    union iodefine_reg32_t  TMDF044;                       /*  TMDF044         */
-    union iodefine_reg32_t  TMDF144;                       /*  TMDF144         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID45;                        /*  TMID45          */
-    union iodefine_reg32_t  TMPTR45;                       /*  TMPTR45         */
-    union iodefine_reg32_t  TMDF045;                       /*  TMDF045         */
-    union iodefine_reg32_t  TMDF145;                       /*  TMDF145         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID46;                        /*  TMID46          */
-    union iodefine_reg32_t  TMPTR46;                       /*  TMPTR46         */
-    union iodefine_reg32_t  TMDF046;                       /*  TMDF046         */
-    union iodefine_reg32_t  TMDF146;                       /*  TMDF146         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID47;                        /*  TMID47          */
-    union iodefine_reg32_t  TMPTR47;                       /*  TMPTR47         */
-    union iodefine_reg32_t  TMDF047;                       /*  TMDF047         */
-    union iodefine_reg32_t  TMDF147;                       /*  TMDF147         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID48;                        /*  TMID48          */
-    union iodefine_reg32_t  TMPTR48;                       /*  TMPTR48         */
-    union iodefine_reg32_t  TMDF048;                       /*  TMDF048         */
-    union iodefine_reg32_t  TMDF148;                       /*  TMDF148         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID49;                        /*  TMID49          */
-    union iodefine_reg32_t  TMPTR49;                       /*  TMPTR49         */
-    union iodefine_reg32_t  TMDF049;                       /*  TMDF049         */
-    union iodefine_reg32_t  TMDF149;                       /*  TMDF149         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID50;                        /*  TMID50          */
-    union iodefine_reg32_t  TMPTR50;                       /*  TMPTR50         */
-    union iodefine_reg32_t  TMDF050;                       /*  TMDF050         */
-    union iodefine_reg32_t  TMDF150;                       /*  TMDF150         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID51;                        /*  TMID51          */
-    union iodefine_reg32_t  TMPTR51;                       /*  TMPTR51         */
-    union iodefine_reg32_t  TMDF051;                       /*  TMDF051         */
-    union iodefine_reg32_t  TMDF151;                       /*  TMDF151         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID52;                        /*  TMID52          */
-    union iodefine_reg32_t  TMPTR52;                       /*  TMPTR52         */
-    union iodefine_reg32_t  TMDF052;                       /*  TMDF052         */
-    union iodefine_reg32_t  TMDF152;                       /*  TMDF152         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID53;                        /*  TMID53          */
-    union iodefine_reg32_t  TMPTR53;                       /*  TMPTR53         */
-    union iodefine_reg32_t  TMDF053;                       /*  TMDF053         */
-    union iodefine_reg32_t  TMDF153;                       /*  TMDF153         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID54;                        /*  TMID54          */
-    union iodefine_reg32_t  TMPTR54;                       /*  TMPTR54         */
-    union iodefine_reg32_t  TMDF054;                       /*  TMDF054         */
-    union iodefine_reg32_t  TMDF154;                       /*  TMDF154         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID55;                        /*  TMID55          */
-    union iodefine_reg32_t  TMPTR55;                       /*  TMPTR55         */
-    union iodefine_reg32_t  TMDF055;                       /*  TMDF055         */
-    union iodefine_reg32_t  TMDF155;                       /*  TMDF155         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID56;                        /*  TMID56          */
-    union iodefine_reg32_t  TMPTR56;                       /*  TMPTR56         */
-    union iodefine_reg32_t  TMDF056;                       /*  TMDF056         */
-    union iodefine_reg32_t  TMDF156;                       /*  TMDF156         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID57;                        /*  TMID57          */
-    union iodefine_reg32_t  TMPTR57;                       /*  TMPTR57         */
-    union iodefine_reg32_t  TMDF057;                       /*  TMDF057         */
-    union iodefine_reg32_t  TMDF157;                       /*  TMDF157         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID58;                        /*  TMID58          */
-    union iodefine_reg32_t  TMPTR58;                       /*  TMPTR58         */
-    union iodefine_reg32_t  TMDF058;                       /*  TMDF058         */
-    union iodefine_reg32_t  TMDF158;                       /*  TMDF158         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID59;                        /*  TMID59          */
-    union iodefine_reg32_t  TMPTR59;                       /*  TMPTR59         */
-    union iodefine_reg32_t  TMDF059;                       /*  TMDF059         */
-    union iodefine_reg32_t  TMDF159;                       /*  TMDF159         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID60;                        /*  TMID60          */
-    union iodefine_reg32_t  TMPTR60;                       /*  TMPTR60         */
-    union iodefine_reg32_t  TMDF060;                       /*  TMDF060         */
-    union iodefine_reg32_t  TMDF160;                       /*  TMDF160         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID61;                        /*  TMID61          */
-    union iodefine_reg32_t  TMPTR61;                       /*  TMPTR61         */
-    union iodefine_reg32_t  TMDF061;                       /*  TMDF061         */
-    union iodefine_reg32_t  TMDF161;                       /*  TMDF161         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID62;                        /*  TMID62          */
-    union iodefine_reg32_t  TMPTR62;                       /*  TMPTR62         */
-    union iodefine_reg32_t  TMDF062;                       /*  TMDF062         */
-    union iodefine_reg32_t  TMDF162;                       /*  TMDF162         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID63;                        /*  TMID63          */
-    union iodefine_reg32_t  TMPTR63;                       /*  TMPTR63         */
-    union iodefine_reg32_t  TMDF063;                       /*  TMDF063         */
-    union iodefine_reg32_t  TMDF163;                       /*  TMDF163         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID64;                        /*  TMID64          */
-    union iodefine_reg32_t  TMPTR64;                       /*  TMPTR64         */
-    union iodefine_reg32_t  TMDF064;                       /*  TMDF064         */
-    union iodefine_reg32_t  TMDF164;                       /*  TMDF164         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID65;                        /*  TMID65          */
-    union iodefine_reg32_t  TMPTR65;                       /*  TMPTR65         */
-    union iodefine_reg32_t  TMDF065;                       /*  TMDF065         */
-    union iodefine_reg32_t  TMDF165;                       /*  TMDF165         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID66;                        /*  TMID66          */
-    union iodefine_reg32_t  TMPTR66;                       /*  TMPTR66         */
-    union iodefine_reg32_t  TMDF066;                       /*  TMDF066         */
-    union iodefine_reg32_t  TMDF166;                       /*  TMDF166         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID67;                        /*  TMID67          */
-    union iodefine_reg32_t  TMPTR67;                       /*  TMPTR67         */
-    union iodefine_reg32_t  TMDF067;                       /*  TMDF067         */
-    union iodefine_reg32_t  TMDF167;                       /*  TMDF167         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID68;                        /*  TMID68          */
-    union iodefine_reg32_t  TMPTR68;                       /*  TMPTR68         */
-    union iodefine_reg32_t  TMDF068;                       /*  TMDF068         */
-    union iodefine_reg32_t  TMDF168;                       /*  TMDF168         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID69;                        /*  TMID69          */
-    union iodefine_reg32_t  TMPTR69;                       /*  TMPTR69         */
-    union iodefine_reg32_t  TMDF069;                       /*  TMDF069         */
-    union iodefine_reg32_t  TMDF169;                       /*  TMDF169         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID70;                        /*  TMID70          */
-    union iodefine_reg32_t  TMPTR70;                       /*  TMPTR70         */
-    union iodefine_reg32_t  TMDF070;                       /*  TMDF070         */
-    union iodefine_reg32_t  TMDF170;                       /*  TMDF170         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID71;                        /*  TMID71          */
-    union iodefine_reg32_t  TMPTR71;                       /*  TMPTR71         */
-    union iodefine_reg32_t  TMDF071;                       /*  TMDF071         */
-    union iodefine_reg32_t  TMDF171;                       /*  TMDF171         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID72;                        /*  TMID72          */
-    union iodefine_reg32_t  TMPTR72;                       /*  TMPTR72         */
-    union iodefine_reg32_t  TMDF072;                       /*  TMDF072         */
-    union iodefine_reg32_t  TMDF172;                       /*  TMDF172         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID73;                        /*  TMID73          */
-    union iodefine_reg32_t  TMPTR73;                       /*  TMPTR73         */
-    union iodefine_reg32_t  TMDF073;                       /*  TMDF073         */
-    union iodefine_reg32_t  TMDF173;                       /*  TMDF173         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID74;                        /*  TMID74          */
-    union iodefine_reg32_t  TMPTR74;                       /*  TMPTR74         */
-    union iodefine_reg32_t  TMDF074;                       /*  TMDF074         */
-    union iodefine_reg32_t  TMDF174;                       /*  TMDF174         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID75;                        /*  TMID75          */
-    union iodefine_reg32_t  TMPTR75;                       /*  TMPTR75         */
-    union iodefine_reg32_t  TMDF075;                       /*  TMDF075         */
-    union iodefine_reg32_t  TMDF175;                       /*  TMDF175         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID76;                        /*  TMID76          */
-    union iodefine_reg32_t  TMPTR76;                       /*  TMPTR76         */
-    union iodefine_reg32_t  TMDF076;                       /*  TMDF076         */
-    union iodefine_reg32_t  TMDF176;                       /*  TMDF176         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID77;                        /*  TMID77          */
-    union iodefine_reg32_t  TMPTR77;                       /*  TMPTR77         */
-    union iodefine_reg32_t  TMDF077;                       /*  TMDF077         */
-    union iodefine_reg32_t  TMDF177;                       /*  TMDF177         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID78;                        /*  TMID78          */
-    union iodefine_reg32_t  TMPTR78;                       /*  TMPTR78         */
-    union iodefine_reg32_t  TMDF078;                       /*  TMDF078         */
-    union iodefine_reg32_t  TMDF178;                       /*  TMDF178         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID79;                        /*  TMID79          */
-    union iodefine_reg32_t  TMPTR79;                       /*  TMPTR79         */
-    union iodefine_reg32_t  TMDF079;                       /*  TMDF079         */
-    union iodefine_reg32_t  TMDF179;                       /*  TMDF179         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-    volatile uint8_t   dummy181[768];                          /*                  */
-#define RSCAN0_THLACC0_COUNT 5
-    union iodefine_reg32_t  THLACC0;                       /*  THLACC0         */
-    union iodefine_reg32_t  THLACC1;                       /*  THLACC1         */
-    union iodefine_reg32_t  THLACC2;                       /*  THLACC2         */
-    union iodefine_reg32_t  THLACC3;                       /*  THLACC3         */
-    union iodefine_reg32_t  THLACC4;                       /*  THLACC4         */
-    
-};
-
-
-struct st_rscan_from_rscan0cncfg
-{
-    union iodefine_reg32_t  CnCFG;                         /*  CnCFG           */
-    union iodefine_reg32_t  CnCTR;                         /*  CnCTR           */
-    union iodefine_reg32_t  CnSTS;                         /*  CnSTS           */
-    union iodefine_reg32_t  CnERFL;                        /*  CnERFL          */
-};
-
-
-struct st_rscan_from_rscan0gaflidj
-{
-    union iodefine_reg32_t  GAFLIDj;                       /*  GAFLIDj         */
-    union iodefine_reg32_t  GAFLMj;                        /*  GAFLMj          */
-    union iodefine_reg32_t  GAFLP0j;                       /*  GAFLP0j         */
-    union iodefine_reg32_t  GAFLP1j;                       /*  GAFLP1j         */
-};
-
-
-struct st_rscan_from_rscan0rmidp
-{
-    union iodefine_reg32_t  RMIDp;                         /*  RMIDp           */
-    union iodefine_reg32_t  RMPTRp;                        /*  RMPTRp          */
-    union iodefine_reg32_t  RMDF0p;                        /*  RMDF0p          */
-    union iodefine_reg32_t  RMDF1p;                        /*  RMDF1p          */
-};
-
-
-struct st_rscan_from_rscan0rfidm
-{
-    union iodefine_reg32_t  RFIDm;                         /*  RFIDm           */
-    union iodefine_reg32_t  RFPTRm;                        /*  RFPTRm          */
-    union iodefine_reg32_t  RFDF0m;                        /*  RFDF0m          */
-    union iodefine_reg32_t  RFDF1m;                        /*  RFDF1m          */
-};
-
-
-struct st_rscan_from_rscan0tmidp
-{
-    union iodefine_reg32_t  TMIDp;                         /*  TMIDp           */
-    union iodefine_reg32_t  TMPTRp;                        /*  TMPTRp          */
-    union iodefine_reg32_t  TMDF0p;                        /*  TMDF0p          */
-    union iodefine_reg32_t  TMDF1p;                        /*  TMDF1p          */
-};
-
-
-struct st_rscan_from_rscan0cfidm
-{
-    union iodefine_reg32_t  CFIDm;                         /*  CFIDm           */
-    union iodefine_reg32_t  CFPTRm;                        /*  CFPTRm          */
-    union iodefine_reg32_t  CFDF0m;                        /*  CFDF0m          */
-    union iodefine_reg32_t  CFDF1m;                        /*  CFDF1m          */
-};
-
-
 #define RSCAN0  (*(struct st_rscan0  *)0xE803A000uL) /* RSCAN0 */
 
 
-/* Start of channnel array defines of RSCAN0 */
-
-/* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */
-/*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */
-#define RSCAN_FROM_RSCAN0CFIDm_COUNT  15
-#define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \
+/* Start of channel array defines of RSCAN0 */
+
+/* Channel array defines of RSCAN_FROM_RSCAN0_CFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0_CFIDm[ channel ]->CFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0_CFIDm_COUNT  (15)
+#define RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \
     &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \
@@ -1919,10 +63,10 @@
 #define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */
 
 
-/* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */
-/*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */
-#define RSCAN_FROM_RSCAN0TMIDp_COUNT  80
-#define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \
+/* Channel array defines of RSCAN_FROM_RSCAN0_TMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0_TMIDp[ channel ]->TMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0_TMIDp_COUNT  (80)
+#define RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \
     &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \
@@ -2017,10 +161,10 @@
 #define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */
 
 
-/* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */
-/*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */
-#define RSCAN_FROM_RSCAN0RFIDm_COUNT  8
-#define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \
+/* Channel array defines of RSCAN_FROM_RSCAN0_RFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0_RFIDm[ channel ]->RFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0_RFIDm_COUNT  (8)
+#define RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \
 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
@@ -2034,10 +178,10 @@
 #define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */
 
 
-/* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */
-/*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */
-#define RSCAN_FROM_RSCAN0RMIDp_COUNT  80
-#define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \
+/* Channel array defines of RSCAN_FROM_RSCAN0_RMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0_RMIDp[ channel ]->RMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0_RMIDp_COUNT  (80)
+#define RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \
     &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \
@@ -2132,10 +276,10 @@
 #define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */
 
 
-/* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */
-/*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */
-#define RSCAN_FROM_RSCAN0GAFLIDj_COUNT  16
-#define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \
+/* Channel array defines of RSCAN_FROM_RSCAN0_GAFLIDj */
+/*(Sample) value = RSCAN_FROM_RSCAN0_GAFLIDj[ channel ]->GAFLIDj.UINT32; */
+#define RSCAN_FROM_RSCAN0_GAFLIDj_COUNT  (16)
+#define RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \
     &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \
@@ -2158,10 +302,10 @@
 #define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */
 
 
-/* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */
-/*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */
-#define RSCAN_FROM_RSCAN0CnCFG_COUNT  5
-#define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \
+/* Channel array defines of RSCAN_FROM_RSCAN0_CnCFG */
+/*(Sample) value = RSCAN_FROM_RSCAN0_CnCFG[ channel ]->CnCFG.UINT32; */
+#define RSCAN_FROM_RSCAN0_CnCFG_COUNT  (5)
+#define RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \
 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
@@ -2171,6868 +315,9032 @@
 #define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */
 #define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */
 
-/* End of channnel array defines of RSCAN0 */
-
-
-#define RSCAN0C0CFG RSCAN0.C0CFG.UINT32
-#define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L]
-#define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL]
-#define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH]
-#define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H]
-#define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL]
-#define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH]
-#define RSCAN0C0CTR RSCAN0.C0CTR.UINT32
-#define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L]
-#define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL]
-#define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH]
-#define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H]
-#define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL]
-#define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH]
-#define RSCAN0C0STS RSCAN0.C0STS.UINT32
-#define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L]
-#define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL]
-#define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH]
-#define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H]
-#define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL]
-#define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH]
-#define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32
-#define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L]
-#define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL]
-#define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH]
-#define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H]
-#define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL]
-#define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH]
-#define RSCAN0C1CFG RSCAN0.C1CFG.UINT32
-#define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L]
-#define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL]
-#define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH]
-#define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H]
-#define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL]
-#define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH]
-#define RSCAN0C1CTR RSCAN0.C1CTR.UINT32
-#define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L]
-#define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL]
-#define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH]
-#define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H]
-#define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL]
-#define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH]
-#define RSCAN0C1STS RSCAN0.C1STS.UINT32
-#define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L]
-#define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL]
-#define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH]
-#define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H]
-#define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL]
-#define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH]
-#define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32
-#define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L]
-#define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL]
-#define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH]
-#define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H]
-#define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL]
-#define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH]
-#define RSCAN0C2CFG RSCAN0.C2CFG.UINT32
-#define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L]
-#define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL]
-#define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH]
-#define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H]
-#define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL]
-#define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH]
-#define RSCAN0C2CTR RSCAN0.C2CTR.UINT32
-#define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L]
-#define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL]
-#define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH]
-#define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H]
-#define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL]
-#define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH]
-#define RSCAN0C2STS RSCAN0.C2STS.UINT32
-#define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L]
-#define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL]
-#define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH]
-#define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H]
-#define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL]
-#define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH]
-#define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32
-#define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L]
-#define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL]
-#define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH]
-#define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H]
-#define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL]
-#define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH]
-#define RSCAN0C3CFG RSCAN0.C3CFG.UINT32
-#define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L]
-#define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL]
-#define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH]
-#define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H]
-#define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL]
-#define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH]
-#define RSCAN0C3CTR RSCAN0.C3CTR.UINT32
-#define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L]
-#define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL]
-#define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH]
-#define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H]
-#define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL]
-#define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH]
-#define RSCAN0C3STS RSCAN0.C3STS.UINT32
-#define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L]
-#define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL]
-#define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH]
-#define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H]
-#define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL]
-#define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH]
-#define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32
-#define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L]
-#define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL]
-#define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH]
-#define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H]
-#define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL]
-#define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH]
-#define RSCAN0C4CFG RSCAN0.C4CFG.UINT32
-#define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L]
-#define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL]
-#define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH]
-#define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H]
-#define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL]
-#define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH]
-#define RSCAN0C4CTR RSCAN0.C4CTR.UINT32
-#define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L]
-#define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL]
-#define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH]
-#define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H]
-#define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL]
-#define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH]
-#define RSCAN0C4STS RSCAN0.C4STS.UINT32
-#define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L]
-#define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL]
-#define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH]
-#define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H]
-#define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL]
-#define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH]
-#define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32
-#define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L]
-#define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL]
-#define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH]
-#define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H]
-#define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL]
-#define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH]
-#define RSCAN0GCFG RSCAN0.GCFG.UINT32
-#define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L]
-#define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL]
-#define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH]
-#define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H]
-#define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL]
-#define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH]
-#define RSCAN0GCTR RSCAN0.GCTR.UINT32
-#define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L]
-#define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL]
-#define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH]
-#define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H]
-#define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL]
-#define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH]
-#define RSCAN0GSTS RSCAN0.GSTS.UINT32
-#define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L]
-#define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL]
-#define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH]
-#define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H]
-#define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL]
-#define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH]
-#define RSCAN0GERFL RSCAN0.GERFL.UINT32
-#define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L]
-#define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL]
-#define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH]
-#define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H]
-#define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL]
-#define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH]
-#define RSCAN0GTSC RSCAN0.GTSC.UINT32
-#define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L]
-#define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H]
-#define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32
-#define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L]
-#define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL]
-#define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH]
-#define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H]
-#define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL]
-#define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH]
-#define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32
-#define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L]
-#define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL]
-#define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH]
-#define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H]
-#define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL]
-#define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH]
-#define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32
-#define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L]
-#define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL]
-#define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH]
-#define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H]
-#define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL]
-#define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH]
-#define RSCAN0RMNB RSCAN0.RMNB.UINT32
-#define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L]
-#define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL]
-#define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH]
-#define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H]
-#define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL]
-#define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH]
-#define RSCAN0RMND0 RSCAN0.RMND0.UINT32
-#define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L]
-#define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL]
-#define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH]
-#define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H]
-#define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL]
-#define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH]
-#define RSCAN0RMND1 RSCAN0.RMND1.UINT32
-#define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L]
-#define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL]
-#define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH]
-#define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H]
-#define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL]
-#define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH]
-#define RSCAN0RMND2 RSCAN0.RMND2.UINT32
-#define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L]
-#define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL]
-#define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH]
-#define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H]
-#define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL]
-#define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH]
-#define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32
-#define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L]
-#define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL]
-#define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH]
-#define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H]
-#define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL]
-#define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH]
-#define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32
-#define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L]
-#define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL]
-#define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH]
-#define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H]
-#define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL]
-#define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH]
-#define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32
-#define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L]
-#define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL]
-#define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH]
-#define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H]
-#define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL]
-#define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH]
-#define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32
-#define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L]
-#define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL]
-#define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH]
-#define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H]
-#define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL]
-#define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH]
-#define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32
-#define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L]
-#define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL]
-#define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH]
-#define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H]
-#define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL]
-#define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH]
-#define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32
-#define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L]
-#define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL]
-#define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH]
-#define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H]
-#define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL]
-#define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH]
-#define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32
-#define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L]
-#define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL]
-#define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH]
-#define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H]
-#define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL]
-#define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH]
-#define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32
-#define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L]
-#define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL]
-#define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH]
-#define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H]
-#define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL]
-#define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH]
-#define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32
-#define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L]
-#define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL]
-#define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH]
-#define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H]
-#define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL]
-#define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH]
-#define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32
-#define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L]
-#define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL]
-#define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH]
-#define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H]
-#define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL]
-#define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH]
-#define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32
-#define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L]
-#define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL]
-#define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH]
-#define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H]
-#define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL]
-#define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH]
-#define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32
-#define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L]
-#define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL]
-#define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH]
-#define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H]
-#define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL]
-#define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH]
-#define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32
-#define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L]
-#define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL]
-#define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH]
-#define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H]
-#define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL]
-#define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH]
-#define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32
-#define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L]
-#define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL]
-#define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH]
-#define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H]
-#define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL]
-#define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH]
-#define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32
-#define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L]
-#define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL]
-#define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH]
-#define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H]
-#define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL]
-#define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH]
-#define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32
-#define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L]
-#define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL]
-#define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH]
-#define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H]
-#define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL]
-#define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH]
-#define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32
-#define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L]
-#define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL]
-#define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH]
-#define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H]
-#define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL]
-#define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH]
-#define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32
-#define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L]
-#define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL]
-#define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH]
-#define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H]
-#define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL]
-#define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH]
-#define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32
-#define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L]
-#define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL]
-#define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH]
-#define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H]
-#define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL]
-#define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH]
-#define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32
-#define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L]
-#define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL]
-#define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH]
-#define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H]
-#define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL]
-#define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH]
-#define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32
-#define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L]
-#define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL]
-#define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH]
-#define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H]
-#define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL]
-#define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH]
-#define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32
-#define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L]
-#define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL]
-#define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH]
-#define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H]
-#define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL]
-#define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH]
-#define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32
-#define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L]
-#define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL]
-#define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH]
-#define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H]
-#define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL]
-#define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH]
-#define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32
-#define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L]
-#define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL]
-#define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH]
-#define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H]
-#define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL]
-#define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH]
-#define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32
-#define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L]
-#define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL]
-#define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH]
-#define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H]
-#define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL]
-#define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH]
-#define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32
-#define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L]
-#define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL]
-#define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH]
-#define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H]
-#define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL]
-#define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH]
-#define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32
-#define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L]
-#define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL]
-#define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH]
-#define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H]
-#define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL]
-#define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH]
-#define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32
-#define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L]
-#define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL]
-#define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH]
-#define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H]
-#define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL]
-#define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH]
-#define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32
-#define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L]
-#define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL]
-#define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH]
-#define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H]
-#define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL]
-#define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH]
-#define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32
-#define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L]
-#define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL]
-#define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH]
-#define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H]
-#define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL]
-#define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH]
-#define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32
-#define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L]
-#define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL]
-#define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH]
-#define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H]
-#define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL]
-#define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH]
-#define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32
-#define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L]
-#define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL]
-#define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH]
-#define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H]
-#define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL]
-#define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH]
-#define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32
-#define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L]
-#define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL]
-#define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH]
-#define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H]
-#define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL]
-#define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH]
-#define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32
-#define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L]
-#define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL]
-#define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH]
-#define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H]
-#define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL]
-#define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH]
-#define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32
-#define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L]
-#define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL]
-#define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH]
-#define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H]
-#define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL]
-#define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH]
-#define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32
-#define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L]
-#define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL]
-#define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH]
-#define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H]
-#define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL]
-#define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH]
-#define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32
-#define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L]
-#define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL]
-#define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH]
-#define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H]
-#define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL]
-#define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH]
-#define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32
-#define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L]
-#define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL]
-#define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH]
-#define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H]
-#define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL]
-#define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH]
-#define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32
-#define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L]
-#define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL]
-#define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH]
-#define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H]
-#define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL]
-#define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH]
-#define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32
-#define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L]
-#define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL]
-#define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH]
-#define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H]
-#define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL]
-#define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH]
-#define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32
-#define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L]
-#define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL]
-#define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH]
-#define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H]
-#define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL]
-#define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH]
-#define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32
-#define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L]
-#define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL]
-#define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH]
-#define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H]
-#define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL]
-#define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH]
-#define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32
-#define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L]
-#define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL]
-#define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH]
-#define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H]
-#define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL]
-#define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH]
-#define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32
-#define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L]
-#define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL]
-#define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH]
-#define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H]
-#define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL]
-#define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH]
-#define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32
-#define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L]
-#define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL]
-#define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH]
-#define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H]
-#define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL]
-#define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH]
-#define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32
-#define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L]
-#define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL]
-#define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH]
-#define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H]
-#define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL]
-#define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH]
-#define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32
-#define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L]
-#define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL]
-#define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH]
-#define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H]
-#define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL]
-#define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH]
-#define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32
-#define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L]
-#define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL]
-#define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH]
-#define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H]
-#define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL]
-#define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH]
-#define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32
-#define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L]
-#define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL]
-#define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH]
-#define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H]
-#define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL]
-#define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH]
-#define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32
-#define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L]
-#define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL]
-#define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH]
-#define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H]
-#define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL]
-#define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH]
-#define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32
-#define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L]
-#define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL]
-#define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH]
-#define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H]
-#define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL]
-#define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH]
-#define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32
-#define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L]
-#define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL]
-#define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH]
-#define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H]
-#define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL]
-#define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH]
-#define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32
-#define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L]
-#define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL]
-#define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH]
-#define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H]
-#define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL]
-#define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH]
-#define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32
-#define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L]
-#define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL]
-#define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH]
-#define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H]
-#define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL]
-#define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH]
-#define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32
-#define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L]
-#define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL]
-#define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH]
-#define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H]
-#define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL]
-#define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH]
-#define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32
-#define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L]
-#define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL]
-#define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH]
-#define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H]
-#define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL]
-#define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH]
-#define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32
-#define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L]
-#define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL]
-#define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH]
-#define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H]
-#define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL]
-#define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH]
-#define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32
-#define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L]
-#define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL]
-#define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH]
-#define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H]
-#define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL]
-#define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH]
-#define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32
-#define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L]
-#define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL]
-#define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH]
-#define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H]
-#define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL]
-#define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH]
-#define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32
-#define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L]
-#define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL]
-#define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH]
-#define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H]
-#define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL]
-#define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH]
-#define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32
-#define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L]
-#define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL]
-#define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH]
-#define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H]
-#define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL]
-#define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH]
-#define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32
-#define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L]
-#define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL]
-#define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH]
-#define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H]
-#define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL]
-#define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH]
-#define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32
-#define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L]
-#define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL]
-#define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH]
-#define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H]
-#define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL]
-#define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH]
-#define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32
-#define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L]
-#define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL]
-#define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH]
-#define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H]
-#define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL]
-#define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH]
-#define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32
-#define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L]
-#define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL]
-#define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH]
-#define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H]
-#define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL]
-#define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH]
-#define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32
-#define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L]
-#define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL]
-#define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH]
-#define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H]
-#define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL]
-#define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH]
-#define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32
-#define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L]
-#define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL]
-#define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH]
-#define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H]
-#define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL]
-#define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH]
-#define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32
-#define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L]
-#define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL]
-#define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH]
-#define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H]
-#define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL]
-#define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH]
-#define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32
-#define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L]
-#define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL]
-#define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH]
-#define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H]
-#define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL]
-#define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH]
-#define RSCAN0FESTS RSCAN0.FESTS.UINT32
-#define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L]
-#define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL]
-#define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH]
-#define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H]
-#define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL]
-#define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH]
-#define RSCAN0FFSTS RSCAN0.FFSTS.UINT32
-#define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L]
-#define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL]
-#define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH]
-#define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H]
-#define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL]
-#define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH]
-#define RSCAN0FMSTS RSCAN0.FMSTS.UINT32
-#define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L]
-#define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL]
-#define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH]
-#define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H]
-#define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL]
-#define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH]
-#define RSCAN0RFISTS RSCAN0.RFISTS.UINT32
-#define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L]
-#define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL]
-#define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH]
-#define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H]
-#define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL]
-#define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH]
-#define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32
-#define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L]
-#define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL]
-#define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH]
-#define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H]
-#define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL]
-#define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH]
-#define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32
-#define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L]
-#define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL]
-#define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH]
-#define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H]
-#define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL]
-#define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH]
-#define RSCAN0TMC0 RSCAN0.TMC0
-#define RSCAN0TMC1 RSCAN0.TMC1
-#define RSCAN0TMC2 RSCAN0.TMC2
-#define RSCAN0TMC3 RSCAN0.TMC3
-#define RSCAN0TMC4 RSCAN0.TMC4
-#define RSCAN0TMC5 RSCAN0.TMC5
-#define RSCAN0TMC6 RSCAN0.TMC6
-#define RSCAN0TMC7 RSCAN0.TMC7
-#define RSCAN0TMC8 RSCAN0.TMC8
-#define RSCAN0TMC9 RSCAN0.TMC9
-#define RSCAN0TMC10 RSCAN0.TMC10
-#define RSCAN0TMC11 RSCAN0.TMC11
-#define RSCAN0TMC12 RSCAN0.TMC12
-#define RSCAN0TMC13 RSCAN0.TMC13
-#define RSCAN0TMC14 RSCAN0.TMC14
-#define RSCAN0TMC15 RSCAN0.TMC15
-#define RSCAN0TMC16 RSCAN0.TMC16
-#define RSCAN0TMC17 RSCAN0.TMC17
-#define RSCAN0TMC18 RSCAN0.TMC18
-#define RSCAN0TMC19 RSCAN0.TMC19
-#define RSCAN0TMC20 RSCAN0.TMC20
-#define RSCAN0TMC21 RSCAN0.TMC21
-#define RSCAN0TMC22 RSCAN0.TMC22
-#define RSCAN0TMC23 RSCAN0.TMC23
-#define RSCAN0TMC24 RSCAN0.TMC24
-#define RSCAN0TMC25 RSCAN0.TMC25
-#define RSCAN0TMC26 RSCAN0.TMC26
-#define RSCAN0TMC27 RSCAN0.TMC27
-#define RSCAN0TMC28 RSCAN0.TMC28
-#define RSCAN0TMC29 RSCAN0.TMC29
-#define RSCAN0TMC30 RSCAN0.TMC30
-#define RSCAN0TMC31 RSCAN0.TMC31
-#define RSCAN0TMC32 RSCAN0.TMC32
-#define RSCAN0TMC33 RSCAN0.TMC33
-#define RSCAN0TMC34 RSCAN0.TMC34
-#define RSCAN0TMC35 RSCAN0.TMC35
-#define RSCAN0TMC36 RSCAN0.TMC36
-#define RSCAN0TMC37 RSCAN0.TMC37
-#define RSCAN0TMC38 RSCAN0.TMC38
-#define RSCAN0TMC39 RSCAN0.TMC39
-#define RSCAN0TMC40 RSCAN0.TMC40
-#define RSCAN0TMC41 RSCAN0.TMC41
-#define RSCAN0TMC42 RSCAN0.TMC42
-#define RSCAN0TMC43 RSCAN0.TMC43
-#define RSCAN0TMC44 RSCAN0.TMC44
-#define RSCAN0TMC45 RSCAN0.TMC45
-#define RSCAN0TMC46 RSCAN0.TMC46
-#define RSCAN0TMC47 RSCAN0.TMC47
-#define RSCAN0TMC48 RSCAN0.TMC48
-#define RSCAN0TMC49 RSCAN0.TMC49
-#define RSCAN0TMC50 RSCAN0.TMC50
-#define RSCAN0TMC51 RSCAN0.TMC51
-#define RSCAN0TMC52 RSCAN0.TMC52
-#define RSCAN0TMC53 RSCAN0.TMC53
-#define RSCAN0TMC54 RSCAN0.TMC54
-#define RSCAN0TMC55 RSCAN0.TMC55
-#define RSCAN0TMC56 RSCAN0.TMC56
-#define RSCAN0TMC57 RSCAN0.TMC57
-#define RSCAN0TMC58 RSCAN0.TMC58
-#define RSCAN0TMC59 RSCAN0.TMC59
-#define RSCAN0TMC60 RSCAN0.TMC60
-#define RSCAN0TMC61 RSCAN0.TMC61
-#define RSCAN0TMC62 RSCAN0.TMC62
-#define RSCAN0TMC63 RSCAN0.TMC63
-#define RSCAN0TMC64 RSCAN0.TMC64
-#define RSCAN0TMC65 RSCAN0.TMC65
-#define RSCAN0TMC66 RSCAN0.TMC66
-#define RSCAN0TMC67 RSCAN0.TMC67
-#define RSCAN0TMC68 RSCAN0.TMC68
-#define RSCAN0TMC69 RSCAN0.TMC69
-#define RSCAN0TMC70 RSCAN0.TMC70
-#define RSCAN0TMC71 RSCAN0.TMC71
-#define RSCAN0TMC72 RSCAN0.TMC72
-#define RSCAN0TMC73 RSCAN0.TMC73
-#define RSCAN0TMC74 RSCAN0.TMC74
-#define RSCAN0TMC75 RSCAN0.TMC75
-#define RSCAN0TMC76 RSCAN0.TMC76
-#define RSCAN0TMC77 RSCAN0.TMC77
-#define RSCAN0TMC78 RSCAN0.TMC78
-#define RSCAN0TMC79 RSCAN0.TMC79
-#define RSCAN0TMSTS0 RSCAN0.TMSTS0
-#define RSCAN0TMSTS1 RSCAN0.TMSTS1
-#define RSCAN0TMSTS2 RSCAN0.TMSTS2
-#define RSCAN0TMSTS3 RSCAN0.TMSTS3
-#define RSCAN0TMSTS4 RSCAN0.TMSTS4
-#define RSCAN0TMSTS5 RSCAN0.TMSTS5
-#define RSCAN0TMSTS6 RSCAN0.TMSTS6
-#define RSCAN0TMSTS7 RSCAN0.TMSTS7
-#define RSCAN0TMSTS8 RSCAN0.TMSTS8
-#define RSCAN0TMSTS9 RSCAN0.TMSTS9
-#define RSCAN0TMSTS10 RSCAN0.TMSTS10
-#define RSCAN0TMSTS11 RSCAN0.TMSTS11
-#define RSCAN0TMSTS12 RSCAN0.TMSTS12
-#define RSCAN0TMSTS13 RSCAN0.TMSTS13
-#define RSCAN0TMSTS14 RSCAN0.TMSTS14
-#define RSCAN0TMSTS15 RSCAN0.TMSTS15
-#define RSCAN0TMSTS16 RSCAN0.TMSTS16
-#define RSCAN0TMSTS17 RSCAN0.TMSTS17
-#define RSCAN0TMSTS18 RSCAN0.TMSTS18
-#define RSCAN0TMSTS19 RSCAN0.TMSTS19
-#define RSCAN0TMSTS20 RSCAN0.TMSTS20
-#define RSCAN0TMSTS21 RSCAN0.TMSTS21
-#define RSCAN0TMSTS22 RSCAN0.TMSTS22
-#define RSCAN0TMSTS23 RSCAN0.TMSTS23
-#define RSCAN0TMSTS24 RSCAN0.TMSTS24
-#define RSCAN0TMSTS25 RSCAN0.TMSTS25
-#define RSCAN0TMSTS26 RSCAN0.TMSTS26
-#define RSCAN0TMSTS27 RSCAN0.TMSTS27
-#define RSCAN0TMSTS28 RSCAN0.TMSTS28
-#define RSCAN0TMSTS29 RSCAN0.TMSTS29
-#define RSCAN0TMSTS30 RSCAN0.TMSTS30
-#define RSCAN0TMSTS31 RSCAN0.TMSTS31
-#define RSCAN0TMSTS32 RSCAN0.TMSTS32
-#define RSCAN0TMSTS33 RSCAN0.TMSTS33
-#define RSCAN0TMSTS34 RSCAN0.TMSTS34
-#define RSCAN0TMSTS35 RSCAN0.TMSTS35
-#define RSCAN0TMSTS36 RSCAN0.TMSTS36
-#define RSCAN0TMSTS37 RSCAN0.TMSTS37
-#define RSCAN0TMSTS38 RSCAN0.TMSTS38
-#define RSCAN0TMSTS39 RSCAN0.TMSTS39
-#define RSCAN0TMSTS40 RSCAN0.TMSTS40
-#define RSCAN0TMSTS41 RSCAN0.TMSTS41
-#define RSCAN0TMSTS42 RSCAN0.TMSTS42
-#define RSCAN0TMSTS43 RSCAN0.TMSTS43
-#define RSCAN0TMSTS44 RSCAN0.TMSTS44
-#define RSCAN0TMSTS45 RSCAN0.TMSTS45
-#define RSCAN0TMSTS46 RSCAN0.TMSTS46
-#define RSCAN0TMSTS47 RSCAN0.TMSTS47
-#define RSCAN0TMSTS48 RSCAN0.TMSTS48
-#define RSCAN0TMSTS49 RSCAN0.TMSTS49
-#define RSCAN0TMSTS50 RSCAN0.TMSTS50
-#define RSCAN0TMSTS51 RSCAN0.TMSTS51
-#define RSCAN0TMSTS52 RSCAN0.TMSTS52
-#define RSCAN0TMSTS53 RSCAN0.TMSTS53
-#define RSCAN0TMSTS54 RSCAN0.TMSTS54
-#define RSCAN0TMSTS55 RSCAN0.TMSTS55
-#define RSCAN0TMSTS56 RSCAN0.TMSTS56
-#define RSCAN0TMSTS57 RSCAN0.TMSTS57
-#define RSCAN0TMSTS58 RSCAN0.TMSTS58
-#define RSCAN0TMSTS59 RSCAN0.TMSTS59
-#define RSCAN0TMSTS60 RSCAN0.TMSTS60
-#define RSCAN0TMSTS61 RSCAN0.TMSTS61
-#define RSCAN0TMSTS62 RSCAN0.TMSTS62
-#define RSCAN0TMSTS63 RSCAN0.TMSTS63
-#define RSCAN0TMSTS64 RSCAN0.TMSTS64
-#define RSCAN0TMSTS65 RSCAN0.TMSTS65
-#define RSCAN0TMSTS66 RSCAN0.TMSTS66
-#define RSCAN0TMSTS67 RSCAN0.TMSTS67
-#define RSCAN0TMSTS68 RSCAN0.TMSTS68
-#define RSCAN0TMSTS69 RSCAN0.TMSTS69
-#define RSCAN0TMSTS70 RSCAN0.TMSTS70
-#define RSCAN0TMSTS71 RSCAN0.TMSTS71
-#define RSCAN0TMSTS72 RSCAN0.TMSTS72
-#define RSCAN0TMSTS73 RSCAN0.TMSTS73
-#define RSCAN0TMSTS74 RSCAN0.TMSTS74
-#define RSCAN0TMSTS75 RSCAN0.TMSTS75
-#define RSCAN0TMSTS76 RSCAN0.TMSTS76
-#define RSCAN0TMSTS77 RSCAN0.TMSTS77
-#define RSCAN0TMSTS78 RSCAN0.TMSTS78
-#define RSCAN0TMSTS79 RSCAN0.TMSTS79
-#define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32
-#define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L]
-#define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL]
-#define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH]
-#define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H]
-#define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL]
-#define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH]
-#define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32
-#define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L]
-#define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL]
-#define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH]
-#define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H]
-#define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL]
-#define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH]
-#define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32
-#define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L]
-#define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL]
-#define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH]
-#define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H]
-#define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL]
-#define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH]
-#define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32
-#define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L]
-#define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL]
-#define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH]
-#define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H]
-#define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL]
-#define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH]
-#define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32
-#define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L]
-#define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL]
-#define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH]
-#define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H]
-#define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL]
-#define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH]
-#define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32
-#define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L]
-#define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL]
-#define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH]
-#define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H]
-#define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL]
-#define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH]
-#define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32
-#define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L]
-#define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL]
-#define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH]
-#define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H]
-#define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL]
-#define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH]
-#define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32
-#define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L]
-#define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL]
-#define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH]
-#define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H]
-#define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL]
-#define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH]
-#define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32
-#define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L]
-#define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL]
-#define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH]
-#define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H]
-#define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL]
-#define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH]
-#define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32
-#define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L]
-#define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL]
-#define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH]
-#define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H]
-#define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL]
-#define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH]
-#define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32
-#define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L]
-#define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL]
-#define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH]
-#define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H]
-#define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL]
-#define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH]
-#define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32
-#define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L]
-#define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL]
-#define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH]
-#define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H]
-#define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL]
-#define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH]
-#define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32
-#define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L]
-#define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL]
-#define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH]
-#define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H]
-#define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL]
-#define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH]
-#define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32
-#define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L]
-#define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL]
-#define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH]
-#define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H]
-#define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL]
-#define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH]
-#define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32
-#define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L]
-#define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL]
-#define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH]
-#define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H]
-#define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL]
-#define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH]
-#define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32
-#define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L]
-#define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL]
-#define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH]
-#define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H]
-#define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL]
-#define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH]
-#define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32
-#define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L]
-#define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL]
-#define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH]
-#define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H]
-#define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL]
-#define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH]
-#define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32
-#define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L]
-#define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL]
-#define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH]
-#define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H]
-#define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL]
-#define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH]
-#define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32
-#define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L]
-#define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL]
-#define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH]
-#define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H]
-#define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL]
-#define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH]
-#define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32
-#define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L]
-#define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL]
-#define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH]
-#define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H]
-#define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL]
-#define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH]
-#define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32
-#define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L]
-#define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL]
-#define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH]
-#define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H]
-#define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL]
-#define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH]
-#define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32
-#define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L]
-#define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL]
-#define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH]
-#define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H]
-#define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL]
-#define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH]
-#define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32
-#define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L]
-#define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL]
-#define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH]
-#define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H]
-#define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL]
-#define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH]
-#define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32
-#define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L]
-#define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL]
-#define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH]
-#define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H]
-#define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL]
-#define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH]
-#define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32
-#define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L]
-#define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL]
-#define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH]
-#define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H]
-#define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL]
-#define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH]
-#define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32
-#define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L]
-#define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL]
-#define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH]
-#define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H]
-#define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL]
-#define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH]
-#define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32
-#define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L]
-#define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL]
-#define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH]
-#define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H]
-#define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL]
-#define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH]
-#define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32
-#define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L]
-#define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL]
-#define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH]
-#define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H]
-#define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL]
-#define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH]
-#define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32
-#define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L]
-#define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL]
-#define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH]
-#define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H]
-#define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL]
-#define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH]
-#define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32
-#define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L]
-#define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL]
-#define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH]
-#define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H]
-#define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL]
-#define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH]
-#define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32
-#define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L]
-#define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL]
-#define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH]
-#define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H]
-#define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL]
-#define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH]
-#define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32
-#define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L]
-#define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL]
-#define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH]
-#define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H]
-#define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL]
-#define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH]
-#define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32
-#define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L]
-#define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL]
-#define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH]
-#define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H]
-#define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL]
-#define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH]
-#define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32
-#define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L]
-#define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL]
-#define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH]
-#define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H]
-#define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL]
-#define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH]
-#define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32
-#define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L]
-#define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL]
-#define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH]
-#define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H]
-#define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL]
-#define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH]
-#define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32
-#define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L]
-#define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL]
-#define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH]
-#define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H]
-#define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL]
-#define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH]
-#define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32
-#define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L]
-#define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL]
-#define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH]
-#define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H]
-#define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL]
-#define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH]
-#define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32
-#define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L]
-#define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL]
-#define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH]
-#define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H]
-#define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL]
-#define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH]
-#define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32
-#define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L]
-#define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL]
-#define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH]
-#define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H]
-#define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL]
-#define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH]
-#define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32
-#define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L]
-#define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL]
-#define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH]
-#define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H]
-#define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL]
-#define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH]
-#define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32
-#define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L]
-#define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL]
-#define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH]
-#define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H]
-#define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL]
-#define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH]
-#define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32
-#define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L]
-#define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL]
-#define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH]
-#define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H]
-#define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL]
-#define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH]
-#define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32
-#define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L]
-#define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL]
-#define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH]
-#define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H]
-#define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL]
-#define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH]
-#define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32
-#define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L]
-#define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL]
-#define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH]
-#define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H]
-#define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL]
-#define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH]
-#define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32
-#define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L]
-#define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL]
-#define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH]
-#define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H]
-#define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL]
-#define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH]
-#define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32
-#define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L]
-#define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL]
-#define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH]
-#define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H]
-#define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL]
-#define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH]
-#define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32
-#define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L]
-#define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL]
-#define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH]
-#define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H]
-#define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL]
-#define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH]
-#define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32
-#define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L]
-#define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL]
-#define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH]
-#define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H]
-#define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL]
-#define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH]
-#define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32
-#define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L]
-#define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL]
-#define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH]
-#define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H]
-#define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL]
-#define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH]
-#define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32
-#define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L]
-#define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H]
-#define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32
-#define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L]
-#define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL]
-#define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH]
-#define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H]
-#define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL]
-#define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH]
-#define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32
-#define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L]
-#define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL]
-#define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH]
-#define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H]
-#define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL]
-#define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH]
-#define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32
-#define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L]
-#define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL]
-#define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH]
-#define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H]
-#define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL]
-#define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH]
-#define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32
-#define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L]
-#define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL]
-#define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH]
-#define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H]
-#define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL]
-#define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH]
-#define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32
-#define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L]
-#define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL]
-#define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH]
-#define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H]
-#define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL]
-#define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH]
-#define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32
-#define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L]
-#define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL]
-#define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH]
-#define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H]
-#define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL]
-#define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH]
-#define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32
-#define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L]
-#define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL]
-#define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH]
-#define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H]
-#define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL]
-#define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH]
-#define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32
-#define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L]
-#define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL]
-#define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH]
-#define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H]
-#define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL]
-#define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH]
-#define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32
-#define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L]
-#define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL]
-#define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH]
-#define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H]
-#define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL]
-#define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH]
-#define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32
-#define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L]
-#define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL]
-#define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH]
-#define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H]
-#define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL]
-#define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH]
-#define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32
-#define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L]
-#define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL]
-#define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH]
-#define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H]
-#define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL]
-#define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH]
-#define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32
-#define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L]
-#define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL]
-#define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH]
-#define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H]
-#define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL]
-#define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH]
-#define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32
-#define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L]
-#define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL]
-#define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH]
-#define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H]
-#define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL]
-#define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH]
-#define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32
-#define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L]
-#define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL]
-#define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH]
-#define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H]
-#define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL]
-#define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH]
-#define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32
-#define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L]
-#define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL]
-#define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH]
-#define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H]
-#define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL]
-#define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH]
-#define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32
-#define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L]
-#define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL]
-#define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH]
-#define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H]
-#define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL]
-#define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH]
-#define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32
-#define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L]
-#define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL]
-#define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH]
-#define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H]
-#define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL]
-#define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH]
-#define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32
-#define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L]
-#define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL]
-#define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH]
-#define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H]
-#define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL]
-#define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH]
-#define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32
-#define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L]
-#define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL]
-#define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH]
-#define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H]
-#define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL]
-#define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH]
-#define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32
-#define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L]
-#define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL]
-#define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH]
-#define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H]
-#define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL]
-#define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH]
-#define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32
-#define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L]
-#define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL]
-#define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH]
-#define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H]
-#define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL]
-#define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH]
-#define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32
-#define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L]
-#define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL]
-#define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH]
-#define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H]
-#define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL]
-#define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH]
-#define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32
-#define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L]
-#define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL]
-#define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH]
-#define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H]
-#define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL]
-#define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH]
-#define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32
-#define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L]
-#define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL]
-#define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH]
-#define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H]
-#define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL]
-#define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH]
-#define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32
-#define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L]
-#define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL]
-#define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH]
-#define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H]
-#define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL]
-#define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH]
-#define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32
-#define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L]
-#define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL]
-#define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH]
-#define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H]
-#define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL]
-#define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH]
-#define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32
-#define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L]
-#define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL]
-#define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH]
-#define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H]
-#define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL]
-#define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH]
-#define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32
-#define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L]
-#define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL]
-#define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH]
-#define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H]
-#define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL]
-#define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH]
-#define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32
-#define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L]
-#define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL]
-#define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH]
-#define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H]
-#define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL]
-#define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH]
-#define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32
-#define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L]
-#define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL]
-#define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH]
-#define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H]
-#define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL]
-#define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH]
-#define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32
-#define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L]
-#define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL]
-#define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH]
-#define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H]
-#define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL]
-#define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH]
-#define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32
-#define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L]
-#define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL]
-#define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH]
-#define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H]
-#define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL]
-#define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH]
-#define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32
-#define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L]
-#define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL]
-#define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH]
-#define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H]
-#define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL]
-#define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH]
-#define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32
-#define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L]
-#define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL]
-#define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH]
-#define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H]
-#define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL]
-#define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH]
-#define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32
-#define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L]
-#define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL]
-#define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH]
-#define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H]
-#define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL]
-#define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH]
-#define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32
-#define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L]
-#define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL]
-#define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH]
-#define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H]
-#define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL]
-#define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH]
-#define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32
-#define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L]
-#define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL]
-#define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH]
-#define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H]
-#define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL]
-#define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH]
-#define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32
-#define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L]
-#define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL]
-#define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH]
-#define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H]
-#define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL]
-#define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH]
-#define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32
-#define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L]
-#define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL]
-#define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH]
-#define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H]
-#define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL]
-#define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH]
-#define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32
-#define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L]
-#define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL]
-#define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH]
-#define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H]
-#define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL]
-#define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH]
-#define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32
-#define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L]
-#define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL]
-#define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH]
-#define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H]
-#define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL]
-#define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH]
-#define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32
-#define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L]
-#define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL]
-#define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH]
-#define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H]
-#define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL]
-#define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH]
-#define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32
-#define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L]
-#define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL]
-#define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH]
-#define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H]
-#define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL]
-#define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH]
-#define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32
-#define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L]
-#define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL]
-#define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH]
-#define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H]
-#define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL]
-#define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH]
-#define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32
-#define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L]
-#define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL]
-#define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH]
-#define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H]
-#define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL]
-#define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH]
-#define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32
-#define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L]
-#define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL]
-#define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH]
-#define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H]
-#define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL]
-#define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH]
-#define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32
-#define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L]
-#define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL]
-#define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH]
-#define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H]
-#define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL]
-#define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH]
-#define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32
-#define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L]
-#define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL]
-#define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH]
-#define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H]
-#define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL]
-#define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH]
-#define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32
-#define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L]
-#define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL]
-#define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH]
-#define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H]
-#define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL]
-#define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH]
-#define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32
-#define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L]
-#define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL]
-#define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH]
-#define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H]
-#define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL]
-#define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH]
-#define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32
-#define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L]
-#define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL]
-#define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH]
-#define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H]
-#define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL]
-#define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH]
-#define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32
-#define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L]
-#define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL]
-#define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH]
-#define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H]
-#define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL]
-#define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH]
-#define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32
-#define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L]
-#define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL]
-#define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH]
-#define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H]
-#define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL]
-#define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH]
-#define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32
-#define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L]
-#define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL]
-#define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH]
-#define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H]
-#define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL]
-#define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH]
-#define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32
-#define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L]
-#define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL]
-#define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH]
-#define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H]
-#define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL]
-#define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH]
-#define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32
-#define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L]
-#define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL]
-#define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH]
-#define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H]
-#define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL]
-#define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH]
-#define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32
-#define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L]
-#define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL]
-#define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH]
-#define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H]
-#define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL]
-#define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH]
-#define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32
-#define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L]
-#define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL]
-#define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH]
-#define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H]
-#define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL]
-#define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH]
-#define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32
-#define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L]
-#define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL]
-#define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH]
-#define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H]
-#define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL]
-#define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH]
-#define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32
-#define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L]
-#define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL]
-#define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH]
-#define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H]
-#define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL]
-#define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH]
-#define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32
-#define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L]
-#define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL]
-#define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH]
-#define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H]
-#define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL]
-#define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH]
-#define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32
-#define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L]
-#define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL]
-#define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH]
-#define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H]
-#define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL]
-#define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH]
-#define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32
-#define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L]
-#define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL]
-#define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH]
-#define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H]
-#define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL]
-#define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH]
-#define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32
-#define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L]
-#define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL]
-#define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH]
-#define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H]
-#define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL]
-#define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH]
-#define RSCAN0RMID0 RSCAN0.RMID0.UINT32
-#define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L]
-#define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL]
-#define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH]
-#define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H]
-#define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL]
-#define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH]
-#define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32
-#define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L]
-#define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL]
-#define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH]
-#define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H]
-#define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL]
-#define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH]
-#define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32
-#define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L]
-#define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL]
-#define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH]
-#define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H]
-#define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL]
-#define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH]
-#define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32
-#define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L]
-#define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL]
-#define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH]
-#define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H]
-#define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL]
-#define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH]
-#define RSCAN0RMID1 RSCAN0.RMID1.UINT32
-#define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L]
-#define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL]
-#define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH]
-#define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H]
-#define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL]
-#define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH]
-#define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32
-#define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L]
-#define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL]
-#define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH]
-#define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H]
-#define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL]
-#define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH]
-#define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32
-#define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L]
-#define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL]
-#define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH]
-#define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H]
-#define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL]
-#define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH]
-#define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32
-#define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L]
-#define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL]
-#define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH]
-#define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H]
-#define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL]
-#define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH]
-#define RSCAN0RMID2 RSCAN0.RMID2.UINT32
-#define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L]
-#define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL]
-#define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH]
-#define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H]
-#define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL]
-#define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH]
-#define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32
-#define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L]
-#define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL]
-#define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH]
-#define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H]
-#define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL]
-#define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH]
-#define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32
-#define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L]
-#define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL]
-#define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH]
-#define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H]
-#define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL]
-#define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH]
-#define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32
-#define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L]
-#define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL]
-#define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH]
-#define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H]
-#define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL]
-#define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH]
-#define RSCAN0RMID3 RSCAN0.RMID3.UINT32
-#define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L]
-#define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL]
-#define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH]
-#define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H]
-#define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL]
-#define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH]
-#define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32
-#define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L]
-#define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL]
-#define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH]
-#define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H]
-#define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL]
-#define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH]
-#define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32
-#define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L]
-#define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL]
-#define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH]
-#define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H]
-#define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL]
-#define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH]
-#define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32
-#define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L]
-#define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL]
-#define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH]
-#define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H]
-#define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL]
-#define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH]
-#define RSCAN0RMID4 RSCAN0.RMID4.UINT32
-#define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L]
-#define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL]
-#define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH]
-#define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H]
-#define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL]
-#define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH]
-#define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32
-#define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L]
-#define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL]
-#define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH]
-#define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H]
-#define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL]
-#define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH]
-#define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32
-#define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L]
-#define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL]
-#define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH]
-#define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H]
-#define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL]
-#define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH]
-#define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32
-#define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L]
-#define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL]
-#define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH]
-#define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H]
-#define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL]
-#define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH]
-#define RSCAN0RMID5 RSCAN0.RMID5.UINT32
-#define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L]
-#define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL]
-#define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH]
-#define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H]
-#define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL]
-#define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH]
-#define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32
-#define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L]
-#define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL]
-#define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH]
-#define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H]
-#define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL]
-#define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH]
-#define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32
-#define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L]
-#define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL]
-#define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH]
-#define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H]
-#define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL]
-#define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH]
-#define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32
-#define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L]
-#define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL]
-#define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH]
-#define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H]
-#define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL]
-#define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH]
-#define RSCAN0RMID6 RSCAN0.RMID6.UINT32
-#define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L]
-#define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL]
-#define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH]
-#define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H]
-#define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL]
-#define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH]
-#define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32
-#define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L]
-#define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL]
-#define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH]
-#define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H]
-#define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL]
-#define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH]
-#define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32
-#define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L]
-#define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL]
-#define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH]
-#define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H]
-#define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL]
-#define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH]
-#define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32
-#define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L]
-#define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL]
-#define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH]
-#define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H]
-#define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL]
-#define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH]
-#define RSCAN0RMID7 RSCAN0.RMID7.UINT32
-#define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L]
-#define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL]
-#define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH]
-#define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H]
-#define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL]
-#define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH]
-#define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32
-#define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L]
-#define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL]
-#define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH]
-#define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H]
-#define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL]
-#define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH]
-#define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32
-#define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L]
-#define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL]
-#define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH]
-#define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H]
-#define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL]
-#define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH]
-#define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32
-#define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L]
-#define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL]
-#define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH]
-#define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H]
-#define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL]
-#define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH]
-#define RSCAN0RMID8 RSCAN0.RMID8.UINT32
-#define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L]
-#define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL]
-#define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH]
-#define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H]
-#define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL]
-#define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH]
-#define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32
-#define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L]
-#define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL]
-#define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH]
-#define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H]
-#define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL]
-#define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH]
-#define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32
-#define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L]
-#define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL]
-#define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH]
-#define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H]
-#define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL]
-#define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH]
-#define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32
-#define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L]
-#define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL]
-#define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH]
-#define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H]
-#define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL]
-#define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH]
-#define RSCAN0RMID9 RSCAN0.RMID9.UINT32
-#define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L]
-#define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL]
-#define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH]
-#define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H]
-#define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL]
-#define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH]
-#define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32
-#define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L]
-#define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL]
-#define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH]
-#define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H]
-#define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL]
-#define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH]
-#define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32
-#define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L]
-#define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL]
-#define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH]
-#define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H]
-#define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL]
-#define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH]
-#define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32
-#define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L]
-#define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL]
-#define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH]
-#define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H]
-#define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL]
-#define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH]
-#define RSCAN0RMID10 RSCAN0.RMID10.UINT32
-#define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L]
-#define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL]
-#define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH]
-#define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H]
-#define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL]
-#define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH]
-#define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32
-#define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L]
-#define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL]
-#define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH]
-#define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H]
-#define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL]
-#define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH]
-#define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32
-#define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L]
-#define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL]
-#define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH]
-#define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H]
-#define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL]
-#define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH]
-#define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32
-#define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L]
-#define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL]
-#define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH]
-#define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H]
-#define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL]
-#define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH]
-#define RSCAN0RMID11 RSCAN0.RMID11.UINT32
-#define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L]
-#define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL]
-#define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH]
-#define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H]
-#define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL]
-#define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH]
-#define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32
-#define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L]
-#define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL]
-#define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH]
-#define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H]
-#define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL]
-#define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH]
-#define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32
-#define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L]
-#define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL]
-#define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH]
-#define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H]
-#define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL]
-#define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH]
-#define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32
-#define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L]
-#define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL]
-#define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH]
-#define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H]
-#define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL]
-#define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH]
-#define RSCAN0RMID12 RSCAN0.RMID12.UINT32
-#define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L]
-#define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL]
-#define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH]
-#define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H]
-#define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL]
-#define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH]
-#define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32
-#define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L]
-#define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL]
-#define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH]
-#define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H]
-#define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL]
-#define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH]
-#define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32
-#define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L]
-#define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL]
-#define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH]
-#define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H]
-#define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL]
-#define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH]
-#define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32
-#define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L]
-#define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL]
-#define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH]
-#define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H]
-#define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL]
-#define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH]
-#define RSCAN0RMID13 RSCAN0.RMID13.UINT32
-#define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L]
-#define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL]
-#define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH]
-#define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H]
-#define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL]
-#define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH]
-#define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32
-#define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L]
-#define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL]
-#define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH]
-#define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H]
-#define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL]
-#define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH]
-#define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32
-#define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L]
-#define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL]
-#define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH]
-#define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H]
-#define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL]
-#define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH]
-#define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32
-#define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L]
-#define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL]
-#define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH]
-#define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H]
-#define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL]
-#define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH]
-#define RSCAN0RMID14 RSCAN0.RMID14.UINT32
-#define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L]
-#define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL]
-#define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH]
-#define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H]
-#define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL]
-#define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH]
-#define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32
-#define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L]
-#define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL]
-#define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH]
-#define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H]
-#define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL]
-#define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH]
-#define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32
-#define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L]
-#define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL]
-#define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH]
-#define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H]
-#define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL]
-#define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH]
-#define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32
-#define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L]
-#define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL]
-#define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH]
-#define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H]
-#define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL]
-#define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH]
-#define RSCAN0RMID15 RSCAN0.RMID15.UINT32
-#define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L]
-#define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL]
-#define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH]
-#define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H]
-#define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL]
-#define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH]
-#define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32
-#define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L]
-#define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL]
-#define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH]
-#define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H]
-#define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL]
-#define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH]
-#define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32
-#define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L]
-#define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL]
-#define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH]
-#define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H]
-#define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL]
-#define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH]
-#define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32
-#define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L]
-#define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL]
-#define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH]
-#define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H]
-#define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL]
-#define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH]
-#define RSCAN0RMID16 RSCAN0.RMID16.UINT32
-#define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L]
-#define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL]
-#define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH]
-#define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H]
-#define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL]
-#define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH]
-#define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32
-#define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L]
-#define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL]
-#define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH]
-#define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H]
-#define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL]
-#define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH]
-#define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32
-#define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L]
-#define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL]
-#define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH]
-#define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H]
-#define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL]
-#define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH]
-#define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32
-#define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L]
-#define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL]
-#define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH]
-#define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H]
-#define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL]
-#define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH]
-#define RSCAN0RMID17 RSCAN0.RMID17.UINT32
-#define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L]
-#define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL]
-#define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH]
-#define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H]
-#define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL]
-#define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH]
-#define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32
-#define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L]
-#define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL]
-#define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH]
-#define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H]
-#define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL]
-#define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH]
-#define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32
-#define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L]
-#define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL]
-#define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH]
-#define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H]
-#define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL]
-#define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH]
-#define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32
-#define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L]
-#define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL]
-#define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH]
-#define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H]
-#define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL]
-#define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH]
-#define RSCAN0RMID18 RSCAN0.RMID18.UINT32
-#define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L]
-#define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL]
-#define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH]
-#define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H]
-#define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL]
-#define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH]
-#define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32
-#define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L]
-#define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL]
-#define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH]
-#define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H]
-#define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL]
-#define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH]
-#define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32
-#define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L]
-#define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL]
-#define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH]
-#define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H]
-#define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL]
-#define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH]
-#define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32
-#define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L]
-#define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL]
-#define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH]
-#define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H]
-#define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL]
-#define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH]
-#define RSCAN0RMID19 RSCAN0.RMID19.UINT32
-#define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L]
-#define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL]
-#define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH]
-#define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H]
-#define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL]
-#define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH]
-#define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32
-#define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L]
-#define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL]
-#define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH]
-#define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H]
-#define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL]
-#define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH]
-#define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32
-#define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L]
-#define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL]
-#define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH]
-#define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H]
-#define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL]
-#define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH]
-#define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32
-#define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L]
-#define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL]
-#define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH]
-#define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H]
-#define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL]
-#define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH]
-#define RSCAN0RMID20 RSCAN0.RMID20.UINT32
-#define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L]
-#define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL]
-#define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH]
-#define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H]
-#define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL]
-#define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH]
-#define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32
-#define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L]
-#define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL]
-#define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH]
-#define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H]
-#define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL]
-#define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH]
-#define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32
-#define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L]
-#define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL]
-#define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH]
-#define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H]
-#define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL]
-#define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH]
-#define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32
-#define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L]
-#define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL]
-#define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH]
-#define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H]
-#define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL]
-#define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH]
-#define RSCAN0RMID21 RSCAN0.RMID21.UINT32
-#define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L]
-#define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL]
-#define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH]
-#define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H]
-#define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL]
-#define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH]
-#define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32
-#define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L]
-#define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL]
-#define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH]
-#define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H]
-#define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL]
-#define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH]
-#define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32
-#define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L]
-#define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL]
-#define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH]
-#define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H]
-#define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL]
-#define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH]
-#define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32
-#define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L]
-#define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL]
-#define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH]
-#define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H]
-#define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL]
-#define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH]
-#define RSCAN0RMID22 RSCAN0.RMID22.UINT32
-#define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L]
-#define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL]
-#define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH]
-#define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H]
-#define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL]
-#define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH]
-#define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32
-#define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L]
-#define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL]
-#define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH]
-#define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H]
-#define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL]
-#define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH]
-#define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32
-#define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L]
-#define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL]
-#define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH]
-#define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H]
-#define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL]
-#define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH]
-#define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32
-#define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L]
-#define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL]
-#define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH]
-#define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H]
-#define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL]
-#define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH]
-#define RSCAN0RMID23 RSCAN0.RMID23.UINT32
-#define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L]
-#define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL]
-#define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH]
-#define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H]
-#define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL]
-#define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH]
-#define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32
-#define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L]
-#define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL]
-#define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH]
-#define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H]
-#define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL]
-#define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH]
-#define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32
-#define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L]
-#define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL]
-#define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH]
-#define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H]
-#define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL]
-#define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH]
-#define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32
-#define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L]
-#define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL]
-#define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH]
-#define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H]
-#define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL]
-#define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH]
-#define RSCAN0RMID24 RSCAN0.RMID24.UINT32
-#define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L]
-#define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL]
-#define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH]
-#define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H]
-#define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL]
-#define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH]
-#define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32
-#define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L]
-#define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL]
-#define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH]
-#define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H]
-#define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL]
-#define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH]
-#define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32
-#define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L]
-#define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL]
-#define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH]
-#define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H]
-#define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL]
-#define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH]
-#define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32
-#define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L]
-#define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL]
-#define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH]
-#define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H]
-#define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL]
-#define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH]
-#define RSCAN0RMID25 RSCAN0.RMID25.UINT32
-#define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L]
-#define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL]
-#define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH]
-#define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H]
-#define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL]
-#define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH]
-#define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32
-#define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L]
-#define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL]
-#define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH]
-#define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H]
-#define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL]
-#define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH]
-#define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32
-#define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L]
-#define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL]
-#define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH]
-#define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H]
-#define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL]
-#define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH]
-#define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32
-#define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L]
-#define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL]
-#define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH]
-#define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H]
-#define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL]
-#define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH]
-#define RSCAN0RMID26 RSCAN0.RMID26.UINT32
-#define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L]
-#define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL]
-#define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH]
-#define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H]
-#define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL]
-#define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH]
-#define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32
-#define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L]
-#define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL]
-#define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH]
-#define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H]
-#define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL]
-#define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH]
-#define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32
-#define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L]
-#define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL]
-#define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH]
-#define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H]
-#define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL]
-#define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH]
-#define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32
-#define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L]
-#define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL]
-#define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH]
-#define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H]
-#define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL]
-#define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH]
-#define RSCAN0RMID27 RSCAN0.RMID27.UINT32
-#define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L]
-#define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL]
-#define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH]
-#define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H]
-#define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL]
-#define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH]
-#define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32
-#define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L]
-#define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL]
-#define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH]
-#define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H]
-#define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL]
-#define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH]
-#define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32
-#define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L]
-#define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL]
-#define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH]
-#define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H]
-#define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL]
-#define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH]
-#define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32
-#define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L]
-#define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL]
-#define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH]
-#define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H]
-#define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL]
-#define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH]
-#define RSCAN0RMID28 RSCAN0.RMID28.UINT32
-#define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L]
-#define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL]
-#define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH]
-#define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H]
-#define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL]
-#define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH]
-#define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32
-#define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L]
-#define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL]
-#define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH]
-#define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H]
-#define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL]
-#define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH]
-#define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32
-#define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L]
-#define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL]
-#define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH]
-#define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H]
-#define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL]
-#define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH]
-#define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32
-#define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L]
-#define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL]
-#define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH]
-#define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H]
-#define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL]
-#define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH]
-#define RSCAN0RMID29 RSCAN0.RMID29.UINT32
-#define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L]
-#define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL]
-#define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH]
-#define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H]
-#define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL]
-#define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH]
-#define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32
-#define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L]
-#define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL]
-#define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH]
-#define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H]
-#define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL]
-#define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH]
-#define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32
-#define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L]
-#define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL]
-#define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH]
-#define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H]
-#define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL]
-#define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH]
-#define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32
-#define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L]
-#define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL]
-#define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH]
-#define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H]
-#define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL]
-#define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH]
-#define RSCAN0RMID30 RSCAN0.RMID30.UINT32
-#define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L]
-#define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL]
-#define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH]
-#define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H]
-#define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL]
-#define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH]
-#define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32
-#define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L]
-#define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL]
-#define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH]
-#define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H]
-#define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL]
-#define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH]
-#define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32
-#define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L]
-#define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL]
-#define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH]
-#define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H]
-#define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL]
-#define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH]
-#define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32
-#define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L]
-#define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL]
-#define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH]
-#define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H]
-#define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL]
-#define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH]
-#define RSCAN0RMID31 RSCAN0.RMID31.UINT32
-#define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L]
-#define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL]
-#define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH]
-#define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H]
-#define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL]
-#define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH]
-#define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32
-#define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L]
-#define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL]
-#define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH]
-#define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H]
-#define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL]
-#define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH]
-#define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32
-#define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L]
-#define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL]
-#define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH]
-#define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H]
-#define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL]
-#define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH]
-#define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32
-#define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L]
-#define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL]
-#define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH]
-#define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H]
-#define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL]
-#define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH]
-#define RSCAN0RMID32 RSCAN0.RMID32.UINT32
-#define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L]
-#define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL]
-#define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH]
-#define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H]
-#define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL]
-#define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH]
-#define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32
-#define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L]
-#define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL]
-#define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH]
-#define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H]
-#define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL]
-#define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH]
-#define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32
-#define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L]
-#define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL]
-#define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH]
-#define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H]
-#define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL]
-#define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH]
-#define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32
-#define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L]
-#define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL]
-#define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH]
-#define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H]
-#define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL]
-#define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH]
-#define RSCAN0RMID33 RSCAN0.RMID33.UINT32
-#define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L]
-#define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL]
-#define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH]
-#define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H]
-#define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL]
-#define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH]
-#define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32
-#define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L]
-#define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL]
-#define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH]
-#define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H]
-#define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL]
-#define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH]
-#define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32
-#define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L]
-#define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL]
-#define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH]
-#define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H]
-#define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL]
-#define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH]
-#define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32
-#define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L]
-#define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL]
-#define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH]
-#define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H]
-#define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL]
-#define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH]
-#define RSCAN0RMID34 RSCAN0.RMID34.UINT32
-#define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L]
-#define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL]
-#define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH]
-#define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H]
-#define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL]
-#define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH]
-#define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32
-#define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L]
-#define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL]
-#define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH]
-#define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H]
-#define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL]
-#define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH]
-#define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32
-#define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L]
-#define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL]
-#define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH]
-#define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H]
-#define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL]
-#define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH]
-#define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32
-#define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L]
-#define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL]
-#define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH]
-#define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H]
-#define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL]
-#define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH]
-#define RSCAN0RMID35 RSCAN0.RMID35.UINT32
-#define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L]
-#define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL]
-#define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH]
-#define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H]
-#define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL]
-#define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH]
-#define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32
-#define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L]
-#define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL]
-#define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH]
-#define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H]
-#define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL]
-#define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH]
-#define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32
-#define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L]
-#define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL]
-#define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH]
-#define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H]
-#define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL]
-#define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH]
-#define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32
-#define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L]
-#define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL]
-#define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH]
-#define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H]
-#define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL]
-#define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH]
-#define RSCAN0RMID36 RSCAN0.RMID36.UINT32
-#define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L]
-#define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL]
-#define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH]
-#define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H]
-#define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL]
-#define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH]
-#define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32
-#define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L]
-#define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL]
-#define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH]
-#define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H]
-#define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL]
-#define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH]
-#define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32
-#define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L]
-#define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL]
-#define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH]
-#define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H]
-#define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL]
-#define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH]
-#define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32
-#define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L]
-#define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL]
-#define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH]
-#define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H]
-#define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL]
-#define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH]
-#define RSCAN0RMID37 RSCAN0.RMID37.UINT32
-#define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L]
-#define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL]
-#define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH]
-#define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H]
-#define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL]
-#define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH]
-#define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32
-#define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L]
-#define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL]
-#define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH]
-#define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H]
-#define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL]
-#define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH]
-#define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32
-#define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L]
-#define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL]
-#define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH]
-#define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H]
-#define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL]
-#define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH]
-#define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32
-#define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L]
-#define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL]
-#define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH]
-#define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H]
-#define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL]
-#define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH]
-#define RSCAN0RMID38 RSCAN0.RMID38.UINT32
-#define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L]
-#define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL]
-#define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH]
-#define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H]
-#define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL]
-#define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH]
-#define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32
-#define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L]
-#define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL]
-#define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH]
-#define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H]
-#define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL]
-#define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH]
-#define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32
-#define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L]
-#define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL]
-#define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH]
-#define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H]
-#define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL]
-#define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH]
-#define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32
-#define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L]
-#define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL]
-#define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH]
-#define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H]
-#define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL]
-#define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH]
-#define RSCAN0RMID39 RSCAN0.RMID39.UINT32
-#define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L]
-#define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL]
-#define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH]
-#define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H]
-#define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL]
-#define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH]
-#define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32
-#define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L]
-#define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL]
-#define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH]
-#define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H]
-#define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL]
-#define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH]
-#define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32
-#define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L]
-#define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL]
-#define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH]
-#define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H]
-#define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL]
-#define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH]
-#define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32
-#define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L]
-#define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL]
-#define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH]
-#define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H]
-#define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL]
-#define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH]
-#define RSCAN0RMID40 RSCAN0.RMID40.UINT32
-#define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L]
-#define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL]
-#define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH]
-#define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H]
-#define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL]
-#define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH]
-#define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32
-#define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L]
-#define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL]
-#define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH]
-#define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H]
-#define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL]
-#define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH]
-#define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32
-#define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L]
-#define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL]
-#define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH]
-#define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H]
-#define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL]
-#define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH]
-#define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32
-#define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L]
-#define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL]
-#define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH]
-#define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H]
-#define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL]
-#define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH]
-#define RSCAN0RMID41 RSCAN0.RMID41.UINT32
-#define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L]
-#define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL]
-#define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH]
-#define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H]
-#define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL]
-#define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH]
-#define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32
-#define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L]
-#define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL]
-#define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH]
-#define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H]
-#define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL]
-#define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH]
-#define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32
-#define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L]
-#define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL]
-#define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH]
-#define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H]
-#define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL]
-#define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH]
-#define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32
-#define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L]
-#define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL]
-#define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH]
-#define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H]
-#define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL]
-#define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH]
-#define RSCAN0RMID42 RSCAN0.RMID42.UINT32
-#define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L]
-#define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL]
-#define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH]
-#define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H]
-#define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL]
-#define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH]
-#define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32
-#define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L]
-#define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL]
-#define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH]
-#define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H]
-#define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL]
-#define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH]
-#define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32
-#define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L]
-#define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL]
-#define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH]
-#define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H]
-#define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL]
-#define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH]
-#define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32
-#define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L]
-#define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL]
-#define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH]
-#define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H]
-#define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL]
-#define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH]
-#define RSCAN0RMID43 RSCAN0.RMID43.UINT32
-#define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L]
-#define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL]
-#define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH]
-#define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H]
-#define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL]
-#define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH]
-#define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32
-#define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L]
-#define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL]
-#define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH]
-#define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H]
-#define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL]
-#define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH]
-#define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32
-#define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L]
-#define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL]
-#define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH]
-#define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H]
-#define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL]
-#define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH]
-#define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32
-#define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L]
-#define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL]
-#define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH]
-#define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H]
-#define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL]
-#define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH]
-#define RSCAN0RMID44 RSCAN0.RMID44.UINT32
-#define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L]
-#define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL]
-#define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH]
-#define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H]
-#define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL]
-#define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH]
-#define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32
-#define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L]
-#define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL]
-#define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH]
-#define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H]
-#define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL]
-#define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH]
-#define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32
-#define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L]
-#define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL]
-#define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH]
-#define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H]
-#define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL]
-#define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH]
-#define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32
-#define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L]
-#define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL]
-#define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH]
-#define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H]
-#define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL]
-#define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH]
-#define RSCAN0RMID45 RSCAN0.RMID45.UINT32
-#define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L]
-#define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL]
-#define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH]
-#define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H]
-#define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL]
-#define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH]
-#define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32
-#define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L]
-#define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL]
-#define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH]
-#define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H]
-#define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL]
-#define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH]
-#define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32
-#define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L]
-#define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL]
-#define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH]
-#define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H]
-#define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL]
-#define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH]
-#define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32
-#define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L]
-#define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL]
-#define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH]
-#define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H]
-#define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL]
-#define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH]
-#define RSCAN0RMID46 RSCAN0.RMID46.UINT32
-#define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L]
-#define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL]
-#define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH]
-#define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H]
-#define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL]
-#define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH]
-#define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32
-#define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L]
-#define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL]
-#define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH]
-#define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H]
-#define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL]
-#define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH]
-#define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32
-#define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L]
-#define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL]
-#define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH]
-#define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H]
-#define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL]
-#define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH]
-#define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32
-#define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L]
-#define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL]
-#define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH]
-#define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H]
-#define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL]
-#define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH]
-#define RSCAN0RMID47 RSCAN0.RMID47.UINT32
-#define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L]
-#define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL]
-#define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH]
-#define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H]
-#define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL]
-#define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH]
-#define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32
-#define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L]
-#define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL]
-#define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH]
-#define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H]
-#define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL]
-#define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH]
-#define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32
-#define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L]
-#define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL]
-#define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH]
-#define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H]
-#define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL]
-#define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH]
-#define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32
-#define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L]
-#define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL]
-#define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH]
-#define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H]
-#define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL]
-#define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH]
-#define RSCAN0RMID48 RSCAN0.RMID48.UINT32
-#define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L]
-#define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL]
-#define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH]
-#define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H]
-#define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL]
-#define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH]
-#define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32
-#define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L]
-#define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL]
-#define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH]
-#define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H]
-#define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL]
-#define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH]
-#define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32
-#define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L]
-#define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL]
-#define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH]
-#define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H]
-#define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL]
-#define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH]
-#define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32
-#define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L]
-#define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL]
-#define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH]
-#define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H]
-#define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL]
-#define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH]
-#define RSCAN0RMID49 RSCAN0.RMID49.UINT32
-#define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L]
-#define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL]
-#define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH]
-#define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H]
-#define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL]
-#define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH]
-#define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32
-#define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L]
-#define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL]
-#define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH]
-#define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H]
-#define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL]
-#define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH]
-#define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32
-#define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L]
-#define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL]
-#define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH]
-#define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H]
-#define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL]
-#define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH]
-#define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32
-#define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L]
-#define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL]
-#define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH]
-#define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H]
-#define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL]
-#define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH]
-#define RSCAN0RMID50 RSCAN0.RMID50.UINT32
-#define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L]
-#define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL]
-#define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH]
-#define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H]
-#define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL]
-#define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH]
-#define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32
-#define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L]
-#define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL]
-#define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH]
-#define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H]
-#define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL]
-#define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH]
-#define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32
-#define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L]
-#define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL]
-#define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH]
-#define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H]
-#define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL]
-#define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH]
-#define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32
-#define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L]
-#define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL]
-#define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH]
-#define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H]
-#define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL]
-#define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH]
-#define RSCAN0RMID51 RSCAN0.RMID51.UINT32
-#define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L]
-#define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL]
-#define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH]
-#define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H]
-#define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL]
-#define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH]
-#define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32
-#define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L]
-#define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL]
-#define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH]
-#define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H]
-#define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL]
-#define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH]
-#define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32
-#define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L]
-#define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL]
-#define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH]
-#define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H]
-#define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL]
-#define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH]
-#define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32
-#define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L]
-#define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL]
-#define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH]
-#define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H]
-#define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL]
-#define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH]
-#define RSCAN0RMID52 RSCAN0.RMID52.UINT32
-#define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L]
-#define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL]
-#define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH]
-#define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H]
-#define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL]
-#define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH]
-#define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32
-#define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L]
-#define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL]
-#define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH]
-#define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H]
-#define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL]
-#define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH]
-#define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32
-#define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L]
-#define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL]
-#define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH]
-#define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H]
-#define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL]
-#define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH]
-#define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32
-#define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L]
-#define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL]
-#define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH]
-#define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H]
-#define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL]
-#define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH]
-#define RSCAN0RMID53 RSCAN0.RMID53.UINT32
-#define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L]
-#define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL]
-#define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH]
-#define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H]
-#define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL]
-#define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH]
-#define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32
-#define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L]
-#define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL]
-#define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH]
-#define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H]
-#define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL]
-#define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH]
-#define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32
-#define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L]
-#define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL]
-#define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH]
-#define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H]
-#define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL]
-#define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH]
-#define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32
-#define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L]
-#define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL]
-#define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH]
-#define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H]
-#define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL]
-#define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH]
-#define RSCAN0RMID54 RSCAN0.RMID54.UINT32
-#define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L]
-#define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL]
-#define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH]
-#define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H]
-#define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL]
-#define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH]
-#define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32
-#define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L]
-#define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL]
-#define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH]
-#define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H]
-#define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL]
-#define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH]
-#define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32
-#define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L]
-#define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL]
-#define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH]
-#define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H]
-#define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL]
-#define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH]
-#define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32
-#define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L]
-#define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL]
-#define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH]
-#define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H]
-#define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL]
-#define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH]
-#define RSCAN0RMID55 RSCAN0.RMID55.UINT32
-#define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L]
-#define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL]
-#define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH]
-#define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H]
-#define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL]
-#define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH]
-#define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32
-#define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L]
-#define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL]
-#define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH]
-#define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H]
-#define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL]
-#define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH]
-#define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32
-#define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L]
-#define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL]
-#define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH]
-#define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H]
-#define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL]
-#define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH]
-#define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32
-#define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L]
-#define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL]
-#define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH]
-#define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H]
-#define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL]
-#define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH]
-#define RSCAN0RMID56 RSCAN0.RMID56.UINT32
-#define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L]
-#define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL]
-#define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH]
-#define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H]
-#define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL]
-#define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH]
-#define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32
-#define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L]
-#define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL]
-#define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH]
-#define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H]
-#define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL]
-#define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH]
-#define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32
-#define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L]
-#define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL]
-#define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH]
-#define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H]
-#define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL]
-#define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH]
-#define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32
-#define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L]
-#define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL]
-#define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH]
-#define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H]
-#define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL]
-#define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH]
-#define RSCAN0RMID57 RSCAN0.RMID57.UINT32
-#define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L]
-#define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL]
-#define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH]
-#define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H]
-#define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL]
-#define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH]
-#define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32
-#define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L]
-#define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL]
-#define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH]
-#define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H]
-#define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL]
-#define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH]
-#define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32
-#define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L]
-#define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL]
-#define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH]
-#define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H]
-#define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL]
-#define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH]
-#define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32
-#define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L]
-#define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL]
-#define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH]
-#define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H]
-#define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL]
-#define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH]
-#define RSCAN0RMID58 RSCAN0.RMID58.UINT32
-#define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L]
-#define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL]
-#define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH]
-#define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H]
-#define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL]
-#define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH]
-#define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32
-#define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L]
-#define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL]
-#define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH]
-#define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H]
-#define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL]
-#define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH]
-#define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32
-#define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L]
-#define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL]
-#define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH]
-#define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H]
-#define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL]
-#define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH]
-#define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32
-#define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L]
-#define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL]
-#define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH]
-#define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H]
-#define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL]
-#define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH]
-#define RSCAN0RMID59 RSCAN0.RMID59.UINT32
-#define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L]
-#define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL]
-#define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH]
-#define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H]
-#define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL]
-#define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH]
-#define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32
-#define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L]
-#define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL]
-#define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH]
-#define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H]
-#define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL]
-#define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH]
-#define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32
-#define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L]
-#define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL]
-#define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH]
-#define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H]
-#define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL]
-#define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH]
-#define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32
-#define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L]
-#define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL]
-#define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH]
-#define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H]
-#define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL]
-#define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH]
-#define RSCAN0RMID60 RSCAN0.RMID60.UINT32
-#define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L]
-#define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL]
-#define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH]
-#define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H]
-#define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL]
-#define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH]
-#define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32
-#define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L]
-#define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL]
-#define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH]
-#define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H]
-#define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL]
-#define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH]
-#define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32
-#define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L]
-#define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL]
-#define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH]
-#define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H]
-#define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL]
-#define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH]
-#define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32
-#define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L]
-#define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL]
-#define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH]
-#define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H]
-#define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL]
-#define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH]
-#define RSCAN0RMID61 RSCAN0.RMID61.UINT32
-#define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L]
-#define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL]
-#define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH]
-#define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H]
-#define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL]
-#define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH]
-#define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32
-#define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L]
-#define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL]
-#define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH]
-#define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H]
-#define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL]
-#define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH]
-#define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32
-#define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L]
-#define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL]
-#define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH]
-#define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H]
-#define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL]
-#define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH]
-#define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32
-#define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L]
-#define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL]
-#define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH]
-#define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H]
-#define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL]
-#define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH]
-#define RSCAN0RMID62 RSCAN0.RMID62.UINT32
-#define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L]
-#define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL]
-#define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH]
-#define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H]
-#define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL]
-#define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH]
-#define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32
-#define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L]
-#define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL]
-#define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH]
-#define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H]
-#define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL]
-#define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH]
-#define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32
-#define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L]
-#define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL]
-#define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH]
-#define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H]
-#define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL]
-#define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH]
-#define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32
-#define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L]
-#define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL]
-#define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH]
-#define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H]
-#define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL]
-#define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH]
-#define RSCAN0RMID63 RSCAN0.RMID63.UINT32
-#define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L]
-#define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL]
-#define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH]
-#define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H]
-#define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL]
-#define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH]
-#define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32
-#define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L]
-#define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL]
-#define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH]
-#define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H]
-#define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL]
-#define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH]
-#define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32
-#define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L]
-#define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL]
-#define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH]
-#define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H]
-#define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL]
-#define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH]
-#define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32
-#define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L]
-#define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL]
-#define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH]
-#define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H]
-#define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL]
-#define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH]
-#define RSCAN0RMID64 RSCAN0.RMID64.UINT32
-#define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L]
-#define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL]
-#define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH]
-#define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H]
-#define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL]
-#define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH]
-#define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32
-#define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L]
-#define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL]
-#define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH]
-#define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H]
-#define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL]
-#define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH]
-#define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32
-#define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L]
-#define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL]
-#define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH]
-#define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H]
-#define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL]
-#define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH]
-#define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32
-#define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L]
-#define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL]
-#define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH]
-#define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H]
-#define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL]
-#define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH]
-#define RSCAN0RMID65 RSCAN0.RMID65.UINT32
-#define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L]
-#define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL]
-#define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH]
-#define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H]
-#define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL]
-#define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH]
-#define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32
-#define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L]
-#define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL]
-#define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH]
-#define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H]
-#define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL]
-#define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH]
-#define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32
-#define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L]
-#define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL]
-#define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH]
-#define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H]
-#define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL]
-#define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH]
-#define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32
-#define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L]
-#define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL]
-#define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH]
-#define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H]
-#define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL]
-#define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH]
-#define RSCAN0RMID66 RSCAN0.RMID66.UINT32
-#define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L]
-#define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL]
-#define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH]
-#define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H]
-#define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL]
-#define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH]
-#define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32
-#define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L]
-#define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL]
-#define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH]
-#define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H]
-#define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL]
-#define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH]
-#define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32
-#define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L]
-#define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL]
-#define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH]
-#define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H]
-#define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL]
-#define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH]
-#define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32
-#define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L]
-#define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL]
-#define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH]
-#define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H]
-#define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL]
-#define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH]
-#define RSCAN0RMID67 RSCAN0.RMID67.UINT32
-#define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L]
-#define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL]
-#define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH]
-#define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H]
-#define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL]
-#define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH]
-#define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32
-#define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L]
-#define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL]
-#define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH]
-#define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H]
-#define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL]
-#define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH]
-#define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32
-#define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L]
-#define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL]
-#define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH]
-#define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H]
-#define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL]
-#define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH]
-#define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32
-#define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L]
-#define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL]
-#define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH]
-#define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H]
-#define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL]
-#define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH]
-#define RSCAN0RMID68 RSCAN0.RMID68.UINT32
-#define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L]
-#define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL]
-#define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH]
-#define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H]
-#define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL]
-#define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH]
-#define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32
-#define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L]
-#define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL]
-#define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH]
-#define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H]
-#define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL]
-#define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH]
-#define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32
-#define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L]
-#define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL]
-#define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH]
-#define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H]
-#define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL]
-#define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH]
-#define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32
-#define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L]
-#define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL]
-#define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH]
-#define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H]
-#define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL]
-#define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH]
-#define RSCAN0RMID69 RSCAN0.RMID69.UINT32
-#define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L]
-#define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL]
-#define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH]
-#define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H]
-#define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL]
-#define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH]
-#define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32
-#define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L]
-#define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL]
-#define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH]
-#define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H]
-#define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL]
-#define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH]
-#define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32
-#define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L]
-#define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL]
-#define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH]
-#define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H]
-#define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL]
-#define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH]
-#define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32
-#define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L]
-#define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL]
-#define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH]
-#define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H]
-#define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL]
-#define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH]
-#define RSCAN0RMID70 RSCAN0.RMID70.UINT32
-#define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L]
-#define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL]
-#define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH]
-#define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H]
-#define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL]
-#define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH]
-#define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32
-#define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L]
-#define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL]
-#define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH]
-#define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H]
-#define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL]
-#define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH]
-#define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32
-#define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L]
-#define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL]
-#define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH]
-#define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H]
-#define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL]
-#define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH]
-#define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32
-#define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L]
-#define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL]
-#define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH]
-#define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H]
-#define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL]
-#define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH]
-#define RSCAN0RMID71 RSCAN0.RMID71.UINT32
-#define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L]
-#define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL]
-#define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH]
-#define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H]
-#define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL]
-#define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH]
-#define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32
-#define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L]
-#define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL]
-#define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH]
-#define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H]
-#define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL]
-#define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH]
-#define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32
-#define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L]
-#define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL]
-#define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH]
-#define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H]
-#define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL]
-#define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH]
-#define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32
-#define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L]
-#define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL]
-#define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH]
-#define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H]
-#define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL]
-#define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH]
-#define RSCAN0RMID72 RSCAN0.RMID72.UINT32
-#define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L]
-#define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL]
-#define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH]
-#define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H]
-#define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL]
-#define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH]
-#define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32
-#define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L]
-#define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL]
-#define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH]
-#define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H]
-#define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL]
-#define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH]
-#define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32
-#define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L]
-#define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL]
-#define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH]
-#define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H]
-#define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL]
-#define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH]
-#define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32
-#define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L]
-#define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL]
-#define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH]
-#define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H]
-#define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL]
-#define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH]
-#define RSCAN0RMID73 RSCAN0.RMID73.UINT32
-#define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L]
-#define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL]
-#define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH]
-#define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H]
-#define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL]
-#define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH]
-#define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32
-#define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L]
-#define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL]
-#define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH]
-#define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H]
-#define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL]
-#define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH]
-#define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32
-#define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L]
-#define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL]
-#define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH]
-#define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H]
-#define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL]
-#define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH]
-#define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32
-#define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L]
-#define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL]
-#define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH]
-#define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H]
-#define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL]
-#define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH]
-#define RSCAN0RMID74 RSCAN0.RMID74.UINT32
-#define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L]
-#define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL]
-#define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH]
-#define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H]
-#define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL]
-#define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH]
-#define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32
-#define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L]
-#define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL]
-#define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH]
-#define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H]
-#define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL]
-#define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH]
-#define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32
-#define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L]
-#define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL]
-#define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH]
-#define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H]
-#define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL]
-#define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH]
-#define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32
-#define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L]
-#define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL]
-#define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH]
-#define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H]
-#define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL]
-#define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH]
-#define RSCAN0RMID75 RSCAN0.RMID75.UINT32
-#define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L]
-#define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL]
-#define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH]
-#define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H]
-#define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL]
-#define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH]
-#define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32
-#define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L]
-#define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL]
-#define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH]
-#define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H]
-#define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL]
-#define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH]
-#define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32
-#define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L]
-#define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL]
-#define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH]
-#define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H]
-#define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL]
-#define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH]
-#define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32
-#define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L]
-#define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL]
-#define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH]
-#define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H]
-#define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL]
-#define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH]
-#define RSCAN0RMID76 RSCAN0.RMID76.UINT32
-#define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L]
-#define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL]
-#define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH]
-#define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H]
-#define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL]
-#define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH]
-#define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32
-#define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L]
-#define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL]
-#define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH]
-#define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H]
-#define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL]
-#define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH]
-#define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32
-#define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L]
-#define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL]
-#define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH]
-#define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H]
-#define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL]
-#define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH]
-#define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32
-#define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L]
-#define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL]
-#define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH]
-#define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H]
-#define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL]
-#define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH]
-#define RSCAN0RMID77 RSCAN0.RMID77.UINT32
-#define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L]
-#define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL]
-#define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH]
-#define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H]
-#define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL]
-#define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH]
-#define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32
-#define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L]
-#define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL]
-#define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH]
-#define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H]
-#define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL]
-#define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH]
-#define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32
-#define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L]
-#define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL]
-#define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH]
-#define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H]
-#define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL]
-#define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH]
-#define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32
-#define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L]
-#define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL]
-#define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH]
-#define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H]
-#define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL]
-#define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH]
-#define RSCAN0RMID78 RSCAN0.RMID78.UINT32
-#define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L]
-#define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL]
-#define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH]
-#define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H]
-#define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL]
-#define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH]
-#define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32
-#define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L]
-#define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL]
-#define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH]
-#define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H]
-#define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL]
-#define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH]
-#define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32
-#define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L]
-#define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL]
-#define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH]
-#define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H]
-#define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL]
-#define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH]
-#define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32
-#define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L]
-#define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL]
-#define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH]
-#define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H]
-#define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL]
-#define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH]
-#define RSCAN0RMID79 RSCAN0.RMID79.UINT32
-#define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L]
-#define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL]
-#define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH]
-#define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H]
-#define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL]
-#define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH]
-#define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32
-#define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L]
-#define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL]
-#define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH]
-#define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H]
-#define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL]
-#define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH]
-#define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32
-#define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L]
-#define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL]
-#define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH]
-#define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H]
-#define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL]
-#define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH]
-#define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32
-#define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L]
-#define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL]
-#define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH]
-#define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H]
-#define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL]
-#define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH]
-#define RSCAN0RFID0 RSCAN0.RFID0.UINT32
-#define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L]
-#define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL]
-#define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH]
-#define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H]
-#define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL]
-#define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH]
-#define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32
-#define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L]
-#define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL]
-#define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH]
-#define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H]
-#define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL]
-#define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH]
-#define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32
-#define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L]
-#define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL]
-#define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH]
-#define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H]
-#define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL]
-#define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH]
-#define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32
-#define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L]
-#define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL]
-#define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH]
-#define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H]
-#define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL]
-#define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH]
-#define RSCAN0RFID1 RSCAN0.RFID1.UINT32
-#define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L]
-#define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL]
-#define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH]
-#define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H]
-#define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL]
-#define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH]
-#define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32
-#define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L]
-#define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL]
-#define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH]
-#define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H]
-#define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL]
-#define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH]
-#define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32
-#define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L]
-#define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL]
-#define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH]
-#define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H]
-#define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL]
-#define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH]
-#define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32
-#define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L]
-#define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL]
-#define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH]
-#define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H]
-#define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL]
-#define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH]
-#define RSCAN0RFID2 RSCAN0.RFID2.UINT32
-#define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L]
-#define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL]
-#define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH]
-#define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H]
-#define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL]
-#define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH]
-#define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32
-#define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L]
-#define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL]
-#define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH]
-#define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H]
-#define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL]
-#define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH]
-#define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32
-#define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L]
-#define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL]
-#define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH]
-#define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H]
-#define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL]
-#define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH]
-#define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32
-#define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L]
-#define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL]
-#define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH]
-#define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H]
-#define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL]
-#define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH]
-#define RSCAN0RFID3 RSCAN0.RFID3.UINT32
-#define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L]
-#define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL]
-#define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH]
-#define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H]
-#define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL]
-#define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH]
-#define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32
-#define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L]
-#define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL]
-#define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH]
-#define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H]
-#define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL]
-#define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH]
-#define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32
-#define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L]
-#define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL]
-#define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH]
-#define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H]
-#define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL]
-#define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH]
-#define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32
-#define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L]
-#define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL]
-#define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH]
-#define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H]
-#define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL]
-#define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH]
-#define RSCAN0RFID4 RSCAN0.RFID4.UINT32
-#define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L]
-#define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL]
-#define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH]
-#define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H]
-#define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL]
-#define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH]
-#define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32
-#define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L]
-#define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL]
-#define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH]
-#define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H]
-#define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL]
-#define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH]
-#define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32
-#define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L]
-#define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL]
-#define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH]
-#define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H]
-#define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL]
-#define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH]
-#define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32
-#define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L]
-#define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL]
-#define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH]
-#define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H]
-#define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL]
-#define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH]
-#define RSCAN0RFID5 RSCAN0.RFID5.UINT32
-#define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L]
-#define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL]
-#define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH]
-#define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H]
-#define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL]
-#define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH]
-#define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32
-#define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L]
-#define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL]
-#define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH]
-#define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H]
-#define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL]
-#define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH]
-#define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32
-#define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L]
-#define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL]
-#define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH]
-#define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H]
-#define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL]
-#define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH]
-#define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32
-#define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L]
-#define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL]
-#define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH]
-#define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H]
-#define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL]
-#define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH]
-#define RSCAN0RFID6 RSCAN0.RFID6.UINT32
-#define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L]
-#define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL]
-#define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH]
-#define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H]
-#define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL]
-#define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH]
-#define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32
-#define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L]
-#define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL]
-#define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH]
-#define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H]
-#define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL]
-#define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH]
-#define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32
-#define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L]
-#define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL]
-#define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH]
-#define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H]
-#define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL]
-#define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH]
-#define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32
-#define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L]
-#define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL]
-#define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH]
-#define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H]
-#define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL]
-#define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH]
-#define RSCAN0RFID7 RSCAN0.RFID7.UINT32
-#define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L]
-#define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL]
-#define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH]
-#define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H]
-#define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL]
-#define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH]
-#define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32
-#define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L]
-#define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL]
-#define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH]
-#define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H]
-#define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL]
-#define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH]
-#define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32
-#define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L]
-#define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL]
-#define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH]
-#define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H]
-#define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL]
-#define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH]
-#define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32
-#define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L]
-#define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL]
-#define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH]
-#define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H]
-#define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL]
-#define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH]
-#define RSCAN0CFID0 RSCAN0.CFID0.UINT32
-#define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L]
-#define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL]
-#define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH]
-#define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H]
-#define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL]
-#define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH]
-#define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32
-#define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L]
-#define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL]
-#define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH]
-#define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H]
-#define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL]
-#define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH]
-#define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32
-#define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L]
-#define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL]
-#define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH]
-#define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H]
-#define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL]
-#define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH]
-#define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32
-#define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L]
-#define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL]
-#define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH]
-#define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H]
-#define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL]
-#define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH]
-#define RSCAN0CFID1 RSCAN0.CFID1.UINT32
-#define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L]
-#define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL]
-#define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH]
-#define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H]
-#define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL]
-#define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH]
-#define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32
-#define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L]
-#define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL]
-#define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH]
-#define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H]
-#define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL]
-#define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH]
-#define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32
-#define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L]
-#define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL]
-#define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH]
-#define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H]
-#define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL]
-#define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH]
-#define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32
-#define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L]
-#define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL]
-#define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH]
-#define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H]
-#define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL]
-#define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH]
-#define RSCAN0CFID2 RSCAN0.CFID2.UINT32
-#define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L]
-#define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL]
-#define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH]
-#define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H]
-#define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL]
-#define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH]
-#define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32
-#define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L]
-#define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL]
-#define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH]
-#define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H]
-#define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL]
-#define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH]
-#define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32
-#define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L]
-#define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL]
-#define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH]
-#define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H]
-#define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL]
-#define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH]
-#define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32
-#define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L]
-#define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL]
-#define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH]
-#define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H]
-#define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL]
-#define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH]
-#define RSCAN0CFID3 RSCAN0.CFID3.UINT32
-#define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L]
-#define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL]
-#define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH]
-#define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H]
-#define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL]
-#define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH]
-#define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32
-#define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L]
-#define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL]
-#define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH]
-#define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H]
-#define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL]
-#define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH]
-#define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32
-#define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L]
-#define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL]
-#define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH]
-#define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H]
-#define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL]
-#define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH]
-#define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32
-#define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L]
-#define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL]
-#define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH]
-#define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H]
-#define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL]
-#define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH]
-#define RSCAN0CFID4 RSCAN0.CFID4.UINT32
-#define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L]
-#define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL]
-#define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH]
-#define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H]
-#define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL]
-#define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH]
-#define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32
-#define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L]
-#define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL]
-#define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH]
-#define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H]
-#define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL]
-#define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH]
-#define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32
-#define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L]
-#define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL]
-#define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH]
-#define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H]
-#define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL]
-#define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH]
-#define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32
-#define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L]
-#define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL]
-#define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH]
-#define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H]
-#define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL]
-#define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH]
-#define RSCAN0CFID5 RSCAN0.CFID5.UINT32
-#define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L]
-#define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL]
-#define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH]
-#define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H]
-#define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL]
-#define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH]
-#define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32
-#define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L]
-#define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL]
-#define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH]
-#define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H]
-#define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL]
-#define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH]
-#define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32
-#define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L]
-#define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL]
-#define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH]
-#define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H]
-#define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL]
-#define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH]
-#define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32
-#define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L]
-#define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL]
-#define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH]
-#define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H]
-#define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL]
-#define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH]
-#define RSCAN0CFID6 RSCAN0.CFID6.UINT32
-#define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L]
-#define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL]
-#define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH]
-#define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H]
-#define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL]
-#define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH]
-#define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32
-#define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L]
-#define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL]
-#define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH]
-#define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H]
-#define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL]
-#define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH]
-#define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32
-#define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L]
-#define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL]
-#define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH]
-#define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H]
-#define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL]
-#define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH]
-#define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32
-#define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L]
-#define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL]
-#define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH]
-#define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H]
-#define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL]
-#define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH]
-#define RSCAN0CFID7 RSCAN0.CFID7.UINT32
-#define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L]
-#define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL]
-#define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH]
-#define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H]
-#define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL]
-#define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH]
-#define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32
-#define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L]
-#define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL]
-#define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH]
-#define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H]
-#define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL]
-#define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH]
-#define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32
-#define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L]
-#define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL]
-#define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH]
-#define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H]
-#define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL]
-#define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH]
-#define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32
-#define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L]
-#define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL]
-#define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH]
-#define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H]
-#define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL]
-#define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH]
-#define RSCAN0CFID8 RSCAN0.CFID8.UINT32
-#define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L]
-#define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL]
-#define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH]
-#define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H]
-#define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL]
-#define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH]
-#define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32
-#define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L]
-#define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL]
-#define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH]
-#define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H]
-#define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL]
-#define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH]
-#define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32
-#define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L]
-#define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL]
-#define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH]
-#define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H]
-#define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL]
-#define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH]
-#define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32
-#define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L]
-#define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL]
-#define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH]
-#define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H]
-#define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL]
-#define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH]
-#define RSCAN0CFID9 RSCAN0.CFID9.UINT32
-#define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L]
-#define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL]
-#define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH]
-#define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H]
-#define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL]
-#define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH]
-#define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32
-#define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L]
-#define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL]
-#define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH]
-#define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H]
-#define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL]
-#define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH]
-#define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32
-#define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L]
-#define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL]
-#define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH]
-#define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H]
-#define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL]
-#define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH]
-#define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32
-#define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L]
-#define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL]
-#define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH]
-#define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H]
-#define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL]
-#define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH]
-#define RSCAN0CFID10 RSCAN0.CFID10.UINT32
-#define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L]
-#define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL]
-#define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH]
-#define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H]
-#define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL]
-#define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH]
-#define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32
-#define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L]
-#define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL]
-#define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH]
-#define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H]
-#define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL]
-#define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH]
-#define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32
-#define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L]
-#define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL]
-#define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH]
-#define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H]
-#define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL]
-#define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH]
-#define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32
-#define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L]
-#define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL]
-#define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH]
-#define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H]
-#define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL]
-#define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH]
-#define RSCAN0CFID11 RSCAN0.CFID11.UINT32
-#define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L]
-#define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL]
-#define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH]
-#define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H]
-#define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL]
-#define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH]
-#define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32
-#define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L]
-#define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL]
-#define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH]
-#define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H]
-#define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL]
-#define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH]
-#define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32
-#define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L]
-#define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL]
-#define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH]
-#define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H]
-#define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL]
-#define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH]
-#define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32
-#define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L]
-#define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL]
-#define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH]
-#define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H]
-#define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL]
-#define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH]
-#define RSCAN0CFID12 RSCAN0.CFID12.UINT32
-#define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L]
-#define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL]
-#define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH]
-#define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H]
-#define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL]
-#define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH]
-#define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32
-#define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L]
-#define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL]
-#define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH]
-#define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H]
-#define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL]
-#define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH]
-#define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32
-#define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L]
-#define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL]
-#define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH]
-#define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H]
-#define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL]
-#define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH]
-#define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32
-#define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L]
-#define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL]
-#define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH]
-#define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H]
-#define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL]
-#define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH]
-#define RSCAN0CFID13 RSCAN0.CFID13.UINT32
-#define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L]
-#define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL]
-#define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH]
-#define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H]
-#define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL]
-#define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH]
-#define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32
-#define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L]
-#define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL]
-#define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH]
-#define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H]
-#define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL]
-#define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH]
-#define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32
-#define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L]
-#define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL]
-#define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH]
-#define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H]
-#define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL]
-#define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH]
-#define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32
-#define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L]
-#define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL]
-#define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH]
-#define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H]
-#define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL]
-#define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH]
-#define RSCAN0CFID14 RSCAN0.CFID14.UINT32
-#define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L]
-#define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL]
-#define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH]
-#define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H]
-#define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL]
-#define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH]
-#define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32
-#define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L]
-#define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL]
-#define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH]
-#define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H]
-#define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL]
-#define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH]
-#define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32
-#define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L]
-#define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL]
-#define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH]
-#define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H]
-#define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL]
-#define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH]
-#define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32
-#define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L]
-#define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL]
-#define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH]
-#define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H]
-#define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL]
-#define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH]
-#define RSCAN0TMID0 RSCAN0.TMID0.UINT32
-#define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L]
-#define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL]
-#define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH]
-#define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H]
-#define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL]
-#define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH]
-#define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32
-#define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L]
-#define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL]
-#define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH]
-#define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H]
-#define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL]
-#define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH]
-#define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32
-#define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L]
-#define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL]
-#define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH]
-#define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H]
-#define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL]
-#define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH]
-#define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32
-#define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L]
-#define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL]
-#define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH]
-#define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H]
-#define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL]
-#define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH]
-#define RSCAN0TMID1 RSCAN0.TMID1.UINT32
-#define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L]
-#define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL]
-#define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH]
-#define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H]
-#define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL]
-#define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH]
-#define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32
-#define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L]
-#define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL]
-#define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH]
-#define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H]
-#define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL]
-#define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH]
-#define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32
-#define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L]
-#define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL]
-#define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH]
-#define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H]
-#define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL]
-#define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH]
-#define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32
-#define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L]
-#define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL]
-#define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH]
-#define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H]
-#define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL]
-#define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH]
-#define RSCAN0TMID2 RSCAN0.TMID2.UINT32
-#define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L]
-#define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL]
-#define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH]
-#define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H]
-#define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL]
-#define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH]
-#define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32
-#define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L]
-#define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL]
-#define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH]
-#define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H]
-#define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL]
-#define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH]
-#define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32
-#define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L]
-#define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL]
-#define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH]
-#define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H]
-#define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL]
-#define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH]
-#define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32
-#define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L]
-#define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL]
-#define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH]
-#define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H]
-#define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL]
-#define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH]
-#define RSCAN0TMID3 RSCAN0.TMID3.UINT32
-#define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L]
-#define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL]
-#define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH]
-#define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H]
-#define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL]
-#define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH]
-#define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32
-#define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L]
-#define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL]
-#define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH]
-#define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H]
-#define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL]
-#define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH]
-#define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32
-#define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L]
-#define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL]
-#define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH]
-#define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H]
-#define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL]
-#define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH]
-#define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32
-#define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L]
-#define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL]
-#define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH]
-#define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H]
-#define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL]
-#define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH]
-#define RSCAN0TMID4 RSCAN0.TMID4.UINT32
-#define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L]
-#define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL]
-#define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH]
-#define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H]
-#define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL]
-#define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH]
-#define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32
-#define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L]
-#define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL]
-#define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH]
-#define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H]
-#define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL]
-#define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH]
-#define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32
-#define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L]
-#define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL]
-#define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH]
-#define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H]
-#define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL]
-#define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH]
-#define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32
-#define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L]
-#define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL]
-#define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH]
-#define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H]
-#define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL]
-#define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH]
-#define RSCAN0TMID5 RSCAN0.TMID5.UINT32
-#define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L]
-#define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL]
-#define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH]
-#define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H]
-#define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL]
-#define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH]
-#define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32
-#define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L]
-#define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL]
-#define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH]
-#define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H]
-#define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL]
-#define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH]
-#define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32
-#define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L]
-#define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL]
-#define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH]
-#define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H]
-#define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL]
-#define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH]
-#define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32
-#define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L]
-#define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL]
-#define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH]
-#define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H]
-#define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL]
-#define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH]
-#define RSCAN0TMID6 RSCAN0.TMID6.UINT32
-#define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L]
-#define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL]
-#define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH]
-#define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H]
-#define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL]
-#define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH]
-#define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32
-#define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L]
-#define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL]
-#define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH]
-#define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H]
-#define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL]
-#define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH]
-#define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32
-#define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L]
-#define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL]
-#define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH]
-#define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H]
-#define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL]
-#define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH]
-#define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32
-#define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L]
-#define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL]
-#define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH]
-#define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H]
-#define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL]
-#define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH]
-#define RSCAN0TMID7 RSCAN0.TMID7.UINT32
-#define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L]
-#define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL]
-#define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH]
-#define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H]
-#define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL]
-#define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH]
-#define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32
-#define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L]
-#define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL]
-#define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH]
-#define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H]
-#define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL]
-#define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH]
-#define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32
-#define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L]
-#define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL]
-#define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH]
-#define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H]
-#define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL]
-#define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH]
-#define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32
-#define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L]
-#define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL]
-#define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH]
-#define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H]
-#define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL]
-#define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH]
-#define RSCAN0TMID8 RSCAN0.TMID8.UINT32
-#define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L]
-#define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL]
-#define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH]
-#define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H]
-#define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL]
-#define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH]
-#define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32
-#define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L]
-#define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL]
-#define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH]
-#define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H]
-#define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL]
-#define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH]
-#define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32
-#define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L]
-#define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL]
-#define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH]
-#define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H]
-#define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL]
-#define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH]
-#define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32
-#define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L]
-#define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL]
-#define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH]
-#define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H]
-#define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL]
-#define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH]
-#define RSCAN0TMID9 RSCAN0.TMID9.UINT32
-#define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L]
-#define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL]
-#define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH]
-#define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H]
-#define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL]
-#define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH]
-#define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32
-#define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L]
-#define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL]
-#define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH]
-#define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H]
-#define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL]
-#define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH]
-#define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32
-#define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L]
-#define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL]
-#define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH]
-#define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H]
-#define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL]
-#define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH]
-#define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32
-#define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L]
-#define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL]
-#define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH]
-#define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H]
-#define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL]
-#define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH]
-#define RSCAN0TMID10 RSCAN0.TMID10.UINT32
-#define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L]
-#define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL]
-#define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH]
-#define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H]
-#define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL]
-#define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH]
-#define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32
-#define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L]
-#define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL]
-#define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH]
-#define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H]
-#define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL]
-#define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH]
-#define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32
-#define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L]
-#define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL]
-#define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH]
-#define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H]
-#define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL]
-#define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH]
-#define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32
-#define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L]
-#define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL]
-#define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH]
-#define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H]
-#define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL]
-#define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH]
-#define RSCAN0TMID11 RSCAN0.TMID11.UINT32
-#define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L]
-#define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL]
-#define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH]
-#define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H]
-#define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL]
-#define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH]
-#define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32
-#define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L]
-#define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL]
-#define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH]
-#define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H]
-#define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL]
-#define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH]
-#define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32
-#define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L]
-#define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL]
-#define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH]
-#define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H]
-#define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL]
-#define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH]
-#define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32
-#define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L]
-#define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL]
-#define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH]
-#define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H]
-#define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL]
-#define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH]
-#define RSCAN0TMID12 RSCAN0.TMID12.UINT32
-#define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L]
-#define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL]
-#define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH]
-#define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H]
-#define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL]
-#define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH]
-#define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32
-#define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L]
-#define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL]
-#define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH]
-#define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H]
-#define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL]
-#define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH]
-#define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32
-#define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L]
-#define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL]
-#define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH]
-#define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H]
-#define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL]
-#define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH]
-#define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32
-#define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L]
-#define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL]
-#define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH]
-#define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H]
-#define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL]
-#define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH]
-#define RSCAN0TMID13 RSCAN0.TMID13.UINT32
-#define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L]
-#define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL]
-#define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH]
-#define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H]
-#define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL]
-#define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH]
-#define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32
-#define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L]
-#define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL]
-#define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH]
-#define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H]
-#define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL]
-#define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH]
-#define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32
-#define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L]
-#define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL]
-#define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH]
-#define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H]
-#define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL]
-#define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH]
-#define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32
-#define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L]
-#define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL]
-#define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH]
-#define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H]
-#define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL]
-#define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH]
-#define RSCAN0TMID14 RSCAN0.TMID14.UINT32
-#define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L]
-#define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL]
-#define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH]
-#define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H]
-#define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL]
-#define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH]
-#define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32
-#define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L]
-#define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL]
-#define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH]
-#define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H]
-#define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL]
-#define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH]
-#define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32
-#define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L]
-#define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL]
-#define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH]
-#define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H]
-#define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL]
-#define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH]
-#define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32
-#define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L]
-#define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL]
-#define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH]
-#define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H]
-#define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL]
-#define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH]
-#define RSCAN0TMID15 RSCAN0.TMID15.UINT32
-#define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L]
-#define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL]
-#define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH]
-#define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H]
-#define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL]
-#define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH]
-#define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32
-#define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L]
-#define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL]
-#define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH]
-#define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H]
-#define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL]
-#define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH]
-#define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32
-#define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L]
-#define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL]
-#define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH]
-#define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H]
-#define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL]
-#define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH]
-#define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32
-#define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L]
-#define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL]
-#define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH]
-#define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H]
-#define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL]
-#define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH]
-#define RSCAN0TMID16 RSCAN0.TMID16.UINT32
-#define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L]
-#define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL]
-#define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH]
-#define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H]
-#define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL]
-#define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH]
-#define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32
-#define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L]
-#define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL]
-#define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH]
-#define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H]
-#define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL]
-#define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH]
-#define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32
-#define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L]
-#define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL]
-#define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH]
-#define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H]
-#define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL]
-#define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH]
-#define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32
-#define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L]
-#define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL]
-#define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH]
-#define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H]
-#define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL]
-#define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH]
-#define RSCAN0TMID17 RSCAN0.TMID17.UINT32
-#define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L]
-#define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL]
-#define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH]
-#define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H]
-#define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL]
-#define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH]
-#define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32
-#define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L]
-#define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL]
-#define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH]
-#define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H]
-#define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL]
-#define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH]
-#define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32
-#define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L]
-#define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL]
-#define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH]
-#define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H]
-#define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL]
-#define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH]
-#define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32
-#define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L]
-#define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL]
-#define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH]
-#define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H]
-#define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL]
-#define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH]
-#define RSCAN0TMID18 RSCAN0.TMID18.UINT32
-#define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L]
-#define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL]
-#define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH]
-#define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H]
-#define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL]
-#define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH]
-#define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32
-#define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L]
-#define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL]
-#define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH]
-#define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H]
-#define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL]
-#define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH]
-#define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32
-#define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L]
-#define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL]
-#define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH]
-#define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H]
-#define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL]
-#define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH]
-#define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32
-#define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L]
-#define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL]
-#define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH]
-#define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H]
-#define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL]
-#define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH]
-#define RSCAN0TMID19 RSCAN0.TMID19.UINT32
-#define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L]
-#define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL]
-#define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH]
-#define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H]
-#define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL]
-#define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH]
-#define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32
-#define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L]
-#define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL]
-#define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH]
-#define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H]
-#define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL]
-#define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH]
-#define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32
-#define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L]
-#define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL]
-#define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH]
-#define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H]
-#define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL]
-#define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH]
-#define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32
-#define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L]
-#define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL]
-#define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH]
-#define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H]
-#define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL]
-#define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH]
-#define RSCAN0TMID20 RSCAN0.TMID20.UINT32
-#define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L]
-#define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL]
-#define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH]
-#define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H]
-#define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL]
-#define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH]
-#define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32
-#define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L]
-#define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL]
-#define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH]
-#define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H]
-#define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL]
-#define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH]
-#define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32
-#define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L]
-#define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL]
-#define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH]
-#define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H]
-#define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL]
-#define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH]
-#define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32
-#define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L]
-#define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL]
-#define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH]
-#define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H]
-#define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL]
-#define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH]
-#define RSCAN0TMID21 RSCAN0.TMID21.UINT32
-#define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L]
-#define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL]
-#define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH]
-#define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H]
-#define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL]
-#define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH]
-#define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32
-#define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L]
-#define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL]
-#define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH]
-#define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H]
-#define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL]
-#define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH]
-#define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32
-#define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L]
-#define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL]
-#define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH]
-#define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H]
-#define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL]
-#define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH]
-#define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32
-#define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L]
-#define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL]
-#define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH]
-#define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H]
-#define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL]
-#define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH]
-#define RSCAN0TMID22 RSCAN0.TMID22.UINT32
-#define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L]
-#define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL]
-#define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH]
-#define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H]
-#define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL]
-#define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH]
-#define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32
-#define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L]
-#define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL]
-#define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH]
-#define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H]
-#define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL]
-#define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH]
-#define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32
-#define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L]
-#define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL]
-#define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH]
-#define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H]
-#define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL]
-#define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH]
-#define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32
-#define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L]
-#define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL]
-#define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH]
-#define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H]
-#define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL]
-#define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH]
-#define RSCAN0TMID23 RSCAN0.TMID23.UINT32
-#define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L]
-#define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL]
-#define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH]
-#define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H]
-#define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL]
-#define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH]
-#define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32
-#define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L]
-#define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL]
-#define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH]
-#define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H]
-#define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL]
-#define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH]
-#define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32
-#define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L]
-#define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL]
-#define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH]
-#define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H]
-#define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL]
-#define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH]
-#define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32
-#define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L]
-#define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL]
-#define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH]
-#define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H]
-#define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL]
-#define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH]
-#define RSCAN0TMID24 RSCAN0.TMID24.UINT32
-#define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L]
-#define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL]
-#define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH]
-#define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H]
-#define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL]
-#define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH]
-#define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32
-#define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L]
-#define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL]
-#define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH]
-#define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H]
-#define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL]
-#define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH]
-#define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32
-#define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L]
-#define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL]
-#define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH]
-#define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H]
-#define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL]
-#define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH]
-#define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32
-#define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L]
-#define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL]
-#define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH]
-#define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H]
-#define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL]
-#define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH]
-#define RSCAN0TMID25 RSCAN0.TMID25.UINT32
-#define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L]
-#define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL]
-#define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH]
-#define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H]
-#define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL]
-#define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH]
-#define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32
-#define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L]
-#define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL]
-#define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH]
-#define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H]
-#define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL]
-#define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH]
-#define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32
-#define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L]
-#define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL]
-#define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH]
-#define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H]
-#define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL]
-#define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH]
-#define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32
-#define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L]
-#define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL]
-#define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH]
-#define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H]
-#define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL]
-#define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH]
-#define RSCAN0TMID26 RSCAN0.TMID26.UINT32
-#define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L]
-#define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL]
-#define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH]
-#define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H]
-#define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL]
-#define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH]
-#define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32
-#define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L]
-#define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL]
-#define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH]
-#define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H]
-#define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL]
-#define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH]
-#define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32
-#define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L]
-#define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL]
-#define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH]
-#define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H]
-#define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL]
-#define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH]
-#define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32
-#define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L]
-#define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL]
-#define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH]
-#define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H]
-#define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL]
-#define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH]
-#define RSCAN0TMID27 RSCAN0.TMID27.UINT32
-#define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L]
-#define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL]
-#define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH]
-#define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H]
-#define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL]
-#define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH]
-#define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32
-#define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L]
-#define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL]
-#define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH]
-#define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H]
-#define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL]
-#define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH]
-#define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32
-#define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L]
-#define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL]
-#define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH]
-#define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H]
-#define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL]
-#define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH]
-#define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32
-#define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L]
-#define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL]
-#define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH]
-#define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H]
-#define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL]
-#define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH]
-#define RSCAN0TMID28 RSCAN0.TMID28.UINT32
-#define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L]
-#define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL]
-#define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH]
-#define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H]
-#define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL]
-#define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH]
-#define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32
-#define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L]
-#define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL]
-#define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH]
-#define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H]
-#define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL]
-#define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH]
-#define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32
-#define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L]
-#define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL]
-#define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH]
-#define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H]
-#define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL]
-#define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH]
-#define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32
-#define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L]
-#define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL]
-#define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH]
-#define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H]
-#define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL]
-#define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH]
-#define RSCAN0TMID29 RSCAN0.TMID29.UINT32
-#define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L]
-#define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL]
-#define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH]
-#define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H]
-#define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL]
-#define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH]
-#define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32
-#define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L]
-#define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL]
-#define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH]
-#define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H]
-#define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL]
-#define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH]
-#define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32
-#define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L]
-#define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL]
-#define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH]
-#define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H]
-#define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL]
-#define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH]
-#define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32
-#define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L]
-#define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL]
-#define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH]
-#define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H]
-#define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL]
-#define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH]
-#define RSCAN0TMID30 RSCAN0.TMID30.UINT32
-#define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L]
-#define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL]
-#define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH]
-#define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H]
-#define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL]
-#define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH]
-#define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32
-#define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L]
-#define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL]
-#define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH]
-#define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H]
-#define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL]
-#define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH]
-#define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32
-#define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L]
-#define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL]
-#define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH]
-#define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H]
-#define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL]
-#define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH]
-#define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32
-#define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L]
-#define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL]
-#define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH]
-#define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H]
-#define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL]
-#define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH]
-#define RSCAN0TMID31 RSCAN0.TMID31.UINT32
-#define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L]
-#define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL]
-#define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH]
-#define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H]
-#define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL]
-#define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH]
-#define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32
-#define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L]
-#define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL]
-#define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH]
-#define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H]
-#define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL]
-#define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH]
-#define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32
-#define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L]
-#define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL]
-#define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH]
-#define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H]
-#define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL]
-#define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH]
-#define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32
-#define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L]
-#define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL]
-#define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH]
-#define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H]
-#define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL]
-#define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH]
-#define RSCAN0TMID32 RSCAN0.TMID32.UINT32
-#define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L]
-#define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL]
-#define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH]
-#define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H]
-#define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL]
-#define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH]
-#define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32
-#define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L]
-#define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL]
-#define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH]
-#define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H]
-#define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL]
-#define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH]
-#define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32
-#define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L]
-#define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL]
-#define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH]
-#define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H]
-#define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL]
-#define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH]
-#define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32
-#define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L]
-#define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL]
-#define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH]
-#define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H]
-#define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL]
-#define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH]
-#define RSCAN0TMID33 RSCAN0.TMID33.UINT32
-#define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L]
-#define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL]
-#define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH]
-#define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H]
-#define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL]
-#define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH]
-#define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32
-#define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L]
-#define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL]
-#define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH]
-#define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H]
-#define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL]
-#define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH]
-#define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32
-#define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L]
-#define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL]
-#define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH]
-#define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H]
-#define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL]
-#define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH]
-#define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32
-#define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L]
-#define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL]
-#define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH]
-#define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H]
-#define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL]
-#define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH]
-#define RSCAN0TMID34 RSCAN0.TMID34.UINT32
-#define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L]
-#define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL]
-#define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH]
-#define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H]
-#define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL]
-#define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH]
-#define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32
-#define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L]
-#define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL]
-#define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH]
-#define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H]
-#define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL]
-#define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH]
-#define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32
-#define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L]
-#define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL]
-#define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH]
-#define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H]
-#define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL]
-#define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH]
-#define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32
-#define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L]
-#define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL]
-#define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH]
-#define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H]
-#define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL]
-#define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH]
-#define RSCAN0TMID35 RSCAN0.TMID35.UINT32
-#define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L]
-#define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL]
-#define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH]
-#define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H]
-#define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL]
-#define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH]
-#define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32
-#define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L]
-#define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL]
-#define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH]
-#define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H]
-#define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL]
-#define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH]
-#define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32
-#define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L]
-#define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL]
-#define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH]
-#define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H]
-#define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL]
-#define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH]
-#define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32
-#define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L]
-#define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL]
-#define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH]
-#define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H]
-#define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL]
-#define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH]
-#define RSCAN0TMID36 RSCAN0.TMID36.UINT32
-#define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L]
-#define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL]
-#define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH]
-#define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H]
-#define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL]
-#define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH]
-#define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32
-#define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L]
-#define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL]
-#define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH]
-#define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H]
-#define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL]
-#define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH]
-#define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32
-#define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L]
-#define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL]
-#define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH]
-#define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H]
-#define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL]
-#define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH]
-#define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32
-#define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L]
-#define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL]
-#define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH]
-#define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H]
-#define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL]
-#define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH]
-#define RSCAN0TMID37 RSCAN0.TMID37.UINT32
-#define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L]
-#define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL]
-#define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH]
-#define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H]
-#define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL]
-#define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH]
-#define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32
-#define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L]
-#define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL]
-#define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH]
-#define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H]
-#define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL]
-#define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH]
-#define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32
-#define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L]
-#define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL]
-#define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH]
-#define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H]
-#define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL]
-#define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH]
-#define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32
-#define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L]
-#define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL]
-#define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH]
-#define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H]
-#define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL]
-#define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH]
-#define RSCAN0TMID38 RSCAN0.TMID38.UINT32
-#define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L]
-#define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL]
-#define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH]
-#define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H]
-#define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL]
-#define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH]
-#define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32
-#define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L]
-#define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL]
-#define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH]
-#define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H]
-#define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL]
-#define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH]
-#define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32
-#define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L]
-#define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL]
-#define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH]
-#define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H]
-#define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL]
-#define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH]
-#define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32
-#define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L]
-#define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL]
-#define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH]
-#define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H]
-#define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL]
-#define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH]
-#define RSCAN0TMID39 RSCAN0.TMID39.UINT32
-#define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L]
-#define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL]
-#define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH]
-#define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H]
-#define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL]
-#define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH]
-#define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32
-#define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L]
-#define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL]
-#define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH]
-#define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H]
-#define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL]
-#define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH]
-#define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32
-#define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L]
-#define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL]
-#define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH]
-#define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H]
-#define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL]
-#define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH]
-#define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32
-#define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L]
-#define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL]
-#define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH]
-#define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H]
-#define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL]
-#define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH]
-#define RSCAN0TMID40 RSCAN0.TMID40.UINT32
-#define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L]
-#define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL]
-#define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH]
-#define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H]
-#define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL]
-#define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH]
-#define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32
-#define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L]
-#define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL]
-#define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH]
-#define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H]
-#define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL]
-#define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH]
-#define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32
-#define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L]
-#define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL]
-#define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH]
-#define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H]
-#define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL]
-#define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH]
-#define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32
-#define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L]
-#define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL]
-#define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH]
-#define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H]
-#define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL]
-#define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH]
-#define RSCAN0TMID41 RSCAN0.TMID41.UINT32
-#define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L]
-#define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL]
-#define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH]
-#define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H]
-#define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL]
-#define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH]
-#define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32
-#define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L]
-#define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL]
-#define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH]
-#define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H]
-#define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL]
-#define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH]
-#define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32
-#define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L]
-#define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL]
-#define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH]
-#define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H]
-#define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL]
-#define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH]
-#define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32
-#define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L]
-#define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL]
-#define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH]
-#define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H]
-#define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL]
-#define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH]
-#define RSCAN0TMID42 RSCAN0.TMID42.UINT32
-#define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L]
-#define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL]
-#define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH]
-#define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H]
-#define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL]
-#define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH]
-#define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32
-#define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L]
-#define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL]
-#define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH]
-#define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H]
-#define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL]
-#define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH]
-#define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32
-#define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L]
-#define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL]
-#define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH]
-#define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H]
-#define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL]
-#define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH]
-#define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32
-#define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L]
-#define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL]
-#define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH]
-#define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H]
-#define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL]
-#define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH]
-#define RSCAN0TMID43 RSCAN0.TMID43.UINT32
-#define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L]
-#define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL]
-#define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH]
-#define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H]
-#define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL]
-#define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH]
-#define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32
-#define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L]
-#define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL]
-#define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH]
-#define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H]
-#define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL]
-#define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH]
-#define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32
-#define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L]
-#define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL]
-#define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH]
-#define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H]
-#define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL]
-#define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH]
-#define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32
-#define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L]
-#define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL]
-#define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH]
-#define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H]
-#define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL]
-#define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH]
-#define RSCAN0TMID44 RSCAN0.TMID44.UINT32
-#define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L]
-#define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL]
-#define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH]
-#define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H]
-#define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL]
-#define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH]
-#define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32
-#define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L]
-#define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL]
-#define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH]
-#define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H]
-#define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL]
-#define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH]
-#define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32
-#define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L]
-#define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL]
-#define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH]
-#define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H]
-#define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL]
-#define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH]
-#define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32
-#define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L]
-#define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL]
-#define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH]
-#define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H]
-#define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL]
-#define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH]
-#define RSCAN0TMID45 RSCAN0.TMID45.UINT32
-#define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L]
-#define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL]
-#define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH]
-#define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H]
-#define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL]
-#define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH]
-#define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32
-#define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L]
-#define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL]
-#define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH]
-#define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H]
-#define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL]
-#define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH]
-#define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32
-#define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L]
-#define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL]
-#define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH]
-#define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H]
-#define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL]
-#define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH]
-#define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32
-#define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L]
-#define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL]
-#define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH]
-#define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H]
-#define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL]
-#define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH]
-#define RSCAN0TMID46 RSCAN0.TMID46.UINT32
-#define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L]
-#define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL]
-#define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH]
-#define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H]
-#define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL]
-#define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH]
-#define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32
-#define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L]
-#define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL]
-#define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH]
-#define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H]
-#define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL]
-#define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH]
-#define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32
-#define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L]
-#define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL]
-#define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH]
-#define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H]
-#define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL]
-#define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH]
-#define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32
-#define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L]
-#define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL]
-#define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH]
-#define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H]
-#define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL]
-#define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH]
-#define RSCAN0TMID47 RSCAN0.TMID47.UINT32
-#define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L]
-#define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL]
-#define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH]
-#define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H]
-#define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL]
-#define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH]
-#define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32
-#define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L]
-#define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL]
-#define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH]
-#define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H]
-#define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL]
-#define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH]
-#define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32
-#define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L]
-#define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL]
-#define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH]
-#define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H]
-#define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL]
-#define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH]
-#define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32
-#define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L]
-#define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL]
-#define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH]
-#define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H]
-#define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL]
-#define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH]
-#define RSCAN0TMID48 RSCAN0.TMID48.UINT32
-#define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L]
-#define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL]
-#define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH]
-#define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H]
-#define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL]
-#define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH]
-#define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32
-#define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L]
-#define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL]
-#define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH]
-#define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H]
-#define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL]
-#define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH]
-#define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32
-#define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L]
-#define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL]
-#define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH]
-#define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H]
-#define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL]
-#define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH]
-#define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32
-#define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L]
-#define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL]
-#define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH]
-#define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H]
-#define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL]
-#define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH]
-#define RSCAN0TMID49 RSCAN0.TMID49.UINT32
-#define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L]
-#define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL]
-#define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH]
-#define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H]
-#define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL]
-#define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH]
-#define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32
-#define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L]
-#define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL]
-#define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH]
-#define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H]
-#define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL]
-#define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH]
-#define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32
-#define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L]
-#define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL]
-#define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH]
-#define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H]
-#define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL]
-#define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH]
-#define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32
-#define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L]
-#define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL]
-#define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH]
-#define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H]
-#define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL]
-#define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH]
-#define RSCAN0TMID50 RSCAN0.TMID50.UINT32
-#define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L]
-#define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL]
-#define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH]
-#define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H]
-#define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL]
-#define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH]
-#define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32
-#define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L]
-#define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL]
-#define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH]
-#define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H]
-#define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL]
-#define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH]
-#define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32
-#define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L]
-#define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL]
-#define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH]
-#define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H]
-#define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL]
-#define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH]
-#define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32
-#define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L]
-#define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL]
-#define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH]
-#define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H]
-#define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL]
-#define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH]
-#define RSCAN0TMID51 RSCAN0.TMID51.UINT32
-#define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L]
-#define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL]
-#define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH]
-#define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H]
-#define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL]
-#define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH]
-#define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32
-#define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L]
-#define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL]
-#define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH]
-#define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H]
-#define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL]
-#define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH]
-#define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32
-#define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L]
-#define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL]
-#define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH]
-#define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H]
-#define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL]
-#define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH]
-#define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32
-#define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L]
-#define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL]
-#define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH]
-#define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H]
-#define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL]
-#define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH]
-#define RSCAN0TMID52 RSCAN0.TMID52.UINT32
-#define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L]
-#define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL]
-#define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH]
-#define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H]
-#define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL]
-#define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH]
-#define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32
-#define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L]
-#define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL]
-#define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH]
-#define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H]
-#define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL]
-#define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH]
-#define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32
-#define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L]
-#define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL]
-#define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH]
-#define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H]
-#define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL]
-#define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH]
-#define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32
-#define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L]
-#define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL]
-#define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH]
-#define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H]
-#define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL]
-#define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH]
-#define RSCAN0TMID53 RSCAN0.TMID53.UINT32
-#define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L]
-#define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL]
-#define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH]
-#define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H]
-#define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL]
-#define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH]
-#define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32
-#define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L]
-#define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL]
-#define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH]
-#define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H]
-#define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL]
-#define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH]
-#define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32
-#define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L]
-#define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL]
-#define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH]
-#define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H]
-#define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL]
-#define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH]
-#define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32
-#define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L]
-#define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL]
-#define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH]
-#define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H]
-#define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL]
-#define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH]
-#define RSCAN0TMID54 RSCAN0.TMID54.UINT32
-#define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L]
-#define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL]
-#define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH]
-#define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H]
-#define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL]
-#define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH]
-#define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32
-#define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L]
-#define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL]
-#define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH]
-#define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H]
-#define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL]
-#define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH]
-#define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32
-#define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L]
-#define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL]
-#define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH]
-#define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H]
-#define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL]
-#define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH]
-#define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32
-#define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L]
-#define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL]
-#define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH]
-#define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H]
-#define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL]
-#define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH]
-#define RSCAN0TMID55 RSCAN0.TMID55.UINT32
-#define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L]
-#define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL]
-#define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH]
-#define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H]
-#define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL]
-#define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH]
-#define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32
-#define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L]
-#define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL]
-#define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH]
-#define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H]
-#define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL]
-#define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH]
-#define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32
-#define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L]
-#define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL]
-#define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH]
-#define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H]
-#define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL]
-#define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH]
-#define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32
-#define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L]
-#define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL]
-#define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH]
-#define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H]
-#define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL]
-#define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH]
-#define RSCAN0TMID56 RSCAN0.TMID56.UINT32
-#define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L]
-#define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL]
-#define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH]
-#define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H]
-#define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL]
-#define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH]
-#define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32
-#define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L]
-#define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL]
-#define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH]
-#define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H]
-#define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL]
-#define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH]
-#define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32
-#define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L]
-#define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL]
-#define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH]
-#define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H]
-#define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL]
-#define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH]
-#define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32
-#define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L]
-#define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL]
-#define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH]
-#define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H]
-#define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL]
-#define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH]
-#define RSCAN0TMID57 RSCAN0.TMID57.UINT32
-#define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L]
-#define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL]
-#define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH]
-#define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H]
-#define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL]
-#define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH]
-#define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32
-#define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L]
-#define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL]
-#define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH]
-#define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H]
-#define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL]
-#define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH]
-#define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32
-#define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L]
-#define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL]
-#define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH]
-#define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H]
-#define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL]
-#define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH]
-#define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32
-#define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L]
-#define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL]
-#define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH]
-#define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H]
-#define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL]
-#define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH]
-#define RSCAN0TMID58 RSCAN0.TMID58.UINT32
-#define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L]
-#define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL]
-#define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH]
-#define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H]
-#define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL]
-#define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH]
-#define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32
-#define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L]
-#define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL]
-#define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH]
-#define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H]
-#define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL]
-#define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH]
-#define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32
-#define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L]
-#define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL]
-#define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH]
-#define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H]
-#define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL]
-#define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH]
-#define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32
-#define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L]
-#define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL]
-#define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH]
-#define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H]
-#define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL]
-#define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH]
-#define RSCAN0TMID59 RSCAN0.TMID59.UINT32
-#define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L]
-#define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL]
-#define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH]
-#define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H]
-#define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL]
-#define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH]
-#define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32
-#define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L]
-#define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL]
-#define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH]
-#define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H]
-#define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL]
-#define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH]
-#define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32
-#define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L]
-#define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL]
-#define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH]
-#define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H]
-#define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL]
-#define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH]
-#define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32
-#define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L]
-#define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL]
-#define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH]
-#define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H]
-#define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL]
-#define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH]
-#define RSCAN0TMID60 RSCAN0.TMID60.UINT32
-#define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L]
-#define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL]
-#define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH]
-#define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H]
-#define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL]
-#define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH]
-#define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32
-#define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L]
-#define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL]
-#define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH]
-#define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H]
-#define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL]
-#define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH]
-#define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32
-#define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L]
-#define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL]
-#define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH]
-#define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H]
-#define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL]
-#define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH]
-#define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32
-#define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L]
-#define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL]
-#define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH]
-#define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H]
-#define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL]
-#define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH]
-#define RSCAN0TMID61 RSCAN0.TMID61.UINT32
-#define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L]
-#define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL]
-#define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH]
-#define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H]
-#define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL]
-#define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH]
-#define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32
-#define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L]
-#define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL]
-#define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH]
-#define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H]
-#define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL]
-#define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH]
-#define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32
-#define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L]
-#define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL]
-#define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH]
-#define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H]
-#define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL]
-#define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH]
-#define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32
-#define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L]
-#define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL]
-#define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH]
-#define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H]
-#define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL]
-#define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH]
-#define RSCAN0TMID62 RSCAN0.TMID62.UINT32
-#define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L]
-#define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL]
-#define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH]
-#define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H]
-#define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL]
-#define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH]
-#define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32
-#define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L]
-#define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL]
-#define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH]
-#define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H]
-#define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL]
-#define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH]
-#define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32
-#define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L]
-#define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL]
-#define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH]
-#define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H]
-#define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL]
-#define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH]
-#define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32
-#define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L]
-#define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL]
-#define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH]
-#define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H]
-#define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL]
-#define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH]
-#define RSCAN0TMID63 RSCAN0.TMID63.UINT32
-#define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L]
-#define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL]
-#define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH]
-#define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H]
-#define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL]
-#define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH]
-#define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32
-#define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L]
-#define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL]
-#define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH]
-#define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H]
-#define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL]
-#define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH]
-#define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32
-#define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L]
-#define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL]
-#define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH]
-#define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H]
-#define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL]
-#define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH]
-#define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32
-#define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L]
-#define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL]
-#define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH]
-#define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H]
-#define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL]
-#define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH]
-#define RSCAN0TMID64 RSCAN0.TMID64.UINT32
-#define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L]
-#define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL]
-#define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH]
-#define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H]
-#define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL]
-#define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH]
-#define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32
-#define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L]
-#define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL]
-#define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH]
-#define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H]
-#define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL]
-#define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH]
-#define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32
-#define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L]
-#define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL]
-#define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH]
-#define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H]
-#define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL]
-#define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH]
-#define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32
-#define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L]
-#define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL]
-#define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH]
-#define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H]
-#define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL]
-#define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH]
-#define RSCAN0TMID65 RSCAN0.TMID65.UINT32
-#define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L]
-#define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL]
-#define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH]
-#define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H]
-#define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL]
-#define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH]
-#define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32
-#define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L]
-#define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL]
-#define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH]
-#define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H]
-#define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL]
-#define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH]
-#define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32
-#define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L]
-#define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL]
-#define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH]
-#define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H]
-#define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL]
-#define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH]
-#define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32
-#define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L]
-#define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL]
-#define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH]
-#define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H]
-#define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL]
-#define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH]
-#define RSCAN0TMID66 RSCAN0.TMID66.UINT32
-#define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L]
-#define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL]
-#define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH]
-#define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H]
-#define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL]
-#define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH]
-#define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32
-#define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L]
-#define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL]
-#define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH]
-#define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H]
-#define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL]
-#define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH]
-#define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32
-#define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L]
-#define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL]
-#define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH]
-#define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H]
-#define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL]
-#define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH]
-#define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32
-#define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L]
-#define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL]
-#define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH]
-#define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H]
-#define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL]
-#define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH]
-#define RSCAN0TMID67 RSCAN0.TMID67.UINT32
-#define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L]
-#define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL]
-#define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH]
-#define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H]
-#define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL]
-#define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH]
-#define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32
-#define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L]
-#define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL]
-#define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH]
-#define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H]
-#define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL]
-#define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH]
-#define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32
-#define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L]
-#define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL]
-#define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH]
-#define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H]
-#define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL]
-#define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH]
-#define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32
-#define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L]
-#define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL]
-#define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH]
-#define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H]
-#define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL]
-#define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH]
-#define RSCAN0TMID68 RSCAN0.TMID68.UINT32
-#define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L]
-#define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL]
-#define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH]
-#define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H]
-#define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL]
-#define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH]
-#define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32
-#define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L]
-#define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL]
-#define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH]
-#define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H]
-#define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL]
-#define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH]
-#define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32
-#define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L]
-#define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL]
-#define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH]
-#define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H]
-#define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL]
-#define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH]
-#define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32
-#define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L]
-#define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL]
-#define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH]
-#define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H]
-#define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL]
-#define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH]
-#define RSCAN0TMID69 RSCAN0.TMID69.UINT32
-#define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L]
-#define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL]
-#define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH]
-#define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H]
-#define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL]
-#define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH]
-#define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32
-#define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L]
-#define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL]
-#define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH]
-#define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H]
-#define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL]
-#define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH]
-#define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32
-#define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L]
-#define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL]
-#define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH]
-#define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H]
-#define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL]
-#define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH]
-#define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32
-#define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L]
-#define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL]
-#define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH]
-#define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H]
-#define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL]
-#define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH]
-#define RSCAN0TMID70 RSCAN0.TMID70.UINT32
-#define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L]
-#define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL]
-#define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH]
-#define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H]
-#define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL]
-#define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH]
-#define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32
-#define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L]
-#define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL]
-#define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH]
-#define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H]
-#define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL]
-#define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH]
-#define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32
-#define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L]
-#define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL]
-#define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH]
-#define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H]
-#define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL]
-#define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH]
-#define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32
-#define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L]
-#define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL]
-#define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH]
-#define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H]
-#define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL]
-#define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH]
-#define RSCAN0TMID71 RSCAN0.TMID71.UINT32
-#define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L]
-#define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL]
-#define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH]
-#define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H]
-#define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL]
-#define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH]
-#define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32
-#define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L]
-#define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL]
-#define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH]
-#define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H]
-#define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL]
-#define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH]
-#define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32
-#define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L]
-#define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL]
-#define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH]
-#define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H]
-#define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL]
-#define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH]
-#define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32
-#define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L]
-#define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL]
-#define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH]
-#define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H]
-#define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL]
-#define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH]
-#define RSCAN0TMID72 RSCAN0.TMID72.UINT32
-#define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L]
-#define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL]
-#define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH]
-#define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H]
-#define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL]
-#define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH]
-#define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32
-#define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L]
-#define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL]
-#define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH]
-#define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H]
-#define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL]
-#define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH]
-#define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32
-#define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L]
-#define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL]
-#define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH]
-#define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H]
-#define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL]
-#define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH]
-#define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32
-#define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L]
-#define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL]
-#define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH]
-#define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H]
-#define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL]
-#define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH]
-#define RSCAN0TMID73 RSCAN0.TMID73.UINT32
-#define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L]
-#define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL]
-#define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH]
-#define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H]
-#define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL]
-#define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH]
-#define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32
-#define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L]
-#define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL]
-#define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH]
-#define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H]
-#define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL]
-#define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH]
-#define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32
-#define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L]
-#define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL]
-#define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH]
-#define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H]
-#define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL]
-#define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH]
-#define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32
-#define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L]
-#define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL]
-#define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH]
-#define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H]
-#define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL]
-#define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH]
-#define RSCAN0TMID74 RSCAN0.TMID74.UINT32
-#define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L]
-#define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL]
-#define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH]
-#define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H]
-#define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL]
-#define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH]
-#define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32
-#define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L]
-#define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL]
-#define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH]
-#define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H]
-#define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL]
-#define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH]
-#define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32
-#define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L]
-#define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL]
-#define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH]
-#define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H]
-#define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL]
-#define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH]
-#define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32
-#define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L]
-#define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL]
-#define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH]
-#define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H]
-#define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL]
-#define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH]
-#define RSCAN0TMID75 RSCAN0.TMID75.UINT32
-#define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L]
-#define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL]
-#define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH]
-#define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H]
-#define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL]
-#define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH]
-#define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32
-#define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L]
-#define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL]
-#define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH]
-#define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H]
-#define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL]
-#define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH]
-#define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32
-#define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L]
-#define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL]
-#define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH]
-#define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H]
-#define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL]
-#define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH]
-#define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32
-#define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L]
-#define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL]
-#define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH]
-#define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H]
-#define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL]
-#define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH]
-#define RSCAN0TMID76 RSCAN0.TMID76.UINT32
-#define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L]
-#define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL]
-#define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH]
-#define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H]
-#define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL]
-#define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH]
-#define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32
-#define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L]
-#define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL]
-#define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH]
-#define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H]
-#define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL]
-#define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH]
-#define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32
-#define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L]
-#define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL]
-#define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH]
-#define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H]
-#define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL]
-#define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH]
-#define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32
-#define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L]
-#define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL]
-#define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH]
-#define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H]
-#define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL]
-#define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH]
-#define RSCAN0TMID77 RSCAN0.TMID77.UINT32
-#define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L]
-#define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL]
-#define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH]
-#define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H]
-#define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL]
-#define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH]
-#define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32
-#define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L]
-#define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL]
-#define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH]
-#define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H]
-#define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL]
-#define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH]
-#define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32
-#define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L]
-#define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL]
-#define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH]
-#define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H]
-#define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL]
-#define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH]
-#define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32
-#define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L]
-#define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL]
-#define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH]
-#define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H]
-#define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL]
-#define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH]
-#define RSCAN0TMID78 RSCAN0.TMID78.UINT32
-#define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L]
-#define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL]
-#define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH]
-#define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H]
-#define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL]
-#define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH]
-#define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32
-#define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L]
-#define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL]
-#define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH]
-#define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H]
-#define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL]
-#define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH]
-#define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32
-#define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L]
-#define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL]
-#define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH]
-#define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H]
-#define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL]
-#define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH]
-#define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32
-#define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L]
-#define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL]
-#define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH]
-#define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H]
-#define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL]
-#define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH]
-#define RSCAN0TMID79 RSCAN0.TMID79.UINT32
-#define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L]
-#define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL]
-#define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH]
-#define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H]
-#define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL]
-#define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH]
-#define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32
-#define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L]
-#define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL]
-#define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH]
-#define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H]
-#define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL]
-#define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH]
-#define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32
-#define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L]
-#define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL]
-#define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH]
-#define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H]
-#define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL]
-#define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH]
-#define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32
-#define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L]
-#define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL]
-#define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH]
-#define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H]
-#define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL]
-#define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH]
-#define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32
-#define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L]
-#define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL]
-#define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH]
-#define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H]
-#define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL]
-#define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH]
-#define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32
-#define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L]
-#define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL]
-#define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH]
-#define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H]
-#define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL]
-#define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH]
-#define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32
-#define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L]
-#define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL]
-#define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH]
-#define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H]
-#define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL]
-#define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH]
-#define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32
-#define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L]
-#define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL]
-#define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH]
-#define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H]
-#define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL]
-#define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH]
-#define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32
-#define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L]
-#define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL]
-#define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH]
-#define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H]
-#define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL]
-#define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH]
+/* End of channel array defines of RSCAN0 */
+
+
+#define RSCAN0C0CFG (RSCAN0.C0CFG.UINT32)
+#define RSCAN0C0CFGL (RSCAN0.C0CFG.UINT16[R_IO_L])
+#define RSCAN0C0CFGLL (RSCAN0.C0CFG.UINT8[R_IO_LL])
+#define RSCAN0C0CFGLH (RSCAN0.C0CFG.UINT8[R_IO_LH])
+#define RSCAN0C0CFGH (RSCAN0.C0CFG.UINT16[R_IO_H])
+#define RSCAN0C0CFGHL (RSCAN0.C0CFG.UINT8[R_IO_HL])
+#define RSCAN0C0CFGHH (RSCAN0.C0CFG.UINT8[R_IO_HH])
+#define RSCAN0C0CTR (RSCAN0.C0CTR.UINT32)
+#define RSCAN0C0CTRL (RSCAN0.C0CTR.UINT16[R_IO_L])
+#define RSCAN0C0CTRLL (RSCAN0.C0CTR.UINT8[R_IO_LL])
+#define RSCAN0C0CTRLH (RSCAN0.C0CTR.UINT8[R_IO_LH])
+#define RSCAN0C0CTRH (RSCAN0.C0CTR.UINT16[R_IO_H])
+#define RSCAN0C0CTRHL (RSCAN0.C0CTR.UINT8[R_IO_HL])
+#define RSCAN0C0CTRHH (RSCAN0.C0CTR.UINT8[R_IO_HH])
+#define RSCAN0C0STS (RSCAN0.C0STS.UINT32)
+#define RSCAN0C0STSL (RSCAN0.C0STS.UINT16[R_IO_L])
+#define RSCAN0C0STSLL (RSCAN0.C0STS.UINT8[R_IO_LL])
+#define RSCAN0C0STSLH (RSCAN0.C0STS.UINT8[R_IO_LH])
+#define RSCAN0C0STSH (RSCAN0.C0STS.UINT16[R_IO_H])
+#define RSCAN0C0STSHL (RSCAN0.C0STS.UINT8[R_IO_HL])
+#define RSCAN0C0STSHH (RSCAN0.C0STS.UINT8[R_IO_HH])
+#define RSCAN0C0ERFL (RSCAN0.C0ERFL.UINT32)
+#define RSCAN0C0ERFLL (RSCAN0.C0ERFL.UINT16[R_IO_L])
+#define RSCAN0C0ERFLLL (RSCAN0.C0ERFL.UINT8[R_IO_LL])
+#define RSCAN0C0ERFLLH (RSCAN0.C0ERFL.UINT8[R_IO_LH])
+#define RSCAN0C0ERFLH (RSCAN0.C0ERFL.UINT16[R_IO_H])
+#define RSCAN0C0ERFLHL (RSCAN0.C0ERFL.UINT8[R_IO_HL])
+#define RSCAN0C0ERFLHH (RSCAN0.C0ERFL.UINT8[R_IO_HH])
+#define RSCAN0C1CFG (RSCAN0.C1CFG.UINT32)
+#define RSCAN0C1CFGL (RSCAN0.C1CFG.UINT16[R_IO_L])
+#define RSCAN0C1CFGLL (RSCAN0.C1CFG.UINT8[R_IO_LL])
+#define RSCAN0C1CFGLH (RSCAN0.C1CFG.UINT8[R_IO_LH])
+#define RSCAN0C1CFGH (RSCAN0.C1CFG.UINT16[R_IO_H])
+#define RSCAN0C1CFGHL (RSCAN0.C1CFG.UINT8[R_IO_HL])
+#define RSCAN0C1CFGHH (RSCAN0.C1CFG.UINT8[R_IO_HH])
+#define RSCAN0C1CTR (RSCAN0.C1CTR.UINT32)
+#define RSCAN0C1CTRL (RSCAN0.C1CTR.UINT16[R_IO_L])
+#define RSCAN0C1CTRLL (RSCAN0.C1CTR.UINT8[R_IO_LL])
+#define RSCAN0C1CTRLH (RSCAN0.C1CTR.UINT8[R_IO_LH])
+#define RSCAN0C1CTRH (RSCAN0.C1CTR.UINT16[R_IO_H])
+#define RSCAN0C1CTRHL (RSCAN0.C1CTR.UINT8[R_IO_HL])
+#define RSCAN0C1CTRHH (RSCAN0.C1CTR.UINT8[R_IO_HH])
+#define RSCAN0C1STS (RSCAN0.C1STS.UINT32)
+#define RSCAN0C1STSL (RSCAN0.C1STS.UINT16[R_IO_L])
+#define RSCAN0C1STSLL (RSCAN0.C1STS.UINT8[R_IO_LL])
+#define RSCAN0C1STSLH (RSCAN0.C1STS.UINT8[R_IO_LH])
+#define RSCAN0C1STSH (RSCAN0.C1STS.UINT16[R_IO_H])
+#define RSCAN0C1STSHL (RSCAN0.C1STS.UINT8[R_IO_HL])
+#define RSCAN0C1STSHH (RSCAN0.C1STS.UINT8[R_IO_HH])
+#define RSCAN0C1ERFL (RSCAN0.C1ERFL.UINT32)
+#define RSCAN0C1ERFLL (RSCAN0.C1ERFL.UINT16[R_IO_L])
+#define RSCAN0C1ERFLLL (RSCAN0.C1ERFL.UINT8[R_IO_LL])
+#define RSCAN0C1ERFLLH (RSCAN0.C1ERFL.UINT8[R_IO_LH])
+#define RSCAN0C1ERFLH (RSCAN0.C1ERFL.UINT16[R_IO_H])
+#define RSCAN0C1ERFLHL (RSCAN0.C1ERFL.UINT8[R_IO_HL])
+#define RSCAN0C1ERFLHH (RSCAN0.C1ERFL.UINT8[R_IO_HH])
+#define RSCAN0C2CFG (RSCAN0.C2CFG.UINT32)
+#define RSCAN0C2CFGL (RSCAN0.C2CFG.UINT16[R_IO_L])
+#define RSCAN0C2CFGLL (RSCAN0.C2CFG.UINT8[R_IO_LL])
+#define RSCAN0C2CFGLH (RSCAN0.C2CFG.UINT8[R_IO_LH])
+#define RSCAN0C2CFGH (RSCAN0.C2CFG.UINT16[R_IO_H])
+#define RSCAN0C2CFGHL (RSCAN0.C2CFG.UINT8[R_IO_HL])
+#define RSCAN0C2CFGHH (RSCAN0.C2CFG.UINT8[R_IO_HH])
+#define RSCAN0C2CTR (RSCAN0.C2CTR.UINT32)
+#define RSCAN0C2CTRL (RSCAN0.C2CTR.UINT16[R_IO_L])
+#define RSCAN0C2CTRLL (RSCAN0.C2CTR.UINT8[R_IO_LL])
+#define RSCAN0C2CTRLH (RSCAN0.C2CTR.UINT8[R_IO_LH])
+#define RSCAN0C2CTRH (RSCAN0.C2CTR.UINT16[R_IO_H])
+#define RSCAN0C2CTRHL (RSCAN0.C2CTR.UINT8[R_IO_HL])
+#define RSCAN0C2CTRHH (RSCAN0.C2CTR.UINT8[R_IO_HH])
+#define RSCAN0C2STS (RSCAN0.C2STS.UINT32)
+#define RSCAN0C2STSL (RSCAN0.C2STS.UINT16[R_IO_L])
+#define RSCAN0C2STSLL (RSCAN0.C2STS.UINT8[R_IO_LL])
+#define RSCAN0C2STSLH (RSCAN0.C2STS.UINT8[R_IO_LH])
+#define RSCAN0C2STSH (RSCAN0.C2STS.UINT16[R_IO_H])
+#define RSCAN0C2STSHL (RSCAN0.C2STS.UINT8[R_IO_HL])
+#define RSCAN0C2STSHH (RSCAN0.C2STS.UINT8[R_IO_HH])
+#define RSCAN0C2ERFL (RSCAN0.C2ERFL.UINT32)
+#define RSCAN0C2ERFLL (RSCAN0.C2ERFL.UINT16[R_IO_L])
+#define RSCAN0C2ERFLLL (RSCAN0.C2ERFL.UINT8[R_IO_LL])
+#define RSCAN0C2ERFLLH (RSCAN0.C2ERFL.UINT8[R_IO_LH])
+#define RSCAN0C2ERFLH (RSCAN0.C2ERFL.UINT16[R_IO_H])
+#define RSCAN0C2ERFLHL (RSCAN0.C2ERFL.UINT8[R_IO_HL])
+#define RSCAN0C2ERFLHH (RSCAN0.C2ERFL.UINT8[R_IO_HH])
+#define RSCAN0C3CFG (RSCAN0.C3CFG.UINT32)
+#define RSCAN0C3CFGL (RSCAN0.C3CFG.UINT16[R_IO_L])
+#define RSCAN0C3CFGLL (RSCAN0.C3CFG.UINT8[R_IO_LL])
+#define RSCAN0C3CFGLH (RSCAN0.C3CFG.UINT8[R_IO_LH])
+#define RSCAN0C3CFGH (RSCAN0.C3CFG.UINT16[R_IO_H])
+#define RSCAN0C3CFGHL (RSCAN0.C3CFG.UINT8[R_IO_HL])
+#define RSCAN0C3CFGHH (RSCAN0.C3CFG.UINT8[R_IO_HH])
+#define RSCAN0C3CTR (RSCAN0.C3CTR.UINT32)
+#define RSCAN0C3CTRL (RSCAN0.C3CTR.UINT16[R_IO_L])
+#define RSCAN0C3CTRLL (RSCAN0.C3CTR.UINT8[R_IO_LL])
+#define RSCAN0C3CTRLH (RSCAN0.C3CTR.UINT8[R_IO_LH])
+#define RSCAN0C3CTRH (RSCAN0.C3CTR.UINT16[R_IO_H])
+#define RSCAN0C3CTRHL (RSCAN0.C3CTR.UINT8[R_IO_HL])
+#define RSCAN0C3CTRHH (RSCAN0.C3CTR.UINT8[R_IO_HH])
+#define RSCAN0C3STS (RSCAN0.C3STS.UINT32)
+#define RSCAN0C3STSL (RSCAN0.C3STS.UINT16[R_IO_L])
+#define RSCAN0C3STSLL (RSCAN0.C3STS.UINT8[R_IO_LL])
+#define RSCAN0C3STSLH (RSCAN0.C3STS.UINT8[R_IO_LH])
+#define RSCAN0C3STSH (RSCAN0.C3STS.UINT16[R_IO_H])
+#define RSCAN0C3STSHL (RSCAN0.C3STS.UINT8[R_IO_HL])
+#define RSCAN0C3STSHH (RSCAN0.C3STS.UINT8[R_IO_HH])
+#define RSCAN0C3ERFL (RSCAN0.C3ERFL.UINT32)
+#define RSCAN0C3ERFLL (RSCAN0.C3ERFL.UINT16[R_IO_L])
+#define RSCAN0C3ERFLLL (RSCAN0.C3ERFL.UINT8[R_IO_LL])
+#define RSCAN0C3ERFLLH (RSCAN0.C3ERFL.UINT8[R_IO_LH])
+#define RSCAN0C3ERFLH (RSCAN0.C3ERFL.UINT16[R_IO_H])
+#define RSCAN0C3ERFLHL (RSCAN0.C3ERFL.UINT8[R_IO_HL])
+#define RSCAN0C3ERFLHH (RSCAN0.C3ERFL.UINT8[R_IO_HH])
+#define RSCAN0C4CFG (RSCAN0.C4CFG.UINT32)
+#define RSCAN0C4CFGL (RSCAN0.C4CFG.UINT16[R_IO_L])
+#define RSCAN0C4CFGLL (RSCAN0.C4CFG.UINT8[R_IO_LL])
+#define RSCAN0C4CFGLH (RSCAN0.C4CFG.UINT8[R_IO_LH])
+#define RSCAN0C4CFGH (RSCAN0.C4CFG.UINT16[R_IO_H])
+#define RSCAN0C4CFGHL (RSCAN0.C4CFG.UINT8[R_IO_HL])
+#define RSCAN0C4CFGHH (RSCAN0.C4CFG.UINT8[R_IO_HH])
+#define RSCAN0C4CTR (RSCAN0.C4CTR.UINT32)
+#define RSCAN0C4CTRL (RSCAN0.C4CTR.UINT16[R_IO_L])
+#define RSCAN0C4CTRLL (RSCAN0.C4CTR.UINT8[R_IO_LL])
+#define RSCAN0C4CTRLH (RSCAN0.C4CTR.UINT8[R_IO_LH])
+#define RSCAN0C4CTRH (RSCAN0.C4CTR.UINT16[R_IO_H])
+#define RSCAN0C4CTRHL (RSCAN0.C4CTR.UINT8[R_IO_HL])
+#define RSCAN0C4CTRHH (RSCAN0.C4CTR.UINT8[R_IO_HH])
+#define RSCAN0C4STS (RSCAN0.C4STS.UINT32)
+#define RSCAN0C4STSL (RSCAN0.C4STS.UINT16[R_IO_L])
+#define RSCAN0C4STSLL (RSCAN0.C4STS.UINT8[R_IO_LL])
+#define RSCAN0C4STSLH (RSCAN0.C4STS.UINT8[R_IO_LH])
+#define RSCAN0C4STSH (RSCAN0.C4STS.UINT16[R_IO_H])
+#define RSCAN0C4STSHL (RSCAN0.C4STS.UINT8[R_IO_HL])
+#define RSCAN0C4STSHH (RSCAN0.C4STS.UINT8[R_IO_HH])
+#define RSCAN0C4ERFL (RSCAN0.C4ERFL.UINT32)
+#define RSCAN0C4ERFLL (RSCAN0.C4ERFL.UINT16[R_IO_L])
+#define RSCAN0C4ERFLLL (RSCAN0.C4ERFL.UINT8[R_IO_LL])
+#define RSCAN0C4ERFLLH (RSCAN0.C4ERFL.UINT8[R_IO_LH])
+#define RSCAN0C4ERFLH (RSCAN0.C4ERFL.UINT16[R_IO_H])
+#define RSCAN0C4ERFLHL (RSCAN0.C4ERFL.UINT8[R_IO_HL])
+#define RSCAN0C4ERFLHH (RSCAN0.C4ERFL.UINT8[R_IO_HH])
+#define RSCAN0GCFG (RSCAN0.GCFG.UINT32)
+#define RSCAN0GCFGL (RSCAN0.GCFG.UINT16[R_IO_L])
+#define RSCAN0GCFGLL (RSCAN0.GCFG.UINT8[R_IO_LL])
+#define RSCAN0GCFGLH (RSCAN0.GCFG.UINT8[R_IO_LH])
+#define RSCAN0GCFGH (RSCAN0.GCFG.UINT16[R_IO_H])
+#define RSCAN0GCFGHL (RSCAN0.GCFG.UINT8[R_IO_HL])
+#define RSCAN0GCFGHH (RSCAN0.GCFG.UINT8[R_IO_HH])
+#define RSCAN0GCTR (RSCAN0.GCTR.UINT32)
+#define RSCAN0GCTRL (RSCAN0.GCTR.UINT16[R_IO_L])
+#define RSCAN0GCTRLL (RSCAN0.GCTR.UINT8[R_IO_LL])
+#define RSCAN0GCTRLH (RSCAN0.GCTR.UINT8[R_IO_LH])
+#define RSCAN0GCTRH (RSCAN0.GCTR.UINT16[R_IO_H])
+#define RSCAN0GCTRHL (RSCAN0.GCTR.UINT8[R_IO_HL])
+#define RSCAN0GCTRHH (RSCAN0.GCTR.UINT8[R_IO_HH])
+#define RSCAN0GSTS (RSCAN0.GSTS.UINT32)
+#define RSCAN0GSTSL (RSCAN0.GSTS.UINT16[R_IO_L])
+#define RSCAN0GSTSLL (RSCAN0.GSTS.UINT8[R_IO_LL])
+#define RSCAN0GSTSLH (RSCAN0.GSTS.UINT8[R_IO_LH])
+#define RSCAN0GSTSH (RSCAN0.GSTS.UINT16[R_IO_H])
+#define RSCAN0GSTSHL (RSCAN0.GSTS.UINT8[R_IO_HL])
+#define RSCAN0GSTSHH (RSCAN0.GSTS.UINT8[R_IO_HH])
+#define RSCAN0GERFL (RSCAN0.GERFL.UINT32)
+#define RSCAN0GERFLL (RSCAN0.GERFL.UINT16[R_IO_L])
+#define RSCAN0GERFLLL (RSCAN0.GERFL.UINT8[R_IO_LL])
+#define RSCAN0GERFLLH (RSCAN0.GERFL.UINT8[R_IO_LH])
+#define RSCAN0GERFLH (RSCAN0.GERFL.UINT16[R_IO_H])
+#define RSCAN0GERFLHL (RSCAN0.GERFL.UINT8[R_IO_HL])
+#define RSCAN0GERFLHH (RSCAN0.GERFL.UINT8[R_IO_HH])
+#define RSCAN0GTSC (RSCAN0.GTSC.UINT32)
+#define RSCAN0GTSCL (RSCAN0.GTSC.UINT16[R_IO_L])
+#define RSCAN0GTSCH (RSCAN0.GTSC.UINT16[R_IO_H])
+#define RSCAN0GAFLECTR (RSCAN0.GAFLECTR.UINT32)
+#define RSCAN0GAFLECTRL (RSCAN0.GAFLECTR.UINT16[R_IO_L])
+#define RSCAN0GAFLECTRLL (RSCAN0.GAFLECTR.UINT8[R_IO_LL])
+#define RSCAN0GAFLECTRLH (RSCAN0.GAFLECTR.UINT8[R_IO_LH])
+#define RSCAN0GAFLECTRH (RSCAN0.GAFLECTR.UINT16[R_IO_H])
+#define RSCAN0GAFLECTRHL (RSCAN0.GAFLECTR.UINT8[R_IO_HL])
+#define RSCAN0GAFLECTRHH (RSCAN0.GAFLECTR.UINT8[R_IO_HH])
+#define RSCAN0GAFLCFG0 (RSCAN0.GAFLCFG0.UINT32)
+#define RSCAN0GAFLCFG0L (RSCAN0.GAFLCFG0.UINT16[R_IO_L])
+#define RSCAN0GAFLCFG0LL (RSCAN0.GAFLCFG0.UINT8[R_IO_LL])
+#define RSCAN0GAFLCFG0LH (RSCAN0.GAFLCFG0.UINT8[R_IO_LH])
+#define RSCAN0GAFLCFG0H (RSCAN0.GAFLCFG0.UINT16[R_IO_H])
+#define RSCAN0GAFLCFG0HL (RSCAN0.GAFLCFG0.UINT8[R_IO_HL])
+#define RSCAN0GAFLCFG0HH (RSCAN0.GAFLCFG0.UINT8[R_IO_HH])
+#define RSCAN0GAFLCFG1 (RSCAN0.GAFLCFG1.UINT32)
+#define RSCAN0GAFLCFG1L (RSCAN0.GAFLCFG1.UINT16[R_IO_L])
+#define RSCAN0GAFLCFG1LL (RSCAN0.GAFLCFG1.UINT8[R_IO_LL])
+#define RSCAN0GAFLCFG1LH (RSCAN0.GAFLCFG1.UINT8[R_IO_LH])
+#define RSCAN0GAFLCFG1H (RSCAN0.GAFLCFG1.UINT16[R_IO_H])
+#define RSCAN0GAFLCFG1HL (RSCAN0.GAFLCFG1.UINT8[R_IO_HL])
+#define RSCAN0GAFLCFG1HH (RSCAN0.GAFLCFG1.UINT8[R_IO_HH])
+#define RSCAN0RMNB (RSCAN0.RMNB.UINT32)
+#define RSCAN0RMNBL (RSCAN0.RMNB.UINT16[R_IO_L])
+#define RSCAN0RMNBLL (RSCAN0.RMNB.UINT8[R_IO_LL])
+#define RSCAN0RMNBLH (RSCAN0.RMNB.UINT8[R_IO_LH])
+#define RSCAN0RMNBH (RSCAN0.RMNB.UINT16[R_IO_H])
+#define RSCAN0RMNBHL (RSCAN0.RMNB.UINT8[R_IO_HL])
+#define RSCAN0RMNBHH (RSCAN0.RMNB.UINT8[R_IO_HH])
+#define RSCAN0RMND0 (RSCAN0.RMND0.UINT32)
+#define RSCAN0RMND0L (RSCAN0.RMND0.UINT16[R_IO_L])
+#define RSCAN0RMND0LL (RSCAN0.RMND0.UINT8[R_IO_LL])
+#define RSCAN0RMND0LH (RSCAN0.RMND0.UINT8[R_IO_LH])
+#define RSCAN0RMND0H (RSCAN0.RMND0.UINT16[R_IO_H])
+#define RSCAN0RMND0HL (RSCAN0.RMND0.UINT8[R_IO_HL])
+#define RSCAN0RMND0HH (RSCAN0.RMND0.UINT8[R_IO_HH])
+#define RSCAN0RMND1 (RSCAN0.RMND1.UINT32)
+#define RSCAN0RMND1L (RSCAN0.RMND1.UINT16[R_IO_L])
+#define RSCAN0RMND1LL (RSCAN0.RMND1.UINT8[R_IO_LL])
+#define RSCAN0RMND1LH (RSCAN0.RMND1.UINT8[R_IO_LH])
+#define RSCAN0RMND1H (RSCAN0.RMND1.UINT16[R_IO_H])
+#define RSCAN0RMND1HL (RSCAN0.RMND1.UINT8[R_IO_HL])
+#define RSCAN0RMND1HH (RSCAN0.RMND1.UINT8[R_IO_HH])
+#define RSCAN0RMND2 (RSCAN0.RMND2.UINT32)
+#define RSCAN0RMND2L (RSCAN0.RMND2.UINT16[R_IO_L])
+#define RSCAN0RMND2LL (RSCAN0.RMND2.UINT8[R_IO_LL])
+#define RSCAN0RMND2LH (RSCAN0.RMND2.UINT8[R_IO_LH])
+#define RSCAN0RMND2H (RSCAN0.RMND2.UINT16[R_IO_H])
+#define RSCAN0RMND2HL (RSCAN0.RMND2.UINT8[R_IO_HL])
+#define RSCAN0RMND2HH (RSCAN0.RMND2.UINT8[R_IO_HH])
+#define RSCAN0RFCC0 (RSCAN0.RFCC0.UINT32)
+#define RSCAN0RFCC0L (RSCAN0.RFCC0.UINT16[R_IO_L])
+#define RSCAN0RFCC0LL (RSCAN0.RFCC0.UINT8[R_IO_LL])
+#define RSCAN0RFCC0LH (RSCAN0.RFCC0.UINT8[R_IO_LH])
+#define RSCAN0RFCC0H (RSCAN0.RFCC0.UINT16[R_IO_H])
+#define RSCAN0RFCC0HL (RSCAN0.RFCC0.UINT8[R_IO_HL])
+#define RSCAN0RFCC0HH (RSCAN0.RFCC0.UINT8[R_IO_HH])
+#define RSCAN0RFCC1 (RSCAN0.RFCC1.UINT32)
+#define RSCAN0RFCC1L (RSCAN0.RFCC1.UINT16[R_IO_L])
+#define RSCAN0RFCC1LL (RSCAN0.RFCC1.UINT8[R_IO_LL])
+#define RSCAN0RFCC1LH (RSCAN0.RFCC1.UINT8[R_IO_LH])
+#define RSCAN0RFCC1H (RSCAN0.RFCC1.UINT16[R_IO_H])
+#define RSCAN0RFCC1HL (RSCAN0.RFCC1.UINT8[R_IO_HL])
+#define RSCAN0RFCC1HH (RSCAN0.RFCC1.UINT8[R_IO_HH])
+#define RSCAN0RFCC2 (RSCAN0.RFCC2.UINT32)
+#define RSCAN0RFCC2L (RSCAN0.RFCC2.UINT16[R_IO_L])
+#define RSCAN0RFCC2LL (RSCAN0.RFCC2.UINT8[R_IO_LL])
+#define RSCAN0RFCC2LH (RSCAN0.RFCC2.UINT8[R_IO_LH])
+#define RSCAN0RFCC2H (RSCAN0.RFCC2.UINT16[R_IO_H])
+#define RSCAN0RFCC2HL (RSCAN0.RFCC2.UINT8[R_IO_HL])
+#define RSCAN0RFCC2HH (RSCAN0.RFCC2.UINT8[R_IO_HH])
+#define RSCAN0RFCC3 (RSCAN0.RFCC3.UINT32)
+#define RSCAN0RFCC3L (RSCAN0.RFCC3.UINT16[R_IO_L])
+#define RSCAN0RFCC3LL (RSCAN0.RFCC3.UINT8[R_IO_LL])
+#define RSCAN0RFCC3LH (RSCAN0.RFCC3.UINT8[R_IO_LH])
+#define RSCAN0RFCC3H (RSCAN0.RFCC3.UINT16[R_IO_H])
+#define RSCAN0RFCC3HL (RSCAN0.RFCC3.UINT8[R_IO_HL])
+#define RSCAN0RFCC3HH (RSCAN0.RFCC3.UINT8[R_IO_HH])
+#define RSCAN0RFCC4 (RSCAN0.RFCC4.UINT32)
+#define RSCAN0RFCC4L (RSCAN0.RFCC4.UINT16[R_IO_L])
+#define RSCAN0RFCC4LL (RSCAN0.RFCC4.UINT8[R_IO_LL])
+#define RSCAN0RFCC4LH (RSCAN0.RFCC4.UINT8[R_IO_LH])
+#define RSCAN0RFCC4H (RSCAN0.RFCC4.UINT16[R_IO_H])
+#define RSCAN0RFCC4HL (RSCAN0.RFCC4.UINT8[R_IO_HL])
+#define RSCAN0RFCC4HH (RSCAN0.RFCC4.UINT8[R_IO_HH])
+#define RSCAN0RFCC5 (RSCAN0.RFCC5.UINT32)
+#define RSCAN0RFCC5L (RSCAN0.RFCC5.UINT16[R_IO_L])
+#define RSCAN0RFCC5LL (RSCAN0.RFCC5.UINT8[R_IO_LL])
+#define RSCAN0RFCC5LH (RSCAN0.RFCC5.UINT8[R_IO_LH])
+#define RSCAN0RFCC5H (RSCAN0.RFCC5.UINT16[R_IO_H])
+#define RSCAN0RFCC5HL (RSCAN0.RFCC5.UINT8[R_IO_HL])
+#define RSCAN0RFCC5HH (RSCAN0.RFCC5.UINT8[R_IO_HH])
+#define RSCAN0RFCC6 (RSCAN0.RFCC6.UINT32)
+#define RSCAN0RFCC6L (RSCAN0.RFCC6.UINT16[R_IO_L])
+#define RSCAN0RFCC6LL (RSCAN0.RFCC6.UINT8[R_IO_LL])
+#define RSCAN0RFCC6LH (RSCAN0.RFCC6.UINT8[R_IO_LH])
+#define RSCAN0RFCC6H (RSCAN0.RFCC6.UINT16[R_IO_H])
+#define RSCAN0RFCC6HL (RSCAN0.RFCC6.UINT8[R_IO_HL])
+#define RSCAN0RFCC6HH (RSCAN0.RFCC6.UINT8[R_IO_HH])
+#define RSCAN0RFCC7 (RSCAN0.RFCC7.UINT32)
+#define RSCAN0RFCC7L (RSCAN0.RFCC7.UINT16[R_IO_L])
+#define RSCAN0RFCC7LL (RSCAN0.RFCC7.UINT8[R_IO_LL])
+#define RSCAN0RFCC7LH (RSCAN0.RFCC7.UINT8[R_IO_LH])
+#define RSCAN0RFCC7H (RSCAN0.RFCC7.UINT16[R_IO_H])
+#define RSCAN0RFCC7HL (RSCAN0.RFCC7.UINT8[R_IO_HL])
+#define RSCAN0RFCC7HH (RSCAN0.RFCC7.UINT8[R_IO_HH])
+#define RSCAN0RFSTS0 (RSCAN0.RFSTS0.UINT32)
+#define RSCAN0RFSTS0L (RSCAN0.RFSTS0.UINT16[R_IO_L])
+#define RSCAN0RFSTS0LL (RSCAN0.RFSTS0.UINT8[R_IO_LL])
+#define RSCAN0RFSTS0LH (RSCAN0.RFSTS0.UINT8[R_IO_LH])
+#define RSCAN0RFSTS0H (RSCAN0.RFSTS0.UINT16[R_IO_H])
+#define RSCAN0RFSTS0HL (RSCAN0.RFSTS0.UINT8[R_IO_HL])
+#define RSCAN0RFSTS0HH (RSCAN0.RFSTS0.UINT8[R_IO_HH])
+#define RSCAN0RFSTS1 (RSCAN0.RFSTS1.UINT32)
+#define RSCAN0RFSTS1L (RSCAN0.RFSTS1.UINT16[R_IO_L])
+#define RSCAN0RFSTS1LL (RSCAN0.RFSTS1.UINT8[R_IO_LL])
+#define RSCAN0RFSTS1LH (RSCAN0.RFSTS1.UINT8[R_IO_LH])
+#define RSCAN0RFSTS1H (RSCAN0.RFSTS1.UINT16[R_IO_H])
+#define RSCAN0RFSTS1HL (RSCAN0.RFSTS1.UINT8[R_IO_HL])
+#define RSCAN0RFSTS1HH (RSCAN0.RFSTS1.UINT8[R_IO_HH])
+#define RSCAN0RFSTS2 (RSCAN0.RFSTS2.UINT32)
+#define RSCAN0RFSTS2L (RSCAN0.RFSTS2.UINT16[R_IO_L])
+#define RSCAN0RFSTS2LL (RSCAN0.RFSTS2.UINT8[R_IO_LL])
+#define RSCAN0RFSTS2LH (RSCAN0.RFSTS2.UINT8[R_IO_LH])
+#define RSCAN0RFSTS2H (RSCAN0.RFSTS2.UINT16[R_IO_H])
+#define RSCAN0RFSTS2HL (RSCAN0.RFSTS2.UINT8[R_IO_HL])
+#define RSCAN0RFSTS2HH (RSCAN0.RFSTS2.UINT8[R_IO_HH])
+#define RSCAN0RFSTS3 (RSCAN0.RFSTS3.UINT32)
+#define RSCAN0RFSTS3L (RSCAN0.RFSTS3.UINT16[R_IO_L])
+#define RSCAN0RFSTS3LL (RSCAN0.RFSTS3.UINT8[R_IO_LL])
+#define RSCAN0RFSTS3LH (RSCAN0.RFSTS3.UINT8[R_IO_LH])
+#define RSCAN0RFSTS3H (RSCAN0.RFSTS3.UINT16[R_IO_H])
+#define RSCAN0RFSTS3HL (RSCAN0.RFSTS3.UINT8[R_IO_HL])
+#define RSCAN0RFSTS3HH (RSCAN0.RFSTS3.UINT8[R_IO_HH])
+#define RSCAN0RFSTS4 (RSCAN0.RFSTS4.UINT32)
+#define RSCAN0RFSTS4L (RSCAN0.RFSTS4.UINT16[R_IO_L])
+#define RSCAN0RFSTS4LL (RSCAN0.RFSTS4.UINT8[R_IO_LL])
+#define RSCAN0RFSTS4LH (RSCAN0.RFSTS4.UINT8[R_IO_LH])
+#define RSCAN0RFSTS4H (RSCAN0.RFSTS4.UINT16[R_IO_H])
+#define RSCAN0RFSTS4HL (RSCAN0.RFSTS4.UINT8[R_IO_HL])
+#define RSCAN0RFSTS4HH (RSCAN0.RFSTS4.UINT8[R_IO_HH])
+#define RSCAN0RFSTS5 (RSCAN0.RFSTS5.UINT32)
+#define RSCAN0RFSTS5L (RSCAN0.RFSTS5.UINT16[R_IO_L])
+#define RSCAN0RFSTS5LL (RSCAN0.RFSTS5.UINT8[R_IO_LL])
+#define RSCAN0RFSTS5LH (RSCAN0.RFSTS5.UINT8[R_IO_LH])
+#define RSCAN0RFSTS5H (RSCAN0.RFSTS5.UINT16[R_IO_H])
+#define RSCAN0RFSTS5HL (RSCAN0.RFSTS5.UINT8[R_IO_HL])
+#define RSCAN0RFSTS5HH (RSCAN0.RFSTS5.UINT8[R_IO_HH])
+#define RSCAN0RFSTS6 (RSCAN0.RFSTS6.UINT32)
+#define RSCAN0RFSTS6L (RSCAN0.RFSTS6.UINT16[R_IO_L])
+#define RSCAN0RFSTS6LL (RSCAN0.RFSTS6.UINT8[R_IO_LL])
+#define RSCAN0RFSTS6LH (RSCAN0.RFSTS6.UINT8[R_IO_LH])
+#define RSCAN0RFSTS6H (RSCAN0.RFSTS6.UINT16[R_IO_H])
+#define RSCAN0RFSTS6HL (RSCAN0.RFSTS6.UINT8[R_IO_HL])
+#define RSCAN0RFSTS6HH (RSCAN0.RFSTS6.UINT8[R_IO_HH])
+#define RSCAN0RFSTS7 (RSCAN0.RFSTS7.UINT32)
+#define RSCAN0RFSTS7L (RSCAN0.RFSTS7.UINT16[R_IO_L])
+#define RSCAN0RFSTS7LL (RSCAN0.RFSTS7.UINT8[R_IO_LL])
+#define RSCAN0RFSTS7LH (RSCAN0.RFSTS7.UINT8[R_IO_LH])
+#define RSCAN0RFSTS7H (RSCAN0.RFSTS7.UINT16[R_IO_H])
+#define RSCAN0RFSTS7HL (RSCAN0.RFSTS7.UINT8[R_IO_HL])
+#define RSCAN0RFSTS7HH (RSCAN0.RFSTS7.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR0 (RSCAN0.RFPCTR0.UINT32)
+#define RSCAN0RFPCTR0L (RSCAN0.RFPCTR0.UINT16[R_IO_L])
+#define RSCAN0RFPCTR0LL (RSCAN0.RFPCTR0.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR0LH (RSCAN0.RFPCTR0.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR0H (RSCAN0.RFPCTR0.UINT16[R_IO_H])
+#define RSCAN0RFPCTR0HL (RSCAN0.RFPCTR0.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR0HH (RSCAN0.RFPCTR0.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR1 (RSCAN0.RFPCTR1.UINT32)
+#define RSCAN0RFPCTR1L (RSCAN0.RFPCTR1.UINT16[R_IO_L])
+#define RSCAN0RFPCTR1LL (RSCAN0.RFPCTR1.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR1LH (RSCAN0.RFPCTR1.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR1H (RSCAN0.RFPCTR1.UINT16[R_IO_H])
+#define RSCAN0RFPCTR1HL (RSCAN0.RFPCTR1.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR1HH (RSCAN0.RFPCTR1.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR2 (RSCAN0.RFPCTR2.UINT32)
+#define RSCAN0RFPCTR2L (RSCAN0.RFPCTR2.UINT16[R_IO_L])
+#define RSCAN0RFPCTR2LL (RSCAN0.RFPCTR2.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR2LH (RSCAN0.RFPCTR2.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR2H (RSCAN0.RFPCTR2.UINT16[R_IO_H])
+#define RSCAN0RFPCTR2HL (RSCAN0.RFPCTR2.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR2HH (RSCAN0.RFPCTR2.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR3 (RSCAN0.RFPCTR3.UINT32)
+#define RSCAN0RFPCTR3L (RSCAN0.RFPCTR3.UINT16[R_IO_L])
+#define RSCAN0RFPCTR3LL (RSCAN0.RFPCTR3.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR3LH (RSCAN0.RFPCTR3.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR3H (RSCAN0.RFPCTR3.UINT16[R_IO_H])
+#define RSCAN0RFPCTR3HL (RSCAN0.RFPCTR3.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR3HH (RSCAN0.RFPCTR3.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR4 (RSCAN0.RFPCTR4.UINT32)
+#define RSCAN0RFPCTR4L (RSCAN0.RFPCTR4.UINT16[R_IO_L])
+#define RSCAN0RFPCTR4LL (RSCAN0.RFPCTR4.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR4LH (RSCAN0.RFPCTR4.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR4H (RSCAN0.RFPCTR4.UINT16[R_IO_H])
+#define RSCAN0RFPCTR4HL (RSCAN0.RFPCTR4.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR4HH (RSCAN0.RFPCTR4.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR5 (RSCAN0.RFPCTR5.UINT32)
+#define RSCAN0RFPCTR5L (RSCAN0.RFPCTR5.UINT16[R_IO_L])
+#define RSCAN0RFPCTR5LL (RSCAN0.RFPCTR5.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR5LH (RSCAN0.RFPCTR5.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR5H (RSCAN0.RFPCTR5.UINT16[R_IO_H])
+#define RSCAN0RFPCTR5HL (RSCAN0.RFPCTR5.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR5HH (RSCAN0.RFPCTR5.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR6 (RSCAN0.RFPCTR6.UINT32)
+#define RSCAN0RFPCTR6L (RSCAN0.RFPCTR6.UINT16[R_IO_L])
+#define RSCAN0RFPCTR6LL (RSCAN0.RFPCTR6.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR6LH (RSCAN0.RFPCTR6.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR6H (RSCAN0.RFPCTR6.UINT16[R_IO_H])
+#define RSCAN0RFPCTR6HL (RSCAN0.RFPCTR6.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR6HH (RSCAN0.RFPCTR6.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR7 (RSCAN0.RFPCTR7.UINT32)
+#define RSCAN0RFPCTR7L (RSCAN0.RFPCTR7.UINT16[R_IO_L])
+#define RSCAN0RFPCTR7LL (RSCAN0.RFPCTR7.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR7LH (RSCAN0.RFPCTR7.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR7H (RSCAN0.RFPCTR7.UINT16[R_IO_H])
+#define RSCAN0RFPCTR7HL (RSCAN0.RFPCTR7.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR7HH (RSCAN0.RFPCTR7.UINT8[R_IO_HH])
+#define RSCAN0CFCC0 (RSCAN0.CFCC0.UINT32)
+#define RSCAN0CFCC0L (RSCAN0.CFCC0.UINT16[R_IO_L])
+#define RSCAN0CFCC0LL (RSCAN0.CFCC0.UINT8[R_IO_LL])
+#define RSCAN0CFCC0LH (RSCAN0.CFCC0.UINT8[R_IO_LH])
+#define RSCAN0CFCC0H (RSCAN0.CFCC0.UINT16[R_IO_H])
+#define RSCAN0CFCC0HL (RSCAN0.CFCC0.UINT8[R_IO_HL])
+#define RSCAN0CFCC0HH (RSCAN0.CFCC0.UINT8[R_IO_HH])
+#define RSCAN0CFCC1 (RSCAN0.CFCC1.UINT32)
+#define RSCAN0CFCC1L (RSCAN0.CFCC1.UINT16[R_IO_L])
+#define RSCAN0CFCC1LL (RSCAN0.CFCC1.UINT8[R_IO_LL])
+#define RSCAN0CFCC1LH (RSCAN0.CFCC1.UINT8[R_IO_LH])
+#define RSCAN0CFCC1H (RSCAN0.CFCC1.UINT16[R_IO_H])
+#define RSCAN0CFCC1HL (RSCAN0.CFCC1.UINT8[R_IO_HL])
+#define RSCAN0CFCC1HH (RSCAN0.CFCC1.UINT8[R_IO_HH])
+#define RSCAN0CFCC2 (RSCAN0.CFCC2.UINT32)
+#define RSCAN0CFCC2L (RSCAN0.CFCC2.UINT16[R_IO_L])
+#define RSCAN0CFCC2LL (RSCAN0.CFCC2.UINT8[R_IO_LL])
+#define RSCAN0CFCC2LH (RSCAN0.CFCC2.UINT8[R_IO_LH])
+#define RSCAN0CFCC2H (RSCAN0.CFCC2.UINT16[R_IO_H])
+#define RSCAN0CFCC2HL (RSCAN0.CFCC2.UINT8[R_IO_HL])
+#define RSCAN0CFCC2HH (RSCAN0.CFCC2.UINT8[R_IO_HH])
+#define RSCAN0CFCC3 (RSCAN0.CFCC3.UINT32)
+#define RSCAN0CFCC3L (RSCAN0.CFCC3.UINT16[R_IO_L])
+#define RSCAN0CFCC3LL (RSCAN0.CFCC3.UINT8[R_IO_LL])
+#define RSCAN0CFCC3LH (RSCAN0.CFCC3.UINT8[R_IO_LH])
+#define RSCAN0CFCC3H (RSCAN0.CFCC3.UINT16[R_IO_H])
+#define RSCAN0CFCC3HL (RSCAN0.CFCC3.UINT8[R_IO_HL])
+#define RSCAN0CFCC3HH (RSCAN0.CFCC3.UINT8[R_IO_HH])
+#define RSCAN0CFCC4 (RSCAN0.CFCC4.UINT32)
+#define RSCAN0CFCC4L (RSCAN0.CFCC4.UINT16[R_IO_L])
+#define RSCAN0CFCC4LL (RSCAN0.CFCC4.UINT8[R_IO_LL])
+#define RSCAN0CFCC4LH (RSCAN0.CFCC4.UINT8[R_IO_LH])
+#define RSCAN0CFCC4H (RSCAN0.CFCC4.UINT16[R_IO_H])
+#define RSCAN0CFCC4HL (RSCAN0.CFCC4.UINT8[R_IO_HL])
+#define RSCAN0CFCC4HH (RSCAN0.CFCC4.UINT8[R_IO_HH])
+#define RSCAN0CFCC5 (RSCAN0.CFCC5.UINT32)
+#define RSCAN0CFCC5L (RSCAN0.CFCC5.UINT16[R_IO_L])
+#define RSCAN0CFCC5LL (RSCAN0.CFCC5.UINT8[R_IO_LL])
+#define RSCAN0CFCC5LH (RSCAN0.CFCC5.UINT8[R_IO_LH])
+#define RSCAN0CFCC5H (RSCAN0.CFCC5.UINT16[R_IO_H])
+#define RSCAN0CFCC5HL (RSCAN0.CFCC5.UINT8[R_IO_HL])
+#define RSCAN0CFCC5HH (RSCAN0.CFCC5.UINT8[R_IO_HH])
+#define RSCAN0CFCC6 (RSCAN0.CFCC6.UINT32)
+#define RSCAN0CFCC6L (RSCAN0.CFCC6.UINT16[R_IO_L])
+#define RSCAN0CFCC6LL (RSCAN0.CFCC6.UINT8[R_IO_LL])
+#define RSCAN0CFCC6LH (RSCAN0.CFCC6.UINT8[R_IO_LH])
+#define RSCAN0CFCC6H (RSCAN0.CFCC6.UINT16[R_IO_H])
+#define RSCAN0CFCC6HL (RSCAN0.CFCC6.UINT8[R_IO_HL])
+#define RSCAN0CFCC6HH (RSCAN0.CFCC6.UINT8[R_IO_HH])
+#define RSCAN0CFCC7 (RSCAN0.CFCC7.UINT32)
+#define RSCAN0CFCC7L (RSCAN0.CFCC7.UINT16[R_IO_L])
+#define RSCAN0CFCC7LL (RSCAN0.CFCC7.UINT8[R_IO_LL])
+#define RSCAN0CFCC7LH (RSCAN0.CFCC7.UINT8[R_IO_LH])
+#define RSCAN0CFCC7H (RSCAN0.CFCC7.UINT16[R_IO_H])
+#define RSCAN0CFCC7HL (RSCAN0.CFCC7.UINT8[R_IO_HL])
+#define RSCAN0CFCC7HH (RSCAN0.CFCC7.UINT8[R_IO_HH])
+#define RSCAN0CFCC8 (RSCAN0.CFCC8.UINT32)
+#define RSCAN0CFCC8L (RSCAN0.CFCC8.UINT16[R_IO_L])
+#define RSCAN0CFCC8LL (RSCAN0.CFCC8.UINT8[R_IO_LL])
+#define RSCAN0CFCC8LH (RSCAN0.CFCC8.UINT8[R_IO_LH])
+#define RSCAN0CFCC8H (RSCAN0.CFCC8.UINT16[R_IO_H])
+#define RSCAN0CFCC8HL (RSCAN0.CFCC8.UINT8[R_IO_HL])
+#define RSCAN0CFCC8HH (RSCAN0.CFCC8.UINT8[R_IO_HH])
+#define RSCAN0CFCC9 (RSCAN0.CFCC9.UINT32)
+#define RSCAN0CFCC9L (RSCAN0.CFCC9.UINT16[R_IO_L])
+#define RSCAN0CFCC9LL (RSCAN0.CFCC9.UINT8[R_IO_LL])
+#define RSCAN0CFCC9LH (RSCAN0.CFCC9.UINT8[R_IO_LH])
+#define RSCAN0CFCC9H (RSCAN0.CFCC9.UINT16[R_IO_H])
+#define RSCAN0CFCC9HL (RSCAN0.CFCC9.UINT8[R_IO_HL])
+#define RSCAN0CFCC9HH (RSCAN0.CFCC9.UINT8[R_IO_HH])
+#define RSCAN0CFCC10 (RSCAN0.CFCC10.UINT32)
+#define RSCAN0CFCC10L (RSCAN0.CFCC10.UINT16[R_IO_L])
+#define RSCAN0CFCC10LL (RSCAN0.CFCC10.UINT8[R_IO_LL])
+#define RSCAN0CFCC10LH (RSCAN0.CFCC10.UINT8[R_IO_LH])
+#define RSCAN0CFCC10H (RSCAN0.CFCC10.UINT16[R_IO_H])
+#define RSCAN0CFCC10HL (RSCAN0.CFCC10.UINT8[R_IO_HL])
+#define RSCAN0CFCC10HH (RSCAN0.CFCC10.UINT8[R_IO_HH])
+#define RSCAN0CFCC11 (RSCAN0.CFCC11.UINT32)
+#define RSCAN0CFCC11L (RSCAN0.CFCC11.UINT16[R_IO_L])
+#define RSCAN0CFCC11LL (RSCAN0.CFCC11.UINT8[R_IO_LL])
+#define RSCAN0CFCC11LH (RSCAN0.CFCC11.UINT8[R_IO_LH])
+#define RSCAN0CFCC11H (RSCAN0.CFCC11.UINT16[R_IO_H])
+#define RSCAN0CFCC11HL (RSCAN0.CFCC11.UINT8[R_IO_HL])
+#define RSCAN0CFCC11HH (RSCAN0.CFCC11.UINT8[R_IO_HH])
+#define RSCAN0CFCC12 (RSCAN0.CFCC12.UINT32)
+#define RSCAN0CFCC12L (RSCAN0.CFCC12.UINT16[R_IO_L])
+#define RSCAN0CFCC12LL (RSCAN0.CFCC12.UINT8[R_IO_LL])
+#define RSCAN0CFCC12LH (RSCAN0.CFCC12.UINT8[R_IO_LH])
+#define RSCAN0CFCC12H (RSCAN0.CFCC12.UINT16[R_IO_H])
+#define RSCAN0CFCC12HL (RSCAN0.CFCC12.UINT8[R_IO_HL])
+#define RSCAN0CFCC12HH (RSCAN0.CFCC12.UINT8[R_IO_HH])
+#define RSCAN0CFCC13 (RSCAN0.CFCC13.UINT32)
+#define RSCAN0CFCC13L (RSCAN0.CFCC13.UINT16[R_IO_L])
+#define RSCAN0CFCC13LL (RSCAN0.CFCC13.UINT8[R_IO_LL])
+#define RSCAN0CFCC13LH (RSCAN0.CFCC13.UINT8[R_IO_LH])
+#define RSCAN0CFCC13H (RSCAN0.CFCC13.UINT16[R_IO_H])
+#define RSCAN0CFCC13HL (RSCAN0.CFCC13.UINT8[R_IO_HL])
+#define RSCAN0CFCC13HH (RSCAN0.CFCC13.UINT8[R_IO_HH])
+#define RSCAN0CFCC14 (RSCAN0.CFCC14.UINT32)
+#define RSCAN0CFCC14L (RSCAN0.CFCC14.UINT16[R_IO_L])
+#define RSCAN0CFCC14LL (RSCAN0.CFCC14.UINT8[R_IO_LL])
+#define RSCAN0CFCC14LH (RSCAN0.CFCC14.UINT8[R_IO_LH])
+#define RSCAN0CFCC14H (RSCAN0.CFCC14.UINT16[R_IO_H])
+#define RSCAN0CFCC14HL (RSCAN0.CFCC14.UINT8[R_IO_HL])
+#define RSCAN0CFCC14HH (RSCAN0.CFCC14.UINT8[R_IO_HH])
+#define RSCAN0CFSTS0 (RSCAN0.CFSTS0.UINT32)
+#define RSCAN0CFSTS0L (RSCAN0.CFSTS0.UINT16[R_IO_L])
+#define RSCAN0CFSTS0LL (RSCAN0.CFSTS0.UINT8[R_IO_LL])
+#define RSCAN0CFSTS0LH (RSCAN0.CFSTS0.UINT8[R_IO_LH])
+#define RSCAN0CFSTS0H (RSCAN0.CFSTS0.UINT16[R_IO_H])
+#define RSCAN0CFSTS0HL (RSCAN0.CFSTS0.UINT8[R_IO_HL])
+#define RSCAN0CFSTS0HH (RSCAN0.CFSTS0.UINT8[R_IO_HH])
+#define RSCAN0CFSTS1 (RSCAN0.CFSTS1.UINT32)
+#define RSCAN0CFSTS1L (RSCAN0.CFSTS1.UINT16[R_IO_L])
+#define RSCAN0CFSTS1LL (RSCAN0.CFSTS1.UINT8[R_IO_LL])
+#define RSCAN0CFSTS1LH (RSCAN0.CFSTS1.UINT8[R_IO_LH])
+#define RSCAN0CFSTS1H (RSCAN0.CFSTS1.UINT16[R_IO_H])
+#define RSCAN0CFSTS1HL (RSCAN0.CFSTS1.UINT8[R_IO_HL])
+#define RSCAN0CFSTS1HH (RSCAN0.CFSTS1.UINT8[R_IO_HH])
+#define RSCAN0CFSTS2 (RSCAN0.CFSTS2.UINT32)
+#define RSCAN0CFSTS2L (RSCAN0.CFSTS2.UINT16[R_IO_L])
+#define RSCAN0CFSTS2LL (RSCAN0.CFSTS2.UINT8[R_IO_LL])
+#define RSCAN0CFSTS2LH (RSCAN0.CFSTS2.UINT8[R_IO_LH])
+#define RSCAN0CFSTS2H (RSCAN0.CFSTS2.UINT16[R_IO_H])
+#define RSCAN0CFSTS2HL (RSCAN0.CFSTS2.UINT8[R_IO_HL])
+#define RSCAN0CFSTS2HH (RSCAN0.CFSTS2.UINT8[R_IO_HH])
+#define RSCAN0CFSTS3 (RSCAN0.CFSTS3.UINT32)
+#define RSCAN0CFSTS3L (RSCAN0.CFSTS3.UINT16[R_IO_L])
+#define RSCAN0CFSTS3LL (RSCAN0.CFSTS3.UINT8[R_IO_LL])
+#define RSCAN0CFSTS3LH (RSCAN0.CFSTS3.UINT8[R_IO_LH])
+#define RSCAN0CFSTS3H (RSCAN0.CFSTS3.UINT16[R_IO_H])
+#define RSCAN0CFSTS3HL (RSCAN0.CFSTS3.UINT8[R_IO_HL])
+#define RSCAN0CFSTS3HH (RSCAN0.CFSTS3.UINT8[R_IO_HH])
+#define RSCAN0CFSTS4 (RSCAN0.CFSTS4.UINT32)
+#define RSCAN0CFSTS4L (RSCAN0.CFSTS4.UINT16[R_IO_L])
+#define RSCAN0CFSTS4LL (RSCAN0.CFSTS4.UINT8[R_IO_LL])
+#define RSCAN0CFSTS4LH (RSCAN0.CFSTS4.UINT8[R_IO_LH])
+#define RSCAN0CFSTS4H (RSCAN0.CFSTS4.UINT16[R_IO_H])
+#define RSCAN0CFSTS4HL (RSCAN0.CFSTS4.UINT8[R_IO_HL])
+#define RSCAN0CFSTS4HH (RSCAN0.CFSTS4.UINT8[R_IO_HH])
+#define RSCAN0CFSTS5 (RSCAN0.CFSTS5.UINT32)
+#define RSCAN0CFSTS5L (RSCAN0.CFSTS5.UINT16[R_IO_L])
+#define RSCAN0CFSTS5LL (RSCAN0.CFSTS5.UINT8[R_IO_LL])
+#define RSCAN0CFSTS5LH (RSCAN0.CFSTS5.UINT8[R_IO_LH])
+#define RSCAN0CFSTS5H (RSCAN0.CFSTS5.UINT16[R_IO_H])
+#define RSCAN0CFSTS5HL (RSCAN0.CFSTS5.UINT8[R_IO_HL])
+#define RSCAN0CFSTS5HH (RSCAN0.CFSTS5.UINT8[R_IO_HH])
+#define RSCAN0CFSTS6 (RSCAN0.CFSTS6.UINT32)
+#define RSCAN0CFSTS6L (RSCAN0.CFSTS6.UINT16[R_IO_L])
+#define RSCAN0CFSTS6LL (RSCAN0.CFSTS6.UINT8[R_IO_LL])
+#define RSCAN0CFSTS6LH (RSCAN0.CFSTS6.UINT8[R_IO_LH])
+#define RSCAN0CFSTS6H (RSCAN0.CFSTS6.UINT16[R_IO_H])
+#define RSCAN0CFSTS6HL (RSCAN0.CFSTS6.UINT8[R_IO_HL])
+#define RSCAN0CFSTS6HH (RSCAN0.CFSTS6.UINT8[R_IO_HH])
+#define RSCAN0CFSTS7 (RSCAN0.CFSTS7.UINT32)
+#define RSCAN0CFSTS7L (RSCAN0.CFSTS7.UINT16[R_IO_L])
+#define RSCAN0CFSTS7LL (RSCAN0.CFSTS7.UINT8[R_IO_LL])
+#define RSCAN0CFSTS7LH (RSCAN0.CFSTS7.UINT8[R_IO_LH])
+#define RSCAN0CFSTS7H (RSCAN0.CFSTS7.UINT16[R_IO_H])
+#define RSCAN0CFSTS7HL (RSCAN0.CFSTS7.UINT8[R_IO_HL])
+#define RSCAN0CFSTS7HH (RSCAN0.CFSTS7.UINT8[R_IO_HH])
+#define RSCAN0CFSTS8 (RSCAN0.CFSTS8.UINT32)
+#define RSCAN0CFSTS8L (RSCAN0.CFSTS8.UINT16[R_IO_L])
+#define RSCAN0CFSTS8LL (RSCAN0.CFSTS8.UINT8[R_IO_LL])
+#define RSCAN0CFSTS8LH (RSCAN0.CFSTS8.UINT8[R_IO_LH])
+#define RSCAN0CFSTS8H (RSCAN0.CFSTS8.UINT16[R_IO_H])
+#define RSCAN0CFSTS8HL (RSCAN0.CFSTS8.UINT8[R_IO_HL])
+#define RSCAN0CFSTS8HH (RSCAN0.CFSTS8.UINT8[R_IO_HH])
+#define RSCAN0CFSTS9 (RSCAN0.CFSTS9.UINT32)
+#define RSCAN0CFSTS9L (RSCAN0.CFSTS9.UINT16[R_IO_L])
+#define RSCAN0CFSTS9LL (RSCAN0.CFSTS9.UINT8[R_IO_LL])
+#define RSCAN0CFSTS9LH (RSCAN0.CFSTS9.UINT8[R_IO_LH])
+#define RSCAN0CFSTS9H (RSCAN0.CFSTS9.UINT16[R_IO_H])
+#define RSCAN0CFSTS9HL (RSCAN0.CFSTS9.UINT8[R_IO_HL])
+#define RSCAN0CFSTS9HH (RSCAN0.CFSTS9.UINT8[R_IO_HH])
+#define RSCAN0CFSTS10 (RSCAN0.CFSTS10.UINT32)
+#define RSCAN0CFSTS10L (RSCAN0.CFSTS10.UINT16[R_IO_L])
+#define RSCAN0CFSTS10LL (RSCAN0.CFSTS10.UINT8[R_IO_LL])
+#define RSCAN0CFSTS10LH (RSCAN0.CFSTS10.UINT8[R_IO_LH])
+#define RSCAN0CFSTS10H (RSCAN0.CFSTS10.UINT16[R_IO_H])
+#define RSCAN0CFSTS10HL (RSCAN0.CFSTS10.UINT8[R_IO_HL])
+#define RSCAN0CFSTS10HH (RSCAN0.CFSTS10.UINT8[R_IO_HH])
+#define RSCAN0CFSTS11 (RSCAN0.CFSTS11.UINT32)
+#define RSCAN0CFSTS11L (RSCAN0.CFSTS11.UINT16[R_IO_L])
+#define RSCAN0CFSTS11LL (RSCAN0.CFSTS11.UINT8[R_IO_LL])
+#define RSCAN0CFSTS11LH (RSCAN0.CFSTS11.UINT8[R_IO_LH])
+#define RSCAN0CFSTS11H (RSCAN0.CFSTS11.UINT16[R_IO_H])
+#define RSCAN0CFSTS11HL (RSCAN0.CFSTS11.UINT8[R_IO_HL])
+#define RSCAN0CFSTS11HH (RSCAN0.CFSTS11.UINT8[R_IO_HH])
+#define RSCAN0CFSTS12 (RSCAN0.CFSTS12.UINT32)
+#define RSCAN0CFSTS12L (RSCAN0.CFSTS12.UINT16[R_IO_L])
+#define RSCAN0CFSTS12LL (RSCAN0.CFSTS12.UINT8[R_IO_LL])
+#define RSCAN0CFSTS12LH (RSCAN0.CFSTS12.UINT8[R_IO_LH])
+#define RSCAN0CFSTS12H (RSCAN0.CFSTS12.UINT16[R_IO_H])
+#define RSCAN0CFSTS12HL (RSCAN0.CFSTS12.UINT8[R_IO_HL])
+#define RSCAN0CFSTS12HH (RSCAN0.CFSTS12.UINT8[R_IO_HH])
+#define RSCAN0CFSTS13 (RSCAN0.CFSTS13.UINT32)
+#define RSCAN0CFSTS13L (RSCAN0.CFSTS13.UINT16[R_IO_L])
+#define RSCAN0CFSTS13LL (RSCAN0.CFSTS13.UINT8[R_IO_LL])
+#define RSCAN0CFSTS13LH (RSCAN0.CFSTS13.UINT8[R_IO_LH])
+#define RSCAN0CFSTS13H (RSCAN0.CFSTS13.UINT16[R_IO_H])
+#define RSCAN0CFSTS13HL (RSCAN0.CFSTS13.UINT8[R_IO_HL])
+#define RSCAN0CFSTS13HH (RSCAN0.CFSTS13.UINT8[R_IO_HH])
+#define RSCAN0CFSTS14 (RSCAN0.CFSTS14.UINT32)
+#define RSCAN0CFSTS14L (RSCAN0.CFSTS14.UINT16[R_IO_L])
+#define RSCAN0CFSTS14LL (RSCAN0.CFSTS14.UINT8[R_IO_LL])
+#define RSCAN0CFSTS14LH (RSCAN0.CFSTS14.UINT8[R_IO_LH])
+#define RSCAN0CFSTS14H (RSCAN0.CFSTS14.UINT16[R_IO_H])
+#define RSCAN0CFSTS14HL (RSCAN0.CFSTS14.UINT8[R_IO_HL])
+#define RSCAN0CFSTS14HH (RSCAN0.CFSTS14.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR0 (RSCAN0.CFPCTR0.UINT32)
+#define RSCAN0CFPCTR0L (RSCAN0.CFPCTR0.UINT16[R_IO_L])
+#define RSCAN0CFPCTR0LL (RSCAN0.CFPCTR0.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR0LH (RSCAN0.CFPCTR0.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR0H (RSCAN0.CFPCTR0.UINT16[R_IO_H])
+#define RSCAN0CFPCTR0HL (RSCAN0.CFPCTR0.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR0HH (RSCAN0.CFPCTR0.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR1 (RSCAN0.CFPCTR1.UINT32)
+#define RSCAN0CFPCTR1L (RSCAN0.CFPCTR1.UINT16[R_IO_L])
+#define RSCAN0CFPCTR1LL (RSCAN0.CFPCTR1.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR1LH (RSCAN0.CFPCTR1.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR1H (RSCAN0.CFPCTR1.UINT16[R_IO_H])
+#define RSCAN0CFPCTR1HL (RSCAN0.CFPCTR1.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR1HH (RSCAN0.CFPCTR1.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR2 (RSCAN0.CFPCTR2.UINT32)
+#define RSCAN0CFPCTR2L (RSCAN0.CFPCTR2.UINT16[R_IO_L])
+#define RSCAN0CFPCTR2LL (RSCAN0.CFPCTR2.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR2LH (RSCAN0.CFPCTR2.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR2H (RSCAN0.CFPCTR2.UINT16[R_IO_H])
+#define RSCAN0CFPCTR2HL (RSCAN0.CFPCTR2.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR2HH (RSCAN0.CFPCTR2.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR3 (RSCAN0.CFPCTR3.UINT32)
+#define RSCAN0CFPCTR3L (RSCAN0.CFPCTR3.UINT16[R_IO_L])
+#define RSCAN0CFPCTR3LL (RSCAN0.CFPCTR3.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR3LH (RSCAN0.CFPCTR3.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR3H (RSCAN0.CFPCTR3.UINT16[R_IO_H])
+#define RSCAN0CFPCTR3HL (RSCAN0.CFPCTR3.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR3HH (RSCAN0.CFPCTR3.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR4 (RSCAN0.CFPCTR4.UINT32)
+#define RSCAN0CFPCTR4L (RSCAN0.CFPCTR4.UINT16[R_IO_L])
+#define RSCAN0CFPCTR4LL (RSCAN0.CFPCTR4.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR4LH (RSCAN0.CFPCTR4.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR4H (RSCAN0.CFPCTR4.UINT16[R_IO_H])
+#define RSCAN0CFPCTR4HL (RSCAN0.CFPCTR4.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR4HH (RSCAN0.CFPCTR4.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR5 (RSCAN0.CFPCTR5.UINT32)
+#define RSCAN0CFPCTR5L (RSCAN0.CFPCTR5.UINT16[R_IO_L])
+#define RSCAN0CFPCTR5LL (RSCAN0.CFPCTR5.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR5LH (RSCAN0.CFPCTR5.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR5H (RSCAN0.CFPCTR5.UINT16[R_IO_H])
+#define RSCAN0CFPCTR5HL (RSCAN0.CFPCTR5.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR5HH (RSCAN0.CFPCTR5.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR6 (RSCAN0.CFPCTR6.UINT32)
+#define RSCAN0CFPCTR6L (RSCAN0.CFPCTR6.UINT16[R_IO_L])
+#define RSCAN0CFPCTR6LL (RSCAN0.CFPCTR6.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR6LH (RSCAN0.CFPCTR6.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR6H (RSCAN0.CFPCTR6.UINT16[R_IO_H])
+#define RSCAN0CFPCTR6HL (RSCAN0.CFPCTR6.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR6HH (RSCAN0.CFPCTR6.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR7 (RSCAN0.CFPCTR7.UINT32)
+#define RSCAN0CFPCTR7L (RSCAN0.CFPCTR7.UINT16[R_IO_L])
+#define RSCAN0CFPCTR7LL (RSCAN0.CFPCTR7.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR7LH (RSCAN0.CFPCTR7.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR7H (RSCAN0.CFPCTR7.UINT16[R_IO_H])
+#define RSCAN0CFPCTR7HL (RSCAN0.CFPCTR7.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR7HH (RSCAN0.CFPCTR7.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR8 (RSCAN0.CFPCTR8.UINT32)
+#define RSCAN0CFPCTR8L (RSCAN0.CFPCTR8.UINT16[R_IO_L])
+#define RSCAN0CFPCTR8LL (RSCAN0.CFPCTR8.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR8LH (RSCAN0.CFPCTR8.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR8H (RSCAN0.CFPCTR8.UINT16[R_IO_H])
+#define RSCAN0CFPCTR8HL (RSCAN0.CFPCTR8.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR8HH (RSCAN0.CFPCTR8.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR9 (RSCAN0.CFPCTR9.UINT32)
+#define RSCAN0CFPCTR9L (RSCAN0.CFPCTR9.UINT16[R_IO_L])
+#define RSCAN0CFPCTR9LL (RSCAN0.CFPCTR9.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR9LH (RSCAN0.CFPCTR9.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR9H (RSCAN0.CFPCTR9.UINT16[R_IO_H])
+#define RSCAN0CFPCTR9HL (RSCAN0.CFPCTR9.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR9HH (RSCAN0.CFPCTR9.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR10 (RSCAN0.CFPCTR10.UINT32)
+#define RSCAN0CFPCTR10L (RSCAN0.CFPCTR10.UINT16[R_IO_L])
+#define RSCAN0CFPCTR10LL (RSCAN0.CFPCTR10.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR10LH (RSCAN0.CFPCTR10.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR10H (RSCAN0.CFPCTR10.UINT16[R_IO_H])
+#define RSCAN0CFPCTR10HL (RSCAN0.CFPCTR10.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR10HH (RSCAN0.CFPCTR10.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR11 (RSCAN0.CFPCTR11.UINT32)
+#define RSCAN0CFPCTR11L (RSCAN0.CFPCTR11.UINT16[R_IO_L])
+#define RSCAN0CFPCTR11LL (RSCAN0.CFPCTR11.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR11LH (RSCAN0.CFPCTR11.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR11H (RSCAN0.CFPCTR11.UINT16[R_IO_H])
+#define RSCAN0CFPCTR11HL (RSCAN0.CFPCTR11.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR11HH (RSCAN0.CFPCTR11.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR12 (RSCAN0.CFPCTR12.UINT32)
+#define RSCAN0CFPCTR12L (RSCAN0.CFPCTR12.UINT16[R_IO_L])
+#define RSCAN0CFPCTR12LL (RSCAN0.CFPCTR12.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR12LH (RSCAN0.CFPCTR12.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR12H (RSCAN0.CFPCTR12.UINT16[R_IO_H])
+#define RSCAN0CFPCTR12HL (RSCAN0.CFPCTR12.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR12HH (RSCAN0.CFPCTR12.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR13 (RSCAN0.CFPCTR13.UINT32)
+#define RSCAN0CFPCTR13L (RSCAN0.CFPCTR13.UINT16[R_IO_L])
+#define RSCAN0CFPCTR13LL (RSCAN0.CFPCTR13.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR13LH (RSCAN0.CFPCTR13.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR13H (RSCAN0.CFPCTR13.UINT16[R_IO_H])
+#define RSCAN0CFPCTR13HL (RSCAN0.CFPCTR13.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR13HH (RSCAN0.CFPCTR13.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR14 (RSCAN0.CFPCTR14.UINT32)
+#define RSCAN0CFPCTR14L (RSCAN0.CFPCTR14.UINT16[R_IO_L])
+#define RSCAN0CFPCTR14LL (RSCAN0.CFPCTR14.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR14LH (RSCAN0.CFPCTR14.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR14H (RSCAN0.CFPCTR14.UINT16[R_IO_H])
+#define RSCAN0CFPCTR14HL (RSCAN0.CFPCTR14.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR14HH (RSCAN0.CFPCTR14.UINT8[R_IO_HH])
+#define RSCAN0FESTS (RSCAN0.FESTS.UINT32)
+#define RSCAN0FESTSL (RSCAN0.FESTS.UINT16[R_IO_L])
+#define RSCAN0FESTSLL (RSCAN0.FESTS.UINT8[R_IO_LL])
+#define RSCAN0FESTSLH (RSCAN0.FESTS.UINT8[R_IO_LH])
+#define RSCAN0FESTSH (RSCAN0.FESTS.UINT16[R_IO_H])
+#define RSCAN0FESTSHL (RSCAN0.FESTS.UINT8[R_IO_HL])
+#define RSCAN0FESTSHH (RSCAN0.FESTS.UINT8[R_IO_HH])
+#define RSCAN0FFSTS (RSCAN0.FFSTS.UINT32)
+#define RSCAN0FFSTSL (RSCAN0.FFSTS.UINT16[R_IO_L])
+#define RSCAN0FFSTSLL (RSCAN0.FFSTS.UINT8[R_IO_LL])
+#define RSCAN0FFSTSLH (RSCAN0.FFSTS.UINT8[R_IO_LH])
+#define RSCAN0FFSTSH (RSCAN0.FFSTS.UINT16[R_IO_H])
+#define RSCAN0FFSTSHL (RSCAN0.FFSTS.UINT8[R_IO_HL])
+#define RSCAN0FFSTSHH (RSCAN0.FFSTS.UINT8[R_IO_HH])
+#define RSCAN0FMSTS (RSCAN0.FMSTS.UINT32)
+#define RSCAN0FMSTSL (RSCAN0.FMSTS.UINT16[R_IO_L])
+#define RSCAN0FMSTSLL (RSCAN0.FMSTS.UINT8[R_IO_LL])
+#define RSCAN0FMSTSLH (RSCAN0.FMSTS.UINT8[R_IO_LH])
+#define RSCAN0FMSTSH (RSCAN0.FMSTS.UINT16[R_IO_H])
+#define RSCAN0FMSTSHL (RSCAN0.FMSTS.UINT8[R_IO_HL])
+#define RSCAN0FMSTSHH (RSCAN0.FMSTS.UINT8[R_IO_HH])
+#define RSCAN0RFISTS (RSCAN0.RFISTS.UINT32)
+#define RSCAN0RFISTSL (RSCAN0.RFISTS.UINT16[R_IO_L])
+#define RSCAN0RFISTSLL (RSCAN0.RFISTS.UINT8[R_IO_LL])
+#define RSCAN0RFISTSLH (RSCAN0.RFISTS.UINT8[R_IO_LH])
+#define RSCAN0RFISTSH (RSCAN0.RFISTS.UINT16[R_IO_H])
+#define RSCAN0RFISTSHL (RSCAN0.RFISTS.UINT8[R_IO_HL])
+#define RSCAN0RFISTSHH (RSCAN0.RFISTS.UINT8[R_IO_HH])
+#define RSCAN0CFRISTS (RSCAN0.CFRISTS.UINT32)
+#define RSCAN0CFRISTSL (RSCAN0.CFRISTS.UINT16[R_IO_L])
+#define RSCAN0CFRISTSLL (RSCAN0.CFRISTS.UINT8[R_IO_LL])
+#define RSCAN0CFRISTSLH (RSCAN0.CFRISTS.UINT8[R_IO_LH])
+#define RSCAN0CFRISTSH (RSCAN0.CFRISTS.UINT16[R_IO_H])
+#define RSCAN0CFRISTSHL (RSCAN0.CFRISTS.UINT8[R_IO_HL])
+#define RSCAN0CFRISTSHH (RSCAN0.CFRISTS.UINT8[R_IO_HH])
+#define RSCAN0CFTISTS (RSCAN0.CFTISTS.UINT32)
+#define RSCAN0CFTISTSL (RSCAN0.CFTISTS.UINT16[R_IO_L])
+#define RSCAN0CFTISTSLL (RSCAN0.CFTISTS.UINT8[R_IO_LL])
+#define RSCAN0CFTISTSLH (RSCAN0.CFTISTS.UINT8[R_IO_LH])
+#define RSCAN0CFTISTSH (RSCAN0.CFTISTS.UINT16[R_IO_H])
+#define RSCAN0CFTISTSHL (RSCAN0.CFTISTS.UINT8[R_IO_HL])
+#define RSCAN0CFTISTSHH (RSCAN0.CFTISTS.UINT8[R_IO_HH])
+#define RSCAN0TMC0 (RSCAN0.TMC0)
+#define RSCAN0TMC1 (RSCAN0.TMC1)
+#define RSCAN0TMC2 (RSCAN0.TMC2)
+#define RSCAN0TMC3 (RSCAN0.TMC3)
+#define RSCAN0TMC4 (RSCAN0.TMC4)
+#define RSCAN0TMC5 (RSCAN0.TMC5)
+#define RSCAN0TMC6 (RSCAN0.TMC6)
+#define RSCAN0TMC7 (RSCAN0.TMC7)
+#define RSCAN0TMC8 (RSCAN0.TMC8)
+#define RSCAN0TMC9 (RSCAN0.TMC9)
+#define RSCAN0TMC10 (RSCAN0.TMC10)
+#define RSCAN0TMC11 (RSCAN0.TMC11)
+#define RSCAN0TMC12 (RSCAN0.TMC12)
+#define RSCAN0TMC13 (RSCAN0.TMC13)
+#define RSCAN0TMC14 (RSCAN0.TMC14)
+#define RSCAN0TMC15 (RSCAN0.TMC15)
+#define RSCAN0TMC16 (RSCAN0.TMC16)
+#define RSCAN0TMC17 (RSCAN0.TMC17)
+#define RSCAN0TMC18 (RSCAN0.TMC18)
+#define RSCAN0TMC19 (RSCAN0.TMC19)
+#define RSCAN0TMC20 (RSCAN0.TMC20)
+#define RSCAN0TMC21 (RSCAN0.TMC21)
+#define RSCAN0TMC22 (RSCAN0.TMC22)
+#define RSCAN0TMC23 (RSCAN0.TMC23)
+#define RSCAN0TMC24 (RSCAN0.TMC24)
+#define RSCAN0TMC25 (RSCAN0.TMC25)
+#define RSCAN0TMC26 (RSCAN0.TMC26)
+#define RSCAN0TMC27 (RSCAN0.TMC27)
+#define RSCAN0TMC28 (RSCAN0.TMC28)
+#define RSCAN0TMC29 (RSCAN0.TMC29)
+#define RSCAN0TMC30 (RSCAN0.TMC30)
+#define RSCAN0TMC31 (RSCAN0.TMC31)
+#define RSCAN0TMC32 (RSCAN0.TMC32)
+#define RSCAN0TMC33 (RSCAN0.TMC33)
+#define RSCAN0TMC34 (RSCAN0.TMC34)
+#define RSCAN0TMC35 (RSCAN0.TMC35)
+#define RSCAN0TMC36 (RSCAN0.TMC36)
+#define RSCAN0TMC37 (RSCAN0.TMC37)
+#define RSCAN0TMC38 (RSCAN0.TMC38)
+#define RSCAN0TMC39 (RSCAN0.TMC39)
+#define RSCAN0TMC40 (RSCAN0.TMC40)
+#define RSCAN0TMC41 (RSCAN0.TMC41)
+#define RSCAN0TMC42 (RSCAN0.TMC42)
+#define RSCAN0TMC43 (RSCAN0.TMC43)
+#define RSCAN0TMC44 (RSCAN0.TMC44)
+#define RSCAN0TMC45 (RSCAN0.TMC45)
+#define RSCAN0TMC46 (RSCAN0.TMC46)
+#define RSCAN0TMC47 (RSCAN0.TMC47)
+#define RSCAN0TMC48 (RSCAN0.TMC48)
+#define RSCAN0TMC49 (RSCAN0.TMC49)
+#define RSCAN0TMC50 (RSCAN0.TMC50)
+#define RSCAN0TMC51 (RSCAN0.TMC51)
+#define RSCAN0TMC52 (RSCAN0.TMC52)
+#define RSCAN0TMC53 (RSCAN0.TMC53)
+#define RSCAN0TMC54 (RSCAN0.TMC54)
+#define RSCAN0TMC55 (RSCAN0.TMC55)
+#define RSCAN0TMC56 (RSCAN0.TMC56)
+#define RSCAN0TMC57 (RSCAN0.TMC57)
+#define RSCAN0TMC58 (RSCAN0.TMC58)
+#define RSCAN0TMC59 (RSCAN0.TMC59)
+#define RSCAN0TMC60 (RSCAN0.TMC60)
+#define RSCAN0TMC61 (RSCAN0.TMC61)
+#define RSCAN0TMC62 (RSCAN0.TMC62)
+#define RSCAN0TMC63 (RSCAN0.TMC63)
+#define RSCAN0TMC64 (RSCAN0.TMC64)
+#define RSCAN0TMC65 (RSCAN0.TMC65)
+#define RSCAN0TMC66 (RSCAN0.TMC66)
+#define RSCAN0TMC67 (RSCAN0.TMC67)
+#define RSCAN0TMC68 (RSCAN0.TMC68)
+#define RSCAN0TMC69 (RSCAN0.TMC69)
+#define RSCAN0TMC70 (RSCAN0.TMC70)
+#define RSCAN0TMC71 (RSCAN0.TMC71)
+#define RSCAN0TMC72 (RSCAN0.TMC72)
+#define RSCAN0TMC73 (RSCAN0.TMC73)
+#define RSCAN0TMC74 (RSCAN0.TMC74)
+#define RSCAN0TMC75 (RSCAN0.TMC75)
+#define RSCAN0TMC76 (RSCAN0.TMC76)
+#define RSCAN0TMC77 (RSCAN0.TMC77)
+#define RSCAN0TMC78 (RSCAN0.TMC78)
+#define RSCAN0TMC79 (RSCAN0.TMC79)
+#define RSCAN0TMSTS0 (RSCAN0.TMSTS0)
+#define RSCAN0TMSTS1 (RSCAN0.TMSTS1)
+#define RSCAN0TMSTS2 (RSCAN0.TMSTS2)
+#define RSCAN0TMSTS3 (RSCAN0.TMSTS3)
+#define RSCAN0TMSTS4 (RSCAN0.TMSTS4)
+#define RSCAN0TMSTS5 (RSCAN0.TMSTS5)
+#define RSCAN0TMSTS6 (RSCAN0.TMSTS6)
+#define RSCAN0TMSTS7 (RSCAN0.TMSTS7)
+#define RSCAN0TMSTS8 (RSCAN0.TMSTS8)
+#define RSCAN0TMSTS9 (RSCAN0.TMSTS9)
+#define RSCAN0TMSTS10 (RSCAN0.TMSTS10)
+#define RSCAN0TMSTS11 (RSCAN0.TMSTS11)
+#define RSCAN0TMSTS12 (RSCAN0.TMSTS12)
+#define RSCAN0TMSTS13 (RSCAN0.TMSTS13)
+#define RSCAN0TMSTS14 (RSCAN0.TMSTS14)
+#define RSCAN0TMSTS15 (RSCAN0.TMSTS15)
+#define RSCAN0TMSTS16 (RSCAN0.TMSTS16)
+#define RSCAN0TMSTS17 (RSCAN0.TMSTS17)
+#define RSCAN0TMSTS18 (RSCAN0.TMSTS18)
+#define RSCAN0TMSTS19 (RSCAN0.TMSTS19)
+#define RSCAN0TMSTS20 (RSCAN0.TMSTS20)
+#define RSCAN0TMSTS21 (RSCAN0.TMSTS21)
+#define RSCAN0TMSTS22 (RSCAN0.TMSTS22)
+#define RSCAN0TMSTS23 (RSCAN0.TMSTS23)
+#define RSCAN0TMSTS24 (RSCAN0.TMSTS24)
+#define RSCAN0TMSTS25 (RSCAN0.TMSTS25)
+#define RSCAN0TMSTS26 (RSCAN0.TMSTS26)
+#define RSCAN0TMSTS27 (RSCAN0.TMSTS27)
+#define RSCAN0TMSTS28 (RSCAN0.TMSTS28)
+#define RSCAN0TMSTS29 (RSCAN0.TMSTS29)
+#define RSCAN0TMSTS30 (RSCAN0.TMSTS30)
+#define RSCAN0TMSTS31 (RSCAN0.TMSTS31)
+#define RSCAN0TMSTS32 (RSCAN0.TMSTS32)
+#define RSCAN0TMSTS33 (RSCAN0.TMSTS33)
+#define RSCAN0TMSTS34 (RSCAN0.TMSTS34)
+#define RSCAN0TMSTS35 (RSCAN0.TMSTS35)
+#define RSCAN0TMSTS36 (RSCAN0.TMSTS36)
+#define RSCAN0TMSTS37 (RSCAN0.TMSTS37)
+#define RSCAN0TMSTS38 (RSCAN0.TMSTS38)
+#define RSCAN0TMSTS39 (RSCAN0.TMSTS39)
+#define RSCAN0TMSTS40 (RSCAN0.TMSTS40)
+#define RSCAN0TMSTS41 (RSCAN0.TMSTS41)
+#define RSCAN0TMSTS42 (RSCAN0.TMSTS42)
+#define RSCAN0TMSTS43 (RSCAN0.TMSTS43)
+#define RSCAN0TMSTS44 (RSCAN0.TMSTS44)
+#define RSCAN0TMSTS45 (RSCAN0.TMSTS45)
+#define RSCAN0TMSTS46 (RSCAN0.TMSTS46)
+#define RSCAN0TMSTS47 (RSCAN0.TMSTS47)
+#define RSCAN0TMSTS48 (RSCAN0.TMSTS48)
+#define RSCAN0TMSTS49 (RSCAN0.TMSTS49)
+#define RSCAN0TMSTS50 (RSCAN0.TMSTS50)
+#define RSCAN0TMSTS51 (RSCAN0.TMSTS51)
+#define RSCAN0TMSTS52 (RSCAN0.TMSTS52)
+#define RSCAN0TMSTS53 (RSCAN0.TMSTS53)
+#define RSCAN0TMSTS54 (RSCAN0.TMSTS54)
+#define RSCAN0TMSTS55 (RSCAN0.TMSTS55)
+#define RSCAN0TMSTS56 (RSCAN0.TMSTS56)
+#define RSCAN0TMSTS57 (RSCAN0.TMSTS57)
+#define RSCAN0TMSTS58 (RSCAN0.TMSTS58)
+#define RSCAN0TMSTS59 (RSCAN0.TMSTS59)
+#define RSCAN0TMSTS60 (RSCAN0.TMSTS60)
+#define RSCAN0TMSTS61 (RSCAN0.TMSTS61)
+#define RSCAN0TMSTS62 (RSCAN0.TMSTS62)
+#define RSCAN0TMSTS63 (RSCAN0.TMSTS63)
+#define RSCAN0TMSTS64 (RSCAN0.TMSTS64)
+#define RSCAN0TMSTS65 (RSCAN0.TMSTS65)
+#define RSCAN0TMSTS66 (RSCAN0.TMSTS66)
+#define RSCAN0TMSTS67 (RSCAN0.TMSTS67)
+#define RSCAN0TMSTS68 (RSCAN0.TMSTS68)
+#define RSCAN0TMSTS69 (RSCAN0.TMSTS69)
+#define RSCAN0TMSTS70 (RSCAN0.TMSTS70)
+#define RSCAN0TMSTS71 (RSCAN0.TMSTS71)
+#define RSCAN0TMSTS72 (RSCAN0.TMSTS72)
+#define RSCAN0TMSTS73 (RSCAN0.TMSTS73)
+#define RSCAN0TMSTS74 (RSCAN0.TMSTS74)
+#define RSCAN0TMSTS75 (RSCAN0.TMSTS75)
+#define RSCAN0TMSTS76 (RSCAN0.TMSTS76)
+#define RSCAN0TMSTS77 (RSCAN0.TMSTS77)
+#define RSCAN0TMSTS78 (RSCAN0.TMSTS78)
+#define RSCAN0TMSTS79 (RSCAN0.TMSTS79)
+#define RSCAN0TMTRSTS0 (RSCAN0.TMTRSTS0.UINT32)
+#define RSCAN0TMTRSTS0L (RSCAN0.TMTRSTS0.UINT16[R_IO_L])
+#define RSCAN0TMTRSTS0LL (RSCAN0.TMTRSTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTRSTS0LH (RSCAN0.TMTRSTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTRSTS0H (RSCAN0.TMTRSTS0.UINT16[R_IO_H])
+#define RSCAN0TMTRSTS0HL (RSCAN0.TMTRSTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTRSTS0HH (RSCAN0.TMTRSTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTRSTS1 (RSCAN0.TMTRSTS1.UINT32)
+#define RSCAN0TMTRSTS1L (RSCAN0.TMTRSTS1.UINT16[R_IO_L])
+#define RSCAN0TMTRSTS1LL (RSCAN0.TMTRSTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTRSTS1LH (RSCAN0.TMTRSTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTRSTS1H (RSCAN0.TMTRSTS1.UINT16[R_IO_H])
+#define RSCAN0TMTRSTS1HL (RSCAN0.TMTRSTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTRSTS1HH (RSCAN0.TMTRSTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTRSTS2 (RSCAN0.TMTRSTS2.UINT32)
+#define RSCAN0TMTRSTS2L (RSCAN0.TMTRSTS2.UINT16[R_IO_L])
+#define RSCAN0TMTRSTS2LL (RSCAN0.TMTRSTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTRSTS2LH (RSCAN0.TMTRSTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTRSTS2H (RSCAN0.TMTRSTS2.UINT16[R_IO_H])
+#define RSCAN0TMTRSTS2HL (RSCAN0.TMTRSTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTRSTS2HH (RSCAN0.TMTRSTS2.UINT8[R_IO_HH])
+#define RSCAN0TMTARSTS0 (RSCAN0.TMTARSTS0.UINT32)
+#define RSCAN0TMTARSTS0L (RSCAN0.TMTARSTS0.UINT16[R_IO_L])
+#define RSCAN0TMTARSTS0LL (RSCAN0.TMTARSTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTARSTS0LH (RSCAN0.TMTARSTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTARSTS0H (RSCAN0.TMTARSTS0.UINT16[R_IO_H])
+#define RSCAN0TMTARSTS0HL (RSCAN0.TMTARSTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTARSTS0HH (RSCAN0.TMTARSTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTARSTS1 (RSCAN0.TMTARSTS1.UINT32)
+#define RSCAN0TMTARSTS1L (RSCAN0.TMTARSTS1.UINT16[R_IO_L])
+#define RSCAN0TMTARSTS1LL (RSCAN0.TMTARSTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTARSTS1LH (RSCAN0.TMTARSTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTARSTS1H (RSCAN0.TMTARSTS1.UINT16[R_IO_H])
+#define RSCAN0TMTARSTS1HL (RSCAN0.TMTARSTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTARSTS1HH (RSCAN0.TMTARSTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTARSTS2 (RSCAN0.TMTARSTS2.UINT32)
+#define RSCAN0TMTARSTS2L (RSCAN0.TMTARSTS2.UINT16[R_IO_L])
+#define RSCAN0TMTARSTS2LL (RSCAN0.TMTARSTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTARSTS2LH (RSCAN0.TMTARSTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTARSTS2H (RSCAN0.TMTARSTS2.UINT16[R_IO_H])
+#define RSCAN0TMTARSTS2HL (RSCAN0.TMTARSTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTARSTS2HH (RSCAN0.TMTARSTS2.UINT8[R_IO_HH])
+#define RSCAN0TMTCSTS0 (RSCAN0.TMTCSTS0.UINT32)
+#define RSCAN0TMTCSTS0L (RSCAN0.TMTCSTS0.UINT16[R_IO_L])
+#define RSCAN0TMTCSTS0LL (RSCAN0.TMTCSTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTCSTS0LH (RSCAN0.TMTCSTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTCSTS0H (RSCAN0.TMTCSTS0.UINT16[R_IO_H])
+#define RSCAN0TMTCSTS0HL (RSCAN0.TMTCSTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTCSTS0HH (RSCAN0.TMTCSTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTCSTS1 (RSCAN0.TMTCSTS1.UINT32)
+#define RSCAN0TMTCSTS1L (RSCAN0.TMTCSTS1.UINT16[R_IO_L])
+#define RSCAN0TMTCSTS1LL (RSCAN0.TMTCSTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTCSTS1LH (RSCAN0.TMTCSTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTCSTS1H (RSCAN0.TMTCSTS1.UINT16[R_IO_H])
+#define RSCAN0TMTCSTS1HL (RSCAN0.TMTCSTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTCSTS1HH (RSCAN0.TMTCSTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTCSTS2 (RSCAN0.TMTCSTS2.UINT32)
+#define RSCAN0TMTCSTS2L (RSCAN0.TMTCSTS2.UINT16[R_IO_L])
+#define RSCAN0TMTCSTS2LL (RSCAN0.TMTCSTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTCSTS2LH (RSCAN0.TMTCSTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTCSTS2H (RSCAN0.TMTCSTS2.UINT16[R_IO_H])
+#define RSCAN0TMTCSTS2HL (RSCAN0.TMTCSTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTCSTS2HH (RSCAN0.TMTCSTS2.UINT8[R_IO_HH])
+#define RSCAN0TMTASTS0 (RSCAN0.TMTASTS0.UINT32)
+#define RSCAN0TMTASTS0L (RSCAN0.TMTASTS0.UINT16[R_IO_L])
+#define RSCAN0TMTASTS0LL (RSCAN0.TMTASTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTASTS0LH (RSCAN0.TMTASTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTASTS0H (RSCAN0.TMTASTS0.UINT16[R_IO_H])
+#define RSCAN0TMTASTS0HL (RSCAN0.TMTASTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTASTS0HH (RSCAN0.TMTASTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTASTS1 (RSCAN0.TMTASTS1.UINT32)
+#define RSCAN0TMTASTS1L (RSCAN0.TMTASTS1.UINT16[R_IO_L])
+#define RSCAN0TMTASTS1LL (RSCAN0.TMTASTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTASTS1LH (RSCAN0.TMTASTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTASTS1H (RSCAN0.TMTASTS1.UINT16[R_IO_H])
+#define RSCAN0TMTASTS1HL (RSCAN0.TMTASTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTASTS1HH (RSCAN0.TMTASTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTASTS2 (RSCAN0.TMTASTS2.UINT32)
+#define RSCAN0TMTASTS2L (RSCAN0.TMTASTS2.UINT16[R_IO_L])
+#define RSCAN0TMTASTS2LL (RSCAN0.TMTASTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTASTS2LH (RSCAN0.TMTASTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTASTS2H (RSCAN0.TMTASTS2.UINT16[R_IO_H])
+#define RSCAN0TMTASTS2HL (RSCAN0.TMTASTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTASTS2HH (RSCAN0.TMTASTS2.UINT8[R_IO_HH])
+#define RSCAN0TMIEC0 (RSCAN0.TMIEC0.UINT32)
+#define RSCAN0TMIEC0L (RSCAN0.TMIEC0.UINT16[R_IO_L])
+#define RSCAN0TMIEC0LL (RSCAN0.TMIEC0.UINT8[R_IO_LL])
+#define RSCAN0TMIEC0LH (RSCAN0.TMIEC0.UINT8[R_IO_LH])
+#define RSCAN0TMIEC0H (RSCAN0.TMIEC0.UINT16[R_IO_H])
+#define RSCAN0TMIEC0HL (RSCAN0.TMIEC0.UINT8[R_IO_HL])
+#define RSCAN0TMIEC0HH (RSCAN0.TMIEC0.UINT8[R_IO_HH])
+#define RSCAN0TMIEC1 (RSCAN0.TMIEC1.UINT32)
+#define RSCAN0TMIEC1L (RSCAN0.TMIEC1.UINT16[R_IO_L])
+#define RSCAN0TMIEC1LL (RSCAN0.TMIEC1.UINT8[R_IO_LL])
+#define RSCAN0TMIEC1LH (RSCAN0.TMIEC1.UINT8[R_IO_LH])
+#define RSCAN0TMIEC1H (RSCAN0.TMIEC1.UINT16[R_IO_H])
+#define RSCAN0TMIEC1HL (RSCAN0.TMIEC1.UINT8[R_IO_HL])
+#define RSCAN0TMIEC1HH (RSCAN0.TMIEC1.UINT8[R_IO_HH])
+#define RSCAN0TMIEC2 (RSCAN0.TMIEC2.UINT32)
+#define RSCAN0TMIEC2L (RSCAN0.TMIEC2.UINT16[R_IO_L])
+#define RSCAN0TMIEC2LL (RSCAN0.TMIEC2.UINT8[R_IO_LL])
+#define RSCAN0TMIEC2LH (RSCAN0.TMIEC2.UINT8[R_IO_LH])
+#define RSCAN0TMIEC2H (RSCAN0.TMIEC2.UINT16[R_IO_H])
+#define RSCAN0TMIEC2HL (RSCAN0.TMIEC2.UINT8[R_IO_HL])
+#define RSCAN0TMIEC2HH (RSCAN0.TMIEC2.UINT8[R_IO_HH])
+#define RSCAN0TXQCC0 (RSCAN0.TXQCC0.UINT32)
+#define RSCAN0TXQCC0L (RSCAN0.TXQCC0.UINT16[R_IO_L])
+#define RSCAN0TXQCC0LL (RSCAN0.TXQCC0.UINT8[R_IO_LL])
+#define RSCAN0TXQCC0LH (RSCAN0.TXQCC0.UINT8[R_IO_LH])
+#define RSCAN0TXQCC0H (RSCAN0.TXQCC0.UINT16[R_IO_H])
+#define RSCAN0TXQCC0HL (RSCAN0.TXQCC0.UINT8[R_IO_HL])
+#define RSCAN0TXQCC0HH (RSCAN0.TXQCC0.UINT8[R_IO_HH])
+#define RSCAN0TXQCC1 (RSCAN0.TXQCC1.UINT32)
+#define RSCAN0TXQCC1L (RSCAN0.TXQCC1.UINT16[R_IO_L])
+#define RSCAN0TXQCC1LL (RSCAN0.TXQCC1.UINT8[R_IO_LL])
+#define RSCAN0TXQCC1LH (RSCAN0.TXQCC1.UINT8[R_IO_LH])
+#define RSCAN0TXQCC1H (RSCAN0.TXQCC1.UINT16[R_IO_H])
+#define RSCAN0TXQCC1HL (RSCAN0.TXQCC1.UINT8[R_IO_HL])
+#define RSCAN0TXQCC1HH (RSCAN0.TXQCC1.UINT8[R_IO_HH])
+#define RSCAN0TXQCC2 (RSCAN0.TXQCC2.UINT32)
+#define RSCAN0TXQCC2L (RSCAN0.TXQCC2.UINT16[R_IO_L])
+#define RSCAN0TXQCC2LL (RSCAN0.TXQCC2.UINT8[R_IO_LL])
+#define RSCAN0TXQCC2LH (RSCAN0.TXQCC2.UINT8[R_IO_LH])
+#define RSCAN0TXQCC2H (RSCAN0.TXQCC2.UINT16[R_IO_H])
+#define RSCAN0TXQCC2HL (RSCAN0.TXQCC2.UINT8[R_IO_HL])
+#define RSCAN0TXQCC2HH (RSCAN0.TXQCC2.UINT8[R_IO_HH])
+#define RSCAN0TXQCC3 (RSCAN0.TXQCC3.UINT32)
+#define RSCAN0TXQCC3L (RSCAN0.TXQCC3.UINT16[R_IO_L])
+#define RSCAN0TXQCC3LL (RSCAN0.TXQCC3.UINT8[R_IO_LL])
+#define RSCAN0TXQCC3LH (RSCAN0.TXQCC3.UINT8[R_IO_LH])
+#define RSCAN0TXQCC3H (RSCAN0.TXQCC3.UINT16[R_IO_H])
+#define RSCAN0TXQCC3HL (RSCAN0.TXQCC3.UINT8[R_IO_HL])
+#define RSCAN0TXQCC3HH (RSCAN0.TXQCC3.UINT8[R_IO_HH])
+#define RSCAN0TXQCC4 (RSCAN0.TXQCC4.UINT32)
+#define RSCAN0TXQCC4L (RSCAN0.TXQCC4.UINT16[R_IO_L])
+#define RSCAN0TXQCC4LL (RSCAN0.TXQCC4.UINT8[R_IO_LL])
+#define RSCAN0TXQCC4LH (RSCAN0.TXQCC4.UINT8[R_IO_LH])
+#define RSCAN0TXQCC4H (RSCAN0.TXQCC4.UINT16[R_IO_H])
+#define RSCAN0TXQCC4HL (RSCAN0.TXQCC4.UINT8[R_IO_HL])
+#define RSCAN0TXQCC4HH (RSCAN0.TXQCC4.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS0 (RSCAN0.TXQSTS0.UINT32)
+#define RSCAN0TXQSTS0L (RSCAN0.TXQSTS0.UINT16[R_IO_L])
+#define RSCAN0TXQSTS0LL (RSCAN0.TXQSTS0.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS0LH (RSCAN0.TXQSTS0.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS0H (RSCAN0.TXQSTS0.UINT16[R_IO_H])
+#define RSCAN0TXQSTS0HL (RSCAN0.TXQSTS0.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS0HH (RSCAN0.TXQSTS0.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS1 (RSCAN0.TXQSTS1.UINT32)
+#define RSCAN0TXQSTS1L (RSCAN0.TXQSTS1.UINT16[R_IO_L])
+#define RSCAN0TXQSTS1LL (RSCAN0.TXQSTS1.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS1LH (RSCAN0.TXQSTS1.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS1H (RSCAN0.TXQSTS1.UINT16[R_IO_H])
+#define RSCAN0TXQSTS1HL (RSCAN0.TXQSTS1.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS1HH (RSCAN0.TXQSTS1.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS2 (RSCAN0.TXQSTS2.UINT32)
+#define RSCAN0TXQSTS2L (RSCAN0.TXQSTS2.UINT16[R_IO_L])
+#define RSCAN0TXQSTS2LL (RSCAN0.TXQSTS2.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS2LH (RSCAN0.TXQSTS2.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS2H (RSCAN0.TXQSTS2.UINT16[R_IO_H])
+#define RSCAN0TXQSTS2HL (RSCAN0.TXQSTS2.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS2HH (RSCAN0.TXQSTS2.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS3 (RSCAN0.TXQSTS3.UINT32)
+#define RSCAN0TXQSTS3L (RSCAN0.TXQSTS3.UINT16[R_IO_L])
+#define RSCAN0TXQSTS3LL (RSCAN0.TXQSTS3.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS3LH (RSCAN0.TXQSTS3.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS3H (RSCAN0.TXQSTS3.UINT16[R_IO_H])
+#define RSCAN0TXQSTS3HL (RSCAN0.TXQSTS3.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS3HH (RSCAN0.TXQSTS3.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS4 (RSCAN0.TXQSTS4.UINT32)
+#define RSCAN0TXQSTS4L (RSCAN0.TXQSTS4.UINT16[R_IO_L])
+#define RSCAN0TXQSTS4LL (RSCAN0.TXQSTS4.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS4LH (RSCAN0.TXQSTS4.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS4H (RSCAN0.TXQSTS4.UINT16[R_IO_H])
+#define RSCAN0TXQSTS4HL (RSCAN0.TXQSTS4.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS4HH (RSCAN0.TXQSTS4.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR0 (RSCAN0.TXQPCTR0.UINT32)
+#define RSCAN0TXQPCTR0L (RSCAN0.TXQPCTR0.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR0LL (RSCAN0.TXQPCTR0.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR0LH (RSCAN0.TXQPCTR0.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR0H (RSCAN0.TXQPCTR0.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR0HL (RSCAN0.TXQPCTR0.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR0HH (RSCAN0.TXQPCTR0.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR1 (RSCAN0.TXQPCTR1.UINT32)
+#define RSCAN0TXQPCTR1L (RSCAN0.TXQPCTR1.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR1LL (RSCAN0.TXQPCTR1.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR1LH (RSCAN0.TXQPCTR1.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR1H (RSCAN0.TXQPCTR1.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR1HL (RSCAN0.TXQPCTR1.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR1HH (RSCAN0.TXQPCTR1.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR2 (RSCAN0.TXQPCTR2.UINT32)
+#define RSCAN0TXQPCTR2L (RSCAN0.TXQPCTR2.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR2LL (RSCAN0.TXQPCTR2.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR2LH (RSCAN0.TXQPCTR2.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR2H (RSCAN0.TXQPCTR2.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR2HL (RSCAN0.TXQPCTR2.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR2HH (RSCAN0.TXQPCTR2.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR3 (RSCAN0.TXQPCTR3.UINT32)
+#define RSCAN0TXQPCTR3L (RSCAN0.TXQPCTR3.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR3LL (RSCAN0.TXQPCTR3.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR3LH (RSCAN0.TXQPCTR3.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR3H (RSCAN0.TXQPCTR3.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR3HL (RSCAN0.TXQPCTR3.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR3HH (RSCAN0.TXQPCTR3.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR4 (RSCAN0.TXQPCTR4.UINT32)
+#define RSCAN0TXQPCTR4L (RSCAN0.TXQPCTR4.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR4LL (RSCAN0.TXQPCTR4.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR4LH (RSCAN0.TXQPCTR4.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR4H (RSCAN0.TXQPCTR4.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR4HL (RSCAN0.TXQPCTR4.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR4HH (RSCAN0.TXQPCTR4.UINT8[R_IO_HH])
+#define RSCAN0THLCC0 (RSCAN0.THLCC0.UINT32)
+#define RSCAN0THLCC0L (RSCAN0.THLCC0.UINT16[R_IO_L])
+#define RSCAN0THLCC0LL (RSCAN0.THLCC0.UINT8[R_IO_LL])
+#define RSCAN0THLCC0LH (RSCAN0.THLCC0.UINT8[R_IO_LH])
+#define RSCAN0THLCC0H (RSCAN0.THLCC0.UINT16[R_IO_H])
+#define RSCAN0THLCC0HL (RSCAN0.THLCC0.UINT8[R_IO_HL])
+#define RSCAN0THLCC0HH (RSCAN0.THLCC0.UINT8[R_IO_HH])
+#define RSCAN0THLCC1 (RSCAN0.THLCC1.UINT32)
+#define RSCAN0THLCC1L (RSCAN0.THLCC1.UINT16[R_IO_L])
+#define RSCAN0THLCC1LL (RSCAN0.THLCC1.UINT8[R_IO_LL])
+#define RSCAN0THLCC1LH (RSCAN0.THLCC1.UINT8[R_IO_LH])
+#define RSCAN0THLCC1H (RSCAN0.THLCC1.UINT16[R_IO_H])
+#define RSCAN0THLCC1HL (RSCAN0.THLCC1.UINT8[R_IO_HL])
+#define RSCAN0THLCC1HH (RSCAN0.THLCC1.UINT8[R_IO_HH])
+#define RSCAN0THLCC2 (RSCAN0.THLCC2.UINT32)
+#define RSCAN0THLCC2L (RSCAN0.THLCC2.UINT16[R_IO_L])
+#define RSCAN0THLCC2LL (RSCAN0.THLCC2.UINT8[R_IO_LL])
+#define RSCAN0THLCC2LH (RSCAN0.THLCC2.UINT8[R_IO_LH])
+#define RSCAN0THLCC2H (RSCAN0.THLCC2.UINT16[R_IO_H])
+#define RSCAN0THLCC2HL (RSCAN0.THLCC2.UINT8[R_IO_HL])
+#define RSCAN0THLCC2HH (RSCAN0.THLCC2.UINT8[R_IO_HH])
+#define RSCAN0THLCC3 (RSCAN0.THLCC3.UINT32)
+#define RSCAN0THLCC3L (RSCAN0.THLCC3.UINT16[R_IO_L])
+#define RSCAN0THLCC3LL (RSCAN0.THLCC3.UINT8[R_IO_LL])
+#define RSCAN0THLCC3LH (RSCAN0.THLCC3.UINT8[R_IO_LH])
+#define RSCAN0THLCC3H (RSCAN0.THLCC3.UINT16[R_IO_H])
+#define RSCAN0THLCC3HL (RSCAN0.THLCC3.UINT8[R_IO_HL])
+#define RSCAN0THLCC3HH (RSCAN0.THLCC3.UINT8[R_IO_HH])
+#define RSCAN0THLCC4 (RSCAN0.THLCC4.UINT32)
+#define RSCAN0THLCC4L (RSCAN0.THLCC4.UINT16[R_IO_L])
+#define RSCAN0THLCC4LL (RSCAN0.THLCC4.UINT8[R_IO_LL])
+#define RSCAN0THLCC4LH (RSCAN0.THLCC4.UINT8[R_IO_LH])
+#define RSCAN0THLCC4H (RSCAN0.THLCC4.UINT16[R_IO_H])
+#define RSCAN0THLCC4HL (RSCAN0.THLCC4.UINT8[R_IO_HL])
+#define RSCAN0THLCC4HH (RSCAN0.THLCC4.UINT8[R_IO_HH])
+#define RSCAN0THLSTS0 (RSCAN0.THLSTS0.UINT32)
+#define RSCAN0THLSTS0L (RSCAN0.THLSTS0.UINT16[R_IO_L])
+#define RSCAN0THLSTS0LL (RSCAN0.THLSTS0.UINT8[R_IO_LL])
+#define RSCAN0THLSTS0LH (RSCAN0.THLSTS0.UINT8[R_IO_LH])
+#define RSCAN0THLSTS0H (RSCAN0.THLSTS0.UINT16[R_IO_H])
+#define RSCAN0THLSTS0HL (RSCAN0.THLSTS0.UINT8[R_IO_HL])
+#define RSCAN0THLSTS0HH (RSCAN0.THLSTS0.UINT8[R_IO_HH])
+#define RSCAN0THLSTS1 (RSCAN0.THLSTS1.UINT32)
+#define RSCAN0THLSTS1L (RSCAN0.THLSTS1.UINT16[R_IO_L])
+#define RSCAN0THLSTS1LL (RSCAN0.THLSTS1.UINT8[R_IO_LL])
+#define RSCAN0THLSTS1LH (RSCAN0.THLSTS1.UINT8[R_IO_LH])
+#define RSCAN0THLSTS1H (RSCAN0.THLSTS1.UINT16[R_IO_H])
+#define RSCAN0THLSTS1HL (RSCAN0.THLSTS1.UINT8[R_IO_HL])
+#define RSCAN0THLSTS1HH (RSCAN0.THLSTS1.UINT8[R_IO_HH])
+#define RSCAN0THLSTS2 (RSCAN0.THLSTS2.UINT32)
+#define RSCAN0THLSTS2L (RSCAN0.THLSTS2.UINT16[R_IO_L])
+#define RSCAN0THLSTS2LL (RSCAN0.THLSTS2.UINT8[R_IO_LL])
+#define RSCAN0THLSTS2LH (RSCAN0.THLSTS2.UINT8[R_IO_LH])
+#define RSCAN0THLSTS2H (RSCAN0.THLSTS2.UINT16[R_IO_H])
+#define RSCAN0THLSTS2HL (RSCAN0.THLSTS2.UINT8[R_IO_HL])
+#define RSCAN0THLSTS2HH (RSCAN0.THLSTS2.UINT8[R_IO_HH])
+#define RSCAN0THLSTS3 (RSCAN0.THLSTS3.UINT32)
+#define RSCAN0THLSTS3L (RSCAN0.THLSTS3.UINT16[R_IO_L])
+#define RSCAN0THLSTS3LL (RSCAN0.THLSTS3.UINT8[R_IO_LL])
+#define RSCAN0THLSTS3LH (RSCAN0.THLSTS3.UINT8[R_IO_LH])
+#define RSCAN0THLSTS3H (RSCAN0.THLSTS3.UINT16[R_IO_H])
+#define RSCAN0THLSTS3HL (RSCAN0.THLSTS3.UINT8[R_IO_HL])
+#define RSCAN0THLSTS3HH (RSCAN0.THLSTS3.UINT8[R_IO_HH])
+#define RSCAN0THLSTS4 (RSCAN0.THLSTS4.UINT32)
+#define RSCAN0THLSTS4L (RSCAN0.THLSTS4.UINT16[R_IO_L])
+#define RSCAN0THLSTS4LL (RSCAN0.THLSTS4.UINT8[R_IO_LL])
+#define RSCAN0THLSTS4LH (RSCAN0.THLSTS4.UINT8[R_IO_LH])
+#define RSCAN0THLSTS4H (RSCAN0.THLSTS4.UINT16[R_IO_H])
+#define RSCAN0THLSTS4HL (RSCAN0.THLSTS4.UINT8[R_IO_HL])
+#define RSCAN0THLSTS4HH (RSCAN0.THLSTS4.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR0 (RSCAN0.THLPCTR0.UINT32)
+#define RSCAN0THLPCTR0L (RSCAN0.THLPCTR0.UINT16[R_IO_L])
+#define RSCAN0THLPCTR0LL (RSCAN0.THLPCTR0.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR0LH (RSCAN0.THLPCTR0.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR0H (RSCAN0.THLPCTR0.UINT16[R_IO_H])
+#define RSCAN0THLPCTR0HL (RSCAN0.THLPCTR0.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR0HH (RSCAN0.THLPCTR0.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR1 (RSCAN0.THLPCTR1.UINT32)
+#define RSCAN0THLPCTR1L (RSCAN0.THLPCTR1.UINT16[R_IO_L])
+#define RSCAN0THLPCTR1LL (RSCAN0.THLPCTR1.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR1LH (RSCAN0.THLPCTR1.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR1H (RSCAN0.THLPCTR1.UINT16[R_IO_H])
+#define RSCAN0THLPCTR1HL (RSCAN0.THLPCTR1.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR1HH (RSCAN0.THLPCTR1.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR2 (RSCAN0.THLPCTR2.UINT32)
+#define RSCAN0THLPCTR2L (RSCAN0.THLPCTR2.UINT16[R_IO_L])
+#define RSCAN0THLPCTR2LL (RSCAN0.THLPCTR2.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR2LH (RSCAN0.THLPCTR2.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR2H (RSCAN0.THLPCTR2.UINT16[R_IO_H])
+#define RSCAN0THLPCTR2HL (RSCAN0.THLPCTR2.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR2HH (RSCAN0.THLPCTR2.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR3 (RSCAN0.THLPCTR3.UINT32)
+#define RSCAN0THLPCTR3L (RSCAN0.THLPCTR3.UINT16[R_IO_L])
+#define RSCAN0THLPCTR3LL (RSCAN0.THLPCTR3.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR3LH (RSCAN0.THLPCTR3.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR3H (RSCAN0.THLPCTR3.UINT16[R_IO_H])
+#define RSCAN0THLPCTR3HL (RSCAN0.THLPCTR3.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR3HH (RSCAN0.THLPCTR3.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR4 (RSCAN0.THLPCTR4.UINT32)
+#define RSCAN0THLPCTR4L (RSCAN0.THLPCTR4.UINT16[R_IO_L])
+#define RSCAN0THLPCTR4LL (RSCAN0.THLPCTR4.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR4LH (RSCAN0.THLPCTR4.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR4H (RSCAN0.THLPCTR4.UINT16[R_IO_H])
+#define RSCAN0THLPCTR4HL (RSCAN0.THLPCTR4.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR4HH (RSCAN0.THLPCTR4.UINT8[R_IO_HH])
+#define RSCAN0GTINTSTS0 (RSCAN0.GTINTSTS0.UINT32)
+#define RSCAN0GTINTSTS0L (RSCAN0.GTINTSTS0.UINT16[R_IO_L])
+#define RSCAN0GTINTSTS0LL (RSCAN0.GTINTSTS0.UINT8[R_IO_LL])
+#define RSCAN0GTINTSTS0LH (RSCAN0.GTINTSTS0.UINT8[R_IO_LH])
+#define RSCAN0GTINTSTS0H (RSCAN0.GTINTSTS0.UINT16[R_IO_H])
+#define RSCAN0GTINTSTS0HL (RSCAN0.GTINTSTS0.UINT8[R_IO_HL])
+#define RSCAN0GTINTSTS0HH (RSCAN0.GTINTSTS0.UINT8[R_IO_HH])
+#define RSCAN0GTINTSTS1 (RSCAN0.GTINTSTS1.UINT32)
+#define RSCAN0GTINTSTS1L (RSCAN0.GTINTSTS1.UINT16[R_IO_L])
+#define RSCAN0GTINTSTS1LL (RSCAN0.GTINTSTS1.UINT8[R_IO_LL])
+#define RSCAN0GTINTSTS1LH (RSCAN0.GTINTSTS1.UINT8[R_IO_LH])
+#define RSCAN0GTINTSTS1H (RSCAN0.GTINTSTS1.UINT16[R_IO_H])
+#define RSCAN0GTINTSTS1HL (RSCAN0.GTINTSTS1.UINT8[R_IO_HL])
+#define RSCAN0GTINTSTS1HH (RSCAN0.GTINTSTS1.UINT8[R_IO_HH])
+#define RSCAN0GTSTCFG (RSCAN0.GTSTCFG.UINT32)
+#define RSCAN0GTSTCFGL (RSCAN0.GTSTCFG.UINT16[R_IO_L])
+#define RSCAN0GTSTCFGLL (RSCAN0.GTSTCFG.UINT8[R_IO_LL])
+#define RSCAN0GTSTCFGLH (RSCAN0.GTSTCFG.UINT8[R_IO_LH])
+#define RSCAN0GTSTCFGH (RSCAN0.GTSTCFG.UINT16[R_IO_H])
+#define RSCAN0GTSTCFGHL (RSCAN0.GTSTCFG.UINT8[R_IO_HL])
+#define RSCAN0GTSTCFGHH (RSCAN0.GTSTCFG.UINT8[R_IO_HH])
+#define RSCAN0GTSTCTR (RSCAN0.GTSTCTR.UINT32)
+#define RSCAN0GTSTCTRL (RSCAN0.GTSTCTR.UINT16[R_IO_L])
+#define RSCAN0GTSTCTRLL (RSCAN0.GTSTCTR.UINT8[R_IO_LL])
+#define RSCAN0GTSTCTRLH (RSCAN0.GTSTCTR.UINT8[R_IO_LH])
+#define RSCAN0GTSTCTRH (RSCAN0.GTSTCTR.UINT16[R_IO_H])
+#define RSCAN0GTSTCTRHL (RSCAN0.GTSTCTR.UINT8[R_IO_HL])
+#define RSCAN0GTSTCTRHH (RSCAN0.GTSTCTR.UINT8[R_IO_HH])
+#define RSCAN0GLOCKK (RSCAN0.GLOCKK.UINT32)
+#define RSCAN0GLOCKKL (RSCAN0.GLOCKK.UINT16[R_IO_L])
+#define RSCAN0GLOCKKH (RSCAN0.GLOCKK.UINT16[R_IO_H])
+#define RSCAN0GAFLID0 (RSCAN0.GAFLID0.UINT32)
+#define RSCAN0GAFLID0L (RSCAN0.GAFLID0.UINT16[R_IO_L])
+#define RSCAN0GAFLID0LL (RSCAN0.GAFLID0.UINT8[R_IO_LL])
+#define RSCAN0GAFLID0LH (RSCAN0.GAFLID0.UINT8[R_IO_LH])
+#define RSCAN0GAFLID0H (RSCAN0.GAFLID0.UINT16[R_IO_H])
+#define RSCAN0GAFLID0HL (RSCAN0.GAFLID0.UINT8[R_IO_HL])
+#define RSCAN0GAFLID0HH (RSCAN0.GAFLID0.UINT8[R_IO_HH])
+#define RSCAN0GAFLM0 (RSCAN0.GAFLM0.UINT32)
+#define RSCAN0GAFLM0L (RSCAN0.GAFLM0.UINT16[R_IO_L])
+#define RSCAN0GAFLM0LL (RSCAN0.GAFLM0.UINT8[R_IO_LL])
+#define RSCAN0GAFLM0LH (RSCAN0.GAFLM0.UINT8[R_IO_LH])
+#define RSCAN0GAFLM0H (RSCAN0.GAFLM0.UINT16[R_IO_H])
+#define RSCAN0GAFLM0HL (RSCAN0.GAFLM0.UINT8[R_IO_HL])
+#define RSCAN0GAFLM0HH (RSCAN0.GAFLM0.UINT8[R_IO_HH])
+#define RSCAN0GAFLP00 (RSCAN0.GAFLP00.UINT32)
+#define RSCAN0GAFLP00L (RSCAN0.GAFLP00.UINT16[R_IO_L])
+#define RSCAN0GAFLP00LL (RSCAN0.GAFLP00.UINT8[R_IO_LL])
+#define RSCAN0GAFLP00LH (RSCAN0.GAFLP00.UINT8[R_IO_LH])
+#define RSCAN0GAFLP00H (RSCAN0.GAFLP00.UINT16[R_IO_H])
+#define RSCAN0GAFLP00HL (RSCAN0.GAFLP00.UINT8[R_IO_HL])
+#define RSCAN0GAFLP00HH (RSCAN0.GAFLP00.UINT8[R_IO_HH])
+#define RSCAN0GAFLP10 (RSCAN0.GAFLP10.UINT32)
+#define RSCAN0GAFLP10L (RSCAN0.GAFLP10.UINT16[R_IO_L])
+#define RSCAN0GAFLP10LL (RSCAN0.GAFLP10.UINT8[R_IO_LL])
+#define RSCAN0GAFLP10LH (RSCAN0.GAFLP10.UINT8[R_IO_LH])
+#define RSCAN0GAFLP10H (RSCAN0.GAFLP10.UINT16[R_IO_H])
+#define RSCAN0GAFLP10HL (RSCAN0.GAFLP10.UINT8[R_IO_HL])
+#define RSCAN0GAFLP10HH (RSCAN0.GAFLP10.UINT8[R_IO_HH])
+#define RSCAN0GAFLID1 (RSCAN0.GAFLID1.UINT32)
+#define RSCAN0GAFLID1L (RSCAN0.GAFLID1.UINT16[R_IO_L])
+#define RSCAN0GAFLID1LL (RSCAN0.GAFLID1.UINT8[R_IO_LL])
+#define RSCAN0GAFLID1LH (RSCAN0.GAFLID1.UINT8[R_IO_LH])
+#define RSCAN0GAFLID1H (RSCAN0.GAFLID1.UINT16[R_IO_H])
+#define RSCAN0GAFLID1HL (RSCAN0.GAFLID1.UINT8[R_IO_HL])
+#define RSCAN0GAFLID1HH (RSCAN0.GAFLID1.UINT8[R_IO_HH])
+#define RSCAN0GAFLM1 (RSCAN0.GAFLM1.UINT32)
+#define RSCAN0GAFLM1L (RSCAN0.GAFLM1.UINT16[R_IO_L])
+#define RSCAN0GAFLM1LL (RSCAN0.GAFLM1.UINT8[R_IO_LL])
+#define RSCAN0GAFLM1LH (RSCAN0.GAFLM1.UINT8[R_IO_LH])
+#define RSCAN0GAFLM1H (RSCAN0.GAFLM1.UINT16[R_IO_H])
+#define RSCAN0GAFLM1HL (RSCAN0.GAFLM1.UINT8[R_IO_HL])
+#define RSCAN0GAFLM1HH (RSCAN0.GAFLM1.UINT8[R_IO_HH])
+#define RSCAN0GAFLP01 (RSCAN0.GAFLP01.UINT32)
+#define RSCAN0GAFLP01L (RSCAN0.GAFLP01.UINT16[R_IO_L])
+#define RSCAN0GAFLP01LL (RSCAN0.GAFLP01.UINT8[R_IO_LL])
+#define RSCAN0GAFLP01LH (RSCAN0.GAFLP01.UINT8[R_IO_LH])
+#define RSCAN0GAFLP01H (RSCAN0.GAFLP01.UINT16[R_IO_H])
+#define RSCAN0GAFLP01HL (RSCAN0.GAFLP01.UINT8[R_IO_HL])
+#define RSCAN0GAFLP01HH (RSCAN0.GAFLP01.UINT8[R_IO_HH])
+#define RSCAN0GAFLP11 (RSCAN0.GAFLP11.UINT32)
+#define RSCAN0GAFLP11L (RSCAN0.GAFLP11.UINT16[R_IO_L])
+#define RSCAN0GAFLP11LL (RSCAN0.GAFLP11.UINT8[R_IO_LL])
+#define RSCAN0GAFLP11LH (RSCAN0.GAFLP11.UINT8[R_IO_LH])
+#define RSCAN0GAFLP11H (RSCAN0.GAFLP11.UINT16[R_IO_H])
+#define RSCAN0GAFLP11HL (RSCAN0.GAFLP11.UINT8[R_IO_HL])
+#define RSCAN0GAFLP11HH (RSCAN0.GAFLP11.UINT8[R_IO_HH])
+#define RSCAN0GAFLID2 (RSCAN0.GAFLID2.UINT32)
+#define RSCAN0GAFLID2L (RSCAN0.GAFLID2.UINT16[R_IO_L])
+#define RSCAN0GAFLID2LL (RSCAN0.GAFLID2.UINT8[R_IO_LL])
+#define RSCAN0GAFLID2LH (RSCAN0.GAFLID2.UINT8[R_IO_LH])
+#define RSCAN0GAFLID2H (RSCAN0.GAFLID2.UINT16[R_IO_H])
+#define RSCAN0GAFLID2HL (RSCAN0.GAFLID2.UINT8[R_IO_HL])
+#define RSCAN0GAFLID2HH (RSCAN0.GAFLID2.UINT8[R_IO_HH])
+#define RSCAN0GAFLM2 (RSCAN0.GAFLM2.UINT32)
+#define RSCAN0GAFLM2L (RSCAN0.GAFLM2.UINT16[R_IO_L])
+#define RSCAN0GAFLM2LL (RSCAN0.GAFLM2.UINT8[R_IO_LL])
+#define RSCAN0GAFLM2LH (RSCAN0.GAFLM2.UINT8[R_IO_LH])
+#define RSCAN0GAFLM2H (RSCAN0.GAFLM2.UINT16[R_IO_H])
+#define RSCAN0GAFLM2HL (RSCAN0.GAFLM2.UINT8[R_IO_HL])
+#define RSCAN0GAFLM2HH (RSCAN0.GAFLM2.UINT8[R_IO_HH])
+#define RSCAN0GAFLP02 (RSCAN0.GAFLP02.UINT32)
+#define RSCAN0GAFLP02L (RSCAN0.GAFLP02.UINT16[R_IO_L])
+#define RSCAN0GAFLP02LL (RSCAN0.GAFLP02.UINT8[R_IO_LL])
+#define RSCAN0GAFLP02LH (RSCAN0.GAFLP02.UINT8[R_IO_LH])
+#define RSCAN0GAFLP02H (RSCAN0.GAFLP02.UINT16[R_IO_H])
+#define RSCAN0GAFLP02HL (RSCAN0.GAFLP02.UINT8[R_IO_HL])
+#define RSCAN0GAFLP02HH (RSCAN0.GAFLP02.UINT8[R_IO_HH])
+#define RSCAN0GAFLP12 (RSCAN0.GAFLP12.UINT32)
+#define RSCAN0GAFLP12L (RSCAN0.GAFLP12.UINT16[R_IO_L])
+#define RSCAN0GAFLP12LL (RSCAN0.GAFLP12.UINT8[R_IO_LL])
+#define RSCAN0GAFLP12LH (RSCAN0.GAFLP12.UINT8[R_IO_LH])
+#define RSCAN0GAFLP12H (RSCAN0.GAFLP12.UINT16[R_IO_H])
+#define RSCAN0GAFLP12HL (RSCAN0.GAFLP12.UINT8[R_IO_HL])
+#define RSCAN0GAFLP12HH (RSCAN0.GAFLP12.UINT8[R_IO_HH])
+#define RSCAN0GAFLID3 (RSCAN0.GAFLID3.UINT32)
+#define RSCAN0GAFLID3L (RSCAN0.GAFLID3.UINT16[R_IO_L])
+#define RSCAN0GAFLID3LL (RSCAN0.GAFLID3.UINT8[R_IO_LL])
+#define RSCAN0GAFLID3LH (RSCAN0.GAFLID3.UINT8[R_IO_LH])
+#define RSCAN0GAFLID3H (RSCAN0.GAFLID3.UINT16[R_IO_H])
+#define RSCAN0GAFLID3HL (RSCAN0.GAFLID3.UINT8[R_IO_HL])
+#define RSCAN0GAFLID3HH (RSCAN0.GAFLID3.UINT8[R_IO_HH])
+#define RSCAN0GAFLM3 (RSCAN0.GAFLM3.UINT32)
+#define RSCAN0GAFLM3L (RSCAN0.GAFLM3.UINT16[R_IO_L])
+#define RSCAN0GAFLM3LL (RSCAN0.GAFLM3.UINT8[R_IO_LL])
+#define RSCAN0GAFLM3LH (RSCAN0.GAFLM3.UINT8[R_IO_LH])
+#define RSCAN0GAFLM3H (RSCAN0.GAFLM3.UINT16[R_IO_H])
+#define RSCAN0GAFLM3HL (RSCAN0.GAFLM3.UINT8[R_IO_HL])
+#define RSCAN0GAFLM3HH (RSCAN0.GAFLM3.UINT8[R_IO_HH])
+#define RSCAN0GAFLP03 (RSCAN0.GAFLP03.UINT32)
+#define RSCAN0GAFLP03L (RSCAN0.GAFLP03.UINT16[R_IO_L])
+#define RSCAN0GAFLP03LL (RSCAN0.GAFLP03.UINT8[R_IO_LL])
+#define RSCAN0GAFLP03LH (RSCAN0.GAFLP03.UINT8[R_IO_LH])
+#define RSCAN0GAFLP03H (RSCAN0.GAFLP03.UINT16[R_IO_H])
+#define RSCAN0GAFLP03HL (RSCAN0.GAFLP03.UINT8[R_IO_HL])
+#define RSCAN0GAFLP03HH (RSCAN0.GAFLP03.UINT8[R_IO_HH])
+#define RSCAN0GAFLP13 (RSCAN0.GAFLP13.UINT32)
+#define RSCAN0GAFLP13L (RSCAN0.GAFLP13.UINT16[R_IO_L])
+#define RSCAN0GAFLP13LL (RSCAN0.GAFLP13.UINT8[R_IO_LL])
+#define RSCAN0GAFLP13LH (RSCAN0.GAFLP13.UINT8[R_IO_LH])
+#define RSCAN0GAFLP13H (RSCAN0.GAFLP13.UINT16[R_IO_H])
+#define RSCAN0GAFLP13HL (RSCAN0.GAFLP13.UINT8[R_IO_HL])
+#define RSCAN0GAFLP13HH (RSCAN0.GAFLP13.UINT8[R_IO_HH])
+#define RSCAN0GAFLID4 (RSCAN0.GAFLID4.UINT32)
+#define RSCAN0GAFLID4L (RSCAN0.GAFLID4.UINT16[R_IO_L])
+#define RSCAN0GAFLID4LL (RSCAN0.GAFLID4.UINT8[R_IO_LL])
+#define RSCAN0GAFLID4LH (RSCAN0.GAFLID4.UINT8[R_IO_LH])
+#define RSCAN0GAFLID4H (RSCAN0.GAFLID4.UINT16[R_IO_H])
+#define RSCAN0GAFLID4HL (RSCAN0.GAFLID4.UINT8[R_IO_HL])
+#define RSCAN0GAFLID4HH (RSCAN0.GAFLID4.UINT8[R_IO_HH])
+#define RSCAN0GAFLM4 (RSCAN0.GAFLM4.UINT32)
+#define RSCAN0GAFLM4L (RSCAN0.GAFLM4.UINT16[R_IO_L])
+#define RSCAN0GAFLM4LL (RSCAN0.GAFLM4.UINT8[R_IO_LL])
+#define RSCAN0GAFLM4LH (RSCAN0.GAFLM4.UINT8[R_IO_LH])
+#define RSCAN0GAFLM4H (RSCAN0.GAFLM4.UINT16[R_IO_H])
+#define RSCAN0GAFLM4HL (RSCAN0.GAFLM4.UINT8[R_IO_HL])
+#define RSCAN0GAFLM4HH (RSCAN0.GAFLM4.UINT8[R_IO_HH])
+#define RSCAN0GAFLP04 (RSCAN0.GAFLP04.UINT32)
+#define RSCAN0GAFLP04L (RSCAN0.GAFLP04.UINT16[R_IO_L])
+#define RSCAN0GAFLP04LL (RSCAN0.GAFLP04.UINT8[R_IO_LL])
+#define RSCAN0GAFLP04LH (RSCAN0.GAFLP04.UINT8[R_IO_LH])
+#define RSCAN0GAFLP04H (RSCAN0.GAFLP04.UINT16[R_IO_H])
+#define RSCAN0GAFLP04HL (RSCAN0.GAFLP04.UINT8[R_IO_HL])
+#define RSCAN0GAFLP04HH (RSCAN0.GAFLP04.UINT8[R_IO_HH])
+#define RSCAN0GAFLP14 (RSCAN0.GAFLP14.UINT32)
+#define RSCAN0GAFLP14L (RSCAN0.GAFLP14.UINT16[R_IO_L])
+#define RSCAN0GAFLP14LL (RSCAN0.GAFLP14.UINT8[R_IO_LL])
+#define RSCAN0GAFLP14LH (RSCAN0.GAFLP14.UINT8[R_IO_LH])
+#define RSCAN0GAFLP14H (RSCAN0.GAFLP14.UINT16[R_IO_H])
+#define RSCAN0GAFLP14HL (RSCAN0.GAFLP14.UINT8[R_IO_HL])
+#define RSCAN0GAFLP14HH (RSCAN0.GAFLP14.UINT8[R_IO_HH])
+#define RSCAN0GAFLID5 (RSCAN0.GAFLID5.UINT32)
+#define RSCAN0GAFLID5L (RSCAN0.GAFLID5.UINT16[R_IO_L])
+#define RSCAN0GAFLID5LL (RSCAN0.GAFLID5.UINT8[R_IO_LL])
+#define RSCAN0GAFLID5LH (RSCAN0.GAFLID5.UINT8[R_IO_LH])
+#define RSCAN0GAFLID5H (RSCAN0.GAFLID5.UINT16[R_IO_H])
+#define RSCAN0GAFLID5HL (RSCAN0.GAFLID5.UINT8[R_IO_HL])
+#define RSCAN0GAFLID5HH (RSCAN0.GAFLID5.UINT8[R_IO_HH])
+#define RSCAN0GAFLM5 (RSCAN0.GAFLM5.UINT32)
+#define RSCAN0GAFLM5L (RSCAN0.GAFLM5.UINT16[R_IO_L])
+#define RSCAN0GAFLM5LL (RSCAN0.GAFLM5.UINT8[R_IO_LL])
+#define RSCAN0GAFLM5LH (RSCAN0.GAFLM5.UINT8[R_IO_LH])
+#define RSCAN0GAFLM5H (RSCAN0.GAFLM5.UINT16[R_IO_H])
+#define RSCAN0GAFLM5HL (RSCAN0.GAFLM5.UINT8[R_IO_HL])
+#define RSCAN0GAFLM5HH (RSCAN0.GAFLM5.UINT8[R_IO_HH])
+#define RSCAN0GAFLP05 (RSCAN0.GAFLP05.UINT32)
+#define RSCAN0GAFLP05L (RSCAN0.GAFLP05.UINT16[R_IO_L])
+#define RSCAN0GAFLP05LL (RSCAN0.GAFLP05.UINT8[R_IO_LL])
+#define RSCAN0GAFLP05LH (RSCAN0.GAFLP05.UINT8[R_IO_LH])
+#define RSCAN0GAFLP05H (RSCAN0.GAFLP05.UINT16[R_IO_H])
+#define RSCAN0GAFLP05HL (RSCAN0.GAFLP05.UINT8[R_IO_HL])
+#define RSCAN0GAFLP05HH (RSCAN0.GAFLP05.UINT8[R_IO_HH])
+#define RSCAN0GAFLP15 (RSCAN0.GAFLP15.UINT32)
+#define RSCAN0GAFLP15L (RSCAN0.GAFLP15.UINT16[R_IO_L])
+#define RSCAN0GAFLP15LL (RSCAN0.GAFLP15.UINT8[R_IO_LL])
+#define RSCAN0GAFLP15LH (RSCAN0.GAFLP15.UINT8[R_IO_LH])
+#define RSCAN0GAFLP15H (RSCAN0.GAFLP15.UINT16[R_IO_H])
+#define RSCAN0GAFLP15HL (RSCAN0.GAFLP15.UINT8[R_IO_HL])
+#define RSCAN0GAFLP15HH (RSCAN0.GAFLP15.UINT8[R_IO_HH])
+#define RSCAN0GAFLID6 (RSCAN0.GAFLID6.UINT32)
+#define RSCAN0GAFLID6L (RSCAN0.GAFLID6.UINT16[R_IO_L])
+#define RSCAN0GAFLID6LL (RSCAN0.GAFLID6.UINT8[R_IO_LL])
+#define RSCAN0GAFLID6LH (RSCAN0.GAFLID6.UINT8[R_IO_LH])
+#define RSCAN0GAFLID6H (RSCAN0.GAFLID6.UINT16[R_IO_H])
+#define RSCAN0GAFLID6HL (RSCAN0.GAFLID6.UINT8[R_IO_HL])
+#define RSCAN0GAFLID6HH (RSCAN0.GAFLID6.UINT8[R_IO_HH])
+#define RSCAN0GAFLM6 (RSCAN0.GAFLM6.UINT32)
+#define RSCAN0GAFLM6L (RSCAN0.GAFLM6.UINT16[R_IO_L])
+#define RSCAN0GAFLM6LL (RSCAN0.GAFLM6.UINT8[R_IO_LL])
+#define RSCAN0GAFLM6LH (RSCAN0.GAFLM6.UINT8[R_IO_LH])
+#define RSCAN0GAFLM6H (RSCAN0.GAFLM6.UINT16[R_IO_H])
+#define RSCAN0GAFLM6HL (RSCAN0.GAFLM6.UINT8[R_IO_HL])
+#define RSCAN0GAFLM6HH (RSCAN0.GAFLM6.UINT8[R_IO_HH])
+#define RSCAN0GAFLP06 (RSCAN0.GAFLP06.UINT32)
+#define RSCAN0GAFLP06L (RSCAN0.GAFLP06.UINT16[R_IO_L])
+#define RSCAN0GAFLP06LL (RSCAN0.GAFLP06.UINT8[R_IO_LL])
+#define RSCAN0GAFLP06LH (RSCAN0.GAFLP06.UINT8[R_IO_LH])
+#define RSCAN0GAFLP06H (RSCAN0.GAFLP06.UINT16[R_IO_H])
+#define RSCAN0GAFLP06HL (RSCAN0.GAFLP06.UINT8[R_IO_HL])
+#define RSCAN0GAFLP06HH (RSCAN0.GAFLP06.UINT8[R_IO_HH])
+#define RSCAN0GAFLP16 (RSCAN0.GAFLP16.UINT32)
+#define RSCAN0GAFLP16L (RSCAN0.GAFLP16.UINT16[R_IO_L])
+#define RSCAN0GAFLP16LL (RSCAN0.GAFLP16.UINT8[R_IO_LL])
+#define RSCAN0GAFLP16LH (RSCAN0.GAFLP16.UINT8[R_IO_LH])
+#define RSCAN0GAFLP16H (RSCAN0.GAFLP16.UINT16[R_IO_H])
+#define RSCAN0GAFLP16HL (RSCAN0.GAFLP16.UINT8[R_IO_HL])
+#define RSCAN0GAFLP16HH (RSCAN0.GAFLP16.UINT8[R_IO_HH])
+#define RSCAN0GAFLID7 (RSCAN0.GAFLID7.UINT32)
+#define RSCAN0GAFLID7L (RSCAN0.GAFLID7.UINT16[R_IO_L])
+#define RSCAN0GAFLID7LL (RSCAN0.GAFLID7.UINT8[R_IO_LL])
+#define RSCAN0GAFLID7LH (RSCAN0.GAFLID7.UINT8[R_IO_LH])
+#define RSCAN0GAFLID7H (RSCAN0.GAFLID7.UINT16[R_IO_H])
+#define RSCAN0GAFLID7HL (RSCAN0.GAFLID7.UINT8[R_IO_HL])
+#define RSCAN0GAFLID7HH (RSCAN0.GAFLID7.UINT8[R_IO_HH])
+#define RSCAN0GAFLM7 (RSCAN0.GAFLM7.UINT32)
+#define RSCAN0GAFLM7L (RSCAN0.GAFLM7.UINT16[R_IO_L])
+#define RSCAN0GAFLM7LL (RSCAN0.GAFLM7.UINT8[R_IO_LL])
+#define RSCAN0GAFLM7LH (RSCAN0.GAFLM7.UINT8[R_IO_LH])
+#define RSCAN0GAFLM7H (RSCAN0.GAFLM7.UINT16[R_IO_H])
+#define RSCAN0GAFLM7HL (RSCAN0.GAFLM7.UINT8[R_IO_HL])
+#define RSCAN0GAFLM7HH (RSCAN0.GAFLM7.UINT8[R_IO_HH])
+#define RSCAN0GAFLP07 (RSCAN0.GAFLP07.UINT32)
+#define RSCAN0GAFLP07L (RSCAN0.GAFLP07.UINT16[R_IO_L])
+#define RSCAN0GAFLP07LL (RSCAN0.GAFLP07.UINT8[R_IO_LL])
+#define RSCAN0GAFLP07LH (RSCAN0.GAFLP07.UINT8[R_IO_LH])
+#define RSCAN0GAFLP07H (RSCAN0.GAFLP07.UINT16[R_IO_H])
+#define RSCAN0GAFLP07HL (RSCAN0.GAFLP07.UINT8[R_IO_HL])
+#define RSCAN0GAFLP07HH (RSCAN0.GAFLP07.UINT8[R_IO_HH])
+#define RSCAN0GAFLP17 (RSCAN0.GAFLP17.UINT32)
+#define RSCAN0GAFLP17L (RSCAN0.GAFLP17.UINT16[R_IO_L])
+#define RSCAN0GAFLP17LL (RSCAN0.GAFLP17.UINT8[R_IO_LL])
+#define RSCAN0GAFLP17LH (RSCAN0.GAFLP17.UINT8[R_IO_LH])
+#define RSCAN0GAFLP17H (RSCAN0.GAFLP17.UINT16[R_IO_H])
+#define RSCAN0GAFLP17HL (RSCAN0.GAFLP17.UINT8[R_IO_HL])
+#define RSCAN0GAFLP17HH (RSCAN0.GAFLP17.UINT8[R_IO_HH])
+#define RSCAN0GAFLID8 (RSCAN0.GAFLID8.UINT32)
+#define RSCAN0GAFLID8L (RSCAN0.GAFLID8.UINT16[R_IO_L])
+#define RSCAN0GAFLID8LL (RSCAN0.GAFLID8.UINT8[R_IO_LL])
+#define RSCAN0GAFLID8LH (RSCAN0.GAFLID8.UINT8[R_IO_LH])
+#define RSCAN0GAFLID8H (RSCAN0.GAFLID8.UINT16[R_IO_H])
+#define RSCAN0GAFLID8HL (RSCAN0.GAFLID8.UINT8[R_IO_HL])
+#define RSCAN0GAFLID8HH (RSCAN0.GAFLID8.UINT8[R_IO_HH])
+#define RSCAN0GAFLM8 (RSCAN0.GAFLM8.UINT32)
+#define RSCAN0GAFLM8L (RSCAN0.GAFLM8.UINT16[R_IO_L])
+#define RSCAN0GAFLM8LL (RSCAN0.GAFLM8.UINT8[R_IO_LL])
+#define RSCAN0GAFLM8LH (RSCAN0.GAFLM8.UINT8[R_IO_LH])
+#define RSCAN0GAFLM8H (RSCAN0.GAFLM8.UINT16[R_IO_H])
+#define RSCAN0GAFLM8HL (RSCAN0.GAFLM8.UINT8[R_IO_HL])
+#define RSCAN0GAFLM8HH (RSCAN0.GAFLM8.UINT8[R_IO_HH])
+#define RSCAN0GAFLP08 (RSCAN0.GAFLP08.UINT32)
+#define RSCAN0GAFLP08L (RSCAN0.GAFLP08.UINT16[R_IO_L])
+#define RSCAN0GAFLP08LL (RSCAN0.GAFLP08.UINT8[R_IO_LL])
+#define RSCAN0GAFLP08LH (RSCAN0.GAFLP08.UINT8[R_IO_LH])
+#define RSCAN0GAFLP08H (RSCAN0.GAFLP08.UINT16[R_IO_H])
+#define RSCAN0GAFLP08HL (RSCAN0.GAFLP08.UINT8[R_IO_HL])
+#define RSCAN0GAFLP08HH (RSCAN0.GAFLP08.UINT8[R_IO_HH])
+#define RSCAN0GAFLP18 (RSCAN0.GAFLP18.UINT32)
+#define RSCAN0GAFLP18L (RSCAN0.GAFLP18.UINT16[R_IO_L])
+#define RSCAN0GAFLP18LL (RSCAN0.GAFLP18.UINT8[R_IO_LL])
+#define RSCAN0GAFLP18LH (RSCAN0.GAFLP18.UINT8[R_IO_LH])
+#define RSCAN0GAFLP18H (RSCAN0.GAFLP18.UINT16[R_IO_H])
+#define RSCAN0GAFLP18HL (RSCAN0.GAFLP18.UINT8[R_IO_HL])
+#define RSCAN0GAFLP18HH (RSCAN0.GAFLP18.UINT8[R_IO_HH])
+#define RSCAN0GAFLID9 (RSCAN0.GAFLID9.UINT32)
+#define RSCAN0GAFLID9L (RSCAN0.GAFLID9.UINT16[R_IO_L])
+#define RSCAN0GAFLID9LL (RSCAN0.GAFLID9.UINT8[R_IO_LL])
+#define RSCAN0GAFLID9LH (RSCAN0.GAFLID9.UINT8[R_IO_LH])
+#define RSCAN0GAFLID9H (RSCAN0.GAFLID9.UINT16[R_IO_H])
+#define RSCAN0GAFLID9HL (RSCAN0.GAFLID9.UINT8[R_IO_HL])
+#define RSCAN0GAFLID9HH (RSCAN0.GAFLID9.UINT8[R_IO_HH])
+#define RSCAN0GAFLM9 (RSCAN0.GAFLM9.UINT32)
+#define RSCAN0GAFLM9L (RSCAN0.GAFLM9.UINT16[R_IO_L])
+#define RSCAN0GAFLM9LL (RSCAN0.GAFLM9.UINT8[R_IO_LL])
+#define RSCAN0GAFLM9LH (RSCAN0.GAFLM9.UINT8[R_IO_LH])
+#define RSCAN0GAFLM9H (RSCAN0.GAFLM9.UINT16[R_IO_H])
+#define RSCAN0GAFLM9HL (RSCAN0.GAFLM9.UINT8[R_IO_HL])
+#define RSCAN0GAFLM9HH (RSCAN0.GAFLM9.UINT8[R_IO_HH])
+#define RSCAN0GAFLP09 (RSCAN0.GAFLP09.UINT32)
+#define RSCAN0GAFLP09L (RSCAN0.GAFLP09.UINT16[R_IO_L])
+#define RSCAN0GAFLP09LL (RSCAN0.GAFLP09.UINT8[R_IO_LL])
+#define RSCAN0GAFLP09LH (RSCAN0.GAFLP09.UINT8[R_IO_LH])
+#define RSCAN0GAFLP09H (RSCAN0.GAFLP09.UINT16[R_IO_H])
+#define RSCAN0GAFLP09HL (RSCAN0.GAFLP09.UINT8[R_IO_HL])
+#define RSCAN0GAFLP09HH (RSCAN0.GAFLP09.UINT8[R_IO_HH])
+#define RSCAN0GAFLP19 (RSCAN0.GAFLP19.UINT32)
+#define RSCAN0GAFLP19L (RSCAN0.GAFLP19.UINT16[R_IO_L])
+#define RSCAN0GAFLP19LL (RSCAN0.GAFLP19.UINT8[R_IO_LL])
+#define RSCAN0GAFLP19LH (RSCAN0.GAFLP19.UINT8[R_IO_LH])
+#define RSCAN0GAFLP19H (RSCAN0.GAFLP19.UINT16[R_IO_H])
+#define RSCAN0GAFLP19HL (RSCAN0.GAFLP19.UINT8[R_IO_HL])
+#define RSCAN0GAFLP19HH (RSCAN0.GAFLP19.UINT8[R_IO_HH])
+#define RSCAN0GAFLID10 (RSCAN0.GAFLID10.UINT32)
+#define RSCAN0GAFLID10L (RSCAN0.GAFLID10.UINT16[R_IO_L])
+#define RSCAN0GAFLID10LL (RSCAN0.GAFLID10.UINT8[R_IO_LL])
+#define RSCAN0GAFLID10LH (RSCAN0.GAFLID10.UINT8[R_IO_LH])
+#define RSCAN0GAFLID10H (RSCAN0.GAFLID10.UINT16[R_IO_H])
+#define RSCAN0GAFLID10HL (RSCAN0.GAFLID10.UINT8[R_IO_HL])
+#define RSCAN0GAFLID10HH (RSCAN0.GAFLID10.UINT8[R_IO_HH])
+#define RSCAN0GAFLM10 (RSCAN0.GAFLM10.UINT32)
+#define RSCAN0GAFLM10L (RSCAN0.GAFLM10.UINT16[R_IO_L])
+#define RSCAN0GAFLM10LL (RSCAN0.GAFLM10.UINT8[R_IO_LL])
+#define RSCAN0GAFLM10LH (RSCAN0.GAFLM10.UINT8[R_IO_LH])
+#define RSCAN0GAFLM10H (RSCAN0.GAFLM10.UINT16[R_IO_H])
+#define RSCAN0GAFLM10HL (RSCAN0.GAFLM10.UINT8[R_IO_HL])
+#define RSCAN0GAFLM10HH (RSCAN0.GAFLM10.UINT8[R_IO_HH])
+#define RSCAN0GAFLP010 (RSCAN0.GAFLP010.UINT32)
+#define RSCAN0GAFLP010L (RSCAN0.GAFLP010.UINT16[R_IO_L])
+#define RSCAN0GAFLP010LL (RSCAN0.GAFLP010.UINT8[R_IO_LL])
+#define RSCAN0GAFLP010LH (RSCAN0.GAFLP010.UINT8[R_IO_LH])
+#define RSCAN0GAFLP010H (RSCAN0.GAFLP010.UINT16[R_IO_H])
+#define RSCAN0GAFLP010HL (RSCAN0.GAFLP010.UINT8[R_IO_HL])
+#define RSCAN0GAFLP010HH (RSCAN0.GAFLP010.UINT8[R_IO_HH])
+#define RSCAN0GAFLP110 (RSCAN0.GAFLP110.UINT32)
+#define RSCAN0GAFLP110L (RSCAN0.GAFLP110.UINT16[R_IO_L])
+#define RSCAN0GAFLP110LL (RSCAN0.GAFLP110.UINT8[R_IO_LL])
+#define RSCAN0GAFLP110LH (RSCAN0.GAFLP110.UINT8[R_IO_LH])
+#define RSCAN0GAFLP110H (RSCAN0.GAFLP110.UINT16[R_IO_H])
+#define RSCAN0GAFLP110HL (RSCAN0.GAFLP110.UINT8[R_IO_HL])
+#define RSCAN0GAFLP110HH (RSCAN0.GAFLP110.UINT8[R_IO_HH])
+#define RSCAN0GAFLID11 (RSCAN0.GAFLID11.UINT32)
+#define RSCAN0GAFLID11L (RSCAN0.GAFLID11.UINT16[R_IO_L])
+#define RSCAN0GAFLID11LL (RSCAN0.GAFLID11.UINT8[R_IO_LL])
+#define RSCAN0GAFLID11LH (RSCAN0.GAFLID11.UINT8[R_IO_LH])
+#define RSCAN0GAFLID11H (RSCAN0.GAFLID11.UINT16[R_IO_H])
+#define RSCAN0GAFLID11HL (RSCAN0.GAFLID11.UINT8[R_IO_HL])
+#define RSCAN0GAFLID11HH (RSCAN0.GAFLID11.UINT8[R_IO_HH])
+#define RSCAN0GAFLM11 (RSCAN0.GAFLM11.UINT32)
+#define RSCAN0GAFLM11L (RSCAN0.GAFLM11.UINT16[R_IO_L])
+#define RSCAN0GAFLM11LL (RSCAN0.GAFLM11.UINT8[R_IO_LL])
+#define RSCAN0GAFLM11LH (RSCAN0.GAFLM11.UINT8[R_IO_LH])
+#define RSCAN0GAFLM11H (RSCAN0.GAFLM11.UINT16[R_IO_H])
+#define RSCAN0GAFLM11HL (RSCAN0.GAFLM11.UINT8[R_IO_HL])
+#define RSCAN0GAFLM11HH (RSCAN0.GAFLM11.UINT8[R_IO_HH])
+#define RSCAN0GAFLP011 (RSCAN0.GAFLP011.UINT32)
+#define RSCAN0GAFLP011L (RSCAN0.GAFLP011.UINT16[R_IO_L])
+#define RSCAN0GAFLP011LL (RSCAN0.GAFLP011.UINT8[R_IO_LL])
+#define RSCAN0GAFLP011LH (RSCAN0.GAFLP011.UINT8[R_IO_LH])
+#define RSCAN0GAFLP011H (RSCAN0.GAFLP011.UINT16[R_IO_H])
+#define RSCAN0GAFLP011HL (RSCAN0.GAFLP011.UINT8[R_IO_HL])
+#define RSCAN0GAFLP011HH (RSCAN0.GAFLP011.UINT8[R_IO_HH])
+#define RSCAN0GAFLP111 (RSCAN0.GAFLP111.UINT32)
+#define RSCAN0GAFLP111L (RSCAN0.GAFLP111.UINT16[R_IO_L])
+#define RSCAN0GAFLP111LL (RSCAN0.GAFLP111.UINT8[R_IO_LL])
+#define RSCAN0GAFLP111LH (RSCAN0.GAFLP111.UINT8[R_IO_LH])
+#define RSCAN0GAFLP111H (RSCAN0.GAFLP111.UINT16[R_IO_H])
+#define RSCAN0GAFLP111HL (RSCAN0.GAFLP111.UINT8[R_IO_HL])
+#define RSCAN0GAFLP111HH (RSCAN0.GAFLP111.UINT8[R_IO_HH])
+#define RSCAN0GAFLID12 (RSCAN0.GAFLID12.UINT32)
+#define RSCAN0GAFLID12L (RSCAN0.GAFLID12.UINT16[R_IO_L])
+#define RSCAN0GAFLID12LL (RSCAN0.GAFLID12.UINT8[R_IO_LL])
+#define RSCAN0GAFLID12LH (RSCAN0.GAFLID12.UINT8[R_IO_LH])
+#define RSCAN0GAFLID12H (RSCAN0.GAFLID12.UINT16[R_IO_H])
+#define RSCAN0GAFLID12HL (RSCAN0.GAFLID12.UINT8[R_IO_HL])
+#define RSCAN0GAFLID12HH (RSCAN0.GAFLID12.UINT8[R_IO_HH])
+#define RSCAN0GAFLM12 (RSCAN0.GAFLM12.UINT32)
+#define RSCAN0GAFLM12L (RSCAN0.GAFLM12.UINT16[R_IO_L])
+#define RSCAN0GAFLM12LL (RSCAN0.GAFLM12.UINT8[R_IO_LL])
+#define RSCAN0GAFLM12LH (RSCAN0.GAFLM12.UINT8[R_IO_LH])
+#define RSCAN0GAFLM12H (RSCAN0.GAFLM12.UINT16[R_IO_H])
+#define RSCAN0GAFLM12HL (RSCAN0.GAFLM12.UINT8[R_IO_HL])
+#define RSCAN0GAFLM12HH (RSCAN0.GAFLM12.UINT8[R_IO_HH])
+#define RSCAN0GAFLP012 (RSCAN0.GAFLP012.UINT32)
+#define RSCAN0GAFLP012L (RSCAN0.GAFLP012.UINT16[R_IO_L])
+#define RSCAN0GAFLP012LL (RSCAN0.GAFLP012.UINT8[R_IO_LL])
+#define RSCAN0GAFLP012LH (RSCAN0.GAFLP012.UINT8[R_IO_LH])
+#define RSCAN0GAFLP012H (RSCAN0.GAFLP012.UINT16[R_IO_H])
+#define RSCAN0GAFLP012HL (RSCAN0.GAFLP012.UINT8[R_IO_HL])
+#define RSCAN0GAFLP012HH (RSCAN0.GAFLP012.UINT8[R_IO_HH])
+#define RSCAN0GAFLP112 (RSCAN0.GAFLP112.UINT32)
+#define RSCAN0GAFLP112L (RSCAN0.GAFLP112.UINT16[R_IO_L])
+#define RSCAN0GAFLP112LL (RSCAN0.GAFLP112.UINT8[R_IO_LL])
+#define RSCAN0GAFLP112LH (RSCAN0.GAFLP112.UINT8[R_IO_LH])
+#define RSCAN0GAFLP112H (RSCAN0.GAFLP112.UINT16[R_IO_H])
+#define RSCAN0GAFLP112HL (RSCAN0.GAFLP112.UINT8[R_IO_HL])
+#define RSCAN0GAFLP112HH (RSCAN0.GAFLP112.UINT8[R_IO_HH])
+#define RSCAN0GAFLID13 (RSCAN0.GAFLID13.UINT32)
+#define RSCAN0GAFLID13L (RSCAN0.GAFLID13.UINT16[R_IO_L])
+#define RSCAN0GAFLID13LL (RSCAN0.GAFLID13.UINT8[R_IO_LL])
+#define RSCAN0GAFLID13LH (RSCAN0.GAFLID13.UINT8[R_IO_LH])
+#define RSCAN0GAFLID13H (RSCAN0.GAFLID13.UINT16[R_IO_H])
+#define RSCAN0GAFLID13HL (RSCAN0.GAFLID13.UINT8[R_IO_HL])
+#define RSCAN0GAFLID13HH (RSCAN0.GAFLID13.UINT8[R_IO_HH])
+#define RSCAN0GAFLM13 (RSCAN0.GAFLM13.UINT32)
+#define RSCAN0GAFLM13L (RSCAN0.GAFLM13.UINT16[R_IO_L])
+#define RSCAN0GAFLM13LL (RSCAN0.GAFLM13.UINT8[R_IO_LL])
+#define RSCAN0GAFLM13LH (RSCAN0.GAFLM13.UINT8[R_IO_LH])
+#define RSCAN0GAFLM13H (RSCAN0.GAFLM13.UINT16[R_IO_H])
+#define RSCAN0GAFLM13HL (RSCAN0.GAFLM13.UINT8[R_IO_HL])
+#define RSCAN0GAFLM13HH (RSCAN0.GAFLM13.UINT8[R_IO_HH])
+#define RSCAN0GAFLP013 (RSCAN0.GAFLP013.UINT32)
+#define RSCAN0GAFLP013L (RSCAN0.GAFLP013.UINT16[R_IO_L])
+#define RSCAN0GAFLP013LL (RSCAN0.GAFLP013.UINT8[R_IO_LL])
+#define RSCAN0GAFLP013LH (RSCAN0.GAFLP013.UINT8[R_IO_LH])
+#define RSCAN0GAFLP013H (RSCAN0.GAFLP013.UINT16[R_IO_H])
+#define RSCAN0GAFLP013HL (RSCAN0.GAFLP013.UINT8[R_IO_HL])
+#define RSCAN0GAFLP013HH (RSCAN0.GAFLP013.UINT8[R_IO_HH])
+#define RSCAN0GAFLP113 (RSCAN0.GAFLP113.UINT32)
+#define RSCAN0GAFLP113L (RSCAN0.GAFLP113.UINT16[R_IO_L])
+#define RSCAN0GAFLP113LL (RSCAN0.GAFLP113.UINT8[R_IO_LL])
+#define RSCAN0GAFLP113LH (RSCAN0.GAFLP113.UINT8[R_IO_LH])
+#define RSCAN0GAFLP113H (RSCAN0.GAFLP113.UINT16[R_IO_H])
+#define RSCAN0GAFLP113HL (RSCAN0.GAFLP113.UINT8[R_IO_HL])
+#define RSCAN0GAFLP113HH (RSCAN0.GAFLP113.UINT8[R_IO_HH])
+#define RSCAN0GAFLID14 (RSCAN0.GAFLID14.UINT32)
+#define RSCAN0GAFLID14L (RSCAN0.GAFLID14.UINT16[R_IO_L])
+#define RSCAN0GAFLID14LL (RSCAN0.GAFLID14.UINT8[R_IO_LL])
+#define RSCAN0GAFLID14LH (RSCAN0.GAFLID14.UINT8[R_IO_LH])
+#define RSCAN0GAFLID14H (RSCAN0.GAFLID14.UINT16[R_IO_H])
+#define RSCAN0GAFLID14HL (RSCAN0.GAFLID14.UINT8[R_IO_HL])
+#define RSCAN0GAFLID14HH (RSCAN0.GAFLID14.UINT8[R_IO_HH])
+#define RSCAN0GAFLM14 (RSCAN0.GAFLM14.UINT32)
+#define RSCAN0GAFLM14L (RSCAN0.GAFLM14.UINT16[R_IO_L])
+#define RSCAN0GAFLM14LL (RSCAN0.GAFLM14.UINT8[R_IO_LL])
+#define RSCAN0GAFLM14LH (RSCAN0.GAFLM14.UINT8[R_IO_LH])
+#define RSCAN0GAFLM14H (RSCAN0.GAFLM14.UINT16[R_IO_H])
+#define RSCAN0GAFLM14HL (RSCAN0.GAFLM14.UINT8[R_IO_HL])
+#define RSCAN0GAFLM14HH (RSCAN0.GAFLM14.UINT8[R_IO_HH])
+#define RSCAN0GAFLP014 (RSCAN0.GAFLP014.UINT32)
+#define RSCAN0GAFLP014L (RSCAN0.GAFLP014.UINT16[R_IO_L])
+#define RSCAN0GAFLP014LL (RSCAN0.GAFLP014.UINT8[R_IO_LL])
+#define RSCAN0GAFLP014LH (RSCAN0.GAFLP014.UINT8[R_IO_LH])
+#define RSCAN0GAFLP014H (RSCAN0.GAFLP014.UINT16[R_IO_H])
+#define RSCAN0GAFLP014HL (RSCAN0.GAFLP014.UINT8[R_IO_HL])
+#define RSCAN0GAFLP014HH (RSCAN0.GAFLP014.UINT8[R_IO_HH])
+#define RSCAN0GAFLP114 (RSCAN0.GAFLP114.UINT32)
+#define RSCAN0GAFLP114L (RSCAN0.GAFLP114.UINT16[R_IO_L])
+#define RSCAN0GAFLP114LL (RSCAN0.GAFLP114.UINT8[R_IO_LL])
+#define RSCAN0GAFLP114LH (RSCAN0.GAFLP114.UINT8[R_IO_LH])
+#define RSCAN0GAFLP114H (RSCAN0.GAFLP114.UINT16[R_IO_H])
+#define RSCAN0GAFLP114HL (RSCAN0.GAFLP114.UINT8[R_IO_HL])
+#define RSCAN0GAFLP114HH (RSCAN0.GAFLP114.UINT8[R_IO_HH])
+#define RSCAN0GAFLID15 (RSCAN0.GAFLID15.UINT32)
+#define RSCAN0GAFLID15L (RSCAN0.GAFLID15.UINT16[R_IO_L])
+#define RSCAN0GAFLID15LL (RSCAN0.GAFLID15.UINT8[R_IO_LL])
+#define RSCAN0GAFLID15LH (RSCAN0.GAFLID15.UINT8[R_IO_LH])
+#define RSCAN0GAFLID15H (RSCAN0.GAFLID15.UINT16[R_IO_H])
+#define RSCAN0GAFLID15HL (RSCAN0.GAFLID15.UINT8[R_IO_HL])
+#define RSCAN0GAFLID15HH (RSCAN0.GAFLID15.UINT8[R_IO_HH])
+#define RSCAN0GAFLM15 (RSCAN0.GAFLM15.UINT32)
+#define RSCAN0GAFLM15L (RSCAN0.GAFLM15.UINT16[R_IO_L])
+#define RSCAN0GAFLM15LL (RSCAN0.GAFLM15.UINT8[R_IO_LL])
+#define RSCAN0GAFLM15LH (RSCAN0.GAFLM15.UINT8[R_IO_LH])
+#define RSCAN0GAFLM15H (RSCAN0.GAFLM15.UINT16[R_IO_H])
+#define RSCAN0GAFLM15HL (RSCAN0.GAFLM15.UINT8[R_IO_HL])
+#define RSCAN0GAFLM15HH (RSCAN0.GAFLM15.UINT8[R_IO_HH])
+#define RSCAN0GAFLP015 (RSCAN0.GAFLP015.UINT32)
+#define RSCAN0GAFLP015L (RSCAN0.GAFLP015.UINT16[R_IO_L])
+#define RSCAN0GAFLP015LL (RSCAN0.GAFLP015.UINT8[R_IO_LL])
+#define RSCAN0GAFLP015LH (RSCAN0.GAFLP015.UINT8[R_IO_LH])
+#define RSCAN0GAFLP015H (RSCAN0.GAFLP015.UINT16[R_IO_H])
+#define RSCAN0GAFLP015HL (RSCAN0.GAFLP015.UINT8[R_IO_HL])
+#define RSCAN0GAFLP015HH (RSCAN0.GAFLP015.UINT8[R_IO_HH])
+#define RSCAN0GAFLP115 (RSCAN0.GAFLP115.UINT32)
+#define RSCAN0GAFLP115L (RSCAN0.GAFLP115.UINT16[R_IO_L])
+#define RSCAN0GAFLP115LL (RSCAN0.GAFLP115.UINT8[R_IO_LL])
+#define RSCAN0GAFLP115LH (RSCAN0.GAFLP115.UINT8[R_IO_LH])
+#define RSCAN0GAFLP115H (RSCAN0.GAFLP115.UINT16[R_IO_H])
+#define RSCAN0GAFLP115HL (RSCAN0.GAFLP115.UINT8[R_IO_HL])
+#define RSCAN0GAFLP115HH (RSCAN0.GAFLP115.UINT8[R_IO_HH])
+#define RSCAN0RMID0 (RSCAN0.RMID0.UINT32)
+#define RSCAN0RMID0L (RSCAN0.RMID0.UINT16[R_IO_L])
+#define RSCAN0RMID0LL (RSCAN0.RMID0.UINT8[R_IO_LL])
+#define RSCAN0RMID0LH (RSCAN0.RMID0.UINT8[R_IO_LH])
+#define RSCAN0RMID0H (RSCAN0.RMID0.UINT16[R_IO_H])
+#define RSCAN0RMID0HL (RSCAN0.RMID0.UINT8[R_IO_HL])
+#define RSCAN0RMID0HH (RSCAN0.RMID0.UINT8[R_IO_HH])
+#define RSCAN0RMPTR0 (RSCAN0.RMPTR0.UINT32)
+#define RSCAN0RMPTR0L (RSCAN0.RMPTR0.UINT16[R_IO_L])
+#define RSCAN0RMPTR0LL (RSCAN0.RMPTR0.UINT8[R_IO_LL])
+#define RSCAN0RMPTR0LH (RSCAN0.RMPTR0.UINT8[R_IO_LH])
+#define RSCAN0RMPTR0H (RSCAN0.RMPTR0.UINT16[R_IO_H])
+#define RSCAN0RMPTR0HL (RSCAN0.RMPTR0.UINT8[R_IO_HL])
+#define RSCAN0RMPTR0HH (RSCAN0.RMPTR0.UINT8[R_IO_HH])
+#define RSCAN0RMDF00 (RSCAN0.RMDF00.UINT32)
+#define RSCAN0RMDF00L (RSCAN0.RMDF00.UINT16[R_IO_L])
+#define RSCAN0RMDF00LL (RSCAN0.RMDF00.UINT8[R_IO_LL])
+#define RSCAN0RMDF00LH (RSCAN0.RMDF00.UINT8[R_IO_LH])
+#define RSCAN0RMDF00H (RSCAN0.RMDF00.UINT16[R_IO_H])
+#define RSCAN0RMDF00HL (RSCAN0.RMDF00.UINT8[R_IO_HL])
+#define RSCAN0RMDF00HH (RSCAN0.RMDF00.UINT8[R_IO_HH])
+#define RSCAN0RMDF10 (RSCAN0.RMDF10.UINT32)
+#define RSCAN0RMDF10L (RSCAN0.RMDF10.UINT16[R_IO_L])
+#define RSCAN0RMDF10LL (RSCAN0.RMDF10.UINT8[R_IO_LL])
+#define RSCAN0RMDF10LH (RSCAN0.RMDF10.UINT8[R_IO_LH])
+#define RSCAN0RMDF10H (RSCAN0.RMDF10.UINT16[R_IO_H])
+#define RSCAN0RMDF10HL (RSCAN0.RMDF10.UINT8[R_IO_HL])
+#define RSCAN0RMDF10HH (RSCAN0.RMDF10.UINT8[R_IO_HH])
+#define RSCAN0RMID1 (RSCAN0.RMID1.UINT32)
+#define RSCAN0RMID1L (RSCAN0.RMID1.UINT16[R_IO_L])
+#define RSCAN0RMID1LL (RSCAN0.RMID1.UINT8[R_IO_LL])
+#define RSCAN0RMID1LH (RSCAN0.RMID1.UINT8[R_IO_LH])
+#define RSCAN0RMID1H (RSCAN0.RMID1.UINT16[R_IO_H])
+#define RSCAN0RMID1HL (RSCAN0.RMID1.UINT8[R_IO_HL])
+#define RSCAN0RMID1HH (RSCAN0.RMID1.UINT8[R_IO_HH])
+#define RSCAN0RMPTR1 (RSCAN0.RMPTR1.UINT32)
+#define RSCAN0RMPTR1L (RSCAN0.RMPTR1.UINT16[R_IO_L])
+#define RSCAN0RMPTR1LL (RSCAN0.RMPTR1.UINT8[R_IO_LL])
+#define RSCAN0RMPTR1LH (RSCAN0.RMPTR1.UINT8[R_IO_LH])
+#define RSCAN0RMPTR1H (RSCAN0.RMPTR1.UINT16[R_IO_H])
+#define RSCAN0RMPTR1HL (RSCAN0.RMPTR1.UINT8[R_IO_HL])
+#define RSCAN0RMPTR1HH (RSCAN0.RMPTR1.UINT8[R_IO_HH])
+#define RSCAN0RMDF01 (RSCAN0.RMDF01.UINT32)
+#define RSCAN0RMDF01L (RSCAN0.RMDF01.UINT16[R_IO_L])
+#define RSCAN0RMDF01LL (RSCAN0.RMDF01.UINT8[R_IO_LL])
+#define RSCAN0RMDF01LH (RSCAN0.RMDF01.UINT8[R_IO_LH])
+#define RSCAN0RMDF01H (RSCAN0.RMDF01.UINT16[R_IO_H])
+#define RSCAN0RMDF01HL (RSCAN0.RMDF01.UINT8[R_IO_HL])
+#define RSCAN0RMDF01HH (RSCAN0.RMDF01.UINT8[R_IO_HH])
+#define RSCAN0RMDF11 (RSCAN0.RMDF11.UINT32)
+#define RSCAN0RMDF11L (RSCAN0.RMDF11.UINT16[R_IO_L])
+#define RSCAN0RMDF11LL (RSCAN0.RMDF11.UINT8[R_IO_LL])
+#define RSCAN0RMDF11LH (RSCAN0.RMDF11.UINT8[R_IO_LH])
+#define RSCAN0RMDF11H (RSCAN0.RMDF11.UINT16[R_IO_H])
+#define RSCAN0RMDF11HL (RSCAN0.RMDF11.UINT8[R_IO_HL])
+#define RSCAN0RMDF11HH (RSCAN0.RMDF11.UINT8[R_IO_HH])
+#define RSCAN0RMID2 (RSCAN0.RMID2.UINT32)
+#define RSCAN0RMID2L (RSCAN0.RMID2.UINT16[R_IO_L])
+#define RSCAN0RMID2LL (RSCAN0.RMID2.UINT8[R_IO_LL])
+#define RSCAN0RMID2LH (RSCAN0.RMID2.UINT8[R_IO_LH])
+#define RSCAN0RMID2H (RSCAN0.RMID2.UINT16[R_IO_H])
+#define RSCAN0RMID2HL (RSCAN0.RMID2.UINT8[R_IO_HL])
+#define RSCAN0RMID2HH (RSCAN0.RMID2.UINT8[R_IO_HH])
+#define RSCAN0RMPTR2 (RSCAN0.RMPTR2.UINT32)
+#define RSCAN0RMPTR2L (RSCAN0.RMPTR2.UINT16[R_IO_L])
+#define RSCAN0RMPTR2LL (RSCAN0.RMPTR2.UINT8[R_IO_LL])
+#define RSCAN0RMPTR2LH (RSCAN0.RMPTR2.UINT8[R_IO_LH])
+#define RSCAN0RMPTR2H (RSCAN0.RMPTR2.UINT16[R_IO_H])
+#define RSCAN0RMPTR2HL (RSCAN0.RMPTR2.UINT8[R_IO_HL])
+#define RSCAN0RMPTR2HH (RSCAN0.RMPTR2.UINT8[R_IO_HH])
+#define RSCAN0RMDF02 (RSCAN0.RMDF02.UINT32)
+#define RSCAN0RMDF02L (RSCAN0.RMDF02.UINT16[R_IO_L])
+#define RSCAN0RMDF02LL (RSCAN0.RMDF02.UINT8[R_IO_LL])
+#define RSCAN0RMDF02LH (RSCAN0.RMDF02.UINT8[R_IO_LH])
+#define RSCAN0RMDF02H (RSCAN0.RMDF02.UINT16[R_IO_H])
+#define RSCAN0RMDF02HL (RSCAN0.RMDF02.UINT8[R_IO_HL])
+#define RSCAN0RMDF02HH (RSCAN0.RMDF02.UINT8[R_IO_HH])
+#define RSCAN0RMDF12 (RSCAN0.RMDF12.UINT32)
+#define RSCAN0RMDF12L (RSCAN0.RMDF12.UINT16[R_IO_L])
+#define RSCAN0RMDF12LL (RSCAN0.RMDF12.UINT8[R_IO_LL])
+#define RSCAN0RMDF12LH (RSCAN0.RMDF12.UINT8[R_IO_LH])
+#define RSCAN0RMDF12H (RSCAN0.RMDF12.UINT16[R_IO_H])
+#define RSCAN0RMDF12HL (RSCAN0.RMDF12.UINT8[R_IO_HL])
+#define RSCAN0RMDF12HH (RSCAN0.RMDF12.UINT8[R_IO_HH])
+#define RSCAN0RMID3 (RSCAN0.RMID3.UINT32)
+#define RSCAN0RMID3L (RSCAN0.RMID3.UINT16[R_IO_L])
+#define RSCAN0RMID3LL (RSCAN0.RMID3.UINT8[R_IO_LL])
+#define RSCAN0RMID3LH (RSCAN0.RMID3.UINT8[R_IO_LH])
+#define RSCAN0RMID3H (RSCAN0.RMID3.UINT16[R_IO_H])
+#define RSCAN0RMID3HL (RSCAN0.RMID3.UINT8[R_IO_HL])
+#define RSCAN0RMID3HH (RSCAN0.RMID3.UINT8[R_IO_HH])
+#define RSCAN0RMPTR3 (RSCAN0.RMPTR3.UINT32)
+#define RSCAN0RMPTR3L (RSCAN0.RMPTR3.UINT16[R_IO_L])
+#define RSCAN0RMPTR3LL (RSCAN0.RMPTR3.UINT8[R_IO_LL])
+#define RSCAN0RMPTR3LH (RSCAN0.RMPTR3.UINT8[R_IO_LH])
+#define RSCAN0RMPTR3H (RSCAN0.RMPTR3.UINT16[R_IO_H])
+#define RSCAN0RMPTR3HL (RSCAN0.RMPTR3.UINT8[R_IO_HL])
+#define RSCAN0RMPTR3HH (RSCAN0.RMPTR3.UINT8[R_IO_HH])
+#define RSCAN0RMDF03 (RSCAN0.RMDF03.UINT32)
+#define RSCAN0RMDF03L (RSCAN0.RMDF03.UINT16[R_IO_L])
+#define RSCAN0RMDF03LL (RSCAN0.RMDF03.UINT8[R_IO_LL])
+#define RSCAN0RMDF03LH (RSCAN0.RMDF03.UINT8[R_IO_LH])
+#define RSCAN0RMDF03H (RSCAN0.RMDF03.UINT16[R_IO_H])
+#define RSCAN0RMDF03HL (RSCAN0.RMDF03.UINT8[R_IO_HL])
+#define RSCAN0RMDF03HH (RSCAN0.RMDF03.UINT8[R_IO_HH])
+#define RSCAN0RMDF13 (RSCAN0.RMDF13.UINT32)
+#define RSCAN0RMDF13L (RSCAN0.RMDF13.UINT16[R_IO_L])
+#define RSCAN0RMDF13LL (RSCAN0.RMDF13.UINT8[R_IO_LL])
+#define RSCAN0RMDF13LH (RSCAN0.RMDF13.UINT8[R_IO_LH])
+#define RSCAN0RMDF13H (RSCAN0.RMDF13.UINT16[R_IO_H])
+#define RSCAN0RMDF13HL (RSCAN0.RMDF13.UINT8[R_IO_HL])
+#define RSCAN0RMDF13HH (RSCAN0.RMDF13.UINT8[R_IO_HH])
+#define RSCAN0RMID4 (RSCAN0.RMID4.UINT32)
+#define RSCAN0RMID4L (RSCAN0.RMID4.UINT16[R_IO_L])
+#define RSCAN0RMID4LL (RSCAN0.RMID4.UINT8[R_IO_LL])
+#define RSCAN0RMID4LH (RSCAN0.RMID4.UINT8[R_IO_LH])
+#define RSCAN0RMID4H (RSCAN0.RMID4.UINT16[R_IO_H])
+#define RSCAN0RMID4HL (RSCAN0.RMID4.UINT8[R_IO_HL])
+#define RSCAN0RMID4HH (RSCAN0.RMID4.UINT8[R_IO_HH])
+#define RSCAN0RMPTR4 (RSCAN0.RMPTR4.UINT32)
+#define RSCAN0RMPTR4L (RSCAN0.RMPTR4.UINT16[R_IO_L])
+#define RSCAN0RMPTR4LL (RSCAN0.RMPTR4.UINT8[R_IO_LL])
+#define RSCAN0RMPTR4LH (RSCAN0.RMPTR4.UINT8[R_IO_LH])
+#define RSCAN0RMPTR4H (RSCAN0.RMPTR4.UINT16[R_IO_H])
+#define RSCAN0RMPTR4HL (RSCAN0.RMPTR4.UINT8[R_IO_HL])
+#define RSCAN0RMPTR4HH (RSCAN0.RMPTR4.UINT8[R_IO_HH])
+#define RSCAN0RMDF04 (RSCAN0.RMDF04.UINT32)
+#define RSCAN0RMDF04L (RSCAN0.RMDF04.UINT16[R_IO_L])
+#define RSCAN0RMDF04LL (RSCAN0.RMDF04.UINT8[R_IO_LL])
+#define RSCAN0RMDF04LH (RSCAN0.RMDF04.UINT8[R_IO_LH])
+#define RSCAN0RMDF04H (RSCAN0.RMDF04.UINT16[R_IO_H])
+#define RSCAN0RMDF04HL (RSCAN0.RMDF04.UINT8[R_IO_HL])
+#define RSCAN0RMDF04HH (RSCAN0.RMDF04.UINT8[R_IO_HH])
+#define RSCAN0RMDF14 (RSCAN0.RMDF14.UINT32)
+#define RSCAN0RMDF14L (RSCAN0.RMDF14.UINT16[R_IO_L])
+#define RSCAN0RMDF14LL (RSCAN0.RMDF14.UINT8[R_IO_LL])
+#define RSCAN0RMDF14LH (RSCAN0.RMDF14.UINT8[R_IO_LH])
+#define RSCAN0RMDF14H (RSCAN0.RMDF14.UINT16[R_IO_H])
+#define RSCAN0RMDF14HL (RSCAN0.RMDF14.UINT8[R_IO_HL])
+#define RSCAN0RMDF14HH (RSCAN0.RMDF14.UINT8[R_IO_HH])
+#define RSCAN0RMID5 (RSCAN0.RMID5.UINT32)
+#define RSCAN0RMID5L (RSCAN0.RMID5.UINT16[R_IO_L])
+#define RSCAN0RMID5LL (RSCAN0.RMID5.UINT8[R_IO_LL])
+#define RSCAN0RMID5LH (RSCAN0.RMID5.UINT8[R_IO_LH])
+#define RSCAN0RMID5H (RSCAN0.RMID5.UINT16[R_IO_H])
+#define RSCAN0RMID5HL (RSCAN0.RMID5.UINT8[R_IO_HL])
+#define RSCAN0RMID5HH (RSCAN0.RMID5.UINT8[R_IO_HH])
+#define RSCAN0RMPTR5 (RSCAN0.RMPTR5.UINT32)
+#define RSCAN0RMPTR5L (RSCAN0.RMPTR5.UINT16[R_IO_L])
+#define RSCAN0RMPTR5LL (RSCAN0.RMPTR5.UINT8[R_IO_LL])
+#define RSCAN0RMPTR5LH (RSCAN0.RMPTR5.UINT8[R_IO_LH])
+#define RSCAN0RMPTR5H (RSCAN0.RMPTR5.UINT16[R_IO_H])
+#define RSCAN0RMPTR5HL (RSCAN0.RMPTR5.UINT8[R_IO_HL])
+#define RSCAN0RMPTR5HH (RSCAN0.RMPTR5.UINT8[R_IO_HH])
+#define RSCAN0RMDF05 (RSCAN0.RMDF05.UINT32)
+#define RSCAN0RMDF05L (RSCAN0.RMDF05.UINT16[R_IO_L])
+#define RSCAN0RMDF05LL (RSCAN0.RMDF05.UINT8[R_IO_LL])
+#define RSCAN0RMDF05LH (RSCAN0.RMDF05.UINT8[R_IO_LH])
+#define RSCAN0RMDF05H (RSCAN0.RMDF05.UINT16[R_IO_H])
+#define RSCAN0RMDF05HL (RSCAN0.RMDF05.UINT8[R_IO_HL])
+#define RSCAN0RMDF05HH (RSCAN0.RMDF05.UINT8[R_IO_HH])
+#define RSCAN0RMDF15 (RSCAN0.RMDF15.UINT32)
+#define RSCAN0RMDF15L (RSCAN0.RMDF15.UINT16[R_IO_L])
+#define RSCAN0RMDF15LL (RSCAN0.RMDF15.UINT8[R_IO_LL])
+#define RSCAN0RMDF15LH (RSCAN0.RMDF15.UINT8[R_IO_LH])
+#define RSCAN0RMDF15H (RSCAN0.RMDF15.UINT16[R_IO_H])
+#define RSCAN0RMDF15HL (RSCAN0.RMDF15.UINT8[R_IO_HL])
+#define RSCAN0RMDF15HH (RSCAN0.RMDF15.UINT8[R_IO_HH])
+#define RSCAN0RMID6 (RSCAN0.RMID6.UINT32)
+#define RSCAN0RMID6L (RSCAN0.RMID6.UINT16[R_IO_L])
+#define RSCAN0RMID6LL (RSCAN0.RMID6.UINT8[R_IO_LL])
+#define RSCAN0RMID6LH (RSCAN0.RMID6.UINT8[R_IO_LH])
+#define RSCAN0RMID6H (RSCAN0.RMID6.UINT16[R_IO_H])
+#define RSCAN0RMID6HL (RSCAN0.RMID6.UINT8[R_IO_HL])
+#define RSCAN0RMID6HH (RSCAN0.RMID6.UINT8[R_IO_HH])
+#define RSCAN0RMPTR6 (RSCAN0.RMPTR6.UINT32)
+#define RSCAN0RMPTR6L (RSCAN0.RMPTR6.UINT16[R_IO_L])
+#define RSCAN0RMPTR6LL (RSCAN0.RMPTR6.UINT8[R_IO_LL])
+#define RSCAN0RMPTR6LH (RSCAN0.RMPTR6.UINT8[R_IO_LH])
+#define RSCAN0RMPTR6H (RSCAN0.RMPTR6.UINT16[R_IO_H])
+#define RSCAN0RMPTR6HL (RSCAN0.RMPTR6.UINT8[R_IO_HL])
+#define RSCAN0RMPTR6HH (RSCAN0.RMPTR6.UINT8[R_IO_HH])
+#define RSCAN0RMDF06 (RSCAN0.RMDF06.UINT32)
+#define RSCAN0RMDF06L (RSCAN0.RMDF06.UINT16[R_IO_L])
+#define RSCAN0RMDF06LL (RSCAN0.RMDF06.UINT8[R_IO_LL])
+#define RSCAN0RMDF06LH (RSCAN0.RMDF06.UINT8[R_IO_LH])
+#define RSCAN0RMDF06H (RSCAN0.RMDF06.UINT16[R_IO_H])
+#define RSCAN0RMDF06HL (RSCAN0.RMDF06.UINT8[R_IO_HL])
+#define RSCAN0RMDF06HH (RSCAN0.RMDF06.UINT8[R_IO_HH])
+#define RSCAN0RMDF16 (RSCAN0.RMDF16.UINT32)
+#define RSCAN0RMDF16L (RSCAN0.RMDF16.UINT16[R_IO_L])
+#define RSCAN0RMDF16LL (RSCAN0.RMDF16.UINT8[R_IO_LL])
+#define RSCAN0RMDF16LH (RSCAN0.RMDF16.UINT8[R_IO_LH])
+#define RSCAN0RMDF16H (RSCAN0.RMDF16.UINT16[R_IO_H])
+#define RSCAN0RMDF16HL (RSCAN0.RMDF16.UINT8[R_IO_HL])
+#define RSCAN0RMDF16HH (RSCAN0.RMDF16.UINT8[R_IO_HH])
+#define RSCAN0RMID7 (RSCAN0.RMID7.UINT32)
+#define RSCAN0RMID7L (RSCAN0.RMID7.UINT16[R_IO_L])
+#define RSCAN0RMID7LL (RSCAN0.RMID7.UINT8[R_IO_LL])
+#define RSCAN0RMID7LH (RSCAN0.RMID7.UINT8[R_IO_LH])
+#define RSCAN0RMID7H (RSCAN0.RMID7.UINT16[R_IO_H])
+#define RSCAN0RMID7HL (RSCAN0.RMID7.UINT8[R_IO_HL])
+#define RSCAN0RMID7HH (RSCAN0.RMID7.UINT8[R_IO_HH])
+#define RSCAN0RMPTR7 (RSCAN0.RMPTR7.UINT32)
+#define RSCAN0RMPTR7L (RSCAN0.RMPTR7.UINT16[R_IO_L])
+#define RSCAN0RMPTR7LL (RSCAN0.RMPTR7.UINT8[R_IO_LL])
+#define RSCAN0RMPTR7LH (RSCAN0.RMPTR7.UINT8[R_IO_LH])
+#define RSCAN0RMPTR7H (RSCAN0.RMPTR7.UINT16[R_IO_H])
+#define RSCAN0RMPTR7HL (RSCAN0.RMPTR7.UINT8[R_IO_HL])
+#define RSCAN0RMPTR7HH (RSCAN0.RMPTR7.UINT8[R_IO_HH])
+#define RSCAN0RMDF07 (RSCAN0.RMDF07.UINT32)
+#define RSCAN0RMDF07L (RSCAN0.RMDF07.UINT16[R_IO_L])
+#define RSCAN0RMDF07LL (RSCAN0.RMDF07.UINT8[R_IO_LL])
+#define RSCAN0RMDF07LH (RSCAN0.RMDF07.UINT8[R_IO_LH])
+#define RSCAN0RMDF07H (RSCAN0.RMDF07.UINT16[R_IO_H])
+#define RSCAN0RMDF07HL (RSCAN0.RMDF07.UINT8[R_IO_HL])
+#define RSCAN0RMDF07HH (RSCAN0.RMDF07.UINT8[R_IO_HH])
+#define RSCAN0RMDF17 (RSCAN0.RMDF17.UINT32)
+#define RSCAN0RMDF17L (RSCAN0.RMDF17.UINT16[R_IO_L])
+#define RSCAN0RMDF17LL (RSCAN0.RMDF17.UINT8[R_IO_LL])
+#define RSCAN0RMDF17LH (RSCAN0.RMDF17.UINT8[R_IO_LH])
+#define RSCAN0RMDF17H (RSCAN0.RMDF17.UINT16[R_IO_H])
+#define RSCAN0RMDF17HL (RSCAN0.RMDF17.UINT8[R_IO_HL])
+#define RSCAN0RMDF17HH (RSCAN0.RMDF17.UINT8[R_IO_HH])
+#define RSCAN0RMID8 (RSCAN0.RMID8.UINT32)
+#define RSCAN0RMID8L (RSCAN0.RMID8.UINT16[R_IO_L])
+#define RSCAN0RMID8LL (RSCAN0.RMID8.UINT8[R_IO_LL])
+#define RSCAN0RMID8LH (RSCAN0.RMID8.UINT8[R_IO_LH])
+#define RSCAN0RMID8H (RSCAN0.RMID8.UINT16[R_IO_H])
+#define RSCAN0RMID8HL (RSCAN0.RMID8.UINT8[R_IO_HL])
+#define RSCAN0RMID8HH (RSCAN0.RMID8.UINT8[R_IO_HH])
+#define RSCAN0RMPTR8 (RSCAN0.RMPTR8.UINT32)
+#define RSCAN0RMPTR8L (RSCAN0.RMPTR8.UINT16[R_IO_L])
+#define RSCAN0RMPTR8LL (RSCAN0.RMPTR8.UINT8[R_IO_LL])
+#define RSCAN0RMPTR8LH (RSCAN0.RMPTR8.UINT8[R_IO_LH])
+#define RSCAN0RMPTR8H (RSCAN0.RMPTR8.UINT16[R_IO_H])
+#define RSCAN0RMPTR8HL (RSCAN0.RMPTR8.UINT8[R_IO_HL])
+#define RSCAN0RMPTR8HH (RSCAN0.RMPTR8.UINT8[R_IO_HH])
+#define RSCAN0RMDF08 (RSCAN0.RMDF08.UINT32)
+#define RSCAN0RMDF08L (RSCAN0.RMDF08.UINT16[R_IO_L])
+#define RSCAN0RMDF08LL (RSCAN0.RMDF08.UINT8[R_IO_LL])
+#define RSCAN0RMDF08LH (RSCAN0.RMDF08.UINT8[R_IO_LH])
+#define RSCAN0RMDF08H (RSCAN0.RMDF08.UINT16[R_IO_H])
+#define RSCAN0RMDF08HL (RSCAN0.RMDF08.UINT8[R_IO_HL])
+#define RSCAN0RMDF08HH (RSCAN0.RMDF08.UINT8[R_IO_HH])
+#define RSCAN0RMDF18 (RSCAN0.RMDF18.UINT32)
+#define RSCAN0RMDF18L (RSCAN0.RMDF18.UINT16[R_IO_L])
+#define RSCAN0RMDF18LL (RSCAN0.RMDF18.UINT8[R_IO_LL])
+#define RSCAN0RMDF18LH (RSCAN0.RMDF18.UINT8[R_IO_LH])
+#define RSCAN0RMDF18H (RSCAN0.RMDF18.UINT16[R_IO_H])
+#define RSCAN0RMDF18HL (RSCAN0.RMDF18.UINT8[R_IO_HL])
+#define RSCAN0RMDF18HH (RSCAN0.RMDF18.UINT8[R_IO_HH])
+#define RSCAN0RMID9 (RSCAN0.RMID9.UINT32)
+#define RSCAN0RMID9L (RSCAN0.RMID9.UINT16[R_IO_L])
+#define RSCAN0RMID9LL (RSCAN0.RMID9.UINT8[R_IO_LL])
+#define RSCAN0RMID9LH (RSCAN0.RMID9.UINT8[R_IO_LH])
+#define RSCAN0RMID9H (RSCAN0.RMID9.UINT16[R_IO_H])
+#define RSCAN0RMID9HL (RSCAN0.RMID9.UINT8[R_IO_HL])
+#define RSCAN0RMID9HH (RSCAN0.RMID9.UINT8[R_IO_HH])
+#define RSCAN0RMPTR9 (RSCAN0.RMPTR9.UINT32)
+#define RSCAN0RMPTR9L (RSCAN0.RMPTR9.UINT16[R_IO_L])
+#define RSCAN0RMPTR9LL (RSCAN0.RMPTR9.UINT8[R_IO_LL])
+#define RSCAN0RMPTR9LH (RSCAN0.RMPTR9.UINT8[R_IO_LH])
+#define RSCAN0RMPTR9H (RSCAN0.RMPTR9.UINT16[R_IO_H])
+#define RSCAN0RMPTR9HL (RSCAN0.RMPTR9.UINT8[R_IO_HL])
+#define RSCAN0RMPTR9HH (RSCAN0.RMPTR9.UINT8[R_IO_HH])
+#define RSCAN0RMDF09 (RSCAN0.RMDF09.UINT32)
+#define RSCAN0RMDF09L (RSCAN0.RMDF09.UINT16[R_IO_L])
+#define RSCAN0RMDF09LL (RSCAN0.RMDF09.UINT8[R_IO_LL])
+#define RSCAN0RMDF09LH (RSCAN0.RMDF09.UINT8[R_IO_LH])
+#define RSCAN0RMDF09H (RSCAN0.RMDF09.UINT16[R_IO_H])
+#define RSCAN0RMDF09HL (RSCAN0.RMDF09.UINT8[R_IO_HL])
+#define RSCAN0RMDF09HH (RSCAN0.RMDF09.UINT8[R_IO_HH])
+#define RSCAN0RMDF19 (RSCAN0.RMDF19.UINT32)
+#define RSCAN0RMDF19L (RSCAN0.RMDF19.UINT16[R_IO_L])
+#define RSCAN0RMDF19LL (RSCAN0.RMDF19.UINT8[R_IO_LL])
+#define RSCAN0RMDF19LH (RSCAN0.RMDF19.UINT8[R_IO_LH])
+#define RSCAN0RMDF19H (RSCAN0.RMDF19.UINT16[R_IO_H])
+#define RSCAN0RMDF19HL (RSCAN0.RMDF19.UINT8[R_IO_HL])
+#define RSCAN0RMDF19HH (RSCAN0.RMDF19.UINT8[R_IO_HH])
+#define RSCAN0RMID10 (RSCAN0.RMID10.UINT32)
+#define RSCAN0RMID10L (RSCAN0.RMID10.UINT16[R_IO_L])
+#define RSCAN0RMID10LL (RSCAN0.RMID10.UINT8[R_IO_LL])
+#define RSCAN0RMID10LH (RSCAN0.RMID10.UINT8[R_IO_LH])
+#define RSCAN0RMID10H (RSCAN0.RMID10.UINT16[R_IO_H])
+#define RSCAN0RMID10HL (RSCAN0.RMID10.UINT8[R_IO_HL])
+#define RSCAN0RMID10HH (RSCAN0.RMID10.UINT8[R_IO_HH])
+#define RSCAN0RMPTR10 (RSCAN0.RMPTR10.UINT32)
+#define RSCAN0RMPTR10L (RSCAN0.RMPTR10.UINT16[R_IO_L])
+#define RSCAN0RMPTR10LL (RSCAN0.RMPTR10.UINT8[R_IO_LL])
+#define RSCAN0RMPTR10LH (RSCAN0.RMPTR10.UINT8[R_IO_LH])
+#define RSCAN0RMPTR10H (RSCAN0.RMPTR10.UINT16[R_IO_H])
+#define RSCAN0RMPTR10HL (RSCAN0.RMPTR10.UINT8[R_IO_HL])
+#define RSCAN0RMPTR10HH (RSCAN0.RMPTR10.UINT8[R_IO_HH])
+#define RSCAN0RMDF010 (RSCAN0.RMDF010.UINT32)
+#define RSCAN0RMDF010L (RSCAN0.RMDF010.UINT16[R_IO_L])
+#define RSCAN0RMDF010LL (RSCAN0.RMDF010.UINT8[R_IO_LL])
+#define RSCAN0RMDF010LH (RSCAN0.RMDF010.UINT8[R_IO_LH])
+#define RSCAN0RMDF010H (RSCAN0.RMDF010.UINT16[R_IO_H])
+#define RSCAN0RMDF010HL (RSCAN0.RMDF010.UINT8[R_IO_HL])
+#define RSCAN0RMDF010HH (RSCAN0.RMDF010.UINT8[R_IO_HH])
+#define RSCAN0RMDF110 (RSCAN0.RMDF110.UINT32)
+#define RSCAN0RMDF110L (RSCAN0.RMDF110.UINT16[R_IO_L])
+#define RSCAN0RMDF110LL (RSCAN0.RMDF110.UINT8[R_IO_LL])
+#define RSCAN0RMDF110LH (RSCAN0.RMDF110.UINT8[R_IO_LH])
+#define RSCAN0RMDF110H (RSCAN0.RMDF110.UINT16[R_IO_H])
+#define RSCAN0RMDF110HL (RSCAN0.RMDF110.UINT8[R_IO_HL])
+#define RSCAN0RMDF110HH (RSCAN0.RMDF110.UINT8[R_IO_HH])
+#define RSCAN0RMID11 (RSCAN0.RMID11.UINT32)
+#define RSCAN0RMID11L (RSCAN0.RMID11.UINT16[R_IO_L])
+#define RSCAN0RMID11LL (RSCAN0.RMID11.UINT8[R_IO_LL])
+#define RSCAN0RMID11LH (RSCAN0.RMID11.UINT8[R_IO_LH])
+#define RSCAN0RMID11H (RSCAN0.RMID11.UINT16[R_IO_H])
+#define RSCAN0RMID11HL (RSCAN0.RMID11.UINT8[R_IO_HL])
+#define RSCAN0RMID11HH (RSCAN0.RMID11.UINT8[R_IO_HH])
+#define RSCAN0RMPTR11 (RSCAN0.RMPTR11.UINT32)
+#define RSCAN0RMPTR11L (RSCAN0.RMPTR11.UINT16[R_IO_L])
+#define RSCAN0RMPTR11LL (RSCAN0.RMPTR11.UINT8[R_IO_LL])
+#define RSCAN0RMPTR11LH (RSCAN0.RMPTR11.UINT8[R_IO_LH])
+#define RSCAN0RMPTR11H (RSCAN0.RMPTR11.UINT16[R_IO_H])
+#define RSCAN0RMPTR11HL (RSCAN0.RMPTR11.UINT8[R_IO_HL])
+#define RSCAN0RMPTR11HH (RSCAN0.RMPTR11.UINT8[R_IO_HH])
+#define RSCAN0RMDF011 (RSCAN0.RMDF011.UINT32)
+#define RSCAN0RMDF011L (RSCAN0.RMDF011.UINT16[R_IO_L])
+#define RSCAN0RMDF011LL (RSCAN0.RMDF011.UINT8[R_IO_LL])
+#define RSCAN0RMDF011LH (RSCAN0.RMDF011.UINT8[R_IO_LH])
+#define RSCAN0RMDF011H (RSCAN0.RMDF011.UINT16[R_IO_H])
+#define RSCAN0RMDF011HL (RSCAN0.RMDF011.UINT8[R_IO_HL])
+#define RSCAN0RMDF011HH (RSCAN0.RMDF011.UINT8[R_IO_HH])
+#define RSCAN0RMDF111 (RSCAN0.RMDF111.UINT32)
+#define RSCAN0RMDF111L (RSCAN0.RMDF111.UINT16[R_IO_L])
+#define RSCAN0RMDF111LL (RSCAN0.RMDF111.UINT8[R_IO_LL])
+#define RSCAN0RMDF111LH (RSCAN0.RMDF111.UINT8[R_IO_LH])
+#define RSCAN0RMDF111H (RSCAN0.RMDF111.UINT16[R_IO_H])
+#define RSCAN0RMDF111HL (RSCAN0.RMDF111.UINT8[R_IO_HL])
+#define RSCAN0RMDF111HH (RSCAN0.RMDF111.UINT8[R_IO_HH])
+#define RSCAN0RMID12 (RSCAN0.RMID12.UINT32)
+#define RSCAN0RMID12L (RSCAN0.RMID12.UINT16[R_IO_L])
+#define RSCAN0RMID12LL (RSCAN0.RMID12.UINT8[R_IO_LL])
+#define RSCAN0RMID12LH (RSCAN0.RMID12.UINT8[R_IO_LH])
+#define RSCAN0RMID12H (RSCAN0.RMID12.UINT16[R_IO_H])
+#define RSCAN0RMID12HL (RSCAN0.RMID12.UINT8[R_IO_HL])
+#define RSCAN0RMID12HH (RSCAN0.RMID12.UINT8[R_IO_HH])
+#define RSCAN0RMPTR12 (RSCAN0.RMPTR12.UINT32)
+#define RSCAN0RMPTR12L (RSCAN0.RMPTR12.UINT16[R_IO_L])
+#define RSCAN0RMPTR12LL (RSCAN0.RMPTR12.UINT8[R_IO_LL])
+#define RSCAN0RMPTR12LH (RSCAN0.RMPTR12.UINT8[R_IO_LH])
+#define RSCAN0RMPTR12H (RSCAN0.RMPTR12.UINT16[R_IO_H])
+#define RSCAN0RMPTR12HL (RSCAN0.RMPTR12.UINT8[R_IO_HL])
+#define RSCAN0RMPTR12HH (RSCAN0.RMPTR12.UINT8[R_IO_HH])
+#define RSCAN0RMDF012 (RSCAN0.RMDF012.UINT32)
+#define RSCAN0RMDF012L (RSCAN0.RMDF012.UINT16[R_IO_L])
+#define RSCAN0RMDF012LL (RSCAN0.RMDF012.UINT8[R_IO_LL])
+#define RSCAN0RMDF012LH (RSCAN0.RMDF012.UINT8[R_IO_LH])
+#define RSCAN0RMDF012H (RSCAN0.RMDF012.UINT16[R_IO_H])
+#define RSCAN0RMDF012HL (RSCAN0.RMDF012.UINT8[R_IO_HL])
+#define RSCAN0RMDF012HH (RSCAN0.RMDF012.UINT8[R_IO_HH])
+#define RSCAN0RMDF112 (RSCAN0.RMDF112.UINT32)
+#define RSCAN0RMDF112L (RSCAN0.RMDF112.UINT16[R_IO_L])
+#define RSCAN0RMDF112LL (RSCAN0.RMDF112.UINT8[R_IO_LL])
+#define RSCAN0RMDF112LH (RSCAN0.RMDF112.UINT8[R_IO_LH])
+#define RSCAN0RMDF112H (RSCAN0.RMDF112.UINT16[R_IO_H])
+#define RSCAN0RMDF112HL (RSCAN0.RMDF112.UINT8[R_IO_HL])
+#define RSCAN0RMDF112HH (RSCAN0.RMDF112.UINT8[R_IO_HH])
+#define RSCAN0RMID13 (RSCAN0.RMID13.UINT32)
+#define RSCAN0RMID13L (RSCAN0.RMID13.UINT16[R_IO_L])
+#define RSCAN0RMID13LL (RSCAN0.RMID13.UINT8[R_IO_LL])
+#define RSCAN0RMID13LH (RSCAN0.RMID13.UINT8[R_IO_LH])
+#define RSCAN0RMID13H (RSCAN0.RMID13.UINT16[R_IO_H])
+#define RSCAN0RMID13HL (RSCAN0.RMID13.UINT8[R_IO_HL])
+#define RSCAN0RMID13HH (RSCAN0.RMID13.UINT8[R_IO_HH])
+#define RSCAN0RMPTR13 (RSCAN0.RMPTR13.UINT32)
+#define RSCAN0RMPTR13L (RSCAN0.RMPTR13.UINT16[R_IO_L])
+#define RSCAN0RMPTR13LL (RSCAN0.RMPTR13.UINT8[R_IO_LL])
+#define RSCAN0RMPTR13LH (RSCAN0.RMPTR13.UINT8[R_IO_LH])
+#define RSCAN0RMPTR13H (RSCAN0.RMPTR13.UINT16[R_IO_H])
+#define RSCAN0RMPTR13HL (RSCAN0.RMPTR13.UINT8[R_IO_HL])
+#define RSCAN0RMPTR13HH (RSCAN0.RMPTR13.UINT8[R_IO_HH])
+#define RSCAN0RMDF013 (RSCAN0.RMDF013.UINT32)
+#define RSCAN0RMDF013L (RSCAN0.RMDF013.UINT16[R_IO_L])
+#define RSCAN0RMDF013LL (RSCAN0.RMDF013.UINT8[R_IO_LL])
+#define RSCAN0RMDF013LH (RSCAN0.RMDF013.UINT8[R_IO_LH])
+#define RSCAN0RMDF013H (RSCAN0.RMDF013.UINT16[R_IO_H])
+#define RSCAN0RMDF013HL (RSCAN0.RMDF013.UINT8[R_IO_HL])
+#define RSCAN0RMDF013HH (RSCAN0.RMDF013.UINT8[R_IO_HH])
+#define RSCAN0RMDF113 (RSCAN0.RMDF113.UINT32)
+#define RSCAN0RMDF113L (RSCAN0.RMDF113.UINT16[R_IO_L])
+#define RSCAN0RMDF113LL (RSCAN0.RMDF113.UINT8[R_IO_LL])
+#define RSCAN0RMDF113LH (RSCAN0.RMDF113.UINT8[R_IO_LH])
+#define RSCAN0RMDF113H (RSCAN0.RMDF113.UINT16[R_IO_H])
+#define RSCAN0RMDF113HL (RSCAN0.RMDF113.UINT8[R_IO_HL])
+#define RSCAN0RMDF113HH (RSCAN0.RMDF113.UINT8[R_IO_HH])
+#define RSCAN0RMID14 (RSCAN0.RMID14.UINT32)
+#define RSCAN0RMID14L (RSCAN0.RMID14.UINT16[R_IO_L])
+#define RSCAN0RMID14LL (RSCAN0.RMID14.UINT8[R_IO_LL])
+#define RSCAN0RMID14LH (RSCAN0.RMID14.UINT8[R_IO_LH])
+#define RSCAN0RMID14H (RSCAN0.RMID14.UINT16[R_IO_H])
+#define RSCAN0RMID14HL (RSCAN0.RMID14.UINT8[R_IO_HL])
+#define RSCAN0RMID14HH (RSCAN0.RMID14.UINT8[R_IO_HH])
+#define RSCAN0RMPTR14 (RSCAN0.RMPTR14.UINT32)
+#define RSCAN0RMPTR14L (RSCAN0.RMPTR14.UINT16[R_IO_L])
+#define RSCAN0RMPTR14LL (RSCAN0.RMPTR14.UINT8[R_IO_LL])
+#define RSCAN0RMPTR14LH (RSCAN0.RMPTR14.UINT8[R_IO_LH])
+#define RSCAN0RMPTR14H (RSCAN0.RMPTR14.UINT16[R_IO_H])
+#define RSCAN0RMPTR14HL (RSCAN0.RMPTR14.UINT8[R_IO_HL])
+#define RSCAN0RMPTR14HH (RSCAN0.RMPTR14.UINT8[R_IO_HH])
+#define RSCAN0RMDF014 (RSCAN0.RMDF014.UINT32)
+#define RSCAN0RMDF014L (RSCAN0.RMDF014.UINT16[R_IO_L])
+#define RSCAN0RMDF014LL (RSCAN0.RMDF014.UINT8[R_IO_LL])
+#define RSCAN0RMDF014LH (RSCAN0.RMDF014.UINT8[R_IO_LH])
+#define RSCAN0RMDF014H (RSCAN0.RMDF014.UINT16[R_IO_H])
+#define RSCAN0RMDF014HL (RSCAN0.RMDF014.UINT8[R_IO_HL])
+#define RSCAN0RMDF014HH (RSCAN0.RMDF014.UINT8[R_IO_HH])
+#define RSCAN0RMDF114 (RSCAN0.RMDF114.UINT32)
+#define RSCAN0RMDF114L (RSCAN0.RMDF114.UINT16[R_IO_L])
+#define RSCAN0RMDF114LL (RSCAN0.RMDF114.UINT8[R_IO_LL])
+#define RSCAN0RMDF114LH (RSCAN0.RMDF114.UINT8[R_IO_LH])
+#define RSCAN0RMDF114H (RSCAN0.RMDF114.UINT16[R_IO_H])
+#define RSCAN0RMDF114HL (RSCAN0.RMDF114.UINT8[R_IO_HL])
+#define RSCAN0RMDF114HH (RSCAN0.RMDF114.UINT8[R_IO_HH])
+#define RSCAN0RMID15 (RSCAN0.RMID15.UINT32)
+#define RSCAN0RMID15L (RSCAN0.RMID15.UINT16[R_IO_L])
+#define RSCAN0RMID15LL (RSCAN0.RMID15.UINT8[R_IO_LL])
+#define RSCAN0RMID15LH (RSCAN0.RMID15.UINT8[R_IO_LH])
+#define RSCAN0RMID15H (RSCAN0.RMID15.UINT16[R_IO_H])
+#define RSCAN0RMID15HL (RSCAN0.RMID15.UINT8[R_IO_HL])
+#define RSCAN0RMID15HH (RSCAN0.RMID15.UINT8[R_IO_HH])
+#define RSCAN0RMPTR15 (RSCAN0.RMPTR15.UINT32)
+#define RSCAN0RMPTR15L (RSCAN0.RMPTR15.UINT16[R_IO_L])
+#define RSCAN0RMPTR15LL (RSCAN0.RMPTR15.UINT8[R_IO_LL])
+#define RSCAN0RMPTR15LH (RSCAN0.RMPTR15.UINT8[R_IO_LH])
+#define RSCAN0RMPTR15H (RSCAN0.RMPTR15.UINT16[R_IO_H])
+#define RSCAN0RMPTR15HL (RSCAN0.RMPTR15.UINT8[R_IO_HL])
+#define RSCAN0RMPTR15HH (RSCAN0.RMPTR15.UINT8[R_IO_HH])
+#define RSCAN0RMDF015 (RSCAN0.RMDF015.UINT32)
+#define RSCAN0RMDF015L (RSCAN0.RMDF015.UINT16[R_IO_L])
+#define RSCAN0RMDF015LL (RSCAN0.RMDF015.UINT8[R_IO_LL])
+#define RSCAN0RMDF015LH (RSCAN0.RMDF015.UINT8[R_IO_LH])
+#define RSCAN0RMDF015H (RSCAN0.RMDF015.UINT16[R_IO_H])
+#define RSCAN0RMDF015HL (RSCAN0.RMDF015.UINT8[R_IO_HL])
+#define RSCAN0RMDF015HH (RSCAN0.RMDF015.UINT8[R_IO_HH])
+#define RSCAN0RMDF115 (RSCAN0.RMDF115.UINT32)
+#define RSCAN0RMDF115L (RSCAN0.RMDF115.UINT16[R_IO_L])
+#define RSCAN0RMDF115LL (RSCAN0.RMDF115.UINT8[R_IO_LL])
+#define RSCAN0RMDF115LH (RSCAN0.RMDF115.UINT8[R_IO_LH])
+#define RSCAN0RMDF115H (RSCAN0.RMDF115.UINT16[R_IO_H])
+#define RSCAN0RMDF115HL (RSCAN0.RMDF115.UINT8[R_IO_HL])
+#define RSCAN0RMDF115HH (RSCAN0.RMDF115.UINT8[R_IO_HH])
+#define RSCAN0RMID16 (RSCAN0.RMID16.UINT32)
+#define RSCAN0RMID16L (RSCAN0.RMID16.UINT16[R_IO_L])
+#define RSCAN0RMID16LL (RSCAN0.RMID16.UINT8[R_IO_LL])
+#define RSCAN0RMID16LH (RSCAN0.RMID16.UINT8[R_IO_LH])
+#define RSCAN0RMID16H (RSCAN0.RMID16.UINT16[R_IO_H])
+#define RSCAN0RMID16HL (RSCAN0.RMID16.UINT8[R_IO_HL])
+#define RSCAN0RMID16HH (RSCAN0.RMID16.UINT8[R_IO_HH])
+#define RSCAN0RMPTR16 (RSCAN0.RMPTR16.UINT32)
+#define RSCAN0RMPTR16L (RSCAN0.RMPTR16.UINT16[R_IO_L])
+#define RSCAN0RMPTR16LL (RSCAN0.RMPTR16.UINT8[R_IO_LL])
+#define RSCAN0RMPTR16LH (RSCAN0.RMPTR16.UINT8[R_IO_LH])
+#define RSCAN0RMPTR16H (RSCAN0.RMPTR16.UINT16[R_IO_H])
+#define RSCAN0RMPTR16HL (RSCAN0.RMPTR16.UINT8[R_IO_HL])
+#define RSCAN0RMPTR16HH (RSCAN0.RMPTR16.UINT8[R_IO_HH])
+#define RSCAN0RMDF016 (RSCAN0.RMDF016.UINT32)
+#define RSCAN0RMDF016L (RSCAN0.RMDF016.UINT16[R_IO_L])
+#define RSCAN0RMDF016LL (RSCAN0.RMDF016.UINT8[R_IO_LL])
+#define RSCAN0RMDF016LH (RSCAN0.RMDF016.UINT8[R_IO_LH])
+#define RSCAN0RMDF016H (RSCAN0.RMDF016.UINT16[R_IO_H])
+#define RSCAN0RMDF016HL (RSCAN0.RMDF016.UINT8[R_IO_HL])
+#define RSCAN0RMDF016HH (RSCAN0.RMDF016.UINT8[R_IO_HH])
+#define RSCAN0RMDF116 (RSCAN0.RMDF116.UINT32)
+#define RSCAN0RMDF116L (RSCAN0.RMDF116.UINT16[R_IO_L])
+#define RSCAN0RMDF116LL (RSCAN0.RMDF116.UINT8[R_IO_LL])
+#define RSCAN0RMDF116LH (RSCAN0.RMDF116.UINT8[R_IO_LH])
+#define RSCAN0RMDF116H (RSCAN0.RMDF116.UINT16[R_IO_H])
+#define RSCAN0RMDF116HL (RSCAN0.RMDF116.UINT8[R_IO_HL])
+#define RSCAN0RMDF116HH (RSCAN0.RMDF116.UINT8[R_IO_HH])
+#define RSCAN0RMID17 (RSCAN0.RMID17.UINT32)
+#define RSCAN0RMID17L (RSCAN0.RMID17.UINT16[R_IO_L])
+#define RSCAN0RMID17LL (RSCAN0.RMID17.UINT8[R_IO_LL])
+#define RSCAN0RMID17LH (RSCAN0.RMID17.UINT8[R_IO_LH])
+#define RSCAN0RMID17H (RSCAN0.RMID17.UINT16[R_IO_H])
+#define RSCAN0RMID17HL (RSCAN0.RMID17.UINT8[R_IO_HL])
+#define RSCAN0RMID17HH (RSCAN0.RMID17.UINT8[R_IO_HH])
+#define RSCAN0RMPTR17 (RSCAN0.RMPTR17.UINT32)
+#define RSCAN0RMPTR17L (RSCAN0.RMPTR17.UINT16[R_IO_L])
+#define RSCAN0RMPTR17LL (RSCAN0.RMPTR17.UINT8[R_IO_LL])
+#define RSCAN0RMPTR17LH (RSCAN0.RMPTR17.UINT8[R_IO_LH])
+#define RSCAN0RMPTR17H (RSCAN0.RMPTR17.UINT16[R_IO_H])
+#define RSCAN0RMPTR17HL (RSCAN0.RMPTR17.UINT8[R_IO_HL])
+#define RSCAN0RMPTR17HH (RSCAN0.RMPTR17.UINT8[R_IO_HH])
+#define RSCAN0RMDF017 (RSCAN0.RMDF017.UINT32)
+#define RSCAN0RMDF017L (RSCAN0.RMDF017.UINT16[R_IO_L])
+#define RSCAN0RMDF017LL (RSCAN0.RMDF017.UINT8[R_IO_LL])
+#define RSCAN0RMDF017LH (RSCAN0.RMDF017.UINT8[R_IO_LH])
+#define RSCAN0RMDF017H (RSCAN0.RMDF017.UINT16[R_IO_H])
+#define RSCAN0RMDF017HL (RSCAN0.RMDF017.UINT8[R_IO_HL])
+#define RSCAN0RMDF017HH (RSCAN0.RMDF017.UINT8[R_IO_HH])
+#define RSCAN0RMDF117 (RSCAN0.RMDF117.UINT32)
+#define RSCAN0RMDF117L (RSCAN0.RMDF117.UINT16[R_IO_L])
+#define RSCAN0RMDF117LL (RSCAN0.RMDF117.UINT8[R_IO_LL])
+#define RSCAN0RMDF117LH (RSCAN0.RMDF117.UINT8[R_IO_LH])
+#define RSCAN0RMDF117H (RSCAN0.RMDF117.UINT16[R_IO_H])
+#define RSCAN0RMDF117HL (RSCAN0.RMDF117.UINT8[R_IO_HL])
+#define RSCAN0RMDF117HH (RSCAN0.RMDF117.UINT8[R_IO_HH])
+#define RSCAN0RMID18 (RSCAN0.RMID18.UINT32)
+#define RSCAN0RMID18L (RSCAN0.RMID18.UINT16[R_IO_L])
+#define RSCAN0RMID18LL (RSCAN0.RMID18.UINT8[R_IO_LL])
+#define RSCAN0RMID18LH (RSCAN0.RMID18.UINT8[R_IO_LH])
+#define RSCAN0RMID18H (RSCAN0.RMID18.UINT16[R_IO_H])
+#define RSCAN0RMID18HL (RSCAN0.RMID18.UINT8[R_IO_HL])
+#define RSCAN0RMID18HH (RSCAN0.RMID18.UINT8[R_IO_HH])
+#define RSCAN0RMPTR18 (RSCAN0.RMPTR18.UINT32)
+#define RSCAN0RMPTR18L (RSCAN0.RMPTR18.UINT16[R_IO_L])
+#define RSCAN0RMPTR18LL (RSCAN0.RMPTR18.UINT8[R_IO_LL])
+#define RSCAN0RMPTR18LH (RSCAN0.RMPTR18.UINT8[R_IO_LH])
+#define RSCAN0RMPTR18H (RSCAN0.RMPTR18.UINT16[R_IO_H])
+#define RSCAN0RMPTR18HL (RSCAN0.RMPTR18.UINT8[R_IO_HL])
+#define RSCAN0RMPTR18HH (RSCAN0.RMPTR18.UINT8[R_IO_HH])
+#define RSCAN0RMDF018 (RSCAN0.RMDF018.UINT32)
+#define RSCAN0RMDF018L (RSCAN0.RMDF018.UINT16[R_IO_L])
+#define RSCAN0RMDF018LL (RSCAN0.RMDF018.UINT8[R_IO_LL])
+#define RSCAN0RMDF018LH (RSCAN0.RMDF018.UINT8[R_IO_LH])
+#define RSCAN0RMDF018H (RSCAN0.RMDF018.UINT16[R_IO_H])
+#define RSCAN0RMDF018HL (RSCAN0.RMDF018.UINT8[R_IO_HL])
+#define RSCAN0RMDF018HH (RSCAN0.RMDF018.UINT8[R_IO_HH])
+#define RSCAN0RMDF118 (RSCAN0.RMDF118.UINT32)
+#define RSCAN0RMDF118L (RSCAN0.RMDF118.UINT16[R_IO_L])
+#define RSCAN0RMDF118LL (RSCAN0.RMDF118.UINT8[R_IO_LL])
+#define RSCAN0RMDF118LH (RSCAN0.RMDF118.UINT8[R_IO_LH])
+#define RSCAN0RMDF118H (RSCAN0.RMDF118.UINT16[R_IO_H])
+#define RSCAN0RMDF118HL (RSCAN0.RMDF118.UINT8[R_IO_HL])
+#define RSCAN0RMDF118HH (RSCAN0.RMDF118.UINT8[R_IO_HH])
+#define RSCAN0RMID19 (RSCAN0.RMID19.UINT32)
+#define RSCAN0RMID19L (RSCAN0.RMID19.UINT16[R_IO_L])
+#define RSCAN0RMID19LL (RSCAN0.RMID19.UINT8[R_IO_LL])
+#define RSCAN0RMID19LH (RSCAN0.RMID19.UINT8[R_IO_LH])
+#define RSCAN0RMID19H (RSCAN0.RMID19.UINT16[R_IO_H])
+#define RSCAN0RMID19HL (RSCAN0.RMID19.UINT8[R_IO_HL])
+#define RSCAN0RMID19HH (RSCAN0.RMID19.UINT8[R_IO_HH])
+#define RSCAN0RMPTR19 (RSCAN0.RMPTR19.UINT32)
+#define RSCAN0RMPTR19L (RSCAN0.RMPTR19.UINT16[R_IO_L])
+#define RSCAN0RMPTR19LL (RSCAN0.RMPTR19.UINT8[R_IO_LL])
+#define RSCAN0RMPTR19LH (RSCAN0.RMPTR19.UINT8[R_IO_LH])
+#define RSCAN0RMPTR19H (RSCAN0.RMPTR19.UINT16[R_IO_H])
+#define RSCAN0RMPTR19HL (RSCAN0.RMPTR19.UINT8[R_IO_HL])
+#define RSCAN0RMPTR19HH (RSCAN0.RMPTR19.UINT8[R_IO_HH])
+#define RSCAN0RMDF019 (RSCAN0.RMDF019.UINT32)
+#define RSCAN0RMDF019L (RSCAN0.RMDF019.UINT16[R_IO_L])
+#define RSCAN0RMDF019LL (RSCAN0.RMDF019.UINT8[R_IO_LL])
+#define RSCAN0RMDF019LH (RSCAN0.RMDF019.UINT8[R_IO_LH])
+#define RSCAN0RMDF019H (RSCAN0.RMDF019.UINT16[R_IO_H])
+#define RSCAN0RMDF019HL (RSCAN0.RMDF019.UINT8[R_IO_HL])
+#define RSCAN0RMDF019HH (RSCAN0.RMDF019.UINT8[R_IO_HH])
+#define RSCAN0RMDF119 (RSCAN0.RMDF119.UINT32)
+#define RSCAN0RMDF119L (RSCAN0.RMDF119.UINT16[R_IO_L])
+#define RSCAN0RMDF119LL (RSCAN0.RMDF119.UINT8[R_IO_LL])
+#define RSCAN0RMDF119LH (RSCAN0.RMDF119.UINT8[R_IO_LH])
+#define RSCAN0RMDF119H (RSCAN0.RMDF119.UINT16[R_IO_H])
+#define RSCAN0RMDF119HL (RSCAN0.RMDF119.UINT8[R_IO_HL])
+#define RSCAN0RMDF119HH (RSCAN0.RMDF119.UINT8[R_IO_HH])
+#define RSCAN0RMID20 (RSCAN0.RMID20.UINT32)
+#define RSCAN0RMID20L (RSCAN0.RMID20.UINT16[R_IO_L])
+#define RSCAN0RMID20LL (RSCAN0.RMID20.UINT8[R_IO_LL])
+#define RSCAN0RMID20LH (RSCAN0.RMID20.UINT8[R_IO_LH])
+#define RSCAN0RMID20H (RSCAN0.RMID20.UINT16[R_IO_H])
+#define RSCAN0RMID20HL (RSCAN0.RMID20.UINT8[R_IO_HL])
+#define RSCAN0RMID20HH (RSCAN0.RMID20.UINT8[R_IO_HH])
+#define RSCAN0RMPTR20 (RSCAN0.RMPTR20.UINT32)
+#define RSCAN0RMPTR20L (RSCAN0.RMPTR20.UINT16[R_IO_L])
+#define RSCAN0RMPTR20LL (RSCAN0.RMPTR20.UINT8[R_IO_LL])
+#define RSCAN0RMPTR20LH (RSCAN0.RMPTR20.UINT8[R_IO_LH])
+#define RSCAN0RMPTR20H (RSCAN0.RMPTR20.UINT16[R_IO_H])
+#define RSCAN0RMPTR20HL (RSCAN0.RMPTR20.UINT8[R_IO_HL])
+#define RSCAN0RMPTR20HH (RSCAN0.RMPTR20.UINT8[R_IO_HH])
+#define RSCAN0RMDF020 (RSCAN0.RMDF020.UINT32)
+#define RSCAN0RMDF020L (RSCAN0.RMDF020.UINT16[R_IO_L])
+#define RSCAN0RMDF020LL (RSCAN0.RMDF020.UINT8[R_IO_LL])
+#define RSCAN0RMDF020LH (RSCAN0.RMDF020.UINT8[R_IO_LH])
+#define RSCAN0RMDF020H (RSCAN0.RMDF020.UINT16[R_IO_H])
+#define RSCAN0RMDF020HL (RSCAN0.RMDF020.UINT8[R_IO_HL])
+#define RSCAN0RMDF020HH (RSCAN0.RMDF020.UINT8[R_IO_HH])
+#define RSCAN0RMDF120 (RSCAN0.RMDF120.UINT32)
+#define RSCAN0RMDF120L (RSCAN0.RMDF120.UINT16[R_IO_L])
+#define RSCAN0RMDF120LL (RSCAN0.RMDF120.UINT8[R_IO_LL])
+#define RSCAN0RMDF120LH (RSCAN0.RMDF120.UINT8[R_IO_LH])
+#define RSCAN0RMDF120H (RSCAN0.RMDF120.UINT16[R_IO_H])
+#define RSCAN0RMDF120HL (RSCAN0.RMDF120.UINT8[R_IO_HL])
+#define RSCAN0RMDF120HH (RSCAN0.RMDF120.UINT8[R_IO_HH])
+#define RSCAN0RMID21 (RSCAN0.RMID21.UINT32)
+#define RSCAN0RMID21L (RSCAN0.RMID21.UINT16[R_IO_L])
+#define RSCAN0RMID21LL (RSCAN0.RMID21.UINT8[R_IO_LL])
+#define RSCAN0RMID21LH (RSCAN0.RMID21.UINT8[R_IO_LH])
+#define RSCAN0RMID21H (RSCAN0.RMID21.UINT16[R_IO_H])
+#define RSCAN0RMID21HL (RSCAN0.RMID21.UINT8[R_IO_HL])
+#define RSCAN0RMID21HH (RSCAN0.RMID21.UINT8[R_IO_HH])
+#define RSCAN0RMPTR21 (RSCAN0.RMPTR21.UINT32)
+#define RSCAN0RMPTR21L (RSCAN0.RMPTR21.UINT16[R_IO_L])
+#define RSCAN0RMPTR21LL (RSCAN0.RMPTR21.UINT8[R_IO_LL])
+#define RSCAN0RMPTR21LH (RSCAN0.RMPTR21.UINT8[R_IO_LH])
+#define RSCAN0RMPTR21H (RSCAN0.RMPTR21.UINT16[R_IO_H])
+#define RSCAN0RMPTR21HL (RSCAN0.RMPTR21.UINT8[R_IO_HL])
+#define RSCAN0RMPTR21HH (RSCAN0.RMPTR21.UINT8[R_IO_HH])
+#define RSCAN0RMDF021 (RSCAN0.RMDF021.UINT32)
+#define RSCAN0RMDF021L (RSCAN0.RMDF021.UINT16[R_IO_L])
+#define RSCAN0RMDF021LL (RSCAN0.RMDF021.UINT8[R_IO_LL])
+#define RSCAN0RMDF021LH (RSCAN0.RMDF021.UINT8[R_IO_LH])
+#define RSCAN0RMDF021H (RSCAN0.RMDF021.UINT16[R_IO_H])
+#define RSCAN0RMDF021HL (RSCAN0.RMDF021.UINT8[R_IO_HL])
+#define RSCAN0RMDF021HH (RSCAN0.RMDF021.UINT8[R_IO_HH])
+#define RSCAN0RMDF121 (RSCAN0.RMDF121.UINT32)
+#define RSCAN0RMDF121L (RSCAN0.RMDF121.UINT16[R_IO_L])
+#define RSCAN0RMDF121LL (RSCAN0.RMDF121.UINT8[R_IO_LL])
+#define RSCAN0RMDF121LH (RSCAN0.RMDF121.UINT8[R_IO_LH])
+#define RSCAN0RMDF121H (RSCAN0.RMDF121.UINT16[R_IO_H])
+#define RSCAN0RMDF121HL (RSCAN0.RMDF121.UINT8[R_IO_HL])
+#define RSCAN0RMDF121HH (RSCAN0.RMDF121.UINT8[R_IO_HH])
+#define RSCAN0RMID22 (RSCAN0.RMID22.UINT32)
+#define RSCAN0RMID22L (RSCAN0.RMID22.UINT16[R_IO_L])
+#define RSCAN0RMID22LL (RSCAN0.RMID22.UINT8[R_IO_LL])
+#define RSCAN0RMID22LH (RSCAN0.RMID22.UINT8[R_IO_LH])
+#define RSCAN0RMID22H (RSCAN0.RMID22.UINT16[R_IO_H])
+#define RSCAN0RMID22HL (RSCAN0.RMID22.UINT8[R_IO_HL])
+#define RSCAN0RMID22HH (RSCAN0.RMID22.UINT8[R_IO_HH])
+#define RSCAN0RMPTR22 (RSCAN0.RMPTR22.UINT32)
+#define RSCAN0RMPTR22L (RSCAN0.RMPTR22.UINT16[R_IO_L])
+#define RSCAN0RMPTR22LL (RSCAN0.RMPTR22.UINT8[R_IO_LL])
+#define RSCAN0RMPTR22LH (RSCAN0.RMPTR22.UINT8[R_IO_LH])
+#define RSCAN0RMPTR22H (RSCAN0.RMPTR22.UINT16[R_IO_H])
+#define RSCAN0RMPTR22HL (RSCAN0.RMPTR22.UINT8[R_IO_HL])
+#define RSCAN0RMPTR22HH (RSCAN0.RMPTR22.UINT8[R_IO_HH])
+#define RSCAN0RMDF022 (RSCAN0.RMDF022.UINT32)
+#define RSCAN0RMDF022L (RSCAN0.RMDF022.UINT16[R_IO_L])
+#define RSCAN0RMDF022LL (RSCAN0.RMDF022.UINT8[R_IO_LL])
+#define RSCAN0RMDF022LH (RSCAN0.RMDF022.UINT8[R_IO_LH])
+#define RSCAN0RMDF022H (RSCAN0.RMDF022.UINT16[R_IO_H])
+#define RSCAN0RMDF022HL (RSCAN0.RMDF022.UINT8[R_IO_HL])
+#define RSCAN0RMDF022HH (RSCAN0.RMDF022.UINT8[R_IO_HH])
+#define RSCAN0RMDF122 (RSCAN0.RMDF122.UINT32)
+#define RSCAN0RMDF122L (RSCAN0.RMDF122.UINT16[R_IO_L])
+#define RSCAN0RMDF122LL (RSCAN0.RMDF122.UINT8[R_IO_LL])
+#define RSCAN0RMDF122LH (RSCAN0.RMDF122.UINT8[R_IO_LH])
+#define RSCAN0RMDF122H (RSCAN0.RMDF122.UINT16[R_IO_H])
+#define RSCAN0RMDF122HL (RSCAN0.RMDF122.UINT8[R_IO_HL])
+#define RSCAN0RMDF122HH (RSCAN0.RMDF122.UINT8[R_IO_HH])
+#define RSCAN0RMID23 (RSCAN0.RMID23.UINT32)
+#define RSCAN0RMID23L (RSCAN0.RMID23.UINT16[R_IO_L])
+#define RSCAN0RMID23LL (RSCAN0.RMID23.UINT8[R_IO_LL])
+#define RSCAN0RMID23LH (RSCAN0.RMID23.UINT8[R_IO_LH])
+#define RSCAN0RMID23H (RSCAN0.RMID23.UINT16[R_IO_H])
+#define RSCAN0RMID23HL (RSCAN0.RMID23.UINT8[R_IO_HL])
+#define RSCAN0RMID23HH (RSCAN0.RMID23.UINT8[R_IO_HH])
+#define RSCAN0RMPTR23 (RSCAN0.RMPTR23.UINT32)
+#define RSCAN0RMPTR23L (RSCAN0.RMPTR23.UINT16[R_IO_L])
+#define RSCAN0RMPTR23LL (RSCAN0.RMPTR23.UINT8[R_IO_LL])
+#define RSCAN0RMPTR23LH (RSCAN0.RMPTR23.UINT8[R_IO_LH])
+#define RSCAN0RMPTR23H (RSCAN0.RMPTR23.UINT16[R_IO_H])
+#define RSCAN0RMPTR23HL (RSCAN0.RMPTR23.UINT8[R_IO_HL])
+#define RSCAN0RMPTR23HH (RSCAN0.RMPTR23.UINT8[R_IO_HH])
+#define RSCAN0RMDF023 (RSCAN0.RMDF023.UINT32)
+#define RSCAN0RMDF023L (RSCAN0.RMDF023.UINT16[R_IO_L])
+#define RSCAN0RMDF023LL (RSCAN0.RMDF023.UINT8[R_IO_LL])
+#define RSCAN0RMDF023LH (RSCAN0.RMDF023.UINT8[R_IO_LH])
+#define RSCAN0RMDF023H (RSCAN0.RMDF023.UINT16[R_IO_H])
+#define RSCAN0RMDF023HL (RSCAN0.RMDF023.UINT8[R_IO_HL])
+#define RSCAN0RMDF023HH (RSCAN0.RMDF023.UINT8[R_IO_HH])
+#define RSCAN0RMDF123 (RSCAN0.RMDF123.UINT32)
+#define RSCAN0RMDF123L (RSCAN0.RMDF123.UINT16[R_IO_L])
+#define RSCAN0RMDF123LL (RSCAN0.RMDF123.UINT8[R_IO_LL])
+#define RSCAN0RMDF123LH (RSCAN0.RMDF123.UINT8[R_IO_LH])
+#define RSCAN0RMDF123H (RSCAN0.RMDF123.UINT16[R_IO_H])
+#define RSCAN0RMDF123HL (RSCAN0.RMDF123.UINT8[R_IO_HL])
+#define RSCAN0RMDF123HH (RSCAN0.RMDF123.UINT8[R_IO_HH])
+#define RSCAN0RMID24 (RSCAN0.RMID24.UINT32)
+#define RSCAN0RMID24L (RSCAN0.RMID24.UINT16[R_IO_L])
+#define RSCAN0RMID24LL (RSCAN0.RMID24.UINT8[R_IO_LL])
+#define RSCAN0RMID24LH (RSCAN0.RMID24.UINT8[R_IO_LH])
+#define RSCAN0RMID24H (RSCAN0.RMID24.UINT16[R_IO_H])
+#define RSCAN0RMID24HL (RSCAN0.RMID24.UINT8[R_IO_HL])
+#define RSCAN0RMID24HH (RSCAN0.RMID24.UINT8[R_IO_HH])
+#define RSCAN0RMPTR24 (RSCAN0.RMPTR24.UINT32)
+#define RSCAN0RMPTR24L (RSCAN0.RMPTR24.UINT16[R_IO_L])
+#define RSCAN0RMPTR24LL (RSCAN0.RMPTR24.UINT8[R_IO_LL])
+#define RSCAN0RMPTR24LH (RSCAN0.RMPTR24.UINT8[R_IO_LH])
+#define RSCAN0RMPTR24H (RSCAN0.RMPTR24.UINT16[R_IO_H])
+#define RSCAN0RMPTR24HL (RSCAN0.RMPTR24.UINT8[R_IO_HL])
+#define RSCAN0RMPTR24HH (RSCAN0.RMPTR24.UINT8[R_IO_HH])
+#define RSCAN0RMDF024 (RSCAN0.RMDF024.UINT32)
+#define RSCAN0RMDF024L (RSCAN0.RMDF024.UINT16[R_IO_L])
+#define RSCAN0RMDF024LL (RSCAN0.RMDF024.UINT8[R_IO_LL])
+#define RSCAN0RMDF024LH (RSCAN0.RMDF024.UINT8[R_IO_LH])
+#define RSCAN0RMDF024H (RSCAN0.RMDF024.UINT16[R_IO_H])
+#define RSCAN0RMDF024HL (RSCAN0.RMDF024.UINT8[R_IO_HL])
+#define RSCAN0RMDF024HH (RSCAN0.RMDF024.UINT8[R_IO_HH])
+#define RSCAN0RMDF124 (RSCAN0.RMDF124.UINT32)
+#define RSCAN0RMDF124L (RSCAN0.RMDF124.UINT16[R_IO_L])
+#define RSCAN0RMDF124LL (RSCAN0.RMDF124.UINT8[R_IO_LL])
+#define RSCAN0RMDF124LH (RSCAN0.RMDF124.UINT8[R_IO_LH])
+#define RSCAN0RMDF124H (RSCAN0.RMDF124.UINT16[R_IO_H])
+#define RSCAN0RMDF124HL (RSCAN0.RMDF124.UINT8[R_IO_HL])
+#define RSCAN0RMDF124HH (RSCAN0.RMDF124.UINT8[R_IO_HH])
+#define RSCAN0RMID25 (RSCAN0.RMID25.UINT32)
+#define RSCAN0RMID25L (RSCAN0.RMID25.UINT16[R_IO_L])
+#define RSCAN0RMID25LL (RSCAN0.RMID25.UINT8[R_IO_LL])
+#define RSCAN0RMID25LH (RSCAN0.RMID25.UINT8[R_IO_LH])
+#define RSCAN0RMID25H (RSCAN0.RMID25.UINT16[R_IO_H])
+#define RSCAN0RMID25HL (RSCAN0.RMID25.UINT8[R_IO_HL])
+#define RSCAN0RMID25HH (RSCAN0.RMID25.UINT8[R_IO_HH])
+#define RSCAN0RMPTR25 (RSCAN0.RMPTR25.UINT32)
+#define RSCAN0RMPTR25L (RSCAN0.RMPTR25.UINT16[R_IO_L])
+#define RSCAN0RMPTR25LL (RSCAN0.RMPTR25.UINT8[R_IO_LL])
+#define RSCAN0RMPTR25LH (RSCAN0.RMPTR25.UINT8[R_IO_LH])
+#define RSCAN0RMPTR25H (RSCAN0.RMPTR25.UINT16[R_IO_H])
+#define RSCAN0RMPTR25HL (RSCAN0.RMPTR25.UINT8[R_IO_HL])
+#define RSCAN0RMPTR25HH (RSCAN0.RMPTR25.UINT8[R_IO_HH])
+#define RSCAN0RMDF025 (RSCAN0.RMDF025.UINT32)
+#define RSCAN0RMDF025L (RSCAN0.RMDF025.UINT16[R_IO_L])
+#define RSCAN0RMDF025LL (RSCAN0.RMDF025.UINT8[R_IO_LL])
+#define RSCAN0RMDF025LH (RSCAN0.RMDF025.UINT8[R_IO_LH])
+#define RSCAN0RMDF025H (RSCAN0.RMDF025.UINT16[R_IO_H])
+#define RSCAN0RMDF025HL (RSCAN0.RMDF025.UINT8[R_IO_HL])
+#define RSCAN0RMDF025HH (RSCAN0.RMDF025.UINT8[R_IO_HH])
+#define RSCAN0RMDF125 (RSCAN0.RMDF125.UINT32)
+#define RSCAN0RMDF125L (RSCAN0.RMDF125.UINT16[R_IO_L])
+#define RSCAN0RMDF125LL (RSCAN0.RMDF125.UINT8[R_IO_LL])
+#define RSCAN0RMDF125LH (RSCAN0.RMDF125.UINT8[R_IO_LH])
+#define RSCAN0RMDF125H (RSCAN0.RMDF125.UINT16[R_IO_H])
+#define RSCAN0RMDF125HL (RSCAN0.RMDF125.UINT8[R_IO_HL])
+#define RSCAN0RMDF125HH (RSCAN0.RMDF125.UINT8[R_IO_HH])
+#define RSCAN0RMID26 (RSCAN0.RMID26.UINT32)
+#define RSCAN0RMID26L (RSCAN0.RMID26.UINT16[R_IO_L])
+#define RSCAN0RMID26LL (RSCAN0.RMID26.UINT8[R_IO_LL])
+#define RSCAN0RMID26LH (RSCAN0.RMID26.UINT8[R_IO_LH])
+#define RSCAN0RMID26H (RSCAN0.RMID26.UINT16[R_IO_H])
+#define RSCAN0RMID26HL (RSCAN0.RMID26.UINT8[R_IO_HL])
+#define RSCAN0RMID26HH (RSCAN0.RMID26.UINT8[R_IO_HH])
+#define RSCAN0RMPTR26 (RSCAN0.RMPTR26.UINT32)
+#define RSCAN0RMPTR26L (RSCAN0.RMPTR26.UINT16[R_IO_L])
+#define RSCAN0RMPTR26LL (RSCAN0.RMPTR26.UINT8[R_IO_LL])
+#define RSCAN0RMPTR26LH (RSCAN0.RMPTR26.UINT8[R_IO_LH])
+#define RSCAN0RMPTR26H (RSCAN0.RMPTR26.UINT16[R_IO_H])
+#define RSCAN0RMPTR26HL (RSCAN0.RMPTR26.UINT8[R_IO_HL])
+#define RSCAN0RMPTR26HH (RSCAN0.RMPTR26.UINT8[R_IO_HH])
+#define RSCAN0RMDF026 (RSCAN0.RMDF026.UINT32)
+#define RSCAN0RMDF026L (RSCAN0.RMDF026.UINT16[R_IO_L])
+#define RSCAN0RMDF026LL (RSCAN0.RMDF026.UINT8[R_IO_LL])
+#define RSCAN0RMDF026LH (RSCAN0.RMDF026.UINT8[R_IO_LH])
+#define RSCAN0RMDF026H (RSCAN0.RMDF026.UINT16[R_IO_H])
+#define RSCAN0RMDF026HL (RSCAN0.RMDF026.UINT8[R_IO_HL])
+#define RSCAN0RMDF026HH (RSCAN0.RMDF026.UINT8[R_IO_HH])
+#define RSCAN0RMDF126 (RSCAN0.RMDF126.UINT32)
+#define RSCAN0RMDF126L (RSCAN0.RMDF126.UINT16[R_IO_L])
+#define RSCAN0RMDF126LL (RSCAN0.RMDF126.UINT8[R_IO_LL])
+#define RSCAN0RMDF126LH (RSCAN0.RMDF126.UINT8[R_IO_LH])
+#define RSCAN0RMDF126H (RSCAN0.RMDF126.UINT16[R_IO_H])
+#define RSCAN0RMDF126HL (RSCAN0.RMDF126.UINT8[R_IO_HL])
+#define RSCAN0RMDF126HH (RSCAN0.RMDF126.UINT8[R_IO_HH])
+#define RSCAN0RMID27 (RSCAN0.RMID27.UINT32)
+#define RSCAN0RMID27L (RSCAN0.RMID27.UINT16[R_IO_L])
+#define RSCAN0RMID27LL (RSCAN0.RMID27.UINT8[R_IO_LL])
+#define RSCAN0RMID27LH (RSCAN0.RMID27.UINT8[R_IO_LH])
+#define RSCAN0RMID27H (RSCAN0.RMID27.UINT16[R_IO_H])
+#define RSCAN0RMID27HL (RSCAN0.RMID27.UINT8[R_IO_HL])
+#define RSCAN0RMID27HH (RSCAN0.RMID27.UINT8[R_IO_HH])
+#define RSCAN0RMPTR27 (RSCAN0.RMPTR27.UINT32)
+#define RSCAN0RMPTR27L (RSCAN0.RMPTR27.UINT16[R_IO_L])
+#define RSCAN0RMPTR27LL (RSCAN0.RMPTR27.UINT8[R_IO_LL])
+#define RSCAN0RMPTR27LH (RSCAN0.RMPTR27.UINT8[R_IO_LH])
+#define RSCAN0RMPTR27H (RSCAN0.RMPTR27.UINT16[R_IO_H])
+#define RSCAN0RMPTR27HL (RSCAN0.RMPTR27.UINT8[R_IO_HL])
+#define RSCAN0RMPTR27HH (RSCAN0.RMPTR27.UINT8[R_IO_HH])
+#define RSCAN0RMDF027 (RSCAN0.RMDF027.UINT32)
+#define RSCAN0RMDF027L (RSCAN0.RMDF027.UINT16[R_IO_L])
+#define RSCAN0RMDF027LL (RSCAN0.RMDF027.UINT8[R_IO_LL])
+#define RSCAN0RMDF027LH (RSCAN0.RMDF027.UINT8[R_IO_LH])
+#define RSCAN0RMDF027H (RSCAN0.RMDF027.UINT16[R_IO_H])
+#define RSCAN0RMDF027HL (RSCAN0.RMDF027.UINT8[R_IO_HL])
+#define RSCAN0RMDF027HH (RSCAN0.RMDF027.UINT8[R_IO_HH])
+#define RSCAN0RMDF127 (RSCAN0.RMDF127.UINT32)
+#define RSCAN0RMDF127L (RSCAN0.RMDF127.UINT16[R_IO_L])
+#define RSCAN0RMDF127LL (RSCAN0.RMDF127.UINT8[R_IO_LL])
+#define RSCAN0RMDF127LH (RSCAN0.RMDF127.UINT8[R_IO_LH])
+#define RSCAN0RMDF127H (RSCAN0.RMDF127.UINT16[R_IO_H])
+#define RSCAN0RMDF127HL (RSCAN0.RMDF127.UINT8[R_IO_HL])
+#define RSCAN0RMDF127HH (RSCAN0.RMDF127.UINT8[R_IO_HH])
+#define RSCAN0RMID28 (RSCAN0.RMID28.UINT32)
+#define RSCAN0RMID28L (RSCAN0.RMID28.UINT16[R_IO_L])
+#define RSCAN0RMID28LL (RSCAN0.RMID28.UINT8[R_IO_LL])
+#define RSCAN0RMID28LH (RSCAN0.RMID28.UINT8[R_IO_LH])
+#define RSCAN0RMID28H (RSCAN0.RMID28.UINT16[R_IO_H])
+#define RSCAN0RMID28HL (RSCAN0.RMID28.UINT8[R_IO_HL])
+#define RSCAN0RMID28HH (RSCAN0.RMID28.UINT8[R_IO_HH])
+#define RSCAN0RMPTR28 (RSCAN0.RMPTR28.UINT32)
+#define RSCAN0RMPTR28L (RSCAN0.RMPTR28.UINT16[R_IO_L])
+#define RSCAN0RMPTR28LL (RSCAN0.RMPTR28.UINT8[R_IO_LL])
+#define RSCAN0RMPTR28LH (RSCAN0.RMPTR28.UINT8[R_IO_LH])
+#define RSCAN0RMPTR28H (RSCAN0.RMPTR28.UINT16[R_IO_H])
+#define RSCAN0RMPTR28HL (RSCAN0.RMPTR28.UINT8[R_IO_HL])
+#define RSCAN0RMPTR28HH (RSCAN0.RMPTR28.UINT8[R_IO_HH])
+#define RSCAN0RMDF028 (RSCAN0.RMDF028.UINT32)
+#define RSCAN0RMDF028L (RSCAN0.RMDF028.UINT16[R_IO_L])
+#define RSCAN0RMDF028LL (RSCAN0.RMDF028.UINT8[R_IO_LL])
+#define RSCAN0RMDF028LH (RSCAN0.RMDF028.UINT8[R_IO_LH])
+#define RSCAN0RMDF028H (RSCAN0.RMDF028.UINT16[R_IO_H])
+#define RSCAN0RMDF028HL (RSCAN0.RMDF028.UINT8[R_IO_HL])
+#define RSCAN0RMDF028HH (RSCAN0.RMDF028.UINT8[R_IO_HH])
+#define RSCAN0RMDF128 (RSCAN0.RMDF128.UINT32)
+#define RSCAN0RMDF128L (RSCAN0.RMDF128.UINT16[R_IO_L])
+#define RSCAN0RMDF128LL (RSCAN0.RMDF128.UINT8[R_IO_LL])
+#define RSCAN0RMDF128LH (RSCAN0.RMDF128.UINT8[R_IO_LH])
+#define RSCAN0RMDF128H (RSCAN0.RMDF128.UINT16[R_IO_H])
+#define RSCAN0RMDF128HL (RSCAN0.RMDF128.UINT8[R_IO_HL])
+#define RSCAN0RMDF128HH (RSCAN0.RMDF128.UINT8[R_IO_HH])
+#define RSCAN0RMID29 (RSCAN0.RMID29.UINT32)
+#define RSCAN0RMID29L (RSCAN0.RMID29.UINT16[R_IO_L])
+#define RSCAN0RMID29LL (RSCAN0.RMID29.UINT8[R_IO_LL])
+#define RSCAN0RMID29LH (RSCAN0.RMID29.UINT8[R_IO_LH])
+#define RSCAN0RMID29H (RSCAN0.RMID29.UINT16[R_IO_H])
+#define RSCAN0RMID29HL (RSCAN0.RMID29.UINT8[R_IO_HL])
+#define RSCAN0RMID29HH (RSCAN0.RMID29.UINT8[R_IO_HH])
+#define RSCAN0RMPTR29 (RSCAN0.RMPTR29.UINT32)
+#define RSCAN0RMPTR29L (RSCAN0.RMPTR29.UINT16[R_IO_L])
+#define RSCAN0RMPTR29LL (RSCAN0.RMPTR29.UINT8[R_IO_LL])
+#define RSCAN0RMPTR29LH (RSCAN0.RMPTR29.UINT8[R_IO_LH])
+#define RSCAN0RMPTR29H (RSCAN0.RMPTR29.UINT16[R_IO_H])
+#define RSCAN0RMPTR29HL (RSCAN0.RMPTR29.UINT8[R_IO_HL])
+#define RSCAN0RMPTR29HH (RSCAN0.RMPTR29.UINT8[R_IO_HH])
+#define RSCAN0RMDF029 (RSCAN0.RMDF029.UINT32)
+#define RSCAN0RMDF029L (RSCAN0.RMDF029.UINT16[R_IO_L])
+#define RSCAN0RMDF029LL (RSCAN0.RMDF029.UINT8[R_IO_LL])
+#define RSCAN0RMDF029LH (RSCAN0.RMDF029.UINT8[R_IO_LH])
+#define RSCAN0RMDF029H (RSCAN0.RMDF029.UINT16[R_IO_H])
+#define RSCAN0RMDF029HL (RSCAN0.RMDF029.UINT8[R_IO_HL])
+#define RSCAN0RMDF029HH (RSCAN0.RMDF029.UINT8[R_IO_HH])
+#define RSCAN0RMDF129 (RSCAN0.RMDF129.UINT32)
+#define RSCAN0RMDF129L (RSCAN0.RMDF129.UINT16[R_IO_L])
+#define RSCAN0RMDF129LL (RSCAN0.RMDF129.UINT8[R_IO_LL])
+#define RSCAN0RMDF129LH (RSCAN0.RMDF129.UINT8[R_IO_LH])
+#define RSCAN0RMDF129H (RSCAN0.RMDF129.UINT16[R_IO_H])
+#define RSCAN0RMDF129HL (RSCAN0.RMDF129.UINT8[R_IO_HL])
+#define RSCAN0RMDF129HH (RSCAN0.RMDF129.UINT8[R_IO_HH])
+#define RSCAN0RMID30 (RSCAN0.RMID30.UINT32)
+#define RSCAN0RMID30L (RSCAN0.RMID30.UINT16[R_IO_L])
+#define RSCAN0RMID30LL (RSCAN0.RMID30.UINT8[R_IO_LL])
+#define RSCAN0RMID30LH (RSCAN0.RMID30.UINT8[R_IO_LH])
+#define RSCAN0RMID30H (RSCAN0.RMID30.UINT16[R_IO_H])
+#define RSCAN0RMID30HL (RSCAN0.RMID30.UINT8[R_IO_HL])
+#define RSCAN0RMID30HH (RSCAN0.RMID30.UINT8[R_IO_HH])
+#define RSCAN0RMPTR30 (RSCAN0.RMPTR30.UINT32)
+#define RSCAN0RMPTR30L (RSCAN0.RMPTR30.UINT16[R_IO_L])
+#define RSCAN0RMPTR30LL (RSCAN0.RMPTR30.UINT8[R_IO_LL])
+#define RSCAN0RMPTR30LH (RSCAN0.RMPTR30.UINT8[R_IO_LH])
+#define RSCAN0RMPTR30H (RSCAN0.RMPTR30.UINT16[R_IO_H])
+#define RSCAN0RMPTR30HL (RSCAN0.RMPTR30.UINT8[R_IO_HL])
+#define RSCAN0RMPTR30HH (RSCAN0.RMPTR30.UINT8[R_IO_HH])
+#define RSCAN0RMDF030 (RSCAN0.RMDF030.UINT32)
+#define RSCAN0RMDF030L (RSCAN0.RMDF030.UINT16[R_IO_L])
+#define RSCAN0RMDF030LL (RSCAN0.RMDF030.UINT8[R_IO_LL])
+#define RSCAN0RMDF030LH (RSCAN0.RMDF030.UINT8[R_IO_LH])
+#define RSCAN0RMDF030H (RSCAN0.RMDF030.UINT16[R_IO_H])
+#define RSCAN0RMDF030HL (RSCAN0.RMDF030.UINT8[R_IO_HL])
+#define RSCAN0RMDF030HH (RSCAN0.RMDF030.UINT8[R_IO_HH])
+#define RSCAN0RMDF130 (RSCAN0.RMDF130.UINT32)
+#define RSCAN0RMDF130L (RSCAN0.RMDF130.UINT16[R_IO_L])
+#define RSCAN0RMDF130LL (RSCAN0.RMDF130.UINT8[R_IO_LL])
+#define RSCAN0RMDF130LH (RSCAN0.RMDF130.UINT8[R_IO_LH])
+#define RSCAN0RMDF130H (RSCAN0.RMDF130.UINT16[R_IO_H])
+#define RSCAN0RMDF130HL (RSCAN0.RMDF130.UINT8[R_IO_HL])
+#define RSCAN0RMDF130HH (RSCAN0.RMDF130.UINT8[R_IO_HH])
+#define RSCAN0RMID31 (RSCAN0.RMID31.UINT32)
+#define RSCAN0RMID31L (RSCAN0.RMID31.UINT16[R_IO_L])
+#define RSCAN0RMID31LL (RSCAN0.RMID31.UINT8[R_IO_LL])
+#define RSCAN0RMID31LH (RSCAN0.RMID31.UINT8[R_IO_LH])
+#define RSCAN0RMID31H (RSCAN0.RMID31.UINT16[R_IO_H])
+#define RSCAN0RMID31HL (RSCAN0.RMID31.UINT8[R_IO_HL])
+#define RSCAN0RMID31HH (RSCAN0.RMID31.UINT8[R_IO_HH])
+#define RSCAN0RMPTR31 (RSCAN0.RMPTR31.UINT32)
+#define RSCAN0RMPTR31L (RSCAN0.RMPTR31.UINT16[R_IO_L])
+#define RSCAN0RMPTR31LL (RSCAN0.RMPTR31.UINT8[R_IO_LL])
+#define RSCAN0RMPTR31LH (RSCAN0.RMPTR31.UINT8[R_IO_LH])
+#define RSCAN0RMPTR31H (RSCAN0.RMPTR31.UINT16[R_IO_H])
+#define RSCAN0RMPTR31HL (RSCAN0.RMPTR31.UINT8[R_IO_HL])
+#define RSCAN0RMPTR31HH (RSCAN0.RMPTR31.UINT8[R_IO_HH])
+#define RSCAN0RMDF031 (RSCAN0.RMDF031.UINT32)
+#define RSCAN0RMDF031L (RSCAN0.RMDF031.UINT16[R_IO_L])
+#define RSCAN0RMDF031LL (RSCAN0.RMDF031.UINT8[R_IO_LL])
+#define RSCAN0RMDF031LH (RSCAN0.RMDF031.UINT8[R_IO_LH])
+#define RSCAN0RMDF031H (RSCAN0.RMDF031.UINT16[R_IO_H])
+#define RSCAN0RMDF031HL (RSCAN0.RMDF031.UINT8[R_IO_HL])
+#define RSCAN0RMDF031HH (RSCAN0.RMDF031.UINT8[R_IO_HH])
+#define RSCAN0RMDF131 (RSCAN0.RMDF131.UINT32)
+#define RSCAN0RMDF131L (RSCAN0.RMDF131.UINT16[R_IO_L])
+#define RSCAN0RMDF131LL (RSCAN0.RMDF131.UINT8[R_IO_LL])
+#define RSCAN0RMDF131LH (RSCAN0.RMDF131.UINT8[R_IO_LH])
+#define RSCAN0RMDF131H (RSCAN0.RMDF131.UINT16[R_IO_H])
+#define RSCAN0RMDF131HL (RSCAN0.RMDF131.UINT8[R_IO_HL])
+#define RSCAN0RMDF131HH (RSCAN0.RMDF131.UINT8[R_IO_HH])
+#define RSCAN0RMID32 (RSCAN0.RMID32.UINT32)
+#define RSCAN0RMID32L (RSCAN0.RMID32.UINT16[R_IO_L])
+#define RSCAN0RMID32LL (RSCAN0.RMID32.UINT8[R_IO_LL])
+#define RSCAN0RMID32LH (RSCAN0.RMID32.UINT8[R_IO_LH])
+#define RSCAN0RMID32H (RSCAN0.RMID32.UINT16[R_IO_H])
+#define RSCAN0RMID32HL (RSCAN0.RMID32.UINT8[R_IO_HL])
+#define RSCAN0RMID32HH (RSCAN0.RMID32.UINT8[R_IO_HH])
+#define RSCAN0RMPTR32 (RSCAN0.RMPTR32.UINT32)
+#define RSCAN0RMPTR32L (RSCAN0.RMPTR32.UINT16[R_IO_L])
+#define RSCAN0RMPTR32LL (RSCAN0.RMPTR32.UINT8[R_IO_LL])
+#define RSCAN0RMPTR32LH (RSCAN0.RMPTR32.UINT8[R_IO_LH])
+#define RSCAN0RMPTR32H (RSCAN0.RMPTR32.UINT16[R_IO_H])
+#define RSCAN0RMPTR32HL (RSCAN0.RMPTR32.UINT8[R_IO_HL])
+#define RSCAN0RMPTR32HH (RSCAN0.RMPTR32.UINT8[R_IO_HH])
+#define RSCAN0RMDF032 (RSCAN0.RMDF032.UINT32)
+#define RSCAN0RMDF032L (RSCAN0.RMDF032.UINT16[R_IO_L])
+#define RSCAN0RMDF032LL (RSCAN0.RMDF032.UINT8[R_IO_LL])
+#define RSCAN0RMDF032LH (RSCAN0.RMDF032.UINT8[R_IO_LH])
+#define RSCAN0RMDF032H (RSCAN0.RMDF032.UINT16[R_IO_H])
+#define RSCAN0RMDF032HL (RSCAN0.RMDF032.UINT8[R_IO_HL])
+#define RSCAN0RMDF032HH (RSCAN0.RMDF032.UINT8[R_IO_HH])
+#define RSCAN0RMDF132 (RSCAN0.RMDF132.UINT32)
+#define RSCAN0RMDF132L (RSCAN0.RMDF132.UINT16[R_IO_L])
+#define RSCAN0RMDF132LL (RSCAN0.RMDF132.UINT8[R_IO_LL])
+#define RSCAN0RMDF132LH (RSCAN0.RMDF132.UINT8[R_IO_LH])
+#define RSCAN0RMDF132H (RSCAN0.RMDF132.UINT16[R_IO_H])
+#define RSCAN0RMDF132HL (RSCAN0.RMDF132.UINT8[R_IO_HL])
+#define RSCAN0RMDF132HH (RSCAN0.RMDF132.UINT8[R_IO_HH])
+#define RSCAN0RMID33 (RSCAN0.RMID33.UINT32)
+#define RSCAN0RMID33L (RSCAN0.RMID33.UINT16[R_IO_L])
+#define RSCAN0RMID33LL (RSCAN0.RMID33.UINT8[R_IO_LL])
+#define RSCAN0RMID33LH (RSCAN0.RMID33.UINT8[R_IO_LH])
+#define RSCAN0RMID33H (RSCAN0.RMID33.UINT16[R_IO_H])
+#define RSCAN0RMID33HL (RSCAN0.RMID33.UINT8[R_IO_HL])
+#define RSCAN0RMID33HH (RSCAN0.RMID33.UINT8[R_IO_HH])
+#define RSCAN0RMPTR33 (RSCAN0.RMPTR33.UINT32)
+#define RSCAN0RMPTR33L (RSCAN0.RMPTR33.UINT16[R_IO_L])
+#define RSCAN0RMPTR33LL (RSCAN0.RMPTR33.UINT8[R_IO_LL])
+#define RSCAN0RMPTR33LH (RSCAN0.RMPTR33.UINT8[R_IO_LH])
+#define RSCAN0RMPTR33H (RSCAN0.RMPTR33.UINT16[R_IO_H])
+#define RSCAN0RMPTR33HL (RSCAN0.RMPTR33.UINT8[R_IO_HL])
+#define RSCAN0RMPTR33HH (RSCAN0.RMPTR33.UINT8[R_IO_HH])
+#define RSCAN0RMDF033 (RSCAN0.RMDF033.UINT32)
+#define RSCAN0RMDF033L (RSCAN0.RMDF033.UINT16[R_IO_L])
+#define RSCAN0RMDF033LL (RSCAN0.RMDF033.UINT8[R_IO_LL])
+#define RSCAN0RMDF033LH (RSCAN0.RMDF033.UINT8[R_IO_LH])
+#define RSCAN0RMDF033H (RSCAN0.RMDF033.UINT16[R_IO_H])
+#define RSCAN0RMDF033HL (RSCAN0.RMDF033.UINT8[R_IO_HL])
+#define RSCAN0RMDF033HH (RSCAN0.RMDF033.UINT8[R_IO_HH])
+#define RSCAN0RMDF133 (RSCAN0.RMDF133.UINT32)
+#define RSCAN0RMDF133L (RSCAN0.RMDF133.UINT16[R_IO_L])
+#define RSCAN0RMDF133LL (RSCAN0.RMDF133.UINT8[R_IO_LL])
+#define RSCAN0RMDF133LH (RSCAN0.RMDF133.UINT8[R_IO_LH])
+#define RSCAN0RMDF133H (RSCAN0.RMDF133.UINT16[R_IO_H])
+#define RSCAN0RMDF133HL (RSCAN0.RMDF133.UINT8[R_IO_HL])
+#define RSCAN0RMDF133HH (RSCAN0.RMDF133.UINT8[R_IO_HH])
+#define RSCAN0RMID34 (RSCAN0.RMID34.UINT32)
+#define RSCAN0RMID34L (RSCAN0.RMID34.UINT16[R_IO_L])
+#define RSCAN0RMID34LL (RSCAN0.RMID34.UINT8[R_IO_LL])
+#define RSCAN0RMID34LH (RSCAN0.RMID34.UINT8[R_IO_LH])
+#define RSCAN0RMID34H (RSCAN0.RMID34.UINT16[R_IO_H])
+#define RSCAN0RMID34HL (RSCAN0.RMID34.UINT8[R_IO_HL])
+#define RSCAN0RMID34HH (RSCAN0.RMID34.UINT8[R_IO_HH])
+#define RSCAN0RMPTR34 (RSCAN0.RMPTR34.UINT32)
+#define RSCAN0RMPTR34L (RSCAN0.RMPTR34.UINT16[R_IO_L])
+#define RSCAN0RMPTR34LL (RSCAN0.RMPTR34.UINT8[R_IO_LL])
+#define RSCAN0RMPTR34LH (RSCAN0.RMPTR34.UINT8[R_IO_LH])
+#define RSCAN0RMPTR34H (RSCAN0.RMPTR34.UINT16[R_IO_H])
+#define RSCAN0RMPTR34HL (RSCAN0.RMPTR34.UINT8[R_IO_HL])
+#define RSCAN0RMPTR34HH (RSCAN0.RMPTR34.UINT8[R_IO_HH])
+#define RSCAN0RMDF034 (RSCAN0.RMDF034.UINT32)
+#define RSCAN0RMDF034L (RSCAN0.RMDF034.UINT16[R_IO_L])
+#define RSCAN0RMDF034LL (RSCAN0.RMDF034.UINT8[R_IO_LL])
+#define RSCAN0RMDF034LH (RSCAN0.RMDF034.UINT8[R_IO_LH])
+#define RSCAN0RMDF034H (RSCAN0.RMDF034.UINT16[R_IO_H])
+#define RSCAN0RMDF034HL (RSCAN0.RMDF034.UINT8[R_IO_HL])
+#define RSCAN0RMDF034HH (RSCAN0.RMDF034.UINT8[R_IO_HH])
+#define RSCAN0RMDF134 (RSCAN0.RMDF134.UINT32)
+#define RSCAN0RMDF134L (RSCAN0.RMDF134.UINT16[R_IO_L])
+#define RSCAN0RMDF134LL (RSCAN0.RMDF134.UINT8[R_IO_LL])
+#define RSCAN0RMDF134LH (RSCAN0.RMDF134.UINT8[R_IO_LH])
+#define RSCAN0RMDF134H (RSCAN0.RMDF134.UINT16[R_IO_H])
+#define RSCAN0RMDF134HL (RSCAN0.RMDF134.UINT8[R_IO_HL])
+#define RSCAN0RMDF134HH (RSCAN0.RMDF134.UINT8[R_IO_HH])
+#define RSCAN0RMID35 (RSCAN0.RMID35.UINT32)
+#define RSCAN0RMID35L (RSCAN0.RMID35.UINT16[R_IO_L])
+#define RSCAN0RMID35LL (RSCAN0.RMID35.UINT8[R_IO_LL])
+#define RSCAN0RMID35LH (RSCAN0.RMID35.UINT8[R_IO_LH])
+#define RSCAN0RMID35H (RSCAN0.RMID35.UINT16[R_IO_H])
+#define RSCAN0RMID35HL (RSCAN0.RMID35.UINT8[R_IO_HL])
+#define RSCAN0RMID35HH (RSCAN0.RMID35.UINT8[R_IO_HH])
+#define RSCAN0RMPTR35 (RSCAN0.RMPTR35.UINT32)
+#define RSCAN0RMPTR35L (RSCAN0.RMPTR35.UINT16[R_IO_L])
+#define RSCAN0RMPTR35LL (RSCAN0.RMPTR35.UINT8[R_IO_LL])
+#define RSCAN0RMPTR35LH (RSCAN0.RMPTR35.UINT8[R_IO_LH])
+#define RSCAN0RMPTR35H (RSCAN0.RMPTR35.UINT16[R_IO_H])
+#define RSCAN0RMPTR35HL (RSCAN0.RMPTR35.UINT8[R_IO_HL])
+#define RSCAN0RMPTR35HH (RSCAN0.RMPTR35.UINT8[R_IO_HH])
+#define RSCAN0RMDF035 (RSCAN0.RMDF035.UINT32)
+#define RSCAN0RMDF035L (RSCAN0.RMDF035.UINT16[R_IO_L])
+#define RSCAN0RMDF035LL (RSCAN0.RMDF035.UINT8[R_IO_LL])
+#define RSCAN0RMDF035LH (RSCAN0.RMDF035.UINT8[R_IO_LH])
+#define RSCAN0RMDF035H (RSCAN0.RMDF035.UINT16[R_IO_H])
+#define RSCAN0RMDF035HL (RSCAN0.RMDF035.UINT8[R_IO_HL])
+#define RSCAN0RMDF035HH (RSCAN0.RMDF035.UINT8[R_IO_HH])
+#define RSCAN0RMDF135 (RSCAN0.RMDF135.UINT32)
+#define RSCAN0RMDF135L (RSCAN0.RMDF135.UINT16[R_IO_L])
+#define RSCAN0RMDF135LL (RSCAN0.RMDF135.UINT8[R_IO_LL])
+#define RSCAN0RMDF135LH (RSCAN0.RMDF135.UINT8[R_IO_LH])
+#define RSCAN0RMDF135H (RSCAN0.RMDF135.UINT16[R_IO_H])
+#define RSCAN0RMDF135HL (RSCAN0.RMDF135.UINT8[R_IO_HL])
+#define RSCAN0RMDF135HH (RSCAN0.RMDF135.UINT8[R_IO_HH])
+#define RSCAN0RMID36 (RSCAN0.RMID36.UINT32)
+#define RSCAN0RMID36L (RSCAN0.RMID36.UINT16[R_IO_L])
+#define RSCAN0RMID36LL (RSCAN0.RMID36.UINT8[R_IO_LL])
+#define RSCAN0RMID36LH (RSCAN0.RMID36.UINT8[R_IO_LH])
+#define RSCAN0RMID36H (RSCAN0.RMID36.UINT16[R_IO_H])
+#define RSCAN0RMID36HL (RSCAN0.RMID36.UINT8[R_IO_HL])
+#define RSCAN0RMID36HH (RSCAN0.RMID36.UINT8[R_IO_HH])
+#define RSCAN0RMPTR36 (RSCAN0.RMPTR36.UINT32)
+#define RSCAN0RMPTR36L (RSCAN0.RMPTR36.UINT16[R_IO_L])
+#define RSCAN0RMPTR36LL (RSCAN0.RMPTR36.UINT8[R_IO_LL])
+#define RSCAN0RMPTR36LH (RSCAN0.RMPTR36.UINT8[R_IO_LH])
+#define RSCAN0RMPTR36H (RSCAN0.RMPTR36.UINT16[R_IO_H])
+#define RSCAN0RMPTR36HL (RSCAN0.RMPTR36.UINT8[R_IO_HL])
+#define RSCAN0RMPTR36HH (RSCAN0.RMPTR36.UINT8[R_IO_HH])
+#define RSCAN0RMDF036 (RSCAN0.RMDF036.UINT32)
+#define RSCAN0RMDF036L (RSCAN0.RMDF036.UINT16[R_IO_L])
+#define RSCAN0RMDF036LL (RSCAN0.RMDF036.UINT8[R_IO_LL])
+#define RSCAN0RMDF036LH (RSCAN0.RMDF036.UINT8[R_IO_LH])
+#define RSCAN0RMDF036H (RSCAN0.RMDF036.UINT16[R_IO_H])
+#define RSCAN0RMDF036HL (RSCAN0.RMDF036.UINT8[R_IO_HL])
+#define RSCAN0RMDF036HH (RSCAN0.RMDF036.UINT8[R_IO_HH])
+#define RSCAN0RMDF136 (RSCAN0.RMDF136.UINT32)
+#define RSCAN0RMDF136L (RSCAN0.RMDF136.UINT16[R_IO_L])
+#define RSCAN0RMDF136LL (RSCAN0.RMDF136.UINT8[R_IO_LL])
+#define RSCAN0RMDF136LH (RSCAN0.RMDF136.UINT8[R_IO_LH])
+#define RSCAN0RMDF136H (RSCAN0.RMDF136.UINT16[R_IO_H])
+#define RSCAN0RMDF136HL (RSCAN0.RMDF136.UINT8[R_IO_HL])
+#define RSCAN0RMDF136HH (RSCAN0.RMDF136.UINT8[R_IO_HH])
+#define RSCAN0RMID37 (RSCAN0.RMID37.UINT32)
+#define RSCAN0RMID37L (RSCAN0.RMID37.UINT16[R_IO_L])
+#define RSCAN0RMID37LL (RSCAN0.RMID37.UINT8[R_IO_LL])
+#define RSCAN0RMID37LH (RSCAN0.RMID37.UINT8[R_IO_LH])
+#define RSCAN0RMID37H (RSCAN0.RMID37.UINT16[R_IO_H])
+#define RSCAN0RMID37HL (RSCAN0.RMID37.UINT8[R_IO_HL])
+#define RSCAN0RMID37HH (RSCAN0.RMID37.UINT8[R_IO_HH])
+#define RSCAN0RMPTR37 (RSCAN0.RMPTR37.UINT32)
+#define RSCAN0RMPTR37L (RSCAN0.RMPTR37.UINT16[R_IO_L])
+#define RSCAN0RMPTR37LL (RSCAN0.RMPTR37.UINT8[R_IO_LL])
+#define RSCAN0RMPTR37LH (RSCAN0.RMPTR37.UINT8[R_IO_LH])
+#define RSCAN0RMPTR37H (RSCAN0.RMPTR37.UINT16[R_IO_H])
+#define RSCAN0RMPTR37HL (RSCAN0.RMPTR37.UINT8[R_IO_HL])
+#define RSCAN0RMPTR37HH (RSCAN0.RMPTR37.UINT8[R_IO_HH])
+#define RSCAN0RMDF037 (RSCAN0.RMDF037.UINT32)
+#define RSCAN0RMDF037L (RSCAN0.RMDF037.UINT16[R_IO_L])
+#define RSCAN0RMDF037LL (RSCAN0.RMDF037.UINT8[R_IO_LL])
+#define RSCAN0RMDF037LH (RSCAN0.RMDF037.UINT8[R_IO_LH])
+#define RSCAN0RMDF037H (RSCAN0.RMDF037.UINT16[R_IO_H])
+#define RSCAN0RMDF037HL (RSCAN0.RMDF037.UINT8[R_IO_HL])
+#define RSCAN0RMDF037HH (RSCAN0.RMDF037.UINT8[R_IO_HH])
+#define RSCAN0RMDF137 (RSCAN0.RMDF137.UINT32)
+#define RSCAN0RMDF137L (RSCAN0.RMDF137.UINT16[R_IO_L])
+#define RSCAN0RMDF137LL (RSCAN0.RMDF137.UINT8[R_IO_LL])
+#define RSCAN0RMDF137LH (RSCAN0.RMDF137.UINT8[R_IO_LH])
+#define RSCAN0RMDF137H (RSCAN0.RMDF137.UINT16[R_IO_H])
+#define RSCAN0RMDF137HL (RSCAN0.RMDF137.UINT8[R_IO_HL])
+#define RSCAN0RMDF137HH (RSCAN0.RMDF137.UINT8[R_IO_HH])
+#define RSCAN0RMID38 (RSCAN0.RMID38.UINT32)
+#define RSCAN0RMID38L (RSCAN0.RMID38.UINT16[R_IO_L])
+#define RSCAN0RMID38LL (RSCAN0.RMID38.UINT8[R_IO_LL])
+#define RSCAN0RMID38LH (RSCAN0.RMID38.UINT8[R_IO_LH])
+#define RSCAN0RMID38H (RSCAN0.RMID38.UINT16[R_IO_H])
+#define RSCAN0RMID38HL (RSCAN0.RMID38.UINT8[R_IO_HL])
+#define RSCAN0RMID38HH (RSCAN0.RMID38.UINT8[R_IO_HH])
+#define RSCAN0RMPTR38 (RSCAN0.RMPTR38.UINT32)
+#define RSCAN0RMPTR38L (RSCAN0.RMPTR38.UINT16[R_IO_L])
+#define RSCAN0RMPTR38LL (RSCAN0.RMPTR38.UINT8[R_IO_LL])
+#define RSCAN0RMPTR38LH (RSCAN0.RMPTR38.UINT8[R_IO_LH])
+#define RSCAN0RMPTR38H (RSCAN0.RMPTR38.UINT16[R_IO_H])
+#define RSCAN0RMPTR38HL (RSCAN0.RMPTR38.UINT8[R_IO_HL])
+#define RSCAN0RMPTR38HH (RSCAN0.RMPTR38.UINT8[R_IO_HH])
+#define RSCAN0RMDF038 (RSCAN0.RMDF038.UINT32)
+#define RSCAN0RMDF038L (RSCAN0.RMDF038.UINT16[R_IO_L])
+#define RSCAN0RMDF038LL (RSCAN0.RMDF038.UINT8[R_IO_LL])
+#define RSCAN0RMDF038LH (RSCAN0.RMDF038.UINT8[R_IO_LH])
+#define RSCAN0RMDF038H (RSCAN0.RMDF038.UINT16[R_IO_H])
+#define RSCAN0RMDF038HL (RSCAN0.RMDF038.UINT8[R_IO_HL])
+#define RSCAN0RMDF038HH (RSCAN0.RMDF038.UINT8[R_IO_HH])
+#define RSCAN0RMDF138 (RSCAN0.RMDF138.UINT32)
+#define RSCAN0RMDF138L (RSCAN0.RMDF138.UINT16[R_IO_L])
+#define RSCAN0RMDF138LL (RSCAN0.RMDF138.UINT8[R_IO_LL])
+#define RSCAN0RMDF138LH (RSCAN0.RMDF138.UINT8[R_IO_LH])
+#define RSCAN0RMDF138H (RSCAN0.RMDF138.UINT16[R_IO_H])
+#define RSCAN0RMDF138HL (RSCAN0.RMDF138.UINT8[R_IO_HL])
+#define RSCAN0RMDF138HH (RSCAN0.RMDF138.UINT8[R_IO_HH])
+#define RSCAN0RMID39 (RSCAN0.RMID39.UINT32)
+#define RSCAN0RMID39L (RSCAN0.RMID39.UINT16[R_IO_L])
+#define RSCAN0RMID39LL (RSCAN0.RMID39.UINT8[R_IO_LL])
+#define RSCAN0RMID39LH (RSCAN0.RMID39.UINT8[R_IO_LH])
+#define RSCAN0RMID39H (RSCAN0.RMID39.UINT16[R_IO_H])
+#define RSCAN0RMID39HL (RSCAN0.RMID39.UINT8[R_IO_HL])
+#define RSCAN0RMID39HH (RSCAN0.RMID39.UINT8[R_IO_HH])
+#define RSCAN0RMPTR39 (RSCAN0.RMPTR39.UINT32)
+#define RSCAN0RMPTR39L (RSCAN0.RMPTR39.UINT16[R_IO_L])
+#define RSCAN0RMPTR39LL (RSCAN0.RMPTR39.UINT8[R_IO_LL])
+#define RSCAN0RMPTR39LH (RSCAN0.RMPTR39.UINT8[R_IO_LH])
+#define RSCAN0RMPTR39H (RSCAN0.RMPTR39.UINT16[R_IO_H])
+#define RSCAN0RMPTR39HL (RSCAN0.RMPTR39.UINT8[R_IO_HL])
+#define RSCAN0RMPTR39HH (RSCAN0.RMPTR39.UINT8[R_IO_HH])
+#define RSCAN0RMDF039 (RSCAN0.RMDF039.UINT32)
+#define RSCAN0RMDF039L (RSCAN0.RMDF039.UINT16[R_IO_L])
+#define RSCAN0RMDF039LL (RSCAN0.RMDF039.UINT8[R_IO_LL])
+#define RSCAN0RMDF039LH (RSCAN0.RMDF039.UINT8[R_IO_LH])
+#define RSCAN0RMDF039H (RSCAN0.RMDF039.UINT16[R_IO_H])
+#define RSCAN0RMDF039HL (RSCAN0.RMDF039.UINT8[R_IO_HL])
+#define RSCAN0RMDF039HH (RSCAN0.RMDF039.UINT8[R_IO_HH])
+#define RSCAN0RMDF139 (RSCAN0.RMDF139.UINT32)
+#define RSCAN0RMDF139L (RSCAN0.RMDF139.UINT16[R_IO_L])
+#define RSCAN0RMDF139LL (RSCAN0.RMDF139.UINT8[R_IO_LL])
+#define RSCAN0RMDF139LH (RSCAN0.RMDF139.UINT8[R_IO_LH])
+#define RSCAN0RMDF139H (RSCAN0.RMDF139.UINT16[R_IO_H])
+#define RSCAN0RMDF139HL (RSCAN0.RMDF139.UINT8[R_IO_HL])
+#define RSCAN0RMDF139HH (RSCAN0.RMDF139.UINT8[R_IO_HH])
+#define RSCAN0RMID40 (RSCAN0.RMID40.UINT32)
+#define RSCAN0RMID40L (RSCAN0.RMID40.UINT16[R_IO_L])
+#define RSCAN0RMID40LL (RSCAN0.RMID40.UINT8[R_IO_LL])
+#define RSCAN0RMID40LH (RSCAN0.RMID40.UINT8[R_IO_LH])
+#define RSCAN0RMID40H (RSCAN0.RMID40.UINT16[R_IO_H])
+#define RSCAN0RMID40HL (RSCAN0.RMID40.UINT8[R_IO_HL])
+#define RSCAN0RMID40HH (RSCAN0.RMID40.UINT8[R_IO_HH])
+#define RSCAN0RMPTR40 (RSCAN0.RMPTR40.UINT32)
+#define RSCAN0RMPTR40L (RSCAN0.RMPTR40.UINT16[R_IO_L])
+#define RSCAN0RMPTR40LL (RSCAN0.RMPTR40.UINT8[R_IO_LL])
+#define RSCAN0RMPTR40LH (RSCAN0.RMPTR40.UINT8[R_IO_LH])
+#define RSCAN0RMPTR40H (RSCAN0.RMPTR40.UINT16[R_IO_H])
+#define RSCAN0RMPTR40HL (RSCAN0.RMPTR40.UINT8[R_IO_HL])
+#define RSCAN0RMPTR40HH (RSCAN0.RMPTR40.UINT8[R_IO_HH])
+#define RSCAN0RMDF040 (RSCAN0.RMDF040.UINT32)
+#define RSCAN0RMDF040L (RSCAN0.RMDF040.UINT16[R_IO_L])
+#define RSCAN0RMDF040LL (RSCAN0.RMDF040.UINT8[R_IO_LL])
+#define RSCAN0RMDF040LH (RSCAN0.RMDF040.UINT8[R_IO_LH])
+#define RSCAN0RMDF040H (RSCAN0.RMDF040.UINT16[R_IO_H])
+#define RSCAN0RMDF040HL (RSCAN0.RMDF040.UINT8[R_IO_HL])
+#define RSCAN0RMDF040HH (RSCAN0.RMDF040.UINT8[R_IO_HH])
+#define RSCAN0RMDF140 (RSCAN0.RMDF140.UINT32)
+#define RSCAN0RMDF140L (RSCAN0.RMDF140.UINT16[R_IO_L])
+#define RSCAN0RMDF140LL (RSCAN0.RMDF140.UINT8[R_IO_LL])
+#define RSCAN0RMDF140LH (RSCAN0.RMDF140.UINT8[R_IO_LH])
+#define RSCAN0RMDF140H (RSCAN0.RMDF140.UINT16[R_IO_H])
+#define RSCAN0RMDF140HL (RSCAN0.RMDF140.UINT8[R_IO_HL])
+#define RSCAN0RMDF140HH (RSCAN0.RMDF140.UINT8[R_IO_HH])
+#define RSCAN0RMID41 (RSCAN0.RMID41.UINT32)
+#define RSCAN0RMID41L (RSCAN0.RMID41.UINT16[R_IO_L])
+#define RSCAN0RMID41LL (RSCAN0.RMID41.UINT8[R_IO_LL])
+#define RSCAN0RMID41LH (RSCAN0.RMID41.UINT8[R_IO_LH])
+#define RSCAN0RMID41H (RSCAN0.RMID41.UINT16[R_IO_H])
+#define RSCAN0RMID41HL (RSCAN0.RMID41.UINT8[R_IO_HL])
+#define RSCAN0RMID41HH (RSCAN0.RMID41.UINT8[R_IO_HH])
+#define RSCAN0RMPTR41 (RSCAN0.RMPTR41.UINT32)
+#define RSCAN0RMPTR41L (RSCAN0.RMPTR41.UINT16[R_IO_L])
+#define RSCAN0RMPTR41LL (RSCAN0.RMPTR41.UINT8[R_IO_LL])
+#define RSCAN0RMPTR41LH (RSCAN0.RMPTR41.UINT8[R_IO_LH])
+#define RSCAN0RMPTR41H (RSCAN0.RMPTR41.UINT16[R_IO_H])
+#define RSCAN0RMPTR41HL (RSCAN0.RMPTR41.UINT8[R_IO_HL])
+#define RSCAN0RMPTR41HH (RSCAN0.RMPTR41.UINT8[R_IO_HH])
+#define RSCAN0RMDF041 (RSCAN0.RMDF041.UINT32)
+#define RSCAN0RMDF041L (RSCAN0.RMDF041.UINT16[R_IO_L])
+#define RSCAN0RMDF041LL (RSCAN0.RMDF041.UINT8[R_IO_LL])
+#define RSCAN0RMDF041LH (RSCAN0.RMDF041.UINT8[R_IO_LH])
+#define RSCAN0RMDF041H (RSCAN0.RMDF041.UINT16[R_IO_H])
+#define RSCAN0RMDF041HL (RSCAN0.RMDF041.UINT8[R_IO_HL])
+#define RSCAN0RMDF041HH (RSCAN0.RMDF041.UINT8[R_IO_HH])
+#define RSCAN0RMDF141 (RSCAN0.RMDF141.UINT32)
+#define RSCAN0RMDF141L (RSCAN0.RMDF141.UINT16[R_IO_L])
+#define RSCAN0RMDF141LL (RSCAN0.RMDF141.UINT8[R_IO_LL])
+#define RSCAN0RMDF141LH (RSCAN0.RMDF141.UINT8[R_IO_LH])
+#define RSCAN0RMDF141H (RSCAN0.RMDF141.UINT16[R_IO_H])
+#define RSCAN0RMDF141HL (RSCAN0.RMDF141.UINT8[R_IO_HL])
+#define RSCAN0RMDF141HH (RSCAN0.RMDF141.UINT8[R_IO_HH])
+#define RSCAN0RMID42 (RSCAN0.RMID42.UINT32)
+#define RSCAN0RMID42L (RSCAN0.RMID42.UINT16[R_IO_L])
+#define RSCAN0RMID42LL (RSCAN0.RMID42.UINT8[R_IO_LL])
+#define RSCAN0RMID42LH (RSCAN0.RMID42.UINT8[R_IO_LH])
+#define RSCAN0RMID42H (RSCAN0.RMID42.UINT16[R_IO_H])
+#define RSCAN0RMID42HL (RSCAN0.RMID42.UINT8[R_IO_HL])
+#define RSCAN0RMID42HH (RSCAN0.RMID42.UINT8[R_IO_HH])
+#define RSCAN0RMPTR42 (RSCAN0.RMPTR42.UINT32)
+#define RSCAN0RMPTR42L (RSCAN0.RMPTR42.UINT16[R_IO_L])
+#define RSCAN0RMPTR42LL (RSCAN0.RMPTR42.UINT8[R_IO_LL])
+#define RSCAN0RMPTR42LH (RSCAN0.RMPTR42.UINT8[R_IO_LH])
+#define RSCAN0RMPTR42H (RSCAN0.RMPTR42.UINT16[R_IO_H])
+#define RSCAN0RMPTR42HL (RSCAN0.RMPTR42.UINT8[R_IO_HL])
+#define RSCAN0RMPTR42HH (RSCAN0.RMPTR42.UINT8[R_IO_HH])
+#define RSCAN0RMDF042 (RSCAN0.RMDF042.UINT32)
+#define RSCAN0RMDF042L (RSCAN0.RMDF042.UINT16[R_IO_L])
+#define RSCAN0RMDF042LL (RSCAN0.RMDF042.UINT8[R_IO_LL])
+#define RSCAN0RMDF042LH (RSCAN0.RMDF042.UINT8[R_IO_LH])
+#define RSCAN0RMDF042H (RSCAN0.RMDF042.UINT16[R_IO_H])
+#define RSCAN0RMDF042HL (RSCAN0.RMDF042.UINT8[R_IO_HL])
+#define RSCAN0RMDF042HH (RSCAN0.RMDF042.UINT8[R_IO_HH])
+#define RSCAN0RMDF142 (RSCAN0.RMDF142.UINT32)
+#define RSCAN0RMDF142L (RSCAN0.RMDF142.UINT16[R_IO_L])
+#define RSCAN0RMDF142LL (RSCAN0.RMDF142.UINT8[R_IO_LL])
+#define RSCAN0RMDF142LH (RSCAN0.RMDF142.UINT8[R_IO_LH])
+#define RSCAN0RMDF142H (RSCAN0.RMDF142.UINT16[R_IO_H])
+#define RSCAN0RMDF142HL (RSCAN0.RMDF142.UINT8[R_IO_HL])
+#define RSCAN0RMDF142HH (RSCAN0.RMDF142.UINT8[R_IO_HH])
+#define RSCAN0RMID43 (RSCAN0.RMID43.UINT32)
+#define RSCAN0RMID43L (RSCAN0.RMID43.UINT16[R_IO_L])
+#define RSCAN0RMID43LL (RSCAN0.RMID43.UINT8[R_IO_LL])
+#define RSCAN0RMID43LH (RSCAN0.RMID43.UINT8[R_IO_LH])
+#define RSCAN0RMID43H (RSCAN0.RMID43.UINT16[R_IO_H])
+#define RSCAN0RMID43HL (RSCAN0.RMID43.UINT8[R_IO_HL])
+#define RSCAN0RMID43HH (RSCAN0.RMID43.UINT8[R_IO_HH])
+#define RSCAN0RMPTR43 (RSCAN0.RMPTR43.UINT32)
+#define RSCAN0RMPTR43L (RSCAN0.RMPTR43.UINT16[R_IO_L])
+#define RSCAN0RMPTR43LL (RSCAN0.RMPTR43.UINT8[R_IO_LL])
+#define RSCAN0RMPTR43LH (RSCAN0.RMPTR43.UINT8[R_IO_LH])
+#define RSCAN0RMPTR43H (RSCAN0.RMPTR43.UINT16[R_IO_H])
+#define RSCAN0RMPTR43HL (RSCAN0.RMPTR43.UINT8[R_IO_HL])
+#define RSCAN0RMPTR43HH (RSCAN0.RMPTR43.UINT8[R_IO_HH])
+#define RSCAN0RMDF043 (RSCAN0.RMDF043.UINT32)
+#define RSCAN0RMDF043L (RSCAN0.RMDF043.UINT16[R_IO_L])
+#define RSCAN0RMDF043LL (RSCAN0.RMDF043.UINT8[R_IO_LL])
+#define RSCAN0RMDF043LH (RSCAN0.RMDF043.UINT8[R_IO_LH])
+#define RSCAN0RMDF043H (RSCAN0.RMDF043.UINT16[R_IO_H])
+#define RSCAN0RMDF043HL (RSCAN0.RMDF043.UINT8[R_IO_HL])
+#define RSCAN0RMDF043HH (RSCAN0.RMDF043.UINT8[R_IO_HH])
+#define RSCAN0RMDF143 (RSCAN0.RMDF143.UINT32)
+#define RSCAN0RMDF143L (RSCAN0.RMDF143.UINT16[R_IO_L])
+#define RSCAN0RMDF143LL (RSCAN0.RMDF143.UINT8[R_IO_LL])
+#define RSCAN0RMDF143LH (RSCAN0.RMDF143.UINT8[R_IO_LH])
+#define RSCAN0RMDF143H (RSCAN0.RMDF143.UINT16[R_IO_H])
+#define RSCAN0RMDF143HL (RSCAN0.RMDF143.UINT8[R_IO_HL])
+#define RSCAN0RMDF143HH (RSCAN0.RMDF143.UINT8[R_IO_HH])
+#define RSCAN0RMID44 (RSCAN0.RMID44.UINT32)
+#define RSCAN0RMID44L (RSCAN0.RMID44.UINT16[R_IO_L])
+#define RSCAN0RMID44LL (RSCAN0.RMID44.UINT8[R_IO_LL])
+#define RSCAN0RMID44LH (RSCAN0.RMID44.UINT8[R_IO_LH])
+#define RSCAN0RMID44H (RSCAN0.RMID44.UINT16[R_IO_H])
+#define RSCAN0RMID44HL (RSCAN0.RMID44.UINT8[R_IO_HL])
+#define RSCAN0RMID44HH (RSCAN0.RMID44.UINT8[R_IO_HH])
+#define RSCAN0RMPTR44 (RSCAN0.RMPTR44.UINT32)
+#define RSCAN0RMPTR44L (RSCAN0.RMPTR44.UINT16[R_IO_L])
+#define RSCAN0RMPTR44LL (RSCAN0.RMPTR44.UINT8[R_IO_LL])
+#define RSCAN0RMPTR44LH (RSCAN0.RMPTR44.UINT8[R_IO_LH])
+#define RSCAN0RMPTR44H (RSCAN0.RMPTR44.UINT16[R_IO_H])
+#define RSCAN0RMPTR44HL (RSCAN0.RMPTR44.UINT8[R_IO_HL])
+#define RSCAN0RMPTR44HH (RSCAN0.RMPTR44.UINT8[R_IO_HH])
+#define RSCAN0RMDF044 (RSCAN0.RMDF044.UINT32)
+#define RSCAN0RMDF044L (RSCAN0.RMDF044.UINT16[R_IO_L])
+#define RSCAN0RMDF044LL (RSCAN0.RMDF044.UINT8[R_IO_LL])
+#define RSCAN0RMDF044LH (RSCAN0.RMDF044.UINT8[R_IO_LH])
+#define RSCAN0RMDF044H (RSCAN0.RMDF044.UINT16[R_IO_H])
+#define RSCAN0RMDF044HL (RSCAN0.RMDF044.UINT8[R_IO_HL])
+#define RSCAN0RMDF044HH (RSCAN0.RMDF044.UINT8[R_IO_HH])
+#define RSCAN0RMDF144 (RSCAN0.RMDF144.UINT32)
+#define RSCAN0RMDF144L (RSCAN0.RMDF144.UINT16[R_IO_L])
+#define RSCAN0RMDF144LL (RSCAN0.RMDF144.UINT8[R_IO_LL])
+#define RSCAN0RMDF144LH (RSCAN0.RMDF144.UINT8[R_IO_LH])
+#define RSCAN0RMDF144H (RSCAN0.RMDF144.UINT16[R_IO_H])
+#define RSCAN0RMDF144HL (RSCAN0.RMDF144.UINT8[R_IO_HL])
+#define RSCAN0RMDF144HH (RSCAN0.RMDF144.UINT8[R_IO_HH])
+#define RSCAN0RMID45 (RSCAN0.RMID45.UINT32)
+#define RSCAN0RMID45L (RSCAN0.RMID45.UINT16[R_IO_L])
+#define RSCAN0RMID45LL (RSCAN0.RMID45.UINT8[R_IO_LL])
+#define RSCAN0RMID45LH (RSCAN0.RMID45.UINT8[R_IO_LH])
+#define RSCAN0RMID45H (RSCAN0.RMID45.UINT16[R_IO_H])
+#define RSCAN0RMID45HL (RSCAN0.RMID45.UINT8[R_IO_HL])
+#define RSCAN0RMID45HH (RSCAN0.RMID45.UINT8[R_IO_HH])
+#define RSCAN0RMPTR45 (RSCAN0.RMPTR45.UINT32)
+#define RSCAN0RMPTR45L (RSCAN0.RMPTR45.UINT16[R_IO_L])
+#define RSCAN0RMPTR45LL (RSCAN0.RMPTR45.UINT8[R_IO_LL])
+#define RSCAN0RMPTR45LH (RSCAN0.RMPTR45.UINT8[R_IO_LH])
+#define RSCAN0RMPTR45H (RSCAN0.RMPTR45.UINT16[R_IO_H])
+#define RSCAN0RMPTR45HL (RSCAN0.RMPTR45.UINT8[R_IO_HL])
+#define RSCAN0RMPTR45HH (RSCAN0.RMPTR45.UINT8[R_IO_HH])
+#define RSCAN0RMDF045 (RSCAN0.RMDF045.UINT32)
+#define RSCAN0RMDF045L (RSCAN0.RMDF045.UINT16[R_IO_L])
+#define RSCAN0RMDF045LL (RSCAN0.RMDF045.UINT8[R_IO_LL])
+#define RSCAN0RMDF045LH (RSCAN0.RMDF045.UINT8[R_IO_LH])
+#define RSCAN0RMDF045H (RSCAN0.RMDF045.UINT16[R_IO_H])
+#define RSCAN0RMDF045HL (RSCAN0.RMDF045.UINT8[R_IO_HL])
+#define RSCAN0RMDF045HH (RSCAN0.RMDF045.UINT8[R_IO_HH])
+#define RSCAN0RMDF145 (RSCAN0.RMDF145.UINT32)
+#define RSCAN0RMDF145L (RSCAN0.RMDF145.UINT16[R_IO_L])
+#define RSCAN0RMDF145LL (RSCAN0.RMDF145.UINT8[R_IO_LL])
+#define RSCAN0RMDF145LH (RSCAN0.RMDF145.UINT8[R_IO_LH])
+#define RSCAN0RMDF145H (RSCAN0.RMDF145.UINT16[R_IO_H])
+#define RSCAN0RMDF145HL (RSCAN0.RMDF145.UINT8[R_IO_HL])
+#define RSCAN0RMDF145HH (RSCAN0.RMDF145.UINT8[R_IO_HH])
+#define RSCAN0RMID46 (RSCAN0.RMID46.UINT32)
+#define RSCAN0RMID46L (RSCAN0.RMID46.UINT16[R_IO_L])
+#define RSCAN0RMID46LL (RSCAN0.RMID46.UINT8[R_IO_LL])
+#define RSCAN0RMID46LH (RSCAN0.RMID46.UINT8[R_IO_LH])
+#define RSCAN0RMID46H (RSCAN0.RMID46.UINT16[R_IO_H])
+#define RSCAN0RMID46HL (RSCAN0.RMID46.UINT8[R_IO_HL])
+#define RSCAN0RMID46HH (RSCAN0.RMID46.UINT8[R_IO_HH])
+#define RSCAN0RMPTR46 (RSCAN0.RMPTR46.UINT32)
+#define RSCAN0RMPTR46L (RSCAN0.RMPTR46.UINT16[R_IO_L])
+#define RSCAN0RMPTR46LL (RSCAN0.RMPTR46.UINT8[R_IO_LL])
+#define RSCAN0RMPTR46LH (RSCAN0.RMPTR46.UINT8[R_IO_LH])
+#define RSCAN0RMPTR46H (RSCAN0.RMPTR46.UINT16[R_IO_H])
+#define RSCAN0RMPTR46HL (RSCAN0.RMPTR46.UINT8[R_IO_HL])
+#define RSCAN0RMPTR46HH (RSCAN0.RMPTR46.UINT8[R_IO_HH])
+#define RSCAN0RMDF046 (RSCAN0.RMDF046.UINT32)
+#define RSCAN0RMDF046L (RSCAN0.RMDF046.UINT16[R_IO_L])
+#define RSCAN0RMDF046LL (RSCAN0.RMDF046.UINT8[R_IO_LL])
+#define RSCAN0RMDF046LH (RSCAN0.RMDF046.UINT8[R_IO_LH])
+#define RSCAN0RMDF046H (RSCAN0.RMDF046.UINT16[R_IO_H])
+#define RSCAN0RMDF046HL (RSCAN0.RMDF046.UINT8[R_IO_HL])
+#define RSCAN0RMDF046HH (RSCAN0.RMDF046.UINT8[R_IO_HH])
+#define RSCAN0RMDF146 (RSCAN0.RMDF146.UINT32)
+#define RSCAN0RMDF146L (RSCAN0.RMDF146.UINT16[R_IO_L])
+#define RSCAN0RMDF146LL (RSCAN0.RMDF146.UINT8[R_IO_LL])
+#define RSCAN0RMDF146LH (RSCAN0.RMDF146.UINT8[R_IO_LH])
+#define RSCAN0RMDF146H (RSCAN0.RMDF146.UINT16[R_IO_H])
+#define RSCAN0RMDF146HL (RSCAN0.RMDF146.UINT8[R_IO_HL])
+#define RSCAN0RMDF146HH (RSCAN0.RMDF146.UINT8[R_IO_HH])
+#define RSCAN0RMID47 (RSCAN0.RMID47.UINT32)
+#define RSCAN0RMID47L (RSCAN0.RMID47.UINT16[R_IO_L])
+#define RSCAN0RMID47LL (RSCAN0.RMID47.UINT8[R_IO_LL])
+#define RSCAN0RMID47LH (RSCAN0.RMID47.UINT8[R_IO_LH])
+#define RSCAN0RMID47H (RSCAN0.RMID47.UINT16[R_IO_H])
+#define RSCAN0RMID47HL (RSCAN0.RMID47.UINT8[R_IO_HL])
+#define RSCAN0RMID47HH (RSCAN0.RMID47.UINT8[R_IO_HH])
+#define RSCAN0RMPTR47 (RSCAN0.RMPTR47.UINT32)
+#define RSCAN0RMPTR47L (RSCAN0.RMPTR47.UINT16[R_IO_L])
+#define RSCAN0RMPTR47LL (RSCAN0.RMPTR47.UINT8[R_IO_LL])
+#define RSCAN0RMPTR47LH (RSCAN0.RMPTR47.UINT8[R_IO_LH])
+#define RSCAN0RMPTR47H (RSCAN0.RMPTR47.UINT16[R_IO_H])
+#define RSCAN0RMPTR47HL (RSCAN0.RMPTR47.UINT8[R_IO_HL])
+#define RSCAN0RMPTR47HH (RSCAN0.RMPTR47.UINT8[R_IO_HH])
+#define RSCAN0RMDF047 (RSCAN0.RMDF047.UINT32)
+#define RSCAN0RMDF047L (RSCAN0.RMDF047.UINT16[R_IO_L])
+#define RSCAN0RMDF047LL (RSCAN0.RMDF047.UINT8[R_IO_LL])
+#define RSCAN0RMDF047LH (RSCAN0.RMDF047.UINT8[R_IO_LH])
+#define RSCAN0RMDF047H (RSCAN0.RMDF047.UINT16[R_IO_H])
+#define RSCAN0RMDF047HL (RSCAN0.RMDF047.UINT8[R_IO_HL])
+#define RSCAN0RMDF047HH (RSCAN0.RMDF047.UINT8[R_IO_HH])
+#define RSCAN0RMDF147 (RSCAN0.RMDF147.UINT32)
+#define RSCAN0RMDF147L (RSCAN0.RMDF147.UINT16[R_IO_L])
+#define RSCAN0RMDF147LL (RSCAN0.RMDF147.UINT8[R_IO_LL])
+#define RSCAN0RMDF147LH (RSCAN0.RMDF147.UINT8[R_IO_LH])
+#define RSCAN0RMDF147H (RSCAN0.RMDF147.UINT16[R_IO_H])
+#define RSCAN0RMDF147HL (RSCAN0.RMDF147.UINT8[R_IO_HL])
+#define RSCAN0RMDF147HH (RSCAN0.RMDF147.UINT8[R_IO_HH])
+#define RSCAN0RMID48 (RSCAN0.RMID48.UINT32)
+#define RSCAN0RMID48L (RSCAN0.RMID48.UINT16[R_IO_L])
+#define RSCAN0RMID48LL (RSCAN0.RMID48.UINT8[R_IO_LL])
+#define RSCAN0RMID48LH (RSCAN0.RMID48.UINT8[R_IO_LH])
+#define RSCAN0RMID48H (RSCAN0.RMID48.UINT16[R_IO_H])
+#define RSCAN0RMID48HL (RSCAN0.RMID48.UINT8[R_IO_HL])
+#define RSCAN0RMID48HH (RSCAN0.RMID48.UINT8[R_IO_HH])
+#define RSCAN0RMPTR48 (RSCAN0.RMPTR48.UINT32)
+#define RSCAN0RMPTR48L (RSCAN0.RMPTR48.UINT16[R_IO_L])
+#define RSCAN0RMPTR48LL (RSCAN0.RMPTR48.UINT8[R_IO_LL])
+#define RSCAN0RMPTR48LH (RSCAN0.RMPTR48.UINT8[R_IO_LH])
+#define RSCAN0RMPTR48H (RSCAN0.RMPTR48.UINT16[R_IO_H])
+#define RSCAN0RMPTR48HL (RSCAN0.RMPTR48.UINT8[R_IO_HL])
+#define RSCAN0RMPTR48HH (RSCAN0.RMPTR48.UINT8[R_IO_HH])
+#define RSCAN0RMDF048 (RSCAN0.RMDF048.UINT32)
+#define RSCAN0RMDF048L (RSCAN0.RMDF048.UINT16[R_IO_L])
+#define RSCAN0RMDF048LL (RSCAN0.RMDF048.UINT8[R_IO_LL])
+#define RSCAN0RMDF048LH (RSCAN0.RMDF048.UINT8[R_IO_LH])
+#define RSCAN0RMDF048H (RSCAN0.RMDF048.UINT16[R_IO_H])
+#define RSCAN0RMDF048HL (RSCAN0.RMDF048.UINT8[R_IO_HL])
+#define RSCAN0RMDF048HH (RSCAN0.RMDF048.UINT8[R_IO_HH])
+#define RSCAN0RMDF148 (RSCAN0.RMDF148.UINT32)
+#define RSCAN0RMDF148L (RSCAN0.RMDF148.UINT16[R_IO_L])
+#define RSCAN0RMDF148LL (RSCAN0.RMDF148.UINT8[R_IO_LL])
+#define RSCAN0RMDF148LH (RSCAN0.RMDF148.UINT8[R_IO_LH])
+#define RSCAN0RMDF148H (RSCAN0.RMDF148.UINT16[R_IO_H])
+#define RSCAN0RMDF148HL (RSCAN0.RMDF148.UINT8[R_IO_HL])
+#define RSCAN0RMDF148HH (RSCAN0.RMDF148.UINT8[R_IO_HH])
+#define RSCAN0RMID49 (RSCAN0.RMID49.UINT32)
+#define RSCAN0RMID49L (RSCAN0.RMID49.UINT16[R_IO_L])
+#define RSCAN0RMID49LL (RSCAN0.RMID49.UINT8[R_IO_LL])
+#define RSCAN0RMID49LH (RSCAN0.RMID49.UINT8[R_IO_LH])
+#define RSCAN0RMID49H (RSCAN0.RMID49.UINT16[R_IO_H])
+#define RSCAN0RMID49HL (RSCAN0.RMID49.UINT8[R_IO_HL])
+#define RSCAN0RMID49HH (RSCAN0.RMID49.UINT8[R_IO_HH])
+#define RSCAN0RMPTR49 (RSCAN0.RMPTR49.UINT32)
+#define RSCAN0RMPTR49L (RSCAN0.RMPTR49.UINT16[R_IO_L])
+#define RSCAN0RMPTR49LL (RSCAN0.RMPTR49.UINT8[R_IO_LL])
+#define RSCAN0RMPTR49LH (RSCAN0.RMPTR49.UINT8[R_IO_LH])
+#define RSCAN0RMPTR49H (RSCAN0.RMPTR49.UINT16[R_IO_H])
+#define RSCAN0RMPTR49HL (RSCAN0.RMPTR49.UINT8[R_IO_HL])
+#define RSCAN0RMPTR49HH (RSCAN0.RMPTR49.UINT8[R_IO_HH])
+#define RSCAN0RMDF049 (RSCAN0.RMDF049.UINT32)
+#define RSCAN0RMDF049L (RSCAN0.RMDF049.UINT16[R_IO_L])
+#define RSCAN0RMDF049LL (RSCAN0.RMDF049.UINT8[R_IO_LL])
+#define RSCAN0RMDF049LH (RSCAN0.RMDF049.UINT8[R_IO_LH])
+#define RSCAN0RMDF049H (RSCAN0.RMDF049.UINT16[R_IO_H])
+#define RSCAN0RMDF049HL (RSCAN0.RMDF049.UINT8[R_IO_HL])
+#define RSCAN0RMDF049HH (RSCAN0.RMDF049.UINT8[R_IO_HH])
+#define RSCAN0RMDF149 (RSCAN0.RMDF149.UINT32)
+#define RSCAN0RMDF149L (RSCAN0.RMDF149.UINT16[R_IO_L])
+#define RSCAN0RMDF149LL (RSCAN0.RMDF149.UINT8[R_IO_LL])
+#define RSCAN0RMDF149LH (RSCAN0.RMDF149.UINT8[R_IO_LH])
+#define RSCAN0RMDF149H (RSCAN0.RMDF149.UINT16[R_IO_H])
+#define RSCAN0RMDF149HL (RSCAN0.RMDF149.UINT8[R_IO_HL])
+#define RSCAN0RMDF149HH (RSCAN0.RMDF149.UINT8[R_IO_HH])
+#define RSCAN0RMID50 (RSCAN0.RMID50.UINT32)
+#define RSCAN0RMID50L (RSCAN0.RMID50.UINT16[R_IO_L])
+#define RSCAN0RMID50LL (RSCAN0.RMID50.UINT8[R_IO_LL])
+#define RSCAN0RMID50LH (RSCAN0.RMID50.UINT8[R_IO_LH])
+#define RSCAN0RMID50H (RSCAN0.RMID50.UINT16[R_IO_H])
+#define RSCAN0RMID50HL (RSCAN0.RMID50.UINT8[R_IO_HL])
+#define RSCAN0RMID50HH (RSCAN0.RMID50.UINT8[R_IO_HH])
+#define RSCAN0RMPTR50 (RSCAN0.RMPTR50.UINT32)
+#define RSCAN0RMPTR50L (RSCAN0.RMPTR50.UINT16[R_IO_L])
+#define RSCAN0RMPTR50LL (RSCAN0.RMPTR50.UINT8[R_IO_LL])
+#define RSCAN0RMPTR50LH (RSCAN0.RMPTR50.UINT8[R_IO_LH])
+#define RSCAN0RMPTR50H (RSCAN0.RMPTR50.UINT16[R_IO_H])
+#define RSCAN0RMPTR50HL (RSCAN0.RMPTR50.UINT8[R_IO_HL])
+#define RSCAN0RMPTR50HH (RSCAN0.RMPTR50.UINT8[R_IO_HH])
+#define RSCAN0RMDF050 (RSCAN0.RMDF050.UINT32)
+#define RSCAN0RMDF050L (RSCAN0.RMDF050.UINT16[R_IO_L])
+#define RSCAN0RMDF050LL (RSCAN0.RMDF050.UINT8[R_IO_LL])
+#define RSCAN0RMDF050LH (RSCAN0.RMDF050.UINT8[R_IO_LH])
+#define RSCAN0RMDF050H (RSCAN0.RMDF050.UINT16[R_IO_H])
+#define RSCAN0RMDF050HL (RSCAN0.RMDF050.UINT8[R_IO_HL])
+#define RSCAN0RMDF050HH (RSCAN0.RMDF050.UINT8[R_IO_HH])
+#define RSCAN0RMDF150 (RSCAN0.RMDF150.UINT32)
+#define RSCAN0RMDF150L (RSCAN0.RMDF150.UINT16[R_IO_L])
+#define RSCAN0RMDF150LL (RSCAN0.RMDF150.UINT8[R_IO_LL])
+#define RSCAN0RMDF150LH (RSCAN0.RMDF150.UINT8[R_IO_LH])
+#define RSCAN0RMDF150H (RSCAN0.RMDF150.UINT16[R_IO_H])
+#define RSCAN0RMDF150HL (RSCAN0.RMDF150.UINT8[R_IO_HL])
+#define RSCAN0RMDF150HH (RSCAN0.RMDF150.UINT8[R_IO_HH])
+#define RSCAN0RMID51 (RSCAN0.RMID51.UINT32)
+#define RSCAN0RMID51L (RSCAN0.RMID51.UINT16[R_IO_L])
+#define RSCAN0RMID51LL (RSCAN0.RMID51.UINT8[R_IO_LL])
+#define RSCAN0RMID51LH (RSCAN0.RMID51.UINT8[R_IO_LH])
+#define RSCAN0RMID51H (RSCAN0.RMID51.UINT16[R_IO_H])
+#define RSCAN0RMID51HL (RSCAN0.RMID51.UINT8[R_IO_HL])
+#define RSCAN0RMID51HH (RSCAN0.RMID51.UINT8[R_IO_HH])
+#define RSCAN0RMPTR51 (RSCAN0.RMPTR51.UINT32)
+#define RSCAN0RMPTR51L (RSCAN0.RMPTR51.UINT16[R_IO_L])
+#define RSCAN0RMPTR51LL (RSCAN0.RMPTR51.UINT8[R_IO_LL])
+#define RSCAN0RMPTR51LH (RSCAN0.RMPTR51.UINT8[R_IO_LH])
+#define RSCAN0RMPTR51H (RSCAN0.RMPTR51.UINT16[R_IO_H])
+#define RSCAN0RMPTR51HL (RSCAN0.RMPTR51.UINT8[R_IO_HL])
+#define RSCAN0RMPTR51HH (RSCAN0.RMPTR51.UINT8[R_IO_HH])
+#define RSCAN0RMDF051 (RSCAN0.RMDF051.UINT32)
+#define RSCAN0RMDF051L (RSCAN0.RMDF051.UINT16[R_IO_L])
+#define RSCAN0RMDF051LL (RSCAN0.RMDF051.UINT8[R_IO_LL])
+#define RSCAN0RMDF051LH (RSCAN0.RMDF051.UINT8[R_IO_LH])
+#define RSCAN0RMDF051H (RSCAN0.RMDF051.UINT16[R_IO_H])
+#define RSCAN0RMDF051HL (RSCAN0.RMDF051.UINT8[R_IO_HL])
+#define RSCAN0RMDF051HH (RSCAN0.RMDF051.UINT8[R_IO_HH])
+#define RSCAN0RMDF151 (RSCAN0.RMDF151.UINT32)
+#define RSCAN0RMDF151L (RSCAN0.RMDF151.UINT16[R_IO_L])
+#define RSCAN0RMDF151LL (RSCAN0.RMDF151.UINT8[R_IO_LL])
+#define RSCAN0RMDF151LH (RSCAN0.RMDF151.UINT8[R_IO_LH])
+#define RSCAN0RMDF151H (RSCAN0.RMDF151.UINT16[R_IO_H])
+#define RSCAN0RMDF151HL (RSCAN0.RMDF151.UINT8[R_IO_HL])
+#define RSCAN0RMDF151HH (RSCAN0.RMDF151.UINT8[R_IO_HH])
+#define RSCAN0RMID52 (RSCAN0.RMID52.UINT32)
+#define RSCAN0RMID52L (RSCAN0.RMID52.UINT16[R_IO_L])
+#define RSCAN0RMID52LL (RSCAN0.RMID52.UINT8[R_IO_LL])
+#define RSCAN0RMID52LH (RSCAN0.RMID52.UINT8[R_IO_LH])
+#define RSCAN0RMID52H (RSCAN0.RMID52.UINT16[R_IO_H])
+#define RSCAN0RMID52HL (RSCAN0.RMID52.UINT8[R_IO_HL])
+#define RSCAN0RMID52HH (RSCAN0.RMID52.UINT8[R_IO_HH])
+#define RSCAN0RMPTR52 (RSCAN0.RMPTR52.UINT32)
+#define RSCAN0RMPTR52L (RSCAN0.RMPTR52.UINT16[R_IO_L])
+#define RSCAN0RMPTR52LL (RSCAN0.RMPTR52.UINT8[R_IO_LL])
+#define RSCAN0RMPTR52LH (RSCAN0.RMPTR52.UINT8[R_IO_LH])
+#define RSCAN0RMPTR52H (RSCAN0.RMPTR52.UINT16[R_IO_H])
+#define RSCAN0RMPTR52HL (RSCAN0.RMPTR52.UINT8[R_IO_HL])
+#define RSCAN0RMPTR52HH (RSCAN0.RMPTR52.UINT8[R_IO_HH])
+#define RSCAN0RMDF052 (RSCAN0.RMDF052.UINT32)
+#define RSCAN0RMDF052L (RSCAN0.RMDF052.UINT16[R_IO_L])
+#define RSCAN0RMDF052LL (RSCAN0.RMDF052.UINT8[R_IO_LL])
+#define RSCAN0RMDF052LH (RSCAN0.RMDF052.UINT8[R_IO_LH])
+#define RSCAN0RMDF052H (RSCAN0.RMDF052.UINT16[R_IO_H])
+#define RSCAN0RMDF052HL (RSCAN0.RMDF052.UINT8[R_IO_HL])
+#define RSCAN0RMDF052HH (RSCAN0.RMDF052.UINT8[R_IO_HH])
+#define RSCAN0RMDF152 (RSCAN0.RMDF152.UINT32)
+#define RSCAN0RMDF152L (RSCAN0.RMDF152.UINT16[R_IO_L])
+#define RSCAN0RMDF152LL (RSCAN0.RMDF152.UINT8[R_IO_LL])
+#define RSCAN0RMDF152LH (RSCAN0.RMDF152.UINT8[R_IO_LH])
+#define RSCAN0RMDF152H (RSCAN0.RMDF152.UINT16[R_IO_H])
+#define RSCAN0RMDF152HL (RSCAN0.RMDF152.UINT8[R_IO_HL])
+#define RSCAN0RMDF152HH (RSCAN0.RMDF152.UINT8[R_IO_HH])
+#define RSCAN0RMID53 (RSCAN0.RMID53.UINT32)
+#define RSCAN0RMID53L (RSCAN0.RMID53.UINT16[R_IO_L])
+#define RSCAN0RMID53LL (RSCAN0.RMID53.UINT8[R_IO_LL])
+#define RSCAN0RMID53LH (RSCAN0.RMID53.UINT8[R_IO_LH])
+#define RSCAN0RMID53H (RSCAN0.RMID53.UINT16[R_IO_H])
+#define RSCAN0RMID53HL (RSCAN0.RMID53.UINT8[R_IO_HL])
+#define RSCAN0RMID53HH (RSCAN0.RMID53.UINT8[R_IO_HH])
+#define RSCAN0RMPTR53 (RSCAN0.RMPTR53.UINT32)
+#define RSCAN0RMPTR53L (RSCAN0.RMPTR53.UINT16[R_IO_L])
+#define RSCAN0RMPTR53LL (RSCAN0.RMPTR53.UINT8[R_IO_LL])
+#define RSCAN0RMPTR53LH (RSCAN0.RMPTR53.UINT8[R_IO_LH])
+#define RSCAN0RMPTR53H (RSCAN0.RMPTR53.UINT16[R_IO_H])
+#define RSCAN0RMPTR53HL (RSCAN0.RMPTR53.UINT8[R_IO_HL])
+#define RSCAN0RMPTR53HH (RSCAN0.RMPTR53.UINT8[R_IO_HH])
+#define RSCAN0RMDF053 (RSCAN0.RMDF053.UINT32)
+#define RSCAN0RMDF053L (RSCAN0.RMDF053.UINT16[R_IO_L])
+#define RSCAN0RMDF053LL (RSCAN0.RMDF053.UINT8[R_IO_LL])
+#define RSCAN0RMDF053LH (RSCAN0.RMDF053.UINT8[R_IO_LH])
+#define RSCAN0RMDF053H (RSCAN0.RMDF053.UINT16[R_IO_H])
+#define RSCAN0RMDF053HL (RSCAN0.RMDF053.UINT8[R_IO_HL])
+#define RSCAN0RMDF053HH (RSCAN0.RMDF053.UINT8[R_IO_HH])
+#define RSCAN0RMDF153 (RSCAN0.RMDF153.UINT32)
+#define RSCAN0RMDF153L (RSCAN0.RMDF153.UINT16[R_IO_L])
+#define RSCAN0RMDF153LL (RSCAN0.RMDF153.UINT8[R_IO_LL])
+#define RSCAN0RMDF153LH (RSCAN0.RMDF153.UINT8[R_IO_LH])
+#define RSCAN0RMDF153H (RSCAN0.RMDF153.UINT16[R_IO_H])
+#define RSCAN0RMDF153HL (RSCAN0.RMDF153.UINT8[R_IO_HL])
+#define RSCAN0RMDF153HH (RSCAN0.RMDF153.UINT8[R_IO_HH])
+#define RSCAN0RMID54 (RSCAN0.RMID54.UINT32)
+#define RSCAN0RMID54L (RSCAN0.RMID54.UINT16[R_IO_L])
+#define RSCAN0RMID54LL (RSCAN0.RMID54.UINT8[R_IO_LL])
+#define RSCAN0RMID54LH (RSCAN0.RMID54.UINT8[R_IO_LH])
+#define RSCAN0RMID54H (RSCAN0.RMID54.UINT16[R_IO_H])
+#define RSCAN0RMID54HL (RSCAN0.RMID54.UINT8[R_IO_HL])
+#define RSCAN0RMID54HH (RSCAN0.RMID54.UINT8[R_IO_HH])
+#define RSCAN0RMPTR54 (RSCAN0.RMPTR54.UINT32)
+#define RSCAN0RMPTR54L (RSCAN0.RMPTR54.UINT16[R_IO_L])
+#define RSCAN0RMPTR54LL (RSCAN0.RMPTR54.UINT8[R_IO_LL])
+#define RSCAN0RMPTR54LH (RSCAN0.RMPTR54.UINT8[R_IO_LH])
+#define RSCAN0RMPTR54H (RSCAN0.RMPTR54.UINT16[R_IO_H])
+#define RSCAN0RMPTR54HL (RSCAN0.RMPTR54.UINT8[R_IO_HL])
+#define RSCAN0RMPTR54HH (RSCAN0.RMPTR54.UINT8[R_IO_HH])
+#define RSCAN0RMDF054 (RSCAN0.RMDF054.UINT32)
+#define RSCAN0RMDF054L (RSCAN0.RMDF054.UINT16[R_IO_L])
+#define RSCAN0RMDF054LL (RSCAN0.RMDF054.UINT8[R_IO_LL])
+#define RSCAN0RMDF054LH (RSCAN0.RMDF054.UINT8[R_IO_LH])
+#define RSCAN0RMDF054H (RSCAN0.RMDF054.UINT16[R_IO_H])
+#define RSCAN0RMDF054HL (RSCAN0.RMDF054.UINT8[R_IO_HL])
+#define RSCAN0RMDF054HH (RSCAN0.RMDF054.UINT8[R_IO_HH])
+#define RSCAN0RMDF154 (RSCAN0.RMDF154.UINT32)
+#define RSCAN0RMDF154L (RSCAN0.RMDF154.UINT16[R_IO_L])
+#define RSCAN0RMDF154LL (RSCAN0.RMDF154.UINT8[R_IO_LL])
+#define RSCAN0RMDF154LH (RSCAN0.RMDF154.UINT8[R_IO_LH])
+#define RSCAN0RMDF154H (RSCAN0.RMDF154.UINT16[R_IO_H])
+#define RSCAN0RMDF154HL (RSCAN0.RMDF154.UINT8[R_IO_HL])
+#define RSCAN0RMDF154HH (RSCAN0.RMDF154.UINT8[R_IO_HH])
+#define RSCAN0RMID55 (RSCAN0.RMID55.UINT32)
+#define RSCAN0RMID55L (RSCAN0.RMID55.UINT16[R_IO_L])
+#define RSCAN0RMID55LL (RSCAN0.RMID55.UINT8[R_IO_LL])
+#define RSCAN0RMID55LH (RSCAN0.RMID55.UINT8[R_IO_LH])
+#define RSCAN0RMID55H (RSCAN0.RMID55.UINT16[R_IO_H])
+#define RSCAN0RMID55HL (RSCAN0.RMID55.UINT8[R_IO_HL])
+#define RSCAN0RMID55HH (RSCAN0.RMID55.UINT8[R_IO_HH])
+#define RSCAN0RMPTR55 (RSCAN0.RMPTR55.UINT32)
+#define RSCAN0RMPTR55L (RSCAN0.RMPTR55.UINT16[R_IO_L])
+#define RSCAN0RMPTR55LL (RSCAN0.RMPTR55.UINT8[R_IO_LL])
+#define RSCAN0RMPTR55LH (RSCAN0.RMPTR55.UINT8[R_IO_LH])
+#define RSCAN0RMPTR55H (RSCAN0.RMPTR55.UINT16[R_IO_H])
+#define RSCAN0RMPTR55HL (RSCAN0.RMPTR55.UINT8[R_IO_HL])
+#define RSCAN0RMPTR55HH (RSCAN0.RMPTR55.UINT8[R_IO_HH])
+#define RSCAN0RMDF055 (RSCAN0.RMDF055.UINT32)
+#define RSCAN0RMDF055L (RSCAN0.RMDF055.UINT16[R_IO_L])
+#define RSCAN0RMDF055LL (RSCAN0.RMDF055.UINT8[R_IO_LL])
+#define RSCAN0RMDF055LH (RSCAN0.RMDF055.UINT8[R_IO_LH])
+#define RSCAN0RMDF055H (RSCAN0.RMDF055.UINT16[R_IO_H])
+#define RSCAN0RMDF055HL (RSCAN0.RMDF055.UINT8[R_IO_HL])
+#define RSCAN0RMDF055HH (RSCAN0.RMDF055.UINT8[R_IO_HH])
+#define RSCAN0RMDF155 (RSCAN0.RMDF155.UINT32)
+#define RSCAN0RMDF155L (RSCAN0.RMDF155.UINT16[R_IO_L])
+#define RSCAN0RMDF155LL (RSCAN0.RMDF155.UINT8[R_IO_LL])
+#define RSCAN0RMDF155LH (RSCAN0.RMDF155.UINT8[R_IO_LH])
+#define RSCAN0RMDF155H (RSCAN0.RMDF155.UINT16[R_IO_H])
+#define RSCAN0RMDF155HL (RSCAN0.RMDF155.UINT8[R_IO_HL])
+#define RSCAN0RMDF155HH (RSCAN0.RMDF155.UINT8[R_IO_HH])
+#define RSCAN0RMID56 (RSCAN0.RMID56.UINT32)
+#define RSCAN0RMID56L (RSCAN0.RMID56.UINT16[R_IO_L])
+#define RSCAN0RMID56LL (RSCAN0.RMID56.UINT8[R_IO_LL])
+#define RSCAN0RMID56LH (RSCAN0.RMID56.UINT8[R_IO_LH])
+#define RSCAN0RMID56H (RSCAN0.RMID56.UINT16[R_IO_H])
+#define RSCAN0RMID56HL (RSCAN0.RMID56.UINT8[R_IO_HL])
+#define RSCAN0RMID56HH (RSCAN0.RMID56.UINT8[R_IO_HH])
+#define RSCAN0RMPTR56 (RSCAN0.RMPTR56.UINT32)
+#define RSCAN0RMPTR56L (RSCAN0.RMPTR56.UINT16[R_IO_L])
+#define RSCAN0RMPTR56LL (RSCAN0.RMPTR56.UINT8[R_IO_LL])
+#define RSCAN0RMPTR56LH (RSCAN0.RMPTR56.UINT8[R_IO_LH])
+#define RSCAN0RMPTR56H (RSCAN0.RMPTR56.UINT16[R_IO_H])
+#define RSCAN0RMPTR56HL (RSCAN0.RMPTR56.UINT8[R_IO_HL])
+#define RSCAN0RMPTR56HH (RSCAN0.RMPTR56.UINT8[R_IO_HH])
+#define RSCAN0RMDF056 (RSCAN0.RMDF056.UINT32)
+#define RSCAN0RMDF056L (RSCAN0.RMDF056.UINT16[R_IO_L])
+#define RSCAN0RMDF056LL (RSCAN0.RMDF056.UINT8[R_IO_LL])
+#define RSCAN0RMDF056LH (RSCAN0.RMDF056.UINT8[R_IO_LH])
+#define RSCAN0RMDF056H (RSCAN0.RMDF056.UINT16[R_IO_H])
+#define RSCAN0RMDF056HL (RSCAN0.RMDF056.UINT8[R_IO_HL])
+#define RSCAN0RMDF056HH (RSCAN0.RMDF056.UINT8[R_IO_HH])
+#define RSCAN0RMDF156 (RSCAN0.RMDF156.UINT32)
+#define RSCAN0RMDF156L (RSCAN0.RMDF156.UINT16[R_IO_L])
+#define RSCAN0RMDF156LL (RSCAN0.RMDF156.UINT8[R_IO_LL])
+#define RSCAN0RMDF156LH (RSCAN0.RMDF156.UINT8[R_IO_LH])
+#define RSCAN0RMDF156H (RSCAN0.RMDF156.UINT16[R_IO_H])
+#define RSCAN0RMDF156HL (RSCAN0.RMDF156.UINT8[R_IO_HL])
+#define RSCAN0RMDF156HH (RSCAN0.RMDF156.UINT8[R_IO_HH])
+#define RSCAN0RMID57 (RSCAN0.RMID57.UINT32)
+#define RSCAN0RMID57L (RSCAN0.RMID57.UINT16[R_IO_L])
+#define RSCAN0RMID57LL (RSCAN0.RMID57.UINT8[R_IO_LL])
+#define RSCAN0RMID57LH (RSCAN0.RMID57.UINT8[R_IO_LH])
+#define RSCAN0RMID57H (RSCAN0.RMID57.UINT16[R_IO_H])
+#define RSCAN0RMID57HL (RSCAN0.RMID57.UINT8[R_IO_HL])
+#define RSCAN0RMID57HH (RSCAN0.RMID57.UINT8[R_IO_HH])
+#define RSCAN0RMPTR57 (RSCAN0.RMPTR57.UINT32)
+#define RSCAN0RMPTR57L (RSCAN0.RMPTR57.UINT16[R_IO_L])
+#define RSCAN0RMPTR57LL (RSCAN0.RMPTR57.UINT8[R_IO_LL])
+#define RSCAN0RMPTR57LH (RSCAN0.RMPTR57.UINT8[R_IO_LH])
+#define RSCAN0RMPTR57H (RSCAN0.RMPTR57.UINT16[R_IO_H])
+#define RSCAN0RMPTR57HL (RSCAN0.RMPTR57.UINT8[R_IO_HL])
+#define RSCAN0RMPTR57HH (RSCAN0.RMPTR57.UINT8[R_IO_HH])
+#define RSCAN0RMDF057 (RSCAN0.RMDF057.UINT32)
+#define RSCAN0RMDF057L (RSCAN0.RMDF057.UINT16[R_IO_L])
+#define RSCAN0RMDF057LL (RSCAN0.RMDF057.UINT8[R_IO_LL])
+#define RSCAN0RMDF057LH (RSCAN0.RMDF057.UINT8[R_IO_LH])
+#define RSCAN0RMDF057H (RSCAN0.RMDF057.UINT16[R_IO_H])
+#define RSCAN0RMDF057HL (RSCAN0.RMDF057.UINT8[R_IO_HL])
+#define RSCAN0RMDF057HH (RSCAN0.RMDF057.UINT8[R_IO_HH])
+#define RSCAN0RMDF157 (RSCAN0.RMDF157.UINT32)
+#define RSCAN0RMDF157L (RSCAN0.RMDF157.UINT16[R_IO_L])
+#define RSCAN0RMDF157LL (RSCAN0.RMDF157.UINT8[R_IO_LL])
+#define RSCAN0RMDF157LH (RSCAN0.RMDF157.UINT8[R_IO_LH])
+#define RSCAN0RMDF157H (RSCAN0.RMDF157.UINT16[R_IO_H])
+#define RSCAN0RMDF157HL (RSCAN0.RMDF157.UINT8[R_IO_HL])
+#define RSCAN0RMDF157HH (RSCAN0.RMDF157.UINT8[R_IO_HH])
+#define RSCAN0RMID58 (RSCAN0.RMID58.UINT32)
+#define RSCAN0RMID58L (RSCAN0.RMID58.UINT16[R_IO_L])
+#define RSCAN0RMID58LL (RSCAN0.RMID58.UINT8[R_IO_LL])
+#define RSCAN0RMID58LH (RSCAN0.RMID58.UINT8[R_IO_LH])
+#define RSCAN0RMID58H (RSCAN0.RMID58.UINT16[R_IO_H])
+#define RSCAN0RMID58HL (RSCAN0.RMID58.UINT8[R_IO_HL])
+#define RSCAN0RMID58HH (RSCAN0.RMID58.UINT8[R_IO_HH])
+#define RSCAN0RMPTR58 (RSCAN0.RMPTR58.UINT32)
+#define RSCAN0RMPTR58L (RSCAN0.RMPTR58.UINT16[R_IO_L])
+#define RSCAN0RMPTR58LL (RSCAN0.RMPTR58.UINT8[R_IO_LL])
+#define RSCAN0RMPTR58LH (RSCAN0.RMPTR58.UINT8[R_IO_LH])
+#define RSCAN0RMPTR58H (RSCAN0.RMPTR58.UINT16[R_IO_H])
+#define RSCAN0RMPTR58HL (RSCAN0.RMPTR58.UINT8[R_IO_HL])
+#define RSCAN0RMPTR58HH (RSCAN0.RMPTR58.UINT8[R_IO_HH])
+#define RSCAN0RMDF058 (RSCAN0.RMDF058.UINT32)
+#define RSCAN0RMDF058L (RSCAN0.RMDF058.UINT16[R_IO_L])
+#define RSCAN0RMDF058LL (RSCAN0.RMDF058.UINT8[R_IO_LL])
+#define RSCAN0RMDF058LH (RSCAN0.RMDF058.UINT8[R_IO_LH])
+#define RSCAN0RMDF058H (RSCAN0.RMDF058.UINT16[R_IO_H])
+#define RSCAN0RMDF058HL (RSCAN0.RMDF058.UINT8[R_IO_HL])
+#define RSCAN0RMDF058HH (RSCAN0.RMDF058.UINT8[R_IO_HH])
+#define RSCAN0RMDF158 (RSCAN0.RMDF158.UINT32)
+#define RSCAN0RMDF158L (RSCAN0.RMDF158.UINT16[R_IO_L])
+#define RSCAN0RMDF158LL (RSCAN0.RMDF158.UINT8[R_IO_LL])
+#define RSCAN0RMDF158LH (RSCAN0.RMDF158.UINT8[R_IO_LH])
+#define RSCAN0RMDF158H (RSCAN0.RMDF158.UINT16[R_IO_H])
+#define RSCAN0RMDF158HL (RSCAN0.RMDF158.UINT8[R_IO_HL])
+#define RSCAN0RMDF158HH (RSCAN0.RMDF158.UINT8[R_IO_HH])
+#define RSCAN0RMID59 (RSCAN0.RMID59.UINT32)
+#define RSCAN0RMID59L (RSCAN0.RMID59.UINT16[R_IO_L])
+#define RSCAN0RMID59LL (RSCAN0.RMID59.UINT8[R_IO_LL])
+#define RSCAN0RMID59LH (RSCAN0.RMID59.UINT8[R_IO_LH])
+#define RSCAN0RMID59H (RSCAN0.RMID59.UINT16[R_IO_H])
+#define RSCAN0RMID59HL (RSCAN0.RMID59.UINT8[R_IO_HL])
+#define RSCAN0RMID59HH (RSCAN0.RMID59.UINT8[R_IO_HH])
+#define RSCAN0RMPTR59 (RSCAN0.RMPTR59.UINT32)
+#define RSCAN0RMPTR59L (RSCAN0.RMPTR59.UINT16[R_IO_L])
+#define RSCAN0RMPTR59LL (RSCAN0.RMPTR59.UINT8[R_IO_LL])
+#define RSCAN0RMPTR59LH (RSCAN0.RMPTR59.UINT8[R_IO_LH])
+#define RSCAN0RMPTR59H (RSCAN0.RMPTR59.UINT16[R_IO_H])
+#define RSCAN0RMPTR59HL (RSCAN0.RMPTR59.UINT8[R_IO_HL])
+#define RSCAN0RMPTR59HH (RSCAN0.RMPTR59.UINT8[R_IO_HH])
+#define RSCAN0RMDF059 (RSCAN0.RMDF059.UINT32)
+#define RSCAN0RMDF059L (RSCAN0.RMDF059.UINT16[R_IO_L])
+#define RSCAN0RMDF059LL (RSCAN0.RMDF059.UINT8[R_IO_LL])
+#define RSCAN0RMDF059LH (RSCAN0.RMDF059.UINT8[R_IO_LH])
+#define RSCAN0RMDF059H (RSCAN0.RMDF059.UINT16[R_IO_H])
+#define RSCAN0RMDF059HL (RSCAN0.RMDF059.UINT8[R_IO_HL])
+#define RSCAN0RMDF059HH (RSCAN0.RMDF059.UINT8[R_IO_HH])
+#define RSCAN0RMDF159 (RSCAN0.RMDF159.UINT32)
+#define RSCAN0RMDF159L (RSCAN0.RMDF159.UINT16[R_IO_L])
+#define RSCAN0RMDF159LL (RSCAN0.RMDF159.UINT8[R_IO_LL])
+#define RSCAN0RMDF159LH (RSCAN0.RMDF159.UINT8[R_IO_LH])
+#define RSCAN0RMDF159H (RSCAN0.RMDF159.UINT16[R_IO_H])
+#define RSCAN0RMDF159HL (RSCAN0.RMDF159.UINT8[R_IO_HL])
+#define RSCAN0RMDF159HH (RSCAN0.RMDF159.UINT8[R_IO_HH])
+#define RSCAN0RMID60 (RSCAN0.RMID60.UINT32)
+#define RSCAN0RMID60L (RSCAN0.RMID60.UINT16[R_IO_L])
+#define RSCAN0RMID60LL (RSCAN0.RMID60.UINT8[R_IO_LL])
+#define RSCAN0RMID60LH (RSCAN0.RMID60.UINT8[R_IO_LH])
+#define RSCAN0RMID60H (RSCAN0.RMID60.UINT16[R_IO_H])
+#define RSCAN0RMID60HL (RSCAN0.RMID60.UINT8[R_IO_HL])
+#define RSCAN0RMID60HH (RSCAN0.RMID60.UINT8[R_IO_HH])
+#define RSCAN0RMPTR60 (RSCAN0.RMPTR60.UINT32)
+#define RSCAN0RMPTR60L (RSCAN0.RMPTR60.UINT16[R_IO_L])
+#define RSCAN0RMPTR60LL (RSCAN0.RMPTR60.UINT8[R_IO_LL])
+#define RSCAN0RMPTR60LH (RSCAN0.RMPTR60.UINT8[R_IO_LH])
+#define RSCAN0RMPTR60H (RSCAN0.RMPTR60.UINT16[R_IO_H])
+#define RSCAN0RMPTR60HL (RSCAN0.RMPTR60.UINT8[R_IO_HL])
+#define RSCAN0RMPTR60HH (RSCAN0.RMPTR60.UINT8[R_IO_HH])
+#define RSCAN0RMDF060 (RSCAN0.RMDF060.UINT32)
+#define RSCAN0RMDF060L (RSCAN0.RMDF060.UINT16[R_IO_L])
+#define RSCAN0RMDF060LL (RSCAN0.RMDF060.UINT8[R_IO_LL])
+#define RSCAN0RMDF060LH (RSCAN0.RMDF060.UINT8[R_IO_LH])
+#define RSCAN0RMDF060H (RSCAN0.RMDF060.UINT16[R_IO_H])
+#define RSCAN0RMDF060HL (RSCAN0.RMDF060.UINT8[R_IO_HL])
+#define RSCAN0RMDF060HH (RSCAN0.RMDF060.UINT8[R_IO_HH])
+#define RSCAN0RMDF160 (RSCAN0.RMDF160.UINT32)
+#define RSCAN0RMDF160L (RSCAN0.RMDF160.UINT16[R_IO_L])
+#define RSCAN0RMDF160LL (RSCAN0.RMDF160.UINT8[R_IO_LL])
+#define RSCAN0RMDF160LH (RSCAN0.RMDF160.UINT8[R_IO_LH])
+#define RSCAN0RMDF160H (RSCAN0.RMDF160.UINT16[R_IO_H])
+#define RSCAN0RMDF160HL (RSCAN0.RMDF160.UINT8[R_IO_HL])
+#define RSCAN0RMDF160HH (RSCAN0.RMDF160.UINT8[R_IO_HH])
+#define RSCAN0RMID61 (RSCAN0.RMID61.UINT32)
+#define RSCAN0RMID61L (RSCAN0.RMID61.UINT16[R_IO_L])
+#define RSCAN0RMID61LL (RSCAN0.RMID61.UINT8[R_IO_LL])
+#define RSCAN0RMID61LH (RSCAN0.RMID61.UINT8[R_IO_LH])
+#define RSCAN0RMID61H (RSCAN0.RMID61.UINT16[R_IO_H])
+#define RSCAN0RMID61HL (RSCAN0.RMID61.UINT8[R_IO_HL])
+#define RSCAN0RMID61HH (RSCAN0.RMID61.UINT8[R_IO_HH])
+#define RSCAN0RMPTR61 (RSCAN0.RMPTR61.UINT32)
+#define RSCAN0RMPTR61L (RSCAN0.RMPTR61.UINT16[R_IO_L])
+#define RSCAN0RMPTR61LL (RSCAN0.RMPTR61.UINT8[R_IO_LL])
+#define RSCAN0RMPTR61LH (RSCAN0.RMPTR61.UINT8[R_IO_LH])
+#define RSCAN0RMPTR61H (RSCAN0.RMPTR61.UINT16[R_IO_H])
+#define RSCAN0RMPTR61HL (RSCAN0.RMPTR61.UINT8[R_IO_HL])
+#define RSCAN0RMPTR61HH (RSCAN0.RMPTR61.UINT8[R_IO_HH])
+#define RSCAN0RMDF061 (RSCAN0.RMDF061.UINT32)
+#define RSCAN0RMDF061L (RSCAN0.RMDF061.UINT16[R_IO_L])
+#define RSCAN0RMDF061LL (RSCAN0.RMDF061.UINT8[R_IO_LL])
+#define RSCAN0RMDF061LH (RSCAN0.RMDF061.UINT8[R_IO_LH])
+#define RSCAN0RMDF061H (RSCAN0.RMDF061.UINT16[R_IO_H])
+#define RSCAN0RMDF061HL (RSCAN0.RMDF061.UINT8[R_IO_HL])
+#define RSCAN0RMDF061HH (RSCAN0.RMDF061.UINT8[R_IO_HH])
+#define RSCAN0RMDF161 (RSCAN0.RMDF161.UINT32)
+#define RSCAN0RMDF161L (RSCAN0.RMDF161.UINT16[R_IO_L])
+#define RSCAN0RMDF161LL (RSCAN0.RMDF161.UINT8[R_IO_LL])
+#define RSCAN0RMDF161LH (RSCAN0.RMDF161.UINT8[R_IO_LH])
+#define RSCAN0RMDF161H (RSCAN0.RMDF161.UINT16[R_IO_H])
+#define RSCAN0RMDF161HL (RSCAN0.RMDF161.UINT8[R_IO_HL])
+#define RSCAN0RMDF161HH (RSCAN0.RMDF161.UINT8[R_IO_HH])
+#define RSCAN0RMID62 (RSCAN0.RMID62.UINT32)
+#define RSCAN0RMID62L (RSCAN0.RMID62.UINT16[R_IO_L])
+#define RSCAN0RMID62LL (RSCAN0.RMID62.UINT8[R_IO_LL])
+#define RSCAN0RMID62LH (RSCAN0.RMID62.UINT8[R_IO_LH])
+#define RSCAN0RMID62H (RSCAN0.RMID62.UINT16[R_IO_H])
+#define RSCAN0RMID62HL (RSCAN0.RMID62.UINT8[R_IO_HL])
+#define RSCAN0RMID62HH (RSCAN0.RMID62.UINT8[R_IO_HH])
+#define RSCAN0RMPTR62 (RSCAN0.RMPTR62.UINT32)
+#define RSCAN0RMPTR62L (RSCAN0.RMPTR62.UINT16[R_IO_L])
+#define RSCAN0RMPTR62LL (RSCAN0.RMPTR62.UINT8[R_IO_LL])
+#define RSCAN0RMPTR62LH (RSCAN0.RMPTR62.UINT8[R_IO_LH])
+#define RSCAN0RMPTR62H (RSCAN0.RMPTR62.UINT16[R_IO_H])
+#define RSCAN0RMPTR62HL (RSCAN0.RMPTR62.UINT8[R_IO_HL])
+#define RSCAN0RMPTR62HH (RSCAN0.RMPTR62.UINT8[R_IO_HH])
+#define RSCAN0RMDF062 (RSCAN0.RMDF062.UINT32)
+#define RSCAN0RMDF062L (RSCAN0.RMDF062.UINT16[R_IO_L])
+#define RSCAN0RMDF062LL (RSCAN0.RMDF062.UINT8[R_IO_LL])
+#define RSCAN0RMDF062LH (RSCAN0.RMDF062.UINT8[R_IO_LH])
+#define RSCAN0RMDF062H (RSCAN0.RMDF062.UINT16[R_IO_H])
+#define RSCAN0RMDF062HL (RSCAN0.RMDF062.UINT8[R_IO_HL])
+#define RSCAN0RMDF062HH (RSCAN0.RMDF062.UINT8[R_IO_HH])
+#define RSCAN0RMDF162 (RSCAN0.RMDF162.UINT32)
+#define RSCAN0RMDF162L (RSCAN0.RMDF162.UINT16[R_IO_L])
+#define RSCAN0RMDF162LL (RSCAN0.RMDF162.UINT8[R_IO_LL])
+#define RSCAN0RMDF162LH (RSCAN0.RMDF162.UINT8[R_IO_LH])
+#define RSCAN0RMDF162H (RSCAN0.RMDF162.UINT16[R_IO_H])
+#define RSCAN0RMDF162HL (RSCAN0.RMDF162.UINT8[R_IO_HL])
+#define RSCAN0RMDF162HH (RSCAN0.RMDF162.UINT8[R_IO_HH])
+#define RSCAN0RMID63 (RSCAN0.RMID63.UINT32)
+#define RSCAN0RMID63L (RSCAN0.RMID63.UINT16[R_IO_L])
+#define RSCAN0RMID63LL (RSCAN0.RMID63.UINT8[R_IO_LL])
+#define RSCAN0RMID63LH (RSCAN0.RMID63.UINT8[R_IO_LH])
+#define RSCAN0RMID63H (RSCAN0.RMID63.UINT16[R_IO_H])
+#define RSCAN0RMID63HL (RSCAN0.RMID63.UINT8[R_IO_HL])
+#define RSCAN0RMID63HH (RSCAN0.RMID63.UINT8[R_IO_HH])
+#define RSCAN0RMPTR63 (RSCAN0.RMPTR63.UINT32)
+#define RSCAN0RMPTR63L (RSCAN0.RMPTR63.UINT16[R_IO_L])
+#define RSCAN0RMPTR63LL (RSCAN0.RMPTR63.UINT8[R_IO_LL])
+#define RSCAN0RMPTR63LH (RSCAN0.RMPTR63.UINT8[R_IO_LH])
+#define RSCAN0RMPTR63H (RSCAN0.RMPTR63.UINT16[R_IO_H])
+#define RSCAN0RMPTR63HL (RSCAN0.RMPTR63.UINT8[R_IO_HL])
+#define RSCAN0RMPTR63HH (RSCAN0.RMPTR63.UINT8[R_IO_HH])
+#define RSCAN0RMDF063 (RSCAN0.RMDF063.UINT32)
+#define RSCAN0RMDF063L (RSCAN0.RMDF063.UINT16[R_IO_L])
+#define RSCAN0RMDF063LL (RSCAN0.RMDF063.UINT8[R_IO_LL])
+#define RSCAN0RMDF063LH (RSCAN0.RMDF063.UINT8[R_IO_LH])
+#define RSCAN0RMDF063H (RSCAN0.RMDF063.UINT16[R_IO_H])
+#define RSCAN0RMDF063HL (RSCAN0.RMDF063.UINT8[R_IO_HL])
+#define RSCAN0RMDF063HH (RSCAN0.RMDF063.UINT8[R_IO_HH])
+#define RSCAN0RMDF163 (RSCAN0.RMDF163.UINT32)
+#define RSCAN0RMDF163L (RSCAN0.RMDF163.UINT16[R_IO_L])
+#define RSCAN0RMDF163LL (RSCAN0.RMDF163.UINT8[R_IO_LL])
+#define RSCAN0RMDF163LH (RSCAN0.RMDF163.UINT8[R_IO_LH])
+#define RSCAN0RMDF163H (RSCAN0.RMDF163.UINT16[R_IO_H])
+#define RSCAN0RMDF163HL (RSCAN0.RMDF163.UINT8[R_IO_HL])
+#define RSCAN0RMDF163HH (RSCAN0.RMDF163.UINT8[R_IO_HH])
+#define RSCAN0RMID64 (RSCAN0.RMID64.UINT32)
+#define RSCAN0RMID64L (RSCAN0.RMID64.UINT16[R_IO_L])
+#define RSCAN0RMID64LL (RSCAN0.RMID64.UINT8[R_IO_LL])
+#define RSCAN0RMID64LH (RSCAN0.RMID64.UINT8[R_IO_LH])
+#define RSCAN0RMID64H (RSCAN0.RMID64.UINT16[R_IO_H])
+#define RSCAN0RMID64HL (RSCAN0.RMID64.UINT8[R_IO_HL])
+#define RSCAN0RMID64HH (RSCAN0.RMID64.UINT8[R_IO_HH])
+#define RSCAN0RMPTR64 (RSCAN0.RMPTR64.UINT32)
+#define RSCAN0RMPTR64L (RSCAN0.RMPTR64.UINT16[R_IO_L])
+#define RSCAN0RMPTR64LL (RSCAN0.RMPTR64.UINT8[R_IO_LL])
+#define RSCAN0RMPTR64LH (RSCAN0.RMPTR64.UINT8[R_IO_LH])
+#define RSCAN0RMPTR64H (RSCAN0.RMPTR64.UINT16[R_IO_H])
+#define RSCAN0RMPTR64HL (RSCAN0.RMPTR64.UINT8[R_IO_HL])
+#define RSCAN0RMPTR64HH (RSCAN0.RMPTR64.UINT8[R_IO_HH])
+#define RSCAN0RMDF064 (RSCAN0.RMDF064.UINT32)
+#define RSCAN0RMDF064L (RSCAN0.RMDF064.UINT16[R_IO_L])
+#define RSCAN0RMDF064LL (RSCAN0.RMDF064.UINT8[R_IO_LL])
+#define RSCAN0RMDF064LH (RSCAN0.RMDF064.UINT8[R_IO_LH])
+#define RSCAN0RMDF064H (RSCAN0.RMDF064.UINT16[R_IO_H])
+#define RSCAN0RMDF064HL (RSCAN0.RMDF064.UINT8[R_IO_HL])
+#define RSCAN0RMDF064HH (RSCAN0.RMDF064.UINT8[R_IO_HH])
+#define RSCAN0RMDF164 (RSCAN0.RMDF164.UINT32)
+#define RSCAN0RMDF164L (RSCAN0.RMDF164.UINT16[R_IO_L])
+#define RSCAN0RMDF164LL (RSCAN0.RMDF164.UINT8[R_IO_LL])
+#define RSCAN0RMDF164LH (RSCAN0.RMDF164.UINT8[R_IO_LH])
+#define RSCAN0RMDF164H (RSCAN0.RMDF164.UINT16[R_IO_H])
+#define RSCAN0RMDF164HL (RSCAN0.RMDF164.UINT8[R_IO_HL])
+#define RSCAN0RMDF164HH (RSCAN0.RMDF164.UINT8[R_IO_HH])
+#define RSCAN0RMID65 (RSCAN0.RMID65.UINT32)
+#define RSCAN0RMID65L (RSCAN0.RMID65.UINT16[R_IO_L])
+#define RSCAN0RMID65LL (RSCAN0.RMID65.UINT8[R_IO_LL])
+#define RSCAN0RMID65LH (RSCAN0.RMID65.UINT8[R_IO_LH])
+#define RSCAN0RMID65H (RSCAN0.RMID65.UINT16[R_IO_H])
+#define RSCAN0RMID65HL (RSCAN0.RMID65.UINT8[R_IO_HL])
+#define RSCAN0RMID65HH (RSCAN0.RMID65.UINT8[R_IO_HH])
+#define RSCAN0RMPTR65 (RSCAN0.RMPTR65.UINT32)
+#define RSCAN0RMPTR65L (RSCAN0.RMPTR65.UINT16[R_IO_L])
+#define RSCAN0RMPTR65LL (RSCAN0.RMPTR65.UINT8[R_IO_LL])
+#define RSCAN0RMPTR65LH (RSCAN0.RMPTR65.UINT8[R_IO_LH])
+#define RSCAN0RMPTR65H (RSCAN0.RMPTR65.UINT16[R_IO_H])
+#define RSCAN0RMPTR65HL (RSCAN0.RMPTR65.UINT8[R_IO_HL])
+#define RSCAN0RMPTR65HH (RSCAN0.RMPTR65.UINT8[R_IO_HH])
+#define RSCAN0RMDF065 (RSCAN0.RMDF065.UINT32)
+#define RSCAN0RMDF065L (RSCAN0.RMDF065.UINT16[R_IO_L])
+#define RSCAN0RMDF065LL (RSCAN0.RMDF065.UINT8[R_IO_LL])
+#define RSCAN0RMDF065LH (RSCAN0.RMDF065.UINT8[R_IO_LH])
+#define RSCAN0RMDF065H (RSCAN0.RMDF065.UINT16[R_IO_H])
+#define RSCAN0RMDF065HL (RSCAN0.RMDF065.UINT8[R_IO_HL])
+#define RSCAN0RMDF065HH (RSCAN0.RMDF065.UINT8[R_IO_HH])
+#define RSCAN0RMDF165 (RSCAN0.RMDF165.UINT32)
+#define RSCAN0RMDF165L (RSCAN0.RMDF165.UINT16[R_IO_L])
+#define RSCAN0RMDF165LL (RSCAN0.RMDF165.UINT8[R_IO_LL])
+#define RSCAN0RMDF165LH (RSCAN0.RMDF165.UINT8[R_IO_LH])
+#define RSCAN0RMDF165H (RSCAN0.RMDF165.UINT16[R_IO_H])
+#define RSCAN0RMDF165HL (RSCAN0.RMDF165.UINT8[R_IO_HL])
+#define RSCAN0RMDF165HH (RSCAN0.RMDF165.UINT8[R_IO_HH])
+#define RSCAN0RMID66 (RSCAN0.RMID66.UINT32)
+#define RSCAN0RMID66L (RSCAN0.RMID66.UINT16[R_IO_L])
+#define RSCAN0RMID66LL (RSCAN0.RMID66.UINT8[R_IO_LL])
+#define RSCAN0RMID66LH (RSCAN0.RMID66.UINT8[R_IO_LH])
+#define RSCAN0RMID66H (RSCAN0.RMID66.UINT16[R_IO_H])
+#define RSCAN0RMID66HL (RSCAN0.RMID66.UINT8[R_IO_HL])
+#define RSCAN0RMID66HH (RSCAN0.RMID66.UINT8[R_IO_HH])
+#define RSCAN0RMPTR66 (RSCAN0.RMPTR66.UINT32)
+#define RSCAN0RMPTR66L (RSCAN0.RMPTR66.UINT16[R_IO_L])
+#define RSCAN0RMPTR66LL (RSCAN0.RMPTR66.UINT8[R_IO_LL])
+#define RSCAN0RMPTR66LH (RSCAN0.RMPTR66.UINT8[R_IO_LH])
+#define RSCAN0RMPTR66H (RSCAN0.RMPTR66.UINT16[R_IO_H])
+#define RSCAN0RMPTR66HL (RSCAN0.RMPTR66.UINT8[R_IO_HL])
+#define RSCAN0RMPTR66HH (RSCAN0.RMPTR66.UINT8[R_IO_HH])
+#define RSCAN0RMDF066 (RSCAN0.RMDF066.UINT32)
+#define RSCAN0RMDF066L (RSCAN0.RMDF066.UINT16[R_IO_L])
+#define RSCAN0RMDF066LL (RSCAN0.RMDF066.UINT8[R_IO_LL])
+#define RSCAN0RMDF066LH (RSCAN0.RMDF066.UINT8[R_IO_LH])
+#define RSCAN0RMDF066H (RSCAN0.RMDF066.UINT16[R_IO_H])
+#define RSCAN0RMDF066HL (RSCAN0.RMDF066.UINT8[R_IO_HL])
+#define RSCAN0RMDF066HH (RSCAN0.RMDF066.UINT8[R_IO_HH])
+#define RSCAN0RMDF166 (RSCAN0.RMDF166.UINT32)
+#define RSCAN0RMDF166L (RSCAN0.RMDF166.UINT16[R_IO_L])
+#define RSCAN0RMDF166LL (RSCAN0.RMDF166.UINT8[R_IO_LL])
+#define RSCAN0RMDF166LH (RSCAN0.RMDF166.UINT8[R_IO_LH])
+#define RSCAN0RMDF166H (RSCAN0.RMDF166.UINT16[R_IO_H])
+#define RSCAN0RMDF166HL (RSCAN0.RMDF166.UINT8[R_IO_HL])
+#define RSCAN0RMDF166HH (RSCAN0.RMDF166.UINT8[R_IO_HH])
+#define RSCAN0RMID67 (RSCAN0.RMID67.UINT32)
+#define RSCAN0RMID67L (RSCAN0.RMID67.UINT16[R_IO_L])
+#define RSCAN0RMID67LL (RSCAN0.RMID67.UINT8[R_IO_LL])
+#define RSCAN0RMID67LH (RSCAN0.RMID67.UINT8[R_IO_LH])
+#define RSCAN0RMID67H (RSCAN0.RMID67.UINT16[R_IO_H])
+#define RSCAN0RMID67HL (RSCAN0.RMID67.UINT8[R_IO_HL])
+#define RSCAN0RMID67HH (RSCAN0.RMID67.UINT8[R_IO_HH])
+#define RSCAN0RMPTR67 (RSCAN0.RMPTR67.UINT32)
+#define RSCAN0RMPTR67L (RSCAN0.RMPTR67.UINT16[R_IO_L])
+#define RSCAN0RMPTR67LL (RSCAN0.RMPTR67.UINT8[R_IO_LL])
+#define RSCAN0RMPTR67LH (RSCAN0.RMPTR67.UINT8[R_IO_LH])
+#define RSCAN0RMPTR67H (RSCAN0.RMPTR67.UINT16[R_IO_H])
+#define RSCAN0RMPTR67HL (RSCAN0.RMPTR67.UINT8[R_IO_HL])
+#define RSCAN0RMPTR67HH (RSCAN0.RMPTR67.UINT8[R_IO_HH])
+#define RSCAN0RMDF067 (RSCAN0.RMDF067.UINT32)
+#define RSCAN0RMDF067L (RSCAN0.RMDF067.UINT16[R_IO_L])
+#define RSCAN0RMDF067LL (RSCAN0.RMDF067.UINT8[R_IO_LL])
+#define RSCAN0RMDF067LH (RSCAN0.RMDF067.UINT8[R_IO_LH])
+#define RSCAN0RMDF067H (RSCAN0.RMDF067.UINT16[R_IO_H])
+#define RSCAN0RMDF067HL (RSCAN0.RMDF067.UINT8[R_IO_HL])
+#define RSCAN0RMDF067HH (RSCAN0.RMDF067.UINT8[R_IO_HH])
+#define RSCAN0RMDF167 (RSCAN0.RMDF167.UINT32)
+#define RSCAN0RMDF167L (RSCAN0.RMDF167.UINT16[R_IO_L])
+#define RSCAN0RMDF167LL (RSCAN0.RMDF167.UINT8[R_IO_LL])
+#define RSCAN0RMDF167LH (RSCAN0.RMDF167.UINT8[R_IO_LH])
+#define RSCAN0RMDF167H (RSCAN0.RMDF167.UINT16[R_IO_H])
+#define RSCAN0RMDF167HL (RSCAN0.RMDF167.UINT8[R_IO_HL])
+#define RSCAN0RMDF167HH (RSCAN0.RMDF167.UINT8[R_IO_HH])
+#define RSCAN0RMID68 (RSCAN0.RMID68.UINT32)
+#define RSCAN0RMID68L (RSCAN0.RMID68.UINT16[R_IO_L])
+#define RSCAN0RMID68LL (RSCAN0.RMID68.UINT8[R_IO_LL])
+#define RSCAN0RMID68LH (RSCAN0.RMID68.UINT8[R_IO_LH])
+#define RSCAN0RMID68H (RSCAN0.RMID68.UINT16[R_IO_H])
+#define RSCAN0RMID68HL (RSCAN0.RMID68.UINT8[R_IO_HL])
+#define RSCAN0RMID68HH (RSCAN0.RMID68.UINT8[R_IO_HH])
+#define RSCAN0RMPTR68 (RSCAN0.RMPTR68.UINT32)
+#define RSCAN0RMPTR68L (RSCAN0.RMPTR68.UINT16[R_IO_L])
+#define RSCAN0RMPTR68LL (RSCAN0.RMPTR68.UINT8[R_IO_LL])
+#define RSCAN0RMPTR68LH (RSCAN0.RMPTR68.UINT8[R_IO_LH])
+#define RSCAN0RMPTR68H (RSCAN0.RMPTR68.UINT16[R_IO_H])
+#define RSCAN0RMPTR68HL (RSCAN0.RMPTR68.UINT8[R_IO_HL])
+#define RSCAN0RMPTR68HH (RSCAN0.RMPTR68.UINT8[R_IO_HH])
+#define RSCAN0RMDF068 (RSCAN0.RMDF068.UINT32)
+#define RSCAN0RMDF068L (RSCAN0.RMDF068.UINT16[R_IO_L])
+#define RSCAN0RMDF068LL (RSCAN0.RMDF068.UINT8[R_IO_LL])
+#define RSCAN0RMDF068LH (RSCAN0.RMDF068.UINT8[R_IO_LH])
+#define RSCAN0RMDF068H (RSCAN0.RMDF068.UINT16[R_IO_H])
+#define RSCAN0RMDF068HL (RSCAN0.RMDF068.UINT8[R_IO_HL])
+#define RSCAN0RMDF068HH (RSCAN0.RMDF068.UINT8[R_IO_HH])
+#define RSCAN0RMDF168 (RSCAN0.RMDF168.UINT32)
+#define RSCAN0RMDF168L (RSCAN0.RMDF168.UINT16[R_IO_L])
+#define RSCAN0RMDF168LL (RSCAN0.RMDF168.UINT8[R_IO_LL])
+#define RSCAN0RMDF168LH (RSCAN0.RMDF168.UINT8[R_IO_LH])
+#define RSCAN0RMDF168H (RSCAN0.RMDF168.UINT16[R_IO_H])
+#define RSCAN0RMDF168HL (RSCAN0.RMDF168.UINT8[R_IO_HL])
+#define RSCAN0RMDF168HH (RSCAN0.RMDF168.UINT8[R_IO_HH])
+#define RSCAN0RMID69 (RSCAN0.RMID69.UINT32)
+#define RSCAN0RMID69L (RSCAN0.RMID69.UINT16[R_IO_L])
+#define RSCAN0RMID69LL (RSCAN0.RMID69.UINT8[R_IO_LL])
+#define RSCAN0RMID69LH (RSCAN0.RMID69.UINT8[R_IO_LH])
+#define RSCAN0RMID69H (RSCAN0.RMID69.UINT16[R_IO_H])
+#define RSCAN0RMID69HL (RSCAN0.RMID69.UINT8[R_IO_HL])
+#define RSCAN0RMID69HH (RSCAN0.RMID69.UINT8[R_IO_HH])
+#define RSCAN0RMPTR69 (RSCAN0.RMPTR69.UINT32)
+#define RSCAN0RMPTR69L (RSCAN0.RMPTR69.UINT16[R_IO_L])
+#define RSCAN0RMPTR69LL (RSCAN0.RMPTR69.UINT8[R_IO_LL])
+#define RSCAN0RMPTR69LH (RSCAN0.RMPTR69.UINT8[R_IO_LH])
+#define RSCAN0RMPTR69H (RSCAN0.RMPTR69.UINT16[R_IO_H])
+#define RSCAN0RMPTR69HL (RSCAN0.RMPTR69.UINT8[R_IO_HL])
+#define RSCAN0RMPTR69HH (RSCAN0.RMPTR69.UINT8[R_IO_HH])
+#define RSCAN0RMDF069 (RSCAN0.RMDF069.UINT32)
+#define RSCAN0RMDF069L (RSCAN0.RMDF069.UINT16[R_IO_L])
+#define RSCAN0RMDF069LL (RSCAN0.RMDF069.UINT8[R_IO_LL])
+#define RSCAN0RMDF069LH (RSCAN0.RMDF069.UINT8[R_IO_LH])
+#define RSCAN0RMDF069H (RSCAN0.RMDF069.UINT16[R_IO_H])
+#define RSCAN0RMDF069HL (RSCAN0.RMDF069.UINT8[R_IO_HL])
+#define RSCAN0RMDF069HH (RSCAN0.RMDF069.UINT8[R_IO_HH])
+#define RSCAN0RMDF169 (RSCAN0.RMDF169.UINT32)
+#define RSCAN0RMDF169L (RSCAN0.RMDF169.UINT16[R_IO_L])
+#define RSCAN0RMDF169LL (RSCAN0.RMDF169.UINT8[R_IO_LL])
+#define RSCAN0RMDF169LH (RSCAN0.RMDF169.UINT8[R_IO_LH])
+#define RSCAN0RMDF169H (RSCAN0.RMDF169.UINT16[R_IO_H])
+#define RSCAN0RMDF169HL (RSCAN0.RMDF169.UINT8[R_IO_HL])
+#define RSCAN0RMDF169HH (RSCAN0.RMDF169.UINT8[R_IO_HH])
+#define RSCAN0RMID70 (RSCAN0.RMID70.UINT32)
+#define RSCAN0RMID70L (RSCAN0.RMID70.UINT16[R_IO_L])
+#define RSCAN0RMID70LL (RSCAN0.RMID70.UINT8[R_IO_LL])
+#define RSCAN0RMID70LH (RSCAN0.RMID70.UINT8[R_IO_LH])
+#define RSCAN0RMID70H (RSCAN0.RMID70.UINT16[R_IO_H])
+#define RSCAN0RMID70HL (RSCAN0.RMID70.UINT8[R_IO_HL])
+#define RSCAN0RMID70HH (RSCAN0.RMID70.UINT8[R_IO_HH])
+#define RSCAN0RMPTR70 (RSCAN0.RMPTR70.UINT32)
+#define RSCAN0RMPTR70L (RSCAN0.RMPTR70.UINT16[R_IO_L])
+#define RSCAN0RMPTR70LL (RSCAN0.RMPTR70.UINT8[R_IO_LL])
+#define RSCAN0RMPTR70LH (RSCAN0.RMPTR70.UINT8[R_IO_LH])
+#define RSCAN0RMPTR70H (RSCAN0.RMPTR70.UINT16[R_IO_H])
+#define RSCAN0RMPTR70HL (RSCAN0.RMPTR70.UINT8[R_IO_HL])
+#define RSCAN0RMPTR70HH (RSCAN0.RMPTR70.UINT8[R_IO_HH])
+#define RSCAN0RMDF070 (RSCAN0.RMDF070.UINT32)
+#define RSCAN0RMDF070L (RSCAN0.RMDF070.UINT16[R_IO_L])
+#define RSCAN0RMDF070LL (RSCAN0.RMDF070.UINT8[R_IO_LL])
+#define RSCAN0RMDF070LH (RSCAN0.RMDF070.UINT8[R_IO_LH])
+#define RSCAN0RMDF070H (RSCAN0.RMDF070.UINT16[R_IO_H])
+#define RSCAN0RMDF070HL (RSCAN0.RMDF070.UINT8[R_IO_HL])
+#define RSCAN0RMDF070HH (RSCAN0.RMDF070.UINT8[R_IO_HH])
+#define RSCAN0RMDF170 (RSCAN0.RMDF170.UINT32)
+#define RSCAN0RMDF170L (RSCAN0.RMDF170.UINT16[R_IO_L])
+#define RSCAN0RMDF170LL (RSCAN0.RMDF170.UINT8[R_IO_LL])
+#define RSCAN0RMDF170LH (RSCAN0.RMDF170.UINT8[R_IO_LH])
+#define RSCAN0RMDF170H (RSCAN0.RMDF170.UINT16[R_IO_H])
+#define RSCAN0RMDF170HL (RSCAN0.RMDF170.UINT8[R_IO_HL])
+#define RSCAN0RMDF170HH (RSCAN0.RMDF170.UINT8[R_IO_HH])
+#define RSCAN0RMID71 (RSCAN0.RMID71.UINT32)
+#define RSCAN0RMID71L (RSCAN0.RMID71.UINT16[R_IO_L])
+#define RSCAN0RMID71LL (RSCAN0.RMID71.UINT8[R_IO_LL])
+#define RSCAN0RMID71LH (RSCAN0.RMID71.UINT8[R_IO_LH])
+#define RSCAN0RMID71H (RSCAN0.RMID71.UINT16[R_IO_H])
+#define RSCAN0RMID71HL (RSCAN0.RMID71.UINT8[R_IO_HL])
+#define RSCAN0RMID71HH (RSCAN0.RMID71.UINT8[R_IO_HH])
+#define RSCAN0RMPTR71 (RSCAN0.RMPTR71.UINT32)
+#define RSCAN0RMPTR71L (RSCAN0.RMPTR71.UINT16[R_IO_L])
+#define RSCAN0RMPTR71LL (RSCAN0.RMPTR71.UINT8[R_IO_LL])
+#define RSCAN0RMPTR71LH (RSCAN0.RMPTR71.UINT8[R_IO_LH])
+#define RSCAN0RMPTR71H (RSCAN0.RMPTR71.UINT16[R_IO_H])
+#define RSCAN0RMPTR71HL (RSCAN0.RMPTR71.UINT8[R_IO_HL])
+#define RSCAN0RMPTR71HH (RSCAN0.RMPTR71.UINT8[R_IO_HH])
+#define RSCAN0RMDF071 (RSCAN0.RMDF071.UINT32)
+#define RSCAN0RMDF071L (RSCAN0.RMDF071.UINT16[R_IO_L])
+#define RSCAN0RMDF071LL (RSCAN0.RMDF071.UINT8[R_IO_LL])
+#define RSCAN0RMDF071LH (RSCAN0.RMDF071.UINT8[R_IO_LH])
+#define RSCAN0RMDF071H (RSCAN0.RMDF071.UINT16[R_IO_H])
+#define RSCAN0RMDF071HL (RSCAN0.RMDF071.UINT8[R_IO_HL])
+#define RSCAN0RMDF071HH (RSCAN0.RMDF071.UINT8[R_IO_HH])
+#define RSCAN0RMDF171 (RSCAN0.RMDF171.UINT32)
+#define RSCAN0RMDF171L (RSCAN0.RMDF171.UINT16[R_IO_L])
+#define RSCAN0RMDF171LL (RSCAN0.RMDF171.UINT8[R_IO_LL])
+#define RSCAN0RMDF171LH (RSCAN0.RMDF171.UINT8[R_IO_LH])
+#define RSCAN0RMDF171H (RSCAN0.RMDF171.UINT16[R_IO_H])
+#define RSCAN0RMDF171HL (RSCAN0.RMDF171.UINT8[R_IO_HL])
+#define RSCAN0RMDF171HH (RSCAN0.RMDF171.UINT8[R_IO_HH])
+#define RSCAN0RMID72 (RSCAN0.RMID72.UINT32)
+#define RSCAN0RMID72L (RSCAN0.RMID72.UINT16[R_IO_L])
+#define RSCAN0RMID72LL (RSCAN0.RMID72.UINT8[R_IO_LL])
+#define RSCAN0RMID72LH (RSCAN0.RMID72.UINT8[R_IO_LH])
+#define RSCAN0RMID72H (RSCAN0.RMID72.UINT16[R_IO_H])
+#define RSCAN0RMID72HL (RSCAN0.RMID72.UINT8[R_IO_HL])
+#define RSCAN0RMID72HH (RSCAN0.RMID72.UINT8[R_IO_HH])
+#define RSCAN0RMPTR72 (RSCAN0.RMPTR72.UINT32)
+#define RSCAN0RMPTR72L (RSCAN0.RMPTR72.UINT16[R_IO_L])
+#define RSCAN0RMPTR72LL (RSCAN0.RMPTR72.UINT8[R_IO_LL])
+#define RSCAN0RMPTR72LH (RSCAN0.RMPTR72.UINT8[R_IO_LH])
+#define RSCAN0RMPTR72H (RSCAN0.RMPTR72.UINT16[R_IO_H])
+#define RSCAN0RMPTR72HL (RSCAN0.RMPTR72.UINT8[R_IO_HL])
+#define RSCAN0RMPTR72HH (RSCAN0.RMPTR72.UINT8[R_IO_HH])
+#define RSCAN0RMDF072 (RSCAN0.RMDF072.UINT32)
+#define RSCAN0RMDF072L (RSCAN0.RMDF072.UINT16[R_IO_L])
+#define RSCAN0RMDF072LL (RSCAN0.RMDF072.UINT8[R_IO_LL])
+#define RSCAN0RMDF072LH (RSCAN0.RMDF072.UINT8[R_IO_LH])
+#define RSCAN0RMDF072H (RSCAN0.RMDF072.UINT16[R_IO_H])
+#define RSCAN0RMDF072HL (RSCAN0.RMDF072.UINT8[R_IO_HL])
+#define RSCAN0RMDF072HH (RSCAN0.RMDF072.UINT8[R_IO_HH])
+#define RSCAN0RMDF172 (RSCAN0.RMDF172.UINT32)
+#define RSCAN0RMDF172L (RSCAN0.RMDF172.UINT16[R_IO_L])
+#define RSCAN0RMDF172LL (RSCAN0.RMDF172.UINT8[R_IO_LL])
+#define RSCAN0RMDF172LH (RSCAN0.RMDF172.UINT8[R_IO_LH])
+#define RSCAN0RMDF172H (RSCAN0.RMDF172.UINT16[R_IO_H])
+#define RSCAN0RMDF172HL (RSCAN0.RMDF172.UINT8[R_IO_HL])
+#define RSCAN0RMDF172HH (RSCAN0.RMDF172.UINT8[R_IO_HH])
+#define RSCAN0RMID73 (RSCAN0.RMID73.UINT32)
+#define RSCAN0RMID73L (RSCAN0.RMID73.UINT16[R_IO_L])
+#define RSCAN0RMID73LL (RSCAN0.RMID73.UINT8[R_IO_LL])
+#define RSCAN0RMID73LH (RSCAN0.RMID73.UINT8[R_IO_LH])
+#define RSCAN0RMID73H (RSCAN0.RMID73.UINT16[R_IO_H])
+#define RSCAN0RMID73HL (RSCAN0.RMID73.UINT8[R_IO_HL])
+#define RSCAN0RMID73HH (RSCAN0.RMID73.UINT8[R_IO_HH])
+#define RSCAN0RMPTR73 (RSCAN0.RMPTR73.UINT32)
+#define RSCAN0RMPTR73L (RSCAN0.RMPTR73.UINT16[R_IO_L])
+#define RSCAN0RMPTR73LL (RSCAN0.RMPTR73.UINT8[R_IO_LL])
+#define RSCAN0RMPTR73LH (RSCAN0.RMPTR73.UINT8[R_IO_LH])
+#define RSCAN0RMPTR73H (RSCAN0.RMPTR73.UINT16[R_IO_H])
+#define RSCAN0RMPTR73HL (RSCAN0.RMPTR73.UINT8[R_IO_HL])
+#define RSCAN0RMPTR73HH (RSCAN0.RMPTR73.UINT8[R_IO_HH])
+#define RSCAN0RMDF073 (RSCAN0.RMDF073.UINT32)
+#define RSCAN0RMDF073L (RSCAN0.RMDF073.UINT16[R_IO_L])
+#define RSCAN0RMDF073LL (RSCAN0.RMDF073.UINT8[R_IO_LL])
+#define RSCAN0RMDF073LH (RSCAN0.RMDF073.UINT8[R_IO_LH])
+#define RSCAN0RMDF073H (RSCAN0.RMDF073.UINT16[R_IO_H])
+#define RSCAN0RMDF073HL (RSCAN0.RMDF073.UINT8[R_IO_HL])
+#define RSCAN0RMDF073HH (RSCAN0.RMDF073.UINT8[R_IO_HH])
+#define RSCAN0RMDF173 (RSCAN0.RMDF173.UINT32)
+#define RSCAN0RMDF173L (RSCAN0.RMDF173.UINT16[R_IO_L])
+#define RSCAN0RMDF173LL (RSCAN0.RMDF173.UINT8[R_IO_LL])
+#define RSCAN0RMDF173LH (RSCAN0.RMDF173.UINT8[R_IO_LH])
+#define RSCAN0RMDF173H (RSCAN0.RMDF173.UINT16[R_IO_H])
+#define RSCAN0RMDF173HL (RSCAN0.RMDF173.UINT8[R_IO_HL])
+#define RSCAN0RMDF173HH (RSCAN0.RMDF173.UINT8[R_IO_HH])
+#define RSCAN0RMID74 (RSCAN0.RMID74.UINT32)
+#define RSCAN0RMID74L (RSCAN0.RMID74.UINT16[R_IO_L])
+#define RSCAN0RMID74LL (RSCAN0.RMID74.UINT8[R_IO_LL])
+#define RSCAN0RMID74LH (RSCAN0.RMID74.UINT8[R_IO_LH])
+#define RSCAN0RMID74H (RSCAN0.RMID74.UINT16[R_IO_H])
+#define RSCAN0RMID74HL (RSCAN0.RMID74.UINT8[R_IO_HL])
+#define RSCAN0RMID74HH (RSCAN0.RMID74.UINT8[R_IO_HH])
+#define RSCAN0RMPTR74 (RSCAN0.RMPTR74.UINT32)
+#define RSCAN0RMPTR74L (RSCAN0.RMPTR74.UINT16[R_IO_L])
+#define RSCAN0RMPTR74LL (RSCAN0.RMPTR74.UINT8[R_IO_LL])
+#define RSCAN0RMPTR74LH (RSCAN0.RMPTR74.UINT8[R_IO_LH])
+#define RSCAN0RMPTR74H (RSCAN0.RMPTR74.UINT16[R_IO_H])
+#define RSCAN0RMPTR74HL (RSCAN0.RMPTR74.UINT8[R_IO_HL])
+#define RSCAN0RMPTR74HH (RSCAN0.RMPTR74.UINT8[R_IO_HH])
+#define RSCAN0RMDF074 (RSCAN0.RMDF074.UINT32)
+#define RSCAN0RMDF074L (RSCAN0.RMDF074.UINT16[R_IO_L])
+#define RSCAN0RMDF074LL (RSCAN0.RMDF074.UINT8[R_IO_LL])
+#define RSCAN0RMDF074LH (RSCAN0.RMDF074.UINT8[R_IO_LH])
+#define RSCAN0RMDF074H (RSCAN0.RMDF074.UINT16[R_IO_H])
+#define RSCAN0RMDF074HL (RSCAN0.RMDF074.UINT8[R_IO_HL])
+#define RSCAN0RMDF074HH (RSCAN0.RMDF074.UINT8[R_IO_HH])
+#define RSCAN0RMDF174 (RSCAN0.RMDF174.UINT32)
+#define RSCAN0RMDF174L (RSCAN0.RMDF174.UINT16[R_IO_L])
+#define RSCAN0RMDF174LL (RSCAN0.RMDF174.UINT8[R_IO_LL])
+#define RSCAN0RMDF174LH (RSCAN0.RMDF174.UINT8[R_IO_LH])
+#define RSCAN0RMDF174H (RSCAN0.RMDF174.UINT16[R_IO_H])
+#define RSCAN0RMDF174HL (RSCAN0.RMDF174.UINT8[R_IO_HL])
+#define RSCAN0RMDF174HH (RSCAN0.RMDF174.UINT8[R_IO_HH])
+#define RSCAN0RMID75 (RSCAN0.RMID75.UINT32)
+#define RSCAN0RMID75L (RSCAN0.RMID75.UINT16[R_IO_L])
+#define RSCAN0RMID75LL (RSCAN0.RMID75.UINT8[R_IO_LL])
+#define RSCAN0RMID75LH (RSCAN0.RMID75.UINT8[R_IO_LH])
+#define RSCAN0RMID75H (RSCAN0.RMID75.UINT16[R_IO_H])
+#define RSCAN0RMID75HL (RSCAN0.RMID75.UINT8[R_IO_HL])
+#define RSCAN0RMID75HH (RSCAN0.RMID75.UINT8[R_IO_HH])
+#define RSCAN0RMPTR75 (RSCAN0.RMPTR75.UINT32)
+#define RSCAN0RMPTR75L (RSCAN0.RMPTR75.UINT16[R_IO_L])
+#define RSCAN0RMPTR75LL (RSCAN0.RMPTR75.UINT8[R_IO_LL])
+#define RSCAN0RMPTR75LH (RSCAN0.RMPTR75.UINT8[R_IO_LH])
+#define RSCAN0RMPTR75H (RSCAN0.RMPTR75.UINT16[R_IO_H])
+#define RSCAN0RMPTR75HL (RSCAN0.RMPTR75.UINT8[R_IO_HL])
+#define RSCAN0RMPTR75HH (RSCAN0.RMPTR75.UINT8[R_IO_HH])
+#define RSCAN0RMDF075 (RSCAN0.RMDF075.UINT32)
+#define RSCAN0RMDF075L (RSCAN0.RMDF075.UINT16[R_IO_L])
+#define RSCAN0RMDF075LL (RSCAN0.RMDF075.UINT8[R_IO_LL])
+#define RSCAN0RMDF075LH (RSCAN0.RMDF075.UINT8[R_IO_LH])
+#define RSCAN0RMDF075H (RSCAN0.RMDF075.UINT16[R_IO_H])
+#define RSCAN0RMDF075HL (RSCAN0.RMDF075.UINT8[R_IO_HL])
+#define RSCAN0RMDF075HH (RSCAN0.RMDF075.UINT8[R_IO_HH])
+#define RSCAN0RMDF175 (RSCAN0.RMDF175.UINT32)
+#define RSCAN0RMDF175L (RSCAN0.RMDF175.UINT16[R_IO_L])
+#define RSCAN0RMDF175LL (RSCAN0.RMDF175.UINT8[R_IO_LL])
+#define RSCAN0RMDF175LH (RSCAN0.RMDF175.UINT8[R_IO_LH])
+#define RSCAN0RMDF175H (RSCAN0.RMDF175.UINT16[R_IO_H])
+#define RSCAN0RMDF175HL (RSCAN0.RMDF175.UINT8[R_IO_HL])
+#define RSCAN0RMDF175HH (RSCAN0.RMDF175.UINT8[R_IO_HH])
+#define RSCAN0RMID76 (RSCAN0.RMID76.UINT32)
+#define RSCAN0RMID76L (RSCAN0.RMID76.UINT16[R_IO_L])
+#define RSCAN0RMID76LL (RSCAN0.RMID76.UINT8[R_IO_LL])
+#define RSCAN0RMID76LH (RSCAN0.RMID76.UINT8[R_IO_LH])
+#define RSCAN0RMID76H (RSCAN0.RMID76.UINT16[R_IO_H])
+#define RSCAN0RMID76HL (RSCAN0.RMID76.UINT8[R_IO_HL])
+#define RSCAN0RMID76HH (RSCAN0.RMID76.UINT8[R_IO_HH])
+#define RSCAN0RMPTR76 (RSCAN0.RMPTR76.UINT32)
+#define RSCAN0RMPTR76L (RSCAN0.RMPTR76.UINT16[R_IO_L])
+#define RSCAN0RMPTR76LL (RSCAN0.RMPTR76.UINT8[R_IO_LL])
+#define RSCAN0RMPTR76LH (RSCAN0.RMPTR76.UINT8[R_IO_LH])
+#define RSCAN0RMPTR76H (RSCAN0.RMPTR76.UINT16[R_IO_H])
+#define RSCAN0RMPTR76HL (RSCAN0.RMPTR76.UINT8[R_IO_HL])
+#define RSCAN0RMPTR76HH (RSCAN0.RMPTR76.UINT8[R_IO_HH])
+#define RSCAN0RMDF076 (RSCAN0.RMDF076.UINT32)
+#define RSCAN0RMDF076L (RSCAN0.RMDF076.UINT16[R_IO_L])
+#define RSCAN0RMDF076LL (RSCAN0.RMDF076.UINT8[R_IO_LL])
+#define RSCAN0RMDF076LH (RSCAN0.RMDF076.UINT8[R_IO_LH])
+#define RSCAN0RMDF076H (RSCAN0.RMDF076.UINT16[R_IO_H])
+#define RSCAN0RMDF076HL (RSCAN0.RMDF076.UINT8[R_IO_HL])
+#define RSCAN0RMDF076HH (RSCAN0.RMDF076.UINT8[R_IO_HH])
+#define RSCAN0RMDF176 (RSCAN0.RMDF176.UINT32)
+#define RSCAN0RMDF176L (RSCAN0.RMDF176.UINT16[R_IO_L])
+#define RSCAN0RMDF176LL (RSCAN0.RMDF176.UINT8[R_IO_LL])
+#define RSCAN0RMDF176LH (RSCAN0.RMDF176.UINT8[R_IO_LH])
+#define RSCAN0RMDF176H (RSCAN0.RMDF176.UINT16[R_IO_H])
+#define RSCAN0RMDF176HL (RSCAN0.RMDF176.UINT8[R_IO_HL])
+#define RSCAN0RMDF176HH (RSCAN0.RMDF176.UINT8[R_IO_HH])
+#define RSCAN0RMID77 (RSCAN0.RMID77.UINT32)
+#define RSCAN0RMID77L (RSCAN0.RMID77.UINT16[R_IO_L])
+#define RSCAN0RMID77LL (RSCAN0.RMID77.UINT8[R_IO_LL])
+#define RSCAN0RMID77LH (RSCAN0.RMID77.UINT8[R_IO_LH])
+#define RSCAN0RMID77H (RSCAN0.RMID77.UINT16[R_IO_H])
+#define RSCAN0RMID77HL (RSCAN0.RMID77.UINT8[R_IO_HL])
+#define RSCAN0RMID77HH (RSCAN0.RMID77.UINT8[R_IO_HH])
+#define RSCAN0RMPTR77 (RSCAN0.RMPTR77.UINT32)
+#define RSCAN0RMPTR77L (RSCAN0.RMPTR77.UINT16[R_IO_L])
+#define RSCAN0RMPTR77LL (RSCAN0.RMPTR77.UINT8[R_IO_LL])
+#define RSCAN0RMPTR77LH (RSCAN0.RMPTR77.UINT8[R_IO_LH])
+#define RSCAN0RMPTR77H (RSCAN0.RMPTR77.UINT16[R_IO_H])
+#define RSCAN0RMPTR77HL (RSCAN0.RMPTR77.UINT8[R_IO_HL])
+#define RSCAN0RMPTR77HH (RSCAN0.RMPTR77.UINT8[R_IO_HH])
+#define RSCAN0RMDF077 (RSCAN0.RMDF077.UINT32)
+#define RSCAN0RMDF077L (RSCAN0.RMDF077.UINT16[R_IO_L])
+#define RSCAN0RMDF077LL (RSCAN0.RMDF077.UINT8[R_IO_LL])
+#define RSCAN0RMDF077LH (RSCAN0.RMDF077.UINT8[R_IO_LH])
+#define RSCAN0RMDF077H (RSCAN0.RMDF077.UINT16[R_IO_H])
+#define RSCAN0RMDF077HL (RSCAN0.RMDF077.UINT8[R_IO_HL])
+#define RSCAN0RMDF077HH (RSCAN0.RMDF077.UINT8[R_IO_HH])
+#define RSCAN0RMDF177 (RSCAN0.RMDF177.UINT32)
+#define RSCAN0RMDF177L (RSCAN0.RMDF177.UINT16[R_IO_L])
+#define RSCAN0RMDF177LL (RSCAN0.RMDF177.UINT8[R_IO_LL])
+#define RSCAN0RMDF177LH (RSCAN0.RMDF177.UINT8[R_IO_LH])
+#define RSCAN0RMDF177H (RSCAN0.RMDF177.UINT16[R_IO_H])
+#define RSCAN0RMDF177HL (RSCAN0.RMDF177.UINT8[R_IO_HL])
+#define RSCAN0RMDF177HH (RSCAN0.RMDF177.UINT8[R_IO_HH])
+#define RSCAN0RMID78 (RSCAN0.RMID78.UINT32)
+#define RSCAN0RMID78L (RSCAN0.RMID78.UINT16[R_IO_L])
+#define RSCAN0RMID78LL (RSCAN0.RMID78.UINT8[R_IO_LL])
+#define RSCAN0RMID78LH (RSCAN0.RMID78.UINT8[R_IO_LH])
+#define RSCAN0RMID78H (RSCAN0.RMID78.UINT16[R_IO_H])
+#define RSCAN0RMID78HL (RSCAN0.RMID78.UINT8[R_IO_HL])
+#define RSCAN0RMID78HH (RSCAN0.RMID78.UINT8[R_IO_HH])
+#define RSCAN0RMPTR78 (RSCAN0.RMPTR78.UINT32)
+#define RSCAN0RMPTR78L (RSCAN0.RMPTR78.UINT16[R_IO_L])
+#define RSCAN0RMPTR78LL (RSCAN0.RMPTR78.UINT8[R_IO_LL])
+#define RSCAN0RMPTR78LH (RSCAN0.RMPTR78.UINT8[R_IO_LH])
+#define RSCAN0RMPTR78H (RSCAN0.RMPTR78.UINT16[R_IO_H])
+#define RSCAN0RMPTR78HL (RSCAN0.RMPTR78.UINT8[R_IO_HL])
+#define RSCAN0RMPTR78HH (RSCAN0.RMPTR78.UINT8[R_IO_HH])
+#define RSCAN0RMDF078 (RSCAN0.RMDF078.UINT32)
+#define RSCAN0RMDF078L (RSCAN0.RMDF078.UINT16[R_IO_L])
+#define RSCAN0RMDF078LL (RSCAN0.RMDF078.UINT8[R_IO_LL])
+#define RSCAN0RMDF078LH (RSCAN0.RMDF078.UINT8[R_IO_LH])
+#define RSCAN0RMDF078H (RSCAN0.RMDF078.UINT16[R_IO_H])
+#define RSCAN0RMDF078HL (RSCAN0.RMDF078.UINT8[R_IO_HL])
+#define RSCAN0RMDF078HH (RSCAN0.RMDF078.UINT8[R_IO_HH])
+#define RSCAN0RMDF178 (RSCAN0.RMDF178.UINT32)
+#define RSCAN0RMDF178L (RSCAN0.RMDF178.UINT16[R_IO_L])
+#define RSCAN0RMDF178LL (RSCAN0.RMDF178.UINT8[R_IO_LL])
+#define RSCAN0RMDF178LH (RSCAN0.RMDF178.UINT8[R_IO_LH])
+#define RSCAN0RMDF178H (RSCAN0.RMDF178.UINT16[R_IO_H])
+#define RSCAN0RMDF178HL (RSCAN0.RMDF178.UINT8[R_IO_HL])
+#define RSCAN0RMDF178HH (RSCAN0.RMDF178.UINT8[R_IO_HH])
+#define RSCAN0RMID79 (RSCAN0.RMID79.UINT32)
+#define RSCAN0RMID79L (RSCAN0.RMID79.UINT16[R_IO_L])
+#define RSCAN0RMID79LL (RSCAN0.RMID79.UINT8[R_IO_LL])
+#define RSCAN0RMID79LH (RSCAN0.RMID79.UINT8[R_IO_LH])
+#define RSCAN0RMID79H (RSCAN0.RMID79.UINT16[R_IO_H])
+#define RSCAN0RMID79HL (RSCAN0.RMID79.UINT8[R_IO_HL])
+#define RSCAN0RMID79HH (RSCAN0.RMID79.UINT8[R_IO_HH])
+#define RSCAN0RMPTR79 (RSCAN0.RMPTR79.UINT32)
+#define RSCAN0RMPTR79L (RSCAN0.RMPTR79.UINT16[R_IO_L])
+#define RSCAN0RMPTR79LL (RSCAN0.RMPTR79.UINT8[R_IO_LL])
+#define RSCAN0RMPTR79LH (RSCAN0.RMPTR79.UINT8[R_IO_LH])
+#define RSCAN0RMPTR79H (RSCAN0.RMPTR79.UINT16[R_IO_H])
+#define RSCAN0RMPTR79HL (RSCAN0.RMPTR79.UINT8[R_IO_HL])
+#define RSCAN0RMPTR79HH (RSCAN0.RMPTR79.UINT8[R_IO_HH])
+#define RSCAN0RMDF079 (RSCAN0.RMDF079.UINT32)
+#define RSCAN0RMDF079L (RSCAN0.RMDF079.UINT16[R_IO_L])
+#define RSCAN0RMDF079LL (RSCAN0.RMDF079.UINT8[R_IO_LL])
+#define RSCAN0RMDF079LH (RSCAN0.RMDF079.UINT8[R_IO_LH])
+#define RSCAN0RMDF079H (RSCAN0.RMDF079.UINT16[R_IO_H])
+#define RSCAN0RMDF079HL (RSCAN0.RMDF079.UINT8[R_IO_HL])
+#define RSCAN0RMDF079HH (RSCAN0.RMDF079.UINT8[R_IO_HH])
+#define RSCAN0RMDF179 (RSCAN0.RMDF179.UINT32)
+#define RSCAN0RMDF179L (RSCAN0.RMDF179.UINT16[R_IO_L])
+#define RSCAN0RMDF179LL (RSCAN0.RMDF179.UINT8[R_IO_LL])
+#define RSCAN0RMDF179LH (RSCAN0.RMDF179.UINT8[R_IO_LH])
+#define RSCAN0RMDF179H (RSCAN0.RMDF179.UINT16[R_IO_H])
+#define RSCAN0RMDF179HL (RSCAN0.RMDF179.UINT8[R_IO_HL])
+#define RSCAN0RMDF179HH (RSCAN0.RMDF179.UINT8[R_IO_HH])
+#define RSCAN0RFID0 (RSCAN0.RFID0.UINT32)
+#define RSCAN0RFID0L (RSCAN0.RFID0.UINT16[R_IO_L])
+#define RSCAN0RFID0LL (RSCAN0.RFID0.UINT8[R_IO_LL])
+#define RSCAN0RFID0LH (RSCAN0.RFID0.UINT8[R_IO_LH])
+#define RSCAN0RFID0H (RSCAN0.RFID0.UINT16[R_IO_H])
+#define RSCAN0RFID0HL (RSCAN0.RFID0.UINT8[R_IO_HL])
+#define RSCAN0RFID0HH (RSCAN0.RFID0.UINT8[R_IO_HH])
+#define RSCAN0RFPTR0 (RSCAN0.RFPTR0.UINT32)
+#define RSCAN0RFPTR0L (RSCAN0.RFPTR0.UINT16[R_IO_L])
+#define RSCAN0RFPTR0LL (RSCAN0.RFPTR0.UINT8[R_IO_LL])
+#define RSCAN0RFPTR0LH (RSCAN0.RFPTR0.UINT8[R_IO_LH])
+#define RSCAN0RFPTR0H (RSCAN0.RFPTR0.UINT16[R_IO_H])
+#define RSCAN0RFPTR0HL (RSCAN0.RFPTR0.UINT8[R_IO_HL])
+#define RSCAN0RFPTR0HH (RSCAN0.RFPTR0.UINT8[R_IO_HH])
+#define RSCAN0RFDF00 (RSCAN0.RFDF00.UINT32)
+#define RSCAN0RFDF00L (RSCAN0.RFDF00.UINT16[R_IO_L])
+#define RSCAN0RFDF00LL (RSCAN0.RFDF00.UINT8[R_IO_LL])
+#define RSCAN0RFDF00LH (RSCAN0.RFDF00.UINT8[R_IO_LH])
+#define RSCAN0RFDF00H (RSCAN0.RFDF00.UINT16[R_IO_H])
+#define RSCAN0RFDF00HL (RSCAN0.RFDF00.UINT8[R_IO_HL])
+#define RSCAN0RFDF00HH (RSCAN0.RFDF00.UINT8[R_IO_HH])
+#define RSCAN0RFDF10 (RSCAN0.RFDF10.UINT32)
+#define RSCAN0RFDF10L (RSCAN0.RFDF10.UINT16[R_IO_L])
+#define RSCAN0RFDF10LL (RSCAN0.RFDF10.UINT8[R_IO_LL])
+#define RSCAN0RFDF10LH (RSCAN0.RFDF10.UINT8[R_IO_LH])
+#define RSCAN0RFDF10H (RSCAN0.RFDF10.UINT16[R_IO_H])
+#define RSCAN0RFDF10HL (RSCAN0.RFDF10.UINT8[R_IO_HL])
+#define RSCAN0RFDF10HH (RSCAN0.RFDF10.UINT8[R_IO_HH])
+#define RSCAN0RFID1 (RSCAN0.RFID1.UINT32)
+#define RSCAN0RFID1L (RSCAN0.RFID1.UINT16[R_IO_L])
+#define RSCAN0RFID1LL (RSCAN0.RFID1.UINT8[R_IO_LL])
+#define RSCAN0RFID1LH (RSCAN0.RFID1.UINT8[R_IO_LH])
+#define RSCAN0RFID1H (RSCAN0.RFID1.UINT16[R_IO_H])
+#define RSCAN0RFID1HL (RSCAN0.RFID1.UINT8[R_IO_HL])
+#define RSCAN0RFID1HH (RSCAN0.RFID1.UINT8[R_IO_HH])
+#define RSCAN0RFPTR1 (RSCAN0.RFPTR1.UINT32)
+#define RSCAN0RFPTR1L (RSCAN0.RFPTR1.UINT16[R_IO_L])
+#define RSCAN0RFPTR1LL (RSCAN0.RFPTR1.UINT8[R_IO_LL])
+#define RSCAN0RFPTR1LH (RSCAN0.RFPTR1.UINT8[R_IO_LH])
+#define RSCAN0RFPTR1H (RSCAN0.RFPTR1.UINT16[R_IO_H])
+#define RSCAN0RFPTR1HL (RSCAN0.RFPTR1.UINT8[R_IO_HL])
+#define RSCAN0RFPTR1HH (RSCAN0.RFPTR1.UINT8[R_IO_HH])
+#define RSCAN0RFDF01 (RSCAN0.RFDF01.UINT32)
+#define RSCAN0RFDF01L (RSCAN0.RFDF01.UINT16[R_IO_L])
+#define RSCAN0RFDF01LL (RSCAN0.RFDF01.UINT8[R_IO_LL])
+#define RSCAN0RFDF01LH (RSCAN0.RFDF01.UINT8[R_IO_LH])
+#define RSCAN0RFDF01H (RSCAN0.RFDF01.UINT16[R_IO_H])
+#define RSCAN0RFDF01HL (RSCAN0.RFDF01.UINT8[R_IO_HL])
+#define RSCAN0RFDF01HH (RSCAN0.RFDF01.UINT8[R_IO_HH])
+#define RSCAN0RFDF11 (RSCAN0.RFDF11.UINT32)
+#define RSCAN0RFDF11L (RSCAN0.RFDF11.UINT16[R_IO_L])
+#define RSCAN0RFDF11LL (RSCAN0.RFDF11.UINT8[R_IO_LL])
+#define RSCAN0RFDF11LH (RSCAN0.RFDF11.UINT8[R_IO_LH])
+#define RSCAN0RFDF11H (RSCAN0.RFDF11.UINT16[R_IO_H])
+#define RSCAN0RFDF11HL (RSCAN0.RFDF11.UINT8[R_IO_HL])
+#define RSCAN0RFDF11HH (RSCAN0.RFDF11.UINT8[R_IO_HH])
+#define RSCAN0RFID2 (RSCAN0.RFID2.UINT32)
+#define RSCAN0RFID2L (RSCAN0.RFID2.UINT16[R_IO_L])
+#define RSCAN0RFID2LL (RSCAN0.RFID2.UINT8[R_IO_LL])
+#define RSCAN0RFID2LH (RSCAN0.RFID2.UINT8[R_IO_LH])
+#define RSCAN0RFID2H (RSCAN0.RFID2.UINT16[R_IO_H])
+#define RSCAN0RFID2HL (RSCAN0.RFID2.UINT8[R_IO_HL])
+#define RSCAN0RFID2HH (RSCAN0.RFID2.UINT8[R_IO_HH])
+#define RSCAN0RFPTR2 (RSCAN0.RFPTR2.UINT32)
+#define RSCAN0RFPTR2L (RSCAN0.RFPTR2.UINT16[R_IO_L])
+#define RSCAN0RFPTR2LL (RSCAN0.RFPTR2.UINT8[R_IO_LL])
+#define RSCAN0RFPTR2LH (RSCAN0.RFPTR2.UINT8[R_IO_LH])
+#define RSCAN0RFPTR2H (RSCAN0.RFPTR2.UINT16[R_IO_H])
+#define RSCAN0RFPTR2HL (RSCAN0.RFPTR2.UINT8[R_IO_HL])
+#define RSCAN0RFPTR2HH (RSCAN0.RFPTR2.UINT8[R_IO_HH])
+#define RSCAN0RFDF02 (RSCAN0.RFDF02.UINT32)
+#define RSCAN0RFDF02L (RSCAN0.RFDF02.UINT16[R_IO_L])
+#define RSCAN0RFDF02LL (RSCAN0.RFDF02.UINT8[R_IO_LL])
+#define RSCAN0RFDF02LH (RSCAN0.RFDF02.UINT8[R_IO_LH])
+#define RSCAN0RFDF02H (RSCAN0.RFDF02.UINT16[R_IO_H])
+#define RSCAN0RFDF02HL (RSCAN0.RFDF02.UINT8[R_IO_HL])
+#define RSCAN0RFDF02HH (RSCAN0.RFDF02.UINT8[R_IO_HH])
+#define RSCAN0RFDF12 (RSCAN0.RFDF12.UINT32)
+#define RSCAN0RFDF12L (RSCAN0.RFDF12.UINT16[R_IO_L])
+#define RSCAN0RFDF12LL (RSCAN0.RFDF12.UINT8[R_IO_LL])
+#define RSCAN0RFDF12LH (RSCAN0.RFDF12.UINT8[R_IO_LH])
+#define RSCAN0RFDF12H (RSCAN0.RFDF12.UINT16[R_IO_H])
+#define RSCAN0RFDF12HL (RSCAN0.RFDF12.UINT8[R_IO_HL])
+#define RSCAN0RFDF12HH (RSCAN0.RFDF12.UINT8[R_IO_HH])
+#define RSCAN0RFID3 (RSCAN0.RFID3.UINT32)
+#define RSCAN0RFID3L (RSCAN0.RFID3.UINT16[R_IO_L])
+#define RSCAN0RFID3LL (RSCAN0.RFID3.UINT8[R_IO_LL])
+#define RSCAN0RFID3LH (RSCAN0.RFID3.UINT8[R_IO_LH])
+#define RSCAN0RFID3H (RSCAN0.RFID3.UINT16[R_IO_H])
+#define RSCAN0RFID3HL (RSCAN0.RFID3.UINT8[R_IO_HL])
+#define RSCAN0RFID3HH (RSCAN0.RFID3.UINT8[R_IO_HH])
+#define RSCAN0RFPTR3 (RSCAN0.RFPTR3.UINT32)
+#define RSCAN0RFPTR3L (RSCAN0.RFPTR3.UINT16[R_IO_L])
+#define RSCAN0RFPTR3LL (RSCAN0.RFPTR3.UINT8[R_IO_LL])
+#define RSCAN0RFPTR3LH (RSCAN0.RFPTR3.UINT8[R_IO_LH])
+#define RSCAN0RFPTR3H (RSCAN0.RFPTR3.UINT16[R_IO_H])
+#define RSCAN0RFPTR3HL (RSCAN0.RFPTR3.UINT8[R_IO_HL])
+#define RSCAN0RFPTR3HH (RSCAN0.RFPTR3.UINT8[R_IO_HH])
+#define RSCAN0RFDF03 (RSCAN0.RFDF03.UINT32)
+#define RSCAN0RFDF03L (RSCAN0.RFDF03.UINT16[R_IO_L])
+#define RSCAN0RFDF03LL (RSCAN0.RFDF03.UINT8[R_IO_LL])
+#define RSCAN0RFDF03LH (RSCAN0.RFDF03.UINT8[R_IO_LH])
+#define RSCAN0RFDF03H (RSCAN0.RFDF03.UINT16[R_IO_H])
+#define RSCAN0RFDF03HL (RSCAN0.RFDF03.UINT8[R_IO_HL])
+#define RSCAN0RFDF03HH (RSCAN0.RFDF03.UINT8[R_IO_HH])
+#define RSCAN0RFDF13 (RSCAN0.RFDF13.UINT32)
+#define RSCAN0RFDF13L (RSCAN0.RFDF13.UINT16[R_IO_L])
+#define RSCAN0RFDF13LL (RSCAN0.RFDF13.UINT8[R_IO_LL])
+#define RSCAN0RFDF13LH (RSCAN0.RFDF13.UINT8[R_IO_LH])
+#define RSCAN0RFDF13H (RSCAN0.RFDF13.UINT16[R_IO_H])
+#define RSCAN0RFDF13HL (RSCAN0.RFDF13.UINT8[R_IO_HL])
+#define RSCAN0RFDF13HH (RSCAN0.RFDF13.UINT8[R_IO_HH])
+#define RSCAN0RFID4 (RSCAN0.RFID4.UINT32)
+#define RSCAN0RFID4L (RSCAN0.RFID4.UINT16[R_IO_L])
+#define RSCAN0RFID4LL (RSCAN0.RFID4.UINT8[R_IO_LL])
+#define RSCAN0RFID4LH (RSCAN0.RFID4.UINT8[R_IO_LH])
+#define RSCAN0RFID4H (RSCAN0.RFID4.UINT16[R_IO_H])
+#define RSCAN0RFID4HL (RSCAN0.RFID4.UINT8[R_IO_HL])
+#define RSCAN0RFID4HH (RSCAN0.RFID4.UINT8[R_IO_HH])
+#define RSCAN0RFPTR4 (RSCAN0.RFPTR4.UINT32)
+#define RSCAN0RFPTR4L (RSCAN0.RFPTR4.UINT16[R_IO_L])
+#define RSCAN0RFPTR4LL (RSCAN0.RFPTR4.UINT8[R_IO_LL])
+#define RSCAN0RFPTR4LH (RSCAN0.RFPTR4.UINT8[R_IO_LH])
+#define RSCAN0RFPTR4H (RSCAN0.RFPTR4.UINT16[R_IO_H])
+#define RSCAN0RFPTR4HL (RSCAN0.RFPTR4.UINT8[R_IO_HL])
+#define RSCAN0RFPTR4HH (RSCAN0.RFPTR4.UINT8[R_IO_HH])
+#define RSCAN0RFDF04 (RSCAN0.RFDF04.UINT32)
+#define RSCAN0RFDF04L (RSCAN0.RFDF04.UINT16[R_IO_L])
+#define RSCAN0RFDF04LL (RSCAN0.RFDF04.UINT8[R_IO_LL])
+#define RSCAN0RFDF04LH (RSCAN0.RFDF04.UINT8[R_IO_LH])
+#define RSCAN0RFDF04H (RSCAN0.RFDF04.UINT16[R_IO_H])
+#define RSCAN0RFDF04HL (RSCAN0.RFDF04.UINT8[R_IO_HL])
+#define RSCAN0RFDF04HH (RSCAN0.RFDF04.UINT8[R_IO_HH])
+#define RSCAN0RFDF14 (RSCAN0.RFDF14.UINT32)
+#define RSCAN0RFDF14L (RSCAN0.RFDF14.UINT16[R_IO_L])
+#define RSCAN0RFDF14LL (RSCAN0.RFDF14.UINT8[R_IO_LL])
+#define RSCAN0RFDF14LH (RSCAN0.RFDF14.UINT8[R_IO_LH])
+#define RSCAN0RFDF14H (RSCAN0.RFDF14.UINT16[R_IO_H])
+#define RSCAN0RFDF14HL (RSCAN0.RFDF14.UINT8[R_IO_HL])
+#define RSCAN0RFDF14HH (RSCAN0.RFDF14.UINT8[R_IO_HH])
+#define RSCAN0RFID5 (RSCAN0.RFID5.UINT32)
+#define RSCAN0RFID5L (RSCAN0.RFID5.UINT16[R_IO_L])
+#define RSCAN0RFID5LL (RSCAN0.RFID5.UINT8[R_IO_LL])
+#define RSCAN0RFID5LH (RSCAN0.RFID5.UINT8[R_IO_LH])
+#define RSCAN0RFID5H (RSCAN0.RFID5.UINT16[R_IO_H])
+#define RSCAN0RFID5HL (RSCAN0.RFID5.UINT8[R_IO_HL])
+#define RSCAN0RFID5HH (RSCAN0.RFID5.UINT8[R_IO_HH])
+#define RSCAN0RFPTR5 (RSCAN0.RFPTR5.UINT32)
+#define RSCAN0RFPTR5L (RSCAN0.RFPTR5.UINT16[R_IO_L])
+#define RSCAN0RFPTR5LL (RSCAN0.RFPTR5.UINT8[R_IO_LL])
+#define RSCAN0RFPTR5LH (RSCAN0.RFPTR5.UINT8[R_IO_LH])
+#define RSCAN0RFPTR5H (RSCAN0.RFPTR5.UINT16[R_IO_H])
+#define RSCAN0RFPTR5HL (RSCAN0.RFPTR5.UINT8[R_IO_HL])
+#define RSCAN0RFPTR5HH (RSCAN0.RFPTR5.UINT8[R_IO_HH])
+#define RSCAN0RFDF05 (RSCAN0.RFDF05.UINT32)
+#define RSCAN0RFDF05L (RSCAN0.RFDF05.UINT16[R_IO_L])
+#define RSCAN0RFDF05LL (RSCAN0.RFDF05.UINT8[R_IO_LL])
+#define RSCAN0RFDF05LH (RSCAN0.RFDF05.UINT8[R_IO_LH])
+#define RSCAN0RFDF05H (RSCAN0.RFDF05.UINT16[R_IO_H])
+#define RSCAN0RFDF05HL (RSCAN0.RFDF05.UINT8[R_IO_HL])
+#define RSCAN0RFDF05HH (RSCAN0.RFDF05.UINT8[R_IO_HH])
+#define RSCAN0RFDF15 (RSCAN0.RFDF15.UINT32)
+#define RSCAN0RFDF15L (RSCAN0.RFDF15.UINT16[R_IO_L])
+#define RSCAN0RFDF15LL (RSCAN0.RFDF15.UINT8[R_IO_LL])
+#define RSCAN0RFDF15LH (RSCAN0.RFDF15.UINT8[R_IO_LH])
+#define RSCAN0RFDF15H (RSCAN0.RFDF15.UINT16[R_IO_H])
+#define RSCAN0RFDF15HL (RSCAN0.RFDF15.UINT8[R_IO_HL])
+#define RSCAN0RFDF15HH (RSCAN0.RFDF15.UINT8[R_IO_HH])
+#define RSCAN0RFID6 (RSCAN0.RFID6.UINT32)
+#define RSCAN0RFID6L (RSCAN0.RFID6.UINT16[R_IO_L])
+#define RSCAN0RFID6LL (RSCAN0.RFID6.UINT8[R_IO_LL])
+#define RSCAN0RFID6LH (RSCAN0.RFID6.UINT8[R_IO_LH])
+#define RSCAN0RFID6H (RSCAN0.RFID6.UINT16[R_IO_H])
+#define RSCAN0RFID6HL (RSCAN0.RFID6.UINT8[R_IO_HL])
+#define RSCAN0RFID6HH (RSCAN0.RFID6.UINT8[R_IO_HH])
+#define RSCAN0RFPTR6 (RSCAN0.RFPTR6.UINT32)
+#define RSCAN0RFPTR6L (RSCAN0.RFPTR6.UINT16[R_IO_L])
+#define RSCAN0RFPTR6LL (RSCAN0.RFPTR6.UINT8[R_IO_LL])
+#define RSCAN0RFPTR6LH (RSCAN0.RFPTR6.UINT8[R_IO_LH])
+#define RSCAN0RFPTR6H (RSCAN0.RFPTR6.UINT16[R_IO_H])
+#define RSCAN0RFPTR6HL (RSCAN0.RFPTR6.UINT8[R_IO_HL])
+#define RSCAN0RFPTR6HH (RSCAN0.RFPTR6.UINT8[R_IO_HH])
+#define RSCAN0RFDF06 (RSCAN0.RFDF06.UINT32)
+#define RSCAN0RFDF06L (RSCAN0.RFDF06.UINT16[R_IO_L])
+#define RSCAN0RFDF06LL (RSCAN0.RFDF06.UINT8[R_IO_LL])
+#define RSCAN0RFDF06LH (RSCAN0.RFDF06.UINT8[R_IO_LH])
+#define RSCAN0RFDF06H (RSCAN0.RFDF06.UINT16[R_IO_H])
+#define RSCAN0RFDF06HL (RSCAN0.RFDF06.UINT8[R_IO_HL])
+#define RSCAN0RFDF06HH (RSCAN0.RFDF06.UINT8[R_IO_HH])
+#define RSCAN0RFDF16 (RSCAN0.RFDF16.UINT32)
+#define RSCAN0RFDF16L (RSCAN0.RFDF16.UINT16[R_IO_L])
+#define RSCAN0RFDF16LL (RSCAN0.RFDF16.UINT8[R_IO_LL])
+#define RSCAN0RFDF16LH (RSCAN0.RFDF16.UINT8[R_IO_LH])
+#define RSCAN0RFDF16H (RSCAN0.RFDF16.UINT16[R_IO_H])
+#define RSCAN0RFDF16HL (RSCAN0.RFDF16.UINT8[R_IO_HL])
+#define RSCAN0RFDF16HH (RSCAN0.RFDF16.UINT8[R_IO_HH])
+#define RSCAN0RFID7 (RSCAN0.RFID7.UINT32)
+#define RSCAN0RFID7L (RSCAN0.RFID7.UINT16[R_IO_L])
+#define RSCAN0RFID7LL (RSCAN0.RFID7.UINT8[R_IO_LL])
+#define RSCAN0RFID7LH (RSCAN0.RFID7.UINT8[R_IO_LH])
+#define RSCAN0RFID7H (RSCAN0.RFID7.UINT16[R_IO_H])
+#define RSCAN0RFID7HL (RSCAN0.RFID7.UINT8[R_IO_HL])
+#define RSCAN0RFID7HH (RSCAN0.RFID7.UINT8[R_IO_HH])
+#define RSCAN0RFPTR7 (RSCAN0.RFPTR7.UINT32)
+#define RSCAN0RFPTR7L (RSCAN0.RFPTR7.UINT16[R_IO_L])
+#define RSCAN0RFPTR7LL (RSCAN0.RFPTR7.UINT8[R_IO_LL])
+#define RSCAN0RFPTR7LH (RSCAN0.RFPTR7.UINT8[R_IO_LH])
+#define RSCAN0RFPTR7H (RSCAN0.RFPTR7.UINT16[R_IO_H])
+#define RSCAN0RFPTR7HL (RSCAN0.RFPTR7.UINT8[R_IO_HL])
+#define RSCAN0RFPTR7HH (RSCAN0.RFPTR7.UINT8[R_IO_HH])
+#define RSCAN0RFDF07 (RSCAN0.RFDF07.UINT32)
+#define RSCAN0RFDF07L (RSCAN0.RFDF07.UINT16[R_IO_L])
+#define RSCAN0RFDF07LL (RSCAN0.RFDF07.UINT8[R_IO_LL])
+#define RSCAN0RFDF07LH (RSCAN0.RFDF07.UINT8[R_IO_LH])
+#define RSCAN0RFDF07H (RSCAN0.RFDF07.UINT16[R_IO_H])
+#define RSCAN0RFDF07HL (RSCAN0.RFDF07.UINT8[R_IO_HL])
+#define RSCAN0RFDF07HH (RSCAN0.RFDF07.UINT8[R_IO_HH])
+#define RSCAN0RFDF17 (RSCAN0.RFDF17.UINT32)
+#define RSCAN0RFDF17L (RSCAN0.RFDF17.UINT16[R_IO_L])
+#define RSCAN0RFDF17LL (RSCAN0.RFDF17.UINT8[R_IO_LL])
+#define RSCAN0RFDF17LH (RSCAN0.RFDF17.UINT8[R_IO_LH])
+#define RSCAN0RFDF17H (RSCAN0.RFDF17.UINT16[R_IO_H])
+#define RSCAN0RFDF17HL (RSCAN0.RFDF17.UINT8[R_IO_HL])
+#define RSCAN0RFDF17HH (RSCAN0.RFDF17.UINT8[R_IO_HH])
+#define RSCAN0CFID0 (RSCAN0.CFID0.UINT32)
+#define RSCAN0CFID0L (RSCAN0.CFID0.UINT16[R_IO_L])
+#define RSCAN0CFID0LL (RSCAN0.CFID0.UINT8[R_IO_LL])
+#define RSCAN0CFID0LH (RSCAN0.CFID0.UINT8[R_IO_LH])
+#define RSCAN0CFID0H (RSCAN0.CFID0.UINT16[R_IO_H])
+#define RSCAN0CFID0HL (RSCAN0.CFID0.UINT8[R_IO_HL])
+#define RSCAN0CFID0HH (RSCAN0.CFID0.UINT8[R_IO_HH])
+#define RSCAN0CFPTR0 (RSCAN0.CFPTR0.UINT32)
+#define RSCAN0CFPTR0L (RSCAN0.CFPTR0.UINT16[R_IO_L])
+#define RSCAN0CFPTR0LL (RSCAN0.CFPTR0.UINT8[R_IO_LL])
+#define RSCAN0CFPTR0LH (RSCAN0.CFPTR0.UINT8[R_IO_LH])
+#define RSCAN0CFPTR0H (RSCAN0.CFPTR0.UINT16[R_IO_H])
+#define RSCAN0CFPTR0HL (RSCAN0.CFPTR0.UINT8[R_IO_HL])
+#define RSCAN0CFPTR0HH (RSCAN0.CFPTR0.UINT8[R_IO_HH])
+#define RSCAN0CFDF00 (RSCAN0.CFDF00.UINT32)
+#define RSCAN0CFDF00L (RSCAN0.CFDF00.UINT16[R_IO_L])
+#define RSCAN0CFDF00LL (RSCAN0.CFDF00.UINT8[R_IO_LL])
+#define RSCAN0CFDF00LH (RSCAN0.CFDF00.UINT8[R_IO_LH])
+#define RSCAN0CFDF00H (RSCAN0.CFDF00.UINT16[R_IO_H])
+#define RSCAN0CFDF00HL (RSCAN0.CFDF00.UINT8[R_IO_HL])
+#define RSCAN0CFDF00HH (RSCAN0.CFDF00.UINT8[R_IO_HH])
+#define RSCAN0CFDF10 (RSCAN0.CFDF10.UINT32)
+#define RSCAN0CFDF10L (RSCAN0.CFDF10.UINT16[R_IO_L])
+#define RSCAN0CFDF10LL (RSCAN0.CFDF10.UINT8[R_IO_LL])
+#define RSCAN0CFDF10LH (RSCAN0.CFDF10.UINT8[R_IO_LH])
+#define RSCAN0CFDF10H (RSCAN0.CFDF10.UINT16[R_IO_H])
+#define RSCAN0CFDF10HL (RSCAN0.CFDF10.UINT8[R_IO_HL])
+#define RSCAN0CFDF10HH (RSCAN0.CFDF10.UINT8[R_IO_HH])
+#define RSCAN0CFID1 (RSCAN0.CFID1.UINT32)
+#define RSCAN0CFID1L (RSCAN0.CFID1.UINT16[R_IO_L])
+#define RSCAN0CFID1LL (RSCAN0.CFID1.UINT8[R_IO_LL])
+#define RSCAN0CFID1LH (RSCAN0.CFID1.UINT8[R_IO_LH])
+#define RSCAN0CFID1H (RSCAN0.CFID1.UINT16[R_IO_H])
+#define RSCAN0CFID1HL (RSCAN0.CFID1.UINT8[R_IO_HL])
+#define RSCAN0CFID1HH (RSCAN0.CFID1.UINT8[R_IO_HH])
+#define RSCAN0CFPTR1 (RSCAN0.CFPTR1.UINT32)
+#define RSCAN0CFPTR1L (RSCAN0.CFPTR1.UINT16[R_IO_L])
+#define RSCAN0CFPTR1LL (RSCAN0.CFPTR1.UINT8[R_IO_LL])
+#define RSCAN0CFPTR1LH (RSCAN0.CFPTR1.UINT8[R_IO_LH])
+#define RSCAN0CFPTR1H (RSCAN0.CFPTR1.UINT16[R_IO_H])
+#define RSCAN0CFPTR1HL (RSCAN0.CFPTR1.UINT8[R_IO_HL])
+#define RSCAN0CFPTR1HH (RSCAN0.CFPTR1.UINT8[R_IO_HH])
+#define RSCAN0CFDF01 (RSCAN0.CFDF01.UINT32)
+#define RSCAN0CFDF01L (RSCAN0.CFDF01.UINT16[R_IO_L])
+#define RSCAN0CFDF01LL (RSCAN0.CFDF01.UINT8[R_IO_LL])
+#define RSCAN0CFDF01LH (RSCAN0.CFDF01.UINT8[R_IO_LH])
+#define RSCAN0CFDF01H (RSCAN0.CFDF01.UINT16[R_IO_H])
+#define RSCAN0CFDF01HL (RSCAN0.CFDF01.UINT8[R_IO_HL])
+#define RSCAN0CFDF01HH (RSCAN0.CFDF01.UINT8[R_IO_HH])
+#define RSCAN0CFDF11 (RSCAN0.CFDF11.UINT32)
+#define RSCAN0CFDF11L (RSCAN0.CFDF11.UINT16[R_IO_L])
+#define RSCAN0CFDF11LL (RSCAN0.CFDF11.UINT8[R_IO_LL])
+#define RSCAN0CFDF11LH (RSCAN0.CFDF11.UINT8[R_IO_LH])
+#define RSCAN0CFDF11H (RSCAN0.CFDF11.UINT16[R_IO_H])
+#define RSCAN0CFDF11HL (RSCAN0.CFDF11.UINT8[R_IO_HL])
+#define RSCAN0CFDF11HH (RSCAN0.CFDF11.UINT8[R_IO_HH])
+#define RSCAN0CFID2 (RSCAN0.CFID2.UINT32)
+#define RSCAN0CFID2L (RSCAN0.CFID2.UINT16[R_IO_L])
+#define RSCAN0CFID2LL (RSCAN0.CFID2.UINT8[R_IO_LL])
+#define RSCAN0CFID2LH (RSCAN0.CFID2.UINT8[R_IO_LH])
+#define RSCAN0CFID2H (RSCAN0.CFID2.UINT16[R_IO_H])
+#define RSCAN0CFID2HL (RSCAN0.CFID2.UINT8[R_IO_HL])
+#define RSCAN0CFID2HH (RSCAN0.CFID2.UINT8[R_IO_HH])
+#define RSCAN0CFPTR2 (RSCAN0.CFPTR2.UINT32)
+#define RSCAN0CFPTR2L (RSCAN0.CFPTR2.UINT16[R_IO_L])
+#define RSCAN0CFPTR2LL (RSCAN0.CFPTR2.UINT8[R_IO_LL])
+#define RSCAN0CFPTR2LH (RSCAN0.CFPTR2.UINT8[R_IO_LH])
+#define RSCAN0CFPTR2H (RSCAN0.CFPTR2.UINT16[R_IO_H])
+#define RSCAN0CFPTR2HL (RSCAN0.CFPTR2.UINT8[R_IO_HL])
+#define RSCAN0CFPTR2HH (RSCAN0.CFPTR2.UINT8[R_IO_HH])
+#define RSCAN0CFDF02 (RSCAN0.CFDF02.UINT32)
+#define RSCAN0CFDF02L (RSCAN0.CFDF02.UINT16[R_IO_L])
+#define RSCAN0CFDF02LL (RSCAN0.CFDF02.UINT8[R_IO_LL])
+#define RSCAN0CFDF02LH (RSCAN0.CFDF02.UINT8[R_IO_LH])
+#define RSCAN0CFDF02H (RSCAN0.CFDF02.UINT16[R_IO_H])
+#define RSCAN0CFDF02HL (RSCAN0.CFDF02.UINT8[R_IO_HL])
+#define RSCAN0CFDF02HH (RSCAN0.CFDF02.UINT8[R_IO_HH])
+#define RSCAN0CFDF12 (RSCAN0.CFDF12.UINT32)
+#define RSCAN0CFDF12L (RSCAN0.CFDF12.UINT16[R_IO_L])
+#define RSCAN0CFDF12LL (RSCAN0.CFDF12.UINT8[R_IO_LL])
+#define RSCAN0CFDF12LH (RSCAN0.CFDF12.UINT8[R_IO_LH])
+#define RSCAN0CFDF12H (RSCAN0.CFDF12.UINT16[R_IO_H])
+#define RSCAN0CFDF12HL (RSCAN0.CFDF12.UINT8[R_IO_HL])
+#define RSCAN0CFDF12HH (RSCAN0.CFDF12.UINT8[R_IO_HH])
+#define RSCAN0CFID3 (RSCAN0.CFID3.UINT32)
+#define RSCAN0CFID3L (RSCAN0.CFID3.UINT16[R_IO_L])
+#define RSCAN0CFID3LL (RSCAN0.CFID3.UINT8[R_IO_LL])
+#define RSCAN0CFID3LH (RSCAN0.CFID3.UINT8[R_IO_LH])
+#define RSCAN0CFID3H (RSCAN0.CFID3.UINT16[R_IO_H])
+#define RSCAN0CFID3HL (RSCAN0.CFID3.UINT8[R_IO_HL])
+#define RSCAN0CFID3HH (RSCAN0.CFID3.UINT8[R_IO_HH])
+#define RSCAN0CFPTR3 (RSCAN0.CFPTR3.UINT32)
+#define RSCAN0CFPTR3L (RSCAN0.CFPTR3.UINT16[R_IO_L])
+#define RSCAN0CFPTR3LL (RSCAN0.CFPTR3.UINT8[R_IO_LL])
+#define RSCAN0CFPTR3LH (RSCAN0.CFPTR3.UINT8[R_IO_LH])
+#define RSCAN0CFPTR3H (RSCAN0.CFPTR3.UINT16[R_IO_H])
+#define RSCAN0CFPTR3HL (RSCAN0.CFPTR3.UINT8[R_IO_HL])
+#define RSCAN0CFPTR3HH (RSCAN0.CFPTR3.UINT8[R_IO_HH])
+#define RSCAN0CFDF03 (RSCAN0.CFDF03.UINT32)
+#define RSCAN0CFDF03L (RSCAN0.CFDF03.UINT16[R_IO_L])
+#define RSCAN0CFDF03LL (RSCAN0.CFDF03.UINT8[R_IO_LL])
+#define RSCAN0CFDF03LH (RSCAN0.CFDF03.UINT8[R_IO_LH])
+#define RSCAN0CFDF03H (RSCAN0.CFDF03.UINT16[R_IO_H])
+#define RSCAN0CFDF03HL (RSCAN0.CFDF03.UINT8[R_IO_HL])
+#define RSCAN0CFDF03HH (RSCAN0.CFDF03.UINT8[R_IO_HH])
+#define RSCAN0CFDF13 (RSCAN0.CFDF13.UINT32)
+#define RSCAN0CFDF13L (RSCAN0.CFDF13.UINT16[R_IO_L])
+#define RSCAN0CFDF13LL (RSCAN0.CFDF13.UINT8[R_IO_LL])
+#define RSCAN0CFDF13LH (RSCAN0.CFDF13.UINT8[R_IO_LH])
+#define RSCAN0CFDF13H (RSCAN0.CFDF13.UINT16[R_IO_H])
+#define RSCAN0CFDF13HL (RSCAN0.CFDF13.UINT8[R_IO_HL])
+#define RSCAN0CFDF13HH (RSCAN0.CFDF13.UINT8[R_IO_HH])
+#define RSCAN0CFID4 (RSCAN0.CFID4.UINT32)
+#define RSCAN0CFID4L (RSCAN0.CFID4.UINT16[R_IO_L])
+#define RSCAN0CFID4LL (RSCAN0.CFID4.UINT8[R_IO_LL])
+#define RSCAN0CFID4LH (RSCAN0.CFID4.UINT8[R_IO_LH])
+#define RSCAN0CFID4H (RSCAN0.CFID4.UINT16[R_IO_H])
+#define RSCAN0CFID4HL (RSCAN0.CFID4.UINT8[R_IO_HL])
+#define RSCAN0CFID4HH (RSCAN0.CFID4.UINT8[R_IO_HH])
+#define RSCAN0CFPTR4 (RSCAN0.CFPTR4.UINT32)
+#define RSCAN0CFPTR4L (RSCAN0.CFPTR4.UINT16[R_IO_L])
+#define RSCAN0CFPTR4LL (RSCAN0.CFPTR4.UINT8[R_IO_LL])
+#define RSCAN0CFPTR4LH (RSCAN0.CFPTR4.UINT8[R_IO_LH])
+#define RSCAN0CFPTR4H (RSCAN0.CFPTR4.UINT16[R_IO_H])
+#define RSCAN0CFPTR4HL (RSCAN0.CFPTR4.UINT8[R_IO_HL])
+#define RSCAN0CFPTR4HH (RSCAN0.CFPTR4.UINT8[R_IO_HH])
+#define RSCAN0CFDF04 (RSCAN0.CFDF04.UINT32)
+#define RSCAN0CFDF04L (RSCAN0.CFDF04.UINT16[R_IO_L])
+#define RSCAN0CFDF04LL (RSCAN0.CFDF04.UINT8[R_IO_LL])
+#define RSCAN0CFDF04LH (RSCAN0.CFDF04.UINT8[R_IO_LH])
+#define RSCAN0CFDF04H (RSCAN0.CFDF04.UINT16[R_IO_H])
+#define RSCAN0CFDF04HL (RSCAN0.CFDF04.UINT8[R_IO_HL])
+#define RSCAN0CFDF04HH (RSCAN0.CFDF04.UINT8[R_IO_HH])
+#define RSCAN0CFDF14 (RSCAN0.CFDF14.UINT32)
+#define RSCAN0CFDF14L (RSCAN0.CFDF14.UINT16[R_IO_L])
+#define RSCAN0CFDF14LL (RSCAN0.CFDF14.UINT8[R_IO_LL])
+#define RSCAN0CFDF14LH (RSCAN0.CFDF14.UINT8[R_IO_LH])
+#define RSCAN0CFDF14H (RSCAN0.CFDF14.UINT16[R_IO_H])
+#define RSCAN0CFDF14HL (RSCAN0.CFDF14.UINT8[R_IO_HL])
+#define RSCAN0CFDF14HH (RSCAN0.CFDF14.UINT8[R_IO_HH])
+#define RSCAN0CFID5 (RSCAN0.CFID5.UINT32)
+#define RSCAN0CFID5L (RSCAN0.CFID5.UINT16[R_IO_L])
+#define RSCAN0CFID5LL (RSCAN0.CFID5.UINT8[R_IO_LL])
+#define RSCAN0CFID5LH (RSCAN0.CFID5.UINT8[R_IO_LH])
+#define RSCAN0CFID5H (RSCAN0.CFID5.UINT16[R_IO_H])
+#define RSCAN0CFID5HL (RSCAN0.CFID5.UINT8[R_IO_HL])
+#define RSCAN0CFID5HH (RSCAN0.CFID5.UINT8[R_IO_HH])
+#define RSCAN0CFPTR5 (RSCAN0.CFPTR5.UINT32)
+#define RSCAN0CFPTR5L (RSCAN0.CFPTR5.UINT16[R_IO_L])
+#define RSCAN0CFPTR5LL (RSCAN0.CFPTR5.UINT8[R_IO_LL])
+#define RSCAN0CFPTR5LH (RSCAN0.CFPTR5.UINT8[R_IO_LH])
+#define RSCAN0CFPTR5H (RSCAN0.CFPTR5.UINT16[R_IO_H])
+#define RSCAN0CFPTR5HL (RSCAN0.CFPTR5.UINT8[R_IO_HL])
+#define RSCAN0CFPTR5HH (RSCAN0.CFPTR5.UINT8[R_IO_HH])
+#define RSCAN0CFDF05 (RSCAN0.CFDF05.UINT32)
+#define RSCAN0CFDF05L (RSCAN0.CFDF05.UINT16[R_IO_L])
+#define RSCAN0CFDF05LL (RSCAN0.CFDF05.UINT8[R_IO_LL])
+#define RSCAN0CFDF05LH (RSCAN0.CFDF05.UINT8[R_IO_LH])
+#define RSCAN0CFDF05H (RSCAN0.CFDF05.UINT16[R_IO_H])
+#define RSCAN0CFDF05HL (RSCAN0.CFDF05.UINT8[R_IO_HL])
+#define RSCAN0CFDF05HH (RSCAN0.CFDF05.UINT8[R_IO_HH])
+#define RSCAN0CFDF15 (RSCAN0.CFDF15.UINT32)
+#define RSCAN0CFDF15L (RSCAN0.CFDF15.UINT16[R_IO_L])
+#define RSCAN0CFDF15LL (RSCAN0.CFDF15.UINT8[R_IO_LL])
+#define RSCAN0CFDF15LH (RSCAN0.CFDF15.UINT8[R_IO_LH])
+#define RSCAN0CFDF15H (RSCAN0.CFDF15.UINT16[R_IO_H])
+#define RSCAN0CFDF15HL (RSCAN0.CFDF15.UINT8[R_IO_HL])
+#define RSCAN0CFDF15HH (RSCAN0.CFDF15.UINT8[R_IO_HH])
+#define RSCAN0CFID6 (RSCAN0.CFID6.UINT32)
+#define RSCAN0CFID6L (RSCAN0.CFID6.UINT16[R_IO_L])
+#define RSCAN0CFID6LL (RSCAN0.CFID6.UINT8[R_IO_LL])
+#define RSCAN0CFID6LH (RSCAN0.CFID6.UINT8[R_IO_LH])
+#define RSCAN0CFID6H (RSCAN0.CFID6.UINT16[R_IO_H])
+#define RSCAN0CFID6HL (RSCAN0.CFID6.UINT8[R_IO_HL])
+#define RSCAN0CFID6HH (RSCAN0.CFID6.UINT8[R_IO_HH])
+#define RSCAN0CFPTR6 (RSCAN0.CFPTR6.UINT32)
+#define RSCAN0CFPTR6L (RSCAN0.CFPTR6.UINT16[R_IO_L])
+#define RSCAN0CFPTR6LL (RSCAN0.CFPTR6.UINT8[R_IO_LL])
+#define RSCAN0CFPTR6LH (RSCAN0.CFPTR6.UINT8[R_IO_LH])
+#define RSCAN0CFPTR6H (RSCAN0.CFPTR6.UINT16[R_IO_H])
+#define RSCAN0CFPTR6HL (RSCAN0.CFPTR6.UINT8[R_IO_HL])
+#define RSCAN0CFPTR6HH (RSCAN0.CFPTR6.UINT8[R_IO_HH])
+#define RSCAN0CFDF06 (RSCAN0.CFDF06.UINT32)
+#define RSCAN0CFDF06L (RSCAN0.CFDF06.UINT16[R_IO_L])
+#define RSCAN0CFDF06LL (RSCAN0.CFDF06.UINT8[R_IO_LL])
+#define RSCAN0CFDF06LH (RSCAN0.CFDF06.UINT8[R_IO_LH])
+#define RSCAN0CFDF06H (RSCAN0.CFDF06.UINT16[R_IO_H])
+#define RSCAN0CFDF06HL (RSCAN0.CFDF06.UINT8[R_IO_HL])
+#define RSCAN0CFDF06HH (RSCAN0.CFDF06.UINT8[R_IO_HH])
+#define RSCAN0CFDF16 (RSCAN0.CFDF16.UINT32)
+#define RSCAN0CFDF16L (RSCAN0.CFDF16.UINT16[R_IO_L])
+#define RSCAN0CFDF16LL (RSCAN0.CFDF16.UINT8[R_IO_LL])
+#define RSCAN0CFDF16LH (RSCAN0.CFDF16.UINT8[R_IO_LH])
+#define RSCAN0CFDF16H (RSCAN0.CFDF16.UINT16[R_IO_H])
+#define RSCAN0CFDF16HL (RSCAN0.CFDF16.UINT8[R_IO_HL])
+#define RSCAN0CFDF16HH (RSCAN0.CFDF16.UINT8[R_IO_HH])
+#define RSCAN0CFID7 (RSCAN0.CFID7.UINT32)
+#define RSCAN0CFID7L (RSCAN0.CFID7.UINT16[R_IO_L])
+#define RSCAN0CFID7LL (RSCAN0.CFID7.UINT8[R_IO_LL])
+#define RSCAN0CFID7LH (RSCAN0.CFID7.UINT8[R_IO_LH])
+#define RSCAN0CFID7H (RSCAN0.CFID7.UINT16[R_IO_H])
+#define RSCAN0CFID7HL (RSCAN0.CFID7.UINT8[R_IO_HL])
+#define RSCAN0CFID7HH (RSCAN0.CFID7.UINT8[R_IO_HH])
+#define RSCAN0CFPTR7 (RSCAN0.CFPTR7.UINT32)
+#define RSCAN0CFPTR7L (RSCAN0.CFPTR7.UINT16[R_IO_L])
+#define RSCAN0CFPTR7LL (RSCAN0.CFPTR7.UINT8[R_IO_LL])
+#define RSCAN0CFPTR7LH (RSCAN0.CFPTR7.UINT8[R_IO_LH])
+#define RSCAN0CFPTR7H (RSCAN0.CFPTR7.UINT16[R_IO_H])
+#define RSCAN0CFPTR7HL (RSCAN0.CFPTR7.UINT8[R_IO_HL])
+#define RSCAN0CFPTR7HH (RSCAN0.CFPTR7.UINT8[R_IO_HH])
+#define RSCAN0CFDF07 (RSCAN0.CFDF07.UINT32)
+#define RSCAN0CFDF07L (RSCAN0.CFDF07.UINT16[R_IO_L])
+#define RSCAN0CFDF07LL (RSCAN0.CFDF07.UINT8[R_IO_LL])
+#define RSCAN0CFDF07LH (RSCAN0.CFDF07.UINT8[R_IO_LH])
+#define RSCAN0CFDF07H (RSCAN0.CFDF07.UINT16[R_IO_H])
+#define RSCAN0CFDF07HL (RSCAN0.CFDF07.UINT8[R_IO_HL])
+#define RSCAN0CFDF07HH (RSCAN0.CFDF07.UINT8[R_IO_HH])
+#define RSCAN0CFDF17 (RSCAN0.CFDF17.UINT32)
+#define RSCAN0CFDF17L (RSCAN0.CFDF17.UINT16[R_IO_L])
+#define RSCAN0CFDF17LL (RSCAN0.CFDF17.UINT8[R_IO_LL])
+#define RSCAN0CFDF17LH (RSCAN0.CFDF17.UINT8[R_IO_LH])
+#define RSCAN0CFDF17H (RSCAN0.CFDF17.UINT16[R_IO_H])
+#define RSCAN0CFDF17HL (RSCAN0.CFDF17.UINT8[R_IO_HL])
+#define RSCAN0CFDF17HH (RSCAN0.CFDF17.UINT8[R_IO_HH])
+#define RSCAN0CFID8 (RSCAN0.CFID8.UINT32)
+#define RSCAN0CFID8L (RSCAN0.CFID8.UINT16[R_IO_L])
+#define RSCAN0CFID8LL (RSCAN0.CFID8.UINT8[R_IO_LL])
+#define RSCAN0CFID8LH (RSCAN0.CFID8.UINT8[R_IO_LH])
+#define RSCAN0CFID8H (RSCAN0.CFID8.UINT16[R_IO_H])
+#define RSCAN0CFID8HL (RSCAN0.CFID8.UINT8[R_IO_HL])
+#define RSCAN0CFID8HH (RSCAN0.CFID8.UINT8[R_IO_HH])
+#define RSCAN0CFPTR8 (RSCAN0.CFPTR8.UINT32)
+#define RSCAN0CFPTR8L (RSCAN0.CFPTR8.UINT16[R_IO_L])
+#define RSCAN0CFPTR8LL (RSCAN0.CFPTR8.UINT8[R_IO_LL])
+#define RSCAN0CFPTR8LH (RSCAN0.CFPTR8.UINT8[R_IO_LH])
+#define RSCAN0CFPTR8H (RSCAN0.CFPTR8.UINT16[R_IO_H])
+#define RSCAN0CFPTR8HL (RSCAN0.CFPTR8.UINT8[R_IO_HL])
+#define RSCAN0CFPTR8HH (RSCAN0.CFPTR8.UINT8[R_IO_HH])
+#define RSCAN0CFDF08 (RSCAN0.CFDF08.UINT32)
+#define RSCAN0CFDF08L (RSCAN0.CFDF08.UINT16[R_IO_L])
+#define RSCAN0CFDF08LL (RSCAN0.CFDF08.UINT8[R_IO_LL])
+#define RSCAN0CFDF08LH (RSCAN0.CFDF08.UINT8[R_IO_LH])
+#define RSCAN0CFDF08H (RSCAN0.CFDF08.UINT16[R_IO_H])
+#define RSCAN0CFDF08HL (RSCAN0.CFDF08.UINT8[R_IO_HL])
+#define RSCAN0CFDF08HH (RSCAN0.CFDF08.UINT8[R_IO_HH])
+#define RSCAN0CFDF18 (RSCAN0.CFDF18.UINT32)
+#define RSCAN0CFDF18L (RSCAN0.CFDF18.UINT16[R_IO_L])
+#define RSCAN0CFDF18LL (RSCAN0.CFDF18.UINT8[R_IO_LL])
+#define RSCAN0CFDF18LH (RSCAN0.CFDF18.UINT8[R_IO_LH])
+#define RSCAN0CFDF18H (RSCAN0.CFDF18.UINT16[R_IO_H])
+#define RSCAN0CFDF18HL (RSCAN0.CFDF18.UINT8[R_IO_HL])
+#define RSCAN0CFDF18HH (RSCAN0.CFDF18.UINT8[R_IO_HH])
+#define RSCAN0CFID9 (RSCAN0.CFID9.UINT32)
+#define RSCAN0CFID9L (RSCAN0.CFID9.UINT16[R_IO_L])
+#define RSCAN0CFID9LL (RSCAN0.CFID9.UINT8[R_IO_LL])
+#define RSCAN0CFID9LH (RSCAN0.CFID9.UINT8[R_IO_LH])
+#define RSCAN0CFID9H (RSCAN0.CFID9.UINT16[R_IO_H])
+#define RSCAN0CFID9HL (RSCAN0.CFID9.UINT8[R_IO_HL])
+#define RSCAN0CFID9HH (RSCAN0.CFID9.UINT8[R_IO_HH])
+#define RSCAN0CFPTR9 (RSCAN0.CFPTR9.UINT32)
+#define RSCAN0CFPTR9L (RSCAN0.CFPTR9.UINT16[R_IO_L])
+#define RSCAN0CFPTR9LL (RSCAN0.CFPTR9.UINT8[R_IO_LL])
+#define RSCAN0CFPTR9LH (RSCAN0.CFPTR9.UINT8[R_IO_LH])
+#define RSCAN0CFPTR9H (RSCAN0.CFPTR9.UINT16[R_IO_H])
+#define RSCAN0CFPTR9HL (RSCAN0.CFPTR9.UINT8[R_IO_HL])
+#define RSCAN0CFPTR9HH (RSCAN0.CFPTR9.UINT8[R_IO_HH])
+#define RSCAN0CFDF09 (RSCAN0.CFDF09.UINT32)
+#define RSCAN0CFDF09L (RSCAN0.CFDF09.UINT16[R_IO_L])
+#define RSCAN0CFDF09LL (RSCAN0.CFDF09.UINT8[R_IO_LL])
+#define RSCAN0CFDF09LH (RSCAN0.CFDF09.UINT8[R_IO_LH])
+#define RSCAN0CFDF09H (RSCAN0.CFDF09.UINT16[R_IO_H])
+#define RSCAN0CFDF09HL (RSCAN0.CFDF09.UINT8[R_IO_HL])
+#define RSCAN0CFDF09HH (RSCAN0.CFDF09.UINT8[R_IO_HH])
+#define RSCAN0CFDF19 (RSCAN0.CFDF19.UINT32)
+#define RSCAN0CFDF19L (RSCAN0.CFDF19.UINT16[R_IO_L])
+#define RSCAN0CFDF19LL (RSCAN0.CFDF19.UINT8[R_IO_LL])
+#define RSCAN0CFDF19LH (RSCAN0.CFDF19.UINT8[R_IO_LH])
+#define RSCAN0CFDF19H (RSCAN0.CFDF19.UINT16[R_IO_H])
+#define RSCAN0CFDF19HL (RSCAN0.CFDF19.UINT8[R_IO_HL])
+#define RSCAN0CFDF19HH (RSCAN0.CFDF19.UINT8[R_IO_HH])
+#define RSCAN0CFID10 (RSCAN0.CFID10.UINT32)
+#define RSCAN0CFID10L (RSCAN0.CFID10.UINT16[R_IO_L])
+#define RSCAN0CFID10LL (RSCAN0.CFID10.UINT8[R_IO_LL])
+#define RSCAN0CFID10LH (RSCAN0.CFID10.UINT8[R_IO_LH])
+#define RSCAN0CFID10H (RSCAN0.CFID10.UINT16[R_IO_H])
+#define RSCAN0CFID10HL (RSCAN0.CFID10.UINT8[R_IO_HL])
+#define RSCAN0CFID10HH (RSCAN0.CFID10.UINT8[R_IO_HH])
+#define RSCAN0CFPTR10 (RSCAN0.CFPTR10.UINT32)
+#define RSCAN0CFPTR10L (RSCAN0.CFPTR10.UINT16[R_IO_L])
+#define RSCAN0CFPTR10LL (RSCAN0.CFPTR10.UINT8[R_IO_LL])
+#define RSCAN0CFPTR10LH (RSCAN0.CFPTR10.UINT8[R_IO_LH])
+#define RSCAN0CFPTR10H (RSCAN0.CFPTR10.UINT16[R_IO_H])
+#define RSCAN0CFPTR10HL (RSCAN0.CFPTR10.UINT8[R_IO_HL])
+#define RSCAN0CFPTR10HH (RSCAN0.CFPTR10.UINT8[R_IO_HH])
+#define RSCAN0CFDF010 (RSCAN0.CFDF010.UINT32)
+#define RSCAN0CFDF010L (RSCAN0.CFDF010.UINT16[R_IO_L])
+#define RSCAN0CFDF010LL (RSCAN0.CFDF010.UINT8[R_IO_LL])
+#define RSCAN0CFDF010LH (RSCAN0.CFDF010.UINT8[R_IO_LH])
+#define RSCAN0CFDF010H (RSCAN0.CFDF010.UINT16[R_IO_H])
+#define RSCAN0CFDF010HL (RSCAN0.CFDF010.UINT8[R_IO_HL])
+#define RSCAN0CFDF010HH (RSCAN0.CFDF010.UINT8[R_IO_HH])
+#define RSCAN0CFDF110 (RSCAN0.CFDF110.UINT32)
+#define RSCAN0CFDF110L (RSCAN0.CFDF110.UINT16[R_IO_L])
+#define RSCAN0CFDF110LL (RSCAN0.CFDF110.UINT8[R_IO_LL])
+#define RSCAN0CFDF110LH (RSCAN0.CFDF110.UINT8[R_IO_LH])
+#define RSCAN0CFDF110H (RSCAN0.CFDF110.UINT16[R_IO_H])
+#define RSCAN0CFDF110HL (RSCAN0.CFDF110.UINT8[R_IO_HL])
+#define RSCAN0CFDF110HH (RSCAN0.CFDF110.UINT8[R_IO_HH])
+#define RSCAN0CFID11 (RSCAN0.CFID11.UINT32)
+#define RSCAN0CFID11L (RSCAN0.CFID11.UINT16[R_IO_L])
+#define RSCAN0CFID11LL (RSCAN0.CFID11.UINT8[R_IO_LL])
+#define RSCAN0CFID11LH (RSCAN0.CFID11.UINT8[R_IO_LH])
+#define RSCAN0CFID11H (RSCAN0.CFID11.UINT16[R_IO_H])
+#define RSCAN0CFID11HL (RSCAN0.CFID11.UINT8[R_IO_HL])
+#define RSCAN0CFID11HH (RSCAN0.CFID11.UINT8[R_IO_HH])
+#define RSCAN0CFPTR11 (RSCAN0.CFPTR11.UINT32)
+#define RSCAN0CFPTR11L (RSCAN0.CFPTR11.UINT16[R_IO_L])
+#define RSCAN0CFPTR11LL (RSCAN0.CFPTR11.UINT8[R_IO_LL])
+#define RSCAN0CFPTR11LH (RSCAN0.CFPTR11.UINT8[R_IO_LH])
+#define RSCAN0CFPTR11H (RSCAN0.CFPTR11.UINT16[R_IO_H])
+#define RSCAN0CFPTR11HL (RSCAN0.CFPTR11.UINT8[R_IO_HL])
+#define RSCAN0CFPTR11HH (RSCAN0.CFPTR11.UINT8[R_IO_HH])
+#define RSCAN0CFDF011 (RSCAN0.CFDF011.UINT32)
+#define RSCAN0CFDF011L (RSCAN0.CFDF011.UINT16[R_IO_L])
+#define RSCAN0CFDF011LL (RSCAN0.CFDF011.UINT8[R_IO_LL])
+#define RSCAN0CFDF011LH (RSCAN0.CFDF011.UINT8[R_IO_LH])
+#define RSCAN0CFDF011H (RSCAN0.CFDF011.UINT16[R_IO_H])
+#define RSCAN0CFDF011HL (RSCAN0.CFDF011.UINT8[R_IO_HL])
+#define RSCAN0CFDF011HH (RSCAN0.CFDF011.UINT8[R_IO_HH])
+#define RSCAN0CFDF111 (RSCAN0.CFDF111.UINT32)
+#define RSCAN0CFDF111L (RSCAN0.CFDF111.UINT16[R_IO_L])
+#define RSCAN0CFDF111LL (RSCAN0.CFDF111.UINT8[R_IO_LL])
+#define RSCAN0CFDF111LH (RSCAN0.CFDF111.UINT8[R_IO_LH])
+#define RSCAN0CFDF111H (RSCAN0.CFDF111.UINT16[R_IO_H])
+#define RSCAN0CFDF111HL (RSCAN0.CFDF111.UINT8[R_IO_HL])
+#define RSCAN0CFDF111HH (RSCAN0.CFDF111.UINT8[R_IO_HH])
+#define RSCAN0CFID12 (RSCAN0.CFID12.UINT32)
+#define RSCAN0CFID12L (RSCAN0.CFID12.UINT16[R_IO_L])
+#define RSCAN0CFID12LL (RSCAN0.CFID12.UINT8[R_IO_LL])
+#define RSCAN0CFID12LH (RSCAN0.CFID12.UINT8[R_IO_LH])
+#define RSCAN0CFID12H (RSCAN0.CFID12.UINT16[R_IO_H])
+#define RSCAN0CFID12HL (RSCAN0.CFID12.UINT8[R_IO_HL])
+#define RSCAN0CFID12HH (RSCAN0.CFID12.UINT8[R_IO_HH])
+#define RSCAN0CFPTR12 (RSCAN0.CFPTR12.UINT32)
+#define RSCAN0CFPTR12L (RSCAN0.CFPTR12.UINT16[R_IO_L])
+#define RSCAN0CFPTR12LL (RSCAN0.CFPTR12.UINT8[R_IO_LL])
+#define RSCAN0CFPTR12LH (RSCAN0.CFPTR12.UINT8[R_IO_LH])
+#define RSCAN0CFPTR12H (RSCAN0.CFPTR12.UINT16[R_IO_H])
+#define RSCAN0CFPTR12HL (RSCAN0.CFPTR12.UINT8[R_IO_HL])
+#define RSCAN0CFPTR12HH (RSCAN0.CFPTR12.UINT8[R_IO_HH])
+#define RSCAN0CFDF012 (RSCAN0.CFDF012.UINT32)
+#define RSCAN0CFDF012L (RSCAN0.CFDF012.UINT16[R_IO_L])
+#define RSCAN0CFDF012LL (RSCAN0.CFDF012.UINT8[R_IO_LL])
+#define RSCAN0CFDF012LH (RSCAN0.CFDF012.UINT8[R_IO_LH])
+#define RSCAN0CFDF012H (RSCAN0.CFDF012.UINT16[R_IO_H])
+#define RSCAN0CFDF012HL (RSCAN0.CFDF012.UINT8[R_IO_HL])
+#define RSCAN0CFDF012HH (RSCAN0.CFDF012.UINT8[R_IO_HH])
+#define RSCAN0CFDF112 (RSCAN0.CFDF112.UINT32)
+#define RSCAN0CFDF112L (RSCAN0.CFDF112.UINT16[R_IO_L])
+#define RSCAN0CFDF112LL (RSCAN0.CFDF112.UINT8[R_IO_LL])
+#define RSCAN0CFDF112LH (RSCAN0.CFDF112.UINT8[R_IO_LH])
+#define RSCAN0CFDF112H (RSCAN0.CFDF112.UINT16[R_IO_H])
+#define RSCAN0CFDF112HL (RSCAN0.CFDF112.UINT8[R_IO_HL])
+#define RSCAN0CFDF112HH (RSCAN0.CFDF112.UINT8[R_IO_HH])
+#define RSCAN0CFID13 (RSCAN0.CFID13.UINT32)
+#define RSCAN0CFID13L (RSCAN0.CFID13.UINT16[R_IO_L])
+#define RSCAN0CFID13LL (RSCAN0.CFID13.UINT8[R_IO_LL])
+#define RSCAN0CFID13LH (RSCAN0.CFID13.UINT8[R_IO_LH])
+#define RSCAN0CFID13H (RSCAN0.CFID13.UINT16[R_IO_H])
+#define RSCAN0CFID13HL (RSCAN0.CFID13.UINT8[R_IO_HL])
+#define RSCAN0CFID13HH (RSCAN0.CFID13.UINT8[R_IO_HH])
+#define RSCAN0CFPTR13 (RSCAN0.CFPTR13.UINT32)
+#define RSCAN0CFPTR13L (RSCAN0.CFPTR13.UINT16[R_IO_L])
+#define RSCAN0CFPTR13LL (RSCAN0.CFPTR13.UINT8[R_IO_LL])
+#define RSCAN0CFPTR13LH (RSCAN0.CFPTR13.UINT8[R_IO_LH])
+#define RSCAN0CFPTR13H (RSCAN0.CFPTR13.UINT16[R_IO_H])
+#define RSCAN0CFPTR13HL (RSCAN0.CFPTR13.UINT8[R_IO_HL])
+#define RSCAN0CFPTR13HH (RSCAN0.CFPTR13.UINT8[R_IO_HH])
+#define RSCAN0CFDF013 (RSCAN0.CFDF013.UINT32)
+#define RSCAN0CFDF013L (RSCAN0.CFDF013.UINT16[R_IO_L])
+#define RSCAN0CFDF013LL (RSCAN0.CFDF013.UINT8[R_IO_LL])
+#define RSCAN0CFDF013LH (RSCAN0.CFDF013.UINT8[R_IO_LH])
+#define RSCAN0CFDF013H (RSCAN0.CFDF013.UINT16[R_IO_H])
+#define RSCAN0CFDF013HL (RSCAN0.CFDF013.UINT8[R_IO_HL])
+#define RSCAN0CFDF013HH (RSCAN0.CFDF013.UINT8[R_IO_HH])
+#define RSCAN0CFDF113 (RSCAN0.CFDF113.UINT32)
+#define RSCAN0CFDF113L (RSCAN0.CFDF113.UINT16[R_IO_L])
+#define RSCAN0CFDF113LL (RSCAN0.CFDF113.UINT8[R_IO_LL])
+#define RSCAN0CFDF113LH (RSCAN0.CFDF113.UINT8[R_IO_LH])
+#define RSCAN0CFDF113H (RSCAN0.CFDF113.UINT16[R_IO_H])
+#define RSCAN0CFDF113HL (RSCAN0.CFDF113.UINT8[R_IO_HL])
+#define RSCAN0CFDF113HH (RSCAN0.CFDF113.UINT8[R_IO_HH])
+#define RSCAN0CFID14 (RSCAN0.CFID14.UINT32)
+#define RSCAN0CFID14L (RSCAN0.CFID14.UINT16[R_IO_L])
+#define RSCAN0CFID14LL (RSCAN0.CFID14.UINT8[R_IO_LL])
+#define RSCAN0CFID14LH (RSCAN0.CFID14.UINT8[R_IO_LH])
+#define RSCAN0CFID14H (RSCAN0.CFID14.UINT16[R_IO_H])
+#define RSCAN0CFID14HL (RSCAN0.CFID14.UINT8[R_IO_HL])
+#define RSCAN0CFID14HH (RSCAN0.CFID14.UINT8[R_IO_HH])
+#define RSCAN0CFPTR14 (RSCAN0.CFPTR14.UINT32)
+#define RSCAN0CFPTR14L (RSCAN0.CFPTR14.UINT16[R_IO_L])
+#define RSCAN0CFPTR14LL (RSCAN0.CFPTR14.UINT8[R_IO_LL])
+#define RSCAN0CFPTR14LH (RSCAN0.CFPTR14.UINT8[R_IO_LH])
+#define RSCAN0CFPTR14H (RSCAN0.CFPTR14.UINT16[R_IO_H])
+#define RSCAN0CFPTR14HL (RSCAN0.CFPTR14.UINT8[R_IO_HL])
+#define RSCAN0CFPTR14HH (RSCAN0.CFPTR14.UINT8[R_IO_HH])
+#define RSCAN0CFDF014 (RSCAN0.CFDF014.UINT32)
+#define RSCAN0CFDF014L (RSCAN0.CFDF014.UINT16[R_IO_L])
+#define RSCAN0CFDF014LL (RSCAN0.CFDF014.UINT8[R_IO_LL])
+#define RSCAN0CFDF014LH (RSCAN0.CFDF014.UINT8[R_IO_LH])
+#define RSCAN0CFDF014H (RSCAN0.CFDF014.UINT16[R_IO_H])
+#define RSCAN0CFDF014HL (RSCAN0.CFDF014.UINT8[R_IO_HL])
+#define RSCAN0CFDF014HH (RSCAN0.CFDF014.UINT8[R_IO_HH])
+#define RSCAN0CFDF114 (RSCAN0.CFDF114.UINT32)
+#define RSCAN0CFDF114L (RSCAN0.CFDF114.UINT16[R_IO_L])
+#define RSCAN0CFDF114LL (RSCAN0.CFDF114.UINT8[R_IO_LL])
+#define RSCAN0CFDF114LH (RSCAN0.CFDF114.UINT8[R_IO_LH])
+#define RSCAN0CFDF114H (RSCAN0.CFDF114.UINT16[R_IO_H])
+#define RSCAN0CFDF114HL (RSCAN0.CFDF114.UINT8[R_IO_HL])
+#define RSCAN0CFDF114HH (RSCAN0.CFDF114.UINT8[R_IO_HH])
+#define RSCAN0TMID0 (RSCAN0.TMID0.UINT32)
+#define RSCAN0TMID0L (RSCAN0.TMID0.UINT16[R_IO_L])
+#define RSCAN0TMID0LL (RSCAN0.TMID0.UINT8[R_IO_LL])
+#define RSCAN0TMID0LH (RSCAN0.TMID0.UINT8[R_IO_LH])
+#define RSCAN0TMID0H (RSCAN0.TMID0.UINT16[R_IO_H])
+#define RSCAN0TMID0HL (RSCAN0.TMID0.UINT8[R_IO_HL])
+#define RSCAN0TMID0HH (RSCAN0.TMID0.UINT8[R_IO_HH])
+#define RSCAN0TMPTR0 (RSCAN0.TMPTR0.UINT32)
+#define RSCAN0TMPTR0L (RSCAN0.TMPTR0.UINT16[R_IO_L])
+#define RSCAN0TMPTR0LL (RSCAN0.TMPTR0.UINT8[R_IO_LL])
+#define RSCAN0TMPTR0LH (RSCAN0.TMPTR0.UINT8[R_IO_LH])
+#define RSCAN0TMPTR0H (RSCAN0.TMPTR0.UINT16[R_IO_H])
+#define RSCAN0TMPTR0HL (RSCAN0.TMPTR0.UINT8[R_IO_HL])
+#define RSCAN0TMPTR0HH (RSCAN0.TMPTR0.UINT8[R_IO_HH])
+#define RSCAN0TMDF00 (RSCAN0.TMDF00.UINT32)
+#define RSCAN0TMDF00L (RSCAN0.TMDF00.UINT16[R_IO_L])
+#define RSCAN0TMDF00LL (RSCAN0.TMDF00.UINT8[R_IO_LL])
+#define RSCAN0TMDF00LH (RSCAN0.TMDF00.UINT8[R_IO_LH])
+#define RSCAN0TMDF00H (RSCAN0.TMDF00.UINT16[R_IO_H])
+#define RSCAN0TMDF00HL (RSCAN0.TMDF00.UINT8[R_IO_HL])
+#define RSCAN0TMDF00HH (RSCAN0.TMDF00.UINT8[R_IO_HH])
+#define RSCAN0TMDF10 (RSCAN0.TMDF10.UINT32)
+#define RSCAN0TMDF10L (RSCAN0.TMDF10.UINT16[R_IO_L])
+#define RSCAN0TMDF10LL (RSCAN0.TMDF10.UINT8[R_IO_LL])
+#define RSCAN0TMDF10LH (RSCAN0.TMDF10.UINT8[R_IO_LH])
+#define RSCAN0TMDF10H (RSCAN0.TMDF10.UINT16[R_IO_H])
+#define RSCAN0TMDF10HL (RSCAN0.TMDF10.UINT8[R_IO_HL])
+#define RSCAN0TMDF10HH (RSCAN0.TMDF10.UINT8[R_IO_HH])
+#define RSCAN0TMID1 (RSCAN0.TMID1.UINT32)
+#define RSCAN0TMID1L (RSCAN0.TMID1.UINT16[R_IO_L])
+#define RSCAN0TMID1LL (RSCAN0.TMID1.UINT8[R_IO_LL])
+#define RSCAN0TMID1LH (RSCAN0.TMID1.UINT8[R_IO_LH])
+#define RSCAN0TMID1H (RSCAN0.TMID1.UINT16[R_IO_H])
+#define RSCAN0TMID1HL (RSCAN0.TMID1.UINT8[R_IO_HL])
+#define RSCAN0TMID1HH (RSCAN0.TMID1.UINT8[R_IO_HH])
+#define RSCAN0TMPTR1 (RSCAN0.TMPTR1.UINT32)
+#define RSCAN0TMPTR1L (RSCAN0.TMPTR1.UINT16[R_IO_L])
+#define RSCAN0TMPTR1LL (RSCAN0.TMPTR1.UINT8[R_IO_LL])
+#define RSCAN0TMPTR1LH (RSCAN0.TMPTR1.UINT8[R_IO_LH])
+#define RSCAN0TMPTR1H (RSCAN0.TMPTR1.UINT16[R_IO_H])
+#define RSCAN0TMPTR1HL (RSCAN0.TMPTR1.UINT8[R_IO_HL])
+#define RSCAN0TMPTR1HH (RSCAN0.TMPTR1.UINT8[R_IO_HH])
+#define RSCAN0TMDF01 (RSCAN0.TMDF01.UINT32)
+#define RSCAN0TMDF01L (RSCAN0.TMDF01.UINT16[R_IO_L])
+#define RSCAN0TMDF01LL (RSCAN0.TMDF01.UINT8[R_IO_LL])
+#define RSCAN0TMDF01LH (RSCAN0.TMDF01.UINT8[R_IO_LH])
+#define RSCAN0TMDF01H (RSCAN0.TMDF01.UINT16[R_IO_H])
+#define RSCAN0TMDF01HL (RSCAN0.TMDF01.UINT8[R_IO_HL])
+#define RSCAN0TMDF01HH (RSCAN0.TMDF01.UINT8[R_IO_HH])
+#define RSCAN0TMDF11 (RSCAN0.TMDF11.UINT32)
+#define RSCAN0TMDF11L (RSCAN0.TMDF11.UINT16[R_IO_L])
+#define RSCAN0TMDF11LL (RSCAN0.TMDF11.UINT8[R_IO_LL])
+#define RSCAN0TMDF11LH (RSCAN0.TMDF11.UINT8[R_IO_LH])
+#define RSCAN0TMDF11H (RSCAN0.TMDF11.UINT16[R_IO_H])
+#define RSCAN0TMDF11HL (RSCAN0.TMDF11.UINT8[R_IO_HL])
+#define RSCAN0TMDF11HH (RSCAN0.TMDF11.UINT8[R_IO_HH])
+#define RSCAN0TMID2 (RSCAN0.TMID2.UINT32)
+#define RSCAN0TMID2L (RSCAN0.TMID2.UINT16[R_IO_L])
+#define RSCAN0TMID2LL (RSCAN0.TMID2.UINT8[R_IO_LL])
+#define RSCAN0TMID2LH (RSCAN0.TMID2.UINT8[R_IO_LH])
+#define RSCAN0TMID2H (RSCAN0.TMID2.UINT16[R_IO_H])
+#define RSCAN0TMID2HL (RSCAN0.TMID2.UINT8[R_IO_HL])
+#define RSCAN0TMID2HH (RSCAN0.TMID2.UINT8[R_IO_HH])
+#define RSCAN0TMPTR2 (RSCAN0.TMPTR2.UINT32)
+#define RSCAN0TMPTR2L (RSCAN0.TMPTR2.UINT16[R_IO_L])
+#define RSCAN0TMPTR2LL (RSCAN0.TMPTR2.UINT8[R_IO_LL])
+#define RSCAN0TMPTR2LH (RSCAN0.TMPTR2.UINT8[R_IO_LH])
+#define RSCAN0TMPTR2H (RSCAN0.TMPTR2.UINT16[R_IO_H])
+#define RSCAN0TMPTR2HL (RSCAN0.TMPTR2.UINT8[R_IO_HL])
+#define RSCAN0TMPTR2HH (RSCAN0.TMPTR2.UINT8[R_IO_HH])
+#define RSCAN0TMDF02 (RSCAN0.TMDF02.UINT32)
+#define RSCAN0TMDF02L (RSCAN0.TMDF02.UINT16[R_IO_L])
+#define RSCAN0TMDF02LL (RSCAN0.TMDF02.UINT8[R_IO_LL])
+#define RSCAN0TMDF02LH (RSCAN0.TMDF02.UINT8[R_IO_LH])
+#define RSCAN0TMDF02H (RSCAN0.TMDF02.UINT16[R_IO_H])
+#define RSCAN0TMDF02HL (RSCAN0.TMDF02.UINT8[R_IO_HL])
+#define RSCAN0TMDF02HH (RSCAN0.TMDF02.UINT8[R_IO_HH])
+#define RSCAN0TMDF12 (RSCAN0.TMDF12.UINT32)
+#define RSCAN0TMDF12L (RSCAN0.TMDF12.UINT16[R_IO_L])
+#define RSCAN0TMDF12LL (RSCAN0.TMDF12.UINT8[R_IO_LL])
+#define RSCAN0TMDF12LH (RSCAN0.TMDF12.UINT8[R_IO_LH])
+#define RSCAN0TMDF12H (RSCAN0.TMDF12.UINT16[R_IO_H])
+#define RSCAN0TMDF12HL (RSCAN0.TMDF12.UINT8[R_IO_HL])
+#define RSCAN0TMDF12HH (RSCAN0.TMDF12.UINT8[R_IO_HH])
+#define RSCAN0TMID3 (RSCAN0.TMID3.UINT32)
+#define RSCAN0TMID3L (RSCAN0.TMID3.UINT16[R_IO_L])
+#define RSCAN0TMID3LL (RSCAN0.TMID3.UINT8[R_IO_LL])
+#define RSCAN0TMID3LH (RSCAN0.TMID3.UINT8[R_IO_LH])
+#define RSCAN0TMID3H (RSCAN0.TMID3.UINT16[R_IO_H])
+#define RSCAN0TMID3HL (RSCAN0.TMID3.UINT8[R_IO_HL])
+#define RSCAN0TMID3HH (RSCAN0.TMID3.UINT8[R_IO_HH])
+#define RSCAN0TMPTR3 (RSCAN0.TMPTR3.UINT32)
+#define RSCAN0TMPTR3L (RSCAN0.TMPTR3.UINT16[R_IO_L])
+#define RSCAN0TMPTR3LL (RSCAN0.TMPTR3.UINT8[R_IO_LL])
+#define RSCAN0TMPTR3LH (RSCAN0.TMPTR3.UINT8[R_IO_LH])
+#define RSCAN0TMPTR3H (RSCAN0.TMPTR3.UINT16[R_IO_H])
+#define RSCAN0TMPTR3HL (RSCAN0.TMPTR3.UINT8[R_IO_HL])
+#define RSCAN0TMPTR3HH (RSCAN0.TMPTR3.UINT8[R_IO_HH])
+#define RSCAN0TMDF03 (RSCAN0.TMDF03.UINT32)
+#define RSCAN0TMDF03L (RSCAN0.TMDF03.UINT16[R_IO_L])
+#define RSCAN0TMDF03LL (RSCAN0.TMDF03.UINT8[R_IO_LL])
+#define RSCAN0TMDF03LH (RSCAN0.TMDF03.UINT8[R_IO_LH])
+#define RSCAN0TMDF03H (RSCAN0.TMDF03.UINT16[R_IO_H])
+#define RSCAN0TMDF03HL (RSCAN0.TMDF03.UINT8[R_IO_HL])
+#define RSCAN0TMDF03HH (RSCAN0.TMDF03.UINT8[R_IO_HH])
+#define RSCAN0TMDF13 (RSCAN0.TMDF13.UINT32)
+#define RSCAN0TMDF13L (RSCAN0.TMDF13.UINT16[R_IO_L])
+#define RSCAN0TMDF13LL (RSCAN0.TMDF13.UINT8[R_IO_LL])
+#define RSCAN0TMDF13LH (RSCAN0.TMDF13.UINT8[R_IO_LH])
+#define RSCAN0TMDF13H (RSCAN0.TMDF13.UINT16[R_IO_H])
+#define RSCAN0TMDF13HL (RSCAN0.TMDF13.UINT8[R_IO_HL])
+#define RSCAN0TMDF13HH (RSCAN0.TMDF13.UINT8[R_IO_HH])
+#define RSCAN0TMID4 (RSCAN0.TMID4.UINT32)
+#define RSCAN0TMID4L (RSCAN0.TMID4.UINT16[R_IO_L])
+#define RSCAN0TMID4LL (RSCAN0.TMID4.UINT8[R_IO_LL])
+#define RSCAN0TMID4LH (RSCAN0.TMID4.UINT8[R_IO_LH])
+#define RSCAN0TMID4H (RSCAN0.TMID4.UINT16[R_IO_H])
+#define RSCAN0TMID4HL (RSCAN0.TMID4.UINT8[R_IO_HL])
+#define RSCAN0TMID4HH (RSCAN0.TMID4.UINT8[R_IO_HH])
+#define RSCAN0TMPTR4 (RSCAN0.TMPTR4.UINT32)
+#define RSCAN0TMPTR4L (RSCAN0.TMPTR4.UINT16[R_IO_L])
+#define RSCAN0TMPTR4LL (RSCAN0.TMPTR4.UINT8[R_IO_LL])
+#define RSCAN0TMPTR4LH (RSCAN0.TMPTR4.UINT8[R_IO_LH])
+#define RSCAN0TMPTR4H (RSCAN0.TMPTR4.UINT16[R_IO_H])
+#define RSCAN0TMPTR4HL (RSCAN0.TMPTR4.UINT8[R_IO_HL])
+#define RSCAN0TMPTR4HH (RSCAN0.TMPTR4.UINT8[R_IO_HH])
+#define RSCAN0TMDF04 (RSCAN0.TMDF04.UINT32)
+#define RSCAN0TMDF04L (RSCAN0.TMDF04.UINT16[R_IO_L])
+#define RSCAN0TMDF04LL (RSCAN0.TMDF04.UINT8[R_IO_LL])
+#define RSCAN0TMDF04LH (RSCAN0.TMDF04.UINT8[R_IO_LH])
+#define RSCAN0TMDF04H (RSCAN0.TMDF04.UINT16[R_IO_H])
+#define RSCAN0TMDF04HL (RSCAN0.TMDF04.UINT8[R_IO_HL])
+#define RSCAN0TMDF04HH (RSCAN0.TMDF04.UINT8[R_IO_HH])
+#define RSCAN0TMDF14 (RSCAN0.TMDF14.UINT32)
+#define RSCAN0TMDF14L (RSCAN0.TMDF14.UINT16[R_IO_L])
+#define RSCAN0TMDF14LL (RSCAN0.TMDF14.UINT8[R_IO_LL])
+#define RSCAN0TMDF14LH (RSCAN0.TMDF14.UINT8[R_IO_LH])
+#define RSCAN0TMDF14H (RSCAN0.TMDF14.UINT16[R_IO_H])
+#define RSCAN0TMDF14HL (RSCAN0.TMDF14.UINT8[R_IO_HL])
+#define RSCAN0TMDF14HH (RSCAN0.TMDF14.UINT8[R_IO_HH])
+#define RSCAN0TMID5 (RSCAN0.TMID5.UINT32)
+#define RSCAN0TMID5L (RSCAN0.TMID5.UINT16[R_IO_L])
+#define RSCAN0TMID5LL (RSCAN0.TMID5.UINT8[R_IO_LL])
+#define RSCAN0TMID5LH (RSCAN0.TMID5.UINT8[R_IO_LH])
+#define RSCAN0TMID5H (RSCAN0.TMID5.UINT16[R_IO_H])
+#define RSCAN0TMID5HL (RSCAN0.TMID5.UINT8[R_IO_HL])
+#define RSCAN0TMID5HH (RSCAN0.TMID5.UINT8[R_IO_HH])
+#define RSCAN0TMPTR5 (RSCAN0.TMPTR5.UINT32)
+#define RSCAN0TMPTR5L (RSCAN0.TMPTR5.UINT16[R_IO_L])
+#define RSCAN0TMPTR5LL (RSCAN0.TMPTR5.UINT8[R_IO_LL])
+#define RSCAN0TMPTR5LH (RSCAN0.TMPTR5.UINT8[R_IO_LH])
+#define RSCAN0TMPTR5H (RSCAN0.TMPTR5.UINT16[R_IO_H])
+#define RSCAN0TMPTR5HL (RSCAN0.TMPTR5.UINT8[R_IO_HL])
+#define RSCAN0TMPTR5HH (RSCAN0.TMPTR5.UINT8[R_IO_HH])
+#define RSCAN0TMDF05 (RSCAN0.TMDF05.UINT32)
+#define RSCAN0TMDF05L (RSCAN0.TMDF05.UINT16[R_IO_L])
+#define RSCAN0TMDF05LL (RSCAN0.TMDF05.UINT8[R_IO_LL])
+#define RSCAN0TMDF05LH (RSCAN0.TMDF05.UINT8[R_IO_LH])
+#define RSCAN0TMDF05H (RSCAN0.TMDF05.UINT16[R_IO_H])
+#define RSCAN0TMDF05HL (RSCAN0.TMDF05.UINT8[R_IO_HL])
+#define RSCAN0TMDF05HH (RSCAN0.TMDF05.UINT8[R_IO_HH])
+#define RSCAN0TMDF15 (RSCAN0.TMDF15.UINT32)
+#define RSCAN0TMDF15L (RSCAN0.TMDF15.UINT16[R_IO_L])
+#define RSCAN0TMDF15LL (RSCAN0.TMDF15.UINT8[R_IO_LL])
+#define RSCAN0TMDF15LH (RSCAN0.TMDF15.UINT8[R_IO_LH])
+#define RSCAN0TMDF15H (RSCAN0.TMDF15.UINT16[R_IO_H])
+#define RSCAN0TMDF15HL (RSCAN0.TMDF15.UINT8[R_IO_HL])
+#define RSCAN0TMDF15HH (RSCAN0.TMDF15.UINT8[R_IO_HH])
+#define RSCAN0TMID6 (RSCAN0.TMID6.UINT32)
+#define RSCAN0TMID6L (RSCAN0.TMID6.UINT16[R_IO_L])
+#define RSCAN0TMID6LL (RSCAN0.TMID6.UINT8[R_IO_LL])
+#define RSCAN0TMID6LH (RSCAN0.TMID6.UINT8[R_IO_LH])
+#define RSCAN0TMID6H (RSCAN0.TMID6.UINT16[R_IO_H])
+#define RSCAN0TMID6HL (RSCAN0.TMID6.UINT8[R_IO_HL])
+#define RSCAN0TMID6HH (RSCAN0.TMID6.UINT8[R_IO_HH])
+#define RSCAN0TMPTR6 (RSCAN0.TMPTR6.UINT32)
+#define RSCAN0TMPTR6L (RSCAN0.TMPTR6.UINT16[R_IO_L])
+#define RSCAN0TMPTR6LL (RSCAN0.TMPTR6.UINT8[R_IO_LL])
+#define RSCAN0TMPTR6LH (RSCAN0.TMPTR6.UINT8[R_IO_LH])
+#define RSCAN0TMPTR6H (RSCAN0.TMPTR6.UINT16[R_IO_H])
+#define RSCAN0TMPTR6HL (RSCAN0.TMPTR6.UINT8[R_IO_HL])
+#define RSCAN0TMPTR6HH (RSCAN0.TMPTR6.UINT8[R_IO_HH])
+#define RSCAN0TMDF06 (RSCAN0.TMDF06.UINT32)
+#define RSCAN0TMDF06L (RSCAN0.TMDF06.UINT16[R_IO_L])
+#define RSCAN0TMDF06LL (RSCAN0.TMDF06.UINT8[R_IO_LL])
+#define RSCAN0TMDF06LH (RSCAN0.TMDF06.UINT8[R_IO_LH])
+#define RSCAN0TMDF06H (RSCAN0.TMDF06.UINT16[R_IO_H])
+#define RSCAN0TMDF06HL (RSCAN0.TMDF06.UINT8[R_IO_HL])
+#define RSCAN0TMDF06HH (RSCAN0.TMDF06.UINT8[R_IO_HH])
+#define RSCAN0TMDF16 (RSCAN0.TMDF16.UINT32)
+#define RSCAN0TMDF16L (RSCAN0.TMDF16.UINT16[R_IO_L])
+#define RSCAN0TMDF16LL (RSCAN0.TMDF16.UINT8[R_IO_LL])
+#define RSCAN0TMDF16LH (RSCAN0.TMDF16.UINT8[R_IO_LH])
+#define RSCAN0TMDF16H (RSCAN0.TMDF16.UINT16[R_IO_H])
+#define RSCAN0TMDF16HL (RSCAN0.TMDF16.UINT8[R_IO_HL])
+#define RSCAN0TMDF16HH (RSCAN0.TMDF16.UINT8[R_IO_HH])
+#define RSCAN0TMID7 (RSCAN0.TMID7.UINT32)
+#define RSCAN0TMID7L (RSCAN0.TMID7.UINT16[R_IO_L])
+#define RSCAN0TMID7LL (RSCAN0.TMID7.UINT8[R_IO_LL])
+#define RSCAN0TMID7LH (RSCAN0.TMID7.UINT8[R_IO_LH])
+#define RSCAN0TMID7H (RSCAN0.TMID7.UINT16[R_IO_H])
+#define RSCAN0TMID7HL (RSCAN0.TMID7.UINT8[R_IO_HL])
+#define RSCAN0TMID7HH (RSCAN0.TMID7.UINT8[R_IO_HH])
+#define RSCAN0TMPTR7 (RSCAN0.TMPTR7.UINT32)
+#define RSCAN0TMPTR7L (RSCAN0.TMPTR7.UINT16[R_IO_L])
+#define RSCAN0TMPTR7LL (RSCAN0.TMPTR7.UINT8[R_IO_LL])
+#define RSCAN0TMPTR7LH (RSCAN0.TMPTR7.UINT8[R_IO_LH])
+#define RSCAN0TMPTR7H (RSCAN0.TMPTR7.UINT16[R_IO_H])
+#define RSCAN0TMPTR7HL (RSCAN0.TMPTR7.UINT8[R_IO_HL])
+#define RSCAN0TMPTR7HH (RSCAN0.TMPTR7.UINT8[R_IO_HH])
+#define RSCAN0TMDF07 (RSCAN0.TMDF07.UINT32)
+#define RSCAN0TMDF07L (RSCAN0.TMDF07.UINT16[R_IO_L])
+#define RSCAN0TMDF07LL (RSCAN0.TMDF07.UINT8[R_IO_LL])
+#define RSCAN0TMDF07LH (RSCAN0.TMDF07.UINT8[R_IO_LH])
+#define RSCAN0TMDF07H (RSCAN0.TMDF07.UINT16[R_IO_H])
+#define RSCAN0TMDF07HL (RSCAN0.TMDF07.UINT8[R_IO_HL])
+#define RSCAN0TMDF07HH (RSCAN0.TMDF07.UINT8[R_IO_HH])
+#define RSCAN0TMDF17 (RSCAN0.TMDF17.UINT32)
+#define RSCAN0TMDF17L (RSCAN0.TMDF17.UINT16[R_IO_L])
+#define RSCAN0TMDF17LL (RSCAN0.TMDF17.UINT8[R_IO_LL])
+#define RSCAN0TMDF17LH (RSCAN0.TMDF17.UINT8[R_IO_LH])
+#define RSCAN0TMDF17H (RSCAN0.TMDF17.UINT16[R_IO_H])
+#define RSCAN0TMDF17HL (RSCAN0.TMDF17.UINT8[R_IO_HL])
+#define RSCAN0TMDF17HH (RSCAN0.TMDF17.UINT8[R_IO_HH])
+#define RSCAN0TMID8 (RSCAN0.TMID8.UINT32)
+#define RSCAN0TMID8L (RSCAN0.TMID8.UINT16[R_IO_L])
+#define RSCAN0TMID8LL (RSCAN0.TMID8.UINT8[R_IO_LL])
+#define RSCAN0TMID8LH (RSCAN0.TMID8.UINT8[R_IO_LH])
+#define RSCAN0TMID8H (RSCAN0.TMID8.UINT16[R_IO_H])
+#define RSCAN0TMID8HL (RSCAN0.TMID8.UINT8[R_IO_HL])
+#define RSCAN0TMID8HH (RSCAN0.TMID8.UINT8[R_IO_HH])
+#define RSCAN0TMPTR8 (RSCAN0.TMPTR8.UINT32)
+#define RSCAN0TMPTR8L (RSCAN0.TMPTR8.UINT16[R_IO_L])
+#define RSCAN0TMPTR8LL (RSCAN0.TMPTR8.UINT8[R_IO_LL])
+#define RSCAN0TMPTR8LH (RSCAN0.TMPTR8.UINT8[R_IO_LH])
+#define RSCAN0TMPTR8H (RSCAN0.TMPTR8.UINT16[R_IO_H])
+#define RSCAN0TMPTR8HL (RSCAN0.TMPTR8.UINT8[R_IO_HL])
+#define RSCAN0TMPTR8HH (RSCAN0.TMPTR8.UINT8[R_IO_HH])
+#define RSCAN0TMDF08 (RSCAN0.TMDF08.UINT32)
+#define RSCAN0TMDF08L (RSCAN0.TMDF08.UINT16[R_IO_L])
+#define RSCAN0TMDF08LL (RSCAN0.TMDF08.UINT8[R_IO_LL])
+#define RSCAN0TMDF08LH (RSCAN0.TMDF08.UINT8[R_IO_LH])
+#define RSCAN0TMDF08H (RSCAN0.TMDF08.UINT16[R_IO_H])
+#define RSCAN0TMDF08HL (RSCAN0.TMDF08.UINT8[R_IO_HL])
+#define RSCAN0TMDF08HH (RSCAN0.TMDF08.UINT8[R_IO_HH])
+#define RSCAN0TMDF18 (RSCAN0.TMDF18.UINT32)
+#define RSCAN0TMDF18L (RSCAN0.TMDF18.UINT16[R_IO_L])
+#define RSCAN0TMDF18LL (RSCAN0.TMDF18.UINT8[R_IO_LL])
+#define RSCAN0TMDF18LH (RSCAN0.TMDF18.UINT8[R_IO_LH])
+#define RSCAN0TMDF18H (RSCAN0.TMDF18.UINT16[R_IO_H])
+#define RSCAN0TMDF18HL (RSCAN0.TMDF18.UINT8[R_IO_HL])
+#define RSCAN0TMDF18HH (RSCAN0.TMDF18.UINT8[R_IO_HH])
+#define RSCAN0TMID9 (RSCAN0.TMID9.UINT32)
+#define RSCAN0TMID9L (RSCAN0.TMID9.UINT16[R_IO_L])
+#define RSCAN0TMID9LL (RSCAN0.TMID9.UINT8[R_IO_LL])
+#define RSCAN0TMID9LH (RSCAN0.TMID9.UINT8[R_IO_LH])
+#define RSCAN0TMID9H (RSCAN0.TMID9.UINT16[R_IO_H])
+#define RSCAN0TMID9HL (RSCAN0.TMID9.UINT8[R_IO_HL])
+#define RSCAN0TMID9HH (RSCAN0.TMID9.UINT8[R_IO_HH])
+#define RSCAN0TMPTR9 (RSCAN0.TMPTR9.UINT32)
+#define RSCAN0TMPTR9L (RSCAN0.TMPTR9.UINT16[R_IO_L])
+#define RSCAN0TMPTR9LL (RSCAN0.TMPTR9.UINT8[R_IO_LL])
+#define RSCAN0TMPTR9LH (RSCAN0.TMPTR9.UINT8[R_IO_LH])
+#define RSCAN0TMPTR9H (RSCAN0.TMPTR9.UINT16[R_IO_H])
+#define RSCAN0TMPTR9HL (RSCAN0.TMPTR9.UINT8[R_IO_HL])
+#define RSCAN0TMPTR9HH (RSCAN0.TMPTR9.UINT8[R_IO_HH])
+#define RSCAN0TMDF09 (RSCAN0.TMDF09.UINT32)
+#define RSCAN0TMDF09L (RSCAN0.TMDF09.UINT16[R_IO_L])
+#define RSCAN0TMDF09LL (RSCAN0.TMDF09.UINT8[R_IO_LL])
+#define RSCAN0TMDF09LH (RSCAN0.TMDF09.UINT8[R_IO_LH])
+#define RSCAN0TMDF09H (RSCAN0.TMDF09.UINT16[R_IO_H])
+#define RSCAN0TMDF09HL (RSCAN0.TMDF09.UINT8[R_IO_HL])
+#define RSCAN0TMDF09HH (RSCAN0.TMDF09.UINT8[R_IO_HH])
+#define RSCAN0TMDF19 (RSCAN0.TMDF19.UINT32)
+#define RSCAN0TMDF19L (RSCAN0.TMDF19.UINT16[R_IO_L])
+#define RSCAN0TMDF19LL (RSCAN0.TMDF19.UINT8[R_IO_LL])
+#define RSCAN0TMDF19LH (RSCAN0.TMDF19.UINT8[R_IO_LH])
+#define RSCAN0TMDF19H (RSCAN0.TMDF19.UINT16[R_IO_H])
+#define RSCAN0TMDF19HL (RSCAN0.TMDF19.UINT8[R_IO_HL])
+#define RSCAN0TMDF19HH (RSCAN0.TMDF19.UINT8[R_IO_HH])
+#define RSCAN0TMID10 (RSCAN0.TMID10.UINT32)
+#define RSCAN0TMID10L (RSCAN0.TMID10.UINT16[R_IO_L])
+#define RSCAN0TMID10LL (RSCAN0.TMID10.UINT8[R_IO_LL])
+#define RSCAN0TMID10LH (RSCAN0.TMID10.UINT8[R_IO_LH])
+#define RSCAN0TMID10H (RSCAN0.TMID10.UINT16[R_IO_H])
+#define RSCAN0TMID10HL (RSCAN0.TMID10.UINT8[R_IO_HL])
+#define RSCAN0TMID10HH (RSCAN0.TMID10.UINT8[R_IO_HH])
+#define RSCAN0TMPTR10 (RSCAN0.TMPTR10.UINT32)
+#define RSCAN0TMPTR10L (RSCAN0.TMPTR10.UINT16[R_IO_L])
+#define RSCAN0TMPTR10LL (RSCAN0.TMPTR10.UINT8[R_IO_LL])
+#define RSCAN0TMPTR10LH (RSCAN0.TMPTR10.UINT8[R_IO_LH])
+#define RSCAN0TMPTR10H (RSCAN0.TMPTR10.UINT16[R_IO_H])
+#define RSCAN0TMPTR10HL (RSCAN0.TMPTR10.UINT8[R_IO_HL])
+#define RSCAN0TMPTR10HH (RSCAN0.TMPTR10.UINT8[R_IO_HH])
+#define RSCAN0TMDF010 (RSCAN0.TMDF010.UINT32)
+#define RSCAN0TMDF010L (RSCAN0.TMDF010.UINT16[R_IO_L])
+#define RSCAN0TMDF010LL (RSCAN0.TMDF010.UINT8[R_IO_LL])
+#define RSCAN0TMDF010LH (RSCAN0.TMDF010.UINT8[R_IO_LH])
+#define RSCAN0TMDF010H (RSCAN0.TMDF010.UINT16[R_IO_H])
+#define RSCAN0TMDF010HL (RSCAN0.TMDF010.UINT8[R_IO_HL])
+#define RSCAN0TMDF010HH (RSCAN0.TMDF010.UINT8[R_IO_HH])
+#define RSCAN0TMDF110 (RSCAN0.TMDF110.UINT32)
+#define RSCAN0TMDF110L (RSCAN0.TMDF110.UINT16[R_IO_L])
+#define RSCAN0TMDF110LL (RSCAN0.TMDF110.UINT8[R_IO_LL])
+#define RSCAN0TMDF110LH (RSCAN0.TMDF110.UINT8[R_IO_LH])
+#define RSCAN0TMDF110H (RSCAN0.TMDF110.UINT16[R_IO_H])
+#define RSCAN0TMDF110HL (RSCAN0.TMDF110.UINT8[R_IO_HL])
+#define RSCAN0TMDF110HH (RSCAN0.TMDF110.UINT8[R_IO_HH])
+#define RSCAN0TMID11 (RSCAN0.TMID11.UINT32)
+#define RSCAN0TMID11L (RSCAN0.TMID11.UINT16[R_IO_L])
+#define RSCAN0TMID11LL (RSCAN0.TMID11.UINT8[R_IO_LL])
+#define RSCAN0TMID11LH (RSCAN0.TMID11.UINT8[R_IO_LH])
+#define RSCAN0TMID11H (RSCAN0.TMID11.UINT16[R_IO_H])
+#define RSCAN0TMID11HL (RSCAN0.TMID11.UINT8[R_IO_HL])
+#define RSCAN0TMID11HH (RSCAN0.TMID11.UINT8[R_IO_HH])
+#define RSCAN0TMPTR11 (RSCAN0.TMPTR11.UINT32)
+#define RSCAN0TMPTR11L (RSCAN0.TMPTR11.UINT16[R_IO_L])
+#define RSCAN0TMPTR11LL (RSCAN0.TMPTR11.UINT8[R_IO_LL])
+#define RSCAN0TMPTR11LH (RSCAN0.TMPTR11.UINT8[R_IO_LH])
+#define RSCAN0TMPTR11H (RSCAN0.TMPTR11.UINT16[R_IO_H])
+#define RSCAN0TMPTR11HL (RSCAN0.TMPTR11.UINT8[R_IO_HL])
+#define RSCAN0TMPTR11HH (RSCAN0.TMPTR11.UINT8[R_IO_HH])
+#define RSCAN0TMDF011 (RSCAN0.TMDF011.UINT32)
+#define RSCAN0TMDF011L (RSCAN0.TMDF011.UINT16[R_IO_L])
+#define RSCAN0TMDF011LL (RSCAN0.TMDF011.UINT8[R_IO_LL])
+#define RSCAN0TMDF011LH (RSCAN0.TMDF011.UINT8[R_IO_LH])
+#define RSCAN0TMDF011H (RSCAN0.TMDF011.UINT16[R_IO_H])
+#define RSCAN0TMDF011HL (RSCAN0.TMDF011.UINT8[R_IO_HL])
+#define RSCAN0TMDF011HH (RSCAN0.TMDF011.UINT8[R_IO_HH])
+#define RSCAN0TMDF111 (RSCAN0.TMDF111.UINT32)
+#define RSCAN0TMDF111L (RSCAN0.TMDF111.UINT16[R_IO_L])
+#define RSCAN0TMDF111LL (RSCAN0.TMDF111.UINT8[R_IO_LL])
+#define RSCAN0TMDF111LH (RSCAN0.TMDF111.UINT8[R_IO_LH])
+#define RSCAN0TMDF111H (RSCAN0.TMDF111.UINT16[R_IO_H])
+#define RSCAN0TMDF111HL (RSCAN0.TMDF111.UINT8[R_IO_HL])
+#define RSCAN0TMDF111HH (RSCAN0.TMDF111.UINT8[R_IO_HH])
+#define RSCAN0TMID12 (RSCAN0.TMID12.UINT32)
+#define RSCAN0TMID12L (RSCAN0.TMID12.UINT16[R_IO_L])
+#define RSCAN0TMID12LL (RSCAN0.TMID12.UINT8[R_IO_LL])
+#define RSCAN0TMID12LH (RSCAN0.TMID12.UINT8[R_IO_LH])
+#define RSCAN0TMID12H (RSCAN0.TMID12.UINT16[R_IO_H])
+#define RSCAN0TMID12HL (RSCAN0.TMID12.UINT8[R_IO_HL])
+#define RSCAN0TMID12HH (RSCAN0.TMID12.UINT8[R_IO_HH])
+#define RSCAN0TMPTR12 (RSCAN0.TMPTR12.UINT32)
+#define RSCAN0TMPTR12L (RSCAN0.TMPTR12.UINT16[R_IO_L])
+#define RSCAN0TMPTR12LL (RSCAN0.TMPTR12.UINT8[R_IO_LL])
+#define RSCAN0TMPTR12LH (RSCAN0.TMPTR12.UINT8[R_IO_LH])
+#define RSCAN0TMPTR12H (RSCAN0.TMPTR12.UINT16[R_IO_H])
+#define RSCAN0TMPTR12HL (RSCAN0.TMPTR12.UINT8[R_IO_HL])
+#define RSCAN0TMPTR12HH (RSCAN0.TMPTR12.UINT8[R_IO_HH])
+#define RSCAN0TMDF012 (RSCAN0.TMDF012.UINT32)
+#define RSCAN0TMDF012L (RSCAN0.TMDF012.UINT16[R_IO_L])
+#define RSCAN0TMDF012LL (RSCAN0.TMDF012.UINT8[R_IO_LL])
+#define RSCAN0TMDF012LH (RSCAN0.TMDF012.UINT8[R_IO_LH])
+#define RSCAN0TMDF012H (RSCAN0.TMDF012.UINT16[R_IO_H])
+#define RSCAN0TMDF012HL (RSCAN0.TMDF012.UINT8[R_IO_HL])
+#define RSCAN0TMDF012HH (RSCAN0.TMDF012.UINT8[R_IO_HH])
+#define RSCAN0TMDF112 (RSCAN0.TMDF112.UINT32)
+#define RSCAN0TMDF112L (RSCAN0.TMDF112.UINT16[R_IO_L])
+#define RSCAN0TMDF112LL (RSCAN0.TMDF112.UINT8[R_IO_LL])
+#define RSCAN0TMDF112LH (RSCAN0.TMDF112.UINT8[R_IO_LH])
+#define RSCAN0TMDF112H (RSCAN0.TMDF112.UINT16[R_IO_H])
+#define RSCAN0TMDF112HL (RSCAN0.TMDF112.UINT8[R_IO_HL])
+#define RSCAN0TMDF112HH (RSCAN0.TMDF112.UINT8[R_IO_HH])
+#define RSCAN0TMID13 (RSCAN0.TMID13.UINT32)
+#define RSCAN0TMID13L (RSCAN0.TMID13.UINT16[R_IO_L])
+#define RSCAN0TMID13LL (RSCAN0.TMID13.UINT8[R_IO_LL])
+#define RSCAN0TMID13LH (RSCAN0.TMID13.UINT8[R_IO_LH])
+#define RSCAN0TMID13H (RSCAN0.TMID13.UINT16[R_IO_H])
+#define RSCAN0TMID13HL (RSCAN0.TMID13.UINT8[R_IO_HL])
+#define RSCAN0TMID13HH (RSCAN0.TMID13.UINT8[R_IO_HH])
+#define RSCAN0TMPTR13 (RSCAN0.TMPTR13.UINT32)
+#define RSCAN0TMPTR13L (RSCAN0.TMPTR13.UINT16[R_IO_L])
+#define RSCAN0TMPTR13LL (RSCAN0.TMPTR13.UINT8[R_IO_LL])
+#define RSCAN0TMPTR13LH (RSCAN0.TMPTR13.UINT8[R_IO_LH])
+#define RSCAN0TMPTR13H (RSCAN0.TMPTR13.UINT16[R_IO_H])
+#define RSCAN0TMPTR13HL (RSCAN0.TMPTR13.UINT8[R_IO_HL])
+#define RSCAN0TMPTR13HH (RSCAN0.TMPTR13.UINT8[R_IO_HH])
+#define RSCAN0TMDF013 (RSCAN0.TMDF013.UINT32)
+#define RSCAN0TMDF013L (RSCAN0.TMDF013.UINT16[R_IO_L])
+#define RSCAN0TMDF013LL (RSCAN0.TMDF013.UINT8[R_IO_LL])
+#define RSCAN0TMDF013LH (RSCAN0.TMDF013.UINT8[R_IO_LH])
+#define RSCAN0TMDF013H (RSCAN0.TMDF013.UINT16[R_IO_H])
+#define RSCAN0TMDF013HL (RSCAN0.TMDF013.UINT8[R_IO_HL])
+#define RSCAN0TMDF013HH (RSCAN0.TMDF013.UINT8[R_IO_HH])
+#define RSCAN0TMDF113 (RSCAN0.TMDF113.UINT32)
+#define RSCAN0TMDF113L (RSCAN0.TMDF113.UINT16[R_IO_L])
+#define RSCAN0TMDF113LL (RSCAN0.TMDF113.UINT8[R_IO_LL])
+#define RSCAN0TMDF113LH (RSCAN0.TMDF113.UINT8[R_IO_LH])
+#define RSCAN0TMDF113H (RSCAN0.TMDF113.UINT16[R_IO_H])
+#define RSCAN0TMDF113HL (RSCAN0.TMDF113.UINT8[R_IO_HL])
+#define RSCAN0TMDF113HH (RSCAN0.TMDF113.UINT8[R_IO_HH])
+#define RSCAN0TMID14 (RSCAN0.TMID14.UINT32)
+#define RSCAN0TMID14L (RSCAN0.TMID14.UINT16[R_IO_L])
+#define RSCAN0TMID14LL (RSCAN0.TMID14.UINT8[R_IO_LL])
+#define RSCAN0TMID14LH (RSCAN0.TMID14.UINT8[R_IO_LH])
+#define RSCAN0TMID14H (RSCAN0.TMID14.UINT16[R_IO_H])
+#define RSCAN0TMID14HL (RSCAN0.TMID14.UINT8[R_IO_HL])
+#define RSCAN0TMID14HH (RSCAN0.TMID14.UINT8[R_IO_HH])
+#define RSCAN0TMPTR14 (RSCAN0.TMPTR14.UINT32)
+#define RSCAN0TMPTR14L (RSCAN0.TMPTR14.UINT16[R_IO_L])
+#define RSCAN0TMPTR14LL (RSCAN0.TMPTR14.UINT8[R_IO_LL])
+#define RSCAN0TMPTR14LH (RSCAN0.TMPTR14.UINT8[R_IO_LH])
+#define RSCAN0TMPTR14H (RSCAN0.TMPTR14.UINT16[R_IO_H])
+#define RSCAN0TMPTR14HL (RSCAN0.TMPTR14.UINT8[R_IO_HL])
+#define RSCAN0TMPTR14HH (RSCAN0.TMPTR14.UINT8[R_IO_HH])
+#define RSCAN0TMDF014 (RSCAN0.TMDF014.UINT32)
+#define RSCAN0TMDF014L (RSCAN0.TMDF014.UINT16[R_IO_L])
+#define RSCAN0TMDF014LL (RSCAN0.TMDF014.UINT8[R_IO_LL])
+#define RSCAN0TMDF014LH (RSCAN0.TMDF014.UINT8[R_IO_LH])
+#define RSCAN0TMDF014H (RSCAN0.TMDF014.UINT16[R_IO_H])
+#define RSCAN0TMDF014HL (RSCAN0.TMDF014.UINT8[R_IO_HL])
+#define RSCAN0TMDF014HH (RSCAN0.TMDF014.UINT8[R_IO_HH])
+#define RSCAN0TMDF114 (RSCAN0.TMDF114.UINT32)
+#define RSCAN0TMDF114L (RSCAN0.TMDF114.UINT16[R_IO_L])
+#define RSCAN0TMDF114LL (RSCAN0.TMDF114.UINT8[R_IO_LL])
+#define RSCAN0TMDF114LH (RSCAN0.TMDF114.UINT8[R_IO_LH])
+#define RSCAN0TMDF114H (RSCAN0.TMDF114.UINT16[R_IO_H])
+#define RSCAN0TMDF114HL (RSCAN0.TMDF114.UINT8[R_IO_HL])
+#define RSCAN0TMDF114HH (RSCAN0.TMDF114.UINT8[R_IO_HH])
+#define RSCAN0TMID15 (RSCAN0.TMID15.UINT32)
+#define RSCAN0TMID15L (RSCAN0.TMID15.UINT16[R_IO_L])
+#define RSCAN0TMID15LL (RSCAN0.TMID15.UINT8[R_IO_LL])
+#define RSCAN0TMID15LH (RSCAN0.TMID15.UINT8[R_IO_LH])
+#define RSCAN0TMID15H (RSCAN0.TMID15.UINT16[R_IO_H])
+#define RSCAN0TMID15HL (RSCAN0.TMID15.UINT8[R_IO_HL])
+#define RSCAN0TMID15HH (RSCAN0.TMID15.UINT8[R_IO_HH])
+#define RSCAN0TMPTR15 (RSCAN0.TMPTR15.UINT32)
+#define RSCAN0TMPTR15L (RSCAN0.TMPTR15.UINT16[R_IO_L])
+#define RSCAN0TMPTR15LL (RSCAN0.TMPTR15.UINT8[R_IO_LL])
+#define RSCAN0TMPTR15LH (RSCAN0.TMPTR15.UINT8[R_IO_LH])
+#define RSCAN0TMPTR15H (RSCAN0.TMPTR15.UINT16[R_IO_H])
+#define RSCAN0TMPTR15HL (RSCAN0.TMPTR15.UINT8[R_IO_HL])
+#define RSCAN0TMPTR15HH (RSCAN0.TMPTR15.UINT8[R_IO_HH])
+#define RSCAN0TMDF015 (RSCAN0.TMDF015.UINT32)
+#define RSCAN0TMDF015L (RSCAN0.TMDF015.UINT16[R_IO_L])
+#define RSCAN0TMDF015LL (RSCAN0.TMDF015.UINT8[R_IO_LL])
+#define RSCAN0TMDF015LH (RSCAN0.TMDF015.UINT8[R_IO_LH])
+#define RSCAN0TMDF015H (RSCAN0.TMDF015.UINT16[R_IO_H])
+#define RSCAN0TMDF015HL (RSCAN0.TMDF015.UINT8[R_IO_HL])
+#define RSCAN0TMDF015HH (RSCAN0.TMDF015.UINT8[R_IO_HH])
+#define RSCAN0TMDF115 (RSCAN0.TMDF115.UINT32)
+#define RSCAN0TMDF115L (RSCAN0.TMDF115.UINT16[R_IO_L])
+#define RSCAN0TMDF115LL (RSCAN0.TMDF115.UINT8[R_IO_LL])
+#define RSCAN0TMDF115LH (RSCAN0.TMDF115.UINT8[R_IO_LH])
+#define RSCAN0TMDF115H (RSCAN0.TMDF115.UINT16[R_IO_H])
+#define RSCAN0TMDF115HL (RSCAN0.TMDF115.UINT8[R_IO_HL])
+#define RSCAN0TMDF115HH (RSCAN0.TMDF115.UINT8[R_IO_HH])
+#define RSCAN0TMID16 (RSCAN0.TMID16.UINT32)
+#define RSCAN0TMID16L (RSCAN0.TMID16.UINT16[R_IO_L])
+#define RSCAN0TMID16LL (RSCAN0.TMID16.UINT8[R_IO_LL])
+#define RSCAN0TMID16LH (RSCAN0.TMID16.UINT8[R_IO_LH])
+#define RSCAN0TMID16H (RSCAN0.TMID16.UINT16[R_IO_H])
+#define RSCAN0TMID16HL (RSCAN0.TMID16.UINT8[R_IO_HL])
+#define RSCAN0TMID16HH (RSCAN0.TMID16.UINT8[R_IO_HH])
+#define RSCAN0TMPTR16 (RSCAN0.TMPTR16.UINT32)
+#define RSCAN0TMPTR16L (RSCAN0.TMPTR16.UINT16[R_IO_L])
+#define RSCAN0TMPTR16LL (RSCAN0.TMPTR16.UINT8[R_IO_LL])
+#define RSCAN0TMPTR16LH (RSCAN0.TMPTR16.UINT8[R_IO_LH])
+#define RSCAN0TMPTR16H (RSCAN0.TMPTR16.UINT16[R_IO_H])
+#define RSCAN0TMPTR16HL (RSCAN0.TMPTR16.UINT8[R_IO_HL])
+#define RSCAN0TMPTR16HH (RSCAN0.TMPTR16.UINT8[R_IO_HH])
+#define RSCAN0TMDF016 (RSCAN0.TMDF016.UINT32)
+#define RSCAN0TMDF016L (RSCAN0.TMDF016.UINT16[R_IO_L])
+#define RSCAN0TMDF016LL (RSCAN0.TMDF016.UINT8[R_IO_LL])
+#define RSCAN0TMDF016LH (RSCAN0.TMDF016.UINT8[R_IO_LH])
+#define RSCAN0TMDF016H (RSCAN0.TMDF016.UINT16[R_IO_H])
+#define RSCAN0TMDF016HL (RSCAN0.TMDF016.UINT8[R_IO_HL])
+#define RSCAN0TMDF016HH (RSCAN0.TMDF016.UINT8[R_IO_HH])
+#define RSCAN0TMDF116 (RSCAN0.TMDF116.UINT32)
+#define RSCAN0TMDF116L (RSCAN0.TMDF116.UINT16[R_IO_L])
+#define RSCAN0TMDF116LL (RSCAN0.TMDF116.UINT8[R_IO_LL])
+#define RSCAN0TMDF116LH (RSCAN0.TMDF116.UINT8[R_IO_LH])
+#define RSCAN0TMDF116H (RSCAN0.TMDF116.UINT16[R_IO_H])
+#define RSCAN0TMDF116HL (RSCAN0.TMDF116.UINT8[R_IO_HL])
+#define RSCAN0TMDF116HH (RSCAN0.TMDF116.UINT8[R_IO_HH])
+#define RSCAN0TMID17 (RSCAN0.TMID17.UINT32)
+#define RSCAN0TMID17L (RSCAN0.TMID17.UINT16[R_IO_L])
+#define RSCAN0TMID17LL (RSCAN0.TMID17.UINT8[R_IO_LL])
+#define RSCAN0TMID17LH (RSCAN0.TMID17.UINT8[R_IO_LH])
+#define RSCAN0TMID17H (RSCAN0.TMID17.UINT16[R_IO_H])
+#define RSCAN0TMID17HL (RSCAN0.TMID17.UINT8[R_IO_HL])
+#define RSCAN0TMID17HH (RSCAN0.TMID17.UINT8[R_IO_HH])
+#define RSCAN0TMPTR17 (RSCAN0.TMPTR17.UINT32)
+#define RSCAN0TMPTR17L (RSCAN0.TMPTR17.UINT16[R_IO_L])
+#define RSCAN0TMPTR17LL (RSCAN0.TMPTR17.UINT8[R_IO_LL])
+#define RSCAN0TMPTR17LH (RSCAN0.TMPTR17.UINT8[R_IO_LH])
+#define RSCAN0TMPTR17H (RSCAN0.TMPTR17.UINT16[R_IO_H])
+#define RSCAN0TMPTR17HL (RSCAN0.TMPTR17.UINT8[R_IO_HL])
+#define RSCAN0TMPTR17HH (RSCAN0.TMPTR17.UINT8[R_IO_HH])
+#define RSCAN0TMDF017 (RSCAN0.TMDF017.UINT32)
+#define RSCAN0TMDF017L (RSCAN0.TMDF017.UINT16[R_IO_L])
+#define RSCAN0TMDF017LL (RSCAN0.TMDF017.UINT8[R_IO_LL])
+#define RSCAN0TMDF017LH (RSCAN0.TMDF017.UINT8[R_IO_LH])
+#define RSCAN0TMDF017H (RSCAN0.TMDF017.UINT16[R_IO_H])
+#define RSCAN0TMDF017HL (RSCAN0.TMDF017.UINT8[R_IO_HL])
+#define RSCAN0TMDF017HH (RSCAN0.TMDF017.UINT8[R_IO_HH])
+#define RSCAN0TMDF117 (RSCAN0.TMDF117.UINT32)
+#define RSCAN0TMDF117L (RSCAN0.TMDF117.UINT16[R_IO_L])
+#define RSCAN0TMDF117LL (RSCAN0.TMDF117.UINT8[R_IO_LL])
+#define RSCAN0TMDF117LH (RSCAN0.TMDF117.UINT8[R_IO_LH])
+#define RSCAN0TMDF117H (RSCAN0.TMDF117.UINT16[R_IO_H])
+#define RSCAN0TMDF117HL (RSCAN0.TMDF117.UINT8[R_IO_HL])
+#define RSCAN0TMDF117HH (RSCAN0.TMDF117.UINT8[R_IO_HH])
+#define RSCAN0TMID18 (RSCAN0.TMID18.UINT32)
+#define RSCAN0TMID18L (RSCAN0.TMID18.UINT16[R_IO_L])
+#define RSCAN0TMID18LL (RSCAN0.TMID18.UINT8[R_IO_LL])
+#define RSCAN0TMID18LH (RSCAN0.TMID18.UINT8[R_IO_LH])
+#define RSCAN0TMID18H (RSCAN0.TMID18.UINT16[R_IO_H])
+#define RSCAN0TMID18HL (RSCAN0.TMID18.UINT8[R_IO_HL])
+#define RSCAN0TMID18HH (RSCAN0.TMID18.UINT8[R_IO_HH])
+#define RSCAN0TMPTR18 (RSCAN0.TMPTR18.UINT32)
+#define RSCAN0TMPTR18L (RSCAN0.TMPTR18.UINT16[R_IO_L])
+#define RSCAN0TMPTR18LL (RSCAN0.TMPTR18.UINT8[R_IO_LL])
+#define RSCAN0TMPTR18LH (RSCAN0.TMPTR18.UINT8[R_IO_LH])
+#define RSCAN0TMPTR18H (RSCAN0.TMPTR18.UINT16[R_IO_H])
+#define RSCAN0TMPTR18HL (RSCAN0.TMPTR18.UINT8[R_IO_HL])
+#define RSCAN0TMPTR18HH (RSCAN0.TMPTR18.UINT8[R_IO_HH])
+#define RSCAN0TMDF018 (RSCAN0.TMDF018.UINT32)
+#define RSCAN0TMDF018L (RSCAN0.TMDF018.UINT16[R_IO_L])
+#define RSCAN0TMDF018LL (RSCAN0.TMDF018.UINT8[R_IO_LL])
+#define RSCAN0TMDF018LH (RSCAN0.TMDF018.UINT8[R_IO_LH])
+#define RSCAN0TMDF018H (RSCAN0.TMDF018.UINT16[R_IO_H])
+#define RSCAN0TMDF018HL (RSCAN0.TMDF018.UINT8[R_IO_HL])
+#define RSCAN0TMDF018HH (RSCAN0.TMDF018.UINT8[R_IO_HH])
+#define RSCAN0TMDF118 (RSCAN0.TMDF118.UINT32)
+#define RSCAN0TMDF118L (RSCAN0.TMDF118.UINT16[R_IO_L])
+#define RSCAN0TMDF118LL (RSCAN0.TMDF118.UINT8[R_IO_LL])
+#define RSCAN0TMDF118LH (RSCAN0.TMDF118.UINT8[R_IO_LH])
+#define RSCAN0TMDF118H (RSCAN0.TMDF118.UINT16[R_IO_H])
+#define RSCAN0TMDF118HL (RSCAN0.TMDF118.UINT8[R_IO_HL])
+#define RSCAN0TMDF118HH (RSCAN0.TMDF118.UINT8[R_IO_HH])
+#define RSCAN0TMID19 (RSCAN0.TMID19.UINT32)
+#define RSCAN0TMID19L (RSCAN0.TMID19.UINT16[R_IO_L])
+#define RSCAN0TMID19LL (RSCAN0.TMID19.UINT8[R_IO_LL])
+#define RSCAN0TMID19LH (RSCAN0.TMID19.UINT8[R_IO_LH])
+#define RSCAN0TMID19H (RSCAN0.TMID19.UINT16[R_IO_H])
+#define RSCAN0TMID19HL (RSCAN0.TMID19.UINT8[R_IO_HL])
+#define RSCAN0TMID19HH (RSCAN0.TMID19.UINT8[R_IO_HH])
+#define RSCAN0TMPTR19 (RSCAN0.TMPTR19.UINT32)
+#define RSCAN0TMPTR19L (RSCAN0.TMPTR19.UINT16[R_IO_L])
+#define RSCAN0TMPTR19LL (RSCAN0.TMPTR19.UINT8[R_IO_LL])
+#define RSCAN0TMPTR19LH (RSCAN0.TMPTR19.UINT8[R_IO_LH])
+#define RSCAN0TMPTR19H (RSCAN0.TMPTR19.UINT16[R_IO_H])
+#define RSCAN0TMPTR19HL (RSCAN0.TMPTR19.UINT8[R_IO_HL])
+#define RSCAN0TMPTR19HH (RSCAN0.TMPTR19.UINT8[R_IO_HH])
+#define RSCAN0TMDF019 (RSCAN0.TMDF019.UINT32)
+#define RSCAN0TMDF019L (RSCAN0.TMDF019.UINT16[R_IO_L])
+#define RSCAN0TMDF019LL (RSCAN0.TMDF019.UINT8[R_IO_LL])
+#define RSCAN0TMDF019LH (RSCAN0.TMDF019.UINT8[R_IO_LH])
+#define RSCAN0TMDF019H (RSCAN0.TMDF019.UINT16[R_IO_H])
+#define RSCAN0TMDF019HL (RSCAN0.TMDF019.UINT8[R_IO_HL])
+#define RSCAN0TMDF019HH (RSCAN0.TMDF019.UINT8[R_IO_HH])
+#define RSCAN0TMDF119 (RSCAN0.TMDF119.UINT32)
+#define RSCAN0TMDF119L (RSCAN0.TMDF119.UINT16[R_IO_L])
+#define RSCAN0TMDF119LL (RSCAN0.TMDF119.UINT8[R_IO_LL])
+#define RSCAN0TMDF119LH (RSCAN0.TMDF119.UINT8[R_IO_LH])
+#define RSCAN0TMDF119H (RSCAN0.TMDF119.UINT16[R_IO_H])
+#define RSCAN0TMDF119HL (RSCAN0.TMDF119.UINT8[R_IO_HL])
+#define RSCAN0TMDF119HH (RSCAN0.TMDF119.UINT8[R_IO_HH])
+#define RSCAN0TMID20 (RSCAN0.TMID20.UINT32)
+#define RSCAN0TMID20L (RSCAN0.TMID20.UINT16[R_IO_L])
+#define RSCAN0TMID20LL (RSCAN0.TMID20.UINT8[R_IO_LL])
+#define RSCAN0TMID20LH (RSCAN0.TMID20.UINT8[R_IO_LH])
+#define RSCAN0TMID20H (RSCAN0.TMID20.UINT16[R_IO_H])
+#define RSCAN0TMID20HL (RSCAN0.TMID20.UINT8[R_IO_HL])
+#define RSCAN0TMID20HH (RSCAN0.TMID20.UINT8[R_IO_HH])
+#define RSCAN0TMPTR20 (RSCAN0.TMPTR20.UINT32)
+#define RSCAN0TMPTR20L (RSCAN0.TMPTR20.UINT16[R_IO_L])
+#define RSCAN0TMPTR20LL (RSCAN0.TMPTR20.UINT8[R_IO_LL])
+#define RSCAN0TMPTR20LH (RSCAN0.TMPTR20.UINT8[R_IO_LH])
+#define RSCAN0TMPTR20H (RSCAN0.TMPTR20.UINT16[R_IO_H])
+#define RSCAN0TMPTR20HL (RSCAN0.TMPTR20.UINT8[R_IO_HL])
+#define RSCAN0TMPTR20HH (RSCAN0.TMPTR20.UINT8[R_IO_HH])
+#define RSCAN0TMDF020 (RSCAN0.TMDF020.UINT32)
+#define RSCAN0TMDF020L (RSCAN0.TMDF020.UINT16[R_IO_L])
+#define RSCAN0TMDF020LL (RSCAN0.TMDF020.UINT8[R_IO_LL])
+#define RSCAN0TMDF020LH (RSCAN0.TMDF020.UINT8[R_IO_LH])
+#define RSCAN0TMDF020H (RSCAN0.TMDF020.UINT16[R_IO_H])
+#define RSCAN0TMDF020HL (RSCAN0.TMDF020.UINT8[R_IO_HL])
+#define RSCAN0TMDF020HH (RSCAN0.TMDF020.UINT8[R_IO_HH])
+#define RSCAN0TMDF120 (RSCAN0.TMDF120.UINT32)
+#define RSCAN0TMDF120L (RSCAN0.TMDF120.UINT16[R_IO_L])
+#define RSCAN0TMDF120LL (RSCAN0.TMDF120.UINT8[R_IO_LL])
+#define RSCAN0TMDF120LH (RSCAN0.TMDF120.UINT8[R_IO_LH])
+#define RSCAN0TMDF120H (RSCAN0.TMDF120.UINT16[R_IO_H])
+#define RSCAN0TMDF120HL (RSCAN0.TMDF120.UINT8[R_IO_HL])
+#define RSCAN0TMDF120HH (RSCAN0.TMDF120.UINT8[R_IO_HH])
+#define RSCAN0TMID21 (RSCAN0.TMID21.UINT32)
+#define RSCAN0TMID21L (RSCAN0.TMID21.UINT16[R_IO_L])
+#define RSCAN0TMID21LL (RSCAN0.TMID21.UINT8[R_IO_LL])
+#define RSCAN0TMID21LH (RSCAN0.TMID21.UINT8[R_IO_LH])
+#define RSCAN0TMID21H (RSCAN0.TMID21.UINT16[R_IO_H])
+#define RSCAN0TMID21HL (RSCAN0.TMID21.UINT8[R_IO_HL])
+#define RSCAN0TMID21HH (RSCAN0.TMID21.UINT8[R_IO_HH])
+#define RSCAN0TMPTR21 (RSCAN0.TMPTR21.UINT32)
+#define RSCAN0TMPTR21L (RSCAN0.TMPTR21.UINT16[R_IO_L])
+#define RSCAN0TMPTR21LL (RSCAN0.TMPTR21.UINT8[R_IO_LL])
+#define RSCAN0TMPTR21LH (RSCAN0.TMPTR21.UINT8[R_IO_LH])
+#define RSCAN0TMPTR21H (RSCAN0.TMPTR21.UINT16[R_IO_H])
+#define RSCAN0TMPTR21HL (RSCAN0.TMPTR21.UINT8[R_IO_HL])
+#define RSCAN0TMPTR21HH (RSCAN0.TMPTR21.UINT8[R_IO_HH])
+#define RSCAN0TMDF021 (RSCAN0.TMDF021.UINT32)
+#define RSCAN0TMDF021L (RSCAN0.TMDF021.UINT16[R_IO_L])
+#define RSCAN0TMDF021LL (RSCAN0.TMDF021.UINT8[R_IO_LL])
+#define RSCAN0TMDF021LH (RSCAN0.TMDF021.UINT8[R_IO_LH])
+#define RSCAN0TMDF021H (RSCAN0.TMDF021.UINT16[R_IO_H])
+#define RSCAN0TMDF021HL (RSCAN0.TMDF021.UINT8[R_IO_HL])
+#define RSCAN0TMDF021HH (RSCAN0.TMDF021.UINT8[R_IO_HH])
+#define RSCAN0TMDF121 (RSCAN0.TMDF121.UINT32)
+#define RSCAN0TMDF121L (RSCAN0.TMDF121.UINT16[R_IO_L])
+#define RSCAN0TMDF121LL (RSCAN0.TMDF121.UINT8[R_IO_LL])
+#define RSCAN0TMDF121LH (RSCAN0.TMDF121.UINT8[R_IO_LH])
+#define RSCAN0TMDF121H (RSCAN0.TMDF121.UINT16[R_IO_H])
+#define RSCAN0TMDF121HL (RSCAN0.TMDF121.UINT8[R_IO_HL])
+#define RSCAN0TMDF121HH (RSCAN0.TMDF121.UINT8[R_IO_HH])
+#define RSCAN0TMID22 (RSCAN0.TMID22.UINT32)
+#define RSCAN0TMID22L (RSCAN0.TMID22.UINT16[R_IO_L])
+#define RSCAN0TMID22LL (RSCAN0.TMID22.UINT8[R_IO_LL])
+#define RSCAN0TMID22LH (RSCAN0.TMID22.UINT8[R_IO_LH])
+#define RSCAN0TMID22H (RSCAN0.TMID22.UINT16[R_IO_H])
+#define RSCAN0TMID22HL (RSCAN0.TMID22.UINT8[R_IO_HL])
+#define RSCAN0TMID22HH (RSCAN0.TMID22.UINT8[R_IO_HH])
+#define RSCAN0TMPTR22 (RSCAN0.TMPTR22.UINT32)
+#define RSCAN0TMPTR22L (RSCAN0.TMPTR22.UINT16[R_IO_L])
+#define RSCAN0TMPTR22LL (RSCAN0.TMPTR22.UINT8[R_IO_LL])
+#define RSCAN0TMPTR22LH (RSCAN0.TMPTR22.UINT8[R_IO_LH])
+#define RSCAN0TMPTR22H (RSCAN0.TMPTR22.UINT16[R_IO_H])
+#define RSCAN0TMPTR22HL (RSCAN0.TMPTR22.UINT8[R_IO_HL])
+#define RSCAN0TMPTR22HH (RSCAN0.TMPTR22.UINT8[R_IO_HH])
+#define RSCAN0TMDF022 (RSCAN0.TMDF022.UINT32)
+#define RSCAN0TMDF022L (RSCAN0.TMDF022.UINT16[R_IO_L])
+#define RSCAN0TMDF022LL (RSCAN0.TMDF022.UINT8[R_IO_LL])
+#define RSCAN0TMDF022LH (RSCAN0.TMDF022.UINT8[R_IO_LH])
+#define RSCAN0TMDF022H (RSCAN0.TMDF022.UINT16[R_IO_H])
+#define RSCAN0TMDF022HL (RSCAN0.TMDF022.UINT8[R_IO_HL])
+#define RSCAN0TMDF022HH (RSCAN0.TMDF022.UINT8[R_IO_HH])
+#define RSCAN0TMDF122 (RSCAN0.TMDF122.UINT32)
+#define RSCAN0TMDF122L (RSCAN0.TMDF122.UINT16[R_IO_L])
+#define RSCAN0TMDF122LL (RSCAN0.TMDF122.UINT8[R_IO_LL])
+#define RSCAN0TMDF122LH (RSCAN0.TMDF122.UINT8[R_IO_LH])
+#define RSCAN0TMDF122H (RSCAN0.TMDF122.UINT16[R_IO_H])
+#define RSCAN0TMDF122HL (RSCAN0.TMDF122.UINT8[R_IO_HL])
+#define RSCAN0TMDF122HH (RSCAN0.TMDF122.UINT8[R_IO_HH])
+#define RSCAN0TMID23 (RSCAN0.TMID23.UINT32)
+#define RSCAN0TMID23L (RSCAN0.TMID23.UINT16[R_IO_L])
+#define RSCAN0TMID23LL (RSCAN0.TMID23.UINT8[R_IO_LL])
+#define RSCAN0TMID23LH (RSCAN0.TMID23.UINT8[R_IO_LH])
+#define RSCAN0TMID23H (RSCAN0.TMID23.UINT16[R_IO_H])
+#define RSCAN0TMID23HL (RSCAN0.TMID23.UINT8[R_IO_HL])
+#define RSCAN0TMID23HH (RSCAN0.TMID23.UINT8[R_IO_HH])
+#define RSCAN0TMPTR23 (RSCAN0.TMPTR23.UINT32)
+#define RSCAN0TMPTR23L (RSCAN0.TMPTR23.UINT16[R_IO_L])
+#define RSCAN0TMPTR23LL (RSCAN0.TMPTR23.UINT8[R_IO_LL])
+#define RSCAN0TMPTR23LH (RSCAN0.TMPTR23.UINT8[R_IO_LH])
+#define RSCAN0TMPTR23H (RSCAN0.TMPTR23.UINT16[R_IO_H])
+#define RSCAN0TMPTR23HL (RSCAN0.TMPTR23.UINT8[R_IO_HL])
+#define RSCAN0TMPTR23HH (RSCAN0.TMPTR23.UINT8[R_IO_HH])
+#define RSCAN0TMDF023 (RSCAN0.TMDF023.UINT32)
+#define RSCAN0TMDF023L (RSCAN0.TMDF023.UINT16[R_IO_L])
+#define RSCAN0TMDF023LL (RSCAN0.TMDF023.UINT8[R_IO_LL])
+#define RSCAN0TMDF023LH (RSCAN0.TMDF023.UINT8[R_IO_LH])
+#define RSCAN0TMDF023H (RSCAN0.TMDF023.UINT16[R_IO_H])
+#define RSCAN0TMDF023HL (RSCAN0.TMDF023.UINT8[R_IO_HL])
+#define RSCAN0TMDF023HH (RSCAN0.TMDF023.UINT8[R_IO_HH])
+#define RSCAN0TMDF123 (RSCAN0.TMDF123.UINT32)
+#define RSCAN0TMDF123L (RSCAN0.TMDF123.UINT16[R_IO_L])
+#define RSCAN0TMDF123LL (RSCAN0.TMDF123.UINT8[R_IO_LL])
+#define RSCAN0TMDF123LH (RSCAN0.TMDF123.UINT8[R_IO_LH])
+#define RSCAN0TMDF123H (RSCAN0.TMDF123.UINT16[R_IO_H])
+#define RSCAN0TMDF123HL (RSCAN0.TMDF123.UINT8[R_IO_HL])
+#define RSCAN0TMDF123HH (RSCAN0.TMDF123.UINT8[R_IO_HH])
+#define RSCAN0TMID24 (RSCAN0.TMID24.UINT32)
+#define RSCAN0TMID24L (RSCAN0.TMID24.UINT16[R_IO_L])
+#define RSCAN0TMID24LL (RSCAN0.TMID24.UINT8[R_IO_LL])
+#define RSCAN0TMID24LH (RSCAN0.TMID24.UINT8[R_IO_LH])
+#define RSCAN0TMID24H (RSCAN0.TMID24.UINT16[R_IO_H])
+#define RSCAN0TMID24HL (RSCAN0.TMID24.UINT8[R_IO_HL])
+#define RSCAN0TMID24HH (RSCAN0.TMID24.UINT8[R_IO_HH])
+#define RSCAN0TMPTR24 (RSCAN0.TMPTR24.UINT32)
+#define RSCAN0TMPTR24L (RSCAN0.TMPTR24.UINT16[R_IO_L])
+#define RSCAN0TMPTR24LL (RSCAN0.TMPTR24.UINT8[R_IO_LL])
+#define RSCAN0TMPTR24LH (RSCAN0.TMPTR24.UINT8[R_IO_LH])
+#define RSCAN0TMPTR24H (RSCAN0.TMPTR24.UINT16[R_IO_H])
+#define RSCAN0TMPTR24HL (RSCAN0.TMPTR24.UINT8[R_IO_HL])
+#define RSCAN0TMPTR24HH (RSCAN0.TMPTR24.UINT8[R_IO_HH])
+#define RSCAN0TMDF024 (RSCAN0.TMDF024.UINT32)
+#define RSCAN0TMDF024L (RSCAN0.TMDF024.UINT16[R_IO_L])
+#define RSCAN0TMDF024LL (RSCAN0.TMDF024.UINT8[R_IO_LL])
+#define RSCAN0TMDF024LH (RSCAN0.TMDF024.UINT8[R_IO_LH])
+#define RSCAN0TMDF024H (RSCAN0.TMDF024.UINT16[R_IO_H])
+#define RSCAN0TMDF024HL (RSCAN0.TMDF024.UINT8[R_IO_HL])
+#define RSCAN0TMDF024HH (RSCAN0.TMDF024.UINT8[R_IO_HH])
+#define RSCAN0TMDF124 (RSCAN0.TMDF124.UINT32)
+#define RSCAN0TMDF124L (RSCAN0.TMDF124.UINT16[R_IO_L])
+#define RSCAN0TMDF124LL (RSCAN0.TMDF124.UINT8[R_IO_LL])
+#define RSCAN0TMDF124LH (RSCAN0.TMDF124.UINT8[R_IO_LH])
+#define RSCAN0TMDF124H (RSCAN0.TMDF124.UINT16[R_IO_H])
+#define RSCAN0TMDF124HL (RSCAN0.TMDF124.UINT8[R_IO_HL])
+#define RSCAN0TMDF124HH (RSCAN0.TMDF124.UINT8[R_IO_HH])
+#define RSCAN0TMID25 (RSCAN0.TMID25.UINT32)
+#define RSCAN0TMID25L (RSCAN0.TMID25.UINT16[R_IO_L])
+#define RSCAN0TMID25LL (RSCAN0.TMID25.UINT8[R_IO_LL])
+#define RSCAN0TMID25LH (RSCAN0.TMID25.UINT8[R_IO_LH])
+#define RSCAN0TMID25H (RSCAN0.TMID25.UINT16[R_IO_H])
+#define RSCAN0TMID25HL (RSCAN0.TMID25.UINT8[R_IO_HL])
+#define RSCAN0TMID25HH (RSCAN0.TMID25.UINT8[R_IO_HH])
+#define RSCAN0TMPTR25 (RSCAN0.TMPTR25.UINT32)
+#define RSCAN0TMPTR25L (RSCAN0.TMPTR25.UINT16[R_IO_L])
+#define RSCAN0TMPTR25LL (RSCAN0.TMPTR25.UINT8[R_IO_LL])
+#define RSCAN0TMPTR25LH (RSCAN0.TMPTR25.UINT8[R_IO_LH])
+#define RSCAN0TMPTR25H (RSCAN0.TMPTR25.UINT16[R_IO_H])
+#define RSCAN0TMPTR25HL (RSCAN0.TMPTR25.UINT8[R_IO_HL])
+#define RSCAN0TMPTR25HH (RSCAN0.TMPTR25.UINT8[R_IO_HH])
+#define RSCAN0TMDF025 (RSCAN0.TMDF025.UINT32)
+#define RSCAN0TMDF025L (RSCAN0.TMDF025.UINT16[R_IO_L])
+#define RSCAN0TMDF025LL (RSCAN0.TMDF025.UINT8[R_IO_LL])
+#define RSCAN0TMDF025LH (RSCAN0.TMDF025.UINT8[R_IO_LH])
+#define RSCAN0TMDF025H (RSCAN0.TMDF025.UINT16[R_IO_H])
+#define RSCAN0TMDF025HL (RSCAN0.TMDF025.UINT8[R_IO_HL])
+#define RSCAN0TMDF025HH (RSCAN0.TMDF025.UINT8[R_IO_HH])
+#define RSCAN0TMDF125 (RSCAN0.TMDF125.UINT32)
+#define RSCAN0TMDF125L (RSCAN0.TMDF125.UINT16[R_IO_L])
+#define RSCAN0TMDF125LL (RSCAN0.TMDF125.UINT8[R_IO_LL])
+#define RSCAN0TMDF125LH (RSCAN0.TMDF125.UINT8[R_IO_LH])
+#define RSCAN0TMDF125H (RSCAN0.TMDF125.UINT16[R_IO_H])
+#define RSCAN0TMDF125HL (RSCAN0.TMDF125.UINT8[R_IO_HL])
+#define RSCAN0TMDF125HH (RSCAN0.TMDF125.UINT8[R_IO_HH])
+#define RSCAN0TMID26 (RSCAN0.TMID26.UINT32)
+#define RSCAN0TMID26L (RSCAN0.TMID26.UINT16[R_IO_L])
+#define RSCAN0TMID26LL (RSCAN0.TMID26.UINT8[R_IO_LL])
+#define RSCAN0TMID26LH (RSCAN0.TMID26.UINT8[R_IO_LH])
+#define RSCAN0TMID26H (RSCAN0.TMID26.UINT16[R_IO_H])
+#define RSCAN0TMID26HL (RSCAN0.TMID26.UINT8[R_IO_HL])
+#define RSCAN0TMID26HH (RSCAN0.TMID26.UINT8[R_IO_HH])
+#define RSCAN0TMPTR26 (RSCAN0.TMPTR26.UINT32)
+#define RSCAN0TMPTR26L (RSCAN0.TMPTR26.UINT16[R_IO_L])
+#define RSCAN0TMPTR26LL (RSCAN0.TMPTR26.UINT8[R_IO_LL])
+#define RSCAN0TMPTR26LH (RSCAN0.TMPTR26.UINT8[R_IO_LH])
+#define RSCAN0TMPTR26H (RSCAN0.TMPTR26.UINT16[R_IO_H])
+#define RSCAN0TMPTR26HL (RSCAN0.TMPTR26.UINT8[R_IO_HL])
+#define RSCAN0TMPTR26HH (RSCAN0.TMPTR26.UINT8[R_IO_HH])
+#define RSCAN0TMDF026 (RSCAN0.TMDF026.UINT32)
+#define RSCAN0TMDF026L (RSCAN0.TMDF026.UINT16[R_IO_L])
+#define RSCAN0TMDF026LL (RSCAN0.TMDF026.UINT8[R_IO_LL])
+#define RSCAN0TMDF026LH (RSCAN0.TMDF026.UINT8[R_IO_LH])
+#define RSCAN0TMDF026H (RSCAN0.TMDF026.UINT16[R_IO_H])
+#define RSCAN0TMDF026HL (RSCAN0.TMDF026.UINT8[R_IO_HL])
+#define RSCAN0TMDF026HH (RSCAN0.TMDF026.UINT8[R_IO_HH])
+#define RSCAN0TMDF126 (RSCAN0.TMDF126.UINT32)
+#define RSCAN0TMDF126L (RSCAN0.TMDF126.UINT16[R_IO_L])
+#define RSCAN0TMDF126LL (RSCAN0.TMDF126.UINT8[R_IO_LL])
+#define RSCAN0TMDF126LH (RSCAN0.TMDF126.UINT8[R_IO_LH])
+#define RSCAN0TMDF126H (RSCAN0.TMDF126.UINT16[R_IO_H])
+#define RSCAN0TMDF126HL (RSCAN0.TMDF126.UINT8[R_IO_HL])
+#define RSCAN0TMDF126HH (RSCAN0.TMDF126.UINT8[R_IO_HH])
+#define RSCAN0TMID27 (RSCAN0.TMID27.UINT32)
+#define RSCAN0TMID27L (RSCAN0.TMID27.UINT16[R_IO_L])
+#define RSCAN0TMID27LL (RSCAN0.TMID27.UINT8[R_IO_LL])
+#define RSCAN0TMID27LH (RSCAN0.TMID27.UINT8[R_IO_LH])
+#define RSCAN0TMID27H (RSCAN0.TMID27.UINT16[R_IO_H])
+#define RSCAN0TMID27HL (RSCAN0.TMID27.UINT8[R_IO_HL])
+#define RSCAN0TMID27HH (RSCAN0.TMID27.UINT8[R_IO_HH])
+#define RSCAN0TMPTR27 (RSCAN0.TMPTR27.UINT32)
+#define RSCAN0TMPTR27L (RSCAN0.TMPTR27.UINT16[R_IO_L])
+#define RSCAN0TMPTR27LL (RSCAN0.TMPTR27.UINT8[R_IO_LL])
+#define RSCAN0TMPTR27LH (RSCAN0.TMPTR27.UINT8[R_IO_LH])
+#define RSCAN0TMPTR27H (RSCAN0.TMPTR27.UINT16[R_IO_H])
+#define RSCAN0TMPTR27HL (RSCAN0.TMPTR27.UINT8[R_IO_HL])
+#define RSCAN0TMPTR27HH (RSCAN0.TMPTR27.UINT8[R_IO_HH])
+#define RSCAN0TMDF027 (RSCAN0.TMDF027.UINT32)
+#define RSCAN0TMDF027L (RSCAN0.TMDF027.UINT16[R_IO_L])
+#define RSCAN0TMDF027LL (RSCAN0.TMDF027.UINT8[R_IO_LL])
+#define RSCAN0TMDF027LH (RSCAN0.TMDF027.UINT8[R_IO_LH])
+#define RSCAN0TMDF027H (RSCAN0.TMDF027.UINT16[R_IO_H])
+#define RSCAN0TMDF027HL (RSCAN0.TMDF027.UINT8[R_IO_HL])
+#define RSCAN0TMDF027HH (RSCAN0.TMDF027.UINT8[R_IO_HH])
+#define RSCAN0TMDF127 (RSCAN0.TMDF127.UINT32)
+#define RSCAN0TMDF127L (RSCAN0.TMDF127.UINT16[R_IO_L])
+#define RSCAN0TMDF127LL (RSCAN0.TMDF127.UINT8[R_IO_LL])
+#define RSCAN0TMDF127LH (RSCAN0.TMDF127.UINT8[R_IO_LH])
+#define RSCAN0TMDF127H (RSCAN0.TMDF127.UINT16[R_IO_H])
+#define RSCAN0TMDF127HL (RSCAN0.TMDF127.UINT8[R_IO_HL])
+#define RSCAN0TMDF127HH (RSCAN0.TMDF127.UINT8[R_IO_HH])
+#define RSCAN0TMID28 (RSCAN0.TMID28.UINT32)
+#define RSCAN0TMID28L (RSCAN0.TMID28.UINT16[R_IO_L])
+#define RSCAN0TMID28LL (RSCAN0.TMID28.UINT8[R_IO_LL])
+#define RSCAN0TMID28LH (RSCAN0.TMID28.UINT8[R_IO_LH])
+#define RSCAN0TMID28H (RSCAN0.TMID28.UINT16[R_IO_H])
+#define RSCAN0TMID28HL (RSCAN0.TMID28.UINT8[R_IO_HL])
+#define RSCAN0TMID28HH (RSCAN0.TMID28.UINT8[R_IO_HH])
+#define RSCAN0TMPTR28 (RSCAN0.TMPTR28.UINT32)
+#define RSCAN0TMPTR28L (RSCAN0.TMPTR28.UINT16[R_IO_L])
+#define RSCAN0TMPTR28LL (RSCAN0.TMPTR28.UINT8[R_IO_LL])
+#define RSCAN0TMPTR28LH (RSCAN0.TMPTR28.UINT8[R_IO_LH])
+#define RSCAN0TMPTR28H (RSCAN0.TMPTR28.UINT16[R_IO_H])
+#define RSCAN0TMPTR28HL (RSCAN0.TMPTR28.UINT8[R_IO_HL])
+#define RSCAN0TMPTR28HH (RSCAN0.TMPTR28.UINT8[R_IO_HH])
+#define RSCAN0TMDF028 (RSCAN0.TMDF028.UINT32)
+#define RSCAN0TMDF028L (RSCAN0.TMDF028.UINT16[R_IO_L])
+#define RSCAN0TMDF028LL (RSCAN0.TMDF028.UINT8[R_IO_LL])
+#define RSCAN0TMDF028LH (RSCAN0.TMDF028.UINT8[R_IO_LH])
+#define RSCAN0TMDF028H (RSCAN0.TMDF028.UINT16[R_IO_H])
+#define RSCAN0TMDF028HL (RSCAN0.TMDF028.UINT8[R_IO_HL])
+#define RSCAN0TMDF028HH (RSCAN0.TMDF028.UINT8[R_IO_HH])
+#define RSCAN0TMDF128 (RSCAN0.TMDF128.UINT32)
+#define RSCAN0TMDF128L (RSCAN0.TMDF128.UINT16[R_IO_L])
+#define RSCAN0TMDF128LL (RSCAN0.TMDF128.UINT8[R_IO_LL])
+#define RSCAN0TMDF128LH (RSCAN0.TMDF128.UINT8[R_IO_LH])
+#define RSCAN0TMDF128H (RSCAN0.TMDF128.UINT16[R_IO_H])
+#define RSCAN0TMDF128HL (RSCAN0.TMDF128.UINT8[R_IO_HL])
+#define RSCAN0TMDF128HH (RSCAN0.TMDF128.UINT8[R_IO_HH])
+#define RSCAN0TMID29 (RSCAN0.TMID29.UINT32)
+#define RSCAN0TMID29L (RSCAN0.TMID29.UINT16[R_IO_L])
+#define RSCAN0TMID29LL (RSCAN0.TMID29.UINT8[R_IO_LL])
+#define RSCAN0TMID29LH (RSCAN0.TMID29.UINT8[R_IO_LH])
+#define RSCAN0TMID29H (RSCAN0.TMID29.UINT16[R_IO_H])
+#define RSCAN0TMID29HL (RSCAN0.TMID29.UINT8[R_IO_HL])
+#define RSCAN0TMID29HH (RSCAN0.TMID29.UINT8[R_IO_HH])
+#define RSCAN0TMPTR29 (RSCAN0.TMPTR29.UINT32)
+#define RSCAN0TMPTR29L (RSCAN0.TMPTR29.UINT16[R_IO_L])
+#define RSCAN0TMPTR29LL (RSCAN0.TMPTR29.UINT8[R_IO_LL])
+#define RSCAN0TMPTR29LH (RSCAN0.TMPTR29.UINT8[R_IO_LH])
+#define RSCAN0TMPTR29H (RSCAN0.TMPTR29.UINT16[R_IO_H])
+#define RSCAN0TMPTR29HL (RSCAN0.TMPTR29.UINT8[R_IO_HL])
+#define RSCAN0TMPTR29HH (RSCAN0.TMPTR29.UINT8[R_IO_HH])
+#define RSCAN0TMDF029 (RSCAN0.TMDF029.UINT32)
+#define RSCAN0TMDF029L (RSCAN0.TMDF029.UINT16[R_IO_L])
+#define RSCAN0TMDF029LL (RSCAN0.TMDF029.UINT8[R_IO_LL])
+#define RSCAN0TMDF029LH (RSCAN0.TMDF029.UINT8[R_IO_LH])
+#define RSCAN0TMDF029H (RSCAN0.TMDF029.UINT16[R_IO_H])
+#define RSCAN0TMDF029HL (RSCAN0.TMDF029.UINT8[R_IO_HL])
+#define RSCAN0TMDF029HH (RSCAN0.TMDF029.UINT8[R_IO_HH])
+#define RSCAN0TMDF129 (RSCAN0.TMDF129.UINT32)
+#define RSCAN0TMDF129L (RSCAN0.TMDF129.UINT16[R_IO_L])
+#define RSCAN0TMDF129LL (RSCAN0.TMDF129.UINT8[R_IO_LL])
+#define RSCAN0TMDF129LH (RSCAN0.TMDF129.UINT8[R_IO_LH])
+#define RSCAN0TMDF129H (RSCAN0.TMDF129.UINT16[R_IO_H])
+#define RSCAN0TMDF129HL (RSCAN0.TMDF129.UINT8[R_IO_HL])
+#define RSCAN0TMDF129HH (RSCAN0.TMDF129.UINT8[R_IO_HH])
+#define RSCAN0TMID30 (RSCAN0.TMID30.UINT32)
+#define RSCAN0TMID30L (RSCAN0.TMID30.UINT16[R_IO_L])
+#define RSCAN0TMID30LL (RSCAN0.TMID30.UINT8[R_IO_LL])
+#define RSCAN0TMID30LH (RSCAN0.TMID30.UINT8[R_IO_LH])
+#define RSCAN0TMID30H (RSCAN0.TMID30.UINT16[R_IO_H])
+#define RSCAN0TMID30HL (RSCAN0.TMID30.UINT8[R_IO_HL])
+#define RSCAN0TMID30HH (RSCAN0.TMID30.UINT8[R_IO_HH])
+#define RSCAN0TMPTR30 (RSCAN0.TMPTR30.UINT32)
+#define RSCAN0TMPTR30L (RSCAN0.TMPTR30.UINT16[R_IO_L])
+#define RSCAN0TMPTR30LL (RSCAN0.TMPTR30.UINT8[R_IO_LL])
+#define RSCAN0TMPTR30LH (RSCAN0.TMPTR30.UINT8[R_IO_LH])
+#define RSCAN0TMPTR30H (RSCAN0.TMPTR30.UINT16[R_IO_H])
+#define RSCAN0TMPTR30HL (RSCAN0.TMPTR30.UINT8[R_IO_HL])
+#define RSCAN0TMPTR30HH (RSCAN0.TMPTR30.UINT8[R_IO_HH])
+#define RSCAN0TMDF030 (RSCAN0.TMDF030.UINT32)
+#define RSCAN0TMDF030L (RSCAN0.TMDF030.UINT16[R_IO_L])
+#define RSCAN0TMDF030LL (RSCAN0.TMDF030.UINT8[R_IO_LL])
+#define RSCAN0TMDF030LH (RSCAN0.TMDF030.UINT8[R_IO_LH])
+#define RSCAN0TMDF030H (RSCAN0.TMDF030.UINT16[R_IO_H])
+#define RSCAN0TMDF030HL (RSCAN0.TMDF030.UINT8[R_IO_HL])
+#define RSCAN0TMDF030HH (RSCAN0.TMDF030.UINT8[R_IO_HH])
+#define RSCAN0TMDF130 (RSCAN0.TMDF130.UINT32)
+#define RSCAN0TMDF130L (RSCAN0.TMDF130.UINT16[R_IO_L])
+#define RSCAN0TMDF130LL (RSCAN0.TMDF130.UINT8[R_IO_LL])
+#define RSCAN0TMDF130LH (RSCAN0.TMDF130.UINT8[R_IO_LH])
+#define RSCAN0TMDF130H (RSCAN0.TMDF130.UINT16[R_IO_H])
+#define RSCAN0TMDF130HL (RSCAN0.TMDF130.UINT8[R_IO_HL])
+#define RSCAN0TMDF130HH (RSCAN0.TMDF130.UINT8[R_IO_HH])
+#define RSCAN0TMID31 (RSCAN0.TMID31.UINT32)
+#define RSCAN0TMID31L (RSCAN0.TMID31.UINT16[R_IO_L])
+#define RSCAN0TMID31LL (RSCAN0.TMID31.UINT8[R_IO_LL])
+#define RSCAN0TMID31LH (RSCAN0.TMID31.UINT8[R_IO_LH])
+#define RSCAN0TMID31H (RSCAN0.TMID31.UINT16[R_IO_H])
+#define RSCAN0TMID31HL (RSCAN0.TMID31.UINT8[R_IO_HL])
+#define RSCAN0TMID31HH (RSCAN0.TMID31.UINT8[R_IO_HH])
+#define RSCAN0TMPTR31 (RSCAN0.TMPTR31.UINT32)
+#define RSCAN0TMPTR31L (RSCAN0.TMPTR31.UINT16[R_IO_L])
+#define RSCAN0TMPTR31LL (RSCAN0.TMPTR31.UINT8[R_IO_LL])
+#define RSCAN0TMPTR31LH (RSCAN0.TMPTR31.UINT8[R_IO_LH])
+#define RSCAN0TMPTR31H (RSCAN0.TMPTR31.UINT16[R_IO_H])
+#define RSCAN0TMPTR31HL (RSCAN0.TMPTR31.UINT8[R_IO_HL])
+#define RSCAN0TMPTR31HH (RSCAN0.TMPTR31.UINT8[R_IO_HH])
+#define RSCAN0TMDF031 (RSCAN0.TMDF031.UINT32)
+#define RSCAN0TMDF031L (RSCAN0.TMDF031.UINT16[R_IO_L])
+#define RSCAN0TMDF031LL (RSCAN0.TMDF031.UINT8[R_IO_LL])
+#define RSCAN0TMDF031LH (RSCAN0.TMDF031.UINT8[R_IO_LH])
+#define RSCAN0TMDF031H (RSCAN0.TMDF031.UINT16[R_IO_H])
+#define RSCAN0TMDF031HL (RSCAN0.TMDF031.UINT8[R_IO_HL])
+#define RSCAN0TMDF031HH (RSCAN0.TMDF031.UINT8[R_IO_HH])
+#define RSCAN0TMDF131 (RSCAN0.TMDF131.UINT32)
+#define RSCAN0TMDF131L (RSCAN0.TMDF131.UINT16[R_IO_L])
+#define RSCAN0TMDF131LL (RSCAN0.TMDF131.UINT8[R_IO_LL])
+#define RSCAN0TMDF131LH (RSCAN0.TMDF131.UINT8[R_IO_LH])
+#define RSCAN0TMDF131H (RSCAN0.TMDF131.UINT16[R_IO_H])
+#define RSCAN0TMDF131HL (RSCAN0.TMDF131.UINT8[R_IO_HL])
+#define RSCAN0TMDF131HH (RSCAN0.TMDF131.UINT8[R_IO_HH])
+#define RSCAN0TMID32 (RSCAN0.TMID32.UINT32)
+#define RSCAN0TMID32L (RSCAN0.TMID32.UINT16[R_IO_L])
+#define RSCAN0TMID32LL (RSCAN0.TMID32.UINT8[R_IO_LL])
+#define RSCAN0TMID32LH (RSCAN0.TMID32.UINT8[R_IO_LH])
+#define RSCAN0TMID32H (RSCAN0.TMID32.UINT16[R_IO_H])
+#define RSCAN0TMID32HL (RSCAN0.TMID32.UINT8[R_IO_HL])
+#define RSCAN0TMID32HH (RSCAN0.TMID32.UINT8[R_IO_HH])
+#define RSCAN0TMPTR32 (RSCAN0.TMPTR32.UINT32)
+#define RSCAN0TMPTR32L (RSCAN0.TMPTR32.UINT16[R_IO_L])
+#define RSCAN0TMPTR32LL (RSCAN0.TMPTR32.UINT8[R_IO_LL])
+#define RSCAN0TMPTR32LH (RSCAN0.TMPTR32.UINT8[R_IO_LH])
+#define RSCAN0TMPTR32H (RSCAN0.TMPTR32.UINT16[R_IO_H])
+#define RSCAN0TMPTR32HL (RSCAN0.TMPTR32.UINT8[R_IO_HL])
+#define RSCAN0TMPTR32HH (RSCAN0.TMPTR32.UINT8[R_IO_HH])
+#define RSCAN0TMDF032 (RSCAN0.TMDF032.UINT32)
+#define RSCAN0TMDF032L (RSCAN0.TMDF032.UINT16[R_IO_L])
+#define RSCAN0TMDF032LL (RSCAN0.TMDF032.UINT8[R_IO_LL])
+#define RSCAN0TMDF032LH (RSCAN0.TMDF032.UINT8[R_IO_LH])
+#define RSCAN0TMDF032H (RSCAN0.TMDF032.UINT16[R_IO_H])
+#define RSCAN0TMDF032HL (RSCAN0.TMDF032.UINT8[R_IO_HL])
+#define RSCAN0TMDF032HH (RSCAN0.TMDF032.UINT8[R_IO_HH])
+#define RSCAN0TMDF132 (RSCAN0.TMDF132.UINT32)
+#define RSCAN0TMDF132L (RSCAN0.TMDF132.UINT16[R_IO_L])
+#define RSCAN0TMDF132LL (RSCAN0.TMDF132.UINT8[R_IO_LL])
+#define RSCAN0TMDF132LH (RSCAN0.TMDF132.UINT8[R_IO_LH])
+#define RSCAN0TMDF132H (RSCAN0.TMDF132.UINT16[R_IO_H])
+#define RSCAN0TMDF132HL (RSCAN0.TMDF132.UINT8[R_IO_HL])
+#define RSCAN0TMDF132HH (RSCAN0.TMDF132.UINT8[R_IO_HH])
+#define RSCAN0TMID33 (RSCAN0.TMID33.UINT32)
+#define RSCAN0TMID33L (RSCAN0.TMID33.UINT16[R_IO_L])
+#define RSCAN0TMID33LL (RSCAN0.TMID33.UINT8[R_IO_LL])
+#define RSCAN0TMID33LH (RSCAN0.TMID33.UINT8[R_IO_LH])
+#define RSCAN0TMID33H (RSCAN0.TMID33.UINT16[R_IO_H])
+#define RSCAN0TMID33HL (RSCAN0.TMID33.UINT8[R_IO_HL])
+#define RSCAN0TMID33HH (RSCAN0.TMID33.UINT8[R_IO_HH])
+#define RSCAN0TMPTR33 (RSCAN0.TMPTR33.UINT32)
+#define RSCAN0TMPTR33L (RSCAN0.TMPTR33.UINT16[R_IO_L])
+#define RSCAN0TMPTR33LL (RSCAN0.TMPTR33.UINT8[R_IO_LL])
+#define RSCAN0TMPTR33LH (RSCAN0.TMPTR33.UINT8[R_IO_LH])
+#define RSCAN0TMPTR33H (RSCAN0.TMPTR33.UINT16[R_IO_H])
+#define RSCAN0TMPTR33HL (RSCAN0.TMPTR33.UINT8[R_IO_HL])
+#define RSCAN0TMPTR33HH (RSCAN0.TMPTR33.UINT8[R_IO_HH])
+#define RSCAN0TMDF033 (RSCAN0.TMDF033.UINT32)
+#define RSCAN0TMDF033L (RSCAN0.TMDF033.UINT16[R_IO_L])
+#define RSCAN0TMDF033LL (RSCAN0.TMDF033.UINT8[R_IO_LL])
+#define RSCAN0TMDF033LH (RSCAN0.TMDF033.UINT8[R_IO_LH])
+#define RSCAN0TMDF033H (RSCAN0.TMDF033.UINT16[R_IO_H])
+#define RSCAN0TMDF033HL (RSCAN0.TMDF033.UINT8[R_IO_HL])
+#define RSCAN0TMDF033HH (RSCAN0.TMDF033.UINT8[R_IO_HH])
+#define RSCAN0TMDF133 (RSCAN0.TMDF133.UINT32)
+#define RSCAN0TMDF133L (RSCAN0.TMDF133.UINT16[R_IO_L])
+#define RSCAN0TMDF133LL (RSCAN0.TMDF133.UINT8[R_IO_LL])
+#define RSCAN0TMDF133LH (RSCAN0.TMDF133.UINT8[R_IO_LH])
+#define RSCAN0TMDF133H (RSCAN0.TMDF133.UINT16[R_IO_H])
+#define RSCAN0TMDF133HL (RSCAN0.TMDF133.UINT8[R_IO_HL])
+#define RSCAN0TMDF133HH (RSCAN0.TMDF133.UINT8[R_IO_HH])
+#define RSCAN0TMID34 (RSCAN0.TMID34.UINT32)
+#define RSCAN0TMID34L (RSCAN0.TMID34.UINT16[R_IO_L])
+#define RSCAN0TMID34LL (RSCAN0.TMID34.UINT8[R_IO_LL])
+#define RSCAN0TMID34LH (RSCAN0.TMID34.UINT8[R_IO_LH])
+#define RSCAN0TMID34H (RSCAN0.TMID34.UINT16[R_IO_H])
+#define RSCAN0TMID34HL (RSCAN0.TMID34.UINT8[R_IO_HL])
+#define RSCAN0TMID34HH (RSCAN0.TMID34.UINT8[R_IO_HH])
+#define RSCAN0TMPTR34 (RSCAN0.TMPTR34.UINT32)
+#define RSCAN0TMPTR34L (RSCAN0.TMPTR34.UINT16[R_IO_L])
+#define RSCAN0TMPTR34LL (RSCAN0.TMPTR34.UINT8[R_IO_LL])
+#define RSCAN0TMPTR34LH (RSCAN0.TMPTR34.UINT8[R_IO_LH])
+#define RSCAN0TMPTR34H (RSCAN0.TMPTR34.UINT16[R_IO_H])
+#define RSCAN0TMPTR34HL (RSCAN0.TMPTR34.UINT8[R_IO_HL])
+#define RSCAN0TMPTR34HH (RSCAN0.TMPTR34.UINT8[R_IO_HH])
+#define RSCAN0TMDF034 (RSCAN0.TMDF034.UINT32)
+#define RSCAN0TMDF034L (RSCAN0.TMDF034.UINT16[R_IO_L])
+#define RSCAN0TMDF034LL (RSCAN0.TMDF034.UINT8[R_IO_LL])
+#define RSCAN0TMDF034LH (RSCAN0.TMDF034.UINT8[R_IO_LH])
+#define RSCAN0TMDF034H (RSCAN0.TMDF034.UINT16[R_IO_H])
+#define RSCAN0TMDF034HL (RSCAN0.TMDF034.UINT8[R_IO_HL])
+#define RSCAN0TMDF034HH (RSCAN0.TMDF034.UINT8[R_IO_HH])
+#define RSCAN0TMDF134 (RSCAN0.TMDF134.UINT32)
+#define RSCAN0TMDF134L (RSCAN0.TMDF134.UINT16[R_IO_L])
+#define RSCAN0TMDF134LL (RSCAN0.TMDF134.UINT8[R_IO_LL])
+#define RSCAN0TMDF134LH (RSCAN0.TMDF134.UINT8[R_IO_LH])
+#define RSCAN0TMDF134H (RSCAN0.TMDF134.UINT16[R_IO_H])
+#define RSCAN0TMDF134HL (RSCAN0.TMDF134.UINT8[R_IO_HL])
+#define RSCAN0TMDF134HH (RSCAN0.TMDF134.UINT8[R_IO_HH])
+#define RSCAN0TMID35 (RSCAN0.TMID35.UINT32)
+#define RSCAN0TMID35L (RSCAN0.TMID35.UINT16[R_IO_L])
+#define RSCAN0TMID35LL (RSCAN0.TMID35.UINT8[R_IO_LL])
+#define RSCAN0TMID35LH (RSCAN0.TMID35.UINT8[R_IO_LH])
+#define RSCAN0TMID35H (RSCAN0.TMID35.UINT16[R_IO_H])
+#define RSCAN0TMID35HL (RSCAN0.TMID35.UINT8[R_IO_HL])
+#define RSCAN0TMID35HH (RSCAN0.TMID35.UINT8[R_IO_HH])
+#define RSCAN0TMPTR35 (RSCAN0.TMPTR35.UINT32)
+#define RSCAN0TMPTR35L (RSCAN0.TMPTR35.UINT16[R_IO_L])
+#define RSCAN0TMPTR35LL (RSCAN0.TMPTR35.UINT8[R_IO_LL])
+#define RSCAN0TMPTR35LH (RSCAN0.TMPTR35.UINT8[R_IO_LH])
+#define RSCAN0TMPTR35H (RSCAN0.TMPTR35.UINT16[R_IO_H])
+#define RSCAN0TMPTR35HL (RSCAN0.TMPTR35.UINT8[R_IO_HL])
+#define RSCAN0TMPTR35HH (RSCAN0.TMPTR35.UINT8[R_IO_HH])
+#define RSCAN0TMDF035 (RSCAN0.TMDF035.UINT32)
+#define RSCAN0TMDF035L (RSCAN0.TMDF035.UINT16[R_IO_L])
+#define RSCAN0TMDF035LL (RSCAN0.TMDF035.UINT8[R_IO_LL])
+#define RSCAN0TMDF035LH (RSCAN0.TMDF035.UINT8[R_IO_LH])
+#define RSCAN0TMDF035H (RSCAN0.TMDF035.UINT16[R_IO_H])
+#define RSCAN0TMDF035HL (RSCAN0.TMDF035.UINT8[R_IO_HL])
+#define RSCAN0TMDF035HH (RSCAN0.TMDF035.UINT8[R_IO_HH])
+#define RSCAN0TMDF135 (RSCAN0.TMDF135.UINT32)
+#define RSCAN0TMDF135L (RSCAN0.TMDF135.UINT16[R_IO_L])
+#define RSCAN0TMDF135LL (RSCAN0.TMDF135.UINT8[R_IO_LL])
+#define RSCAN0TMDF135LH (RSCAN0.TMDF135.UINT8[R_IO_LH])
+#define RSCAN0TMDF135H (RSCAN0.TMDF135.UINT16[R_IO_H])
+#define RSCAN0TMDF135HL (RSCAN0.TMDF135.UINT8[R_IO_HL])
+#define RSCAN0TMDF135HH (RSCAN0.TMDF135.UINT8[R_IO_HH])
+#define RSCAN0TMID36 (RSCAN0.TMID36.UINT32)
+#define RSCAN0TMID36L (RSCAN0.TMID36.UINT16[R_IO_L])
+#define RSCAN0TMID36LL (RSCAN0.TMID36.UINT8[R_IO_LL])
+#define RSCAN0TMID36LH (RSCAN0.TMID36.UINT8[R_IO_LH])
+#define RSCAN0TMID36H (RSCAN0.TMID36.UINT16[R_IO_H])
+#define RSCAN0TMID36HL (RSCAN0.TMID36.UINT8[R_IO_HL])
+#define RSCAN0TMID36HH (RSCAN0.TMID36.UINT8[R_IO_HH])
+#define RSCAN0TMPTR36 (RSCAN0.TMPTR36.UINT32)
+#define RSCAN0TMPTR36L (RSCAN0.TMPTR36.UINT16[R_IO_L])
+#define RSCAN0TMPTR36LL (RSCAN0.TMPTR36.UINT8[R_IO_LL])
+#define RSCAN0TMPTR36LH (RSCAN0.TMPTR36.UINT8[R_IO_LH])
+#define RSCAN0TMPTR36H (RSCAN0.TMPTR36.UINT16[R_IO_H])
+#define RSCAN0TMPTR36HL (RSCAN0.TMPTR36.UINT8[R_IO_HL])
+#define RSCAN0TMPTR36HH (RSCAN0.TMPTR36.UINT8[R_IO_HH])
+#define RSCAN0TMDF036 (RSCAN0.TMDF036.UINT32)
+#define RSCAN0TMDF036L (RSCAN0.TMDF036.UINT16[R_IO_L])
+#define RSCAN0TMDF036LL (RSCAN0.TMDF036.UINT8[R_IO_LL])
+#define RSCAN0TMDF036LH (RSCAN0.TMDF036.UINT8[R_IO_LH])
+#define RSCAN0TMDF036H (RSCAN0.TMDF036.UINT16[R_IO_H])
+#define RSCAN0TMDF036HL (RSCAN0.TMDF036.UINT8[R_IO_HL])
+#define RSCAN0TMDF036HH (RSCAN0.TMDF036.UINT8[R_IO_HH])
+#define RSCAN0TMDF136 (RSCAN0.TMDF136.UINT32)
+#define RSCAN0TMDF136L (RSCAN0.TMDF136.UINT16[R_IO_L])
+#define RSCAN0TMDF136LL (RSCAN0.TMDF136.UINT8[R_IO_LL])
+#define RSCAN0TMDF136LH (RSCAN0.TMDF136.UINT8[R_IO_LH])
+#define RSCAN0TMDF136H (RSCAN0.TMDF136.UINT16[R_IO_H])
+#define RSCAN0TMDF136HL (RSCAN0.TMDF136.UINT8[R_IO_HL])
+#define RSCAN0TMDF136HH (RSCAN0.TMDF136.UINT8[R_IO_HH])
+#define RSCAN0TMID37 (RSCAN0.TMID37.UINT32)
+#define RSCAN0TMID37L (RSCAN0.TMID37.UINT16[R_IO_L])
+#define RSCAN0TMID37LL (RSCAN0.TMID37.UINT8[R_IO_LL])
+#define RSCAN0TMID37LH (RSCAN0.TMID37.UINT8[R_IO_LH])
+#define RSCAN0TMID37H (RSCAN0.TMID37.UINT16[R_IO_H])
+#define RSCAN0TMID37HL (RSCAN0.TMID37.UINT8[R_IO_HL])
+#define RSCAN0TMID37HH (RSCAN0.TMID37.UINT8[R_IO_HH])
+#define RSCAN0TMPTR37 (RSCAN0.TMPTR37.UINT32)
+#define RSCAN0TMPTR37L (RSCAN0.TMPTR37.UINT16[R_IO_L])
+#define RSCAN0TMPTR37LL (RSCAN0.TMPTR37.UINT8[R_IO_LL])
+#define RSCAN0TMPTR37LH (RSCAN0.TMPTR37.UINT8[R_IO_LH])
+#define RSCAN0TMPTR37H (RSCAN0.TMPTR37.UINT16[R_IO_H])
+#define RSCAN0TMPTR37HL (RSCAN0.TMPTR37.UINT8[R_IO_HL])
+#define RSCAN0TMPTR37HH (RSCAN0.TMPTR37.UINT8[R_IO_HH])
+#define RSCAN0TMDF037 (RSCAN0.TMDF037.UINT32)
+#define RSCAN0TMDF037L (RSCAN0.TMDF037.UINT16[R_IO_L])
+#define RSCAN0TMDF037LL (RSCAN0.TMDF037.UINT8[R_IO_LL])
+#define RSCAN0TMDF037LH (RSCAN0.TMDF037.UINT8[R_IO_LH])
+#define RSCAN0TMDF037H (RSCAN0.TMDF037.UINT16[R_IO_H])
+#define RSCAN0TMDF037HL (RSCAN0.TMDF037.UINT8[R_IO_HL])
+#define RSCAN0TMDF037HH (RSCAN0.TMDF037.UINT8[R_IO_HH])
+#define RSCAN0TMDF137 (RSCAN0.TMDF137.UINT32)
+#define RSCAN0TMDF137L (RSCAN0.TMDF137.UINT16[R_IO_L])
+#define RSCAN0TMDF137LL (RSCAN0.TMDF137.UINT8[R_IO_LL])
+#define RSCAN0TMDF137LH (RSCAN0.TMDF137.UINT8[R_IO_LH])
+#define RSCAN0TMDF137H (RSCAN0.TMDF137.UINT16[R_IO_H])
+#define RSCAN0TMDF137HL (RSCAN0.TMDF137.UINT8[R_IO_HL])
+#define RSCAN0TMDF137HH (RSCAN0.TMDF137.UINT8[R_IO_HH])
+#define RSCAN0TMID38 (RSCAN0.TMID38.UINT32)
+#define RSCAN0TMID38L (RSCAN0.TMID38.UINT16[R_IO_L])
+#define RSCAN0TMID38LL (RSCAN0.TMID38.UINT8[R_IO_LL])
+#define RSCAN0TMID38LH (RSCAN0.TMID38.UINT8[R_IO_LH])
+#define RSCAN0TMID38H (RSCAN0.TMID38.UINT16[R_IO_H])
+#define RSCAN0TMID38HL (RSCAN0.TMID38.UINT8[R_IO_HL])
+#define RSCAN0TMID38HH (RSCAN0.TMID38.UINT8[R_IO_HH])
+#define RSCAN0TMPTR38 (RSCAN0.TMPTR38.UINT32)
+#define RSCAN0TMPTR38L (RSCAN0.TMPTR38.UINT16[R_IO_L])
+#define RSCAN0TMPTR38LL (RSCAN0.TMPTR38.UINT8[R_IO_LL])
+#define RSCAN0TMPTR38LH (RSCAN0.TMPTR38.UINT8[R_IO_LH])
+#define RSCAN0TMPTR38H (RSCAN0.TMPTR38.UINT16[R_IO_H])
+#define RSCAN0TMPTR38HL (RSCAN0.TMPTR38.UINT8[R_IO_HL])
+#define RSCAN0TMPTR38HH (RSCAN0.TMPTR38.UINT8[R_IO_HH])
+#define RSCAN0TMDF038 (RSCAN0.TMDF038.UINT32)
+#define RSCAN0TMDF038L (RSCAN0.TMDF038.UINT16[R_IO_L])
+#define RSCAN0TMDF038LL (RSCAN0.TMDF038.UINT8[R_IO_LL])
+#define RSCAN0TMDF038LH (RSCAN0.TMDF038.UINT8[R_IO_LH])
+#define RSCAN0TMDF038H (RSCAN0.TMDF038.UINT16[R_IO_H])
+#define RSCAN0TMDF038HL (RSCAN0.TMDF038.UINT8[R_IO_HL])
+#define RSCAN0TMDF038HH (RSCAN0.TMDF038.UINT8[R_IO_HH])
+#define RSCAN0TMDF138 (RSCAN0.TMDF138.UINT32)
+#define RSCAN0TMDF138L (RSCAN0.TMDF138.UINT16[R_IO_L])
+#define RSCAN0TMDF138LL (RSCAN0.TMDF138.UINT8[R_IO_LL])
+#define RSCAN0TMDF138LH (RSCAN0.TMDF138.UINT8[R_IO_LH])
+#define RSCAN0TMDF138H (RSCAN0.TMDF138.UINT16[R_IO_H])
+#define RSCAN0TMDF138HL (RSCAN0.TMDF138.UINT8[R_IO_HL])
+#define RSCAN0TMDF138HH (RSCAN0.TMDF138.UINT8[R_IO_HH])
+#define RSCAN0TMID39 (RSCAN0.TMID39.UINT32)
+#define RSCAN0TMID39L (RSCAN0.TMID39.UINT16[R_IO_L])
+#define RSCAN0TMID39LL (RSCAN0.TMID39.UINT8[R_IO_LL])
+#define RSCAN0TMID39LH (RSCAN0.TMID39.UINT8[R_IO_LH])
+#define RSCAN0TMID39H (RSCAN0.TMID39.UINT16[R_IO_H])
+#define RSCAN0TMID39HL (RSCAN0.TMID39.UINT8[R_IO_HL])
+#define RSCAN0TMID39HH (RSCAN0.TMID39.UINT8[R_IO_HH])
+#define RSCAN0TMPTR39 (RSCAN0.TMPTR39.UINT32)
+#define RSCAN0TMPTR39L (RSCAN0.TMPTR39.UINT16[R_IO_L])
+#define RSCAN0TMPTR39LL (RSCAN0.TMPTR39.UINT8[R_IO_LL])
+#define RSCAN0TMPTR39LH (RSCAN0.TMPTR39.UINT8[R_IO_LH])
+#define RSCAN0TMPTR39H (RSCAN0.TMPTR39.UINT16[R_IO_H])
+#define RSCAN0TMPTR39HL (RSCAN0.TMPTR39.UINT8[R_IO_HL])
+#define RSCAN0TMPTR39HH (RSCAN0.TMPTR39.UINT8[R_IO_HH])
+#define RSCAN0TMDF039 (RSCAN0.TMDF039.UINT32)
+#define RSCAN0TMDF039L (RSCAN0.TMDF039.UINT16[R_IO_L])
+#define RSCAN0TMDF039LL (RSCAN0.TMDF039.UINT8[R_IO_LL])
+#define RSCAN0TMDF039LH (RSCAN0.TMDF039.UINT8[R_IO_LH])
+#define RSCAN0TMDF039H (RSCAN0.TMDF039.UINT16[R_IO_H])
+#define RSCAN0TMDF039HL (RSCAN0.TMDF039.UINT8[R_IO_HL])
+#define RSCAN0TMDF039HH (RSCAN0.TMDF039.UINT8[R_IO_HH])
+#define RSCAN0TMDF139 (RSCAN0.TMDF139.UINT32)
+#define RSCAN0TMDF139L (RSCAN0.TMDF139.UINT16[R_IO_L])
+#define RSCAN0TMDF139LL (RSCAN0.TMDF139.UINT8[R_IO_LL])
+#define RSCAN0TMDF139LH (RSCAN0.TMDF139.UINT8[R_IO_LH])
+#define RSCAN0TMDF139H (RSCAN0.TMDF139.UINT16[R_IO_H])
+#define RSCAN0TMDF139HL (RSCAN0.TMDF139.UINT8[R_IO_HL])
+#define RSCAN0TMDF139HH (RSCAN0.TMDF139.UINT8[R_IO_HH])
+#define RSCAN0TMID40 (RSCAN0.TMID40.UINT32)
+#define RSCAN0TMID40L (RSCAN0.TMID40.UINT16[R_IO_L])
+#define RSCAN0TMID40LL (RSCAN0.TMID40.UINT8[R_IO_LL])
+#define RSCAN0TMID40LH (RSCAN0.TMID40.UINT8[R_IO_LH])
+#define RSCAN0TMID40H (RSCAN0.TMID40.UINT16[R_IO_H])
+#define RSCAN0TMID40HL (RSCAN0.TMID40.UINT8[R_IO_HL])
+#define RSCAN0TMID40HH (RSCAN0.TMID40.UINT8[R_IO_HH])
+#define RSCAN0TMPTR40 (RSCAN0.TMPTR40.UINT32)
+#define RSCAN0TMPTR40L (RSCAN0.TMPTR40.UINT16[R_IO_L])
+#define RSCAN0TMPTR40LL (RSCAN0.TMPTR40.UINT8[R_IO_LL])
+#define RSCAN0TMPTR40LH (RSCAN0.TMPTR40.UINT8[R_IO_LH])
+#define RSCAN0TMPTR40H (RSCAN0.TMPTR40.UINT16[R_IO_H])
+#define RSCAN0TMPTR40HL (RSCAN0.TMPTR40.UINT8[R_IO_HL])
+#define RSCAN0TMPTR40HH (RSCAN0.TMPTR40.UINT8[R_IO_HH])
+#define RSCAN0TMDF040 (RSCAN0.TMDF040.UINT32)
+#define RSCAN0TMDF040L (RSCAN0.TMDF040.UINT16[R_IO_L])
+#define RSCAN0TMDF040LL (RSCAN0.TMDF040.UINT8[R_IO_LL])
+#define RSCAN0TMDF040LH (RSCAN0.TMDF040.UINT8[R_IO_LH])
+#define RSCAN0TMDF040H (RSCAN0.TMDF040.UINT16[R_IO_H])
+#define RSCAN0TMDF040HL (RSCAN0.TMDF040.UINT8[R_IO_HL])
+#define RSCAN0TMDF040HH (RSCAN0.TMDF040.UINT8[R_IO_HH])
+#define RSCAN0TMDF140 (RSCAN0.TMDF140.UINT32)
+#define RSCAN0TMDF140L (RSCAN0.TMDF140.UINT16[R_IO_L])
+#define RSCAN0TMDF140LL (RSCAN0.TMDF140.UINT8[R_IO_LL])
+#define RSCAN0TMDF140LH (RSCAN0.TMDF140.UINT8[R_IO_LH])
+#define RSCAN0TMDF140H (RSCAN0.TMDF140.UINT16[R_IO_H])
+#define RSCAN0TMDF140HL (RSCAN0.TMDF140.UINT8[R_IO_HL])
+#define RSCAN0TMDF140HH (RSCAN0.TMDF140.UINT8[R_IO_HH])
+#define RSCAN0TMID41 (RSCAN0.TMID41.UINT32)
+#define RSCAN0TMID41L (RSCAN0.TMID41.UINT16[R_IO_L])
+#define RSCAN0TMID41LL (RSCAN0.TMID41.UINT8[R_IO_LL])
+#define RSCAN0TMID41LH (RSCAN0.TMID41.UINT8[R_IO_LH])
+#define RSCAN0TMID41H (RSCAN0.TMID41.UINT16[R_IO_H])
+#define RSCAN0TMID41HL (RSCAN0.TMID41.UINT8[R_IO_HL])
+#define RSCAN0TMID41HH (RSCAN0.TMID41.UINT8[R_IO_HH])
+#define RSCAN0TMPTR41 (RSCAN0.TMPTR41.UINT32)
+#define RSCAN0TMPTR41L (RSCAN0.TMPTR41.UINT16[R_IO_L])
+#define RSCAN0TMPTR41LL (RSCAN0.TMPTR41.UINT8[R_IO_LL])
+#define RSCAN0TMPTR41LH (RSCAN0.TMPTR41.UINT8[R_IO_LH])
+#define RSCAN0TMPTR41H (RSCAN0.TMPTR41.UINT16[R_IO_H])
+#define RSCAN0TMPTR41HL (RSCAN0.TMPTR41.UINT8[R_IO_HL])
+#define RSCAN0TMPTR41HH (RSCAN0.TMPTR41.UINT8[R_IO_HH])
+#define RSCAN0TMDF041 (RSCAN0.TMDF041.UINT32)
+#define RSCAN0TMDF041L (RSCAN0.TMDF041.UINT16[R_IO_L])
+#define RSCAN0TMDF041LL (RSCAN0.TMDF041.UINT8[R_IO_LL])
+#define RSCAN0TMDF041LH (RSCAN0.TMDF041.UINT8[R_IO_LH])
+#define RSCAN0TMDF041H (RSCAN0.TMDF041.UINT16[R_IO_H])
+#define RSCAN0TMDF041HL (RSCAN0.TMDF041.UINT8[R_IO_HL])
+#define RSCAN0TMDF041HH (RSCAN0.TMDF041.UINT8[R_IO_HH])
+#define RSCAN0TMDF141 (RSCAN0.TMDF141.UINT32)
+#define RSCAN0TMDF141L (RSCAN0.TMDF141.UINT16[R_IO_L])
+#define RSCAN0TMDF141LL (RSCAN0.TMDF141.UINT8[R_IO_LL])
+#define RSCAN0TMDF141LH (RSCAN0.TMDF141.UINT8[R_IO_LH])
+#define RSCAN0TMDF141H (RSCAN0.TMDF141.UINT16[R_IO_H])
+#define RSCAN0TMDF141HL (RSCAN0.TMDF141.UINT8[R_IO_HL])
+#define RSCAN0TMDF141HH (RSCAN0.TMDF141.UINT8[R_IO_HH])
+#define RSCAN0TMID42 (RSCAN0.TMID42.UINT32)
+#define RSCAN0TMID42L (RSCAN0.TMID42.UINT16[R_IO_L])
+#define RSCAN0TMID42LL (RSCAN0.TMID42.UINT8[R_IO_LL])
+#define RSCAN0TMID42LH (RSCAN0.TMID42.UINT8[R_IO_LH])
+#define RSCAN0TMID42H (RSCAN0.TMID42.UINT16[R_IO_H])
+#define RSCAN0TMID42HL (RSCAN0.TMID42.UINT8[R_IO_HL])
+#define RSCAN0TMID42HH (RSCAN0.TMID42.UINT8[R_IO_HH])
+#define RSCAN0TMPTR42 (RSCAN0.TMPTR42.UINT32)
+#define RSCAN0TMPTR42L (RSCAN0.TMPTR42.UINT16[R_IO_L])
+#define RSCAN0TMPTR42LL (RSCAN0.TMPTR42.UINT8[R_IO_LL])
+#define RSCAN0TMPTR42LH (RSCAN0.TMPTR42.UINT8[R_IO_LH])
+#define RSCAN0TMPTR42H (RSCAN0.TMPTR42.UINT16[R_IO_H])
+#define RSCAN0TMPTR42HL (RSCAN0.TMPTR42.UINT8[R_IO_HL])
+#define RSCAN0TMPTR42HH (RSCAN0.TMPTR42.UINT8[R_IO_HH])
+#define RSCAN0TMDF042 (RSCAN0.TMDF042.UINT32)
+#define RSCAN0TMDF042L (RSCAN0.TMDF042.UINT16[R_IO_L])
+#define RSCAN0TMDF042LL (RSCAN0.TMDF042.UINT8[R_IO_LL])
+#define RSCAN0TMDF042LH (RSCAN0.TMDF042.UINT8[R_IO_LH])
+#define RSCAN0TMDF042H (RSCAN0.TMDF042.UINT16[R_IO_H])
+#define RSCAN0TMDF042HL (RSCAN0.TMDF042.UINT8[R_IO_HL])
+#define RSCAN0TMDF042HH (RSCAN0.TMDF042.UINT8[R_IO_HH])
+#define RSCAN0TMDF142 (RSCAN0.TMDF142.UINT32)
+#define RSCAN0TMDF142L (RSCAN0.TMDF142.UINT16[R_IO_L])
+#define RSCAN0TMDF142LL (RSCAN0.TMDF142.UINT8[R_IO_LL])
+#define RSCAN0TMDF142LH (RSCAN0.TMDF142.UINT8[R_IO_LH])
+#define RSCAN0TMDF142H (RSCAN0.TMDF142.UINT16[R_IO_H])
+#define RSCAN0TMDF142HL (RSCAN0.TMDF142.UINT8[R_IO_HL])
+#define RSCAN0TMDF142HH (RSCAN0.TMDF142.UINT8[R_IO_HH])
+#define RSCAN0TMID43 (RSCAN0.TMID43.UINT32)
+#define RSCAN0TMID43L (RSCAN0.TMID43.UINT16[R_IO_L])
+#define RSCAN0TMID43LL (RSCAN0.TMID43.UINT8[R_IO_LL])
+#define RSCAN0TMID43LH (RSCAN0.TMID43.UINT8[R_IO_LH])
+#define RSCAN0TMID43H (RSCAN0.TMID43.UINT16[R_IO_H])
+#define RSCAN0TMID43HL (RSCAN0.TMID43.UINT8[R_IO_HL])
+#define RSCAN0TMID43HH (RSCAN0.TMID43.UINT8[R_IO_HH])
+#define RSCAN0TMPTR43 (RSCAN0.TMPTR43.UINT32)
+#define RSCAN0TMPTR43L (RSCAN0.TMPTR43.UINT16[R_IO_L])
+#define RSCAN0TMPTR43LL (RSCAN0.TMPTR43.UINT8[R_IO_LL])
+#define RSCAN0TMPTR43LH (RSCAN0.TMPTR43.UINT8[R_IO_LH])
+#define RSCAN0TMPTR43H (RSCAN0.TMPTR43.UINT16[R_IO_H])
+#define RSCAN0TMPTR43HL (RSCAN0.TMPTR43.UINT8[R_IO_HL])
+#define RSCAN0TMPTR43HH (RSCAN0.TMPTR43.UINT8[R_IO_HH])
+#define RSCAN0TMDF043 (RSCAN0.TMDF043.UINT32)
+#define RSCAN0TMDF043L (RSCAN0.TMDF043.UINT16[R_IO_L])
+#define RSCAN0TMDF043LL (RSCAN0.TMDF043.UINT8[R_IO_LL])
+#define RSCAN0TMDF043LH (RSCAN0.TMDF043.UINT8[R_IO_LH])
+#define RSCAN0TMDF043H (RSCAN0.TMDF043.UINT16[R_IO_H])
+#define RSCAN0TMDF043HL (RSCAN0.TMDF043.UINT8[R_IO_HL])
+#define RSCAN0TMDF043HH (RSCAN0.TMDF043.UINT8[R_IO_HH])
+#define RSCAN0TMDF143 (RSCAN0.TMDF143.UINT32)
+#define RSCAN0TMDF143L (RSCAN0.TMDF143.UINT16[R_IO_L])
+#define RSCAN0TMDF143LL (RSCAN0.TMDF143.UINT8[R_IO_LL])
+#define RSCAN0TMDF143LH (RSCAN0.TMDF143.UINT8[R_IO_LH])
+#define RSCAN0TMDF143H (RSCAN0.TMDF143.UINT16[R_IO_H])
+#define RSCAN0TMDF143HL (RSCAN0.TMDF143.UINT8[R_IO_HL])
+#define RSCAN0TMDF143HH (RSCAN0.TMDF143.UINT8[R_IO_HH])
+#define RSCAN0TMID44 (RSCAN0.TMID44.UINT32)
+#define RSCAN0TMID44L (RSCAN0.TMID44.UINT16[R_IO_L])
+#define RSCAN0TMID44LL (RSCAN0.TMID44.UINT8[R_IO_LL])
+#define RSCAN0TMID44LH (RSCAN0.TMID44.UINT8[R_IO_LH])
+#define RSCAN0TMID44H (RSCAN0.TMID44.UINT16[R_IO_H])
+#define RSCAN0TMID44HL (RSCAN0.TMID44.UINT8[R_IO_HL])
+#define RSCAN0TMID44HH (RSCAN0.TMID44.UINT8[R_IO_HH])
+#define RSCAN0TMPTR44 (RSCAN0.TMPTR44.UINT32)
+#define RSCAN0TMPTR44L (RSCAN0.TMPTR44.UINT16[R_IO_L])
+#define RSCAN0TMPTR44LL (RSCAN0.TMPTR44.UINT8[R_IO_LL])
+#define RSCAN0TMPTR44LH (RSCAN0.TMPTR44.UINT8[R_IO_LH])
+#define RSCAN0TMPTR44H (RSCAN0.TMPTR44.UINT16[R_IO_H])
+#define RSCAN0TMPTR44HL (RSCAN0.TMPTR44.UINT8[R_IO_HL])
+#define RSCAN0TMPTR44HH (RSCAN0.TMPTR44.UINT8[R_IO_HH])
+#define RSCAN0TMDF044 (RSCAN0.TMDF044.UINT32)
+#define RSCAN0TMDF044L (RSCAN0.TMDF044.UINT16[R_IO_L])
+#define RSCAN0TMDF044LL (RSCAN0.TMDF044.UINT8[R_IO_LL])
+#define RSCAN0TMDF044LH (RSCAN0.TMDF044.UINT8[R_IO_LH])
+#define RSCAN0TMDF044H (RSCAN0.TMDF044.UINT16[R_IO_H])
+#define RSCAN0TMDF044HL (RSCAN0.TMDF044.UINT8[R_IO_HL])
+#define RSCAN0TMDF044HH (RSCAN0.TMDF044.UINT8[R_IO_HH])
+#define RSCAN0TMDF144 (RSCAN0.TMDF144.UINT32)
+#define RSCAN0TMDF144L (RSCAN0.TMDF144.UINT16[R_IO_L])
+#define RSCAN0TMDF144LL (RSCAN0.TMDF144.UINT8[R_IO_LL])
+#define RSCAN0TMDF144LH (RSCAN0.TMDF144.UINT8[R_IO_LH])
+#define RSCAN0TMDF144H (RSCAN0.TMDF144.UINT16[R_IO_H])
+#define RSCAN0TMDF144HL (RSCAN0.TMDF144.UINT8[R_IO_HL])
+#define RSCAN0TMDF144HH (RSCAN0.TMDF144.UINT8[R_IO_HH])
+#define RSCAN0TMID45 (RSCAN0.TMID45.UINT32)
+#define RSCAN0TMID45L (RSCAN0.TMID45.UINT16[R_IO_L])
+#define RSCAN0TMID45LL (RSCAN0.TMID45.UINT8[R_IO_LL])
+#define RSCAN0TMID45LH (RSCAN0.TMID45.UINT8[R_IO_LH])
+#define RSCAN0TMID45H (RSCAN0.TMID45.UINT16[R_IO_H])
+#define RSCAN0TMID45HL (RSCAN0.TMID45.UINT8[R_IO_HL])
+#define RSCAN0TMID45HH (RSCAN0.TMID45.UINT8[R_IO_HH])
+#define RSCAN0TMPTR45 (RSCAN0.TMPTR45.UINT32)
+#define RSCAN0TMPTR45L (RSCAN0.TMPTR45.UINT16[R_IO_L])
+#define RSCAN0TMPTR45LL (RSCAN0.TMPTR45.UINT8[R_IO_LL])
+#define RSCAN0TMPTR45LH (RSCAN0.TMPTR45.UINT8[R_IO_LH])
+#define RSCAN0TMPTR45H (RSCAN0.TMPTR45.UINT16[R_IO_H])
+#define RSCAN0TMPTR45HL (RSCAN0.TMPTR45.UINT8[R_IO_HL])
+#define RSCAN0TMPTR45HH (RSCAN0.TMPTR45.UINT8[R_IO_HH])
+#define RSCAN0TMDF045 (RSCAN0.TMDF045.UINT32)
+#define RSCAN0TMDF045L (RSCAN0.TMDF045.UINT16[R_IO_L])
+#define RSCAN0TMDF045LL (RSCAN0.TMDF045.UINT8[R_IO_LL])
+#define RSCAN0TMDF045LH (RSCAN0.TMDF045.UINT8[R_IO_LH])
+#define RSCAN0TMDF045H (RSCAN0.TMDF045.UINT16[R_IO_H])
+#define RSCAN0TMDF045HL (RSCAN0.TMDF045.UINT8[R_IO_HL])
+#define RSCAN0TMDF045HH (RSCAN0.TMDF045.UINT8[R_IO_HH])
+#define RSCAN0TMDF145 (RSCAN0.TMDF145.UINT32)
+#define RSCAN0TMDF145L (RSCAN0.TMDF145.UINT16[R_IO_L])
+#define RSCAN0TMDF145LL (RSCAN0.TMDF145.UINT8[R_IO_LL])
+#define RSCAN0TMDF145LH (RSCAN0.TMDF145.UINT8[R_IO_LH])
+#define RSCAN0TMDF145H (RSCAN0.TMDF145.UINT16[R_IO_H])
+#define RSCAN0TMDF145HL (RSCAN0.TMDF145.UINT8[R_IO_HL])
+#define RSCAN0TMDF145HH (RSCAN0.TMDF145.UINT8[R_IO_HH])
+#define RSCAN0TMID46 (RSCAN0.TMID46.UINT32)
+#define RSCAN0TMID46L (RSCAN0.TMID46.UINT16[R_IO_L])
+#define RSCAN0TMID46LL (RSCAN0.TMID46.UINT8[R_IO_LL])
+#define RSCAN0TMID46LH (RSCAN0.TMID46.UINT8[R_IO_LH])
+#define RSCAN0TMID46H (RSCAN0.TMID46.UINT16[R_IO_H])
+#define RSCAN0TMID46HL (RSCAN0.TMID46.UINT8[R_IO_HL])
+#define RSCAN0TMID46HH (RSCAN0.TMID46.UINT8[R_IO_HH])
+#define RSCAN0TMPTR46 (RSCAN0.TMPTR46.UINT32)
+#define RSCAN0TMPTR46L (RSCAN0.TMPTR46.UINT16[R_IO_L])
+#define RSCAN0TMPTR46LL (RSCAN0.TMPTR46.UINT8[R_IO_LL])
+#define RSCAN0TMPTR46LH (RSCAN0.TMPTR46.UINT8[R_IO_LH])
+#define RSCAN0TMPTR46H (RSCAN0.TMPTR46.UINT16[R_IO_H])
+#define RSCAN0TMPTR46HL (RSCAN0.TMPTR46.UINT8[R_IO_HL])
+#define RSCAN0TMPTR46HH (RSCAN0.TMPTR46.UINT8[R_IO_HH])
+#define RSCAN0TMDF046 (RSCAN0.TMDF046.UINT32)
+#define RSCAN0TMDF046L (RSCAN0.TMDF046.UINT16[R_IO_L])
+#define RSCAN0TMDF046LL (RSCAN0.TMDF046.UINT8[R_IO_LL])
+#define RSCAN0TMDF046LH (RSCAN0.TMDF046.UINT8[R_IO_LH])
+#define RSCAN0TMDF046H (RSCAN0.TMDF046.UINT16[R_IO_H])
+#define RSCAN0TMDF046HL (RSCAN0.TMDF046.UINT8[R_IO_HL])
+#define RSCAN0TMDF046HH (RSCAN0.TMDF046.UINT8[R_IO_HH])
+#define RSCAN0TMDF146 (RSCAN0.TMDF146.UINT32)
+#define RSCAN0TMDF146L (RSCAN0.TMDF146.UINT16[R_IO_L])
+#define RSCAN0TMDF146LL (RSCAN0.TMDF146.UINT8[R_IO_LL])
+#define RSCAN0TMDF146LH (RSCAN0.TMDF146.UINT8[R_IO_LH])
+#define RSCAN0TMDF146H (RSCAN0.TMDF146.UINT16[R_IO_H])
+#define RSCAN0TMDF146HL (RSCAN0.TMDF146.UINT8[R_IO_HL])
+#define RSCAN0TMDF146HH (RSCAN0.TMDF146.UINT8[R_IO_HH])
+#define RSCAN0TMID47 (RSCAN0.TMID47.UINT32)
+#define RSCAN0TMID47L (RSCAN0.TMID47.UINT16[R_IO_L])
+#define RSCAN0TMID47LL (RSCAN0.TMID47.UINT8[R_IO_LL])
+#define RSCAN0TMID47LH (RSCAN0.TMID47.UINT8[R_IO_LH])
+#define RSCAN0TMID47H (RSCAN0.TMID47.UINT16[R_IO_H])
+#define RSCAN0TMID47HL (RSCAN0.TMID47.UINT8[R_IO_HL])
+#define RSCAN0TMID47HH (RSCAN0.TMID47.UINT8[R_IO_HH])
+#define RSCAN0TMPTR47 (RSCAN0.TMPTR47.UINT32)
+#define RSCAN0TMPTR47L (RSCAN0.TMPTR47.UINT16[R_IO_L])
+#define RSCAN0TMPTR47LL (RSCAN0.TMPTR47.UINT8[R_IO_LL])
+#define RSCAN0TMPTR47LH (RSCAN0.TMPTR47.UINT8[R_IO_LH])
+#define RSCAN0TMPTR47H (RSCAN0.TMPTR47.UINT16[R_IO_H])
+#define RSCAN0TMPTR47HL (RSCAN0.TMPTR47.UINT8[R_IO_HL])
+#define RSCAN0TMPTR47HH (RSCAN0.TMPTR47.UINT8[R_IO_HH])
+#define RSCAN0TMDF047 (RSCAN0.TMDF047.UINT32)
+#define RSCAN0TMDF047L (RSCAN0.TMDF047.UINT16[R_IO_L])
+#define RSCAN0TMDF047LL (RSCAN0.TMDF047.UINT8[R_IO_LL])
+#define RSCAN0TMDF047LH (RSCAN0.TMDF047.UINT8[R_IO_LH])
+#define RSCAN0TMDF047H (RSCAN0.TMDF047.UINT16[R_IO_H])
+#define RSCAN0TMDF047HL (RSCAN0.TMDF047.UINT8[R_IO_HL])
+#define RSCAN0TMDF047HH (RSCAN0.TMDF047.UINT8[R_IO_HH])
+#define RSCAN0TMDF147 (RSCAN0.TMDF147.UINT32)
+#define RSCAN0TMDF147L (RSCAN0.TMDF147.UINT16[R_IO_L])
+#define RSCAN0TMDF147LL (RSCAN0.TMDF147.UINT8[R_IO_LL])
+#define RSCAN0TMDF147LH (RSCAN0.TMDF147.UINT8[R_IO_LH])
+#define RSCAN0TMDF147H (RSCAN0.TMDF147.UINT16[R_IO_H])
+#define RSCAN0TMDF147HL (RSCAN0.TMDF147.UINT8[R_IO_HL])
+#define RSCAN0TMDF147HH (RSCAN0.TMDF147.UINT8[R_IO_HH])
+#define RSCAN0TMID48 (RSCAN0.TMID48.UINT32)
+#define RSCAN0TMID48L (RSCAN0.TMID48.UINT16[R_IO_L])
+#define RSCAN0TMID48LL (RSCAN0.TMID48.UINT8[R_IO_LL])
+#define RSCAN0TMID48LH (RSCAN0.TMID48.UINT8[R_IO_LH])
+#define RSCAN0TMID48H (RSCAN0.TMID48.UINT16[R_IO_H])
+#define RSCAN0TMID48HL (RSCAN0.TMID48.UINT8[R_IO_HL])
+#define RSCAN0TMID48HH (RSCAN0.TMID48.UINT8[R_IO_HH])
+#define RSCAN0TMPTR48 (RSCAN0.TMPTR48.UINT32)
+#define RSCAN0TMPTR48L (RSCAN0.TMPTR48.UINT16[R_IO_L])
+#define RSCAN0TMPTR48LL (RSCAN0.TMPTR48.UINT8[R_IO_LL])
+#define RSCAN0TMPTR48LH (RSCAN0.TMPTR48.UINT8[R_IO_LH])
+#define RSCAN0TMPTR48H (RSCAN0.TMPTR48.UINT16[R_IO_H])
+#define RSCAN0TMPTR48HL (RSCAN0.TMPTR48.UINT8[R_IO_HL])
+#define RSCAN0TMPTR48HH (RSCAN0.TMPTR48.UINT8[R_IO_HH])
+#define RSCAN0TMDF048 (RSCAN0.TMDF048.UINT32)
+#define RSCAN0TMDF048L (RSCAN0.TMDF048.UINT16[R_IO_L])
+#define RSCAN0TMDF048LL (RSCAN0.TMDF048.UINT8[R_IO_LL])
+#define RSCAN0TMDF048LH (RSCAN0.TMDF048.UINT8[R_IO_LH])
+#define RSCAN0TMDF048H (RSCAN0.TMDF048.UINT16[R_IO_H])
+#define RSCAN0TMDF048HL (RSCAN0.TMDF048.UINT8[R_IO_HL])
+#define RSCAN0TMDF048HH (RSCAN0.TMDF048.UINT8[R_IO_HH])
+#define RSCAN0TMDF148 (RSCAN0.TMDF148.UINT32)
+#define RSCAN0TMDF148L (RSCAN0.TMDF148.UINT16[R_IO_L])
+#define RSCAN0TMDF148LL (RSCAN0.TMDF148.UINT8[R_IO_LL])
+#define RSCAN0TMDF148LH (RSCAN0.TMDF148.UINT8[R_IO_LH])
+#define RSCAN0TMDF148H (RSCAN0.TMDF148.UINT16[R_IO_H])
+#define RSCAN0TMDF148HL (RSCAN0.TMDF148.UINT8[R_IO_HL])
+#define RSCAN0TMDF148HH (RSCAN0.TMDF148.UINT8[R_IO_HH])
+#define RSCAN0TMID49 (RSCAN0.TMID49.UINT32)
+#define RSCAN0TMID49L (RSCAN0.TMID49.UINT16[R_IO_L])
+#define RSCAN0TMID49LL (RSCAN0.TMID49.UINT8[R_IO_LL])
+#define RSCAN0TMID49LH (RSCAN0.TMID49.UINT8[R_IO_LH])
+#define RSCAN0TMID49H (RSCAN0.TMID49.UINT16[R_IO_H])
+#define RSCAN0TMID49HL (RSCAN0.TMID49.UINT8[R_IO_HL])
+#define RSCAN0TMID49HH (RSCAN0.TMID49.UINT8[R_IO_HH])
+#define RSCAN0TMPTR49 (RSCAN0.TMPTR49.UINT32)
+#define RSCAN0TMPTR49L (RSCAN0.TMPTR49.UINT16[R_IO_L])
+#define RSCAN0TMPTR49LL (RSCAN0.TMPTR49.UINT8[R_IO_LL])
+#define RSCAN0TMPTR49LH (RSCAN0.TMPTR49.UINT8[R_IO_LH])
+#define RSCAN0TMPTR49H (RSCAN0.TMPTR49.UINT16[R_IO_H])
+#define RSCAN0TMPTR49HL (RSCAN0.TMPTR49.UINT8[R_IO_HL])
+#define RSCAN0TMPTR49HH (RSCAN0.TMPTR49.UINT8[R_IO_HH])
+#define RSCAN0TMDF049 (RSCAN0.TMDF049.UINT32)
+#define RSCAN0TMDF049L (RSCAN0.TMDF049.UINT16[R_IO_L])
+#define RSCAN0TMDF049LL (RSCAN0.TMDF049.UINT8[R_IO_LL])
+#define RSCAN0TMDF049LH (RSCAN0.TMDF049.UINT8[R_IO_LH])
+#define RSCAN0TMDF049H (RSCAN0.TMDF049.UINT16[R_IO_H])
+#define RSCAN0TMDF049HL (RSCAN0.TMDF049.UINT8[R_IO_HL])
+#define RSCAN0TMDF049HH (RSCAN0.TMDF049.UINT8[R_IO_HH])
+#define RSCAN0TMDF149 (RSCAN0.TMDF149.UINT32)
+#define RSCAN0TMDF149L (RSCAN0.TMDF149.UINT16[R_IO_L])
+#define RSCAN0TMDF149LL (RSCAN0.TMDF149.UINT8[R_IO_LL])
+#define RSCAN0TMDF149LH (RSCAN0.TMDF149.UINT8[R_IO_LH])
+#define RSCAN0TMDF149H (RSCAN0.TMDF149.UINT16[R_IO_H])
+#define RSCAN0TMDF149HL (RSCAN0.TMDF149.UINT8[R_IO_HL])
+#define RSCAN0TMDF149HH (RSCAN0.TMDF149.UINT8[R_IO_HH])
+#define RSCAN0TMID50 (RSCAN0.TMID50.UINT32)
+#define RSCAN0TMID50L (RSCAN0.TMID50.UINT16[R_IO_L])
+#define RSCAN0TMID50LL (RSCAN0.TMID50.UINT8[R_IO_LL])
+#define RSCAN0TMID50LH (RSCAN0.TMID50.UINT8[R_IO_LH])
+#define RSCAN0TMID50H (RSCAN0.TMID50.UINT16[R_IO_H])
+#define RSCAN0TMID50HL (RSCAN0.TMID50.UINT8[R_IO_HL])
+#define RSCAN0TMID50HH (RSCAN0.TMID50.UINT8[R_IO_HH])
+#define RSCAN0TMPTR50 (RSCAN0.TMPTR50.UINT32)
+#define RSCAN0TMPTR50L (RSCAN0.TMPTR50.UINT16[R_IO_L])
+#define RSCAN0TMPTR50LL (RSCAN0.TMPTR50.UINT8[R_IO_LL])
+#define RSCAN0TMPTR50LH (RSCAN0.TMPTR50.UINT8[R_IO_LH])
+#define RSCAN0TMPTR50H (RSCAN0.TMPTR50.UINT16[R_IO_H])
+#define RSCAN0TMPTR50HL (RSCAN0.TMPTR50.UINT8[R_IO_HL])
+#define RSCAN0TMPTR50HH (RSCAN0.TMPTR50.UINT8[R_IO_HH])
+#define RSCAN0TMDF050 (RSCAN0.TMDF050.UINT32)
+#define RSCAN0TMDF050L (RSCAN0.TMDF050.UINT16[R_IO_L])
+#define RSCAN0TMDF050LL (RSCAN0.TMDF050.UINT8[R_IO_LL])
+#define RSCAN0TMDF050LH (RSCAN0.TMDF050.UINT8[R_IO_LH])
+#define RSCAN0TMDF050H (RSCAN0.TMDF050.UINT16[R_IO_H])
+#define RSCAN0TMDF050HL (RSCAN0.TMDF050.UINT8[R_IO_HL])
+#define RSCAN0TMDF050HH (RSCAN0.TMDF050.UINT8[R_IO_HH])
+#define RSCAN0TMDF150 (RSCAN0.TMDF150.UINT32)
+#define RSCAN0TMDF150L (RSCAN0.TMDF150.UINT16[R_IO_L])
+#define RSCAN0TMDF150LL (RSCAN0.TMDF150.UINT8[R_IO_LL])
+#define RSCAN0TMDF150LH (RSCAN0.TMDF150.UINT8[R_IO_LH])
+#define RSCAN0TMDF150H (RSCAN0.TMDF150.UINT16[R_IO_H])
+#define RSCAN0TMDF150HL (RSCAN0.TMDF150.UINT8[R_IO_HL])
+#define RSCAN0TMDF150HH (RSCAN0.TMDF150.UINT8[R_IO_HH])
+#define RSCAN0TMID51 (RSCAN0.TMID51.UINT32)
+#define RSCAN0TMID51L (RSCAN0.TMID51.UINT16[R_IO_L])
+#define RSCAN0TMID51LL (RSCAN0.TMID51.UINT8[R_IO_LL])
+#define RSCAN0TMID51LH (RSCAN0.TMID51.UINT8[R_IO_LH])
+#define RSCAN0TMID51H (RSCAN0.TMID51.UINT16[R_IO_H])
+#define RSCAN0TMID51HL (RSCAN0.TMID51.UINT8[R_IO_HL])
+#define RSCAN0TMID51HH (RSCAN0.TMID51.UINT8[R_IO_HH])
+#define RSCAN0TMPTR51 (RSCAN0.TMPTR51.UINT32)
+#define RSCAN0TMPTR51L (RSCAN0.TMPTR51.UINT16[R_IO_L])
+#define RSCAN0TMPTR51LL (RSCAN0.TMPTR51.UINT8[R_IO_LL])
+#define RSCAN0TMPTR51LH (RSCAN0.TMPTR51.UINT8[R_IO_LH])
+#define RSCAN0TMPTR51H (RSCAN0.TMPTR51.UINT16[R_IO_H])
+#define RSCAN0TMPTR51HL (RSCAN0.TMPTR51.UINT8[R_IO_HL])
+#define RSCAN0TMPTR51HH (RSCAN0.TMPTR51.UINT8[R_IO_HH])
+#define RSCAN0TMDF051 (RSCAN0.TMDF051.UINT32)
+#define RSCAN0TMDF051L (RSCAN0.TMDF051.UINT16[R_IO_L])
+#define RSCAN0TMDF051LL (RSCAN0.TMDF051.UINT8[R_IO_LL])
+#define RSCAN0TMDF051LH (RSCAN0.TMDF051.UINT8[R_IO_LH])
+#define RSCAN0TMDF051H (RSCAN0.TMDF051.UINT16[R_IO_H])
+#define RSCAN0TMDF051HL (RSCAN0.TMDF051.UINT8[R_IO_HL])
+#define RSCAN0TMDF051HH (RSCAN0.TMDF051.UINT8[R_IO_HH])
+#define RSCAN0TMDF151 (RSCAN0.TMDF151.UINT32)
+#define RSCAN0TMDF151L (RSCAN0.TMDF151.UINT16[R_IO_L])
+#define RSCAN0TMDF151LL (RSCAN0.TMDF151.UINT8[R_IO_LL])
+#define RSCAN0TMDF151LH (RSCAN0.TMDF151.UINT8[R_IO_LH])
+#define RSCAN0TMDF151H (RSCAN0.TMDF151.UINT16[R_IO_H])
+#define RSCAN0TMDF151HL (RSCAN0.TMDF151.UINT8[R_IO_HL])
+#define RSCAN0TMDF151HH (RSCAN0.TMDF151.UINT8[R_IO_HH])
+#define RSCAN0TMID52 (RSCAN0.TMID52.UINT32)
+#define RSCAN0TMID52L (RSCAN0.TMID52.UINT16[R_IO_L])
+#define RSCAN0TMID52LL (RSCAN0.TMID52.UINT8[R_IO_LL])
+#define RSCAN0TMID52LH (RSCAN0.TMID52.UINT8[R_IO_LH])
+#define RSCAN0TMID52H (RSCAN0.TMID52.UINT16[R_IO_H])
+#define RSCAN0TMID52HL (RSCAN0.TMID52.UINT8[R_IO_HL])
+#define RSCAN0TMID52HH (RSCAN0.TMID52.UINT8[R_IO_HH])
+#define RSCAN0TMPTR52 (RSCAN0.TMPTR52.UINT32)
+#define RSCAN0TMPTR52L (RSCAN0.TMPTR52.UINT16[R_IO_L])
+#define RSCAN0TMPTR52LL (RSCAN0.TMPTR52.UINT8[R_IO_LL])
+#define RSCAN0TMPTR52LH (RSCAN0.TMPTR52.UINT8[R_IO_LH])
+#define RSCAN0TMPTR52H (RSCAN0.TMPTR52.UINT16[R_IO_H])
+#define RSCAN0TMPTR52HL (RSCAN0.TMPTR52.UINT8[R_IO_HL])
+#define RSCAN0TMPTR52HH (RSCAN0.TMPTR52.UINT8[R_IO_HH])
+#define RSCAN0TMDF052 (RSCAN0.TMDF052.UINT32)
+#define RSCAN0TMDF052L (RSCAN0.TMDF052.UINT16[R_IO_L])
+#define RSCAN0TMDF052LL (RSCAN0.TMDF052.UINT8[R_IO_LL])
+#define RSCAN0TMDF052LH (RSCAN0.TMDF052.UINT8[R_IO_LH])
+#define RSCAN0TMDF052H (RSCAN0.TMDF052.UINT16[R_IO_H])
+#define RSCAN0TMDF052HL (RSCAN0.TMDF052.UINT8[R_IO_HL])
+#define RSCAN0TMDF052HH (RSCAN0.TMDF052.UINT8[R_IO_HH])
+#define RSCAN0TMDF152 (RSCAN0.TMDF152.UINT32)
+#define RSCAN0TMDF152L (RSCAN0.TMDF152.UINT16[R_IO_L])
+#define RSCAN0TMDF152LL (RSCAN0.TMDF152.UINT8[R_IO_LL])
+#define RSCAN0TMDF152LH (RSCAN0.TMDF152.UINT8[R_IO_LH])
+#define RSCAN0TMDF152H (RSCAN0.TMDF152.UINT16[R_IO_H])
+#define RSCAN0TMDF152HL (RSCAN0.TMDF152.UINT8[R_IO_HL])
+#define RSCAN0TMDF152HH (RSCAN0.TMDF152.UINT8[R_IO_HH])
+#define RSCAN0TMID53 (RSCAN0.TMID53.UINT32)
+#define RSCAN0TMID53L (RSCAN0.TMID53.UINT16[R_IO_L])
+#define RSCAN0TMID53LL (RSCAN0.TMID53.UINT8[R_IO_LL])
+#define RSCAN0TMID53LH (RSCAN0.TMID53.UINT8[R_IO_LH])
+#define RSCAN0TMID53H (RSCAN0.TMID53.UINT16[R_IO_H])
+#define RSCAN0TMID53HL (RSCAN0.TMID53.UINT8[R_IO_HL])
+#define RSCAN0TMID53HH (RSCAN0.TMID53.UINT8[R_IO_HH])
+#define RSCAN0TMPTR53 (RSCAN0.TMPTR53.UINT32)
+#define RSCAN0TMPTR53L (RSCAN0.TMPTR53.UINT16[R_IO_L])
+#define RSCAN0TMPTR53LL (RSCAN0.TMPTR53.UINT8[R_IO_LL])
+#define RSCAN0TMPTR53LH (RSCAN0.TMPTR53.UINT8[R_IO_LH])
+#define RSCAN0TMPTR53H (RSCAN0.TMPTR53.UINT16[R_IO_H])
+#define RSCAN0TMPTR53HL (RSCAN0.TMPTR53.UINT8[R_IO_HL])
+#define RSCAN0TMPTR53HH (RSCAN0.TMPTR53.UINT8[R_IO_HH])
+#define RSCAN0TMDF053 (RSCAN0.TMDF053.UINT32)
+#define RSCAN0TMDF053L (RSCAN0.TMDF053.UINT16[R_IO_L])
+#define RSCAN0TMDF053LL (RSCAN0.TMDF053.UINT8[R_IO_LL])
+#define RSCAN0TMDF053LH (RSCAN0.TMDF053.UINT8[R_IO_LH])
+#define RSCAN0TMDF053H (RSCAN0.TMDF053.UINT16[R_IO_H])
+#define RSCAN0TMDF053HL (RSCAN0.TMDF053.UINT8[R_IO_HL])
+#define RSCAN0TMDF053HH (RSCAN0.TMDF053.UINT8[R_IO_HH])
+#define RSCAN0TMDF153 (RSCAN0.TMDF153.UINT32)
+#define RSCAN0TMDF153L (RSCAN0.TMDF153.UINT16[R_IO_L])
+#define RSCAN0TMDF153LL (RSCAN0.TMDF153.UINT8[R_IO_LL])
+#define RSCAN0TMDF153LH (RSCAN0.TMDF153.UINT8[R_IO_LH])
+#define RSCAN0TMDF153H (RSCAN0.TMDF153.UINT16[R_IO_H])
+#define RSCAN0TMDF153HL (RSCAN0.TMDF153.UINT8[R_IO_HL])
+#define RSCAN0TMDF153HH (RSCAN0.TMDF153.UINT8[R_IO_HH])
+#define RSCAN0TMID54 (RSCAN0.TMID54.UINT32)
+#define RSCAN0TMID54L (RSCAN0.TMID54.UINT16[R_IO_L])
+#define RSCAN0TMID54LL (RSCAN0.TMID54.UINT8[R_IO_LL])
+#define RSCAN0TMID54LH (RSCAN0.TMID54.UINT8[R_IO_LH])
+#define RSCAN0TMID54H (RSCAN0.TMID54.UINT16[R_IO_H])
+#define RSCAN0TMID54HL (RSCAN0.TMID54.UINT8[R_IO_HL])
+#define RSCAN0TMID54HH (RSCAN0.TMID54.UINT8[R_IO_HH])
+#define RSCAN0TMPTR54 (RSCAN0.TMPTR54.UINT32)
+#define RSCAN0TMPTR54L (RSCAN0.TMPTR54.UINT16[R_IO_L])
+#define RSCAN0TMPTR54LL (RSCAN0.TMPTR54.UINT8[R_IO_LL])
+#define RSCAN0TMPTR54LH (RSCAN0.TMPTR54.UINT8[R_IO_LH])
+#define RSCAN0TMPTR54H (RSCAN0.TMPTR54.UINT16[R_IO_H])
+#define RSCAN0TMPTR54HL (RSCAN0.TMPTR54.UINT8[R_IO_HL])
+#define RSCAN0TMPTR54HH (RSCAN0.TMPTR54.UINT8[R_IO_HH])
+#define RSCAN0TMDF054 (RSCAN0.TMDF054.UINT32)
+#define RSCAN0TMDF054L (RSCAN0.TMDF054.UINT16[R_IO_L])
+#define RSCAN0TMDF054LL (RSCAN0.TMDF054.UINT8[R_IO_LL])
+#define RSCAN0TMDF054LH (RSCAN0.TMDF054.UINT8[R_IO_LH])
+#define RSCAN0TMDF054H (RSCAN0.TMDF054.UINT16[R_IO_H])
+#define RSCAN0TMDF054HL (RSCAN0.TMDF054.UINT8[R_IO_HL])
+#define RSCAN0TMDF054HH (RSCAN0.TMDF054.UINT8[R_IO_HH])
+#define RSCAN0TMDF154 (RSCAN0.TMDF154.UINT32)
+#define RSCAN0TMDF154L (RSCAN0.TMDF154.UINT16[R_IO_L])
+#define RSCAN0TMDF154LL (RSCAN0.TMDF154.UINT8[R_IO_LL])
+#define RSCAN0TMDF154LH (RSCAN0.TMDF154.UINT8[R_IO_LH])
+#define RSCAN0TMDF154H (RSCAN0.TMDF154.UINT16[R_IO_H])
+#define RSCAN0TMDF154HL (RSCAN0.TMDF154.UINT8[R_IO_HL])
+#define RSCAN0TMDF154HH (RSCAN0.TMDF154.UINT8[R_IO_HH])
+#define RSCAN0TMID55 (RSCAN0.TMID55.UINT32)
+#define RSCAN0TMID55L (RSCAN0.TMID55.UINT16[R_IO_L])
+#define RSCAN0TMID55LL (RSCAN0.TMID55.UINT8[R_IO_LL])
+#define RSCAN0TMID55LH (RSCAN0.TMID55.UINT8[R_IO_LH])
+#define RSCAN0TMID55H (RSCAN0.TMID55.UINT16[R_IO_H])
+#define RSCAN0TMID55HL (RSCAN0.TMID55.UINT8[R_IO_HL])
+#define RSCAN0TMID55HH (RSCAN0.TMID55.UINT8[R_IO_HH])
+#define RSCAN0TMPTR55 (RSCAN0.TMPTR55.UINT32)
+#define RSCAN0TMPTR55L (RSCAN0.TMPTR55.UINT16[R_IO_L])
+#define RSCAN0TMPTR55LL (RSCAN0.TMPTR55.UINT8[R_IO_LL])
+#define RSCAN0TMPTR55LH (RSCAN0.TMPTR55.UINT8[R_IO_LH])
+#define RSCAN0TMPTR55H (RSCAN0.TMPTR55.UINT16[R_IO_H])
+#define RSCAN0TMPTR55HL (RSCAN0.TMPTR55.UINT8[R_IO_HL])
+#define RSCAN0TMPTR55HH (RSCAN0.TMPTR55.UINT8[R_IO_HH])
+#define RSCAN0TMDF055 (RSCAN0.TMDF055.UINT32)
+#define RSCAN0TMDF055L (RSCAN0.TMDF055.UINT16[R_IO_L])
+#define RSCAN0TMDF055LL (RSCAN0.TMDF055.UINT8[R_IO_LL])
+#define RSCAN0TMDF055LH (RSCAN0.TMDF055.UINT8[R_IO_LH])
+#define RSCAN0TMDF055H (RSCAN0.TMDF055.UINT16[R_IO_H])
+#define RSCAN0TMDF055HL (RSCAN0.TMDF055.UINT8[R_IO_HL])
+#define RSCAN0TMDF055HH (RSCAN0.TMDF055.UINT8[R_IO_HH])
+#define RSCAN0TMDF155 (RSCAN0.TMDF155.UINT32)
+#define RSCAN0TMDF155L (RSCAN0.TMDF155.UINT16[R_IO_L])
+#define RSCAN0TMDF155LL (RSCAN0.TMDF155.UINT8[R_IO_LL])
+#define RSCAN0TMDF155LH (RSCAN0.TMDF155.UINT8[R_IO_LH])
+#define RSCAN0TMDF155H (RSCAN0.TMDF155.UINT16[R_IO_H])
+#define RSCAN0TMDF155HL (RSCAN0.TMDF155.UINT8[R_IO_HL])
+#define RSCAN0TMDF155HH (RSCAN0.TMDF155.UINT8[R_IO_HH])
+#define RSCAN0TMID56 (RSCAN0.TMID56.UINT32)
+#define RSCAN0TMID56L (RSCAN0.TMID56.UINT16[R_IO_L])
+#define RSCAN0TMID56LL (RSCAN0.TMID56.UINT8[R_IO_LL])
+#define RSCAN0TMID56LH (RSCAN0.TMID56.UINT8[R_IO_LH])
+#define RSCAN0TMID56H (RSCAN0.TMID56.UINT16[R_IO_H])
+#define RSCAN0TMID56HL (RSCAN0.TMID56.UINT8[R_IO_HL])
+#define RSCAN0TMID56HH (RSCAN0.TMID56.UINT8[R_IO_HH])
+#define RSCAN0TMPTR56 (RSCAN0.TMPTR56.UINT32)
+#define RSCAN0TMPTR56L (RSCAN0.TMPTR56.UINT16[R_IO_L])
+#define RSCAN0TMPTR56LL (RSCAN0.TMPTR56.UINT8[R_IO_LL])
+#define RSCAN0TMPTR56LH (RSCAN0.TMPTR56.UINT8[R_IO_LH])
+#define RSCAN0TMPTR56H (RSCAN0.TMPTR56.UINT16[R_IO_H])
+#define RSCAN0TMPTR56HL (RSCAN0.TMPTR56.UINT8[R_IO_HL])
+#define RSCAN0TMPTR56HH (RSCAN0.TMPTR56.UINT8[R_IO_HH])
+#define RSCAN0TMDF056 (RSCAN0.TMDF056.UINT32)
+#define RSCAN0TMDF056L (RSCAN0.TMDF056.UINT16[R_IO_L])
+#define RSCAN0TMDF056LL (RSCAN0.TMDF056.UINT8[R_IO_LL])
+#define RSCAN0TMDF056LH (RSCAN0.TMDF056.UINT8[R_IO_LH])
+#define RSCAN0TMDF056H (RSCAN0.TMDF056.UINT16[R_IO_H])
+#define RSCAN0TMDF056HL (RSCAN0.TMDF056.UINT8[R_IO_HL])
+#define RSCAN0TMDF056HH (RSCAN0.TMDF056.UINT8[R_IO_HH])
+#define RSCAN0TMDF156 (RSCAN0.TMDF156.UINT32)
+#define RSCAN0TMDF156L (RSCAN0.TMDF156.UINT16[R_IO_L])
+#define RSCAN0TMDF156LL (RSCAN0.TMDF156.UINT8[R_IO_LL])
+#define RSCAN0TMDF156LH (RSCAN0.TMDF156.UINT8[R_IO_LH])
+#define RSCAN0TMDF156H (RSCAN0.TMDF156.UINT16[R_IO_H])
+#define RSCAN0TMDF156HL (RSCAN0.TMDF156.UINT8[R_IO_HL])
+#define RSCAN0TMDF156HH (RSCAN0.TMDF156.UINT8[R_IO_HH])
+#define RSCAN0TMID57 (RSCAN0.TMID57.UINT32)
+#define RSCAN0TMID57L (RSCAN0.TMID57.UINT16[R_IO_L])
+#define RSCAN0TMID57LL (RSCAN0.TMID57.UINT8[R_IO_LL])
+#define RSCAN0TMID57LH (RSCAN0.TMID57.UINT8[R_IO_LH])
+#define RSCAN0TMID57H (RSCAN0.TMID57.UINT16[R_IO_H])
+#define RSCAN0TMID57HL (RSCAN0.TMID57.UINT8[R_IO_HL])
+#define RSCAN0TMID57HH (RSCAN0.TMID57.UINT8[R_IO_HH])
+#define RSCAN0TMPTR57 (RSCAN0.TMPTR57.UINT32)
+#define RSCAN0TMPTR57L (RSCAN0.TMPTR57.UINT16[R_IO_L])
+#define RSCAN0TMPTR57LL (RSCAN0.TMPTR57.UINT8[R_IO_LL])
+#define RSCAN0TMPTR57LH (RSCAN0.TMPTR57.UINT8[R_IO_LH])
+#define RSCAN0TMPTR57H (RSCAN0.TMPTR57.UINT16[R_IO_H])
+#define RSCAN0TMPTR57HL (RSCAN0.TMPTR57.UINT8[R_IO_HL])
+#define RSCAN0TMPTR57HH (RSCAN0.TMPTR57.UINT8[R_IO_HH])
+#define RSCAN0TMDF057 (RSCAN0.TMDF057.UINT32)
+#define RSCAN0TMDF057L (RSCAN0.TMDF057.UINT16[R_IO_L])
+#define RSCAN0TMDF057LL (RSCAN0.TMDF057.UINT8[R_IO_LL])
+#define RSCAN0TMDF057LH (RSCAN0.TMDF057.UINT8[R_IO_LH])
+#define RSCAN0TMDF057H (RSCAN0.TMDF057.UINT16[R_IO_H])
+#define RSCAN0TMDF057HL (RSCAN0.TMDF057.UINT8[R_IO_HL])
+#define RSCAN0TMDF057HH (RSCAN0.TMDF057.UINT8[R_IO_HH])
+#define RSCAN0TMDF157 (RSCAN0.TMDF157.UINT32)
+#define RSCAN0TMDF157L (RSCAN0.TMDF157.UINT16[R_IO_L])
+#define RSCAN0TMDF157LL (RSCAN0.TMDF157.UINT8[R_IO_LL])
+#define RSCAN0TMDF157LH (RSCAN0.TMDF157.UINT8[R_IO_LH])
+#define RSCAN0TMDF157H (RSCAN0.TMDF157.UINT16[R_IO_H])
+#define RSCAN0TMDF157HL (RSCAN0.TMDF157.UINT8[R_IO_HL])
+#define RSCAN0TMDF157HH (RSCAN0.TMDF157.UINT8[R_IO_HH])
+#define RSCAN0TMID58 (RSCAN0.TMID58.UINT32)
+#define RSCAN0TMID58L (RSCAN0.TMID58.UINT16[R_IO_L])
+#define RSCAN0TMID58LL (RSCAN0.TMID58.UINT8[R_IO_LL])
+#define RSCAN0TMID58LH (RSCAN0.TMID58.UINT8[R_IO_LH])
+#define RSCAN0TMID58H (RSCAN0.TMID58.UINT16[R_IO_H])
+#define RSCAN0TMID58HL (RSCAN0.TMID58.UINT8[R_IO_HL])
+#define RSCAN0TMID58HH (RSCAN0.TMID58.UINT8[R_IO_HH])
+#define RSCAN0TMPTR58 (RSCAN0.TMPTR58.UINT32)
+#define RSCAN0TMPTR58L (RSCAN0.TMPTR58.UINT16[R_IO_L])
+#define RSCAN0TMPTR58LL (RSCAN0.TMPTR58.UINT8[R_IO_LL])
+#define RSCAN0TMPTR58LH (RSCAN0.TMPTR58.UINT8[R_IO_LH])
+#define RSCAN0TMPTR58H (RSCAN0.TMPTR58.UINT16[R_IO_H])
+#define RSCAN0TMPTR58HL (RSCAN0.TMPTR58.UINT8[R_IO_HL])
+#define RSCAN0TMPTR58HH (RSCAN0.TMPTR58.UINT8[R_IO_HH])
+#define RSCAN0TMDF058 (RSCAN0.TMDF058.UINT32)
+#define RSCAN0TMDF058L (RSCAN0.TMDF058.UINT16[R_IO_L])
+#define RSCAN0TMDF058LL (RSCAN0.TMDF058.UINT8[R_IO_LL])
+#define RSCAN0TMDF058LH (RSCAN0.TMDF058.UINT8[R_IO_LH])
+#define RSCAN0TMDF058H (RSCAN0.TMDF058.UINT16[R_IO_H])
+#define RSCAN0TMDF058HL (RSCAN0.TMDF058.UINT8[R_IO_HL])
+#define RSCAN0TMDF058HH (RSCAN0.TMDF058.UINT8[R_IO_HH])
+#define RSCAN0TMDF158 (RSCAN0.TMDF158.UINT32)
+#define RSCAN0TMDF158L (RSCAN0.TMDF158.UINT16[R_IO_L])
+#define RSCAN0TMDF158LL (RSCAN0.TMDF158.UINT8[R_IO_LL])
+#define RSCAN0TMDF158LH (RSCAN0.TMDF158.UINT8[R_IO_LH])
+#define RSCAN0TMDF158H (RSCAN0.TMDF158.UINT16[R_IO_H])
+#define RSCAN0TMDF158HL (RSCAN0.TMDF158.UINT8[R_IO_HL])
+#define RSCAN0TMDF158HH (RSCAN0.TMDF158.UINT8[R_IO_HH])
+#define RSCAN0TMID59 (RSCAN0.TMID59.UINT32)
+#define RSCAN0TMID59L (RSCAN0.TMID59.UINT16[R_IO_L])
+#define RSCAN0TMID59LL (RSCAN0.TMID59.UINT8[R_IO_LL])
+#define RSCAN0TMID59LH (RSCAN0.TMID59.UINT8[R_IO_LH])
+#define RSCAN0TMID59H (RSCAN0.TMID59.UINT16[R_IO_H])
+#define RSCAN0TMID59HL (RSCAN0.TMID59.UINT8[R_IO_HL])
+#define RSCAN0TMID59HH (RSCAN0.TMID59.UINT8[R_IO_HH])
+#define RSCAN0TMPTR59 (RSCAN0.TMPTR59.UINT32)
+#define RSCAN0TMPTR59L (RSCAN0.TMPTR59.UINT16[R_IO_L])
+#define RSCAN0TMPTR59LL (RSCAN0.TMPTR59.UINT8[R_IO_LL])
+#define RSCAN0TMPTR59LH (RSCAN0.TMPTR59.UINT8[R_IO_LH])
+#define RSCAN0TMPTR59H (RSCAN0.TMPTR59.UINT16[R_IO_H])
+#define RSCAN0TMPTR59HL (RSCAN0.TMPTR59.UINT8[R_IO_HL])
+#define RSCAN0TMPTR59HH (RSCAN0.TMPTR59.UINT8[R_IO_HH])
+#define RSCAN0TMDF059 (RSCAN0.TMDF059.UINT32)
+#define RSCAN0TMDF059L (RSCAN0.TMDF059.UINT16[R_IO_L])
+#define RSCAN0TMDF059LL (RSCAN0.TMDF059.UINT8[R_IO_LL])
+#define RSCAN0TMDF059LH (RSCAN0.TMDF059.UINT8[R_IO_LH])
+#define RSCAN0TMDF059H (RSCAN0.TMDF059.UINT16[R_IO_H])
+#define RSCAN0TMDF059HL (RSCAN0.TMDF059.UINT8[R_IO_HL])
+#define RSCAN0TMDF059HH (RSCAN0.TMDF059.UINT8[R_IO_HH])
+#define RSCAN0TMDF159 (RSCAN0.TMDF159.UINT32)
+#define RSCAN0TMDF159L (RSCAN0.TMDF159.UINT16[R_IO_L])
+#define RSCAN0TMDF159LL (RSCAN0.TMDF159.UINT8[R_IO_LL])
+#define RSCAN0TMDF159LH (RSCAN0.TMDF159.UINT8[R_IO_LH])
+#define RSCAN0TMDF159H (RSCAN0.TMDF159.UINT16[R_IO_H])
+#define RSCAN0TMDF159HL (RSCAN0.TMDF159.UINT8[R_IO_HL])
+#define RSCAN0TMDF159HH (RSCAN0.TMDF159.UINT8[R_IO_HH])
+#define RSCAN0TMID60 (RSCAN0.TMID60.UINT32)
+#define RSCAN0TMID60L (RSCAN0.TMID60.UINT16[R_IO_L])
+#define RSCAN0TMID60LL (RSCAN0.TMID60.UINT8[R_IO_LL])
+#define RSCAN0TMID60LH (RSCAN0.TMID60.UINT8[R_IO_LH])
+#define RSCAN0TMID60H (RSCAN0.TMID60.UINT16[R_IO_H])
+#define RSCAN0TMID60HL (RSCAN0.TMID60.UINT8[R_IO_HL])
+#define RSCAN0TMID60HH (RSCAN0.TMID60.UINT8[R_IO_HH])
+#define RSCAN0TMPTR60 (RSCAN0.TMPTR60.UINT32)
+#define RSCAN0TMPTR60L (RSCAN0.TMPTR60.UINT16[R_IO_L])
+#define RSCAN0TMPTR60LL (RSCAN0.TMPTR60.UINT8[R_IO_LL])
+#define RSCAN0TMPTR60LH (RSCAN0.TMPTR60.UINT8[R_IO_LH])
+#define RSCAN0TMPTR60H (RSCAN0.TMPTR60.UINT16[R_IO_H])
+#define RSCAN0TMPTR60HL (RSCAN0.TMPTR60.UINT8[R_IO_HL])
+#define RSCAN0TMPTR60HH (RSCAN0.TMPTR60.UINT8[R_IO_HH])
+#define RSCAN0TMDF060 (RSCAN0.TMDF060.UINT32)
+#define RSCAN0TMDF060L (RSCAN0.TMDF060.UINT16[R_IO_L])
+#define RSCAN0TMDF060LL (RSCAN0.TMDF060.UINT8[R_IO_LL])
+#define RSCAN0TMDF060LH (RSCAN0.TMDF060.UINT8[R_IO_LH])
+#define RSCAN0TMDF060H (RSCAN0.TMDF060.UINT16[R_IO_H])
+#define RSCAN0TMDF060HL (RSCAN0.TMDF060.UINT8[R_IO_HL])
+#define RSCAN0TMDF060HH (RSCAN0.TMDF060.UINT8[R_IO_HH])
+#define RSCAN0TMDF160 (RSCAN0.TMDF160.UINT32)
+#define RSCAN0TMDF160L (RSCAN0.TMDF160.UINT16[R_IO_L])
+#define RSCAN0TMDF160LL (RSCAN0.TMDF160.UINT8[R_IO_LL])
+#define RSCAN0TMDF160LH (RSCAN0.TMDF160.UINT8[R_IO_LH])
+#define RSCAN0TMDF160H (RSCAN0.TMDF160.UINT16[R_IO_H])
+#define RSCAN0TMDF160HL (RSCAN0.TMDF160.UINT8[R_IO_HL])
+#define RSCAN0TMDF160HH (RSCAN0.TMDF160.UINT8[R_IO_HH])
+#define RSCAN0TMID61 (RSCAN0.TMID61.UINT32)
+#define RSCAN0TMID61L (RSCAN0.TMID61.UINT16[R_IO_L])
+#define RSCAN0TMID61LL (RSCAN0.TMID61.UINT8[R_IO_LL])
+#define RSCAN0TMID61LH (RSCAN0.TMID61.UINT8[R_IO_LH])
+#define RSCAN0TMID61H (RSCAN0.TMID61.UINT16[R_IO_H])
+#define RSCAN0TMID61HL (RSCAN0.TMID61.UINT8[R_IO_HL])
+#define RSCAN0TMID61HH (RSCAN0.TMID61.UINT8[R_IO_HH])
+#define RSCAN0TMPTR61 (RSCAN0.TMPTR61.UINT32)
+#define RSCAN0TMPTR61L (RSCAN0.TMPTR61.UINT16[R_IO_L])
+#define RSCAN0TMPTR61LL (RSCAN0.TMPTR61.UINT8[R_IO_LL])
+#define RSCAN0TMPTR61LH (RSCAN0.TMPTR61.UINT8[R_IO_LH])
+#define RSCAN0TMPTR61H (RSCAN0.TMPTR61.UINT16[R_IO_H])
+#define RSCAN0TMPTR61HL (RSCAN0.TMPTR61.UINT8[R_IO_HL])
+#define RSCAN0TMPTR61HH (RSCAN0.TMPTR61.UINT8[R_IO_HH])
+#define RSCAN0TMDF061 (RSCAN0.TMDF061.UINT32)
+#define RSCAN0TMDF061L (RSCAN0.TMDF061.UINT16[R_IO_L])
+#define RSCAN0TMDF061LL (RSCAN0.TMDF061.UINT8[R_IO_LL])
+#define RSCAN0TMDF061LH (RSCAN0.TMDF061.UINT8[R_IO_LH])
+#define RSCAN0TMDF061H (RSCAN0.TMDF061.UINT16[R_IO_H])
+#define RSCAN0TMDF061HL (RSCAN0.TMDF061.UINT8[R_IO_HL])
+#define RSCAN0TMDF061HH (RSCAN0.TMDF061.UINT8[R_IO_HH])
+#define RSCAN0TMDF161 (RSCAN0.TMDF161.UINT32)
+#define RSCAN0TMDF161L (RSCAN0.TMDF161.UINT16[R_IO_L])
+#define RSCAN0TMDF161LL (RSCAN0.TMDF161.UINT8[R_IO_LL])
+#define RSCAN0TMDF161LH (RSCAN0.TMDF161.UINT8[R_IO_LH])
+#define RSCAN0TMDF161H (RSCAN0.TMDF161.UINT16[R_IO_H])
+#define RSCAN0TMDF161HL (RSCAN0.TMDF161.UINT8[R_IO_HL])
+#define RSCAN0TMDF161HH (RSCAN0.TMDF161.UINT8[R_IO_HH])
+#define RSCAN0TMID62 (RSCAN0.TMID62.UINT32)
+#define RSCAN0TMID62L (RSCAN0.TMID62.UINT16[R_IO_L])
+#define RSCAN0TMID62LL (RSCAN0.TMID62.UINT8[R_IO_LL])
+#define RSCAN0TMID62LH (RSCAN0.TMID62.UINT8[R_IO_LH])
+#define RSCAN0TMID62H (RSCAN0.TMID62.UINT16[R_IO_H])
+#define RSCAN0TMID62HL (RSCAN0.TMID62.UINT8[R_IO_HL])
+#define RSCAN0TMID62HH (RSCAN0.TMID62.UINT8[R_IO_HH])
+#define RSCAN0TMPTR62 (RSCAN0.TMPTR62.UINT32)
+#define RSCAN0TMPTR62L (RSCAN0.TMPTR62.UINT16[R_IO_L])
+#define RSCAN0TMPTR62LL (RSCAN0.TMPTR62.UINT8[R_IO_LL])
+#define RSCAN0TMPTR62LH (RSCAN0.TMPTR62.UINT8[R_IO_LH])
+#define RSCAN0TMPTR62H (RSCAN0.TMPTR62.UINT16[R_IO_H])
+#define RSCAN0TMPTR62HL (RSCAN0.TMPTR62.UINT8[R_IO_HL])
+#define RSCAN0TMPTR62HH (RSCAN0.TMPTR62.UINT8[R_IO_HH])
+#define RSCAN0TMDF062 (RSCAN0.TMDF062.UINT32)
+#define RSCAN0TMDF062L (RSCAN0.TMDF062.UINT16[R_IO_L])
+#define RSCAN0TMDF062LL (RSCAN0.TMDF062.UINT8[R_IO_LL])
+#define RSCAN0TMDF062LH (RSCAN0.TMDF062.UINT8[R_IO_LH])
+#define RSCAN0TMDF062H (RSCAN0.TMDF062.UINT16[R_IO_H])
+#define RSCAN0TMDF062HL (RSCAN0.TMDF062.UINT8[R_IO_HL])
+#define RSCAN0TMDF062HH (RSCAN0.TMDF062.UINT8[R_IO_HH])
+#define RSCAN0TMDF162 (RSCAN0.TMDF162.UINT32)
+#define RSCAN0TMDF162L (RSCAN0.TMDF162.UINT16[R_IO_L])
+#define RSCAN0TMDF162LL (RSCAN0.TMDF162.UINT8[R_IO_LL])
+#define RSCAN0TMDF162LH (RSCAN0.TMDF162.UINT8[R_IO_LH])
+#define RSCAN0TMDF162H (RSCAN0.TMDF162.UINT16[R_IO_H])
+#define RSCAN0TMDF162HL (RSCAN0.TMDF162.UINT8[R_IO_HL])
+#define RSCAN0TMDF162HH (RSCAN0.TMDF162.UINT8[R_IO_HH])
+#define RSCAN0TMID63 (RSCAN0.TMID63.UINT32)
+#define RSCAN0TMID63L (RSCAN0.TMID63.UINT16[R_IO_L])
+#define RSCAN0TMID63LL (RSCAN0.TMID63.UINT8[R_IO_LL])
+#define RSCAN0TMID63LH (RSCAN0.TMID63.UINT8[R_IO_LH])
+#define RSCAN0TMID63H (RSCAN0.TMID63.UINT16[R_IO_H])
+#define RSCAN0TMID63HL (RSCAN0.TMID63.UINT8[R_IO_HL])
+#define RSCAN0TMID63HH (RSCAN0.TMID63.UINT8[R_IO_HH])
+#define RSCAN0TMPTR63 (RSCAN0.TMPTR63.UINT32)
+#define RSCAN0TMPTR63L (RSCAN0.TMPTR63.UINT16[R_IO_L])
+#define RSCAN0TMPTR63LL (RSCAN0.TMPTR63.UINT8[R_IO_LL])
+#define RSCAN0TMPTR63LH (RSCAN0.TMPTR63.UINT8[R_IO_LH])
+#define RSCAN0TMPTR63H (RSCAN0.TMPTR63.UINT16[R_IO_H])
+#define RSCAN0TMPTR63HL (RSCAN0.TMPTR63.UINT8[R_IO_HL])
+#define RSCAN0TMPTR63HH (RSCAN0.TMPTR63.UINT8[R_IO_HH])
+#define RSCAN0TMDF063 (RSCAN0.TMDF063.UINT32)
+#define RSCAN0TMDF063L (RSCAN0.TMDF063.UINT16[R_IO_L])
+#define RSCAN0TMDF063LL (RSCAN0.TMDF063.UINT8[R_IO_LL])
+#define RSCAN0TMDF063LH (RSCAN0.TMDF063.UINT8[R_IO_LH])
+#define RSCAN0TMDF063H (RSCAN0.TMDF063.UINT16[R_IO_H])
+#define RSCAN0TMDF063HL (RSCAN0.TMDF063.UINT8[R_IO_HL])
+#define RSCAN0TMDF063HH (RSCAN0.TMDF063.UINT8[R_IO_HH])
+#define RSCAN0TMDF163 (RSCAN0.TMDF163.UINT32)
+#define RSCAN0TMDF163L (RSCAN0.TMDF163.UINT16[R_IO_L])
+#define RSCAN0TMDF163LL (RSCAN0.TMDF163.UINT8[R_IO_LL])
+#define RSCAN0TMDF163LH (RSCAN0.TMDF163.UINT8[R_IO_LH])
+#define RSCAN0TMDF163H (RSCAN0.TMDF163.UINT16[R_IO_H])
+#define RSCAN0TMDF163HL (RSCAN0.TMDF163.UINT8[R_IO_HL])
+#define RSCAN0TMDF163HH (RSCAN0.TMDF163.UINT8[R_IO_HH])
+#define RSCAN0TMID64 (RSCAN0.TMID64.UINT32)
+#define RSCAN0TMID64L (RSCAN0.TMID64.UINT16[R_IO_L])
+#define RSCAN0TMID64LL (RSCAN0.TMID64.UINT8[R_IO_LL])
+#define RSCAN0TMID64LH (RSCAN0.TMID64.UINT8[R_IO_LH])
+#define RSCAN0TMID64H (RSCAN0.TMID64.UINT16[R_IO_H])
+#define RSCAN0TMID64HL (RSCAN0.TMID64.UINT8[R_IO_HL])
+#define RSCAN0TMID64HH (RSCAN0.TMID64.UINT8[R_IO_HH])
+#define RSCAN0TMPTR64 (RSCAN0.TMPTR64.UINT32)
+#define RSCAN0TMPTR64L (RSCAN0.TMPTR64.UINT16[R_IO_L])
+#define RSCAN0TMPTR64LL (RSCAN0.TMPTR64.UINT8[R_IO_LL])
+#define RSCAN0TMPTR64LH (RSCAN0.TMPTR64.UINT8[R_IO_LH])
+#define RSCAN0TMPTR64H (RSCAN0.TMPTR64.UINT16[R_IO_H])
+#define RSCAN0TMPTR64HL (RSCAN0.TMPTR64.UINT8[R_IO_HL])
+#define RSCAN0TMPTR64HH (RSCAN0.TMPTR64.UINT8[R_IO_HH])
+#define RSCAN0TMDF064 (RSCAN0.TMDF064.UINT32)
+#define RSCAN0TMDF064L (RSCAN0.TMDF064.UINT16[R_IO_L])
+#define RSCAN0TMDF064LL (RSCAN0.TMDF064.UINT8[R_IO_LL])
+#define RSCAN0TMDF064LH (RSCAN0.TMDF064.UINT8[R_IO_LH])
+#define RSCAN0TMDF064H (RSCAN0.TMDF064.UINT16[R_IO_H])
+#define RSCAN0TMDF064HL (RSCAN0.TMDF064.UINT8[R_IO_HL])
+#define RSCAN0TMDF064HH (RSCAN0.TMDF064.UINT8[R_IO_HH])
+#define RSCAN0TMDF164 (RSCAN0.TMDF164.UINT32)
+#define RSCAN0TMDF164L (RSCAN0.TMDF164.UINT16[R_IO_L])
+#define RSCAN0TMDF164LL (RSCAN0.TMDF164.UINT8[R_IO_LL])
+#define RSCAN0TMDF164LH (RSCAN0.TMDF164.UINT8[R_IO_LH])
+#define RSCAN0TMDF164H (RSCAN0.TMDF164.UINT16[R_IO_H])
+#define RSCAN0TMDF164HL (RSCAN0.TMDF164.UINT8[R_IO_HL])
+#define RSCAN0TMDF164HH (RSCAN0.TMDF164.UINT8[R_IO_HH])
+#define RSCAN0TMID65 (RSCAN0.TMID65.UINT32)
+#define RSCAN0TMID65L (RSCAN0.TMID65.UINT16[R_IO_L])
+#define RSCAN0TMID65LL (RSCAN0.TMID65.UINT8[R_IO_LL])
+#define RSCAN0TMID65LH (RSCAN0.TMID65.UINT8[R_IO_LH])
+#define RSCAN0TMID65H (RSCAN0.TMID65.UINT16[R_IO_H])
+#define RSCAN0TMID65HL (RSCAN0.TMID65.UINT8[R_IO_HL])
+#define RSCAN0TMID65HH (RSCAN0.TMID65.UINT8[R_IO_HH])
+#define RSCAN0TMPTR65 (RSCAN0.TMPTR65.UINT32)
+#define RSCAN0TMPTR65L (RSCAN0.TMPTR65.UINT16[R_IO_L])
+#define RSCAN0TMPTR65LL (RSCAN0.TMPTR65.UINT8[R_IO_LL])
+#define RSCAN0TMPTR65LH (RSCAN0.TMPTR65.UINT8[R_IO_LH])
+#define RSCAN0TMPTR65H (RSCAN0.TMPTR65.UINT16[R_IO_H])
+#define RSCAN0TMPTR65HL (RSCAN0.TMPTR65.UINT8[R_IO_HL])
+#define RSCAN0TMPTR65HH (RSCAN0.TMPTR65.UINT8[R_IO_HH])
+#define RSCAN0TMDF065 (RSCAN0.TMDF065.UINT32)
+#define RSCAN0TMDF065L (RSCAN0.TMDF065.UINT16[R_IO_L])
+#define RSCAN0TMDF065LL (RSCAN0.TMDF065.UINT8[R_IO_LL])
+#define RSCAN0TMDF065LH (RSCAN0.TMDF065.UINT8[R_IO_LH])
+#define RSCAN0TMDF065H (RSCAN0.TMDF065.UINT16[R_IO_H])
+#define RSCAN0TMDF065HL (RSCAN0.TMDF065.UINT8[R_IO_HL])
+#define RSCAN0TMDF065HH (RSCAN0.TMDF065.UINT8[R_IO_HH])
+#define RSCAN0TMDF165 (RSCAN0.TMDF165.UINT32)
+#define RSCAN0TMDF165L (RSCAN0.TMDF165.UINT16[R_IO_L])
+#define RSCAN0TMDF165LL (RSCAN0.TMDF165.UINT8[R_IO_LL])
+#define RSCAN0TMDF165LH (RSCAN0.TMDF165.UINT8[R_IO_LH])
+#define RSCAN0TMDF165H (RSCAN0.TMDF165.UINT16[R_IO_H])
+#define RSCAN0TMDF165HL (RSCAN0.TMDF165.UINT8[R_IO_HL])
+#define RSCAN0TMDF165HH (RSCAN0.TMDF165.UINT8[R_IO_HH])
+#define RSCAN0TMID66 (RSCAN0.TMID66.UINT32)
+#define RSCAN0TMID66L (RSCAN0.TMID66.UINT16[R_IO_L])
+#define RSCAN0TMID66LL (RSCAN0.TMID66.UINT8[R_IO_LL])
+#define RSCAN0TMID66LH (RSCAN0.TMID66.UINT8[R_IO_LH])
+#define RSCAN0TMID66H (RSCAN0.TMID66.UINT16[R_IO_H])
+#define RSCAN0TMID66HL (RSCAN0.TMID66.UINT8[R_IO_HL])
+#define RSCAN0TMID66HH (RSCAN0.TMID66.UINT8[R_IO_HH])
+#define RSCAN0TMPTR66 (RSCAN0.TMPTR66.UINT32)
+#define RSCAN0TMPTR66L (RSCAN0.TMPTR66.UINT16[R_IO_L])
+#define RSCAN0TMPTR66LL (RSCAN0.TMPTR66.UINT8[R_IO_LL])
+#define RSCAN0TMPTR66LH (RSCAN0.TMPTR66.UINT8[R_IO_LH])
+#define RSCAN0TMPTR66H (RSCAN0.TMPTR66.UINT16[R_IO_H])
+#define RSCAN0TMPTR66HL (RSCAN0.TMPTR66.UINT8[R_IO_HL])
+#define RSCAN0TMPTR66HH (RSCAN0.TMPTR66.UINT8[R_IO_HH])
+#define RSCAN0TMDF066 (RSCAN0.TMDF066.UINT32)
+#define RSCAN0TMDF066L (RSCAN0.TMDF066.UINT16[R_IO_L])
+#define RSCAN0TMDF066LL (RSCAN0.TMDF066.UINT8[R_IO_LL])
+#define RSCAN0TMDF066LH (RSCAN0.TMDF066.UINT8[R_IO_LH])
+#define RSCAN0TMDF066H (RSCAN0.TMDF066.UINT16[R_IO_H])
+#define RSCAN0TMDF066HL (RSCAN0.TMDF066.UINT8[R_IO_HL])
+#define RSCAN0TMDF066HH (RSCAN0.TMDF066.UINT8[R_IO_HH])
+#define RSCAN0TMDF166 (RSCAN0.TMDF166.UINT32)
+#define RSCAN0TMDF166L (RSCAN0.TMDF166.UINT16[R_IO_L])
+#define RSCAN0TMDF166LL (RSCAN0.TMDF166.UINT8[R_IO_LL])
+#define RSCAN0TMDF166LH (RSCAN0.TMDF166.UINT8[R_IO_LH])
+#define RSCAN0TMDF166H (RSCAN0.TMDF166.UINT16[R_IO_H])
+#define RSCAN0TMDF166HL (RSCAN0.TMDF166.UINT8[R_IO_HL])
+#define RSCAN0TMDF166HH (RSCAN0.TMDF166.UINT8[R_IO_HH])
+#define RSCAN0TMID67 (RSCAN0.TMID67.UINT32)
+#define RSCAN0TMID67L (RSCAN0.TMID67.UINT16[R_IO_L])
+#define RSCAN0TMID67LL (RSCAN0.TMID67.UINT8[R_IO_LL])
+#define RSCAN0TMID67LH (RSCAN0.TMID67.UINT8[R_IO_LH])
+#define RSCAN0TMID67H (RSCAN0.TMID67.UINT16[R_IO_H])
+#define RSCAN0TMID67HL (RSCAN0.TMID67.UINT8[R_IO_HL])
+#define RSCAN0TMID67HH (RSCAN0.TMID67.UINT8[R_IO_HH])
+#define RSCAN0TMPTR67 (RSCAN0.TMPTR67.UINT32)
+#define RSCAN0TMPTR67L (RSCAN0.TMPTR67.UINT16[R_IO_L])
+#define RSCAN0TMPTR67LL (RSCAN0.TMPTR67.UINT8[R_IO_LL])
+#define RSCAN0TMPTR67LH (RSCAN0.TMPTR67.UINT8[R_IO_LH])
+#define RSCAN0TMPTR67H (RSCAN0.TMPTR67.UINT16[R_IO_H])
+#define RSCAN0TMPTR67HL (RSCAN0.TMPTR67.UINT8[R_IO_HL])
+#define RSCAN0TMPTR67HH (RSCAN0.TMPTR67.UINT8[R_IO_HH])
+#define RSCAN0TMDF067 (RSCAN0.TMDF067.UINT32)
+#define RSCAN0TMDF067L (RSCAN0.TMDF067.UINT16[R_IO_L])
+#define RSCAN0TMDF067LL (RSCAN0.TMDF067.UINT8[R_IO_LL])
+#define RSCAN0TMDF067LH (RSCAN0.TMDF067.UINT8[R_IO_LH])
+#define RSCAN0TMDF067H (RSCAN0.TMDF067.UINT16[R_IO_H])
+#define RSCAN0TMDF067HL (RSCAN0.TMDF067.UINT8[R_IO_HL])
+#define RSCAN0TMDF067HH (RSCAN0.TMDF067.UINT8[R_IO_HH])
+#define RSCAN0TMDF167 (RSCAN0.TMDF167.UINT32)
+#define RSCAN0TMDF167L (RSCAN0.TMDF167.UINT16[R_IO_L])
+#define RSCAN0TMDF167LL (RSCAN0.TMDF167.UINT8[R_IO_LL])
+#define RSCAN0TMDF167LH (RSCAN0.TMDF167.UINT8[R_IO_LH])
+#define RSCAN0TMDF167H (RSCAN0.TMDF167.UINT16[R_IO_H])
+#define RSCAN0TMDF167HL (RSCAN0.TMDF167.UINT8[R_IO_HL])
+#define RSCAN0TMDF167HH (RSCAN0.TMDF167.UINT8[R_IO_HH])
+#define RSCAN0TMID68 (RSCAN0.TMID68.UINT32)
+#define RSCAN0TMID68L (RSCAN0.TMID68.UINT16[R_IO_L])
+#define RSCAN0TMID68LL (RSCAN0.TMID68.UINT8[R_IO_LL])
+#define RSCAN0TMID68LH (RSCAN0.TMID68.UINT8[R_IO_LH])
+#define RSCAN0TMID68H (RSCAN0.TMID68.UINT16[R_IO_H])
+#define RSCAN0TMID68HL (RSCAN0.TMID68.UINT8[R_IO_HL])
+#define RSCAN0TMID68HH (RSCAN0.TMID68.UINT8[R_IO_HH])
+#define RSCAN0TMPTR68 (RSCAN0.TMPTR68.UINT32)
+#define RSCAN0TMPTR68L (RSCAN0.TMPTR68.UINT16[R_IO_L])
+#define RSCAN0TMPTR68LL (RSCAN0.TMPTR68.UINT8[R_IO_LL])
+#define RSCAN0TMPTR68LH (RSCAN0.TMPTR68.UINT8[R_IO_LH])
+#define RSCAN0TMPTR68H (RSCAN0.TMPTR68.UINT16[R_IO_H])
+#define RSCAN0TMPTR68HL (RSCAN0.TMPTR68.UINT8[R_IO_HL])
+#define RSCAN0TMPTR68HH (RSCAN0.TMPTR68.UINT8[R_IO_HH])
+#define RSCAN0TMDF068 (RSCAN0.TMDF068.UINT32)
+#define RSCAN0TMDF068L (RSCAN0.TMDF068.UINT16[R_IO_L])
+#define RSCAN0TMDF068LL (RSCAN0.TMDF068.UINT8[R_IO_LL])
+#define RSCAN0TMDF068LH (RSCAN0.TMDF068.UINT8[R_IO_LH])
+#define RSCAN0TMDF068H (RSCAN0.TMDF068.UINT16[R_IO_H])
+#define RSCAN0TMDF068HL (RSCAN0.TMDF068.UINT8[R_IO_HL])
+#define RSCAN0TMDF068HH (RSCAN0.TMDF068.UINT8[R_IO_HH])
+#define RSCAN0TMDF168 (RSCAN0.TMDF168.UINT32)
+#define RSCAN0TMDF168L (RSCAN0.TMDF168.UINT16[R_IO_L])
+#define RSCAN0TMDF168LL (RSCAN0.TMDF168.UINT8[R_IO_LL])
+#define RSCAN0TMDF168LH (RSCAN0.TMDF168.UINT8[R_IO_LH])
+#define RSCAN0TMDF168H (RSCAN0.TMDF168.UINT16[R_IO_H])
+#define RSCAN0TMDF168HL (RSCAN0.TMDF168.UINT8[R_IO_HL])
+#define RSCAN0TMDF168HH (RSCAN0.TMDF168.UINT8[R_IO_HH])
+#define RSCAN0TMID69 (RSCAN0.TMID69.UINT32)
+#define RSCAN0TMID69L (RSCAN0.TMID69.UINT16[R_IO_L])
+#define RSCAN0TMID69LL (RSCAN0.TMID69.UINT8[R_IO_LL])
+#define RSCAN0TMID69LH (RSCAN0.TMID69.UINT8[R_IO_LH])
+#define RSCAN0TMID69H (RSCAN0.TMID69.UINT16[R_IO_H])
+#define RSCAN0TMID69HL (RSCAN0.TMID69.UINT8[R_IO_HL])
+#define RSCAN0TMID69HH (RSCAN0.TMID69.UINT8[R_IO_HH])
+#define RSCAN0TMPTR69 (RSCAN0.TMPTR69.UINT32)
+#define RSCAN0TMPTR69L (RSCAN0.TMPTR69.UINT16[R_IO_L])
+#define RSCAN0TMPTR69LL (RSCAN0.TMPTR69.UINT8[R_IO_LL])
+#define RSCAN0TMPTR69LH (RSCAN0.TMPTR69.UINT8[R_IO_LH])
+#define RSCAN0TMPTR69H (RSCAN0.TMPTR69.UINT16[R_IO_H])
+#define RSCAN0TMPTR69HL (RSCAN0.TMPTR69.UINT8[R_IO_HL])
+#define RSCAN0TMPTR69HH (RSCAN0.TMPTR69.UINT8[R_IO_HH])
+#define RSCAN0TMDF069 (RSCAN0.TMDF069.UINT32)
+#define RSCAN0TMDF069L (RSCAN0.TMDF069.UINT16[R_IO_L])
+#define RSCAN0TMDF069LL (RSCAN0.TMDF069.UINT8[R_IO_LL])
+#define RSCAN0TMDF069LH (RSCAN0.TMDF069.UINT8[R_IO_LH])
+#define RSCAN0TMDF069H (RSCAN0.TMDF069.UINT16[R_IO_H])
+#define RSCAN0TMDF069HL (RSCAN0.TMDF069.UINT8[R_IO_HL])
+#define RSCAN0TMDF069HH (RSCAN0.TMDF069.UINT8[R_IO_HH])
+#define RSCAN0TMDF169 (RSCAN0.TMDF169.UINT32)
+#define RSCAN0TMDF169L (RSCAN0.TMDF169.UINT16[R_IO_L])
+#define RSCAN0TMDF169LL (RSCAN0.TMDF169.UINT8[R_IO_LL])
+#define RSCAN0TMDF169LH (RSCAN0.TMDF169.UINT8[R_IO_LH])
+#define RSCAN0TMDF169H (RSCAN0.TMDF169.UINT16[R_IO_H])
+#define RSCAN0TMDF169HL (RSCAN0.TMDF169.UINT8[R_IO_HL])
+#define RSCAN0TMDF169HH (RSCAN0.TMDF169.UINT8[R_IO_HH])
+#define RSCAN0TMID70 (RSCAN0.TMID70.UINT32)
+#define RSCAN0TMID70L (RSCAN0.TMID70.UINT16[R_IO_L])
+#define RSCAN0TMID70LL (RSCAN0.TMID70.UINT8[R_IO_LL])
+#define RSCAN0TMID70LH (RSCAN0.TMID70.UINT8[R_IO_LH])
+#define RSCAN0TMID70H (RSCAN0.TMID70.UINT16[R_IO_H])
+#define RSCAN0TMID70HL (RSCAN0.TMID70.UINT8[R_IO_HL])
+#define RSCAN0TMID70HH (RSCAN0.TMID70.UINT8[R_IO_HH])
+#define RSCAN0TMPTR70 (RSCAN0.TMPTR70.UINT32)
+#define RSCAN0TMPTR70L (RSCAN0.TMPTR70.UINT16[R_IO_L])
+#define RSCAN0TMPTR70LL (RSCAN0.TMPTR70.UINT8[R_IO_LL])
+#define RSCAN0TMPTR70LH (RSCAN0.TMPTR70.UINT8[R_IO_LH])
+#define RSCAN0TMPTR70H (RSCAN0.TMPTR70.UINT16[R_IO_H])
+#define RSCAN0TMPTR70HL (RSCAN0.TMPTR70.UINT8[R_IO_HL])
+#define RSCAN0TMPTR70HH (RSCAN0.TMPTR70.UINT8[R_IO_HH])
+#define RSCAN0TMDF070 (RSCAN0.TMDF070.UINT32)
+#define RSCAN0TMDF070L (RSCAN0.TMDF070.UINT16[R_IO_L])
+#define RSCAN0TMDF070LL (RSCAN0.TMDF070.UINT8[R_IO_LL])
+#define RSCAN0TMDF070LH (RSCAN0.TMDF070.UINT8[R_IO_LH])
+#define RSCAN0TMDF070H (RSCAN0.TMDF070.UINT16[R_IO_H])
+#define RSCAN0TMDF070HL (RSCAN0.TMDF070.UINT8[R_IO_HL])
+#define RSCAN0TMDF070HH (RSCAN0.TMDF070.UINT8[R_IO_HH])
+#define RSCAN0TMDF170 (RSCAN0.TMDF170.UINT32)
+#define RSCAN0TMDF170L (RSCAN0.TMDF170.UINT16[R_IO_L])
+#define RSCAN0TMDF170LL (RSCAN0.TMDF170.UINT8[R_IO_LL])
+#define RSCAN0TMDF170LH (RSCAN0.TMDF170.UINT8[R_IO_LH])
+#define RSCAN0TMDF170H (RSCAN0.TMDF170.UINT16[R_IO_H])
+#define RSCAN0TMDF170HL (RSCAN0.TMDF170.UINT8[R_IO_HL])
+#define RSCAN0TMDF170HH (RSCAN0.TMDF170.UINT8[R_IO_HH])
+#define RSCAN0TMID71 (RSCAN0.TMID71.UINT32)
+#define RSCAN0TMID71L (RSCAN0.TMID71.UINT16[R_IO_L])
+#define RSCAN0TMID71LL (RSCAN0.TMID71.UINT8[R_IO_LL])
+#define RSCAN0TMID71LH (RSCAN0.TMID71.UINT8[R_IO_LH])
+#define RSCAN0TMID71H (RSCAN0.TMID71.UINT16[R_IO_H])
+#define RSCAN0TMID71HL (RSCAN0.TMID71.UINT8[R_IO_HL])
+#define RSCAN0TMID71HH (RSCAN0.TMID71.UINT8[R_IO_HH])
+#define RSCAN0TMPTR71 (RSCAN0.TMPTR71.UINT32)
+#define RSCAN0TMPTR71L (RSCAN0.TMPTR71.UINT16[R_IO_L])
+#define RSCAN0TMPTR71LL (RSCAN0.TMPTR71.UINT8[R_IO_LL])
+#define RSCAN0TMPTR71LH (RSCAN0.TMPTR71.UINT8[R_IO_LH])
+#define RSCAN0TMPTR71H (RSCAN0.TMPTR71.UINT16[R_IO_H])
+#define RSCAN0TMPTR71HL (RSCAN0.TMPTR71.UINT8[R_IO_HL])
+#define RSCAN0TMPTR71HH (RSCAN0.TMPTR71.UINT8[R_IO_HH])
+#define RSCAN0TMDF071 (RSCAN0.TMDF071.UINT32)
+#define RSCAN0TMDF071L (RSCAN0.TMDF071.UINT16[R_IO_L])
+#define RSCAN0TMDF071LL (RSCAN0.TMDF071.UINT8[R_IO_LL])
+#define RSCAN0TMDF071LH (RSCAN0.TMDF071.UINT8[R_IO_LH])
+#define RSCAN0TMDF071H (RSCAN0.TMDF071.UINT16[R_IO_H])
+#define RSCAN0TMDF071HL (RSCAN0.TMDF071.UINT8[R_IO_HL])
+#define RSCAN0TMDF071HH (RSCAN0.TMDF071.UINT8[R_IO_HH])
+#define RSCAN0TMDF171 (RSCAN0.TMDF171.UINT32)
+#define RSCAN0TMDF171L (RSCAN0.TMDF171.UINT16[R_IO_L])
+#define RSCAN0TMDF171LL (RSCAN0.TMDF171.UINT8[R_IO_LL])
+#define RSCAN0TMDF171LH (RSCAN0.TMDF171.UINT8[R_IO_LH])
+#define RSCAN0TMDF171H (RSCAN0.TMDF171.UINT16[R_IO_H])
+#define RSCAN0TMDF171HL (RSCAN0.TMDF171.UINT8[R_IO_HL])
+#define RSCAN0TMDF171HH (RSCAN0.TMDF171.UINT8[R_IO_HH])
+#define RSCAN0TMID72 (RSCAN0.TMID72.UINT32)
+#define RSCAN0TMID72L (RSCAN0.TMID72.UINT16[R_IO_L])
+#define RSCAN0TMID72LL (RSCAN0.TMID72.UINT8[R_IO_LL])
+#define RSCAN0TMID72LH (RSCAN0.TMID72.UINT8[R_IO_LH])
+#define RSCAN0TMID72H (RSCAN0.TMID72.UINT16[R_IO_H])
+#define RSCAN0TMID72HL (RSCAN0.TMID72.UINT8[R_IO_HL])
+#define RSCAN0TMID72HH (RSCAN0.TMID72.UINT8[R_IO_HH])
+#define RSCAN0TMPTR72 (RSCAN0.TMPTR72.UINT32)
+#define RSCAN0TMPTR72L (RSCAN0.TMPTR72.UINT16[R_IO_L])
+#define RSCAN0TMPTR72LL (RSCAN0.TMPTR72.UINT8[R_IO_LL])
+#define RSCAN0TMPTR72LH (RSCAN0.TMPTR72.UINT8[R_IO_LH])
+#define RSCAN0TMPTR72H (RSCAN0.TMPTR72.UINT16[R_IO_H])
+#define RSCAN0TMPTR72HL (RSCAN0.TMPTR72.UINT8[R_IO_HL])
+#define RSCAN0TMPTR72HH (RSCAN0.TMPTR72.UINT8[R_IO_HH])
+#define RSCAN0TMDF072 (RSCAN0.TMDF072.UINT32)
+#define RSCAN0TMDF072L (RSCAN0.TMDF072.UINT16[R_IO_L])
+#define RSCAN0TMDF072LL (RSCAN0.TMDF072.UINT8[R_IO_LL])
+#define RSCAN0TMDF072LH (RSCAN0.TMDF072.UINT8[R_IO_LH])
+#define RSCAN0TMDF072H (RSCAN0.TMDF072.UINT16[R_IO_H])
+#define RSCAN0TMDF072HL (RSCAN0.TMDF072.UINT8[R_IO_HL])
+#define RSCAN0TMDF072HH (RSCAN0.TMDF072.UINT8[R_IO_HH])
+#define RSCAN0TMDF172 (RSCAN0.TMDF172.UINT32)
+#define RSCAN0TMDF172L (RSCAN0.TMDF172.UINT16[R_IO_L])
+#define RSCAN0TMDF172LL (RSCAN0.TMDF172.UINT8[R_IO_LL])
+#define RSCAN0TMDF172LH (RSCAN0.TMDF172.UINT8[R_IO_LH])
+#define RSCAN0TMDF172H (RSCAN0.TMDF172.UINT16[R_IO_H])
+#define RSCAN0TMDF172HL (RSCAN0.TMDF172.UINT8[R_IO_HL])
+#define RSCAN0TMDF172HH (RSCAN0.TMDF172.UINT8[R_IO_HH])
+#define RSCAN0TMID73 (RSCAN0.TMID73.UINT32)
+#define RSCAN0TMID73L (RSCAN0.TMID73.UINT16[R_IO_L])
+#define RSCAN0TMID73LL (RSCAN0.TMID73.UINT8[R_IO_LL])
+#define RSCAN0TMID73LH (RSCAN0.TMID73.UINT8[R_IO_LH])
+#define RSCAN0TMID73H (RSCAN0.TMID73.UINT16[R_IO_H])
+#define RSCAN0TMID73HL (RSCAN0.TMID73.UINT8[R_IO_HL])
+#define RSCAN0TMID73HH (RSCAN0.TMID73.UINT8[R_IO_HH])
+#define RSCAN0TMPTR73 (RSCAN0.TMPTR73.UINT32)
+#define RSCAN0TMPTR73L (RSCAN0.TMPTR73.UINT16[R_IO_L])
+#define RSCAN0TMPTR73LL (RSCAN0.TMPTR73.UINT8[R_IO_LL])
+#define RSCAN0TMPTR73LH (RSCAN0.TMPTR73.UINT8[R_IO_LH])
+#define RSCAN0TMPTR73H (RSCAN0.TMPTR73.UINT16[R_IO_H])
+#define RSCAN0TMPTR73HL (RSCAN0.TMPTR73.UINT8[R_IO_HL])
+#define RSCAN0TMPTR73HH (RSCAN0.TMPTR73.UINT8[R_IO_HH])
+#define RSCAN0TMDF073 (RSCAN0.TMDF073.UINT32)
+#define RSCAN0TMDF073L (RSCAN0.TMDF073.UINT16[R_IO_L])
+#define RSCAN0TMDF073LL (RSCAN0.TMDF073.UINT8[R_IO_LL])
+#define RSCAN0TMDF073LH (RSCAN0.TMDF073.UINT8[R_IO_LH])
+#define RSCAN0TMDF073H (RSCAN0.TMDF073.UINT16[R_IO_H])
+#define RSCAN0TMDF073HL (RSCAN0.TMDF073.UINT8[R_IO_HL])
+#define RSCAN0TMDF073HH (RSCAN0.TMDF073.UINT8[R_IO_HH])
+#define RSCAN0TMDF173 (RSCAN0.TMDF173.UINT32)
+#define RSCAN0TMDF173L (RSCAN0.TMDF173.UINT16[R_IO_L])
+#define RSCAN0TMDF173LL (RSCAN0.TMDF173.UINT8[R_IO_LL])
+#define RSCAN0TMDF173LH (RSCAN0.TMDF173.UINT8[R_IO_LH])
+#define RSCAN0TMDF173H (RSCAN0.TMDF173.UINT16[R_IO_H])
+#define RSCAN0TMDF173HL (RSCAN0.TMDF173.UINT8[R_IO_HL])
+#define RSCAN0TMDF173HH (RSCAN0.TMDF173.UINT8[R_IO_HH])
+#define RSCAN0TMID74 (RSCAN0.TMID74.UINT32)
+#define RSCAN0TMID74L (RSCAN0.TMID74.UINT16[R_IO_L])
+#define RSCAN0TMID74LL (RSCAN0.TMID74.UINT8[R_IO_LL])
+#define RSCAN0TMID74LH (RSCAN0.TMID74.UINT8[R_IO_LH])
+#define RSCAN0TMID74H (RSCAN0.TMID74.UINT16[R_IO_H])
+#define RSCAN0TMID74HL (RSCAN0.TMID74.UINT8[R_IO_HL])
+#define RSCAN0TMID74HH (RSCAN0.TMID74.UINT8[R_IO_HH])
+#define RSCAN0TMPTR74 (RSCAN0.TMPTR74.UINT32)
+#define RSCAN0TMPTR74L (RSCAN0.TMPTR74.UINT16[R_IO_L])
+#define RSCAN0TMPTR74LL (RSCAN0.TMPTR74.UINT8[R_IO_LL])
+#define RSCAN0TMPTR74LH (RSCAN0.TMPTR74.UINT8[R_IO_LH])
+#define RSCAN0TMPTR74H (RSCAN0.TMPTR74.UINT16[R_IO_H])
+#define RSCAN0TMPTR74HL (RSCAN0.TMPTR74.UINT8[R_IO_HL])
+#define RSCAN0TMPTR74HH (RSCAN0.TMPTR74.UINT8[R_IO_HH])
+#define RSCAN0TMDF074 (RSCAN0.TMDF074.UINT32)
+#define RSCAN0TMDF074L (RSCAN0.TMDF074.UINT16[R_IO_L])
+#define RSCAN0TMDF074LL (RSCAN0.TMDF074.UINT8[R_IO_LL])
+#define RSCAN0TMDF074LH (RSCAN0.TMDF074.UINT8[R_IO_LH])
+#define RSCAN0TMDF074H (RSCAN0.TMDF074.UINT16[R_IO_H])
+#define RSCAN0TMDF074HL (RSCAN0.TMDF074.UINT8[R_IO_HL])
+#define RSCAN0TMDF074HH (RSCAN0.TMDF074.UINT8[R_IO_HH])
+#define RSCAN0TMDF174 (RSCAN0.TMDF174.UINT32)
+#define RSCAN0TMDF174L (RSCAN0.TMDF174.UINT16[R_IO_L])
+#define RSCAN0TMDF174LL (RSCAN0.TMDF174.UINT8[R_IO_LL])
+#define RSCAN0TMDF174LH (RSCAN0.TMDF174.UINT8[R_IO_LH])
+#define RSCAN0TMDF174H (RSCAN0.TMDF174.UINT16[R_IO_H])
+#define RSCAN0TMDF174HL (RSCAN0.TMDF174.UINT8[R_IO_HL])
+#define RSCAN0TMDF174HH (RSCAN0.TMDF174.UINT8[R_IO_HH])
+#define RSCAN0TMID75 (RSCAN0.TMID75.UINT32)
+#define RSCAN0TMID75L (RSCAN0.TMID75.UINT16[R_IO_L])
+#define RSCAN0TMID75LL (RSCAN0.TMID75.UINT8[R_IO_LL])
+#define RSCAN0TMID75LH (RSCAN0.TMID75.UINT8[R_IO_LH])
+#define RSCAN0TMID75H (RSCAN0.TMID75.UINT16[R_IO_H])
+#define RSCAN0TMID75HL (RSCAN0.TMID75.UINT8[R_IO_HL])
+#define RSCAN0TMID75HH (RSCAN0.TMID75.UINT8[R_IO_HH])
+#define RSCAN0TMPTR75 (RSCAN0.TMPTR75.UINT32)
+#define RSCAN0TMPTR75L (RSCAN0.TMPTR75.UINT16[R_IO_L])
+#define RSCAN0TMPTR75LL (RSCAN0.TMPTR75.UINT8[R_IO_LL])
+#define RSCAN0TMPTR75LH (RSCAN0.TMPTR75.UINT8[R_IO_LH])
+#define RSCAN0TMPTR75H (RSCAN0.TMPTR75.UINT16[R_IO_H])
+#define RSCAN0TMPTR75HL (RSCAN0.TMPTR75.UINT8[R_IO_HL])
+#define RSCAN0TMPTR75HH (RSCAN0.TMPTR75.UINT8[R_IO_HH])
+#define RSCAN0TMDF075 (RSCAN0.TMDF075.UINT32)
+#define RSCAN0TMDF075L (RSCAN0.TMDF075.UINT16[R_IO_L])
+#define RSCAN0TMDF075LL (RSCAN0.TMDF075.UINT8[R_IO_LL])
+#define RSCAN0TMDF075LH (RSCAN0.TMDF075.UINT8[R_IO_LH])
+#define RSCAN0TMDF075H (RSCAN0.TMDF075.UINT16[R_IO_H])
+#define RSCAN0TMDF075HL (RSCAN0.TMDF075.UINT8[R_IO_HL])
+#define RSCAN0TMDF075HH (RSCAN0.TMDF075.UINT8[R_IO_HH])
+#define RSCAN0TMDF175 (RSCAN0.TMDF175.UINT32)
+#define RSCAN0TMDF175L (RSCAN0.TMDF175.UINT16[R_IO_L])
+#define RSCAN0TMDF175LL (RSCAN0.TMDF175.UINT8[R_IO_LL])
+#define RSCAN0TMDF175LH (RSCAN0.TMDF175.UINT8[R_IO_LH])
+#define RSCAN0TMDF175H (RSCAN0.TMDF175.UINT16[R_IO_H])
+#define RSCAN0TMDF175HL (RSCAN0.TMDF175.UINT8[R_IO_HL])
+#define RSCAN0TMDF175HH (RSCAN0.TMDF175.UINT8[R_IO_HH])
+#define RSCAN0TMID76 (RSCAN0.TMID76.UINT32)
+#define RSCAN0TMID76L (RSCAN0.TMID76.UINT16[R_IO_L])
+#define RSCAN0TMID76LL (RSCAN0.TMID76.UINT8[R_IO_LL])
+#define RSCAN0TMID76LH (RSCAN0.TMID76.UINT8[R_IO_LH])
+#define RSCAN0TMID76H (RSCAN0.TMID76.UINT16[R_IO_H])
+#define RSCAN0TMID76HL (RSCAN0.TMID76.UINT8[R_IO_HL])
+#define RSCAN0TMID76HH (RSCAN0.TMID76.UINT8[R_IO_HH])
+#define RSCAN0TMPTR76 (RSCAN0.TMPTR76.UINT32)
+#define RSCAN0TMPTR76L (RSCAN0.TMPTR76.UINT16[R_IO_L])
+#define RSCAN0TMPTR76LL (RSCAN0.TMPTR76.UINT8[R_IO_LL])
+#define RSCAN0TMPTR76LH (RSCAN0.TMPTR76.UINT8[R_IO_LH])
+#define RSCAN0TMPTR76H (RSCAN0.TMPTR76.UINT16[R_IO_H])
+#define RSCAN0TMPTR76HL (RSCAN0.TMPTR76.UINT8[R_IO_HL])
+#define RSCAN0TMPTR76HH (RSCAN0.TMPTR76.UINT8[R_IO_HH])
+#define RSCAN0TMDF076 (RSCAN0.TMDF076.UINT32)
+#define RSCAN0TMDF076L (RSCAN0.TMDF076.UINT16[R_IO_L])
+#define RSCAN0TMDF076LL (RSCAN0.TMDF076.UINT8[R_IO_LL])
+#define RSCAN0TMDF076LH (RSCAN0.TMDF076.UINT8[R_IO_LH])
+#define RSCAN0TMDF076H (RSCAN0.TMDF076.UINT16[R_IO_H])
+#define RSCAN0TMDF076HL (RSCAN0.TMDF076.UINT8[R_IO_HL])
+#define RSCAN0TMDF076HH (RSCAN0.TMDF076.UINT8[R_IO_HH])
+#define RSCAN0TMDF176 (RSCAN0.TMDF176.UINT32)
+#define RSCAN0TMDF176L (RSCAN0.TMDF176.UINT16[R_IO_L])
+#define RSCAN0TMDF176LL (RSCAN0.TMDF176.UINT8[R_IO_LL])
+#define RSCAN0TMDF176LH (RSCAN0.TMDF176.UINT8[R_IO_LH])
+#define RSCAN0TMDF176H (RSCAN0.TMDF176.UINT16[R_IO_H])
+#define RSCAN0TMDF176HL (RSCAN0.TMDF176.UINT8[R_IO_HL])
+#define RSCAN0TMDF176HH (RSCAN0.TMDF176.UINT8[R_IO_HH])
+#define RSCAN0TMID77 (RSCAN0.TMID77.UINT32)
+#define RSCAN0TMID77L (RSCAN0.TMID77.UINT16[R_IO_L])
+#define RSCAN0TMID77LL (RSCAN0.TMID77.UINT8[R_IO_LL])
+#define RSCAN0TMID77LH (RSCAN0.TMID77.UINT8[R_IO_LH])
+#define RSCAN0TMID77H (RSCAN0.TMID77.UINT16[R_IO_H])
+#define RSCAN0TMID77HL (RSCAN0.TMID77.UINT8[R_IO_HL])
+#define RSCAN0TMID77HH (RSCAN0.TMID77.UINT8[R_IO_HH])
+#define RSCAN0TMPTR77 (RSCAN0.TMPTR77.UINT32)
+#define RSCAN0TMPTR77L (RSCAN0.TMPTR77.UINT16[R_IO_L])
+#define RSCAN0TMPTR77LL (RSCAN0.TMPTR77.UINT8[R_IO_LL])
+#define RSCAN0TMPTR77LH (RSCAN0.TMPTR77.UINT8[R_IO_LH])
+#define RSCAN0TMPTR77H (RSCAN0.TMPTR77.UINT16[R_IO_H])
+#define RSCAN0TMPTR77HL (RSCAN0.TMPTR77.UINT8[R_IO_HL])
+#define RSCAN0TMPTR77HH (RSCAN0.TMPTR77.UINT8[R_IO_HH])
+#define RSCAN0TMDF077 (RSCAN0.TMDF077.UINT32)
+#define RSCAN0TMDF077L (RSCAN0.TMDF077.UINT16[R_IO_L])
+#define RSCAN0TMDF077LL (RSCAN0.TMDF077.UINT8[R_IO_LL])
+#define RSCAN0TMDF077LH (RSCAN0.TMDF077.UINT8[R_IO_LH])
+#define RSCAN0TMDF077H (RSCAN0.TMDF077.UINT16[R_IO_H])
+#define RSCAN0TMDF077HL (RSCAN0.TMDF077.UINT8[R_IO_HL])
+#define RSCAN0TMDF077HH (RSCAN0.TMDF077.UINT8[R_IO_HH])
+#define RSCAN0TMDF177 (RSCAN0.TMDF177.UINT32)
+#define RSCAN0TMDF177L (RSCAN0.TMDF177.UINT16[R_IO_L])
+#define RSCAN0TMDF177LL (RSCAN0.TMDF177.UINT8[R_IO_LL])
+#define RSCAN0TMDF177LH (RSCAN0.TMDF177.UINT8[R_IO_LH])
+#define RSCAN0TMDF177H (RSCAN0.TMDF177.UINT16[R_IO_H])
+#define RSCAN0TMDF177HL (RSCAN0.TMDF177.UINT8[R_IO_HL])
+#define RSCAN0TMDF177HH (RSCAN0.TMDF177.UINT8[R_IO_HH])
+#define RSCAN0TMID78 (RSCAN0.TMID78.UINT32)
+#define RSCAN0TMID78L (RSCAN0.TMID78.UINT16[R_IO_L])
+#define RSCAN0TMID78LL (RSCAN0.TMID78.UINT8[R_IO_LL])
+#define RSCAN0TMID78LH (RSCAN0.TMID78.UINT8[R_IO_LH])
+#define RSCAN0TMID78H (RSCAN0.TMID78.UINT16[R_IO_H])
+#define RSCAN0TMID78HL (RSCAN0.TMID78.UINT8[R_IO_HL])
+#define RSCAN0TMID78HH (RSCAN0.TMID78.UINT8[R_IO_HH])
+#define RSCAN0TMPTR78 (RSCAN0.TMPTR78.UINT32)
+#define RSCAN0TMPTR78L (RSCAN0.TMPTR78.UINT16[R_IO_L])
+#define RSCAN0TMPTR78LL (RSCAN0.TMPTR78.UINT8[R_IO_LL])
+#define RSCAN0TMPTR78LH (RSCAN0.TMPTR78.UINT8[R_IO_LH])
+#define RSCAN0TMPTR78H (RSCAN0.TMPTR78.UINT16[R_IO_H])
+#define RSCAN0TMPTR78HL (RSCAN0.TMPTR78.UINT8[R_IO_HL])
+#define RSCAN0TMPTR78HH (RSCAN0.TMPTR78.UINT8[R_IO_HH])
+#define RSCAN0TMDF078 (RSCAN0.TMDF078.UINT32)
+#define RSCAN0TMDF078L (RSCAN0.TMDF078.UINT16[R_IO_L])
+#define RSCAN0TMDF078LL (RSCAN0.TMDF078.UINT8[R_IO_LL])
+#define RSCAN0TMDF078LH (RSCAN0.TMDF078.UINT8[R_IO_LH])
+#define RSCAN0TMDF078H (RSCAN0.TMDF078.UINT16[R_IO_H])
+#define RSCAN0TMDF078HL (RSCAN0.TMDF078.UINT8[R_IO_HL])
+#define RSCAN0TMDF078HH (RSCAN0.TMDF078.UINT8[R_IO_HH])
+#define RSCAN0TMDF178 (RSCAN0.TMDF178.UINT32)
+#define RSCAN0TMDF178L (RSCAN0.TMDF178.UINT16[R_IO_L])
+#define RSCAN0TMDF178LL (RSCAN0.TMDF178.UINT8[R_IO_LL])
+#define RSCAN0TMDF178LH (RSCAN0.TMDF178.UINT8[R_IO_LH])
+#define RSCAN0TMDF178H (RSCAN0.TMDF178.UINT16[R_IO_H])
+#define RSCAN0TMDF178HL (RSCAN0.TMDF178.UINT8[R_IO_HL])
+#define RSCAN0TMDF178HH (RSCAN0.TMDF178.UINT8[R_IO_HH])
+#define RSCAN0TMID79 (RSCAN0.TMID79.UINT32)
+#define RSCAN0TMID79L (RSCAN0.TMID79.UINT16[R_IO_L])
+#define RSCAN0TMID79LL (RSCAN0.TMID79.UINT8[R_IO_LL])
+#define RSCAN0TMID79LH (RSCAN0.TMID79.UINT8[R_IO_LH])
+#define RSCAN0TMID79H (RSCAN0.TMID79.UINT16[R_IO_H])
+#define RSCAN0TMID79HL (RSCAN0.TMID79.UINT8[R_IO_HL])
+#define RSCAN0TMID79HH (RSCAN0.TMID79.UINT8[R_IO_HH])
+#define RSCAN0TMPTR79 (RSCAN0.TMPTR79.UINT32)
+#define RSCAN0TMPTR79L (RSCAN0.TMPTR79.UINT16[R_IO_L])
+#define RSCAN0TMPTR79LL (RSCAN0.TMPTR79.UINT8[R_IO_LL])
+#define RSCAN0TMPTR79LH (RSCAN0.TMPTR79.UINT8[R_IO_LH])
+#define RSCAN0TMPTR79H (RSCAN0.TMPTR79.UINT16[R_IO_H])
+#define RSCAN0TMPTR79HL (RSCAN0.TMPTR79.UINT8[R_IO_HL])
+#define RSCAN0TMPTR79HH (RSCAN0.TMPTR79.UINT8[R_IO_HH])
+#define RSCAN0TMDF079 (RSCAN0.TMDF079.UINT32)
+#define RSCAN0TMDF079L (RSCAN0.TMDF079.UINT16[R_IO_L])
+#define RSCAN0TMDF079LL (RSCAN0.TMDF079.UINT8[R_IO_LL])
+#define RSCAN0TMDF079LH (RSCAN0.TMDF079.UINT8[R_IO_LH])
+#define RSCAN0TMDF079H (RSCAN0.TMDF079.UINT16[R_IO_H])
+#define RSCAN0TMDF079HL (RSCAN0.TMDF079.UINT8[R_IO_HL])
+#define RSCAN0TMDF079HH (RSCAN0.TMDF079.UINT8[R_IO_HH])
+#define RSCAN0TMDF179 (RSCAN0.TMDF179.UINT32)
+#define RSCAN0TMDF179L (RSCAN0.TMDF179.UINT16[R_IO_L])
+#define RSCAN0TMDF179LL (RSCAN0.TMDF179.UINT8[R_IO_LL])
+#define RSCAN0TMDF179LH (RSCAN0.TMDF179.UINT8[R_IO_LH])
+#define RSCAN0TMDF179H (RSCAN0.TMDF179.UINT16[R_IO_H])
+#define RSCAN0TMDF179HL (RSCAN0.TMDF179.UINT8[R_IO_HL])
+#define RSCAN0TMDF179HH (RSCAN0.TMDF179.UINT8[R_IO_HH])
+#define RSCAN0THLACC0 (RSCAN0.THLACC0.UINT32)
+#define RSCAN0THLACC0L (RSCAN0.THLACC0.UINT16[R_IO_L])
+#define RSCAN0THLACC0LL (RSCAN0.THLACC0.UINT8[R_IO_LL])
+#define RSCAN0THLACC0LH (RSCAN0.THLACC0.UINT8[R_IO_LH])
+#define RSCAN0THLACC0H (RSCAN0.THLACC0.UINT16[R_IO_H])
+#define RSCAN0THLACC0HL (RSCAN0.THLACC0.UINT8[R_IO_HL])
+#define RSCAN0THLACC0HH (RSCAN0.THLACC0.UINT8[R_IO_HH])
+#define RSCAN0THLACC1 (RSCAN0.THLACC1.UINT32)
+#define RSCAN0THLACC1L (RSCAN0.THLACC1.UINT16[R_IO_L])
+#define RSCAN0THLACC1LL (RSCAN0.THLACC1.UINT8[R_IO_LL])
+#define RSCAN0THLACC1LH (RSCAN0.THLACC1.UINT8[R_IO_LH])
+#define RSCAN0THLACC1H (RSCAN0.THLACC1.UINT16[R_IO_H])
+#define RSCAN0THLACC1HL (RSCAN0.THLACC1.UINT8[R_IO_HL])
+#define RSCAN0THLACC1HH (RSCAN0.THLACC1.UINT8[R_IO_HH])
+#define RSCAN0THLACC2 (RSCAN0.THLACC2.UINT32)
+#define RSCAN0THLACC2L (RSCAN0.THLACC2.UINT16[R_IO_L])
+#define RSCAN0THLACC2LL (RSCAN0.THLACC2.UINT8[R_IO_LL])
+#define RSCAN0THLACC2LH (RSCAN0.THLACC2.UINT8[R_IO_LH])
+#define RSCAN0THLACC2H (RSCAN0.THLACC2.UINT16[R_IO_H])
+#define RSCAN0THLACC2HL (RSCAN0.THLACC2.UINT8[R_IO_HL])
+#define RSCAN0THLACC2HH (RSCAN0.THLACC2.UINT8[R_IO_HH])
+#define RSCAN0THLACC3 (RSCAN0.THLACC3.UINT32)
+#define RSCAN0THLACC3L (RSCAN0.THLACC3.UINT16[R_IO_L])
+#define RSCAN0THLACC3LL (RSCAN0.THLACC3.UINT8[R_IO_LL])
+#define RSCAN0THLACC3LH (RSCAN0.THLACC3.UINT8[R_IO_LH])
+#define RSCAN0THLACC3H (RSCAN0.THLACC3.UINT16[R_IO_H])
+#define RSCAN0THLACC3HL (RSCAN0.THLACC3.UINT8[R_IO_HL])
+#define RSCAN0THLACC3HH (RSCAN0.THLACC3.UINT8[R_IO_HH])
+#define RSCAN0THLACC4 (RSCAN0.THLACC4.UINT32)
+#define RSCAN0THLACC4L (RSCAN0.THLACC4.UINT16[R_IO_L])
+#define RSCAN0THLACC4LL (RSCAN0.THLACC4.UINT8[R_IO_LL])
+#define RSCAN0THLACC4LH (RSCAN0.THLACC4.UINT8[R_IO_LH])
+#define RSCAN0THLACC4H (RSCAN0.THLACC4.UINT16[R_IO_H])
+#define RSCAN0THLACC4HL (RSCAN0.THLACC4.UINT8[R_IO_HL])
+#define RSCAN0THLACC4HH (RSCAN0.THLACC4.UINT8[R_IO_HH])
+
+#define RSCAN0_GAFLCFG0_COUNT (2)
+#define RSCAN0_RMND0_COUNT (3)
+#define RSCAN0_RFCC0_COUNT (8)
+#define RSCAN0_RFSTS0_COUNT (8)
+#define RSCAN0_RFPCTR0_COUNT (8)
+#define RSCAN0_CFCC0_COUNT (15)
+#define RSCAN0_CFSTS0_COUNT (15)
+#define RSCAN0_CFPCTR0_COUNT (15)
+#define RSCAN0_TMC0_COUNT (80)
+#define RSCAN0_TMSTS0_COUNT (80)
+#define RSCAN0_TMTRSTS0_COUNT (3)
+#define RSCAN0_TMTARSTS0_COUNT (3)
+#define RSCAN0_TMTCSTS0_COUNT (3)
+#define RSCAN0_TMTASTS0_COUNT (3)
+#define RSCAN0_TMIEC0_COUNT (3)
+#define RSCAN0_TXQCC0_COUNT (5)
+#define RSCAN0_TXQSTS0_COUNT (5)
+#define RSCAN0_TXQPCTR0_COUNT (5)
+#define RSCAN0_THLCC0_COUNT (5)
+#define RSCAN0_THLSTS0_COUNT (5)
+#define RSCAN0_THLPCTR0_COUNT (5)
+#define RSCAN0_GTINTSTS0_COUNT (2)
+#define RSCAN0_THLACC0_COUNT (5)
+
+
+typedef struct st_rscan0
+{
+                                                           /* RSCAN0           */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C0CFG;                         /*  C0CFG           */
+    union iodefine_reg32_t  C0CTR;                         /*  C0CTR           */
+    union iodefine_reg32_t  C0STS;                         /*  C0STS           */
+    union iodefine_reg32_t  C0ERFL;                        /*  C0ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C1CFG;                         /*  C1CFG           */
+    union iodefine_reg32_t  C1CTR;                         /*  C1CTR           */
+    union iodefine_reg32_t  C1STS;                         /*  C1STS           */
+    union iodefine_reg32_t  C1ERFL;                        /*  C1ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C2CFG;                         /*  C2CFG           */
+    union iodefine_reg32_t  C2CTR;                         /*  C2CTR           */
+    union iodefine_reg32_t  C2STS;                         /*  C2STS           */
+    union iodefine_reg32_t  C2ERFL;                        /*  C2ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C3CFG;                         /*  C3CFG           */
+    union iodefine_reg32_t  C3CTR;                         /*  C3CTR           */
+    union iodefine_reg32_t  C3STS;                         /*  C3STS           */
+    union iodefine_reg32_t  C3ERFL;                        /*  C3ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C4CFG;                         /*  C4CFG           */
+    union iodefine_reg32_t  C4CTR;                         /*  C4CTR           */
+    union iodefine_reg32_t  C4STS;                         /*  C4STS           */
+    union iodefine_reg32_t  C4ERFL;                        /*  C4ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+    volatile uint8_t   dummy159[52];                           /*                  */
+    union iodefine_reg32_t  GCFG;                          /*  GCFG            */
+    union iodefine_reg32_t  GCTR;                          /*  GCTR            */
+    union iodefine_reg32_t  GSTS;                          /*  GSTS            */
+    union iodefine_reg32_t  GERFL;                         /*  GERFL           */
+    union iodefine_reg32_16_t  GTSC;                       /*  GTSC            */
+    union iodefine_reg32_t  GAFLECTR;                      /*  GAFLECTR        */
+
+/* #define RSCAN0_GAFLCFG0_COUNT (2) */
+    union iodefine_reg32_t  GAFLCFG0;                      /*  GAFLCFG0        */
+    union iodefine_reg32_t  GAFLCFG1;                      /*  GAFLCFG1        */
+    union iodefine_reg32_t  RMNB;                          /*  RMNB            */
+
+/* #define RSCAN0_RMND0_COUNT (3) */
+    union iodefine_reg32_t  RMND0;                         /*  RMND0           */
+    union iodefine_reg32_t  RMND1;                         /*  RMND1           */
+    union iodefine_reg32_t  RMND2;                         /*  RMND2           */
+    
+    volatile uint8_t   dummy160[4];                            /*                  */
+
+/* #define RSCAN0_RFCC0_COUNT (8) */
+    union iodefine_reg32_t  RFCC0;                         /*  RFCC0           */
+    union iodefine_reg32_t  RFCC1;                         /*  RFCC1           */
+    union iodefine_reg32_t  RFCC2;                         /*  RFCC2           */
+    union iodefine_reg32_t  RFCC3;                         /*  RFCC3           */
+    union iodefine_reg32_t  RFCC4;                         /*  RFCC4           */
+    union iodefine_reg32_t  RFCC5;                         /*  RFCC5           */
+    union iodefine_reg32_t  RFCC6;                         /*  RFCC6           */
+    union iodefine_reg32_t  RFCC7;                         /*  RFCC7           */
+
+/* #define RSCAN0_RFSTS0_COUNT (8) */
+    union iodefine_reg32_t  RFSTS0;                        /*  RFSTS0          */
+    union iodefine_reg32_t  RFSTS1;                        /*  RFSTS1          */
+    union iodefine_reg32_t  RFSTS2;                        /*  RFSTS2          */
+    union iodefine_reg32_t  RFSTS3;                        /*  RFSTS3          */
+    union iodefine_reg32_t  RFSTS4;                        /*  RFSTS4          */
+    union iodefine_reg32_t  RFSTS5;                        /*  RFSTS5          */
+    union iodefine_reg32_t  RFSTS6;                        /*  RFSTS6          */
+    union iodefine_reg32_t  RFSTS7;                        /*  RFSTS7          */
+
+/* #define RSCAN0_RFPCTR0_COUNT (8) */
+    union iodefine_reg32_t  RFPCTR0;                       /*  RFPCTR0         */
+    union iodefine_reg32_t  RFPCTR1;                       /*  RFPCTR1         */
+    union iodefine_reg32_t  RFPCTR2;                       /*  RFPCTR2         */
+    union iodefine_reg32_t  RFPCTR3;                       /*  RFPCTR3         */
+    union iodefine_reg32_t  RFPCTR4;                       /*  RFPCTR4         */
+    union iodefine_reg32_t  RFPCTR5;                       /*  RFPCTR5         */
+    union iodefine_reg32_t  RFPCTR6;                       /*  RFPCTR6         */
+    union iodefine_reg32_t  RFPCTR7;                       /*  RFPCTR7         */
+
+/* #define RSCAN0_CFCC0_COUNT (15) */
+    union iodefine_reg32_t  CFCC0;                         /*  CFCC0           */
+    union iodefine_reg32_t  CFCC1;                         /*  CFCC1           */
+    union iodefine_reg32_t  CFCC2;                         /*  CFCC2           */
+    union iodefine_reg32_t  CFCC3;                         /*  CFCC3           */
+    union iodefine_reg32_t  CFCC4;                         /*  CFCC4           */
+    union iodefine_reg32_t  CFCC5;                         /*  CFCC5           */
+    union iodefine_reg32_t  CFCC6;                         /*  CFCC6           */
+    union iodefine_reg32_t  CFCC7;                         /*  CFCC7           */
+    union iodefine_reg32_t  CFCC8;                         /*  CFCC8           */
+    union iodefine_reg32_t  CFCC9;                         /*  CFCC9           */
+    union iodefine_reg32_t  CFCC10;                        /*  CFCC10          */
+    union iodefine_reg32_t  CFCC11;                        /*  CFCC11          */
+    union iodefine_reg32_t  CFCC12;                        /*  CFCC12          */
+    union iodefine_reg32_t  CFCC13;                        /*  CFCC13          */
+    union iodefine_reg32_t  CFCC14;                        /*  CFCC14          */
+    
+    volatile uint8_t   dummy161[36];                           /*                  */
+
+/* #define RSCAN0_CFSTS0_COUNT (15) */
+    union iodefine_reg32_t  CFSTS0;                        /*  CFSTS0          */
+    union iodefine_reg32_t  CFSTS1;                        /*  CFSTS1          */
+    union iodefine_reg32_t  CFSTS2;                        /*  CFSTS2          */
+    union iodefine_reg32_t  CFSTS3;                        /*  CFSTS3          */
+    union iodefine_reg32_t  CFSTS4;                        /*  CFSTS4          */
+    union iodefine_reg32_t  CFSTS5;                        /*  CFSTS5          */
+    union iodefine_reg32_t  CFSTS6;                        /*  CFSTS6          */
+    union iodefine_reg32_t  CFSTS7;                        /*  CFSTS7          */
+    union iodefine_reg32_t  CFSTS8;                        /*  CFSTS8          */
+    union iodefine_reg32_t  CFSTS9;                        /*  CFSTS9          */
+    union iodefine_reg32_t  CFSTS10;                       /*  CFSTS10         */
+    union iodefine_reg32_t  CFSTS11;                       /*  CFSTS11         */
+    union iodefine_reg32_t  CFSTS12;                       /*  CFSTS12         */
+    union iodefine_reg32_t  CFSTS13;                       /*  CFSTS13         */
+    union iodefine_reg32_t  CFSTS14;                       /*  CFSTS14         */
+    
+    volatile uint8_t   dummy162[36];                           /*                  */
+
+/* #define RSCAN0_CFPCTR0_COUNT (15) */
+    union iodefine_reg32_t  CFPCTR0;                       /*  CFPCTR0         */
+    union iodefine_reg32_t  CFPCTR1;                       /*  CFPCTR1         */
+    union iodefine_reg32_t  CFPCTR2;                       /*  CFPCTR2         */
+    union iodefine_reg32_t  CFPCTR3;                       /*  CFPCTR3         */
+    union iodefine_reg32_t  CFPCTR4;                       /*  CFPCTR4         */
+    union iodefine_reg32_t  CFPCTR5;                       /*  CFPCTR5         */
+    union iodefine_reg32_t  CFPCTR6;                       /*  CFPCTR6         */
+    union iodefine_reg32_t  CFPCTR7;                       /*  CFPCTR7         */
+    union iodefine_reg32_t  CFPCTR8;                       /*  CFPCTR8         */
+    union iodefine_reg32_t  CFPCTR9;                       /*  CFPCTR9         */
+    union iodefine_reg32_t  CFPCTR10;                      /*  CFPCTR10        */
+    union iodefine_reg32_t  CFPCTR11;                      /*  CFPCTR11        */
+    union iodefine_reg32_t  CFPCTR12;                      /*  CFPCTR12        */
+    union iodefine_reg32_t  CFPCTR13;                      /*  CFPCTR13        */
+    union iodefine_reg32_t  CFPCTR14;                      /*  CFPCTR14        */
+    
+    volatile uint8_t   dummy163[36];                           /*                  */
+    union iodefine_reg32_t  FESTS;                         /*  FESTS           */
+    union iodefine_reg32_t  FFSTS;                         /*  FFSTS           */
+    union iodefine_reg32_t  FMSTS;                         /*  FMSTS           */
+    union iodefine_reg32_t  RFISTS;                        /*  RFISTS          */
+    union iodefine_reg32_t  CFRISTS;                       /*  CFRISTS         */
+    union iodefine_reg32_t  CFTISTS;                       /*  CFTISTS         */
+    
+
+/* #define RSCAN0_TMC0_COUNT (80) */
+    volatile uint8_t   TMC0;                                   /*  TMC0            */
+    volatile uint8_t   TMC1;                                   /*  TMC1            */
+    volatile uint8_t   TMC2;                                   /*  TMC2            */
+    volatile uint8_t   TMC3;                                   /*  TMC3            */
+    volatile uint8_t   TMC4;                                   /*  TMC4            */
+    volatile uint8_t   TMC5;                                   /*  TMC5            */
+    volatile uint8_t   TMC6;                                   /*  TMC6            */
+    volatile uint8_t   TMC7;                                   /*  TMC7            */
+    volatile uint8_t   TMC8;                                   /*  TMC8            */
+    volatile uint8_t   TMC9;                                   /*  TMC9            */
+    volatile uint8_t   TMC10;                                  /*  TMC10           */
+    volatile uint8_t   TMC11;                                  /*  TMC11           */
+    volatile uint8_t   TMC12;                                  /*  TMC12           */
+    volatile uint8_t   TMC13;                                  /*  TMC13           */
+    volatile uint8_t   TMC14;                                  /*  TMC14           */
+    volatile uint8_t   TMC15;                                  /*  TMC15           */
+    volatile uint8_t   TMC16;                                  /*  TMC16           */
+    volatile uint8_t   TMC17;                                  /*  TMC17           */
+    volatile uint8_t   TMC18;                                  /*  TMC18           */
+    volatile uint8_t   TMC19;                                  /*  TMC19           */
+    volatile uint8_t   TMC20;                                  /*  TMC20           */
+    volatile uint8_t   TMC21;                                  /*  TMC21           */
+    volatile uint8_t   TMC22;                                  /*  TMC22           */
+    volatile uint8_t   TMC23;                                  /*  TMC23           */
+    volatile uint8_t   TMC24;                                  /*  TMC24           */
+    volatile uint8_t   TMC25;                                  /*  TMC25           */
+    volatile uint8_t   TMC26;                                  /*  TMC26           */
+    volatile uint8_t   TMC27;                                  /*  TMC27           */
+    volatile uint8_t   TMC28;                                  /*  TMC28           */
+    volatile uint8_t   TMC29;                                  /*  TMC29           */
+    volatile uint8_t   TMC30;                                  /*  TMC30           */
+    volatile uint8_t   TMC31;                                  /*  TMC31           */
+    volatile uint8_t   TMC32;                                  /*  TMC32           */
+    volatile uint8_t   TMC33;                                  /*  TMC33           */
+    volatile uint8_t   TMC34;                                  /*  TMC34           */
+    volatile uint8_t   TMC35;                                  /*  TMC35           */
+    volatile uint8_t   TMC36;                                  /*  TMC36           */
+    volatile uint8_t   TMC37;                                  /*  TMC37           */
+    volatile uint8_t   TMC38;                                  /*  TMC38           */
+    volatile uint8_t   TMC39;                                  /*  TMC39           */
+    volatile uint8_t   TMC40;                                  /*  TMC40           */
+    volatile uint8_t   TMC41;                                  /*  TMC41           */
+    volatile uint8_t   TMC42;                                  /*  TMC42           */
+    volatile uint8_t   TMC43;                                  /*  TMC43           */
+    volatile uint8_t   TMC44;                                  /*  TMC44           */
+    volatile uint8_t   TMC45;                                  /*  TMC45           */
+    volatile uint8_t   TMC46;                                  /*  TMC46           */
+    volatile uint8_t   TMC47;                                  /*  TMC47           */
+    volatile uint8_t   TMC48;                                  /*  TMC48           */
+    volatile uint8_t   TMC49;                                  /*  TMC49           */
+    volatile uint8_t   TMC50;                                  /*  TMC50           */
+    volatile uint8_t   TMC51;                                  /*  TMC51           */
+    volatile uint8_t   TMC52;                                  /*  TMC52           */
+    volatile uint8_t   TMC53;                                  /*  TMC53           */
+    volatile uint8_t   TMC54;                                  /*  TMC54           */
+    volatile uint8_t   TMC55;                                  /*  TMC55           */
+    volatile uint8_t   TMC56;                                  /*  TMC56           */
+    volatile uint8_t   TMC57;                                  /*  TMC57           */
+    volatile uint8_t   TMC58;                                  /*  TMC58           */
+    volatile uint8_t   TMC59;                                  /*  TMC59           */
+    volatile uint8_t   TMC60;                                  /*  TMC60           */
+    volatile uint8_t   TMC61;                                  /*  TMC61           */
+    volatile uint8_t   TMC62;                                  /*  TMC62           */
+    volatile uint8_t   TMC63;                                  /*  TMC63           */
+    volatile uint8_t   TMC64;                                  /*  TMC64           */
+    volatile uint8_t   TMC65;                                  /*  TMC65           */
+    volatile uint8_t   TMC66;                                  /*  TMC66           */
+    volatile uint8_t   TMC67;                                  /*  TMC67           */
+    volatile uint8_t   TMC68;                                  /*  TMC68           */
+    volatile uint8_t   TMC69;                                  /*  TMC69           */
+    volatile uint8_t   TMC70;                                  /*  TMC70           */
+    volatile uint8_t   TMC71;                                  /*  TMC71           */
+    volatile uint8_t   TMC72;                                  /*  TMC72           */
+    volatile uint8_t   TMC73;                                  /*  TMC73           */
+    volatile uint8_t   TMC74;                                  /*  TMC74           */
+    volatile uint8_t   TMC75;                                  /*  TMC75           */
+    volatile uint8_t   TMC76;                                  /*  TMC76           */
+    volatile uint8_t   TMC77;                                  /*  TMC77           */
+    volatile uint8_t   TMC78;                                  /*  TMC78           */
+    volatile uint8_t   TMC79;                                  /*  TMC79           */
+    volatile uint8_t   dummy164[48];                           /*                  */
+
+/* #define RSCAN0_TMSTS0_COUNT (80) */
+    volatile uint8_t   TMSTS0;                                 /*  TMSTS0          */
+    volatile uint8_t   TMSTS1;                                 /*  TMSTS1          */
+    volatile uint8_t   TMSTS2;                                 /*  TMSTS2          */
+    volatile uint8_t   TMSTS3;                                 /*  TMSTS3          */
+    volatile uint8_t   TMSTS4;                                 /*  TMSTS4          */
+    volatile uint8_t   TMSTS5;                                 /*  TMSTS5          */
+    volatile uint8_t   TMSTS6;                                 /*  TMSTS6          */
+    volatile uint8_t   TMSTS7;                                 /*  TMSTS7          */
+    volatile uint8_t   TMSTS8;                                 /*  TMSTS8          */
+    volatile uint8_t   TMSTS9;                                 /*  TMSTS9          */
+    volatile uint8_t   TMSTS10;                                /*  TMSTS10         */
+    volatile uint8_t   TMSTS11;                                /*  TMSTS11         */
+    volatile uint8_t   TMSTS12;                                /*  TMSTS12         */
+    volatile uint8_t   TMSTS13;                                /*  TMSTS13         */
+    volatile uint8_t   TMSTS14;                                /*  TMSTS14         */
+    volatile uint8_t   TMSTS15;                                /*  TMSTS15         */
+    volatile uint8_t   TMSTS16;                                /*  TMSTS16         */
+    volatile uint8_t   TMSTS17;                                /*  TMSTS17         */
+    volatile uint8_t   TMSTS18;                                /*  TMSTS18         */
+    volatile uint8_t   TMSTS19;                                /*  TMSTS19         */
+    volatile uint8_t   TMSTS20;                                /*  TMSTS20         */
+    volatile uint8_t   TMSTS21;                                /*  TMSTS21         */
+    volatile uint8_t   TMSTS22;                                /*  TMSTS22         */
+    volatile uint8_t   TMSTS23;                                /*  TMSTS23         */
+    volatile uint8_t   TMSTS24;                                /*  TMSTS24         */
+    volatile uint8_t   TMSTS25;                                /*  TMSTS25         */
+    volatile uint8_t   TMSTS26;                                /*  TMSTS26         */
+    volatile uint8_t   TMSTS27;                                /*  TMSTS27         */
+    volatile uint8_t   TMSTS28;                                /*  TMSTS28         */
+    volatile uint8_t   TMSTS29;                                /*  TMSTS29         */
+    volatile uint8_t   TMSTS30;                                /*  TMSTS30         */
+    volatile uint8_t   TMSTS31;                                /*  TMSTS31         */
+    volatile uint8_t   TMSTS32;                                /*  TMSTS32         */
+    volatile uint8_t   TMSTS33;                                /*  TMSTS33         */
+    volatile uint8_t   TMSTS34;                                /*  TMSTS34         */
+    volatile uint8_t   TMSTS35;                                /*  TMSTS35         */
+    volatile uint8_t   TMSTS36;                                /*  TMSTS36         */
+    volatile uint8_t   TMSTS37;                                /*  TMSTS37         */
+    volatile uint8_t   TMSTS38;                                /*  TMSTS38         */
+    volatile uint8_t   TMSTS39;                                /*  TMSTS39         */
+    volatile uint8_t   TMSTS40;                                /*  TMSTS40         */
+    volatile uint8_t   TMSTS41;                                /*  TMSTS41         */
+    volatile uint8_t   TMSTS42;                                /*  TMSTS42         */
+    volatile uint8_t   TMSTS43;                                /*  TMSTS43         */
+    volatile uint8_t   TMSTS44;                                /*  TMSTS44         */
+    volatile uint8_t   TMSTS45;                                /*  TMSTS45         */
+    volatile uint8_t   TMSTS46;                                /*  TMSTS46         */
+    volatile uint8_t   TMSTS47;                                /*  TMSTS47         */
+    volatile uint8_t   TMSTS48;                                /*  TMSTS48         */
+    volatile uint8_t   TMSTS49;                                /*  TMSTS49         */
+    volatile uint8_t   TMSTS50;                                /*  TMSTS50         */
+    volatile uint8_t   TMSTS51;                                /*  TMSTS51         */
+    volatile uint8_t   TMSTS52;                                /*  TMSTS52         */
+    volatile uint8_t   TMSTS53;                                /*  TMSTS53         */
+    volatile uint8_t   TMSTS54;                                /*  TMSTS54         */
+    volatile uint8_t   TMSTS55;                                /*  TMSTS55         */
+    volatile uint8_t   TMSTS56;                                /*  TMSTS56         */
+    volatile uint8_t   TMSTS57;                                /*  TMSTS57         */
+    volatile uint8_t   TMSTS58;                                /*  TMSTS58         */
+    volatile uint8_t   TMSTS59;                                /*  TMSTS59         */
+    volatile uint8_t   TMSTS60;                                /*  TMSTS60         */
+    volatile uint8_t   TMSTS61;                                /*  TMSTS61         */
+    volatile uint8_t   TMSTS62;                                /*  TMSTS62         */
+    volatile uint8_t   TMSTS63;                                /*  TMSTS63         */
+    volatile uint8_t   TMSTS64;                                /*  TMSTS64         */
+    volatile uint8_t   TMSTS65;                                /*  TMSTS65         */
+    volatile uint8_t   TMSTS66;                                /*  TMSTS66         */
+    volatile uint8_t   TMSTS67;                                /*  TMSTS67         */
+    volatile uint8_t   TMSTS68;                                /*  TMSTS68         */
+    volatile uint8_t   TMSTS69;                                /*  TMSTS69         */
+    volatile uint8_t   TMSTS70;                                /*  TMSTS70         */
+    volatile uint8_t   TMSTS71;                                /*  TMSTS71         */
+    volatile uint8_t   TMSTS72;                                /*  TMSTS72         */
+    volatile uint8_t   TMSTS73;                                /*  TMSTS73         */
+    volatile uint8_t   TMSTS74;                                /*  TMSTS74         */
+    volatile uint8_t   TMSTS75;                                /*  TMSTS75         */
+    volatile uint8_t   TMSTS76;                                /*  TMSTS76         */
+    volatile uint8_t   TMSTS77;                                /*  TMSTS77         */
+    volatile uint8_t   TMSTS78;                                /*  TMSTS78         */
+    volatile uint8_t   TMSTS79;                                /*  TMSTS79         */
+    volatile uint8_t   dummy165[48];                           /*                  */
+
+/* #define RSCAN0_TMTRSTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTRSTS0;                      /*  TMTRSTS0        */
+    union iodefine_reg32_t  TMTRSTS1;                      /*  TMTRSTS1        */
+    union iodefine_reg32_t  TMTRSTS2;                      /*  TMTRSTS2        */
+    
+    volatile uint8_t   dummy166[4];                            /*                  */
+
+/* #define RSCAN0_TMTARSTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTARSTS0;                     /*  TMTARSTS0       */
+    union iodefine_reg32_t  TMTARSTS1;                     /*  TMTARSTS1       */
+    union iodefine_reg32_t  TMTARSTS2;                     /*  TMTARSTS2       */
+    
+    volatile uint8_t   dummy167[4];                            /*                  */
+
+/* #define RSCAN0_TMTCSTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTCSTS0;                      /*  TMTCSTS0        */
+    union iodefine_reg32_t  TMTCSTS1;                      /*  TMTCSTS1        */
+    union iodefine_reg32_t  TMTCSTS2;                      /*  TMTCSTS2        */
+    
+    volatile uint8_t   dummy168[4];                            /*                  */
+
+/* #define RSCAN0_TMTASTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTASTS0;                      /*  TMTASTS0        */
+    union iodefine_reg32_t  TMTASTS1;                      /*  TMTASTS1        */
+    union iodefine_reg32_t  TMTASTS2;                      /*  TMTASTS2        */
+    
+    volatile uint8_t   dummy169[4];                            /*                  */
+
+/* #define RSCAN0_TMIEC0_COUNT (3) */
+    union iodefine_reg32_t  TMIEC0;                        /*  TMIEC0          */
+    union iodefine_reg32_t  TMIEC1;                        /*  TMIEC1          */
+    union iodefine_reg32_t  TMIEC2;                        /*  TMIEC2          */
+    
+    volatile uint8_t   dummy170[4];                            /*                  */
+
+/* #define RSCAN0_TXQCC0_COUNT (5) */
+    union iodefine_reg32_t  TXQCC0;                        /*  TXQCC0          */
+    union iodefine_reg32_t  TXQCC1;                        /*  TXQCC1          */
+    union iodefine_reg32_t  TXQCC2;                        /*  TXQCC2          */
+    union iodefine_reg32_t  TXQCC3;                        /*  TXQCC3          */
+    union iodefine_reg32_t  TXQCC4;                        /*  TXQCC4          */
+    
+    volatile uint8_t   dummy171[12];                           /*                  */
+
+/* #define RSCAN0_TXQSTS0_COUNT (5) */
+    union iodefine_reg32_t  TXQSTS0;                       /*  TXQSTS0         */
+    union iodefine_reg32_t  TXQSTS1;                       /*  TXQSTS1         */
+    union iodefine_reg32_t  TXQSTS2;                       /*  TXQSTS2         */
+    union iodefine_reg32_t  TXQSTS3;                       /*  TXQSTS3         */
+    union iodefine_reg32_t  TXQSTS4;                       /*  TXQSTS4         */
+    
+    volatile uint8_t   dummy172[12];                           /*                  */
+
+/* #define RSCAN0_TXQPCTR0_COUNT (5) */
+    union iodefine_reg32_t  TXQPCTR0;                      /*  TXQPCTR0        */
+    union iodefine_reg32_t  TXQPCTR1;                      /*  TXQPCTR1        */
+    union iodefine_reg32_t  TXQPCTR2;                      /*  TXQPCTR2        */
+    union iodefine_reg32_t  TXQPCTR3;                      /*  TXQPCTR3        */
+    union iodefine_reg32_t  TXQPCTR4;                      /*  TXQPCTR4        */
+    
+    volatile uint8_t   dummy173[12];                           /*                  */
+
+/* #define RSCAN0_THLCC0_COUNT (5) */
+    union iodefine_reg32_t  THLCC0;                        /*  THLCC0          */
+    union iodefine_reg32_t  THLCC1;                        /*  THLCC1          */
+    union iodefine_reg32_t  THLCC2;                        /*  THLCC2          */
+    union iodefine_reg32_t  THLCC3;                        /*  THLCC3          */
+    union iodefine_reg32_t  THLCC4;                        /*  THLCC4          */
+    
+    volatile uint8_t   dummy174[12];                           /*                  */
+
+/* #define RSCAN0_THLSTS0_COUNT (5) */
+    union iodefine_reg32_t  THLSTS0;                       /*  THLSTS0         */
+    union iodefine_reg32_t  THLSTS1;                       /*  THLSTS1         */
+    union iodefine_reg32_t  THLSTS2;                       /*  THLSTS2         */
+    union iodefine_reg32_t  THLSTS3;                       /*  THLSTS3         */
+    union iodefine_reg32_t  THLSTS4;                       /*  THLSTS4         */
+    
+    volatile uint8_t   dummy175[12];                           /*                  */
+
+/* #define RSCAN0_THLPCTR0_COUNT (5) */
+    union iodefine_reg32_t  THLPCTR0;                      /*  THLPCTR0        */
+    union iodefine_reg32_t  THLPCTR1;                      /*  THLPCTR1        */
+    union iodefine_reg32_t  THLPCTR2;                      /*  THLPCTR2        */
+    union iodefine_reg32_t  THLPCTR3;                      /*  THLPCTR3        */
+    union iodefine_reg32_t  THLPCTR4;                      /*  THLPCTR4        */
+    
+    volatile uint8_t   dummy176[12];                           /*                  */
+
+/* #define RSCAN0_GTINTSTS0_COUNT (2) */
+    union iodefine_reg32_t  GTINTSTS0;                     /*  GTINTSTS0       */
+    union iodefine_reg32_t  GTINTSTS1;                     /*  GTINTSTS1       */
+    union iodefine_reg32_t  GTSTCFG;                       /*  GTSTCFG         */
+    union iodefine_reg32_t  GTSTCTR;                       /*  GTSTCTR         */
+    
+    volatile uint8_t   dummy177[12];                           /*                  */
+    union iodefine_reg32_16_t  GLOCKK;                     /*  GLOCKK          */
+    
+    volatile uint8_t   dummy178[128];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID0;                       /*  GAFLID0         */
+    union iodefine_reg32_t  GAFLM0;                        /*  GAFLM0          */
+    union iodefine_reg32_t  GAFLP00;                       /*  GAFLP00         */
+    union iodefine_reg32_t  GAFLP10;                       /*  GAFLP10         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID1;                       /*  GAFLID1         */
+    union iodefine_reg32_t  GAFLM1;                        /*  GAFLM1          */
+    union iodefine_reg32_t  GAFLP01;                       /*  GAFLP01         */
+    union iodefine_reg32_t  GAFLP11;                       /*  GAFLP11         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID2;                       /*  GAFLID2         */
+    union iodefine_reg32_t  GAFLM2;                        /*  GAFLM2          */
+    union iodefine_reg32_t  GAFLP02;                       /*  GAFLP02         */
+    union iodefine_reg32_t  GAFLP12;                       /*  GAFLP12         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID3;                       /*  GAFLID3         */
+    union iodefine_reg32_t  GAFLM3;                        /*  GAFLM3          */
+    union iodefine_reg32_t  GAFLP03;                       /*  GAFLP03         */
+    union iodefine_reg32_t  GAFLP13;                       /*  GAFLP13         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID4;                       /*  GAFLID4         */
+    union iodefine_reg32_t  GAFLM4;                        /*  GAFLM4          */
+    union iodefine_reg32_t  GAFLP04;                       /*  GAFLP04         */
+    union iodefine_reg32_t  GAFLP14;                       /*  GAFLP14         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID5;                       /*  GAFLID5         */
+    union iodefine_reg32_t  GAFLM5;                        /*  GAFLM5          */
+    union iodefine_reg32_t  GAFLP05;                       /*  GAFLP05         */
+    union iodefine_reg32_t  GAFLP15;                       /*  GAFLP15         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID6;                       /*  GAFLID6         */
+    union iodefine_reg32_t  GAFLM6;                        /*  GAFLM6          */
+    union iodefine_reg32_t  GAFLP06;                       /*  GAFLP06         */
+    union iodefine_reg32_t  GAFLP16;                       /*  GAFLP16         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID7;                       /*  GAFLID7         */
+    union iodefine_reg32_t  GAFLM7;                        /*  GAFLM7          */
+    union iodefine_reg32_t  GAFLP07;                       /*  GAFLP07         */
+    union iodefine_reg32_t  GAFLP17;                       /*  GAFLP17         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID8;                       /*  GAFLID8         */
+    union iodefine_reg32_t  GAFLM8;                        /*  GAFLM8          */
+    union iodefine_reg32_t  GAFLP08;                       /*  GAFLP08         */
+    union iodefine_reg32_t  GAFLP18;                       /*  GAFLP18         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID9;                       /*  GAFLID9         */
+    union iodefine_reg32_t  GAFLM9;                        /*  GAFLM9          */
+    union iodefine_reg32_t  GAFLP09;                       /*  GAFLP09         */
+    union iodefine_reg32_t  GAFLP19;                       /*  GAFLP19         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID10;                      /*  GAFLID10        */
+    union iodefine_reg32_t  GAFLM10;                       /*  GAFLM10         */
+    union iodefine_reg32_t  GAFLP010;                      /*  GAFLP010        */
+    union iodefine_reg32_t  GAFLP110;                      /*  GAFLP110        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID11;                      /*  GAFLID11        */
+    union iodefine_reg32_t  GAFLM11;                       /*  GAFLM11         */
+    union iodefine_reg32_t  GAFLP011;                      /*  GAFLP011        */
+    union iodefine_reg32_t  GAFLP111;                      /*  GAFLP111        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID12;                      /*  GAFLID12        */
+    union iodefine_reg32_t  GAFLM12;                       /*  GAFLM12         */
+    union iodefine_reg32_t  GAFLP012;                      /*  GAFLP012        */
+    union iodefine_reg32_t  GAFLP112;                      /*  GAFLP112        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID13;                      /*  GAFLID13        */
+    union iodefine_reg32_t  GAFLM13;                       /*  GAFLM13         */
+    union iodefine_reg32_t  GAFLP013;                      /*  GAFLP013        */
+    union iodefine_reg32_t  GAFLP113;                      /*  GAFLP113        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID14;                      /*  GAFLID14        */
+    union iodefine_reg32_t  GAFLM14;                       /*  GAFLM14         */
+    union iodefine_reg32_t  GAFLP014;                      /*  GAFLP014        */
+    union iodefine_reg32_t  GAFLP114;                      /*  GAFLP114        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID15;                      /*  GAFLID15        */
+    union iodefine_reg32_t  GAFLM15;                       /*  GAFLM15         */
+    union iodefine_reg32_t  GAFLP015;                      /*  GAFLP015        */
+    union iodefine_reg32_t  GAFLP115;                      /*  GAFLP115        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID0;                         /*  RMID0           */
+    union iodefine_reg32_t  RMPTR0;                        /*  RMPTR0          */
+    union iodefine_reg32_t  RMDF00;                        /*  RMDF00          */
+    union iodefine_reg32_t  RMDF10;                        /*  RMDF10          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID1;                         /*  RMID1           */
+    union iodefine_reg32_t  RMPTR1;                        /*  RMPTR1          */
+    union iodefine_reg32_t  RMDF01;                        /*  RMDF01          */
+    union iodefine_reg32_t  RMDF11;                        /*  RMDF11          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID2;                         /*  RMID2           */
+    union iodefine_reg32_t  RMPTR2;                        /*  RMPTR2          */
+    union iodefine_reg32_t  RMDF02;                        /*  RMDF02          */
+    union iodefine_reg32_t  RMDF12;                        /*  RMDF12          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID3;                         /*  RMID3           */
+    union iodefine_reg32_t  RMPTR3;                        /*  RMPTR3          */
+    union iodefine_reg32_t  RMDF03;                        /*  RMDF03          */
+    union iodefine_reg32_t  RMDF13;                        /*  RMDF13          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID4;                         /*  RMID4           */
+    union iodefine_reg32_t  RMPTR4;                        /*  RMPTR4          */
+    union iodefine_reg32_t  RMDF04;                        /*  RMDF04          */
+    union iodefine_reg32_t  RMDF14;                        /*  RMDF14          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID5;                         /*  RMID5           */
+    union iodefine_reg32_t  RMPTR5;                        /*  RMPTR5          */
+    union iodefine_reg32_t  RMDF05;                        /*  RMDF05          */
+    union iodefine_reg32_t  RMDF15;                        /*  RMDF15          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID6;                         /*  RMID6           */
+    union iodefine_reg32_t  RMPTR6;                        /*  RMPTR6          */
+    union iodefine_reg32_t  RMDF06;                        /*  RMDF06          */
+    union iodefine_reg32_t  RMDF16;                        /*  RMDF16          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID7;                         /*  RMID7           */
+    union iodefine_reg32_t  RMPTR7;                        /*  RMPTR7          */
+    union iodefine_reg32_t  RMDF07;                        /*  RMDF07          */
+    union iodefine_reg32_t  RMDF17;                        /*  RMDF17          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID8;                         /*  RMID8           */
+    union iodefine_reg32_t  RMPTR8;                        /*  RMPTR8          */
+    union iodefine_reg32_t  RMDF08;                        /*  RMDF08          */
+    union iodefine_reg32_t  RMDF18;                        /*  RMDF18          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID9;                         /*  RMID9           */
+    union iodefine_reg32_t  RMPTR9;                        /*  RMPTR9          */
+    union iodefine_reg32_t  RMDF09;                        /*  RMDF09          */
+    union iodefine_reg32_t  RMDF19;                        /*  RMDF19          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID10;                        /*  RMID10          */
+    union iodefine_reg32_t  RMPTR10;                       /*  RMPTR10         */
+    union iodefine_reg32_t  RMDF010;                       /*  RMDF010         */
+    union iodefine_reg32_t  RMDF110;                       /*  RMDF110         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID11;                        /*  RMID11          */
+    union iodefine_reg32_t  RMPTR11;                       /*  RMPTR11         */
+    union iodefine_reg32_t  RMDF011;                       /*  RMDF011         */
+    union iodefine_reg32_t  RMDF111;                       /*  RMDF111         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID12;                        /*  RMID12          */
+    union iodefine_reg32_t  RMPTR12;                       /*  RMPTR12         */
+    union iodefine_reg32_t  RMDF012;                       /*  RMDF012         */
+    union iodefine_reg32_t  RMDF112;                       /*  RMDF112         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID13;                        /*  RMID13          */
+    union iodefine_reg32_t  RMPTR13;                       /*  RMPTR13         */
+    union iodefine_reg32_t  RMDF013;                       /*  RMDF013         */
+    union iodefine_reg32_t  RMDF113;                       /*  RMDF113         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID14;                        /*  RMID14          */
+    union iodefine_reg32_t  RMPTR14;                       /*  RMPTR14         */
+    union iodefine_reg32_t  RMDF014;                       /*  RMDF014         */
+    union iodefine_reg32_t  RMDF114;                       /*  RMDF114         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID15;                        /*  RMID15          */
+    union iodefine_reg32_t  RMPTR15;                       /*  RMPTR15         */
+    union iodefine_reg32_t  RMDF015;                       /*  RMDF015         */
+    union iodefine_reg32_t  RMDF115;                       /*  RMDF115         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID16;                        /*  RMID16          */
+    union iodefine_reg32_t  RMPTR16;                       /*  RMPTR16         */
+    union iodefine_reg32_t  RMDF016;                       /*  RMDF016         */
+    union iodefine_reg32_t  RMDF116;                       /*  RMDF116         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID17;                        /*  RMID17          */
+    union iodefine_reg32_t  RMPTR17;                       /*  RMPTR17         */
+    union iodefine_reg32_t  RMDF017;                       /*  RMDF017         */
+    union iodefine_reg32_t  RMDF117;                       /*  RMDF117         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID18;                        /*  RMID18          */
+    union iodefine_reg32_t  RMPTR18;                       /*  RMPTR18         */
+    union iodefine_reg32_t  RMDF018;                       /*  RMDF018         */
+    union iodefine_reg32_t  RMDF118;                       /*  RMDF118         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID19;                        /*  RMID19          */
+    union iodefine_reg32_t  RMPTR19;                       /*  RMPTR19         */
+    union iodefine_reg32_t  RMDF019;                       /*  RMDF019         */
+    union iodefine_reg32_t  RMDF119;                       /*  RMDF119         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID20;                        /*  RMID20          */
+    union iodefine_reg32_t  RMPTR20;                       /*  RMPTR20         */
+    union iodefine_reg32_t  RMDF020;                       /*  RMDF020         */
+    union iodefine_reg32_t  RMDF120;                       /*  RMDF120         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID21;                        /*  RMID21          */
+    union iodefine_reg32_t  RMPTR21;                       /*  RMPTR21         */
+    union iodefine_reg32_t  RMDF021;                       /*  RMDF021         */
+    union iodefine_reg32_t  RMDF121;                       /*  RMDF121         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID22;                        /*  RMID22          */
+    union iodefine_reg32_t  RMPTR22;                       /*  RMPTR22         */
+    union iodefine_reg32_t  RMDF022;                       /*  RMDF022         */
+    union iodefine_reg32_t  RMDF122;                       /*  RMDF122         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID23;                        /*  RMID23          */
+    union iodefine_reg32_t  RMPTR23;                       /*  RMPTR23         */
+    union iodefine_reg32_t  RMDF023;                       /*  RMDF023         */
+    union iodefine_reg32_t  RMDF123;                       /*  RMDF123         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID24;                        /*  RMID24          */
+    union iodefine_reg32_t  RMPTR24;                       /*  RMPTR24         */
+    union iodefine_reg32_t  RMDF024;                       /*  RMDF024         */
+    union iodefine_reg32_t  RMDF124;                       /*  RMDF124         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID25;                        /*  RMID25          */
+    union iodefine_reg32_t  RMPTR25;                       /*  RMPTR25         */
+    union iodefine_reg32_t  RMDF025;                       /*  RMDF025         */
+    union iodefine_reg32_t  RMDF125;                       /*  RMDF125         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID26;                        /*  RMID26          */
+    union iodefine_reg32_t  RMPTR26;                       /*  RMPTR26         */
+    union iodefine_reg32_t  RMDF026;                       /*  RMDF026         */
+    union iodefine_reg32_t  RMDF126;                       /*  RMDF126         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID27;                        /*  RMID27          */
+    union iodefine_reg32_t  RMPTR27;                       /*  RMPTR27         */
+    union iodefine_reg32_t  RMDF027;                       /*  RMDF027         */
+    union iodefine_reg32_t  RMDF127;                       /*  RMDF127         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID28;                        /*  RMID28          */
+    union iodefine_reg32_t  RMPTR28;                       /*  RMPTR28         */
+    union iodefine_reg32_t  RMDF028;                       /*  RMDF028         */
+    union iodefine_reg32_t  RMDF128;                       /*  RMDF128         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID29;                        /*  RMID29          */
+    union iodefine_reg32_t  RMPTR29;                       /*  RMPTR29         */
+    union iodefine_reg32_t  RMDF029;                       /*  RMDF029         */
+    union iodefine_reg32_t  RMDF129;                       /*  RMDF129         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID30;                        /*  RMID30          */
+    union iodefine_reg32_t  RMPTR30;                       /*  RMPTR30         */
+    union iodefine_reg32_t  RMDF030;                       /*  RMDF030         */
+    union iodefine_reg32_t  RMDF130;                       /*  RMDF130         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID31;                        /*  RMID31          */
+    union iodefine_reg32_t  RMPTR31;                       /*  RMPTR31         */
+    union iodefine_reg32_t  RMDF031;                       /*  RMDF031         */
+    union iodefine_reg32_t  RMDF131;                       /*  RMDF131         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID32;                        /*  RMID32          */
+    union iodefine_reg32_t  RMPTR32;                       /*  RMPTR32         */
+    union iodefine_reg32_t  RMDF032;                       /*  RMDF032         */
+    union iodefine_reg32_t  RMDF132;                       /*  RMDF132         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID33;                        /*  RMID33          */
+    union iodefine_reg32_t  RMPTR33;                       /*  RMPTR33         */
+    union iodefine_reg32_t  RMDF033;                       /*  RMDF033         */
+    union iodefine_reg32_t  RMDF133;                       /*  RMDF133         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID34;                        /*  RMID34          */
+    union iodefine_reg32_t  RMPTR34;                       /*  RMPTR34         */
+    union iodefine_reg32_t  RMDF034;                       /*  RMDF034         */
+    union iodefine_reg32_t  RMDF134;                       /*  RMDF134         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID35;                        /*  RMID35          */
+    union iodefine_reg32_t  RMPTR35;                       /*  RMPTR35         */
+    union iodefine_reg32_t  RMDF035;                       /*  RMDF035         */
+    union iodefine_reg32_t  RMDF135;                       /*  RMDF135         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID36;                        /*  RMID36          */
+    union iodefine_reg32_t  RMPTR36;                       /*  RMPTR36         */
+    union iodefine_reg32_t  RMDF036;                       /*  RMDF036         */
+    union iodefine_reg32_t  RMDF136;                       /*  RMDF136         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID37;                        /*  RMID37          */
+    union iodefine_reg32_t  RMPTR37;                       /*  RMPTR37         */
+    union iodefine_reg32_t  RMDF037;                       /*  RMDF037         */
+    union iodefine_reg32_t  RMDF137;                       /*  RMDF137         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID38;                        /*  RMID38          */
+    union iodefine_reg32_t  RMPTR38;                       /*  RMPTR38         */
+    union iodefine_reg32_t  RMDF038;                       /*  RMDF038         */
+    union iodefine_reg32_t  RMDF138;                       /*  RMDF138         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID39;                        /*  RMID39          */
+    union iodefine_reg32_t  RMPTR39;                       /*  RMPTR39         */
+    union iodefine_reg32_t  RMDF039;                       /*  RMDF039         */
+    union iodefine_reg32_t  RMDF139;                       /*  RMDF139         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID40;                        /*  RMID40          */
+    union iodefine_reg32_t  RMPTR40;                       /*  RMPTR40         */
+    union iodefine_reg32_t  RMDF040;                       /*  RMDF040         */
+    union iodefine_reg32_t  RMDF140;                       /*  RMDF140         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID41;                        /*  RMID41          */
+    union iodefine_reg32_t  RMPTR41;                       /*  RMPTR41         */
+    union iodefine_reg32_t  RMDF041;                       /*  RMDF041         */
+    union iodefine_reg32_t  RMDF141;                       /*  RMDF141         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID42;                        /*  RMID42          */
+    union iodefine_reg32_t  RMPTR42;                       /*  RMPTR42         */
+    union iodefine_reg32_t  RMDF042;                       /*  RMDF042         */
+    union iodefine_reg32_t  RMDF142;                       /*  RMDF142         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID43;                        /*  RMID43          */
+    union iodefine_reg32_t  RMPTR43;                       /*  RMPTR43         */
+    union iodefine_reg32_t  RMDF043;                       /*  RMDF043         */
+    union iodefine_reg32_t  RMDF143;                       /*  RMDF143         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID44;                        /*  RMID44          */
+    union iodefine_reg32_t  RMPTR44;                       /*  RMPTR44         */
+    union iodefine_reg32_t  RMDF044;                       /*  RMDF044         */
+    union iodefine_reg32_t  RMDF144;                       /*  RMDF144         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID45;                        /*  RMID45          */
+    union iodefine_reg32_t  RMPTR45;                       /*  RMPTR45         */
+    union iodefine_reg32_t  RMDF045;                       /*  RMDF045         */
+    union iodefine_reg32_t  RMDF145;                       /*  RMDF145         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID46;                        /*  RMID46          */
+    union iodefine_reg32_t  RMPTR46;                       /*  RMPTR46         */
+    union iodefine_reg32_t  RMDF046;                       /*  RMDF046         */
+    union iodefine_reg32_t  RMDF146;                       /*  RMDF146         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID47;                        /*  RMID47          */
+    union iodefine_reg32_t  RMPTR47;                       /*  RMPTR47         */
+    union iodefine_reg32_t  RMDF047;                       /*  RMDF047         */
+    union iodefine_reg32_t  RMDF147;                       /*  RMDF147         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID48;                        /*  RMID48          */
+    union iodefine_reg32_t  RMPTR48;                       /*  RMPTR48         */
+    union iodefine_reg32_t  RMDF048;                       /*  RMDF048         */
+    union iodefine_reg32_t  RMDF148;                       /*  RMDF148         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID49;                        /*  RMID49          */
+    union iodefine_reg32_t  RMPTR49;                       /*  RMPTR49         */
+    union iodefine_reg32_t  RMDF049;                       /*  RMDF049         */
+    union iodefine_reg32_t  RMDF149;                       /*  RMDF149         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID50;                        /*  RMID50          */
+    union iodefine_reg32_t  RMPTR50;                       /*  RMPTR50         */
+    union iodefine_reg32_t  RMDF050;                       /*  RMDF050         */
+    union iodefine_reg32_t  RMDF150;                       /*  RMDF150         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID51;                        /*  RMID51          */
+    union iodefine_reg32_t  RMPTR51;                       /*  RMPTR51         */
+    union iodefine_reg32_t  RMDF051;                       /*  RMDF051         */
+    union iodefine_reg32_t  RMDF151;                       /*  RMDF151         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID52;                        /*  RMID52          */
+    union iodefine_reg32_t  RMPTR52;                       /*  RMPTR52         */
+    union iodefine_reg32_t  RMDF052;                       /*  RMDF052         */
+    union iodefine_reg32_t  RMDF152;                       /*  RMDF152         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID53;                        /*  RMID53          */
+    union iodefine_reg32_t  RMPTR53;                       /*  RMPTR53         */
+    union iodefine_reg32_t  RMDF053;                       /*  RMDF053         */
+    union iodefine_reg32_t  RMDF153;                       /*  RMDF153         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID54;                        /*  RMID54          */
+    union iodefine_reg32_t  RMPTR54;                       /*  RMPTR54         */
+    union iodefine_reg32_t  RMDF054;                       /*  RMDF054         */
+    union iodefine_reg32_t  RMDF154;                       /*  RMDF154         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID55;                        /*  RMID55          */
+    union iodefine_reg32_t  RMPTR55;                       /*  RMPTR55         */
+    union iodefine_reg32_t  RMDF055;                       /*  RMDF055         */
+    union iodefine_reg32_t  RMDF155;                       /*  RMDF155         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID56;                        /*  RMID56          */
+    union iodefine_reg32_t  RMPTR56;                       /*  RMPTR56         */
+    union iodefine_reg32_t  RMDF056;                       /*  RMDF056         */
+    union iodefine_reg32_t  RMDF156;                       /*  RMDF156         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID57;                        /*  RMID57          */
+    union iodefine_reg32_t  RMPTR57;                       /*  RMPTR57         */
+    union iodefine_reg32_t  RMDF057;                       /*  RMDF057         */
+    union iodefine_reg32_t  RMDF157;                       /*  RMDF157         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID58;                        /*  RMID58          */
+    union iodefine_reg32_t  RMPTR58;                       /*  RMPTR58         */
+    union iodefine_reg32_t  RMDF058;                       /*  RMDF058         */
+    union iodefine_reg32_t  RMDF158;                       /*  RMDF158         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID59;                        /*  RMID59          */
+    union iodefine_reg32_t  RMPTR59;                       /*  RMPTR59         */
+    union iodefine_reg32_t  RMDF059;                       /*  RMDF059         */
+    union iodefine_reg32_t  RMDF159;                       /*  RMDF159         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID60;                        /*  RMID60          */
+    union iodefine_reg32_t  RMPTR60;                       /*  RMPTR60         */
+    union iodefine_reg32_t  RMDF060;                       /*  RMDF060         */
+    union iodefine_reg32_t  RMDF160;                       /*  RMDF160         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID61;                        /*  RMID61          */
+    union iodefine_reg32_t  RMPTR61;                       /*  RMPTR61         */
+    union iodefine_reg32_t  RMDF061;                       /*  RMDF061         */
+    union iodefine_reg32_t  RMDF161;                       /*  RMDF161         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID62;                        /*  RMID62          */
+    union iodefine_reg32_t  RMPTR62;                       /*  RMPTR62         */
+    union iodefine_reg32_t  RMDF062;                       /*  RMDF062         */
+    union iodefine_reg32_t  RMDF162;                       /*  RMDF162         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID63;                        /*  RMID63          */
+    union iodefine_reg32_t  RMPTR63;                       /*  RMPTR63         */
+    union iodefine_reg32_t  RMDF063;                       /*  RMDF063         */
+    union iodefine_reg32_t  RMDF163;                       /*  RMDF163         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID64;                        /*  RMID64          */
+    union iodefine_reg32_t  RMPTR64;                       /*  RMPTR64         */
+    union iodefine_reg32_t  RMDF064;                       /*  RMDF064         */
+    union iodefine_reg32_t  RMDF164;                       /*  RMDF164         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID65;                        /*  RMID65          */
+    union iodefine_reg32_t  RMPTR65;                       /*  RMPTR65         */
+    union iodefine_reg32_t  RMDF065;                       /*  RMDF065         */
+    union iodefine_reg32_t  RMDF165;                       /*  RMDF165         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID66;                        /*  RMID66          */
+    union iodefine_reg32_t  RMPTR66;                       /*  RMPTR66         */
+    union iodefine_reg32_t  RMDF066;                       /*  RMDF066         */
+    union iodefine_reg32_t  RMDF166;                       /*  RMDF166         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID67;                        /*  RMID67          */
+    union iodefine_reg32_t  RMPTR67;                       /*  RMPTR67         */
+    union iodefine_reg32_t  RMDF067;                       /*  RMDF067         */
+    union iodefine_reg32_t  RMDF167;                       /*  RMDF167         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID68;                        /*  RMID68          */
+    union iodefine_reg32_t  RMPTR68;                       /*  RMPTR68         */
+    union iodefine_reg32_t  RMDF068;                       /*  RMDF068         */
+    union iodefine_reg32_t  RMDF168;                       /*  RMDF168         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID69;                        /*  RMID69          */
+    union iodefine_reg32_t  RMPTR69;                       /*  RMPTR69         */
+    union iodefine_reg32_t  RMDF069;                       /*  RMDF069         */
+    union iodefine_reg32_t  RMDF169;                       /*  RMDF169         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID70;                        /*  RMID70          */
+    union iodefine_reg32_t  RMPTR70;                       /*  RMPTR70         */
+    union iodefine_reg32_t  RMDF070;                       /*  RMDF070         */
+    union iodefine_reg32_t  RMDF170;                       /*  RMDF170         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID71;                        /*  RMID71          */
+    union iodefine_reg32_t  RMPTR71;                       /*  RMPTR71         */
+    union iodefine_reg32_t  RMDF071;                       /*  RMDF071         */
+    union iodefine_reg32_t  RMDF171;                       /*  RMDF171         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID72;                        /*  RMID72          */
+    union iodefine_reg32_t  RMPTR72;                       /*  RMPTR72         */
+    union iodefine_reg32_t  RMDF072;                       /*  RMDF072         */
+    union iodefine_reg32_t  RMDF172;                       /*  RMDF172         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID73;                        /*  RMID73          */
+    union iodefine_reg32_t  RMPTR73;                       /*  RMPTR73         */
+    union iodefine_reg32_t  RMDF073;                       /*  RMDF073         */
+    union iodefine_reg32_t  RMDF173;                       /*  RMDF173         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID74;                        /*  RMID74          */
+    union iodefine_reg32_t  RMPTR74;                       /*  RMPTR74         */
+    union iodefine_reg32_t  RMDF074;                       /*  RMDF074         */
+    union iodefine_reg32_t  RMDF174;                       /*  RMDF174         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID75;                        /*  RMID75          */
+    union iodefine_reg32_t  RMPTR75;                       /*  RMPTR75         */
+    union iodefine_reg32_t  RMDF075;                       /*  RMDF075         */
+    union iodefine_reg32_t  RMDF175;                       /*  RMDF175         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID76;                        /*  RMID76          */
+    union iodefine_reg32_t  RMPTR76;                       /*  RMPTR76         */
+    union iodefine_reg32_t  RMDF076;                       /*  RMDF076         */
+    union iodefine_reg32_t  RMDF176;                       /*  RMDF176         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID77;                        /*  RMID77          */
+    union iodefine_reg32_t  RMPTR77;                       /*  RMPTR77         */
+    union iodefine_reg32_t  RMDF077;                       /*  RMDF077         */
+    union iodefine_reg32_t  RMDF177;                       /*  RMDF177         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID78;                        /*  RMID78          */
+    union iodefine_reg32_t  RMPTR78;                       /*  RMPTR78         */
+    union iodefine_reg32_t  RMDF078;                       /*  RMDF078         */
+    union iodefine_reg32_t  RMDF178;                       /*  RMDF178         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID79;                        /*  RMID79          */
+    union iodefine_reg32_t  RMPTR79;                       /*  RMPTR79         */
+    union iodefine_reg32_t  RMDF079;                       /*  RMDF079         */
+    union iodefine_reg32_t  RMDF179;                       /*  RMDF179         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+    volatile uint8_t   dummy179[768];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID0;                         /*  RFID0           */
+    union iodefine_reg32_t  RFPTR0;                        /*  RFPTR0          */
+    union iodefine_reg32_t  RFDF00;                        /*  RFDF00          */
+    union iodefine_reg32_t  RFDF10;                        /*  RFDF10          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID1;                         /*  RFID1           */
+    union iodefine_reg32_t  RFPTR1;                        /*  RFPTR1          */
+    union iodefine_reg32_t  RFDF01;                        /*  RFDF01          */
+    union iodefine_reg32_t  RFDF11;                        /*  RFDF11          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID2;                         /*  RFID2           */
+    union iodefine_reg32_t  RFPTR2;                        /*  RFPTR2          */
+    union iodefine_reg32_t  RFDF02;                        /*  RFDF02          */
+    union iodefine_reg32_t  RFDF12;                        /*  RFDF12          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID3;                         /*  RFID3           */
+    union iodefine_reg32_t  RFPTR3;                        /*  RFPTR3          */
+    union iodefine_reg32_t  RFDF03;                        /*  RFDF03          */
+    union iodefine_reg32_t  RFDF13;                        /*  RFDF13          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID4;                         /*  RFID4           */
+    union iodefine_reg32_t  RFPTR4;                        /*  RFPTR4          */
+    union iodefine_reg32_t  RFDF04;                        /*  RFDF04          */
+    union iodefine_reg32_t  RFDF14;                        /*  RFDF14          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID5;                         /*  RFID5           */
+    union iodefine_reg32_t  RFPTR5;                        /*  RFPTR5          */
+    union iodefine_reg32_t  RFDF05;                        /*  RFDF05          */
+    union iodefine_reg32_t  RFDF15;                        /*  RFDF15          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID6;                         /*  RFID6           */
+    union iodefine_reg32_t  RFPTR6;                        /*  RFPTR6          */
+    union iodefine_reg32_t  RFDF06;                        /*  RFDF06          */
+    union iodefine_reg32_t  RFDF16;                        /*  RFDF16          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID7;                         /*  RFID7           */
+    union iodefine_reg32_t  RFPTR7;                        /*  RFPTR7          */
+    union iodefine_reg32_t  RFDF07;                        /*  RFDF07          */
+    union iodefine_reg32_t  RFDF17;                        /*  RFDF17          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID0;                         /*  CFID0           */
+    union iodefine_reg32_t  CFPTR0;                        /*  CFPTR0          */
+    union iodefine_reg32_t  CFDF00;                        /*  CFDF00          */
+    union iodefine_reg32_t  CFDF10;                        /*  CFDF10          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID1;                         /*  CFID1           */
+    union iodefine_reg32_t  CFPTR1;                        /*  CFPTR1          */
+    union iodefine_reg32_t  CFDF01;                        /*  CFDF01          */
+    union iodefine_reg32_t  CFDF11;                        /*  CFDF11          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID2;                         /*  CFID2           */
+    union iodefine_reg32_t  CFPTR2;                        /*  CFPTR2          */
+    union iodefine_reg32_t  CFDF02;                        /*  CFDF02          */
+    union iodefine_reg32_t  CFDF12;                        /*  CFDF12          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID3;                         /*  CFID3           */
+    union iodefine_reg32_t  CFPTR3;                        /*  CFPTR3          */
+    union iodefine_reg32_t  CFDF03;                        /*  CFDF03          */
+    union iodefine_reg32_t  CFDF13;                        /*  CFDF13          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID4;                         /*  CFID4           */
+    union iodefine_reg32_t  CFPTR4;                        /*  CFPTR4          */
+    union iodefine_reg32_t  CFDF04;                        /*  CFDF04          */
+    union iodefine_reg32_t  CFDF14;                        /*  CFDF14          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID5;                         /*  CFID5           */
+    union iodefine_reg32_t  CFPTR5;                        /*  CFPTR5          */
+    union iodefine_reg32_t  CFDF05;                        /*  CFDF05          */
+    union iodefine_reg32_t  CFDF15;                        /*  CFDF15          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID6;                         /*  CFID6           */
+    union iodefine_reg32_t  CFPTR6;                        /*  CFPTR6          */
+    union iodefine_reg32_t  CFDF06;                        /*  CFDF06          */
+    union iodefine_reg32_t  CFDF16;                        /*  CFDF16          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID7;                         /*  CFID7           */
+    union iodefine_reg32_t  CFPTR7;                        /*  CFPTR7          */
+    union iodefine_reg32_t  CFDF07;                        /*  CFDF07          */
+    union iodefine_reg32_t  CFDF17;                        /*  CFDF17          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID8;                         /*  CFID8           */
+    union iodefine_reg32_t  CFPTR8;                        /*  CFPTR8          */
+    union iodefine_reg32_t  CFDF08;                        /*  CFDF08          */
+    union iodefine_reg32_t  CFDF18;                        /*  CFDF18          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID9;                         /*  CFID9           */
+    union iodefine_reg32_t  CFPTR9;                        /*  CFPTR9          */
+    union iodefine_reg32_t  CFDF09;                        /*  CFDF09          */
+    union iodefine_reg32_t  CFDF19;                        /*  CFDF19          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID10;                        /*  CFID10          */
+    union iodefine_reg32_t  CFPTR10;                       /*  CFPTR10         */
+    union iodefine_reg32_t  CFDF010;                       /*  CFDF010         */
+    union iodefine_reg32_t  CFDF110;                       /*  CFDF110         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID11;                        /*  CFID11          */
+    union iodefine_reg32_t  CFPTR11;                       /*  CFPTR11         */
+    union iodefine_reg32_t  CFDF011;                       /*  CFDF011         */
+    union iodefine_reg32_t  CFDF111;                       /*  CFDF111         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID12;                        /*  CFID12          */
+    union iodefine_reg32_t  CFPTR12;                       /*  CFPTR12         */
+    union iodefine_reg32_t  CFDF012;                       /*  CFDF012         */
+    union iodefine_reg32_t  CFDF112;                       /*  CFDF112         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID13;                        /*  CFID13          */
+    union iodefine_reg32_t  CFPTR13;                       /*  CFPTR13         */
+    union iodefine_reg32_t  CFDF013;                       /*  CFDF013         */
+    union iodefine_reg32_t  CFDF113;                       /*  CFDF113         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID14;                        /*  CFID14          */
+    union iodefine_reg32_t  CFPTR14;                       /*  CFPTR14         */
+    union iodefine_reg32_t  CFDF014;                       /*  CFDF014         */
+    union iodefine_reg32_t  CFDF114;                       /*  CFDF114         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+    volatile uint8_t   dummy180[144];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID0;                         /*  TMID0           */
+    union iodefine_reg32_t  TMPTR0;                        /*  TMPTR0          */
+    union iodefine_reg32_t  TMDF00;                        /*  TMDF00          */
+    union iodefine_reg32_t  TMDF10;                        /*  TMDF10          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID1;                         /*  TMID1           */
+    union iodefine_reg32_t  TMPTR1;                        /*  TMPTR1          */
+    union iodefine_reg32_t  TMDF01;                        /*  TMDF01          */
+    union iodefine_reg32_t  TMDF11;                        /*  TMDF11          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID2;                         /*  TMID2           */
+    union iodefine_reg32_t  TMPTR2;                        /*  TMPTR2          */
+    union iodefine_reg32_t  TMDF02;                        /*  TMDF02          */
+    union iodefine_reg32_t  TMDF12;                        /*  TMDF12          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID3;                         /*  TMID3           */
+    union iodefine_reg32_t  TMPTR3;                        /*  TMPTR3          */
+    union iodefine_reg32_t  TMDF03;                        /*  TMDF03          */
+    union iodefine_reg32_t  TMDF13;                        /*  TMDF13          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID4;                         /*  TMID4           */
+    union iodefine_reg32_t  TMPTR4;                        /*  TMPTR4          */
+    union iodefine_reg32_t  TMDF04;                        /*  TMDF04          */
+    union iodefine_reg32_t  TMDF14;                        /*  TMDF14          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID5;                         /*  TMID5           */
+    union iodefine_reg32_t  TMPTR5;                        /*  TMPTR5          */
+    union iodefine_reg32_t  TMDF05;                        /*  TMDF05          */
+    union iodefine_reg32_t  TMDF15;                        /*  TMDF15          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID6;                         /*  TMID6           */
+    union iodefine_reg32_t  TMPTR6;                        /*  TMPTR6          */
+    union iodefine_reg32_t  TMDF06;                        /*  TMDF06          */
+    union iodefine_reg32_t  TMDF16;                        /*  TMDF16          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID7;                         /*  TMID7           */
+    union iodefine_reg32_t  TMPTR7;                        /*  TMPTR7          */
+    union iodefine_reg32_t  TMDF07;                        /*  TMDF07          */
+    union iodefine_reg32_t  TMDF17;                        /*  TMDF17          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID8;                         /*  TMID8           */
+    union iodefine_reg32_t  TMPTR8;                        /*  TMPTR8          */
+    union iodefine_reg32_t  TMDF08;                        /*  TMDF08          */
+    union iodefine_reg32_t  TMDF18;                        /*  TMDF18          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID9;                         /*  TMID9           */
+    union iodefine_reg32_t  TMPTR9;                        /*  TMPTR9          */
+    union iodefine_reg32_t  TMDF09;                        /*  TMDF09          */
+    union iodefine_reg32_t  TMDF19;                        /*  TMDF19          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID10;                        /*  TMID10          */
+    union iodefine_reg32_t  TMPTR10;                       /*  TMPTR10         */
+    union iodefine_reg32_t  TMDF010;                       /*  TMDF010         */
+    union iodefine_reg32_t  TMDF110;                       /*  TMDF110         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID11;                        /*  TMID11          */
+    union iodefine_reg32_t  TMPTR11;                       /*  TMPTR11         */
+    union iodefine_reg32_t  TMDF011;                       /*  TMDF011         */
+    union iodefine_reg32_t  TMDF111;                       /*  TMDF111         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID12;                        /*  TMID12          */
+    union iodefine_reg32_t  TMPTR12;                       /*  TMPTR12         */
+    union iodefine_reg32_t  TMDF012;                       /*  TMDF012         */
+    union iodefine_reg32_t  TMDF112;                       /*  TMDF112         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID13;                        /*  TMID13          */
+    union iodefine_reg32_t  TMPTR13;                       /*  TMPTR13         */
+    union iodefine_reg32_t  TMDF013;                       /*  TMDF013         */
+    union iodefine_reg32_t  TMDF113;                       /*  TMDF113         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID14;                        /*  TMID14          */
+    union iodefine_reg32_t  TMPTR14;                       /*  TMPTR14         */
+    union iodefine_reg32_t  TMDF014;                       /*  TMDF014         */
+    union iodefine_reg32_t  TMDF114;                       /*  TMDF114         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID15;                        /*  TMID15          */
+    union iodefine_reg32_t  TMPTR15;                       /*  TMPTR15         */
+    union iodefine_reg32_t  TMDF015;                       /*  TMDF015         */
+    union iodefine_reg32_t  TMDF115;                       /*  TMDF115         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID16;                        /*  TMID16          */
+    union iodefine_reg32_t  TMPTR16;                       /*  TMPTR16         */
+    union iodefine_reg32_t  TMDF016;                       /*  TMDF016         */
+    union iodefine_reg32_t  TMDF116;                       /*  TMDF116         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID17;                        /*  TMID17          */
+    union iodefine_reg32_t  TMPTR17;                       /*  TMPTR17         */
+    union iodefine_reg32_t  TMDF017;                       /*  TMDF017         */
+    union iodefine_reg32_t  TMDF117;                       /*  TMDF117         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID18;                        /*  TMID18          */
+    union iodefine_reg32_t  TMPTR18;                       /*  TMPTR18         */
+    union iodefine_reg32_t  TMDF018;                       /*  TMDF018         */
+    union iodefine_reg32_t  TMDF118;                       /*  TMDF118         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID19;                        /*  TMID19          */
+    union iodefine_reg32_t  TMPTR19;                       /*  TMPTR19         */
+    union iodefine_reg32_t  TMDF019;                       /*  TMDF019         */
+    union iodefine_reg32_t  TMDF119;                       /*  TMDF119         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID20;                        /*  TMID20          */
+    union iodefine_reg32_t  TMPTR20;                       /*  TMPTR20         */
+    union iodefine_reg32_t  TMDF020;                       /*  TMDF020         */
+    union iodefine_reg32_t  TMDF120;                       /*  TMDF120         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID21;                        /*  TMID21          */
+    union iodefine_reg32_t  TMPTR21;                       /*  TMPTR21         */
+    union iodefine_reg32_t  TMDF021;                       /*  TMDF021         */
+    union iodefine_reg32_t  TMDF121;                       /*  TMDF121         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID22;                        /*  TMID22          */
+    union iodefine_reg32_t  TMPTR22;                       /*  TMPTR22         */
+    union iodefine_reg32_t  TMDF022;                       /*  TMDF022         */
+    union iodefine_reg32_t  TMDF122;                       /*  TMDF122         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID23;                        /*  TMID23          */
+    union iodefine_reg32_t  TMPTR23;                       /*  TMPTR23         */
+    union iodefine_reg32_t  TMDF023;                       /*  TMDF023         */
+    union iodefine_reg32_t  TMDF123;                       /*  TMDF123         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID24;                        /*  TMID24          */
+    union iodefine_reg32_t  TMPTR24;                       /*  TMPTR24         */
+    union iodefine_reg32_t  TMDF024;                       /*  TMDF024         */
+    union iodefine_reg32_t  TMDF124;                       /*  TMDF124         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID25;                        /*  TMID25          */
+    union iodefine_reg32_t  TMPTR25;                       /*  TMPTR25         */
+    union iodefine_reg32_t  TMDF025;                       /*  TMDF025         */
+    union iodefine_reg32_t  TMDF125;                       /*  TMDF125         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID26;                        /*  TMID26          */
+    union iodefine_reg32_t  TMPTR26;                       /*  TMPTR26         */
+    union iodefine_reg32_t  TMDF026;                       /*  TMDF026         */
+    union iodefine_reg32_t  TMDF126;                       /*  TMDF126         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID27;                        /*  TMID27          */
+    union iodefine_reg32_t  TMPTR27;                       /*  TMPTR27         */
+    union iodefine_reg32_t  TMDF027;                       /*  TMDF027         */
+    union iodefine_reg32_t  TMDF127;                       /*  TMDF127         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID28;                        /*  TMID28          */
+    union iodefine_reg32_t  TMPTR28;                       /*  TMPTR28         */
+    union iodefine_reg32_t  TMDF028;                       /*  TMDF028         */
+    union iodefine_reg32_t  TMDF128;                       /*  TMDF128         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID29;                        /*  TMID29          */
+    union iodefine_reg32_t  TMPTR29;                       /*  TMPTR29         */
+    union iodefine_reg32_t  TMDF029;                       /*  TMDF029         */
+    union iodefine_reg32_t  TMDF129;                       /*  TMDF129         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID30;                        /*  TMID30          */
+    union iodefine_reg32_t  TMPTR30;                       /*  TMPTR30         */
+    union iodefine_reg32_t  TMDF030;                       /*  TMDF030         */
+    union iodefine_reg32_t  TMDF130;                       /*  TMDF130         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID31;                        /*  TMID31          */
+    union iodefine_reg32_t  TMPTR31;                       /*  TMPTR31         */
+    union iodefine_reg32_t  TMDF031;                       /*  TMDF031         */
+    union iodefine_reg32_t  TMDF131;                       /*  TMDF131         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID32;                        /*  TMID32          */
+    union iodefine_reg32_t  TMPTR32;                       /*  TMPTR32         */
+    union iodefine_reg32_t  TMDF032;                       /*  TMDF032         */
+    union iodefine_reg32_t  TMDF132;                       /*  TMDF132         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID33;                        /*  TMID33          */
+    union iodefine_reg32_t  TMPTR33;                       /*  TMPTR33         */
+    union iodefine_reg32_t  TMDF033;                       /*  TMDF033         */
+    union iodefine_reg32_t  TMDF133;                       /*  TMDF133         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID34;                        /*  TMID34          */
+    union iodefine_reg32_t  TMPTR34;                       /*  TMPTR34         */
+    union iodefine_reg32_t  TMDF034;                       /*  TMDF034         */
+    union iodefine_reg32_t  TMDF134;                       /*  TMDF134         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID35;                        /*  TMID35          */
+    union iodefine_reg32_t  TMPTR35;                       /*  TMPTR35         */
+    union iodefine_reg32_t  TMDF035;                       /*  TMDF035         */
+    union iodefine_reg32_t  TMDF135;                       /*  TMDF135         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID36;                        /*  TMID36          */
+    union iodefine_reg32_t  TMPTR36;                       /*  TMPTR36         */
+    union iodefine_reg32_t  TMDF036;                       /*  TMDF036         */
+    union iodefine_reg32_t  TMDF136;                       /*  TMDF136         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID37;                        /*  TMID37          */
+    union iodefine_reg32_t  TMPTR37;                       /*  TMPTR37         */
+    union iodefine_reg32_t  TMDF037;                       /*  TMDF037         */
+    union iodefine_reg32_t  TMDF137;                       /*  TMDF137         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID38;                        /*  TMID38          */
+    union iodefine_reg32_t  TMPTR38;                       /*  TMPTR38         */
+    union iodefine_reg32_t  TMDF038;                       /*  TMDF038         */
+    union iodefine_reg32_t  TMDF138;                       /*  TMDF138         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID39;                        /*  TMID39          */
+    union iodefine_reg32_t  TMPTR39;                       /*  TMPTR39         */
+    union iodefine_reg32_t  TMDF039;                       /*  TMDF039         */
+    union iodefine_reg32_t  TMDF139;                       /*  TMDF139         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID40;                        /*  TMID40          */
+    union iodefine_reg32_t  TMPTR40;                       /*  TMPTR40         */
+    union iodefine_reg32_t  TMDF040;                       /*  TMDF040         */
+    union iodefine_reg32_t  TMDF140;                       /*  TMDF140         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID41;                        /*  TMID41          */
+    union iodefine_reg32_t  TMPTR41;                       /*  TMPTR41         */
+    union iodefine_reg32_t  TMDF041;                       /*  TMDF041         */
+    union iodefine_reg32_t  TMDF141;                       /*  TMDF141         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID42;                        /*  TMID42          */
+    union iodefine_reg32_t  TMPTR42;                       /*  TMPTR42         */
+    union iodefine_reg32_t  TMDF042;                       /*  TMDF042         */
+    union iodefine_reg32_t  TMDF142;                       /*  TMDF142         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID43;                        /*  TMID43          */
+    union iodefine_reg32_t  TMPTR43;                       /*  TMPTR43         */
+    union iodefine_reg32_t  TMDF043;                       /*  TMDF043         */
+    union iodefine_reg32_t  TMDF143;                       /*  TMDF143         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID44;                        /*  TMID44          */
+    union iodefine_reg32_t  TMPTR44;                       /*  TMPTR44         */
+    union iodefine_reg32_t  TMDF044;                       /*  TMDF044         */
+    union iodefine_reg32_t  TMDF144;                       /*  TMDF144         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID45;                        /*  TMID45          */
+    union iodefine_reg32_t  TMPTR45;                       /*  TMPTR45         */
+    union iodefine_reg32_t  TMDF045;                       /*  TMDF045         */
+    union iodefine_reg32_t  TMDF145;                       /*  TMDF145         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID46;                        /*  TMID46          */
+    union iodefine_reg32_t  TMPTR46;                       /*  TMPTR46         */
+    union iodefine_reg32_t  TMDF046;                       /*  TMDF046         */
+    union iodefine_reg32_t  TMDF146;                       /*  TMDF146         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID47;                        /*  TMID47          */
+    union iodefine_reg32_t  TMPTR47;                       /*  TMPTR47         */
+    union iodefine_reg32_t  TMDF047;                       /*  TMDF047         */
+    union iodefine_reg32_t  TMDF147;                       /*  TMDF147         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID48;                        /*  TMID48          */
+    union iodefine_reg32_t  TMPTR48;                       /*  TMPTR48         */
+    union iodefine_reg32_t  TMDF048;                       /*  TMDF048         */
+    union iodefine_reg32_t  TMDF148;                       /*  TMDF148         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID49;                        /*  TMID49          */
+    union iodefine_reg32_t  TMPTR49;                       /*  TMPTR49         */
+    union iodefine_reg32_t  TMDF049;                       /*  TMDF049         */
+    union iodefine_reg32_t  TMDF149;                       /*  TMDF149         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID50;                        /*  TMID50          */
+    union iodefine_reg32_t  TMPTR50;                       /*  TMPTR50         */
+    union iodefine_reg32_t  TMDF050;                       /*  TMDF050         */
+    union iodefine_reg32_t  TMDF150;                       /*  TMDF150         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID51;                        /*  TMID51          */
+    union iodefine_reg32_t  TMPTR51;                       /*  TMPTR51         */
+    union iodefine_reg32_t  TMDF051;                       /*  TMDF051         */
+    union iodefine_reg32_t  TMDF151;                       /*  TMDF151         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID52;                        /*  TMID52          */
+    union iodefine_reg32_t  TMPTR52;                       /*  TMPTR52         */
+    union iodefine_reg32_t  TMDF052;                       /*  TMDF052         */
+    union iodefine_reg32_t  TMDF152;                       /*  TMDF152         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID53;                        /*  TMID53          */
+    union iodefine_reg32_t  TMPTR53;                       /*  TMPTR53         */
+    union iodefine_reg32_t  TMDF053;                       /*  TMDF053         */
+    union iodefine_reg32_t  TMDF153;                       /*  TMDF153         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID54;                        /*  TMID54          */
+    union iodefine_reg32_t  TMPTR54;                       /*  TMPTR54         */
+    union iodefine_reg32_t  TMDF054;                       /*  TMDF054         */
+    union iodefine_reg32_t  TMDF154;                       /*  TMDF154         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID55;                        /*  TMID55          */
+    union iodefine_reg32_t  TMPTR55;                       /*  TMPTR55         */
+    union iodefine_reg32_t  TMDF055;                       /*  TMDF055         */
+    union iodefine_reg32_t  TMDF155;                       /*  TMDF155         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID56;                        /*  TMID56          */
+    union iodefine_reg32_t  TMPTR56;                       /*  TMPTR56         */
+    union iodefine_reg32_t  TMDF056;                       /*  TMDF056         */
+    union iodefine_reg32_t  TMDF156;                       /*  TMDF156         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID57;                        /*  TMID57          */
+    union iodefine_reg32_t  TMPTR57;                       /*  TMPTR57         */
+    union iodefine_reg32_t  TMDF057;                       /*  TMDF057         */
+    union iodefine_reg32_t  TMDF157;                       /*  TMDF157         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID58;                        /*  TMID58          */
+    union iodefine_reg32_t  TMPTR58;                       /*  TMPTR58         */
+    union iodefine_reg32_t  TMDF058;                       /*  TMDF058         */
+    union iodefine_reg32_t  TMDF158;                       /*  TMDF158         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID59;                        /*  TMID59          */
+    union iodefine_reg32_t  TMPTR59;                       /*  TMPTR59         */
+    union iodefine_reg32_t  TMDF059;                       /*  TMDF059         */
+    union iodefine_reg32_t  TMDF159;                       /*  TMDF159         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID60;                        /*  TMID60          */
+    union iodefine_reg32_t  TMPTR60;                       /*  TMPTR60         */
+    union iodefine_reg32_t  TMDF060;                       /*  TMDF060         */
+    union iodefine_reg32_t  TMDF160;                       /*  TMDF160         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID61;                        /*  TMID61          */
+    union iodefine_reg32_t  TMPTR61;                       /*  TMPTR61         */
+    union iodefine_reg32_t  TMDF061;                       /*  TMDF061         */
+    union iodefine_reg32_t  TMDF161;                       /*  TMDF161         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID62;                        /*  TMID62          */
+    union iodefine_reg32_t  TMPTR62;                       /*  TMPTR62         */
+    union iodefine_reg32_t  TMDF062;                       /*  TMDF062         */
+    union iodefine_reg32_t  TMDF162;                       /*  TMDF162         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID63;                        /*  TMID63          */
+    union iodefine_reg32_t  TMPTR63;                       /*  TMPTR63         */
+    union iodefine_reg32_t  TMDF063;                       /*  TMDF063         */
+    union iodefine_reg32_t  TMDF163;                       /*  TMDF163         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID64;                        /*  TMID64          */
+    union iodefine_reg32_t  TMPTR64;                       /*  TMPTR64         */
+    union iodefine_reg32_t  TMDF064;                       /*  TMDF064         */
+    union iodefine_reg32_t  TMDF164;                       /*  TMDF164         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID65;                        /*  TMID65          */
+    union iodefine_reg32_t  TMPTR65;                       /*  TMPTR65         */
+    union iodefine_reg32_t  TMDF065;                       /*  TMDF065         */
+    union iodefine_reg32_t  TMDF165;                       /*  TMDF165         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID66;                        /*  TMID66          */
+    union iodefine_reg32_t  TMPTR66;                       /*  TMPTR66         */
+    union iodefine_reg32_t  TMDF066;                       /*  TMDF066         */
+    union iodefine_reg32_t  TMDF166;                       /*  TMDF166         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID67;                        /*  TMID67          */
+    union iodefine_reg32_t  TMPTR67;                       /*  TMPTR67         */
+    union iodefine_reg32_t  TMDF067;                       /*  TMDF067         */
+    union iodefine_reg32_t  TMDF167;                       /*  TMDF167         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID68;                        /*  TMID68          */
+    union iodefine_reg32_t  TMPTR68;                       /*  TMPTR68         */
+    union iodefine_reg32_t  TMDF068;                       /*  TMDF068         */
+    union iodefine_reg32_t  TMDF168;                       /*  TMDF168         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID69;                        /*  TMID69          */
+    union iodefine_reg32_t  TMPTR69;                       /*  TMPTR69         */
+    union iodefine_reg32_t  TMDF069;                       /*  TMDF069         */
+    union iodefine_reg32_t  TMDF169;                       /*  TMDF169         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID70;                        /*  TMID70          */
+    union iodefine_reg32_t  TMPTR70;                       /*  TMPTR70         */
+    union iodefine_reg32_t  TMDF070;                       /*  TMDF070         */
+    union iodefine_reg32_t  TMDF170;                       /*  TMDF170         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID71;                        /*  TMID71          */
+    union iodefine_reg32_t  TMPTR71;                       /*  TMPTR71         */
+    union iodefine_reg32_t  TMDF071;                       /*  TMDF071         */
+    union iodefine_reg32_t  TMDF171;                       /*  TMDF171         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID72;                        /*  TMID72          */
+    union iodefine_reg32_t  TMPTR72;                       /*  TMPTR72         */
+    union iodefine_reg32_t  TMDF072;                       /*  TMDF072         */
+    union iodefine_reg32_t  TMDF172;                       /*  TMDF172         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID73;                        /*  TMID73          */
+    union iodefine_reg32_t  TMPTR73;                       /*  TMPTR73         */
+    union iodefine_reg32_t  TMDF073;                       /*  TMDF073         */
+    union iodefine_reg32_t  TMDF173;                       /*  TMDF173         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID74;                        /*  TMID74          */
+    union iodefine_reg32_t  TMPTR74;                       /*  TMPTR74         */
+    union iodefine_reg32_t  TMDF074;                       /*  TMDF074         */
+    union iodefine_reg32_t  TMDF174;                       /*  TMDF174         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID75;                        /*  TMID75          */
+    union iodefine_reg32_t  TMPTR75;                       /*  TMPTR75         */
+    union iodefine_reg32_t  TMDF075;                       /*  TMDF075         */
+    union iodefine_reg32_t  TMDF175;                       /*  TMDF175         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID76;                        /*  TMID76          */
+    union iodefine_reg32_t  TMPTR76;                       /*  TMPTR76         */
+    union iodefine_reg32_t  TMDF076;                       /*  TMDF076         */
+    union iodefine_reg32_t  TMDF176;                       /*  TMDF176         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID77;                        /*  TMID77          */
+    union iodefine_reg32_t  TMPTR77;                       /*  TMPTR77         */
+    union iodefine_reg32_t  TMDF077;                       /*  TMDF077         */
+    union iodefine_reg32_t  TMDF177;                       /*  TMDF177         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID78;                        /*  TMID78          */
+    union iodefine_reg32_t  TMPTR78;                       /*  TMPTR78         */
+    union iodefine_reg32_t  TMDF078;                       /*  TMDF078         */
+    union iodefine_reg32_t  TMDF178;                       /*  TMDF178         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID79;                        /*  TMID79          */
+    union iodefine_reg32_t  TMPTR79;                       /*  TMPTR79         */
+    union iodefine_reg32_t  TMDF079;                       /*  TMDF079         */
+    union iodefine_reg32_t  TMDF179;                       /*  TMDF179         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+    volatile uint8_t   dummy181[768];                          /*                  */
+
+/* #define RSCAN0_THLACC0_COUNT (5) */
+    union iodefine_reg32_t  THLACC0;                       /*  THLACC0         */
+    union iodefine_reg32_t  THLACC1;                       /*  THLACC1         */
+    union iodefine_reg32_t  THLACC2;                       /*  THLACC2         */
+    union iodefine_reg32_t  THLACC3;                       /*  THLACC3         */
+    union iodefine_reg32_t  THLACC4;                       /*  THLACC4         */
+    
+} r_io_rscan0_t;
+
+
+typedef struct st_rscan_from_rscan0cncfg
+{
+ 
+    union iodefine_reg32_t  CnCFG;                         /*  CnCFG           */
+    union iodefine_reg32_t  CnCTR;                         /*  CnCTR           */
+    union iodefine_reg32_t  CnSTS;                         /*  CnSTS           */
+    union iodefine_reg32_t  CnERFL;                        /*  CnERFL          */
+} r_io_rscan_from_rscan0cncfg_t;
+
+
+typedef struct st_rscan_from_rscan0gaflidj
+{
+ 
+    union iodefine_reg32_t  GAFLIDj;                       /*  GAFLIDj         */
+    union iodefine_reg32_t  GAFLMj;                        /*  GAFLMj          */
+    union iodefine_reg32_t  GAFLP0j;                       /*  GAFLP0j         */
+    union iodefine_reg32_t  GAFLP1j;                       /*  GAFLP1j         */
+} r_io_rscan_from_rscan0gaflidj_t;
+
+
+typedef struct st_rscan_from_rscan0rmidp
+{
+ 
+    union iodefine_reg32_t  RMIDp;                         /*  RMIDp           */
+    union iodefine_reg32_t  RMPTRp;                        /*  RMPTRp          */
+    union iodefine_reg32_t  RMDF0p;                        /*  RMDF0p          */
+    union iodefine_reg32_t  RMDF1p;                        /*  RMDF1p          */
+} r_io_rscan_from_rscan0rmidp_t;
+
+
+typedef struct st_rscan_from_rscan0rfidm
+{
+ 
+    union iodefine_reg32_t  RFIDm;                         /*  RFIDm           */
+    union iodefine_reg32_t  RFPTRm;                        /*  RFPTRm          */
+    union iodefine_reg32_t  RFDF0m;                        /*  RFDF0m          */
+    union iodefine_reg32_t  RFDF1m;                        /*  RFDF1m          */
+} r_io_rscan_from_rscan0rfidm_t;
+
+
+typedef struct st_rscan_from_rscan0tmidp
+{
+ 
+    union iodefine_reg32_t  TMIDp;                         /*  TMIDp           */
+    union iodefine_reg32_t  TMPTRp;                        /*  TMPTRp          */
+    union iodefine_reg32_t  TMDF0p;                        /*  TMDF0p          */
+    union iodefine_reg32_t  TMDF1p;                        /*  TMDF1p          */
+} r_io_rscan_from_rscan0tmidp_t;
+
+
+typedef struct st_rscan_from_rscan0cfidm
+{
+ 
+    union iodefine_reg32_t  CFIDm;                         /*  CFIDm           */
+    union iodefine_reg32_t  CFPTRm;                        /*  CFPTRm          */
+    union iodefine_reg32_t  CFDF0m;                        /*  CFDF0m          */
+    union iodefine_reg32_t  CFDF1m;                        /*  CFDF1m          */
+} r_io_rscan_from_rscan0cfidm_t;
+
+
+/* Channel array defines of RSCAN0 (2)*/
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS
+volatile struct st_rscan_from_rscan0cfidm*  RSCAN_FROM_RSCAN0_CFIDm[ RSCAN_FROM_RSCAN0_CFIDm_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS
+volatile struct st_rscan_from_rscan0tmidp*  RSCAN_FROM_RSCAN0_TMIDp[ RSCAN_FROM_RSCAN0_TMIDp_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS
+volatile struct st_rscan_from_rscan0rfidm*  RSCAN_FROM_RSCAN0_RFIDm[ RSCAN_FROM_RSCAN0_RFIDm_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS
+volatile struct st_rscan_from_rscan0rmidp*  RSCAN_FROM_RSCAN0_RMIDp[ RSCAN_FROM_RSCAN0_RMIDp_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS
+volatile struct st_rscan_from_rscan0gaflidj*  RSCAN_FROM_RSCAN0_GAFLIDj[ RSCAN_FROM_RSCAN0_GAFLIDj_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS
+volatile struct st_rscan_from_rscan0cncfg*  RSCAN_FROM_RSCAN0_CnCFG[ RSCAN_FROM_RSCAN0_CnCFG_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS */
+/* End of channel array defines of RSCAN0 (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
 /* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,27 +18,173 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : rspi_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef RSPI_IODEFINE_H
 #define RSPI_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-#include "reg32_t.h"
+#define RSPI0   (*(struct st_rspi    *)0xE800C800uL) /* RSPI0 */
+#define RSPI1   (*(struct st_rspi    *)0xE800D000uL) /* RSPI1 */
+#define RSPI2   (*(struct st_rspi    *)0xE800D800uL) /* RSPI2 */
+#define RSPI3   (*(struct st_rspi    *)0xE800E000uL) /* RSPI3 */
+#define RSPI4   (*(struct st_rspi    *)0xE800E800uL) /* RSPI4 */
+
+
+/* Start of channel array defines of RSPI */
+
+/* Channel array defines of RSPI */
+/*(Sample) value = RSPI[ channel ]->SPCR; */
+#define RSPI_COUNT  (5)
+#define RSPI_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of RSPI */
+
 
-struct st_rspi
-{                                                          /* RSPI             */
+#define SPCR_0 (RSPI0.SPCR)
+#define SSLP_0 (RSPI0.SSLP)
+#define SPPCR_0 (RSPI0.SPPCR)
+#define SPSR_0 (RSPI0.SPSR)
+#define SPDR_0   (RSPI0.SPDR.UINT32)
+#define SPDR_0L  (RSPI0.SPDR.UINT16[R_IO_L])
+#define SPDR_0H  (RSPI0.SPDR.UINT16[R_IO_H])
+#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL])
+#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH])
+#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL])
+#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH])
+#define SPSCR_0 (RSPI0.SPSCR)
+#define SPSSR_0 (RSPI0.SPSSR)
+#define SPBR_0 (RSPI0.SPBR)
+#define SPDCR_0 (RSPI0.SPDCR)
+#define SPCKD_0 (RSPI0.SPCKD)
+#define SSLND_0 (RSPI0.SSLND)
+#define SPND_0 (RSPI0.SPND)
+#define SPCMD0_0 (RSPI0.SPCMD0)
+#define SPCMD1_0 (RSPI0.SPCMD1)
+#define SPCMD2_0 (RSPI0.SPCMD2)
+#define SPCMD3_0 (RSPI0.SPCMD3)
+#define SPBFCR_0 (RSPI0.SPBFCR)
+#define SPBFDR_0 (RSPI0.SPBFDR)
+#define SPCR_1 (RSPI1.SPCR)
+#define SSLP_1 (RSPI1.SSLP)
+#define SPPCR_1 (RSPI1.SPPCR)
+#define SPSR_1 (RSPI1.SPSR)
+#define SPDR_1   (RSPI1.SPDR.UINT32)
+#define SPDR_1L  (RSPI1.SPDR.UINT16[R_IO_L])
+#define SPDR_1H  (RSPI1.SPDR.UINT16[R_IO_H])
+#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL])
+#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH])
+#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL])
+#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH])
+#define SPSCR_1 (RSPI1.SPSCR)
+#define SPSSR_1 (RSPI1.SPSSR)
+#define SPBR_1 (RSPI1.SPBR)
+#define SPDCR_1 (RSPI1.SPDCR)
+#define SPCKD_1 (RSPI1.SPCKD)
+#define SSLND_1 (RSPI1.SSLND)
+#define SPND_1 (RSPI1.SPND)
+#define SPCMD0_1 (RSPI1.SPCMD0)
+#define SPCMD1_1 (RSPI1.SPCMD1)
+#define SPCMD2_1 (RSPI1.SPCMD2)
+#define SPCMD3_1 (RSPI1.SPCMD3)
+#define SPBFCR_1 (RSPI1.SPBFCR)
+#define SPBFDR_1 (RSPI1.SPBFDR)
+#define SPCR_2 (RSPI2.SPCR)
+#define SSLP_2 (RSPI2.SSLP)
+#define SPPCR_2 (RSPI2.SPPCR)
+#define SPSR_2 (RSPI2.SPSR)
+#define SPDR_2   (RSPI2.SPDR.UINT32)
+#define SPDR_2L  (RSPI2.SPDR.UINT16[R_IO_L])
+#define SPDR_2H  (RSPI2.SPDR.UINT16[R_IO_H])
+#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL])
+#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH])
+#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL])
+#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH])
+#define SPSCR_2 (RSPI2.SPSCR)
+#define SPSSR_2 (RSPI2.SPSSR)
+#define SPBR_2 (RSPI2.SPBR)
+#define SPDCR_2 (RSPI2.SPDCR)
+#define SPCKD_2 (RSPI2.SPCKD)
+#define SSLND_2 (RSPI2.SSLND)
+#define SPND_2 (RSPI2.SPND)
+#define SPCMD0_2 (RSPI2.SPCMD0)
+#define SPCMD1_2 (RSPI2.SPCMD1)
+#define SPCMD2_2 (RSPI2.SPCMD2)
+#define SPCMD3_2 (RSPI2.SPCMD3)
+#define SPBFCR_2 (RSPI2.SPBFCR)
+#define SPBFDR_2 (RSPI2.SPBFDR)
+#define SPCR_3 (RSPI3.SPCR)
+#define SSLP_3 (RSPI3.SSLP)
+#define SPPCR_3 (RSPI3.SPPCR)
+#define SPSR_3 (RSPI3.SPSR)
+#define SPDR_3   (RSPI3.SPDR.UINT32)
+#define SPDR_3L  (RSPI3.SPDR.UINT16[R_IO_L])
+#define SPDR_3H  (RSPI3.SPDR.UINT16[R_IO_H])
+#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL])
+#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH])
+#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL])
+#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH])
+#define SPSCR_3 (RSPI3.SPSCR)
+#define SPSSR_3 (RSPI3.SPSSR)
+#define SPBR_3 (RSPI3.SPBR)
+#define SPDCR_3 (RSPI3.SPDCR)
+#define SPCKD_3 (RSPI3.SPCKD)
+#define SSLND_3 (RSPI3.SSLND)
+#define SPND_3 (RSPI3.SPND)
+#define SPCMD0_3 (RSPI3.SPCMD0)
+#define SPCMD1_3 (RSPI3.SPCMD1)
+#define SPCMD2_3 (RSPI3.SPCMD2)
+#define SPCMD3_3 (RSPI3.SPCMD3)
+#define SPBFCR_3 (RSPI3.SPBFCR)
+#define SPBFDR_3 (RSPI3.SPBFDR)
+#define SPCR_4 (RSPI4.SPCR)
+#define SSLP_4 (RSPI4.SSLP)
+#define SPPCR_4 (RSPI4.SPPCR)
+#define SPSR_4 (RSPI4.SPSR)
+#define SPDR_4   (RSPI4.SPDR.UINT32)
+#define SPDR_4L  (RSPI4.SPDR.UINT16[R_IO_L])
+#define SPDR_4H  (RSPI4.SPDR.UINT16[R_IO_H])
+#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL])
+#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH])
+#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL])
+#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH])
+#define SPSCR_4 (RSPI4.SPSCR)
+#define SPSSR_4 (RSPI4.SPSSR)
+#define SPBR_4 (RSPI4.SPBR)
+#define SPDCR_4 (RSPI4.SPDCR)
+#define SPCKD_4 (RSPI4.SPCKD)
+#define SSLND_4 (RSPI4.SSLND)
+#define SPND_4 (RSPI4.SPND)
+#define SPCMD0_4 (RSPI4.SPCMD0)
+#define SPCMD1_4 (RSPI4.SPCMD1)
+#define SPCMD2_4 (RSPI4.SPCMD2)
+#define SPCMD3_4 (RSPI4.SPCMD3)
+#define SPBFCR_4 (RSPI4.SPBFCR)
+#define SPBFDR_4 (RSPI4.SPBFDR)
+
+#define SPCMD_COUNT (4)
+
+
+typedef struct st_rspi
+{
+                                                           /* RSPI             */
     volatile uint8_t   SPCR;                                   /*  SPCR            */
     volatile uint8_t   SSLP;                                   /*  SSLP            */
     volatile uint8_t   SPPCR;                                  /*  SPPCR           */
     volatile uint8_t   SPSR;                                   /*  SPSR            */
-    union reg32_t  SPDR;                          /*  SPDR            */
+    union iodefine_reg32_t  SPDR;                          /*  SPDR            */
     
     volatile uint8_t   SPSCR;                                  /*  SPSCR           */
     volatile uint8_t   SPSSR;                                  /*  SPSSR           */
@@ -48,7 +194,8 @@
     volatile uint8_t   SSLND;                                  /*  SSLND           */
     volatile uint8_t   SPND;                                   /*  SPND            */
     volatile uint8_t   dummy1[1];                              /*                  */
-#define SPCMD_COUNT 4
+
+/* #define SPCMD_COUNT (4) */
     volatile uint16_t SPCMD0;                                 /*  SPCMD0          */
     volatile uint16_t SPCMD1;                                 /*  SPCMD1          */
     volatile uint16_t SPCMD2;                                 /*  SPCMD2          */
@@ -57,148 +204,21 @@
     volatile uint8_t   SPBFCR;                                 /*  SPBFCR          */
     volatile uint8_t   dummy3[1];                              /*                  */
     volatile uint16_t SPBFDR;                                 /*  SPBFDR          */
-};
-
-
-#define RSPI0   (*(struct st_rspi    *)0xE800C800uL) /* RSPI0 */
-#define RSPI1   (*(struct st_rspi    *)0xE800D000uL) /* RSPI1 */
-#define RSPI2   (*(struct st_rspi    *)0xE800D800uL) /* RSPI2 */
-#define RSPI3   (*(struct st_rspi    *)0xE800E000uL) /* RSPI3 */
-#define RSPI4   (*(struct st_rspi    *)0xE800E800uL) /* RSPI4 */
-
-
-/* Start of channnel array defines of RSPI */
-
-/* Channnel array defines of RSPI */
-/*(Sample) value = RSPI[ channel ]->SPCR; */
-#define RSPI_COUNT  5
-#define RSPI_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of RSPI */
+} r_io_rspi_t;
 
 
-#define SPCR_0 RSPI0.SPCR
-#define SSLP_0 RSPI0.SSLP
-#define SPPCR_0 RSPI0.SPPCR
-#define SPSR_0 RSPI0.SPSR
-#define SPDR_0   RSPI0.SPDR.UINT32
-#define SPDR_0L  RSPI0.SPDR.UINT16[L]
-#define SPDR_0H  RSPI0.SPDR.UINT16[H]
-#define SPDR_0LL RSPI0.SPDR.UINT8[LL]
-#define SPDR_0LH RSPI0.SPDR.UINT8[LH]
-#define SPDR_0HL RSPI0.SPDR.UINT8[HL]
-#define SPDR_0HH RSPI0.SPDR.UINT8[HH]
-#define SPSCR_0 RSPI0.SPSCR
-#define SPSSR_0 RSPI0.SPSSR
-#define SPBR_0 RSPI0.SPBR
-#define SPDCR_0 RSPI0.SPDCR
-#define SPCKD_0 RSPI0.SPCKD
-#define SSLND_0 RSPI0.SSLND
-#define SPND_0 RSPI0.SPND
-#define SPCMD0_0 RSPI0.SPCMD0
-#define SPCMD1_0 RSPI0.SPCMD1
-#define SPCMD2_0 RSPI0.SPCMD2
-#define SPCMD3_0 RSPI0.SPCMD3
-#define SPBFCR_0 RSPI0.SPBFCR
-#define SPBFDR_0 RSPI0.SPBFDR
-#define SPCR_1 RSPI1.SPCR
-#define SSLP_1 RSPI1.SSLP
-#define SPPCR_1 RSPI1.SPPCR
-#define SPSR_1 RSPI1.SPSR
-#define SPDR_1   RSPI1.SPDR.UINT32
-#define SPDR_1L  RSPI1.SPDR.UINT16[L]
-#define SPDR_1H  RSPI1.SPDR.UINT16[H]
-#define SPDR_1LL RSPI1.SPDR.UINT8[LL]
-#define SPDR_1LH RSPI1.SPDR.UINT8[LH]
-#define SPDR_1HL RSPI1.SPDR.UINT8[HL]
-#define SPDR_1HH RSPI1.SPDR.UINT8[HH]
-#define SPSCR_1 RSPI1.SPSCR
-#define SPSSR_1 RSPI1.SPSSR
-#define SPBR_1 RSPI1.SPBR
-#define SPDCR_1 RSPI1.SPDCR
-#define SPCKD_1 RSPI1.SPCKD
-#define SSLND_1 RSPI1.SSLND
-#define SPND_1 RSPI1.SPND
-#define SPCMD0_1 RSPI1.SPCMD0
-#define SPCMD1_1 RSPI1.SPCMD1
-#define SPCMD2_1 RSPI1.SPCMD2
-#define SPCMD3_1 RSPI1.SPCMD3
-#define SPBFCR_1 RSPI1.SPBFCR
-#define SPBFDR_1 RSPI1.SPBFDR
-#define SPCR_2 RSPI2.SPCR
-#define SSLP_2 RSPI2.SSLP
-#define SPPCR_2 RSPI2.SPPCR
-#define SPSR_2 RSPI2.SPSR
-#define SPDR_2   RSPI2.SPDR.UINT32
-#define SPDR_2L  RSPI2.SPDR.UINT16[L]
-#define SPDR_2H  RSPI2.SPDR.UINT16[H]
-#define SPDR_2LL RSPI2.SPDR.UINT8[LL]
-#define SPDR_2LH RSPI2.SPDR.UINT8[LH]
-#define SPDR_2HL RSPI2.SPDR.UINT8[HL]
-#define SPDR_2HH RSPI2.SPDR.UINT8[HH]
-#define SPSCR_2 RSPI2.SPSCR
-#define SPSSR_2 RSPI2.SPSSR
-#define SPBR_2 RSPI2.SPBR
-#define SPDCR_2 RSPI2.SPDCR
-#define SPCKD_2 RSPI2.SPCKD
-#define SSLND_2 RSPI2.SSLND
-#define SPND_2 RSPI2.SPND
-#define SPCMD0_2 RSPI2.SPCMD0
-#define SPCMD1_2 RSPI2.SPCMD1
-#define SPCMD2_2 RSPI2.SPCMD2
-#define SPCMD3_2 RSPI2.SPCMD3
-#define SPBFCR_2 RSPI2.SPBFCR
-#define SPBFDR_2 RSPI2.SPBFDR
-#define SPCR_3 RSPI3.SPCR
-#define SSLP_3 RSPI3.SSLP
-#define SPPCR_3 RSPI3.SPPCR
-#define SPSR_3 RSPI3.SPSR
-#define SPDR_3   RSPI3.SPDR.UINT32
-#define SPDR_3L  RSPI3.SPDR.UINT16[L]
-#define SPDR_3H  RSPI3.SPDR.UINT16[H]
-#define SPDR_3LL RSPI3.SPDR.UINT8[LL]
-#define SPDR_3LH RSPI3.SPDR.UINT8[LH]
-#define SPDR_3HL RSPI3.SPDR.UINT8[HL]
-#define SPDR_3HH RSPI3.SPDR.UINT8[HH]
-#define SPSCR_3 RSPI3.SPSCR
-#define SPSSR_3 RSPI3.SPSSR
-#define SPBR_3 RSPI3.SPBR
-#define SPDCR_3 RSPI3.SPDCR
-#define SPCKD_3 RSPI3.SPCKD
-#define SSLND_3 RSPI3.SSLND
-#define SPND_3 RSPI3.SPND
-#define SPCMD0_3 RSPI3.SPCMD0
-#define SPCMD1_3 RSPI3.SPCMD1
-#define SPCMD2_3 RSPI3.SPCMD2
-#define SPCMD3_3 RSPI3.SPCMD3
-#define SPBFCR_3 RSPI3.SPBFCR
-#define SPBFDR_3 RSPI3.SPBFDR
-#define SPCR_4 RSPI4.SPCR
-#define SSLP_4 RSPI4.SSLP
-#define SPPCR_4 RSPI4.SPPCR
-#define SPSR_4 RSPI4.SPSR
-#define SPDR_4   RSPI4.SPDR.UINT32
-#define SPDR_4L  RSPI4.SPDR.UINT16[L]
-#define SPDR_4H  RSPI4.SPDR.UINT16[H]
-#define SPDR_4LL RSPI4.SPDR.UINT8[LL]
-#define SPDR_4LH RSPI4.SPDR.UINT8[LH]
-#define SPDR_4HL RSPI4.SPDR.UINT8[HL]
-#define SPDR_4HH RSPI4.SPDR.UINT8[HH]
-#define SPSCR_4 RSPI4.SPSCR
-#define SPSSR_4 RSPI4.SPSSR
-#define SPBR_4 RSPI4.SPBR
-#define SPDCR_4 RSPI4.SPDCR
-#define SPCKD_4 RSPI4.SPCKD
-#define SSLND_4 RSPI4.SSLND
-#define SPND_4 RSPI4.SPND
-#define SPCMD0_4 RSPI4.SPCMD0
-#define SPCMD1_4 RSPI4.SPCMD1
-#define SPCMD2_4 RSPI4.SPCMD2
-#define SPCMD3_4 RSPI4.SPCMD3
-#define SPBFCR_4 RSPI4.SPBFCR
-#define SPBFDR_4 RSPI4.SPBFDR
+/* Channel array defines of RSPI (2)*/
+#ifdef  DECLARE_RSPI_CHANNELS
+volatile struct st_rspi*  RSPI[ RSPI_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSPI_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSPI_CHANNELS */
+/* End of channel array defines of RSPI (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,50 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : rtc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef RTC_IODEFINE_H
 #define RTC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_rtc
-{                                                          /* RTC              */
+#define RTC     (*(struct st_rtc     *)0xFCFF1000uL) /* RTC */
+
+
+#define RTCR64CNT (RTC.R64CNT)
+#define RTCRSECCNT (RTC.RSECCNT)
+#define RTCRMINCNT (RTC.RMINCNT)
+#define RTCRHRCNT (RTC.RHRCNT)
+#define RTCRWKCNT (RTC.RWKCNT)
+#define RTCRDAYCNT (RTC.RDAYCNT)
+#define RTCRMONCNT (RTC.RMONCNT)
+#define RTCRYRCNT (RTC.RYRCNT)
+#define RTCRSECAR (RTC.RSECAR)
+#define RTCRMINAR (RTC.RMINAR)
+#define RTCRHRAR (RTC.RHRAR)
+#define RTCRWKAR (RTC.RWKAR)
+#define RTCRDAYAR (RTC.RDAYAR)
+#define RTCRMONAR (RTC.RMONAR)
+#define RTCRCR1 (RTC.RCR1)
+#define RTCRCR2 (RTC.RCR2)
+#define RTCRYRAR (RTC.RYRAR)
+#define RTCRCR3 (RTC.RCR3)
+#define RTCRCR5 (RTC.RCR5)
+#define RTCRFRH (RTC.RFRH)
+#define RTCRFRL (RTC.RFRL)
+
+
+typedef struct st_rtc
+{
+                                                           /* RTC              */
     volatile uint8_t   R64CNT;                                 /*  R64CNT          */
     volatile uint8_t   dummy537[1];                            /*                  */
     volatile uint8_t   RSECCNT;                                /*  RSECCNT         */
@@ -71,32 +101,11 @@
     volatile uint8_t   dummy554[3];                            /*                  */
     volatile uint16_t RFRH;                                   /*  RFRH            */
     volatile uint16_t RFRL;                                   /*  RFRL            */
-};
-
-
-#define RTC     (*(struct st_rtc     *)0xFCFF1000uL) /* RTC */
+} r_io_rtc_t;
 
 
-#define RTCR64CNT RTC.R64CNT
-#define RTCRSECCNT RTC.RSECCNT
-#define RTCRMINCNT RTC.RMINCNT
-#define RTCRHRCNT RTC.RHRCNT
-#define RTCRWKCNT RTC.RWKCNT
-#define RTCRDAYCNT RTC.RDAYCNT
-#define RTCRMONCNT RTC.RMONCNT
-#define RTCRYRCNT RTC.RYRCNT
-#define RTCRSECAR RTC.RSECAR
-#define RTCRMINAR RTC.RMINAR
-#define RTCRHRAR RTC.RHRAR
-#define RTCRWKAR RTC.RWKAR
-#define RTCRDAYAR RTC.RDAYAR
-#define RTCRMONAR RTC.RMONAR
-#define RTCRCR1 RTC.RCR1
-#define RTCRCR2 RTC.RCR2
-#define RTCRYRAR RTC.RYRAR
-#define RTCRCR3 RTC.RCR3
-#define RTCRCR5 RTC.RCR5
-#define RTCRFRH RTC.RFRH
-#define RTCRFRL RTC.RFRL
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,21 +18,137 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : scif_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SCIF_IODEFINE_H
 #define SCIF_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
 /* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_scif
-{                                                          /* SCIF             */
+#define SCIF0   (*(struct st_scif    *)0xE8007000uL) /* SCIF0 */
+#define SCIF1   (*(struct st_scif    *)0xE8007800uL) /* SCIF1 */
+#define SCIF2   (*(struct st_scif    *)0xE8008000uL) /* SCIF2 */
+#define SCIF3   (*(struct st_scif    *)0xE8008800uL) /* SCIF3 */
+#define SCIF4   (*(struct st_scif    *)0xE8009000uL) /* SCIF4 */
+#define SCIF5   (*(struct st_scif    *)0xE8009800uL) /* SCIF5 */
+#define SCIF6   (*(struct st_scif    *)0xE800A000uL) /* SCIF6 */
+#define SCIF7   (*(struct st_scif    *)0xE800A800uL) /* SCIF7 */
+
+
+/* Start of channel array defines of SCIF */
+
+/* Channel array defines of SCIF */
+/*(Sample) value = SCIF[ channel ]->SCSMR; */
+#define SCIF_COUNT  (8)
+#define SCIF_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SCIF */
+
+
+#define SCSMR_0 (SCIF0.SCSMR)
+#define SCBRR_0 (SCIF0.SCBRR)
+#define SCSCR_0 (SCIF0.SCSCR)
+#define SCFTDR_0 (SCIF0.SCFTDR)
+#define SCFSR_0 (SCIF0.SCFSR)
+#define SCFRDR_0 (SCIF0.SCFRDR)
+#define SCFCR_0 (SCIF0.SCFCR)
+#define SCFDR_0 (SCIF0.SCFDR)
+#define SCSPTR_0 (SCIF0.SCSPTR)
+#define SCLSR_0 (SCIF0.SCLSR)
+#define SCEMR_0 (SCIF0.SCEMR)
+#define SCSMR_1 (SCIF1.SCSMR)
+#define SCBRR_1 (SCIF1.SCBRR)
+#define SCSCR_1 (SCIF1.SCSCR)
+#define SCFTDR_1 (SCIF1.SCFTDR)
+#define SCFSR_1 (SCIF1.SCFSR)
+#define SCFRDR_1 (SCIF1.SCFRDR)
+#define SCFCR_1 (SCIF1.SCFCR)
+#define SCFDR_1 (SCIF1.SCFDR)
+#define SCSPTR_1 (SCIF1.SCSPTR)
+#define SCLSR_1 (SCIF1.SCLSR)
+#define SCEMR_1 (SCIF1.SCEMR)
+#define SCSMR_2 (SCIF2.SCSMR)
+#define SCBRR_2 (SCIF2.SCBRR)
+#define SCSCR_2 (SCIF2.SCSCR)
+#define SCFTDR_2 (SCIF2.SCFTDR)
+#define SCFSR_2 (SCIF2.SCFSR)
+#define SCFRDR_2 (SCIF2.SCFRDR)
+#define SCFCR_2 (SCIF2.SCFCR)
+#define SCFDR_2 (SCIF2.SCFDR)
+#define SCSPTR_2 (SCIF2.SCSPTR)
+#define SCLSR_2 (SCIF2.SCLSR)
+#define SCEMR_2 (SCIF2.SCEMR)
+#define SCSMR_3 (SCIF3.SCSMR)
+#define SCBRR_3 (SCIF3.SCBRR)
+#define SCSCR_3 (SCIF3.SCSCR)
+#define SCFTDR_3 (SCIF3.SCFTDR)
+#define SCFSR_3 (SCIF3.SCFSR)
+#define SCFRDR_3 (SCIF3.SCFRDR)
+#define SCFCR_3 (SCIF3.SCFCR)
+#define SCFDR_3 (SCIF3.SCFDR)
+#define SCSPTR_3 (SCIF3.SCSPTR)
+#define SCLSR_3 (SCIF3.SCLSR)
+#define SCEMR_3 (SCIF3.SCEMR)
+#define SCSMR_4 (SCIF4.SCSMR)
+#define SCBRR_4 (SCIF4.SCBRR)
+#define SCSCR_4 (SCIF4.SCSCR)
+#define SCFTDR_4 (SCIF4.SCFTDR)
+#define SCFSR_4 (SCIF4.SCFSR)
+#define SCFRDR_4 (SCIF4.SCFRDR)
+#define SCFCR_4 (SCIF4.SCFCR)
+#define SCFDR_4 (SCIF4.SCFDR)
+#define SCSPTR_4 (SCIF4.SCSPTR)
+#define SCLSR_4 (SCIF4.SCLSR)
+#define SCEMR_4 (SCIF4.SCEMR)
+#define SCSMR_5 (SCIF5.SCSMR)
+#define SCBRR_5 (SCIF5.SCBRR)
+#define SCSCR_5 (SCIF5.SCSCR)
+#define SCFTDR_5 (SCIF5.SCFTDR)
+#define SCFSR_5 (SCIF5.SCFSR)
+#define SCFRDR_5 (SCIF5.SCFRDR)
+#define SCFCR_5 (SCIF5.SCFCR)
+#define SCFDR_5 (SCIF5.SCFDR)
+#define SCSPTR_5 (SCIF5.SCSPTR)
+#define SCLSR_5 (SCIF5.SCLSR)
+#define SCEMR_5 (SCIF5.SCEMR)
+#define SCSMR_6 (SCIF6.SCSMR)
+#define SCBRR_6 (SCIF6.SCBRR)
+#define SCSCR_6 (SCIF6.SCSCR)
+#define SCFTDR_6 (SCIF6.SCFTDR)
+#define SCFSR_6 (SCIF6.SCFSR)
+#define SCFRDR_6 (SCIF6.SCFRDR)
+#define SCFCR_6 (SCIF6.SCFCR)
+#define SCFDR_6 (SCIF6.SCFDR)
+#define SCSPTR_6 (SCIF6.SCSPTR)
+#define SCLSR_6 (SCIF6.SCLSR)
+#define SCEMR_6 (SCIF6.SCEMR)
+#define SCSMR_7 (SCIF7.SCSMR)
+#define SCBRR_7 (SCIF7.SCBRR)
+#define SCSCR_7 (SCIF7.SCSCR)
+#define SCFTDR_7 (SCIF7.SCFTDR)
+#define SCFSR_7 (SCIF7.SCFSR)
+#define SCFRDR_7 (SCIF7.SCFRDR)
+#define SCFCR_7 (SCIF7.SCFCR)
+#define SCFDR_7 (SCIF7.SCFDR)
+#define SCSPTR_7 (SCIF7.SCSPTR)
+#define SCLSR_7 (SCIF7.SCLSR)
+#define SCEMR_7 (SCIF7.SCEMR)
+
+
+typedef struct st_scif
+{
+                                                           /* SCIF             */
     volatile uint16_t SCSMR;                                  /*  SCSMR           */
     volatile uint8_t   dummy1[2];                              /*                  */
     volatile uint8_t   SCBRR;                                  /*  SCBRR           */
@@ -54,129 +170,21 @@
     volatile uint16_t SCLSR;                                  /*  SCLSR           */
     volatile uint8_t   dummy10[2];                             /*                  */
     volatile uint16_t SCEMR;                                  /*  SCEMR           */
-};
-
-
-#define SCIF0   (*(struct st_scif    *)0xE8007000uL) /* SCIF0 */
-#define SCIF1   (*(struct st_scif    *)0xE8007800uL) /* SCIF1 */
-#define SCIF2   (*(struct st_scif    *)0xE8008000uL) /* SCIF2 */
-#define SCIF3   (*(struct st_scif    *)0xE8008800uL) /* SCIF3 */
-#define SCIF4   (*(struct st_scif    *)0xE8009000uL) /* SCIF4 */
-#define SCIF5   (*(struct st_scif    *)0xE8009800uL) /* SCIF5 */
-#define SCIF6   (*(struct st_scif    *)0xE800A000uL) /* SCIF6 */
-#define SCIF7   (*(struct st_scif    *)0xE800A800uL) /* SCIF7 */
-
-#define P_SCIF0   (0xE8007000uL) /* SCIF0 */
-#define P_SCIF1   (0xE8007800uL) /* SCIF1 */
-#define P_SCIF2   (0xE8008000uL) /* SCIF2 */
-#define P_SCIF3   (0xE8008800uL) /* SCIF3 */
-#define P_SCIF4   (0xE8009000uL) /* SCIF4 */
-#define P_SCIF5   (0xE8009800uL) /* SCIF5 */
-#define P_SCIF6   (0xE800A000uL) /* SCIF6 */
-#define P_SCIF7   (0xE800A800uL) /* SCIF7 */
-
-
-/* Start of channnel array defines of SCIF */
-
-/* Channnel array defines of SCIF */
-/*(Sample) value = SCIF[ channel ]->SCSMR; */
-#define SCIF_COUNT  8
-#define SCIF_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of SCIF */
+} r_io_scif_t;
 
 
-#define SCSMR_0 SCIF0.SCSMR
-#define SCBRR_0 SCIF0.SCBRR
-#define SCSCR_0 SCIF0.SCSCR
-#define SCFTDR_0 SCIF0.SCFTDR
-#define SCFSR_0 SCIF0.SCFSR
-#define SCFRDR_0 SCIF0.SCFRDR
-#define SCFCR_0 SCIF0.SCFCR
-#define SCFDR_0 SCIF0.SCFDR
-#define SCSPTR_0 SCIF0.SCSPTR
-#define SCLSR_0 SCIF0.SCLSR
-#define SCEMR_0 SCIF0.SCEMR
-#define SCSMR_1 SCIF1.SCSMR
-#define SCBRR_1 SCIF1.SCBRR
-#define SCSCR_1 SCIF1.SCSCR
-#define SCFTDR_1 SCIF1.SCFTDR
-#define SCFSR_1 SCIF1.SCFSR
-#define SCFRDR_1 SCIF1.SCFRDR
-#define SCFCR_1 SCIF1.SCFCR
-#define SCFDR_1 SCIF1.SCFDR
-#define SCSPTR_1 SCIF1.SCSPTR
-#define SCLSR_1 SCIF1.SCLSR
-#define SCEMR_1 SCIF1.SCEMR
-#define SCSMR_2 SCIF2.SCSMR
-#define SCBRR_2 SCIF2.SCBRR
-#define SCSCR_2 SCIF2.SCSCR
-#define SCFTDR_2 SCIF2.SCFTDR
-#define SCFSR_2 SCIF2.SCFSR
-#define SCFRDR_2 SCIF2.SCFRDR
-#define SCFCR_2 SCIF2.SCFCR
-#define SCFDR_2 SCIF2.SCFDR
-#define SCSPTR_2 SCIF2.SCSPTR
-#define SCLSR_2 SCIF2.SCLSR
-#define SCEMR_2 SCIF2.SCEMR
-#define SCSMR_3 SCIF3.SCSMR
-#define SCBRR_3 SCIF3.SCBRR
-#define SCSCR_3 SCIF3.SCSCR
-#define SCFTDR_3 SCIF3.SCFTDR
-#define SCFSR_3 SCIF3.SCFSR
-#define SCFRDR_3 SCIF3.SCFRDR
-#define SCFCR_3 SCIF3.SCFCR
-#define SCFDR_3 SCIF3.SCFDR
-#define SCSPTR_3 SCIF3.SCSPTR
-#define SCLSR_3 SCIF3.SCLSR
-#define SCEMR_3 SCIF3.SCEMR
-#define SCSMR_4 SCIF4.SCSMR
-#define SCBRR_4 SCIF4.SCBRR
-#define SCSCR_4 SCIF4.SCSCR
-#define SCFTDR_4 SCIF4.SCFTDR
-#define SCFSR_4 SCIF4.SCFSR
-#define SCFRDR_4 SCIF4.SCFRDR
-#define SCFCR_4 SCIF4.SCFCR
-#define SCFDR_4 SCIF4.SCFDR
-#define SCSPTR_4 SCIF4.SCSPTR
-#define SCLSR_4 SCIF4.SCLSR
-#define SCEMR_4 SCIF4.SCEMR
-#define SCSMR_5 SCIF5.SCSMR
-#define SCBRR_5 SCIF5.SCBRR
-#define SCSCR_5 SCIF5.SCSCR
-#define SCFTDR_5 SCIF5.SCFTDR
-#define SCFSR_5 SCIF5.SCFSR
-#define SCFRDR_5 SCIF5.SCFRDR
-#define SCFCR_5 SCIF5.SCFCR
-#define SCFDR_5 SCIF5.SCFDR
-#define SCSPTR_5 SCIF5.SCSPTR
-#define SCLSR_5 SCIF5.SCLSR
-#define SCEMR_5 SCIF5.SCEMR
-#define SCSMR_6 SCIF6.SCSMR
-#define SCBRR_6 SCIF6.SCBRR
-#define SCSCR_6 SCIF6.SCSCR
-#define SCFTDR_6 SCIF6.SCFTDR
-#define SCFSR_6 SCIF6.SCFSR
-#define SCFRDR_6 SCIF6.SCFRDR
-#define SCFCR_6 SCIF6.SCFCR
-#define SCFDR_6 SCIF6.SCFDR
-#define SCSPTR_6 SCIF6.SCSPTR
-#define SCLSR_6 SCIF6.SCLSR
-#define SCEMR_6 SCIF6.SCEMR
-#define SCSMR_7 SCIF7.SCSMR
-#define SCBRR_7 SCIF7.SCBRR
-#define SCSCR_7 SCIF7.SCSCR
-#define SCFTDR_7 SCIF7.SCFTDR
-#define SCFSR_7 SCIF7.SCFSR
-#define SCFRDR_7 SCIF7.SCFRDR
-#define SCFCR_7 SCIF7.SCFCR
-#define SCFDR_7 SCIF7.SCFDR
-#define SCSPTR_7 SCIF7.SCSPTR
-#define SCLSR_7 SCIF7.SCLSR
-#define SCEMR_7 SCIF7.SCEMR
+/* Channel array defines of SCIF (2)*/
+#ifdef  DECLARE_SCIF_CHANNELS
+volatile struct st_scif*  SCIF[ SCIF_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCIF_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCIF_CHANNELS */
+/* End of channel array defines of SCIF (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
 /* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,63 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : scim_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SCIM_IODEFINE_H
 #define SCIM_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_scim
-{                                                          /* SCIM             */
+#define SCIM0   (*(struct st_scim    *)0xE800B000uL) /* SCIM0 */
+#define SCIM1   (*(struct st_scim    *)0xE800B800uL) /* SCIM1 */
+
+
+/* Start of channel array defines of SCIM */
+
+/* Channel array defines of SCIM */
+/*(Sample) value = SCIM[ channel ]->SMR; */
+#define SCIM_COUNT  (2)
+#define SCIM_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCIM0, &SCIM1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SCIM */
+
+
+#define SMR0 (SCIM0.SMR)
+#define BRR0 (SCIM0.BRR)
+#define SCR0 (SCIM0.SCR)
+#define TDR0 (SCIM0.TDR)
+#define SSR0 (SCIM0.SSR)
+#define RDR0 (SCIM0.RDR)
+#define SCMR0 (SCIM0.SCMR)
+#define SEMR0 (SCIM0.SEMR)
+#define SNFR0 (SCIM0.SNFR)
+#define SECR0 (SCIM0.SECR)
+#define SMR1 (SCIM1.SMR)
+#define BRR1 (SCIM1.BRR)
+#define SCR1 (SCIM1.SCR)
+#define TDR1 (SCIM1.TDR)
+#define SSR1 (SCIM1.SSR)
+#define RDR1 (SCIM1.RDR)
+#define SCMR1 (SCIM1.SCMR)
+#define SEMR1 (SCIM1.SEMR)
+#define SNFR1 (SCIM1.SNFR)
+#define SECR1 (SCIM1.SECR)
+
+
+typedef struct st_scim
+{
+                                                           /* SCIM             */
     volatile uint8_t   SMR;                                    /*  SMR             */
     volatile uint8_t   BRR;                                    /*  BRR             */
     volatile uint8_t   SCR;                                    /*  SCR             */
@@ -43,45 +86,21 @@
     volatile uint8_t   SNFR;                                   /*  SNFR            */
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint8_t   SECR;                                   /*  SECR            */
-};
-
-
-#define SCIM0   (*(struct st_scim    *)0xE800B000uL) /* SCIM0 */
-#define SCIM1   (*(struct st_scim    *)0xE800B800uL) /* SCIM1 */
-
-
-/* Start of channnel array defines of SCIM */
-
-/* Channnel array defines of SCIM */
-/*(Sample) value = SCIM[ channel ]->SMR; */
-#define SCIM_COUNT  2
-#define SCIM_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCIM0, &SCIM1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of SCIM */
+} r_io_scim_t;
 
 
-#define SMR0 SCIM0.SMR
-#define BRR0 SCIM0.BRR
-#define SCR0 SCIM0.SCR
-#define TDR0 SCIM0.TDR
-#define SSR0 SCIM0.SSR
-#define RDR0 SCIM0.RDR
-#define SCMR0 SCIM0.SCMR
-#define SEMR0 SCIM0.SEMR
-#define SNFR0 SCIM0.SNFR
-#define SECR0 SCIM0.SECR
-#define SMR1 SCIM1.SMR
-#define BRR1 SCIM1.BRR
-#define SCR1 SCIM1.SCR
-#define TDR1 SCIM1.TDR
-#define SSR1 SCIM1.SSR
-#define RDR1 SCIM1.RDR
-#define SCMR1 SCIM1.SCMR
-#define SEMR1 SCIM1.SEMR
-#define SNFR1 SCIM1.SNFR
-#define SECR1 SCIM1.SECR
+/* Channel array defines of SCIM (2)*/
+#ifdef  DECLARE_SCIM_CHANNELS
+volatile struct st_scim*  SCIM[ SCIM_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCIM_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCIM_CHANNELS */
+/* End of channel array defines of SCIM (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,61 +18,427 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : scux_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SCUX_IODEFINE_H
 #define SCUX_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_scux
-{                                                          /* SCUX             */
+#define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
+
+
+/* Start of channel array defines of SCUX */
+
+/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
+#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
+#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
+#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
+
+
+/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  (2)
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
+#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
+
+
+/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
+#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
+#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
+#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
+
+
+/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
+#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
+#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
+#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
+
+
+/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
+#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
+#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
+#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
+
+
+/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
+#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
+#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
+#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
+
+/* End of channel array defines of SCUX */
+
+
+#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0)
+#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0)
+#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1)
+#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1)
+#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2)
+#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2)
+#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3)
+#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3)
+#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0)
+#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0)
+#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1)
+#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1)
+#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2)
+#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2)
+#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3)
+#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3)
+#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0)
+#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0)
+#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0)
+#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0)
+#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0)
+#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0)
+#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0)
+#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1)
+#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1)
+#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1)
+#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1)
+#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1)
+#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1)
+#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1)
+#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2)
+#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2)
+#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2)
+#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2)
+#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2)
+#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2)
+#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2)
+#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3)
+#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3)
+#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3)
+#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3)
+#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3)
+#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3)
+#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3)
+#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0)
+#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0)
+#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0)
+#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0)
+#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0)
+#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0)
+#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1)
+#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1)
+#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1)
+#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1)
+#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1)
+#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1)
+#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2)
+#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2)
+#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2)
+#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2)
+#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2)
+#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2)
+#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3)
+#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3)
+#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3)
+#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3)
+#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3)
+#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3)
+#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0)
+#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0)
+#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0)
+#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0)
+#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0)
+#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0)
+#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0)
+#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0)
+#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0)
+#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0)
+#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0)
+#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0)
+#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0)
+#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0)
+#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0)
+#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0)
+#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0)
+#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0)
+#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0)
+#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0)
+#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0)
+#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0)
+#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0)
+#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0)
+#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0)
+#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1)
+#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1)
+#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1)
+#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1)
+#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1)
+#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1)
+#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1)
+#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1)
+#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1)
+#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1)
+#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1)
+#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1)
+#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1)
+#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1)
+#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1)
+#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1)
+#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1)
+#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1)
+#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1)
+#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1)
+#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1)
+#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1)
+#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1)
+#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1)
+#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1)
+#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0)
+#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0)
+#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0)
+#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0)
+#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0)
+#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0)
+#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0)
+#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0)
+#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0)
+#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0)
+#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0)
+#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0)
+#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0)
+#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0)
+#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0)
+#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0)
+#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0)
+#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0)
+#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0)
+#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0)
+#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0)
+#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1)
+#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1)
+#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1)
+#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1)
+#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1)
+#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1)
+#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1)
+#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1)
+#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1)
+#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1)
+#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1)
+#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1)
+#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1)
+#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1)
+#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1)
+#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1)
+#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1)
+#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1)
+#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1)
+#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1)
+#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1)
+#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2)
+#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2)
+#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2)
+#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2)
+#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2)
+#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2)
+#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2)
+#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2)
+#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2)
+#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2)
+#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2)
+#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2)
+#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2)
+#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2)
+#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2)
+#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2)
+#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2)
+#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2)
+#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2)
+#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2)
+#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2)
+#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3)
+#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3)
+#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3)
+#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3)
+#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3)
+#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3)
+#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3)
+#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3)
+#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3)
+#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3)
+#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3)
+#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3)
+#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3)
+#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3)
+#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3)
+#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3)
+#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3)
+#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3)
+#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3)
+#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3)
+#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3)
+#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0)
+#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0)
+#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0)
+#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0)
+#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0)
+#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0)
+#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0)
+#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0)
+#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0)
+#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0)
+#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0)
+#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM)
+#define SCUXDMACR_CIM (SCUX.DMACR_CIM)
+#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32)
+#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L])
+#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H])
+#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32)
+#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L])
+#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H])
+#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32)
+#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L])
+#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H])
+#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32)
+#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L])
+#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H])
+#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32)
+#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L])
+#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H])
+#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32)
+#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L])
+#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H])
+#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32)
+#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L])
+#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H])
+#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32)
+#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L])
+#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H])
+#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM)
+#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM)
+#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM)
+#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM)
+#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM)
+#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM)
+#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM)
+#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM)
+#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM)
+#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM)
+#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM)
+#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM)
+#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM)
+#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM)
+#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM)
+#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM)
+
+#define SCUX_DMATDnCIM_COUNT (4)
+#define SCUX_DMATUnCIM_COUNT (4)
+#define SCUX_FDTSELnCIM_COUNT (4)
+#define SCUX_FUTSELnCIM_COUNT (4)
+#define SCUX_SRCRSELnCIM_COUNT (4)
+
+
+typedef struct st_scux
+{
+                                                           /* SCUX             */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
     volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
     volatile uint8_t   dummy259[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_1;                           /*  IPCIR_IPC0_1    */
     volatile uint32_t  IPSLR_IPC0_1;                           /*  IPSLR_IPC0_1    */
     volatile uint8_t   dummy260[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_2;                           /*  IPCIR_IPC0_2    */
     volatile uint32_t  IPSLR_IPC0_2;                           /*  IPSLR_IPC0_2    */
     volatile uint8_t   dummy261[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_3;                           /*  IPCIR_IPC0_3    */
     volatile uint32_t  IPSLR_IPC0_3;                           /*  IPSLR_IPC0_3    */
     volatile uint8_t   dummy262[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
     volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
     volatile uint8_t   dummy263[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_1;                           /*  OPCIR_OPC0_1    */
     volatile uint32_t  OPSLR_OPC0_1;                           /*  OPSLR_OPC0_1    */
     volatile uint8_t   dummy264[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_2;                           /*  OPCIR_OPC0_2    */
     volatile uint32_t  OPSLR_OPC0_2;                           /*  OPSLR_OPC0_2    */
     volatile uint8_t   dummy265[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_3;                           /*  OPCIR_OPC0_3    */
     volatile uint32_t  OPSLR_OPC0_3;                           /*  OPSLR_OPC0_3    */
     volatile uint8_t   dummy266[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
     volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
@@ -82,8 +448,10 @@
     volatile uint32_t  DEVMR_FFD0_0;                           /*  DEVMR_FFD0_0    */
     volatile uint8_t   dummy267[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy268[224];                          /*                  */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_1;                           /*  FFDIR_FFD0_1    */
     volatile uint32_t  FDAIR_FFD0_1;                           /*  FDAIR_FFD0_1    */
@@ -93,8 +461,10 @@
     volatile uint32_t  DEVMR_FFD0_1;                           /*  DEVMR_FFD0_1    */
     volatile uint8_t   dummy269[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_1;                           /*  DEVCR_FFD0_1    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy270[224];                          /*                  */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_2;                           /*  FFDIR_FFD0_2    */
     volatile uint32_t  FDAIR_FFD0_2;                           /*  FDAIR_FFD0_2    */
@@ -104,8 +474,10 @@
     volatile uint32_t  DEVMR_FFD0_2;                           /*  DEVMR_FFD0_2    */
     volatile uint8_t   dummy271[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_2;                           /*  DEVCR_FFD0_2    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy272[224];                          /*                  */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_3;                           /*  FFDIR_FFD0_3    */
     volatile uint32_t  FDAIR_FFD0_3;                           /*  FDAIR_FFD0_3    */
@@ -115,8 +487,10 @@
     volatile uint32_t  DEVMR_FFD0_3;                           /*  DEVMR_FFD0_3    */
     volatile uint8_t   dummy273[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_3;                           /*  DEVCR_FFD0_3    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy274[224];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
     volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
@@ -125,8 +499,10 @@
     volatile uint32_t  UEVMR_FFU0_0;                           /*  UEVMR_FFU0_0    */
     volatile uint8_t   dummy275[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy276[228];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_1;                           /*  FFUIR_FFU0_1    */
     volatile uint32_t  FUAIR_FFU0_1;                           /*  FUAIR_FFU0_1    */
@@ -135,8 +511,10 @@
     volatile uint32_t  UEVMR_FFU0_1;                           /*  UEVMR_FFU0_1    */
     volatile uint8_t   dummy277[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_1;                           /*  UEVCR_FFU0_1    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy278[228];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_2;                           /*  FFUIR_FFU0_2    */
     volatile uint32_t  FUAIR_FFU0_2;                           /*  FUAIR_FFU0_2    */
@@ -145,8 +523,10 @@
     volatile uint32_t  UEVMR_FFU0_2;                           /*  UEVMR_FFU0_2    */
     volatile uint8_t   dummy279[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_2;                           /*  UEVCR_FFU0_2    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy280[228];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_3;                           /*  FFUIR_FFU0_3    */
     volatile uint32_t  FUAIR_FFU0_3;                           /*  FUAIR_FFU0_3    */
@@ -155,8 +535,10 @@
     volatile uint32_t  UEVMR_FFU0_3;                           /*  UEVMR_FFU0_3    */
     volatile uint8_t   dummy281[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_3;                           /*  UEVCR_FFU0_3    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy282[228];                          /*                  */
+
 /* start of struct st_scux_from_srcir0_2src0_n */
     volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
     volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
@@ -185,8 +567,10 @@
     volatile uint8_t   dummy284[4];                            /*                  */
     volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
     volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
+
 /* end of struct st_scux_from_srcir0_2src0_n */
     volatile uint8_t   dummy285[148];                          /*                  */
+
 /* start of struct st_scux_from_srcir0_2src0_n */
     volatile uint32_t  SRCIR0_2SRC0_1;                         /*  SRCIR0_2SRC0_1  */
     volatile uint32_t  SADIR0_2SRC0_1;                         /*  SADIR0_2SRC0_1  */
@@ -215,8 +599,10 @@
     volatile uint8_t   dummy287[4];                            /*                  */
     volatile uint32_t  SEVCR1_2SRC0_1;                         /*  SEVCR1_2SRC0_1  */
     volatile uint32_t  SRCIRR_2SRC0_1;                         /*  SRCIRR_2SRC0_1  */
+
 /* end of struct st_scux_from_srcir0_2src0_n */
     volatile uint8_t   dummy288[148];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
     volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
@@ -240,8 +626,10 @@
     volatile uint32_t  VEVMR_DVU0_0;                           /*  VEVMR_DVU0_0    */
     volatile uint8_t   dummy289[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy290[168];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_1;                           /*  DVUIR_DVU0_1    */
     volatile uint32_t  VADIR_DVU0_1;                           /*  VADIR_DVU0_1    */
@@ -265,8 +653,10 @@
     volatile uint32_t  VEVMR_DVU0_1;                           /*  VEVMR_DVU0_1    */
     volatile uint8_t   dummy291[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_1;                           /*  VEVCR_DVU0_1    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy292[168];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_2;                           /*  DVUIR_DVU0_2    */
     volatile uint32_t  VADIR_DVU0_2;                           /*  VADIR_DVU0_2    */
@@ -290,8 +680,10 @@
     volatile uint32_t  VEVMR_DVU0_2;                           /*  VEVMR_DVU0_2    */
     volatile uint8_t   dummy293[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_2;                           /*  VEVCR_DVU0_2    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy294[168];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_3;                           /*  DVUIR_DVU0_3    */
     volatile uint32_t  VADIR_DVU0_3;                           /*  VADIR_DVU0_3    */
@@ -315,6 +707,7 @@
     volatile uint32_t  VEVMR_DVU0_3;                           /*  VEVMR_DVU0_3    */
     volatile uint8_t   dummy295[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_3;                           /*  VEVCR_DVU0_3    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy296[168];                          /*                  */
     volatile uint32_t  MIXIR_MIX0_0;                           /*  MIXIR_MIX0_0    */
@@ -331,12 +724,14 @@
     volatile uint8_t   dummy297[212];                          /*                  */
     volatile uint32_t  SWRSR_CIM;                              /*  SWRSR_CIM       */
     volatile uint32_t  DMACR_CIM;                              /*  DMACR_CIM       */
-#define SCUX_DMATDn_CIM_COUNT 4
+
+/* #define SCUX_DMATDnCIM_COUNT (4) */
     union iodefine_reg32_16_t  DMATD0_CIM;                 /*  DMATD0_CIM      */
     union iodefine_reg32_16_t  DMATD1_CIM;                 /*  DMATD1_CIM      */
     union iodefine_reg32_16_t  DMATD2_CIM;                 /*  DMATD2_CIM      */
     union iodefine_reg32_16_t  DMATD3_CIM;                 /*  DMATD3_CIM      */
-#define SCUX_DMATUn_CIM_COUNT 4
+
+/* #define SCUX_DMATUnCIM_COUNT (4) */
     union iodefine_reg32_16_t  DMATU0_CIM;                 /*  DMATU0_CIM      */
     union iodefine_reg32_16_t  DMATU1_CIM;                 /*  DMATU1_CIM      */
     union iodefine_reg32_16_t  DMATU2_CIM;                 /*  DMATU2_CIM      */
@@ -344,45 +739,51 @@
     
     volatile uint8_t   dummy298[16];                           /*                  */
     volatile uint32_t  SSIRSEL_CIM;                            /*  SSIRSEL_CIM     */
-#define SCUX_FDTSELn_CIM_COUNT 4
+
+/* #define SCUX_FDTSELnCIM_COUNT (4) */
     volatile uint32_t  FDTSEL0_CIM;                            /*  FDTSEL0_CIM     */
     volatile uint32_t  FDTSEL1_CIM;                            /*  FDTSEL1_CIM     */
     volatile uint32_t  FDTSEL2_CIM;                            /*  FDTSEL2_CIM     */
     volatile uint32_t  FDTSEL3_CIM;                            /*  FDTSEL3_CIM     */
-#define SCUX_FUTSELn_CIM_COUNT 4
+
+/* #define SCUX_FUTSELnCIM_COUNT (4) */
     volatile uint32_t  FUTSEL0_CIM;                            /*  FUTSEL0_CIM     */
     volatile uint32_t  FUTSEL1_CIM;                            /*  FUTSEL1_CIM     */
     volatile uint32_t  FUTSEL2_CIM;                            /*  FUTSEL2_CIM     */
     volatile uint32_t  FUTSEL3_CIM;                            /*  FUTSEL3_CIM     */
     volatile uint32_t  SSIPMD_CIM;                             /*  SSIPMD_CIM      */
     volatile uint32_t  SSICTRL_CIM;                            /*  SSICTRL_CIM     */
-#define SCUX_SRCRSELn_CIM_COUNT 4
+
+/* #define SCUX_SRCRSELnCIM_COUNT (4) */
     volatile uint32_t  SRCRSEL0_CIM;                           /*  SRCRSEL0_CIM    */
     volatile uint32_t  SRCRSEL1_CIM;                           /*  SRCRSEL1_CIM    */
     volatile uint32_t  SRCRSEL2_CIM;                           /*  SRCRSEL2_CIM    */
     volatile uint32_t  SRCRSEL3_CIM;                           /*  SRCRSEL3_CIM    */
     volatile uint32_t  MIXRSEL_CIM;                            /*  MIXRSEL_CIM     */
-};
+} r_io_scux_t;
 
 
-struct st_scux_from_ipcir_ipc0_n
+typedef struct st_scux_from_ipcir_ipc0_n
 {
+ 
     volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
     volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
     volatile uint8_t   dummy1[248];                            /*                  */
-};
+} r_io_scux_from_ipcir_ipc0_n_t;
 
 
-struct st_scux_from_opcir_opc0_n
+typedef struct st_scux_from_opcir_opc0_n
 {
+ 
     volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
     volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
     volatile uint8_t   dummy1[248];                            /*                  */
-};
+} r_io_scux_from_opcir_opc0_n_t;
 
 
-struct st_scux_from_ffdir_ffd0_n
+typedef struct st_scux_from_ffdir_ffd0_n
 {
+ 
     volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
     volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
     volatile uint32_t  DRQSR_FFD0_0;                           /*  DRQSR_FFD0_0    */
@@ -391,11 +792,12 @@
     volatile uint32_t  DEVMR_FFD0_0;                           /*  DEVMR_FFD0_0    */
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
-};
+} r_io_scux_from_ffdir_ffd0_n_t;
 
 
-struct st_scux_from_ffuir_ffu0_n
+typedef struct st_scux_from_ffuir_ffu0_n
 {
+ 
     volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
     volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
     volatile uint32_t  URQSR_FFU0_0;                           /*  URQSR_FFU0_0    */
@@ -403,11 +805,12 @@
     volatile uint32_t  UEVMR_FFU0_0;                           /*  UEVMR_FFU0_0    */
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
-};
+} r_io_scux_from_ffuir_ffu0_n_t;
 
 
-struct st_scux_from_srcir0_2src0_n
+typedef struct st_scux_from_srcir0_2src0_n
 {
+ 
     volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
     volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
     volatile uint32_t  SRCBR0_2SRC0_0;                         /*  SRCBR0_2SRC0_0  */
@@ -435,11 +838,12 @@
     volatile uint8_t   dummy2[4];                              /*                  */
     volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
     volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
-};
+} r_io_scux_from_srcir0_2src0_n_t;
 
 
-struct st_scux_from_dvuir_dvu0_n
+typedef struct st_scux_from_dvuir_dvu0_n
 {
+ 
     volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
     volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
     volatile uint32_t  DVUBR_DVU0_0;                           /*  DVUBR_DVU0_0    */
@@ -462,347 +866,56 @@
     volatile uint32_t  VEVMR_DVU0_0;                           /*  VEVMR_DVU0_0    */
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
-};
-
-
-#define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
-
-
-/* Start of channnel array defines of SCUX */
-
-/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
-#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  4
-#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
-#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
-#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
-#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
-#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  2
-#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
-#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
-
-
-/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
-#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  4
-#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
-#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
-#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
-#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
-#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  4
-#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
-#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
-#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
-#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
-#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  4
-#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
-#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
-#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
-#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
-#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  4
-#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
-#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
-#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
-#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
-
-/* End of channnel array defines of SCUX */
+} r_io_scux_from_dvuir_dvu0_n_t;
 
 
-#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
-#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
-#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
-#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
-#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
-#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
-#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
-#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
-#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
-#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
-#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
-#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
-#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
-#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
-#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
-#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
-#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
-#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
-#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
-#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
-#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
-#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
-#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
-#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
-#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
-#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
-#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
-#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
-#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
-#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
-#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
-#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
-#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
-#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
-#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
-#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
-#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
-#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
-#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
-#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
-#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
-#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
-#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
-#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
-#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
-#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
-#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
-#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
-#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
-#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
-#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
-#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
-#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
-#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
-#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
-#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
-#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
-#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
-#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
-#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
-#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
-#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
-#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
-#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
-#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
-#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
-#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
-#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
-#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
-#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
-#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
-#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
-#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
-#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
-#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
-#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
-#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
-#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
-#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
-#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
-#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
-#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
-#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
-#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
-#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
-#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
-#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
-#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
-#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
-#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
-#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
-#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
-#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
-#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
-#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
-#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
-#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
-#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
-#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
-#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
-#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
-#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
-#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
-#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
-#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
-#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
-#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
-#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
-#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
-#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
-#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
-#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
-#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
-#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
-#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
-#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
-#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
-#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
-#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
-#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
-#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
-#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
-#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
-#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
-#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
-#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
-#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
-#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
-#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
-#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
-#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
-#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
-#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
-#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
-#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
-#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
-#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
-#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
-#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
-#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
-#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
-#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
-#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
-#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
-#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
-#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
-#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
-#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
-#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
-#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
-#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
-#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
-#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
-#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
-#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
-#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
-#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
-#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
-#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
-#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
-#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
-#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
-#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
-#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
-#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
-#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
-#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
-#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
-#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
-#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
-#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
-#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
-#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
-#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
-#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
-#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
-#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
-#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
-#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
-#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
-#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
-#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
-#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
-#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
-#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
-#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
-#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
-#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
-#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
-#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
-#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
-#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
-#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
-#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
-#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
-#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
-#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
-#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
-#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
-#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
-#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
-#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
-#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
-#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
-#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
-#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
-#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
-#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
-#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
-#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
-#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
-#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
-#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
-#define SCUXSWRSR_CIM SCUX.SWRSR_CIM
-#define SCUXDMACR_CIM SCUX.DMACR_CIM
-#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
-#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
-#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
-#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
-#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
-#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
-#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
-#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
-#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
-#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
-#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
-#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
-#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
-#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
-#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
-#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
-#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
-#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
-#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
-#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
-#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
-#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
-#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
-#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
-#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
-#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
-#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
-#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
-#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
-#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
-#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
-#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
-#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
-#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
-#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
-#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
-#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
-#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
-#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
-#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
+/* Channel array defines of SCUX (2)*/
+#ifdef  DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_dvuir_dvu0_n*  SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_srcir0_2src0_n*  SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ffuir_ffu0_n*  SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ffdir_ffd0_n*  SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_opcir_opc0_n*  SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ipcir_ipc0_n*  SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */
+/* End of channel array defines of SCUX (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,27 +18,20 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : sdg_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SDG_IODEFINE_H
 #define SDG_IODEFINE_H
-
-struct st_sdg
-{                                                          /* SDG              */
-    volatile uint8_t   SGCR1;                                  /*  SGCR1           */
-    volatile uint8_t   SGCSR;                                  /*  SGCSR           */
-    volatile uint8_t   SGCR2;                                  /*  SGCR2           */
-    volatile uint8_t   SGLR;                                   /*  SGLR            */
-    volatile uint8_t   SGTFR;                                  /*  SGTFR           */
-    volatile uint8_t   SGSFR;                                  /*  SGSFR           */
-};
-
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
 #define SDG0    (*(struct st_sdg     *)0xFCFF4800uL) /* SDG0 */
 #define SDG1    (*(struct st_sdg     *)0xFCFF4A00uL) /* SDG1 */
@@ -46,41 +39,69 @@
 #define SDG3    (*(struct st_sdg     *)0xFCFF4E00uL) /* SDG3 */
 
 
-/* Start of channnel array defines of SDG */
+/* Start of channel array defines of SDG */
 
-/* Channnel array defines of SDG */
+/* Channel array defines of SDG */
 /*(Sample) value = SDG[ channel ]->SGCR1; */
-#define SDG_COUNT  4
+#define SDG_COUNT  (4)
 #define SDG_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &SDG0, &SDG1, &SDG2, &SDG3 \
 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
 
-/* End of channnel array defines of SDG */
+/* End of channel array defines of SDG */
 
 
-#define SGCR1_0 SDG0.SGCR1
-#define SGCSR_0 SDG0.SGCSR
-#define SGCR2_0 SDG0.SGCR2
-#define SGLR_0 SDG0.SGLR
-#define SGTFR_0 SDG0.SGTFR
-#define SGSFR_0 SDG0.SGSFR
-#define SGCR1_1 SDG1.SGCR1
-#define SGCSR_1 SDG1.SGCSR
-#define SGCR2_1 SDG1.SGCR2
-#define SGLR_1 SDG1.SGLR
-#define SGTFR_1 SDG1.SGTFR
-#define SGSFR_1 SDG1.SGSFR
-#define SGCR1_2 SDG2.SGCR1
-#define SGCSR_2 SDG2.SGCSR
-#define SGCR2_2 SDG2.SGCR2
-#define SGLR_2 SDG2.SGLR
-#define SGTFR_2 SDG2.SGTFR
-#define SGSFR_2 SDG2.SGSFR
-#define SGCR1_3 SDG3.SGCR1
-#define SGCSR_3 SDG3.SGCSR
-#define SGCR2_3 SDG3.SGCR2
-#define SGLR_3 SDG3.SGLR
-#define SGTFR_3 SDG3.SGTFR
-#define SGSFR_3 SDG3.SGSFR
+#define SGCR1_0 (SDG0.SGCR1)
+#define SGCSR_0 (SDG0.SGCSR)
+#define SGCR2_0 (SDG0.SGCR2)
+#define SGLR_0 (SDG0.SGLR)
+#define SGTFR_0 (SDG0.SGTFR)
+#define SGSFR_0 (SDG0.SGSFR)
+#define SGCR1_1 (SDG1.SGCR1)
+#define SGCSR_1 (SDG1.SGCSR)
+#define SGCR2_1 (SDG1.SGCR2)
+#define SGLR_1 (SDG1.SGLR)
+#define SGTFR_1 (SDG1.SGTFR)
+#define SGSFR_1 (SDG1.SGSFR)
+#define SGCR1_2 (SDG2.SGCR1)
+#define SGCSR_2 (SDG2.SGCSR)
+#define SGCR2_2 (SDG2.SGCR2)
+#define SGLR_2 (SDG2.SGLR)
+#define SGTFR_2 (SDG2.SGTFR)
+#define SGSFR_2 (SDG2.SGSFR)
+#define SGCR1_3 (SDG3.SGCR1)
+#define SGCSR_3 (SDG3.SGCSR)
+#define SGCR2_3 (SDG3.SGCR2)
+#define SGLR_3 (SDG3.SGLR)
+#define SGTFR_3 (SDG3.SGTFR)
+#define SGSFR_3 (SDG3.SGSFR)
+
+
+typedef struct st_sdg
+{
+                                                           /* SDG              */
+    volatile uint8_t   SGCR1;                                  /*  SGCR1           */
+    volatile uint8_t   SGCSR;                                  /*  SGCSR           */
+    volatile uint8_t   SGCR2;                                  /*  SGCR2           */
+    volatile uint8_t   SGLR;                                   /*  SGLR            */
+    volatile uint8_t   SGTFR;                                  /*  SGTFR           */
+    volatile uint8_t   SGSFR;                                  /*  SGSFR           */
+} r_io_sdg_t;
+
+
+/* Channel array defines of SDG (2)*/
+#ifdef  DECLARE_SDG_CHANNELS
+volatile struct st_sdg*  SDG[ SDG_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SDG_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SDG_CHANNELS */
+/* End of channel array defines of SDG (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,19 +18,43 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : spdif_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SPDIF_IODEFINE_H
 #define SPDIF_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
-struct st_spdif
-{                                                          /* SPDIF            */
+#define SPDIF   (*(struct st_spdif   *)0xE8012000uL) /* SPDIF */
+
+
+#define SPDIFTLCA (SPDIF.TLCA)
+#define SPDIFTRCA (SPDIF.TRCA)
+#define SPDIFTLCS (SPDIF.TLCS)
+#define SPDIFTRCS (SPDIF.TRCS)
+#define SPDIFTUI (SPDIF.TUI)
+#define SPDIFRLCA (SPDIF.RLCA)
+#define SPDIFRRCA (SPDIF.RRCA)
+#define SPDIFRLCS (SPDIF.RLCS)
+#define SPDIFRRCS (SPDIF.RRCS)
+#define SPDIFRUI (SPDIF.RUI)
+#define SPDIFCTRL (SPDIF.CTRL)
+#define SPDIFSTAT (SPDIF.STAT)
+#define SPDIFTDAD (SPDIF.TDAD)
+#define SPDIFRDAD (SPDIF.RDAD)
+
+
+typedef struct st_spdif
+{
+                                                           /* SPDIF            */
     volatile uint32_t  TLCA;                                   /*  TLCA            */
     volatile uint32_t  TRCA;                                   /*  TRCA            */
     volatile uint32_t  TLCS;                                   /*  TLCS            */
@@ -45,24 +69,11 @@
     volatile uint32_t  STAT;                                   /*  STAT            */
     volatile uint32_t  TDAD;                                   /*  TDAD            */
     volatile uint32_t  RDAD;                                   /*  RDAD            */
-};
-
-
-#define SPDIF   (*(struct st_spdif   *)0xE8012000uL) /* SPDIF */
+} r_io_spdif_t;
 
 
-#define SPDIFTLCA SPDIF.TLCA
-#define SPDIFTRCA SPDIF.TRCA
-#define SPDIFTLCS SPDIF.TLCS
-#define SPDIFTRCS SPDIF.TRCS
-#define SPDIFTUI SPDIF.TUI
-#define SPDIFRLCA SPDIF.RLCA
-#define SPDIFRRCA SPDIF.RRCA
-#define SPDIFRLCS SPDIF.RLCS
-#define SPDIFRRCS SPDIF.RRCS
-#define SPDIFRUI SPDIF.RUI
-#define SPDIFCTRL SPDIF.CTRL
-#define SPDIFSTAT SPDIF.STAT
-#define SPDIFTDAD SPDIF.TDAD
-#define SPDIFRDAD SPDIF.RDAD
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,139 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : spibsc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SPIBSC_IODEFINE_H
 #define SPIBSC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_spibsc
-{                                                          /* SPIBSC           */
+#define SPIBSC0 (*(struct st_spibsc  *)0x3FEFA000uL) /* SPIBSC0 */
+#define SPIBSC1 (*(struct st_spibsc  *)0x3FEFB000uL) /* SPIBSC1 */
+
+
+/* Start of channel array defines of SPIBSC */
+
+/* Channel array defines of SPIBSC */
+/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
+#define SPIBSC_COUNT  (2)
+#define SPIBSC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SPIBSC0, &SPIBSC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SPIBSC */
+
+
+#define CMNCR_0 (SPIBSC0.CMNCR)
+#define SSLDR_0 (SPIBSC0.SSLDR)
+#define SPBCR_0 (SPIBSC0.SPBCR)
+#define DRCR_0 (SPIBSC0.DRCR)
+#define DRCMR_0 (SPIBSC0.DRCMR)
+#define DREAR_0 (SPIBSC0.DREAR)
+#define DROPR_0 (SPIBSC0.DROPR)
+#define DRENR_0 (SPIBSC0.DRENR)
+#define SMCR_0 (SPIBSC0.SMCR)
+#define SMCMR_0 (SPIBSC0.SMCMR)
+#define SMADR_0 (SPIBSC0.SMADR)
+#define SMOPR_0 (SPIBSC0.SMOPR)
+#define SMENR_0 (SPIBSC0.SMENR)
+#define SMRDR0_0   (SPIBSC0.SMRDR0.UINT32)
+#define SMRDR0_0L  (SPIBSC0.SMRDR0.UINT16[R_IO_L])
+#define SMRDR0_0H  (SPIBSC0.SMRDR0.UINT16[R_IO_H])
+#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL])
+#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH])
+#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL])
+#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH])
+#define SMRDR1_0   (SPIBSC0.SMRDR1.UINT32)
+#define SMRDR1_0L  (SPIBSC0.SMRDR1.UINT16[R_IO_L])
+#define SMRDR1_0H  (SPIBSC0.SMRDR1.UINT16[R_IO_H])
+#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL])
+#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH])
+#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL])
+#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH])
+#define SMWDR0_0   (SPIBSC0.SMWDR0.UINT32)
+#define SMWDR0_0L  (SPIBSC0.SMWDR0.UINT16[R_IO_L])
+#define SMWDR0_0H  (SPIBSC0.SMWDR0.UINT16[R_IO_H])
+#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL])
+#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH])
+#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL])
+#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH])
+#define SMWDR1_0   (SPIBSC0.SMWDR1.UINT32)
+#define SMWDR1_0L  (SPIBSC0.SMWDR1.UINT16[R_IO_L])
+#define SMWDR1_0H  (SPIBSC0.SMWDR1.UINT16[R_IO_H])
+#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL])
+#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH])
+#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL])
+#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH])
+#define CMNSR_0 (SPIBSC0.CMNSR)
+#define CKDLY_0 (SPIBSC0.CKDLY)
+#define DRDMCR_0 (SPIBSC0.DRDMCR)
+#define DRDRENR_0 (SPIBSC0.DRDRENR)
+#define SMDMCR_0 (SPIBSC0.SMDMCR)
+#define SMDRENR_0 (SPIBSC0.SMDRENR)
+#define SPODLY_0 (SPIBSC0.SPODLY)
+#define CMNCR_1 (SPIBSC1.CMNCR)
+#define SSLDR_1 (SPIBSC1.SSLDR)
+#define SPBCR_1 (SPIBSC1.SPBCR)
+#define DRCR_1 (SPIBSC1.DRCR)
+#define DRCMR_1 (SPIBSC1.DRCMR)
+#define DREAR_1 (SPIBSC1.DREAR)
+#define DROPR_1 (SPIBSC1.DROPR)
+#define DRENR_1 (SPIBSC1.DRENR)
+#define SMCR_1 (SPIBSC1.SMCR)
+#define SMCMR_1 (SPIBSC1.SMCMR)
+#define SMADR_1 (SPIBSC1.SMADR)
+#define SMOPR_1 (SPIBSC1.SMOPR)
+#define SMENR_1 (SPIBSC1.SMENR)
+#define SMRDR0_1   (SPIBSC1.SMRDR0.UINT32)
+#define SMRDR0_1L  (SPIBSC1.SMRDR0.UINT16[R_IO_L])
+#define SMRDR0_1H  (SPIBSC1.SMRDR0.UINT16[R_IO_H])
+#define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL])
+#define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH])
+#define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL])
+#define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH])
+#define SMRDR1_1   (SPIBSC1.SMRDR1.UINT32)
+#define SMRDR1_1L  (SPIBSC1.SMRDR1.UINT16[R_IO_L])
+#define SMRDR1_1H  (SPIBSC1.SMRDR1.UINT16[R_IO_H])
+#define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL])
+#define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH])
+#define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL])
+#define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH])
+#define SMWDR0_1   (SPIBSC1.SMWDR0.UINT32)
+#define SMWDR0_1L  (SPIBSC1.SMWDR0.UINT16[R_IO_L])
+#define SMWDR0_1H  (SPIBSC1.SMWDR0.UINT16[R_IO_H])
+#define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL])
+#define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH])
+#define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL])
+#define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH])
+#define SMWDR1_1   (SPIBSC1.SMWDR1.UINT32)
+#define SMWDR1_1L  (SPIBSC1.SMWDR1.UINT16[R_IO_L])
+#define SMWDR1_1H  (SPIBSC1.SMWDR1.UINT16[R_IO_H])
+#define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL])
+#define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH])
+#define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL])
+#define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH])
+#define CMNSR_1 (SPIBSC1.CMNSR)
+#define CKDLY_1 (SPIBSC1.CKDLY)
+#define DRDMCR_1 (SPIBSC1.DRDMCR)
+#define DRDRENR_1 (SPIBSC1.DRDRENR)
+#define SMDMCR_1 (SPIBSC1.SMDMCR)
+#define SMDRENR_1 (SPIBSC1.SMDRENR)
+#define SPODLY_1 (SPIBSC1.SPODLY)
+
+
+typedef struct st_spibsc
+{
+                                                           /* SPIBSC           */
     volatile uint32_t  CMNCR;                                  /*  CMNCR           */
     volatile uint32_t  SSLDR;                                  /*  SSLDR           */
     volatile uint32_t  SPBCR;                                  /*  SPBCR           */
@@ -52,122 +171,29 @@
     union iodefine_reg32_t  SMWDR1;                        /*  SMWDR1          */
     
     volatile uint32_t  CMNSR;                                  /*  CMNSR           */
-    volatile uint8_t   dummy2[12];                             /*                  */
+    volatile uint8_t   dummy2[4];                              /*                  */
+    volatile uint32_t  CKDLY;                                  /*  CKDLY           */
+    volatile uint8_t   dummy3[4];                              /*                  */
     volatile uint32_t  DRDMCR;                                 /*  DRDMCR          */
     volatile uint32_t  DRDRENR;                                /*  DRDRENR         */
     volatile uint32_t  SMDMCR;                                 /*  SMDMCR          */
     volatile uint32_t  SMDRENR;                                /*  SMDRENR         */
-};
-
-
-#define SPIBSC0 (*(struct st_spibsc  *)0x3FEFA000uL) /* SPIBSC0 */
-#define SPIBSC1 (*(struct st_spibsc  *)0x3FEFB000uL) /* SPIBSC1 */
-
-
-/* Start of channnel array defines of SPIBSC */
-
-/* Channnel array defines of SPIBSC */
-/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
-#define SPIBSC_COUNT  2
-#define SPIBSC_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SPIBSC0, &SPIBSC1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of SPIBSC */
+    volatile uint32_t  SPODLY;                                 /*  SPODLY          */
+} r_io_spibsc_t;
 
 
-#define CMNCR_0 SPIBSC0.CMNCR
-#define SSLDR_0 SPIBSC0.SSLDR
-#define SPBCR_0 SPIBSC0.SPBCR
-#define DRCR_0 SPIBSC0.DRCR
-#define DRCMR_0 SPIBSC0.DRCMR
-#define DREAR_0 SPIBSC0.DREAR
-#define DROPR_0 SPIBSC0.DROPR
-#define DRENR_0 SPIBSC0.DRENR
-#define SMCR_0 SPIBSC0.SMCR
-#define SMCMR_0 SPIBSC0.SMCMR
-#define SMADR_0 SPIBSC0.SMADR
-#define SMOPR_0 SPIBSC0.SMOPR
-#define SMENR_0 SPIBSC0.SMENR
-#define SMRDR0_0   SPIBSC0.SMRDR0.UINT32
-#define SMRDR0_0L  SPIBSC0.SMRDR0.UINT16[L]
-#define SMRDR0_0H  SPIBSC0.SMRDR0.UINT16[H]
-#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
-#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
-#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
-#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
-#define SMRDR1_0   SPIBSC0.SMRDR1.UINT32
-#define SMRDR1_0L  SPIBSC0.SMRDR1.UINT16[L]
-#define SMRDR1_0H  SPIBSC0.SMRDR1.UINT16[H]
-#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
-#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
-#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
-#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
-#define SMWDR0_0   SPIBSC0.SMWDR0.UINT32
-#define SMWDR0_0L  SPIBSC0.SMWDR0.UINT16[L]
-#define SMWDR0_0H  SPIBSC0.SMWDR0.UINT16[H]
-#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
-#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
-#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
-#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
-#define SMWDR1_0   SPIBSC0.SMWDR1.UINT32
-#define SMWDR1_0L  SPIBSC0.SMWDR1.UINT16[L]
-#define SMWDR1_0H  SPIBSC0.SMWDR1.UINT16[H]
-#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
-#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
-#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
-#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
-#define CMNSR_0 SPIBSC0.CMNSR
-#define DRDMCR_0 SPIBSC0.DRDMCR
-#define DRDRENR_0 SPIBSC0.DRDRENR
-#define SMDMCR_0 SPIBSC0.SMDMCR
-#define SMDRENR_0 SPIBSC0.SMDRENR
-#define CMNCR_1 SPIBSC1.CMNCR
-#define SSLDR_1 SPIBSC1.SSLDR
-#define SPBCR_1 SPIBSC1.SPBCR
-#define DRCR_1 SPIBSC1.DRCR
-#define DRCMR_1 SPIBSC1.DRCMR
-#define DREAR_1 SPIBSC1.DREAR
-#define DROPR_1 SPIBSC1.DROPR
-#define DRENR_1 SPIBSC1.DRENR
-#define SMCR_1 SPIBSC1.SMCR
-#define SMCMR_1 SPIBSC1.SMCMR
-#define SMADR_1 SPIBSC1.SMADR
-#define SMOPR_1 SPIBSC1.SMOPR
-#define SMENR_1 SPIBSC1.SMENR
-#define SMRDR0_1   SPIBSC1.SMRDR0.UINT32
-#define SMRDR0_1L  SPIBSC1.SMRDR0.UINT16[L]
-#define SMRDR0_1H  SPIBSC1.SMRDR0.UINT16[H]
-#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
-#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
-#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
-#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
-#define SMRDR1_1   SPIBSC1.SMRDR1.UINT32
-#define SMRDR1_1L  SPIBSC1.SMRDR1.UINT16[L]
-#define SMRDR1_1H  SPIBSC1.SMRDR1.UINT16[H]
-#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
-#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
-#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
-#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
-#define SMWDR0_1   SPIBSC1.SMWDR0.UINT32
-#define SMWDR0_1L  SPIBSC1.SMWDR0.UINT16[L]
-#define SMWDR0_1H  SPIBSC1.SMWDR0.UINT16[H]
-#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
-#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
-#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
-#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
-#define SMWDR1_1   SPIBSC1.SMWDR1.UINT32
-#define SMWDR1_1L  SPIBSC1.SMWDR1.UINT16[L]
-#define SMWDR1_1H  SPIBSC1.SMWDR1.UINT16[H]
-#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
-#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
-#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
-#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
-#define CMNSR_1 SPIBSC1.CMNSR
-#define DRDMCR_1 SPIBSC1.DRDMCR
-#define DRDRENR_1 SPIBSC1.DRDRENR
-#define SMDMCR_1 SPIBSC1.SMDMCR
-#define SMDRENR_1 SPIBSC1.SMDRENR
+/* Channel array defines of SPIBSC (2)*/
+#ifdef  DECLARE_SPIBSC_CHANNELS
+volatile struct st_spibsc*  SPIBSC[ SPIBSC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SPIBSC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SPIBSC_CHANNELS */
+/* End of channel array defines of SPIBSC (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,107 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : ssif_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SSIF_IODEFINE_H
 #define SSIF_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_ssif
-{                                                          /* SSIF             */
+#define SSIF0   (*(struct st_ssif    *)0xE820B000uL) /* SSIF0 */
+#define SSIF1   (*(struct st_ssif    *)0xE820B800uL) /* SSIF1 */
+#define SSIF2   (*(struct st_ssif    *)0xE820C000uL) /* SSIF2 */
+#define SSIF3   (*(struct st_ssif    *)0xE820C800uL) /* SSIF3 */
+#define SSIF4   (*(struct st_ssif    *)0xE820D000uL) /* SSIF4 */
+#define SSIF5   (*(struct st_ssif    *)0xE820D800uL) /* SSIF5 */
+
+
+/* Start of channel array defines of SSIF */
+
+/* Channel array defines of SSIF */
+/*(Sample) value = SSIF[ channel ]->SSICR; */
+#define SSIF_COUNT  (6)
+#define SSIF_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SSIF */
+
+
+#define SSICR_0 (SSIF0.SSICR)
+#define SSISR_0 (SSIF0.SSISR)
+#define SSIFCR_0 (SSIF0.SSIFCR)
+#define SSIFSR_0 (SSIF0.SSIFSR)
+#define SSIFTDR_0 (SSIF0.SSIFTDR)
+#define SSIFRDR_0 (SSIF0.SSIFRDR)
+#define SSITDMR_0 (SSIF0.SSITDMR)
+#define SSIFCCR_0 (SSIF0.SSIFCCR)
+#define SSIFCMR_0 (SSIF0.SSIFCMR)
+#define SSIFCSR_0 (SSIF0.SSIFCSR)
+#define SSICR_1 (SSIF1.SSICR)
+#define SSISR_1 (SSIF1.SSISR)
+#define SSIFCR_1 (SSIF1.SSIFCR)
+#define SSIFSR_1 (SSIF1.SSIFSR)
+#define SSIFTDR_1 (SSIF1.SSIFTDR)
+#define SSIFRDR_1 (SSIF1.SSIFRDR)
+#define SSITDMR_1 (SSIF1.SSITDMR)
+#define SSIFCCR_1 (SSIF1.SSIFCCR)
+#define SSIFCMR_1 (SSIF1.SSIFCMR)
+#define SSIFCSR_1 (SSIF1.SSIFCSR)
+#define SSICR_2 (SSIF2.SSICR)
+#define SSISR_2 (SSIF2.SSISR)
+#define SSIFCR_2 (SSIF2.SSIFCR)
+#define SSIFSR_2 (SSIF2.SSIFSR)
+#define SSIFTDR_2 (SSIF2.SSIFTDR)
+#define SSIFRDR_2 (SSIF2.SSIFRDR)
+#define SSITDMR_2 (SSIF2.SSITDMR)
+#define SSIFCCR_2 (SSIF2.SSIFCCR)
+#define SSIFCMR_2 (SSIF2.SSIFCMR)
+#define SSIFCSR_2 (SSIF2.SSIFCSR)
+#define SSICR_3 (SSIF3.SSICR)
+#define SSISR_3 (SSIF3.SSISR)
+#define SSIFCR_3 (SSIF3.SSIFCR)
+#define SSIFSR_3 (SSIF3.SSIFSR)
+#define SSIFTDR_3 (SSIF3.SSIFTDR)
+#define SSIFRDR_3 (SSIF3.SSIFRDR)
+#define SSITDMR_3 (SSIF3.SSITDMR)
+#define SSIFCCR_3 (SSIF3.SSIFCCR)
+#define SSIFCMR_3 (SSIF3.SSIFCMR)
+#define SSIFCSR_3 (SSIF3.SSIFCSR)
+#define SSICR_4 (SSIF4.SSICR)
+#define SSISR_4 (SSIF4.SSISR)
+#define SSIFCR_4 (SSIF4.SSIFCR)
+#define SSIFSR_4 (SSIF4.SSIFSR)
+#define SSIFTDR_4 (SSIF4.SSIFTDR)
+#define SSIFRDR_4 (SSIF4.SSIFRDR)
+#define SSITDMR_4 (SSIF4.SSITDMR)
+#define SSIFCCR_4 (SSIF4.SSIFCCR)
+#define SSIFCMR_4 (SSIF4.SSIFCMR)
+#define SSIFCSR_4 (SSIF4.SSIFCSR)
+#define SSICR_5 (SSIF5.SSICR)
+#define SSISR_5 (SSIF5.SSISR)
+#define SSIFCR_5 (SSIF5.SSIFCR)
+#define SSIFSR_5 (SSIF5.SSIFSR)
+#define SSIFTDR_5 (SSIF5.SSIFTDR)
+#define SSIFRDR_5 (SSIF5.SSIFRDR)
+#define SSITDMR_5 (SSIF5.SSITDMR)
+#define SSIFCCR_5 (SSIF5.SSIFCCR)
+#define SSIFCMR_5 (SSIF5.SSIFCMR)
+#define SSIFCSR_5 (SSIF5.SSIFCSR)
+
+
+typedef struct st_ssif
+{
+                                                           /* SSIF             */
     volatile uint32_t  SSICR;                                  /*  SSICR           */
     volatile uint32_t  SSISR;                                  /*  SSISR           */
     volatile uint8_t   dummy1[8];                              /*                  */
@@ -43,89 +130,21 @@
     volatile uint32_t  SSIFCCR;                                /*  SSIFCCR         */
     volatile uint32_t  SSIFCMR;                                /*  SSIFCMR         */
     volatile uint32_t  SSIFCSR;                                /*  SSIFCSR         */
-};
-
-
-#define SSIF0   (*(struct st_ssif    *)0xE820B000uL) /* SSIF0 */
-#define SSIF1   (*(struct st_ssif    *)0xE820B800uL) /* SSIF1 */
-#define SSIF2   (*(struct st_ssif    *)0xE820C000uL) /* SSIF2 */
-#define SSIF3   (*(struct st_ssif    *)0xE820C800uL) /* SSIF3 */
-#define SSIF4   (*(struct st_ssif    *)0xE820D000uL) /* SSIF4 */
-#define SSIF5   (*(struct st_ssif    *)0xE820D800uL) /* SSIF5 */
-
-
-/* Start of channnel array defines of SSIF */
-
-/* Channnel array defines of SSIF */
-/*(Sample) value = SSIF[ channel ]->SSICR; */
-#define SSIF_COUNT  6
-#define SSIF_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of SSIF */
+} r_io_ssif_t;
 
 
-#define SSICR_0 SSIF0.SSICR
-#define SSISR_0 SSIF0.SSISR
-#define SSIFCR_0 SSIF0.SSIFCR
-#define SSIFSR_0 SSIF0.SSIFSR
-#define SSIFTDR_0 SSIF0.SSIFTDR
-#define SSIFRDR_0 SSIF0.SSIFRDR
-#define SSITDMR_0 SSIF0.SSITDMR
-#define SSIFCCR_0 SSIF0.SSIFCCR
-#define SSIFCMR_0 SSIF0.SSIFCMR
-#define SSIFCSR_0 SSIF0.SSIFCSR
-#define SSICR_1 SSIF1.SSICR
-#define SSISR_1 SSIF1.SSISR
-#define SSIFCR_1 SSIF1.SSIFCR
-#define SSIFSR_1 SSIF1.SSIFSR
-#define SSIFTDR_1 SSIF1.SSIFTDR
-#define SSIFRDR_1 SSIF1.SSIFRDR
-#define SSITDMR_1 SSIF1.SSITDMR
-#define SSIFCCR_1 SSIF1.SSIFCCR
-#define SSIFCMR_1 SSIF1.SSIFCMR
-#define SSIFCSR_1 SSIF1.SSIFCSR
-#define SSICR_2 SSIF2.SSICR
-#define SSISR_2 SSIF2.SSISR
-#define SSIFCR_2 SSIF2.SSIFCR
-#define SSIFSR_2 SSIF2.SSIFSR
-#define SSIFTDR_2 SSIF2.SSIFTDR
-#define SSIFRDR_2 SSIF2.SSIFRDR
-#define SSITDMR_2 SSIF2.SSITDMR
-#define SSIFCCR_2 SSIF2.SSIFCCR
-#define SSIFCMR_2 SSIF2.SSIFCMR
-#define SSIFCSR_2 SSIF2.SSIFCSR
-#define SSICR_3 SSIF3.SSICR
-#define SSISR_3 SSIF3.SSISR
-#define SSIFCR_3 SSIF3.SSIFCR
-#define SSIFSR_3 SSIF3.SSIFSR
-#define SSIFTDR_3 SSIF3.SSIFTDR
-#define SSIFRDR_3 SSIF3.SSIFRDR
-#define SSITDMR_3 SSIF3.SSITDMR
-#define SSIFCCR_3 SSIF3.SSIFCCR
-#define SSIFCMR_3 SSIF3.SSIFCMR
-#define SSIFCSR_3 SSIF3.SSIFCSR
-#define SSICR_4 SSIF4.SSICR
-#define SSISR_4 SSIF4.SSISR
-#define SSIFCR_4 SSIF4.SSIFCR
-#define SSIFSR_4 SSIF4.SSIFSR
-#define SSIFTDR_4 SSIF4.SSIFTDR
-#define SSIFRDR_4 SSIF4.SSIFRDR
-#define SSITDMR_4 SSIF4.SSITDMR
-#define SSIFCCR_4 SSIF4.SSIFCCR
-#define SSIFCMR_4 SSIF4.SSIFCMR
-#define SSIFCSR_4 SSIF4.SSIFCSR
-#define SSICR_5 SSIF5.SSICR
-#define SSISR_5 SSIF5.SSISR
-#define SSIFCR_5 SSIF5.SSIFCR
-#define SSIFSR_5 SSIF5.SSIFSR
-#define SSIFTDR_5 SSIF5.SSIFTDR
-#define SSIFRDR_5 SSIF5.SSIFRDR
-#define SSITDMR_5 SSIF5.SSITDMR
-#define SSIFCCR_5 SSIF5.SSIFCCR
-#define SSIFCMR_5 SSIF5.SSIFCMR
-#define SSIFCSR_5 SSIF5.SSIFCSR
+/* Channel array defines of SSIF (2)*/
+#ifdef  DECLARE_SSIF_CHANNELS
+volatile struct st_ssif*  SSIF[ SSIF_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SSIF_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SSIF_CHANNELS */
+/* End of channel array defines of SSIF (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,20 +18,365 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : usb20_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef USB20_IODEFINE_H
 #define USB20_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_usb20
-{                                                          /* USB20            */
+#define USB200  (*(struct st_usb20   *)0xE8010000uL) /* USB200 */
+#define USB201  (*(struct st_usb20   *)0xE8207000uL) /* USB201 */
+
+
+/* Start of channel array defines of USB20 */
+
+/* Channel array defines of USB20 */
+/*(Sample) value = USB20[ channel ]->SYSCFG0; */
+#define USB20_COUNT  (2)
+#define USB20_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &USB200, &USB201 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channel array defines of USB20_FROM_D0FIFOB0 */
+/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
+#define USB20_FROM_D0FIFOB0_COUNT  (2)
+#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
+    &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
+#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
+#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
+#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
+
+
+
+
+/* Channel array defines of USB20_FROM_PIPE1ATRE */
+/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
+#define USB20_FROM_PIPE1ATRE_COUNT  (5)
+#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
+    &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
+#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
+#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
+#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
+#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
+#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
+#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
+#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
+#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
+#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
+
+
+
+
+/* Channel array defines of USB20_FROM_D0FIFOSEL */
+/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
+#define USB20_FROM_D0FIFOSEL_COUNT  (2)
+#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
+    &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
+#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
+#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
+#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
+
+
+/* End of channel array defines of USB20 */
+
+
+#define SYSCFG0_0 (USB200.SYSCFG0)
+#define BUSWAIT_0 (USB200.BUSWAIT)
+#define SYSSTS0_0 (USB200.SYSSTS0)
+#define DVSTCTR0_0 (USB200.DVSTCTR0)
+#define TESTMODE_0 (USB200.TESTMODE)
+#define D0FBCFG_0 (USB200.D0FBCFG)
+#define D1FBCFG_0 (USB200.D1FBCFG)
+#define CFIFO_0   (USB200.CFIFO.UINT32)
+#define CFIFO_0L  (USB200.CFIFO.UINT16[R_IO_L])
+#define CFIFO_0H  (USB200.CFIFO.UINT16[R_IO_H])
+#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL])
+#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH])
+#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL])
+#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH])
+#define D0FIFO_0   (USB200.D0FIFO.UINT32)
+#define D0FIFO_0L  (USB200.D0FIFO.UINT16[R_IO_L])
+#define D0FIFO_0H  (USB200.D0FIFO.UINT16[R_IO_H])
+#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL])
+#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH])
+#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL])
+#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH])
+#define D1FIFO_0   (USB200.D1FIFO.UINT32)
+#define D1FIFO_0L  (USB200.D1FIFO.UINT16[R_IO_L])
+#define D1FIFO_0H  (USB200.D1FIFO.UINT16[R_IO_H])
+#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL])
+#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH])
+#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL])
+#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH])
+#define CFIFOSEL_0 (USB200.CFIFOSEL)
+#define CFIFOCTR_0 (USB200.CFIFOCTR)
+#define D0FIFOSEL_0 (USB200.D0FIFOSEL)
+#define D0FIFOCTR_0 (USB200.D0FIFOCTR)
+#define D1FIFOSEL_0 (USB200.D1FIFOSEL)
+#define D1FIFOCTR_0 (USB200.D1FIFOCTR)
+#define INTENB0_0 (USB200.INTENB0)
+#define INTENB1_0 (USB200.INTENB1)
+#define BRDYENB_0 (USB200.BRDYENB)
+#define NRDYENB_0 (USB200.NRDYENB)
+#define BEMPENB_0 (USB200.BEMPENB)
+#define SOFCFG_0 (USB200.SOFCFG)
+#define INTSTS0_0 (USB200.INTSTS0)
+#define INTSTS1_0 (USB200.INTSTS1)
+#define BRDYSTS_0 (USB200.BRDYSTS)
+#define NRDYSTS_0 (USB200.NRDYSTS)
+#define BEMPSTS_0 (USB200.BEMPSTS)
+#define FRMNUM_0 (USB200.FRMNUM)
+#define UFRMNUM_0 (USB200.UFRMNUM)
+#define USBADDR_0 (USB200.USBADDR)
+#define USBREQ_0 (USB200.USBREQ)
+#define USBVAL_0 (USB200.USBVAL)
+#define USBINDX_0 (USB200.USBINDX)
+#define USBLENG_0 (USB200.USBLENG)
+#define DCPCFG_0 (USB200.DCPCFG)
+#define DCPMAXP_0 (USB200.DCPMAXP)
+#define DCPCTR_0 (USB200.DCPCTR)
+#define PIPESEL_0 (USB200.PIPESEL)
+#define PIPECFG_0 (USB200.PIPECFG)
+#define PIPEBUF_0 (USB200.PIPEBUF)
+#define PIPEMAXP_0 (USB200.PIPEMAXP)
+#define PIPEPERI_0 (USB200.PIPEPERI)
+#define PIPE1CTR_0 (USB200.PIPE1CTR)
+#define PIPE2CTR_0 (USB200.PIPE2CTR)
+#define PIPE3CTR_0 (USB200.PIPE3CTR)
+#define PIPE4CTR_0 (USB200.PIPE4CTR)
+#define PIPE5CTR_0 (USB200.PIPE5CTR)
+#define PIPE6CTR_0 (USB200.PIPE6CTR)
+#define PIPE7CTR_0 (USB200.PIPE7CTR)
+#define PIPE8CTR_0 (USB200.PIPE8CTR)
+#define PIPE9CTR_0 (USB200.PIPE9CTR)
+#define PIPEACTR_0 (USB200.PIPEACTR)
+#define PIPEBCTR_0 (USB200.PIPEBCTR)
+#define PIPECCTR_0 (USB200.PIPECCTR)
+#define PIPEDCTR_0 (USB200.PIPEDCTR)
+#define PIPEECTR_0 (USB200.PIPEECTR)
+#define PIPEFCTR_0 (USB200.PIPEFCTR)
+#define PIPE1TRE_0 (USB200.PIPE1TRE)
+#define PIPE1TRN_0 (USB200.PIPE1TRN)
+#define PIPE2TRE_0 (USB200.PIPE2TRE)
+#define PIPE2TRN_0 (USB200.PIPE2TRN)
+#define PIPE3TRE_0 (USB200.PIPE3TRE)
+#define PIPE3TRN_0 (USB200.PIPE3TRN)
+#define PIPE4TRE_0 (USB200.PIPE4TRE)
+#define PIPE4TRN_0 (USB200.PIPE4TRN)
+#define PIPE5TRE_0 (USB200.PIPE5TRE)
+#define PIPE5TRN_0 (USB200.PIPE5TRN)
+#define PIPEBTRE_0 (USB200.PIPEBTRE)
+#define PIPEBTRN_0 (USB200.PIPEBTRN)
+#define PIPECTRE_0 (USB200.PIPECTRE)
+#define PIPECTRN_0 (USB200.PIPECTRN)
+#define PIPEDTRE_0 (USB200.PIPEDTRE)
+#define PIPEDTRN_0 (USB200.PIPEDTRN)
+#define PIPEETRE_0 (USB200.PIPEETRE)
+#define PIPEETRN_0 (USB200.PIPEETRN)
+#define PIPEFTRE_0 (USB200.PIPEFTRE)
+#define PIPEFTRN_0 (USB200.PIPEFTRN)
+#define PIPE9TRE_0 (USB200.PIPE9TRE)
+#define PIPE9TRN_0 (USB200.PIPE9TRN)
+#define PIPEATRE_0 (USB200.PIPEATRE)
+#define PIPEATRN_0 (USB200.PIPEATRN)
+#define DEVADD0_0 (USB200.DEVADD0)
+#define DEVADD1_0 (USB200.DEVADD1)
+#define DEVADD2_0 (USB200.DEVADD2)
+#define DEVADD3_0 (USB200.DEVADD3)
+#define DEVADD4_0 (USB200.DEVADD4)
+#define DEVADD5_0 (USB200.DEVADD5)
+#define DEVADD6_0 (USB200.DEVADD6)
+#define DEVADD7_0 (USB200.DEVADD7)
+#define DEVADD8_0 (USB200.DEVADD8)
+#define DEVADD9_0 (USB200.DEVADD9)
+#define DEVADDA_0 (USB200.DEVADDA)
+#define SUSPMODE_0 (USB200.SUSPMODE)
+#define D0FIFOB0_0 (USB200.D0FIFOB0)
+#define D0FIFOB1_0 (USB200.D0FIFOB1)
+#define D0FIFOB2_0 (USB200.D0FIFOB2)
+#define D0FIFOB3_0 (USB200.D0FIFOB3)
+#define D0FIFOB4_0 (USB200.D0FIFOB4)
+#define D0FIFOB5_0 (USB200.D0FIFOB5)
+#define D0FIFOB6_0 (USB200.D0FIFOB6)
+#define D0FIFOB7_0 (USB200.D0FIFOB7)
+#define D1FIFOB0_0 (USB200.D1FIFOB0)
+#define D1FIFOB1_0 (USB200.D1FIFOB1)
+#define D1FIFOB2_0 (USB200.D1FIFOB2)
+#define D1FIFOB3_0 (USB200.D1FIFOB3)
+#define D1FIFOB4_0 (USB200.D1FIFOB4)
+#define D1FIFOB5_0 (USB200.D1FIFOB5)
+#define D1FIFOB6_0 (USB200.D1FIFOB6)
+#define D1FIFOB7_0 (USB200.D1FIFOB7)
+#define SYSCFG0_1 (USB201.SYSCFG0)
+#define BUSWAIT_1 (USB201.BUSWAIT)
+#define SYSSTS0_1 (USB201.SYSSTS0)
+#define DVSTCTR0_1 (USB201.DVSTCTR0)
+#define TESTMODE_1 (USB201.TESTMODE)
+#define D0FBCFG_1 (USB201.D0FBCFG)
+#define D1FBCFG_1 (USB201.D1FBCFG)
+#define CFIFO_1   (USB201.CFIFO.UINT32)
+#define CFIFO_1L  (USB201.CFIFO.UINT16[R_IO_L])
+#define CFIFO_1H  (USB201.CFIFO.UINT16[R_IO_H])
+#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL])
+#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH])
+#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL])
+#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH])
+#define D0FIFO_1   (USB201.D0FIFO.UINT32)
+#define D0FIFO_1L  (USB201.D0FIFO.UINT16[R_IO_L])
+#define D0FIFO_1H  (USB201.D0FIFO.UINT16[R_IO_H])
+#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL])
+#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH])
+#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL])
+#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH])
+#define D1FIFO_1   (USB201.D1FIFO.UINT32)
+#define D1FIFO_1L  (USB201.D1FIFO.UINT16[R_IO_L])
+#define D1FIFO_1H  (USB201.D1FIFO.UINT16[R_IO_H])
+#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL])
+#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH])
+#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL])
+#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH])
+#define CFIFOSEL_1 (USB201.CFIFOSEL)
+#define CFIFOCTR_1 (USB201.CFIFOCTR)
+#define D0FIFOSEL_1 (USB201.D0FIFOSEL)
+#define D0FIFOCTR_1 (USB201.D0FIFOCTR)
+#define D1FIFOSEL_1 (USB201.D1FIFOSEL)
+#define D1FIFOCTR_1 (USB201.D1FIFOCTR)
+#define INTENB0_1 (USB201.INTENB0)
+#define INTENB1_1 (USB201.INTENB1)
+#define BRDYENB_1 (USB201.BRDYENB)
+#define NRDYENB_1 (USB201.NRDYENB)
+#define BEMPENB_1 (USB201.BEMPENB)
+#define SOFCFG_1 (USB201.SOFCFG)
+#define INTSTS0_1 (USB201.INTSTS0)
+#define INTSTS1_1 (USB201.INTSTS1)
+#define BRDYSTS_1 (USB201.BRDYSTS)
+#define NRDYSTS_1 (USB201.NRDYSTS)
+#define BEMPSTS_1 (USB201.BEMPSTS)
+#define FRMNUM_1 (USB201.FRMNUM)
+#define UFRMNUM_1 (USB201.UFRMNUM)
+#define USBADDR_1 (USB201.USBADDR)
+#define USBREQ_1 (USB201.USBREQ)
+#define USBVAL_1 (USB201.USBVAL)
+#define USBINDX_1 (USB201.USBINDX)
+#define USBLENG_1 (USB201.USBLENG)
+#define DCPCFG_1 (USB201.DCPCFG)
+#define DCPMAXP_1 (USB201.DCPMAXP)
+#define DCPCTR_1 (USB201.DCPCTR)
+#define PIPESEL_1 (USB201.PIPESEL)
+#define PIPECFG_1 (USB201.PIPECFG)
+#define PIPEBUF_1 (USB201.PIPEBUF)
+#define PIPEMAXP_1 (USB201.PIPEMAXP)
+#define PIPEPERI_1 (USB201.PIPEPERI)
+#define PIPE1CTR_1 (USB201.PIPE1CTR)
+#define PIPE2CTR_1 (USB201.PIPE2CTR)
+#define PIPE3CTR_1 (USB201.PIPE3CTR)
+#define PIPE4CTR_1 (USB201.PIPE4CTR)
+#define PIPE5CTR_1 (USB201.PIPE5CTR)
+#define PIPE6CTR_1 (USB201.PIPE6CTR)
+#define PIPE7CTR_1 (USB201.PIPE7CTR)
+#define PIPE8CTR_1 (USB201.PIPE8CTR)
+#define PIPE9CTR_1 (USB201.PIPE9CTR)
+#define PIPEACTR_1 (USB201.PIPEACTR)
+#define PIPEBCTR_1 (USB201.PIPEBCTR)
+#define PIPECCTR_1 (USB201.PIPECCTR)
+#define PIPEDCTR_1 (USB201.PIPEDCTR)
+#define PIPEECTR_1 (USB201.PIPEECTR)
+#define PIPEFCTR_1 (USB201.PIPEFCTR)
+#define PIPE1TRE_1 (USB201.PIPE1TRE)
+#define PIPE1TRN_1 (USB201.PIPE1TRN)
+#define PIPE2TRE_1 (USB201.PIPE2TRE)
+#define PIPE2TRN_1 (USB201.PIPE2TRN)
+#define PIPE3TRE_1 (USB201.PIPE3TRE)
+#define PIPE3TRN_1 (USB201.PIPE3TRN)
+#define PIPE4TRE_1 (USB201.PIPE4TRE)
+#define PIPE4TRN_1 (USB201.PIPE4TRN)
+#define PIPE5TRE_1 (USB201.PIPE5TRE)
+#define PIPE5TRN_1 (USB201.PIPE5TRN)
+#define PIPEBTRE_1 (USB201.PIPEBTRE)
+#define PIPEBTRN_1 (USB201.PIPEBTRN)
+#define PIPECTRE_1 (USB201.PIPECTRE)
+#define PIPECTRN_1 (USB201.PIPECTRN)
+#define PIPEDTRE_1 (USB201.PIPEDTRE)
+#define PIPEDTRN_1 (USB201.PIPEDTRN)
+#define PIPEETRE_1 (USB201.PIPEETRE)
+#define PIPEETRN_1 (USB201.PIPEETRN)
+#define PIPEFTRE_1 (USB201.PIPEFTRE)
+#define PIPEFTRN_1 (USB201.PIPEFTRN)
+#define PIPE9TRE_1 (USB201.PIPE9TRE)
+#define PIPE9TRN_1 (USB201.PIPE9TRN)
+#define PIPEATRE_1 (USB201.PIPEATRE)
+#define PIPEATRN_1 (USB201.PIPEATRN)
+#define DEVADD0_1 (USB201.DEVADD0)
+#define DEVADD1_1 (USB201.DEVADD1)
+#define DEVADD2_1 (USB201.DEVADD2)
+#define DEVADD3_1 (USB201.DEVADD3)
+#define DEVADD4_1 (USB201.DEVADD4)
+#define DEVADD5_1 (USB201.DEVADD5)
+#define DEVADD6_1 (USB201.DEVADD6)
+#define DEVADD7_1 (USB201.DEVADD7)
+#define DEVADD8_1 (USB201.DEVADD8)
+#define DEVADD9_1 (USB201.DEVADD9)
+#define DEVADDA_1 (USB201.DEVADDA)
+#define SUSPMODE_1 (USB201.SUSPMODE)
+#define D0FIFOB0_1 (USB201.D0FIFOB0)
+#define D0FIFOB1_1 (USB201.D0FIFOB1)
+#define D0FIFOB2_1 (USB201.D0FIFOB2)
+#define D0FIFOB3_1 (USB201.D0FIFOB3)
+#define D0FIFOB4_1 (USB201.D0FIFOB4)
+#define D0FIFOB5_1 (USB201.D0FIFOB5)
+#define D0FIFOB6_1 (USB201.D0FIFOB6)
+#define D0FIFOB7_1 (USB201.D0FIFOB7)
+#define D1FIFOB0_1 (USB201.D1FIFOB0)
+#define D1FIFOB1_1 (USB201.D1FIFOB1)
+#define D1FIFOB2_1 (USB201.D1FIFOB2)
+#define D1FIFOB3_1 (USB201.D1FIFOB3)
+#define D1FIFOB4_1 (USB201.D1FIFOB4)
+#define D1FIFOB5_1 (USB201.D1FIFOB5)
+#define D1FIFOB6_1 (USB201.D1FIFOB6)
+#define D1FIFOB7_1 (USB201.D1FIFOB7)
+
+#define USB20_D0FBCFG_COUNT (2)
+#define USB20_D0FIFO_COUNT (2)
+#define USB20_INTENB0_COUNT (2)
+#define USB20_INTSTS0_COUNT (2)
+#define USB20_PIPE1CTR_COUNT (0xF)
+#define USB20_DEVADD0_COUNT (0xB)
+#define USB20_D0FIFOB0_COUNT (0x8)
+
+
+typedef struct st_usb20
+{
+                                                           /* USB20            */
     volatile uint16_t SYSCFG0;                                /*  SYSCFG0         */
     volatile uint16_t BUSWAIT;                                /*  BUSWAIT         */
     volatile uint16_t SYSSTS0;                                /*  SYSSTS0         */
@@ -40,26 +385,33 @@
     volatile uint8_t   dummy2[2];                              /*                  */
     volatile uint16_t TESTMODE;                               /*  TESTMODE        */
     volatile uint8_t   dummy3[2];                              /*                  */
-#define USB20_D0FBCFG_COUNT 2
+
+/* #define USB20_D0FBCFG_COUNT (2) */
     volatile uint16_t D0FBCFG;                                /*  D0FBCFG         */
     volatile uint16_t D1FBCFG;                                /*  D1FBCFG         */
     union iodefine_reg32_t  CFIFO;                         /*  CFIFO           */
-#define USB20_D0FIFO_COUNT 2
+
+/* #define USB20_D0FIFO_COUNT (2) */
     union iodefine_reg32_t  D0FIFO;                        /*  D0FIFO          */
     union iodefine_reg32_t  D1FIFO;                        /*  D1FIFO          */
     
     volatile uint16_t CFIFOSEL;                               /*  CFIFOSEL        */
     volatile uint16_t CFIFOCTR;                               /*  CFIFOCTR        */
     volatile uint8_t   dummy4[4];                              /*                  */
+
 /* start of struct st_usb20_from_d0fifosel */
     volatile uint16_t D0FIFOSEL;                              /*  D0FIFOSEL       */
     volatile uint16_t D0FIFOCTR;                              /*  D0FIFOCTR       */
+
 /* end of struct st_usb20_from_d0fifosel */
+
 /* start of struct st_usb20_from_d0fifosel */
     volatile uint16_t D1FIFOSEL;                              /*  D1FIFOSEL       */
     volatile uint16_t D1FIFOCTR;                              /*  D1FIFOCTR       */
+
 /* end of struct st_usb20_from_d0fifosel */
-#define USB20_INTENB0_COUNT 2
+
+/* #define USB20_INTENB0_COUNT (2) */
     volatile uint16_t INTENB0;                                /*  INTENB0         */
     volatile uint16_t INTENB1;                                /*  INTENB1         */
     volatile uint8_t   dummy5[2];                              /*                  */
@@ -68,7 +420,8 @@
     volatile uint16_t BEMPENB;                                /*  BEMPENB         */
     volatile uint16_t SOFCFG;                                 /*  SOFCFG          */
     volatile uint8_t   dummy6[2];                              /*                  */
-#define USB20_INTSTS0_COUNT 2
+
+/* #define USB20_INTSTS0_COUNT (2) */
     volatile uint16_t INTSTS0;                                /*  INTSTS0         */
     volatile uint16_t INTSTS1;                                /*  INTSTS1         */
     volatile uint8_t   dummy7[2];                              /*                  */
@@ -93,7 +446,8 @@
     volatile uint16_t PIPEBUF;                                /*  PIPEBUF         */
     volatile uint16_t PIPEMAXP;                               /*  PIPEMAXP        */
     volatile uint16_t PIPEPERI;                               /*  PIPEPERI        */
-#define USB20_PIPE1CTR_COUNT 0xF
+
+/* #define USB20_PIPE1CTR_COUNT (0xF) */
     volatile uint16_t PIPE1CTR;                               /*  PIPE1CTR        */
     volatile uint16_t PIPE2CTR;                               /*  PIPE2CTR        */
     volatile uint16_t PIPE3CTR;                               /*  PIPE3CTR        */
@@ -110,25 +464,35 @@
     volatile uint16_t PIPEECTR;                               /*  PIPEECTR        */
     volatile uint16_t PIPEFCTR;                               /*  PIPEFCTR        */
     volatile uint8_t   dummy11[2];                             /*                  */
+
 /* start of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPE1TRE;                               /*  PIPE1TRE        */
     volatile uint16_t PIPE1TRN;                               /*  PIPE1TRN        */
+
 /* end of struct st_usb20_from_pipe1tre */
+
 /* start of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPE2TRE;                               /*  PIPE2TRE        */
     volatile uint16_t PIPE2TRN;                               /*  PIPE2TRN        */
+
 /* end of struct st_usb20_from_pipe1tre */
+
 /* start of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPE3TRE;                               /*  PIPE3TRE        */
     volatile uint16_t PIPE3TRN;                               /*  PIPE3TRN        */
+
 /* end of struct st_usb20_from_pipe1tre */
+
 /* start of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPE4TRE;                               /*  PIPE4TRE        */
     volatile uint16_t PIPE4TRN;                               /*  PIPE4TRN        */
+
 /* end of struct st_usb20_from_pipe1tre */
+
 /* start of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPE5TRE;                               /*  PIPE5TRE        */
     volatile uint16_t PIPE5TRN;                               /*  PIPE5TRN        */
+
 /* end of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPEBTRE;                               /*  PIPEBTRE        */
     volatile uint16_t PIPEBTRN;                               /*  PIPEBTRN        */
@@ -145,7 +509,8 @@
     volatile uint16_t PIPEATRE;                               /*  PIPEATRE        */
     volatile uint16_t PIPEATRN;                               /*  PIPEATRN        */
     volatile uint8_t   dummy12[16];                            /*                  */
-#define USB20_DEVADD0_COUNT 0xB
+
+/* #define USB20_DEVADD0_COUNT (0xB) */
     volatile uint16_t DEVADD0;                                /*  DEVADD0         */
     volatile uint16_t DEVADD1;                                /*  DEVADD1         */
     volatile uint16_t DEVADD2;                                /*  DEVADD2         */
@@ -160,6 +525,7 @@
     volatile uint8_t   dummy13[28];                            /*                  */
     volatile uint16_t SUSPMODE;                               /*  SUSPMODE        */
     volatile uint8_t   dummy14[92];                            /*                  */
+
 /* start of struct st_usb20_from_dmfifob0 */
     volatile uint32_t  D0FIFOB0;                               /*  D0FIFOB0        */
     volatile uint32_t  D0FIFOB1;                               /*  D0FIFOB1        */
@@ -169,7 +535,9 @@
     volatile uint32_t  D0FIFOB5;                               /*  D0FIFOB5        */
     volatile uint32_t  D0FIFOB6;                               /*  D0FIFOB6        */
     volatile uint32_t  D0FIFOB7;                               /*  D0FIFOB7        */
+
 /* end of struct st_usb20_from_dmfifob0 */
+
 /* start of struct st_usb20_from_dmfifob0 */
     volatile uint32_t  D1FIFOB0;                               /*  D1FIFOB0        */
     volatile uint32_t  D1FIFOB1;                               /*  D1FIFOB1        */
@@ -179,27 +547,32 @@
     volatile uint32_t  D1FIFOB5;                               /*  D1FIFOB5        */
     volatile uint32_t  D1FIFOB6;                               /*  D1FIFOB6        */
     volatile uint32_t  D1FIFOB7;                               /*  D1FIFOB7        */
+
 /* end of struct st_usb20_from_dmfifob0 */
-};
+} r_io_usb20_t;
 
 
-struct st_usb20_from_d0fifosel
+typedef struct st_usb20_from_d0fifosel
 {
+ 
     volatile uint16_t D0FIFOSEL;                              /*  D0FIFOSEL       */
     volatile uint16_t D0FIFOCTR;                              /*  D0FIFOCTR       */
-};
+} r_io_usb20_from_d0fifosel_t;
 
 
-struct st_usb20_from_pipe1tre
+typedef struct st_usb20_from_pipe1tre
 {
+ 
     volatile uint16_t PIPE1TRE;                               /*  PIPE1TRE        */
     volatile uint16_t PIPE1TRN;                               /*  PIPE1TRN        */
-};
+} r_io_usb20_from_pipe1tre_t;
 
 
-struct st_usb20_from_dmfifob0
+typedef struct st_usb20_from_dmfifob0
 {
-#define USB20_D0FIFOB0_COUNT 0x8
+ 
+
+/* #define USB20_D0FIFOB0_COUNT (0x8) */
     volatile uint32_t  D0FIFOB0;                               /*  D0FIFOB0        */
     volatile uint32_t  D0FIFOB1;                               /*  D0FIFOB1        */
     volatile uint32_t  D0FIFOB2;                               /*  D0FIFOB2        */
@@ -208,339 +581,42 @@
     volatile uint32_t  D0FIFOB5;                               /*  D0FIFOB5        */
     volatile uint32_t  D0FIFOB6;                               /*  D0FIFOB6        */
     volatile uint32_t  D0FIFOB7;                               /*  D0FIFOB7        */
-};
-
-
-#define USB200  (*(struct st_usb20   *)0xE8010000uL) /* USB200 */
-#define USB201  (*(struct st_usb20   *)0xE8207000uL) /* USB201 */
-
-
-/* Start of channnel array defines of USB20 */
-
-/* Channnel array defines of USB20 */
-/*(Sample) value = USB20[ channel ]->SYSCFG0; */
-#define USB20_COUNT  2
-#define USB20_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &USB200, &USB201 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-
-
-/* Channnel array defines of USB20_FROM_D0FIFOB0 */
-/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
-#define USB20_FROM_D0FIFOB0_COUNT  2
-#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
-    &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
-#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
-#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
-#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
-
-
-
-
-/* Channnel array defines of USB20_FROM_PIPE1ATRE */
-/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
-#define USB20_FROM_PIPE1ATRE_COUNT  5
-#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
-    &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
-#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
-#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
-#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
-#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
-#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
-#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
-#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
-#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
-#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
-
-
-
-
-/* Channnel array defines of USB20_FROM_D0FIFOSEL */
-/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
-#define USB20_FROM_D0FIFOSEL_COUNT  2
-#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
-    &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
-#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
-#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
-#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
-
-
-/* End of channnel array defines of USB20 */
+} r_io_usb20_from_dmfifob0_t;
 
 
-#define SYSCFG0_0 USB200.SYSCFG0
-#define BUSWAIT_0 USB200.BUSWAIT
-#define SYSSTS0_0 USB200.SYSSTS0
-#define DVSTCTR0_0 USB200.DVSTCTR0
-#define TESTMODE_0 USB200.TESTMODE
-#define D0FBCFG_0 USB200.D0FBCFG
-#define D1FBCFG_0 USB200.D1FBCFG
-#define CFIFO_0   USB200.CFIFO.UINT32
-#define CFIFO_0L  USB200.CFIFO.UINT16[L]
-#define CFIFO_0H  USB200.CFIFO.UINT16[H]
-#define CFIFO_0LL USB200.CFIFO.UINT8[LL]
-#define CFIFO_0LH USB200.CFIFO.UINT8[LH]
-#define CFIFO_0HL USB200.CFIFO.UINT8[HL]
-#define CFIFO_0HH USB200.CFIFO.UINT8[HH]
-#define D0FIFO_0   USB200.D0FIFO.UINT32
-#define D0FIFO_0L  USB200.D0FIFO.UINT16[L]
-#define D0FIFO_0H  USB200.D0FIFO.UINT16[H]
-#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL]
-#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH]
-#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL]
-#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH]
-#define D1FIFO_0   USB200.D1FIFO.UINT32
-#define D1FIFO_0L  USB200.D1FIFO.UINT16[L]
-#define D1FIFO_0H  USB200.D1FIFO.UINT16[H]
-#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL]
-#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH]
-#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL]
-#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH]
-#define CFIFOSEL_0 USB200.CFIFOSEL
-#define CFIFOCTR_0 USB200.CFIFOCTR
-#define D0FIFOSEL_0 USB200.D0FIFOSEL
-#define D0FIFOCTR_0 USB200.D0FIFOCTR
-#define D1FIFOSEL_0 USB200.D1FIFOSEL
-#define D1FIFOCTR_0 USB200.D1FIFOCTR
-#define INTENB0_0 USB200.INTENB0
-#define INTENB1_0 USB200.INTENB1
-#define BRDYENB_0 USB200.BRDYENB
-#define NRDYENB_0 USB200.NRDYENB
-#define BEMPENB_0 USB200.BEMPENB
-#define SOFCFG_0 USB200.SOFCFG
-#define INTSTS0_0 USB200.INTSTS0
-#define INTSTS1_0 USB200.INTSTS1
-#define BRDYSTS_0 USB200.BRDYSTS
-#define NRDYSTS_0 USB200.NRDYSTS
-#define BEMPSTS_0 USB200.BEMPSTS
-#define FRMNUM_0 USB200.FRMNUM
-#define UFRMNUM_0 USB200.UFRMNUM
-#define USBADDR_0 USB200.USBADDR
-#define USBREQ_0 USB200.USBREQ
-#define USBVAL_0 USB200.USBVAL
-#define USBINDX_0 USB200.USBINDX
-#define USBLENG_0 USB200.USBLENG
-#define DCPCFG_0 USB200.DCPCFG
-#define DCPMAXP_0 USB200.DCPMAXP
-#define DCPCTR_0 USB200.DCPCTR
-#define PIPESEL_0 USB200.PIPESEL
-#define PIPECFG_0 USB200.PIPECFG
-#define PIPEBUF_0 USB200.PIPEBUF
-#define PIPEMAXP_0 USB200.PIPEMAXP
-#define PIPEPERI_0 USB200.PIPEPERI
-#define PIPE1CTR_0 USB200.PIPE1CTR
-#define PIPE2CTR_0 USB200.PIPE2CTR
-#define PIPE3CTR_0 USB200.PIPE3CTR
-#define PIPE4CTR_0 USB200.PIPE4CTR
-#define PIPE5CTR_0 USB200.PIPE5CTR
-#define PIPE6CTR_0 USB200.PIPE6CTR
-#define PIPE7CTR_0 USB200.PIPE7CTR
-#define PIPE8CTR_0 USB200.PIPE8CTR
-#define PIPE9CTR_0 USB200.PIPE9CTR
-#define PIPEACTR_0 USB200.PIPEACTR
-#define PIPEBCTR_0 USB200.PIPEBCTR
-#define PIPECCTR_0 USB200.PIPECCTR
-#define PIPEDCTR_0 USB200.PIPEDCTR
-#define PIPEECTR_0 USB200.PIPEECTR
-#define PIPEFCTR_0 USB200.PIPEFCTR
-#define PIPE1TRE_0 USB200.PIPE1TRE
-#define PIPE1TRN_0 USB200.PIPE1TRN
-#define PIPE2TRE_0 USB200.PIPE2TRE
-#define PIPE2TRN_0 USB200.PIPE2TRN
-#define PIPE3TRE_0 USB200.PIPE3TRE
-#define PIPE3TRN_0 USB200.PIPE3TRN
-#define PIPE4TRE_0 USB200.PIPE4TRE
-#define PIPE4TRN_0 USB200.PIPE4TRN
-#define PIPE5TRE_0 USB200.PIPE5TRE
-#define PIPE5TRN_0 USB200.PIPE5TRN
-#define PIPEBTRE_0 USB200.PIPEBTRE
-#define PIPEBTRN_0 USB200.PIPEBTRN
-#define PIPECTRE_0 USB200.PIPECTRE
-#define PIPECTRN_0 USB200.PIPECTRN
-#define PIPEDTRE_0 USB200.PIPEDTRE
-#define PIPEDTRN_0 USB200.PIPEDTRN
-#define PIPEETRE_0 USB200.PIPEETRE
-#define PIPEETRN_0 USB200.PIPEETRN
-#define PIPEFTRE_0 USB200.PIPEFTRE
-#define PIPEFTRN_0 USB200.PIPEFTRN
-#define PIPE9TRE_0 USB200.PIPE9TRE
-#define PIPE9TRN_0 USB200.PIPE9TRN
-#define PIPEATRE_0 USB200.PIPEATRE
-#define PIPEATRN_0 USB200.PIPEATRN
-#define DEVADD0_0 USB200.DEVADD0
-#define DEVADD1_0 USB200.DEVADD1
-#define DEVADD2_0 USB200.DEVADD2
-#define DEVADD3_0 USB200.DEVADD3
-#define DEVADD4_0 USB200.DEVADD4
-#define DEVADD5_0 USB200.DEVADD5
-#define DEVADD6_0 USB200.DEVADD6
-#define DEVADD7_0 USB200.DEVADD7
-#define DEVADD8_0 USB200.DEVADD8
-#define DEVADD9_0 USB200.DEVADD9
-#define DEVADDA_0 USB200.DEVADDA
-#define SUSPMODE_0 USB200.SUSPMODE
-#define D0FIFOB0_0 USB200.D0FIFOB0
-#define D0FIFOB1_0 USB200.D0FIFOB1
-#define D0FIFOB2_0 USB200.D0FIFOB2
-#define D0FIFOB3_0 USB200.D0FIFOB3
-#define D0FIFOB4_0 USB200.D0FIFOB4
-#define D0FIFOB5_0 USB200.D0FIFOB5
-#define D0FIFOB6_0 USB200.D0FIFOB6
-#define D0FIFOB7_0 USB200.D0FIFOB7
-#define D1FIFOB0_0 USB200.D1FIFOB0
-#define D1FIFOB1_0 USB200.D1FIFOB1
-#define D1FIFOB2_0 USB200.D1FIFOB2
-#define D1FIFOB3_0 USB200.D1FIFOB3
-#define D1FIFOB4_0 USB200.D1FIFOB4
-#define D1FIFOB5_0 USB200.D1FIFOB5
-#define D1FIFOB6_0 USB200.D1FIFOB6
-#define D1FIFOB7_0 USB200.D1FIFOB7
-#define SYSCFG0_1 USB201.SYSCFG0
-#define BUSWAIT_1 USB201.BUSWAIT
-#define SYSSTS0_1 USB201.SYSSTS0
-#define DVSTCTR0_1 USB201.DVSTCTR0
-#define TESTMODE_1 USB201.TESTMODE
-#define D0FBCFG_1 USB201.D0FBCFG
-#define D1FBCFG_1 USB201.D1FBCFG
-#define CFIFO_1   USB201.CFIFO.UINT32
-#define CFIFO_1L  USB201.CFIFO.UINT16[L]
-#define CFIFO_1H  USB201.CFIFO.UINT16[H]
-#define CFIFO_1LL USB201.CFIFO.UINT8[LL]
-#define CFIFO_1LH USB201.CFIFO.UINT8[LH]
-#define CFIFO_1HL USB201.CFIFO.UINT8[HL]
-#define CFIFO_1HH USB201.CFIFO.UINT8[HH]
-#define D0FIFO_1   USB201.D0FIFO.UINT32
-#define D0FIFO_1L  USB201.D0FIFO.UINT16[L]
-#define D0FIFO_1H  USB201.D0FIFO.UINT16[H]
-#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL]
-#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH]
-#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL]
-#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH]
-#define D1FIFO_1   USB201.D1FIFO.UINT32
-#define D1FIFO_1L  USB201.D1FIFO.UINT16[L]
-#define D1FIFO_1H  USB201.D1FIFO.UINT16[H]
-#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL]
-#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH]
-#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL]
-#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH]
-#define CFIFOSEL_1 USB201.CFIFOSEL
-#define CFIFOCTR_1 USB201.CFIFOCTR
-#define D0FIFOSEL_1 USB201.D0FIFOSEL
-#define D0FIFOCTR_1 USB201.D0FIFOCTR
-#define D1FIFOSEL_1 USB201.D1FIFOSEL
-#define D1FIFOCTR_1 USB201.D1FIFOCTR
-#define INTENB0_1 USB201.INTENB0
-#define INTENB1_1 USB201.INTENB1
-#define BRDYENB_1 USB201.BRDYENB
-#define NRDYENB_1 USB201.NRDYENB
-#define BEMPENB_1 USB201.BEMPENB
-#define SOFCFG_1 USB201.SOFCFG
-#define INTSTS0_1 USB201.INTSTS0
-#define INTSTS1_1 USB201.INTSTS1
-#define BRDYSTS_1 USB201.BRDYSTS
-#define NRDYSTS_1 USB201.NRDYSTS
-#define BEMPSTS_1 USB201.BEMPSTS
-#define FRMNUM_1 USB201.FRMNUM
-#define UFRMNUM_1 USB201.UFRMNUM
-#define USBADDR_1 USB201.USBADDR
-#define USBREQ_1 USB201.USBREQ
-#define USBVAL_1 USB201.USBVAL
-#define USBINDX_1 USB201.USBINDX
-#define USBLENG_1 USB201.USBLENG
-#define DCPCFG_1 USB201.DCPCFG
-#define DCPMAXP_1 USB201.DCPMAXP
-#define DCPCTR_1 USB201.DCPCTR
-#define PIPESEL_1 USB201.PIPESEL
-#define PIPECFG_1 USB201.PIPECFG
-#define PIPEBUF_1 USB201.PIPEBUF
-#define PIPEMAXP_1 USB201.PIPEMAXP
-#define PIPEPERI_1 USB201.PIPEPERI
-#define PIPE1CTR_1 USB201.PIPE1CTR
-#define PIPE2CTR_1 USB201.PIPE2CTR
-#define PIPE3CTR_1 USB201.PIPE3CTR
-#define PIPE4CTR_1 USB201.PIPE4CTR
-#define PIPE5CTR_1 USB201.PIPE5CTR
-#define PIPE6CTR_1 USB201.PIPE6CTR
-#define PIPE7CTR_1 USB201.PIPE7CTR
-#define PIPE8CTR_1 USB201.PIPE8CTR
-#define PIPE9CTR_1 USB201.PIPE9CTR
-#define PIPEACTR_1 USB201.PIPEACTR
-#define PIPEBCTR_1 USB201.PIPEBCTR
-#define PIPECCTR_1 USB201.PIPECCTR
-#define PIPEDCTR_1 USB201.PIPEDCTR
-#define PIPEECTR_1 USB201.PIPEECTR
-#define PIPEFCTR_1 USB201.PIPEFCTR
-#define PIPE1TRE_1 USB201.PIPE1TRE
-#define PIPE1TRN_1 USB201.PIPE1TRN
-#define PIPE2TRE_1 USB201.PIPE2TRE
-#define PIPE2TRN_1 USB201.PIPE2TRN
-#define PIPE3TRE_1 USB201.PIPE3TRE
-#define PIPE3TRN_1 USB201.PIPE3TRN
-#define PIPE4TRE_1 USB201.PIPE4TRE
-#define PIPE4TRN_1 USB201.PIPE4TRN
-#define PIPE5TRE_1 USB201.PIPE5TRE
-#define PIPE5TRN_1 USB201.PIPE5TRN
-#define PIPEBTRE_1 USB201.PIPEBTRE
-#define PIPEBTRN_1 USB201.PIPEBTRN
-#define PIPECTRE_1 USB201.PIPECTRE
-#define PIPECTRN_1 USB201.PIPECTRN
-#define PIPEDTRE_1 USB201.PIPEDTRE
-#define PIPEDTRN_1 USB201.PIPEDTRN
-#define PIPEETRE_1 USB201.PIPEETRE
-#define PIPEETRN_1 USB201.PIPEETRN
-#define PIPEFTRE_1 USB201.PIPEFTRE
-#define PIPEFTRN_1 USB201.PIPEFTRN
-#define PIPE9TRE_1 USB201.PIPE9TRE
-#define PIPE9TRN_1 USB201.PIPE9TRN
-#define PIPEATRE_1 USB201.PIPEATRE
-#define PIPEATRN_1 USB201.PIPEATRN
-#define DEVADD0_1 USB201.DEVADD0
-#define DEVADD1_1 USB201.DEVADD1
-#define DEVADD2_1 USB201.DEVADD2
-#define DEVADD3_1 USB201.DEVADD3
-#define DEVADD4_1 USB201.DEVADD4
-#define DEVADD5_1 USB201.DEVADD5
-#define DEVADD6_1 USB201.DEVADD6
-#define DEVADD7_1 USB201.DEVADD7
-#define DEVADD8_1 USB201.DEVADD8
-#define DEVADD9_1 USB201.DEVADD9
-#define DEVADDA_1 USB201.DEVADDA
-#define SUSPMODE_1 USB201.SUSPMODE
-#define D0FIFOB0_1 USB201.D0FIFOB0
-#define D0FIFOB1_1 USB201.D0FIFOB1
-#define D0FIFOB2_1 USB201.D0FIFOB2
-#define D0FIFOB3_1 USB201.D0FIFOB3
-#define D0FIFOB4_1 USB201.D0FIFOB4
-#define D0FIFOB5_1 USB201.D0FIFOB5
-#define D0FIFOB6_1 USB201.D0FIFOB6
-#define D0FIFOB7_1 USB201.D0FIFOB7
-#define D1FIFOB0_1 USB201.D1FIFOB0
-#define D1FIFOB1_1 USB201.D1FIFOB1
-#define D1FIFOB2_1 USB201.D1FIFOB2
-#define D1FIFOB3_1 USB201.D1FIFOB3
-#define D1FIFOB4_1 USB201.D1FIFOB4
-#define D1FIFOB5_1 USB201.D1FIFOB5
-#define D1FIFOB6_1 USB201.D1FIFOB6
-#define D1FIFOB7_1 USB201.D1FIFOB7
+/* Channel array defines of USB20 (2)*/
+#ifdef  DECLARE_USB20_CHANNELS
+volatile struct st_usb20*  USB20[ USB20_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_CHANNELS */
+
+#ifdef  DECLARE_USB20_FROM_D0FIFOB0_CHANNELS
+volatile struct st_usb20_from_dmfifob0*  USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_FROM_D0FIFOB0_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */
+
+#ifdef  DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS
+volatile struct st_usb20_from_pipe1tre*  USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_FROM_PIPE1ATRE_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */
+
+#ifdef  DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS
+volatile struct st_usb20_from_d0fifosel*  USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_FROM_D0FIFOSEL_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */
+/* End of channel array defines of USB20 (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,21 +18,1004 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : vdc5_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef VDC5_IODEFINE_H
 #define VDC5_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_vdc5
-{                                                          /* VDC5             */
+#define VDC50   (*(struct st_vdc5    *)0xFCFF7400uL) /* VDC50 */
+#define VDC51   (*(struct st_vdc5    *)0xFCFF9400uL) /* VDC51 */
+
+
+/* Start of channel array defines of VDC5 */
+
+/* Channel array defines of VDC5 */
+/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
+#define VDC5_COUNT  (2)
+#define VDC5_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &VDC50, &VDC51 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */
+/*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC50_FROM_GR2_AB7_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
+    &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
+#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
+#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
+#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
+
+
+
+
+/* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
+    &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
+#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
+#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
+#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
+
+
+
+
+/* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */
+/*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
+#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT  (2)
+#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
+    &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
+#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
+#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
+#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
+
+
+
+
+/* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
+#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
+    &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
+#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
+#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
+#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
+
+
+
+
+/* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
+#define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
+    &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
+#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
+#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
+#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
+
+
+
+
+/* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */
+/*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC50_FROM_GR0_AB7_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
+    &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
+#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
+#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
+#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
+
+
+
+
+/* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
+    &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
+#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
+#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
+#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
+
+
+/* End of channel array defines of VDC5 */
+
+
+#define VDC50INP_UPDATE (VDC50.INP_UPDATE)
+#define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT)
+#define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT)
+#define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ)
+#define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ)
+#define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE)
+#define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0)
+#define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1)
+#define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE)
+#define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0)
+#define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1)
+#define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0)
+#define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1)
+#define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0)
+#define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1)
+#define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG)
+#define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE)
+#define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1)
+#define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2)
+#define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3)
+#define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4)
+#define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5)
+#define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6)
+#define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7)
+#define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9)
+#define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0)
+#define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT)
+#define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1)
+#define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2)
+#define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3)
+#define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4)
+#define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5)
+#define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6)
+#define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7)
+#define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1)
+#define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2)
+#define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3)
+#define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4)
+#define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5)
+#define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6)
+#define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7)
+#define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8)
+#define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1)
+#define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE)
+#define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1)
+#define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2)
+#define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3)
+#define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4)
+#define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5)
+#define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6)
+#define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7)
+#define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8)
+#define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9)
+#define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10)
+#define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11)
+#define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1)
+#define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0)
+#define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1)
+#define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2)
+#define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3)
+#define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD)
+#define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT)
+#define VDC50GR0_UPDATE (VDC50.GR0_UPDATE)
+#define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD)
+#define VDC50GR0_FLM1 (VDC50.GR0_FLM1)
+#define VDC50GR0_FLM2 (VDC50.GR0_FLM2)
+#define VDC50GR0_FLM3 (VDC50.GR0_FLM3)
+#define VDC50GR0_FLM4 (VDC50.GR0_FLM4)
+#define VDC50GR0_FLM5 (VDC50.GR0_FLM5)
+#define VDC50GR0_FLM6 (VDC50.GR0_FLM6)
+#define VDC50GR0_AB1 (VDC50.GR0_AB1)
+#define VDC50GR0_AB2 (VDC50.GR0_AB2)
+#define VDC50GR0_AB3 (VDC50.GR0_AB3)
+#define VDC50GR0_AB7 (VDC50.GR0_AB7)
+#define VDC50GR0_AB8 (VDC50.GR0_AB8)
+#define VDC50GR0_AB9 (VDC50.GR0_AB9)
+#define VDC50GR0_AB10 (VDC50.GR0_AB10)
+#define VDC50GR0_AB11 (VDC50.GR0_AB11)
+#define VDC50GR0_BASE (VDC50.GR0_BASE)
+#define VDC50GR0_CLUT (VDC50.GR0_CLUT)
+#define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE)
+#define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET)
+#define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1)
+#define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2)
+#define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3)
+#define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1)
+#define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2)
+#define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3)
+#define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4)
+#define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5)
+#define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6)
+#define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1)
+#define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2)
+#define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE)
+#define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0)
+#define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1)
+#define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0)
+#define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1)
+#define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0)
+#define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1)
+#define VDC50GR2_UPDATE (VDC50.GR2_UPDATE)
+#define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD)
+#define VDC50GR2_FLM1 (VDC50.GR2_FLM1)
+#define VDC50GR2_FLM2 (VDC50.GR2_FLM2)
+#define VDC50GR2_FLM3 (VDC50.GR2_FLM3)
+#define VDC50GR2_FLM4 (VDC50.GR2_FLM4)
+#define VDC50GR2_FLM5 (VDC50.GR2_FLM5)
+#define VDC50GR2_FLM6 (VDC50.GR2_FLM6)
+#define VDC50GR2_AB1 (VDC50.GR2_AB1)
+#define VDC50GR2_AB2 (VDC50.GR2_AB2)
+#define VDC50GR2_AB3 (VDC50.GR2_AB3)
+#define VDC50GR2_AB4 (VDC50.GR2_AB4)
+#define VDC50GR2_AB5 (VDC50.GR2_AB5)
+#define VDC50GR2_AB6 (VDC50.GR2_AB6)
+#define VDC50GR2_AB7 (VDC50.GR2_AB7)
+#define VDC50GR2_AB8 (VDC50.GR2_AB8)
+#define VDC50GR2_AB9 (VDC50.GR2_AB9)
+#define VDC50GR2_AB10 (VDC50.GR2_AB10)
+#define VDC50GR2_AB11 (VDC50.GR2_AB11)
+#define VDC50GR2_BASE (VDC50.GR2_BASE)
+#define VDC50GR2_CLUT (VDC50.GR2_CLUT)
+#define VDC50GR2_MON (VDC50.GR2_MON)
+#define VDC50GR3_UPDATE (VDC50.GR3_UPDATE)
+#define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD)
+#define VDC50GR3_FLM1 (VDC50.GR3_FLM1)
+#define VDC50GR3_FLM2 (VDC50.GR3_FLM2)
+#define VDC50GR3_FLM3 (VDC50.GR3_FLM3)
+#define VDC50GR3_FLM4 (VDC50.GR3_FLM4)
+#define VDC50GR3_FLM5 (VDC50.GR3_FLM5)
+#define VDC50GR3_FLM6 (VDC50.GR3_FLM6)
+#define VDC50GR3_AB1 (VDC50.GR3_AB1)
+#define VDC50GR3_AB2 (VDC50.GR3_AB2)
+#define VDC50GR3_AB3 (VDC50.GR3_AB3)
+#define VDC50GR3_AB4 (VDC50.GR3_AB4)
+#define VDC50GR3_AB5 (VDC50.GR3_AB5)
+#define VDC50GR3_AB6 (VDC50.GR3_AB6)
+#define VDC50GR3_AB7 (VDC50.GR3_AB7)
+#define VDC50GR3_AB8 (VDC50.GR3_AB8)
+#define VDC50GR3_AB9 (VDC50.GR3_AB9)
+#define VDC50GR3_AB10 (VDC50.GR3_AB10)
+#define VDC50GR3_AB11 (VDC50.GR3_AB11)
+#define VDC50GR3_BASE (VDC50.GR3_BASE)
+#define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT)
+#define VDC50GR3_MON (VDC50.GR3_MON)
+#define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE)
+#define VDC50GAM_SW (VDC50.GAM_SW)
+#define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1)
+#define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2)
+#define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3)
+#define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4)
+#define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5)
+#define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6)
+#define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7)
+#define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8)
+#define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9)
+#define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10)
+#define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11)
+#define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12)
+#define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13)
+#define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14)
+#define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15)
+#define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16)
+#define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1)
+#define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2)
+#define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3)
+#define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4)
+#define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5)
+#define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6)
+#define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7)
+#define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8)
+#define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE)
+#define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1)
+#define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2)
+#define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3)
+#define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4)
+#define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5)
+#define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6)
+#define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7)
+#define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8)
+#define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9)
+#define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10)
+#define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11)
+#define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12)
+#define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13)
+#define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14)
+#define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15)
+#define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16)
+#define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1)
+#define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2)
+#define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3)
+#define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4)
+#define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5)
+#define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6)
+#define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7)
+#define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8)
+#define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE)
+#define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1)
+#define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2)
+#define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3)
+#define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4)
+#define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5)
+#define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6)
+#define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7)
+#define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8)
+#define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9)
+#define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10)
+#define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11)
+#define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12)
+#define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13)
+#define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14)
+#define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15)
+#define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16)
+#define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1)
+#define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2)
+#define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3)
+#define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4)
+#define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5)
+#define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6)
+#define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7)
+#define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8)
+#define VDC50TCON_UPDATE (VDC50.TCON_UPDATE)
+#define VDC50TCON_TIM (VDC50.TCON_TIM)
+#define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1)
+#define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2)
+#define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1)
+#define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2)
+#define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1)
+#define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2)
+#define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1)
+#define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2)
+#define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1)
+#define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2)
+#define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1)
+#define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2)
+#define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1)
+#define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2)
+#define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE)
+#define VDC50OUT_UPDATE (VDC50.OUT_UPDATE)
+#define VDC50OUT_SET (VDC50.OUT_SET)
+#define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1)
+#define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2)
+#define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST)
+#define VDC50OUT_PDTHA (VDC50.OUT_PDTHA)
+#define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE)
+#define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1)
+#define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2)
+#define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3)
+#define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4)
+#define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5)
+#define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6)
+#define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK)
+#define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT)
+#define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE)
+#define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1)
+#define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2)
+#define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3)
+#define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4)
+#define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5)
+#define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6)
+#define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7)
+#define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9)
+#define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0)
+#define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT)
+#define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1)
+#define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2)
+#define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3)
+#define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4)
+#define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5)
+#define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6)
+#define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7)
+#define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1)
+#define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2)
+#define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3)
+#define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4)
+#define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5)
+#define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6)
+#define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7)
+#define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8)
+#define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1)
+#define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE)
+#define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1)
+#define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2)
+#define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3)
+#define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4)
+#define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5)
+#define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6)
+#define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7)
+#define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8)
+#define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9)
+#define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10)
+#define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11)
+#define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1)
+#define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0)
+#define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1)
+#define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2)
+#define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3)
+#define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD)
+#define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT)
+#define VDC50GR1_UPDATE (VDC50.GR1_UPDATE)
+#define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD)
+#define VDC50GR1_FLM1 (VDC50.GR1_FLM1)
+#define VDC50GR1_FLM2 (VDC50.GR1_FLM2)
+#define VDC50GR1_FLM3 (VDC50.GR1_FLM3)
+#define VDC50GR1_FLM4 (VDC50.GR1_FLM4)
+#define VDC50GR1_FLM5 (VDC50.GR1_FLM5)
+#define VDC50GR1_FLM6 (VDC50.GR1_FLM6)
+#define VDC50GR1_AB1 (VDC50.GR1_AB1)
+#define VDC50GR1_AB2 (VDC50.GR1_AB2)
+#define VDC50GR1_AB3 (VDC50.GR1_AB3)
+#define VDC50GR1_AB4 (VDC50.GR1_AB4)
+#define VDC50GR1_AB5 (VDC50.GR1_AB5)
+#define VDC50GR1_AB6 (VDC50.GR1_AB6)
+#define VDC50GR1_AB7 (VDC50.GR1_AB7)
+#define VDC50GR1_AB8 (VDC50.GR1_AB8)
+#define VDC50GR1_AB9 (VDC50.GR1_AB9)
+#define VDC50GR1_AB10 (VDC50.GR1_AB10)
+#define VDC50GR1_AB11 (VDC50.GR1_AB11)
+#define VDC50GR1_BASE (VDC50.GR1_BASE)
+#define VDC50GR1_CLUT (VDC50.GR1_CLUT)
+#define VDC50GR1_MON (VDC50.GR1_MON)
+#define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE)
+#define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET)
+#define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1)
+#define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2)
+#define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3)
+#define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1)
+#define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2)
+#define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3)
+#define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4)
+#define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5)
+#define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6)
+#define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1)
+#define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2)
+#define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE)
+#define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0)
+#define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1)
+#define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0)
+#define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1)
+#define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0)
+#define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1)
+#define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE)
+#define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1)
+#define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2)
+#define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3)
+#define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4)
+#define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5)
+#define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6)
+#define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7)
+#define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE)
+#define VDC50GR_VIN_MON (VDC50.GR_VIN_MON)
+#define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE)
+#define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1)
+#define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2)
+#define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3)
+#define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4)
+#define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5)
+#define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6)
+#define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7)
+#define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1)
+#define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2)
+#define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3)
+#define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7)
+#define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1)
+#define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2)
+#define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3)
+#define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8)
+#define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1)
+#define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE)
+#define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1)
+#define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2)
+#define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3)
+#define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4)
+#define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5)
+#define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6)
+#define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7)
+#define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE)
+#define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD)
+#define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1)
+#define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2)
+#define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3)
+#define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4)
+#define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5)
+#define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6)
+#define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1)
+#define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2)
+#define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3)
+#define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7)
+#define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8)
+#define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9)
+#define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10)
+#define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11)
+#define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE)
+#define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT)
+#define VDC50GR_OIR_MON (VDC50.GR_OIR_MON)
+#define VDC51INP_UPDATE (VDC51.INP_UPDATE)
+#define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT)
+#define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT)
+#define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ)
+#define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ)
+#define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE)
+#define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0)
+#define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1)
+#define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE)
+#define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0)
+#define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1)
+#define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0)
+#define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1)
+#define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0)
+#define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1)
+#define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG)
+#define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE)
+#define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1)
+#define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2)
+#define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3)
+#define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4)
+#define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5)
+#define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6)
+#define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7)
+#define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9)
+#define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0)
+#define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT)
+#define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1)
+#define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2)
+#define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3)
+#define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4)
+#define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5)
+#define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6)
+#define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7)
+#define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1)
+#define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2)
+#define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3)
+#define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4)
+#define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5)
+#define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6)
+#define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7)
+#define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8)
+#define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1)
+#define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE)
+#define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1)
+#define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2)
+#define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3)
+#define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4)
+#define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5)
+#define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6)
+#define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7)
+#define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8)
+#define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9)
+#define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10)
+#define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11)
+#define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1)
+#define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0)
+#define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1)
+#define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2)
+#define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3)
+#define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD)
+#define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT)
+#define VDC51GR0_UPDATE (VDC51.GR0_UPDATE)
+#define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD)
+#define VDC51GR0_FLM1 (VDC51.GR0_FLM1)
+#define VDC51GR0_FLM2 (VDC51.GR0_FLM2)
+#define VDC51GR0_FLM3 (VDC51.GR0_FLM3)
+#define VDC51GR0_FLM4 (VDC51.GR0_FLM4)
+#define VDC51GR0_FLM5 (VDC51.GR0_FLM5)
+#define VDC51GR0_FLM6 (VDC51.GR0_FLM6)
+#define VDC51GR0_AB1 (VDC51.GR0_AB1)
+#define VDC51GR0_AB2 (VDC51.GR0_AB2)
+#define VDC51GR0_AB3 (VDC51.GR0_AB3)
+#define VDC51GR0_AB7 (VDC51.GR0_AB7)
+#define VDC51GR0_AB8 (VDC51.GR0_AB8)
+#define VDC51GR0_AB9 (VDC51.GR0_AB9)
+#define VDC51GR0_AB10 (VDC51.GR0_AB10)
+#define VDC51GR0_AB11 (VDC51.GR0_AB11)
+#define VDC51GR0_BASE (VDC51.GR0_BASE)
+#define VDC51GR0_CLUT (VDC51.GR0_CLUT)
+#define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE)
+#define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET)
+#define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1)
+#define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2)
+#define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3)
+#define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1)
+#define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2)
+#define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3)
+#define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4)
+#define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5)
+#define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6)
+#define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1)
+#define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2)
+#define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE)
+#define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0)
+#define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1)
+#define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0)
+#define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1)
+#define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0)
+#define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1)
+#define VDC51GR2_UPDATE (VDC51.GR2_UPDATE)
+#define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD)
+#define VDC51GR2_FLM1 (VDC51.GR2_FLM1)
+#define VDC51GR2_FLM2 (VDC51.GR2_FLM2)
+#define VDC51GR2_FLM3 (VDC51.GR2_FLM3)
+#define VDC51GR2_FLM4 (VDC51.GR2_FLM4)
+#define VDC51GR2_FLM5 (VDC51.GR2_FLM5)
+#define VDC51GR2_FLM6 (VDC51.GR2_FLM6)
+#define VDC51GR2_AB1 (VDC51.GR2_AB1)
+#define VDC51GR2_AB2 (VDC51.GR2_AB2)
+#define VDC51GR2_AB3 (VDC51.GR2_AB3)
+#define VDC51GR2_AB4 (VDC51.GR2_AB4)
+#define VDC51GR2_AB5 (VDC51.GR2_AB5)
+#define VDC51GR2_AB6 (VDC51.GR2_AB6)
+#define VDC51GR2_AB7 (VDC51.GR2_AB7)
+#define VDC51GR2_AB8 (VDC51.GR2_AB8)
+#define VDC51GR2_AB9 (VDC51.GR2_AB9)
+#define VDC51GR2_AB10 (VDC51.GR2_AB10)
+#define VDC51GR2_AB11 (VDC51.GR2_AB11)
+#define VDC51GR2_BASE (VDC51.GR2_BASE)
+#define VDC51GR2_CLUT (VDC51.GR2_CLUT)
+#define VDC51GR2_MON (VDC51.GR2_MON)
+#define VDC51GR3_UPDATE (VDC51.GR3_UPDATE)
+#define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD)
+#define VDC51GR3_FLM1 (VDC51.GR3_FLM1)
+#define VDC51GR3_FLM2 (VDC51.GR3_FLM2)
+#define VDC51GR3_FLM3 (VDC51.GR3_FLM3)
+#define VDC51GR3_FLM4 (VDC51.GR3_FLM4)
+#define VDC51GR3_FLM5 (VDC51.GR3_FLM5)
+#define VDC51GR3_FLM6 (VDC51.GR3_FLM6)
+#define VDC51GR3_AB1 (VDC51.GR3_AB1)
+#define VDC51GR3_AB2 (VDC51.GR3_AB2)
+#define VDC51GR3_AB3 (VDC51.GR3_AB3)
+#define VDC51GR3_AB4 (VDC51.GR3_AB4)
+#define VDC51GR3_AB5 (VDC51.GR3_AB5)
+#define VDC51GR3_AB6 (VDC51.GR3_AB6)
+#define VDC51GR3_AB7 (VDC51.GR3_AB7)
+#define VDC51GR3_AB8 (VDC51.GR3_AB8)
+#define VDC51GR3_AB9 (VDC51.GR3_AB9)
+#define VDC51GR3_AB10 (VDC51.GR3_AB10)
+#define VDC51GR3_AB11 (VDC51.GR3_AB11)
+#define VDC51GR3_BASE (VDC51.GR3_BASE)
+#define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT)
+#define VDC51GR3_MON (VDC51.GR3_MON)
+#define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE)
+#define VDC51GAM_SW (VDC51.GAM_SW)
+#define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1)
+#define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2)
+#define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3)
+#define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4)
+#define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5)
+#define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6)
+#define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7)
+#define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8)
+#define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9)
+#define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10)
+#define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11)
+#define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12)
+#define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13)
+#define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14)
+#define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15)
+#define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16)
+#define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1)
+#define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2)
+#define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3)
+#define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4)
+#define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5)
+#define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6)
+#define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7)
+#define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8)
+#define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE)
+#define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1)
+#define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2)
+#define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3)
+#define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4)
+#define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5)
+#define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6)
+#define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7)
+#define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8)
+#define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9)
+#define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10)
+#define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11)
+#define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12)
+#define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13)
+#define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14)
+#define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15)
+#define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16)
+#define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1)
+#define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2)
+#define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3)
+#define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4)
+#define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5)
+#define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6)
+#define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7)
+#define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8)
+#define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE)
+#define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1)
+#define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2)
+#define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3)
+#define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4)
+#define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5)
+#define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6)
+#define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7)
+#define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8)
+#define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9)
+#define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10)
+#define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11)
+#define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12)
+#define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13)
+#define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14)
+#define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15)
+#define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16)
+#define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1)
+#define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2)
+#define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3)
+#define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4)
+#define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5)
+#define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6)
+#define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7)
+#define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8)
+#define VDC51TCON_UPDATE (VDC51.TCON_UPDATE)
+#define VDC51TCON_TIM (VDC51.TCON_TIM)
+#define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1)
+#define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2)
+#define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1)
+#define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2)
+#define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1)
+#define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2)
+#define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1)
+#define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2)
+#define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1)
+#define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2)
+#define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1)
+#define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2)
+#define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1)
+#define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2)
+#define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE)
+#define VDC51OUT_UPDATE (VDC51.OUT_UPDATE)
+#define VDC51OUT_SET (VDC51.OUT_SET)
+#define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1)
+#define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2)
+#define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST)
+#define VDC51OUT_PDTHA (VDC51.OUT_PDTHA)
+#define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE)
+#define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1)
+#define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2)
+#define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3)
+#define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4)
+#define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5)
+#define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6)
+#define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK)
+#define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT)
+#define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE)
+#define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1)
+#define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2)
+#define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3)
+#define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4)
+#define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5)
+#define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6)
+#define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7)
+#define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9)
+#define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0)
+#define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT)
+#define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1)
+#define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2)
+#define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3)
+#define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4)
+#define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5)
+#define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6)
+#define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7)
+#define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1)
+#define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2)
+#define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3)
+#define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4)
+#define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5)
+#define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6)
+#define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7)
+#define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8)
+#define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1)
+#define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE)
+#define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1)
+#define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2)
+#define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3)
+#define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4)
+#define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5)
+#define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6)
+#define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7)
+#define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8)
+#define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9)
+#define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10)
+#define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11)
+#define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1)
+#define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0)
+#define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1)
+#define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2)
+#define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3)
+#define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD)
+#define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT)
+#define VDC51GR1_UPDATE (VDC51.GR1_UPDATE)
+#define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD)
+#define VDC51GR1_FLM1 (VDC51.GR1_FLM1)
+#define VDC51GR1_FLM2 (VDC51.GR1_FLM2)
+#define VDC51GR1_FLM3 (VDC51.GR1_FLM3)
+#define VDC51GR1_FLM4 (VDC51.GR1_FLM4)
+#define VDC51GR1_FLM5 (VDC51.GR1_FLM5)
+#define VDC51GR1_FLM6 (VDC51.GR1_FLM6)
+#define VDC51GR1_AB1 (VDC51.GR1_AB1)
+#define VDC51GR1_AB2 (VDC51.GR1_AB2)
+#define VDC51GR1_AB3 (VDC51.GR1_AB3)
+#define VDC51GR1_AB4 (VDC51.GR1_AB4)
+#define VDC51GR1_AB5 (VDC51.GR1_AB5)
+#define VDC51GR1_AB6 (VDC51.GR1_AB6)
+#define VDC51GR1_AB7 (VDC51.GR1_AB7)
+#define VDC51GR1_AB8 (VDC51.GR1_AB8)
+#define VDC51GR1_AB9 (VDC51.GR1_AB9)
+#define VDC51GR1_AB10 (VDC51.GR1_AB10)
+#define VDC51GR1_AB11 (VDC51.GR1_AB11)
+#define VDC51GR1_BASE (VDC51.GR1_BASE)
+#define VDC51GR1_CLUT (VDC51.GR1_CLUT)
+#define VDC51GR1_MON (VDC51.GR1_MON)
+#define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE)
+#define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET)
+#define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1)
+#define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2)
+#define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3)
+#define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1)
+#define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2)
+#define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3)
+#define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4)
+#define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5)
+#define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6)
+#define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1)
+#define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2)
+#define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE)
+#define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0)
+#define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1)
+#define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0)
+#define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1)
+#define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0)
+#define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1)
+#define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE)
+#define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1)
+#define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2)
+#define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3)
+#define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4)
+#define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5)
+#define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6)
+#define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7)
+#define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE)
+#define VDC51GR_VIN_MON (VDC51.GR_VIN_MON)
+#define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE)
+#define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1)
+#define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2)
+#define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3)
+#define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4)
+#define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5)
+#define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6)
+#define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7)
+#define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1)
+#define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2)
+#define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3)
+#define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7)
+#define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1)
+#define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2)
+#define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3)
+#define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8)
+#define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1)
+#define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE)
+#define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1)
+#define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2)
+#define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3)
+#define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4)
+#define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5)
+#define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6)
+#define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7)
+#define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE)
+#define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD)
+#define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1)
+#define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2)
+#define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3)
+#define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4)
+#define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5)
+#define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6)
+#define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1)
+#define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2)
+#define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3)
+#define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7)
+#define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8)
+#define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9)
+#define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10)
+#define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11)
+#define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE)
+#define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT)
+#define VDC51GR_OIR_MON (VDC51.GR_OIR_MON)
+
+#define VDC5_IMGCNT_NR_CNT0_COUNT (2)
+#define VDC5_SC0_SCL0_FRC1_COUNT (7)
+#define VDC5_SC0_SCL0_DS1_COUNT (7)
+#define VDC5_SC0_SCL0_US1_COUNT (8)
+#define VDC5_SC0_SCL1_WR1_COUNT (4)
+#define VDC5_SC0_SCL1_PBUF0_COUNT (4)
+#define VDC5_GR0_FLM1_COUNT (6)
+#define VDC5_GR0_AB1_COUNT (3)
+#define VDC5_ADJ0_ENH_TIM1_COUNT (3)
+#define VDC5_ADJ0_ENH_SHP1_COUNT (6)
+#define VDC5_ADJ0_ENH_LTI1_COUNT (2)
+#define VDC5_GR2_FLM1_COUNT (6)
+#define VDC5_GR2_AB1_COUNT (3)
+#define VDC5_GR3_FLM1_COUNT (6)
+#define VDC5_GR3_AB1_COUNT (3)
+#define VDC5_GAM_G_LUT1_COUNT (16)
+#define VDC5_GAM_G_AREA1_COUNT (8)
+#define VDC5_GAM_B_LUT1_COUNT (16)
+#define VDC5_GAM_B_AREA1_COUNT (8)
+#define VDC5_GAM_R_LUT1_COUNT (16)
+#define VDC5_GAM_R_AREA1_COUNT (8)
+#define VDC5_TCON_TIM_STVA1_COUNT (2)
+#define VDC5_TCON_TIM_STVB1_COUNT (2)
+#define VDC5_TCON_TIM_STH1_COUNT (2)
+#define VDC5_TCON_TIM_STB1_COUNT (2)
+#define VDC5_TCON_TIM_CPV1_COUNT (2)
+#define VDC5_TCON_TIM_POLA1_COUNT (2)
+#define VDC5_TCON_TIM_POLB1_COUNT (2)
+#define VDC5_OUT_BRIGHT1_COUNT (2)
+#define VDC5_SYSCNT_INT1_COUNT (6)
+#define VDC5_SC1_SCL0_FRC1_COUNT (7)
+#define VDC5_SC1_SC1_SCL0_DS1_COUNT (7)
+#define VDC5_SC1_SC1_SCL0_US1_COUNT (8)
+#define VDC5_SC1_SCL1_WR1_COUNT (4)
+#define VDC5_SC1_SCL1_PBUF0_COUNT (4)
+#define VDC5_GR1_FLM1_COUNT (6)
+#define VDC5_GR1_AB1_COUNT (3)
+#define VDC5_ADJ1_ENH_TIM1_COUNT (3)
+#define VDC5_ADJ1_ENH_SHP1_COUNT (6)
+#define VDC5_ADJ1_ENH_LTI1_COUNT (2)
+#define VDC5_GR_VIN_AB1_COUNT (7)
+#define VDC5_OIR_SCL0_FRC1_COUNT (7)
+#define VDC5_OIR_SCL0_DS1_COUNT (3)
+#define VDC5_OIR_SCL1_WR1_COUNT (4)
+#define VDC5_GR_OIR_FLM1_COUNT (6)
+#define VDC5_GR_OIR_AB1_COUNT (3)
+
+
+typedef struct st_vdc5
+{
+                                                           /* VDC5             */
     volatile uint32_t  INP_UPDATE;                             /*  INP_UPDATE      */
     volatile uint32_t  INP_SEL_CNT;                            /*  INP_SEL_CNT     */
     volatile uint32_t  INP_EXT_SYNC_CNT;                       /*  INP_EXT_SYNC_CNT */
@@ -40,7 +1023,8 @@
     volatile uint32_t  INP_DLY_ADJ;                            /*  INP_DLY_ADJ     */
     volatile uint8_t   dummy1[108];                            /*                  */
     volatile uint32_t  IMGCNT_UPDATE;                          /*  IMGCNT_UPDATE   */
-#define VDC5_IMGCNT_NR_CNT0_COUNT 2
+
+/* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */
     volatile uint32_t  IMGCNT_NR_CNT0;                         /*  IMGCNT_NR_CNT0  */
     volatile uint32_t  IMGCNT_NR_CNT1;                         /*  IMGCNT_NR_CNT1  */
     volatile uint8_t   dummy2[20];                             /*                  */
@@ -54,9 +1038,11 @@
     volatile uint8_t   dummy3[4];                              /*                  */
     volatile uint32_t  IMGCNT_DRC_REG;                         /*  IMGCNT_DRC_REG  */
     volatile uint8_t   dummy4[60];                             /*                  */
+
 /* start of struct st_vdc5_from_sc0_scl0_update */
     volatile uint32_t  SC0_SCL0_UPDATE;                        /*  SC0_SCL0_UPDATE */
-#define VDC5_SC0_SCL0_FRC1_COUNT 7
+
+/* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */
     volatile uint32_t  SC0_SCL0_FRC1;                          /*  SC0_SCL0_FRC1   */
     volatile uint32_t  SC0_SCL0_FRC2;                          /*  SC0_SCL0_FRC2   */
     volatile uint32_t  SC0_SCL0_FRC3;                          /*  SC0_SCL0_FRC3   */
@@ -68,7 +1054,8 @@
     volatile uint32_t  SC0_SCL0_FRC9;                          /*  SC0_SCL0_FRC9   */
     volatile uint16_t SC0_SCL0_MON0;                          /*  SC0_SCL0_MON0   */
     volatile uint16_t SC0_SCL0_INT;                           /*  SC0_SCL0_INT    */
-#define VDC5_SC0_SCL0_DS1_COUNT 7
+
+/* #define VDC5_SC0_SCL0_DS1_COUNT (7) */
     volatile uint32_t  SC0_SCL0_DS1;                           /*  SC0_SCL0_DS1    */
     volatile uint32_t  SC0_SCL0_DS2;                           /*  SC0_SCL0_DS2    */
     volatile uint32_t  SC0_SCL0_DS3;                           /*  SC0_SCL0_DS3    */
@@ -76,7 +1063,8 @@
     volatile uint32_t  SC0_SCL0_DS5;                           /*  SC0_SCL0_DS5    */
     volatile uint32_t  SC0_SCL0_DS6;                           /*  SC0_SCL0_DS6    */
     volatile uint32_t  SC0_SCL0_DS7;                           /*  SC0_SCL0_DS7    */
-#define VDC5_SC0_SCL0_US1_COUNT 8
+
+/* #define VDC5_SC0_SCL0_US1_COUNT (8) */
     volatile uint32_t  SC0_SCL0_US1;                           /*  SC0_SCL0_US1    */
     volatile uint32_t  SC0_SCL0_US2;                           /*  SC0_SCL0_US2    */
     volatile uint32_t  SC0_SCL0_US3;                           /*  SC0_SCL0_US3    */
@@ -90,7 +1078,8 @@
     volatile uint8_t   dummy7[16];                             /*                  */
     volatile uint32_t  SC0_SCL1_UPDATE;                        /*  SC0_SCL1_UPDATE */
     volatile uint8_t   dummy8[4];                              /*                  */
-#define VDC5_SC0_SCL1_WR1_COUNT 4
+
+/* #define VDC5_SC0_SCL1_WR1_COUNT (4) */
     volatile uint32_t  SC0_SCL1_WR1;                           /*  SC0_SCL1_WR1    */
     volatile uint32_t  SC0_SCL1_WR2;                           /*  SC0_SCL1_WR2    */
     volatile uint32_t  SC0_SCL1_WR3;                           /*  SC0_SCL1_WR3    */
@@ -102,35 +1091,44 @@
     volatile uint32_t  SC0_SCL1_WR8;                           /*  SC0_SCL1_WR8    */
     volatile uint32_t  SC0_SCL1_WR9;                           /*  SC0_SCL1_WR9    */
     volatile uint32_t  SC0_SCL1_WR10;                          /*  SC0_SCL1_WR10   */
+
 /* end of struct st_vdc5_from_sc0_scl0_update */
     volatile uint32_t  SC0_SCL1_WR11;                          /*  SC0_SCL1_WR11   */
     volatile uint32_t  SC0_SCL1_MON1;                          /*  SC0_SCL1_MON1   */
+
 /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
-#define VDC5_SC0_SCL1_PBUF0_COUNT 4
+
+/* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */
     volatile uint32_t  SC0_SCL1_PBUF0;                         /*  SC0_SCL1_PBUF0  */
     volatile uint32_t  SC0_SCL1_PBUF1;                         /*  SC0_SCL1_PBUF1  */
     volatile uint32_t  SC0_SCL1_PBUF2;                         /*  SC0_SCL1_PBUF2  */
     volatile uint32_t  SC0_SCL1_PBUF3;                         /*  SC0_SCL1_PBUF3  */
     volatile uint32_t  SC0_SCL1_PBUF_FLD;                      /*  SC0_SCL1_PBUF_FLD */
     volatile uint32_t  SC0_SCL1_PBUF_CNT;                      /*  SC0_SCL1_PBUF_CNT */
+
 /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
     volatile uint8_t   dummy10[44];                            /*                  */
+
 /* start of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR0_UPDATE;                             /*  GR0_UPDATE      */
     volatile uint32_t  GR0_FLM_RD;                             /*  GR0_FLM_RD      */
-#define VDC5_GR0_FLM1_COUNT 6
+
+/* #define VDC5_GR0_FLM1_COUNT (6) */
     volatile uint32_t  GR0_FLM1;                               /*  GR0_FLM1        */
     volatile uint32_t  GR0_FLM2;                               /*  GR0_FLM2        */
     volatile uint32_t  GR0_FLM3;                               /*  GR0_FLM3        */
     volatile uint32_t  GR0_FLM4;                               /*  GR0_FLM4        */
     volatile uint32_t  GR0_FLM5;                               /*  GR0_FLM5        */
     volatile uint32_t  GR0_FLM6;                               /*  GR0_FLM6        */
-#define VDC5_GR0_AB1_COUNT 3
+
+/* #define VDC5_GR0_AB1_COUNT (3) */
     volatile uint32_t  GR0_AB1;                                /*  GR0_AB1         */
     volatile uint32_t  GR0_AB2;                                /*  GR0_AB2         */
     volatile uint32_t  GR0_AB3;                                /*  GR0_AB3         */
+
 /* end of struct st_vdc5_from_gr0_update */
     volatile uint8_t   dummy11[12];                            /*                  */
+
 /* start of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR0_AB7;                                /*  GR0_AB7         */
     volatile uint32_t  GR0_AB8;                                /*  GR0_AB8         */
@@ -138,24 +1136,29 @@
     volatile uint32_t  GR0_AB10;                               /*  GR0_AB10        */
     volatile uint32_t  GR0_AB11;                               /*  GR0_AB11        */
     volatile uint32_t  GR0_BASE;                               /*  GR0_BASE        */
+
 /* end of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR0_CLUT;                               /*  GR0_CLUT        */
     volatile uint8_t   dummy12[44];                            /*                  */
+
 /* start of struct st_vdc5_from_adj0_update */
     volatile uint32_t  ADJ0_UPDATE;                            /*  ADJ0_UPDATE     */
     volatile uint32_t  ADJ0_BKSTR_SET;                         /*  ADJ0_BKSTR_SET  */
-#define VDC5_ADJ0_ENH_TIM1_COUNT 3
+
+/* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */
     volatile uint32_t  ADJ0_ENH_TIM1;                          /*  ADJ0_ENH_TIM1   */
     volatile uint32_t  ADJ0_ENH_TIM2;                          /*  ADJ0_ENH_TIM2   */
     volatile uint32_t  ADJ0_ENH_TIM3;                          /*  ADJ0_ENH_TIM3   */
-#define VDC5_ADJ0_ENH_SHP1_COUNT 6
+
+/* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */
     volatile uint32_t  ADJ0_ENH_SHP1;                          /*  ADJ0_ENH_SHP1   */
     volatile uint32_t  ADJ0_ENH_SHP2;                          /*  ADJ0_ENH_SHP2   */
     volatile uint32_t  ADJ0_ENH_SHP3;                          /*  ADJ0_ENH_SHP3   */
     volatile uint32_t  ADJ0_ENH_SHP4;                          /*  ADJ0_ENH_SHP4   */
     volatile uint32_t  ADJ0_ENH_SHP5;                          /*  ADJ0_ENH_SHP5   */
     volatile uint32_t  ADJ0_ENH_SHP6;                          /*  ADJ0_ENH_SHP6   */
-#define VDC5_ADJ0_ENH_LTI1_COUNT 2
+
+/* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */
     volatile uint32_t  ADJ0_ENH_LTI1;                          /*  ADJ0_ENH_LTI1   */
     volatile uint32_t  ADJ0_ENH_LTI2;                          /*  ADJ0_ENH_LTI2   */
     volatile uint32_t  ADJ0_MTX_MODE;                          /*  ADJ0_MTX_MODE   */
@@ -165,26 +1168,32 @@
     volatile uint32_t  ADJ0_MTX_CBB_ADJ1;                      /*  ADJ0_MTX_CBB_ADJ1 */
     volatile uint32_t  ADJ0_MTX_CRR_ADJ0;                      /*  ADJ0_MTX_CRR_ADJ0 */
     volatile uint32_t  ADJ0_MTX_CRR_ADJ1;                      /*  ADJ0_MTX_CRR_ADJ1 */
+
 /* end of struct st_vdc5_from_adj0_update */
     volatile uint8_t   dummy13[48];                            /*                  */
+
 /* start of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR2_UPDATE;                             /*  GR2_UPDATE      */
     volatile uint32_t  GR2_FLM_RD;                             /*  GR2_FLM_RD      */
-#define VDC5_GR2_FLM1_COUNT 6
+
+/* #define VDC5_GR2_FLM1_COUNT (6) */
     volatile uint32_t  GR2_FLM1;                               /*  GR2_FLM1        */
     volatile uint32_t  GR2_FLM2;                               /*  GR2_FLM2        */
     volatile uint32_t  GR2_FLM3;                               /*  GR2_FLM3        */
     volatile uint32_t  GR2_FLM4;                               /*  GR2_FLM4        */
     volatile uint32_t  GR2_FLM5;                               /*  GR2_FLM5        */
     volatile uint32_t  GR2_FLM6;                               /*  GR2_FLM6        */
-#define VDC5_GR2_AB1_COUNT 3
+
+/* #define VDC5_GR2_AB1_COUNT (3) */
     volatile uint32_t  GR2_AB1;                                /*  GR2_AB1         */
     volatile uint32_t  GR2_AB2;                                /*  GR2_AB2         */
     volatile uint32_t  GR2_AB3;                                /*  GR2_AB3         */
+
 /* end of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR2_AB4;                                /*  GR2_AB4         */
     volatile uint32_t  GR2_AB5;                                /*  GR2_AB5         */
     volatile uint32_t  GR2_AB6;                                /*  GR2_AB6         */
+
 /* start of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR2_AB7;                                /*  GR2_AB7         */
     volatile uint32_t  GR2_AB8;                                /*  GR2_AB8         */
@@ -192,28 +1201,34 @@
     volatile uint32_t  GR2_AB10;                               /*  GR2_AB10        */
     volatile uint32_t  GR2_AB11;                               /*  GR2_AB11        */
     volatile uint32_t  GR2_BASE;                               /*  GR2_BASE        */
+
 /* end of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR2_CLUT;                               /*  GR2_CLUT        */
     volatile uint32_t  GR2_MON;                                /*  GR2_MON         */
     volatile uint8_t   dummy14[40];                            /*                  */
+
 /* start of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR3_UPDATE;                             /*  GR3_UPDATE      */
     volatile uint32_t  GR3_FLM_RD;                             /*  GR3_FLM_RD      */
-#define VDC5_GR3_FLM1_COUNT 6
+
+/* #define VDC5_GR3_FLM1_COUNT (6) */
     volatile uint32_t  GR3_FLM1;                               /*  GR3_FLM1        */
     volatile uint32_t  GR3_FLM2;                               /*  GR3_FLM2        */
     volatile uint32_t  GR3_FLM3;                               /*  GR3_FLM3        */
     volatile uint32_t  GR3_FLM4;                               /*  GR3_FLM4        */
     volatile uint32_t  GR3_FLM5;                               /*  GR3_FLM5        */
     volatile uint32_t  GR3_FLM6;                               /*  GR3_FLM6        */
-#define VDC5_GR3_AB1_COUNT 3
+
+/* #define VDC5_GR3_AB1_COUNT (3) */
     volatile uint32_t  GR3_AB1;                                /*  GR3_AB1         */
     volatile uint32_t  GR3_AB2;                                /*  GR3_AB2         */
     volatile uint32_t  GR3_AB3;                                /*  GR3_AB3         */
+
 /* end of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR3_AB4;                                /*  GR3_AB4         */
     volatile uint32_t  GR3_AB5;                                /*  GR3_AB5         */
     volatile uint32_t  GR3_AB6;                                /*  GR3_AB6         */
+
 /* start of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR3_AB7;                                /*  GR3_AB7         */
     volatile uint32_t  GR3_AB8;                                /*  GR3_AB8         */
@@ -221,13 +1236,15 @@
     volatile uint32_t  GR3_AB10;                               /*  GR3_AB10        */
     volatile uint32_t  GR3_AB11;                               /*  GR3_AB11        */
     volatile uint32_t  GR3_BASE;                               /*  GR3_BASE        */
+
 /* end of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR3_CLUT_INT;                           /*  GR3_CLUT_INT    */
     volatile uint32_t  GR3_MON;                                /*  GR3_MON         */
     volatile uint8_t   dummy15[40];                            /*                  */
     volatile uint32_t  GAM_G_UPDATE;                           /*  GAM_G_UPDATE    */
     volatile uint32_t  GAM_SW;                                 /*  GAM_SW          */
-#define VDC5_GAM_G_LUT1_COUNT 16
+
+/* #define VDC5_GAM_G_LUT1_COUNT (16) */
     volatile uint32_t  GAM_G_LUT1;                             /*  GAM_G_LUT1      */
     volatile uint32_t  GAM_G_LUT2;                             /*  GAM_G_LUT2      */
     volatile uint32_t  GAM_G_LUT3;                             /*  GAM_G_LUT3      */
@@ -244,7 +1261,8 @@
     volatile uint32_t  GAM_G_LUT14;                            /*  GAM_G_LUT14     */
     volatile uint32_t  GAM_G_LUT15;                            /*  GAM_G_LUT15     */
     volatile uint32_t  GAM_G_LUT16;                            /*  GAM_G_LUT16     */
-#define VDC5_GAM_G_AREA1_COUNT 8
+
+/* #define VDC5_GAM_G_AREA1_COUNT (8) */
     volatile uint32_t  GAM_G_AREA1;                            /*  GAM_G_AREA1     */
     volatile uint32_t  GAM_G_AREA2;                            /*  GAM_G_AREA2     */
     volatile uint32_t  GAM_G_AREA3;                            /*  GAM_G_AREA3     */
@@ -256,7 +1274,8 @@
     volatile uint8_t   dummy16[24];                            /*                  */
     volatile uint32_t  GAM_B_UPDATE;                           /*  GAM_B_UPDATE    */
     volatile uint8_t   dummy17[4];                             /*                  */
-#define VDC5_GAM_B_LUT1_COUNT 16
+
+/* #define VDC5_GAM_B_LUT1_COUNT (16) */
     volatile uint32_t  GAM_B_LUT1;                             /*  GAM_B_LUT1      */
     volatile uint32_t  GAM_B_LUT2;                             /*  GAM_B_LUT2      */
     volatile uint32_t  GAM_B_LUT3;                             /*  GAM_B_LUT3      */
@@ -273,7 +1292,8 @@
     volatile uint32_t  GAM_B_LUT14;                            /*  GAM_B_LUT14     */
     volatile uint32_t  GAM_B_LUT15;                            /*  GAM_B_LUT15     */
     volatile uint32_t  GAM_B_LUT16;                            /*  GAM_B_LUT16     */
-#define VDC5_GAM_B_AREA1_COUNT 8
+
+/* #define VDC5_GAM_B_AREA1_COUNT (8) */
     volatile uint32_t  GAM_B_AREA1;                            /*  GAM_B_AREA1     */
     volatile uint32_t  GAM_B_AREA2;                            /*  GAM_B_AREA2     */
     volatile uint32_t  GAM_B_AREA3;                            /*  GAM_B_AREA3     */
@@ -285,7 +1305,8 @@
     volatile uint8_t   dummy18[24];                            /*                  */
     volatile uint32_t  GAM_R_UPDATE;                           /*  GAM_R_UPDATE    */
     volatile uint8_t   dummy19[4];                             /*                  */
-#define VDC5_GAM_R_LUT1_COUNT 16
+
+/* #define VDC5_GAM_R_LUT1_COUNT (16) */
     volatile uint32_t  GAM_R_LUT1;                             /*  GAM_R_LUT1      */
     volatile uint32_t  GAM_R_LUT2;                             /*  GAM_R_LUT2      */
     volatile uint32_t  GAM_R_LUT3;                             /*  GAM_R_LUT3      */
@@ -302,7 +1323,8 @@
     volatile uint32_t  GAM_R_LUT14;                            /*  GAM_R_LUT14     */
     volatile uint32_t  GAM_R_LUT15;                            /*  GAM_R_LUT15     */
     volatile uint32_t  GAM_R_LUT16;                            /*  GAM_R_LUT16     */
-#define VDC5_GAM_R_AREA1_COUNT 8
+
+/* #define VDC5_GAM_R_AREA1_COUNT (8) */
     volatile uint32_t  GAM_R_AREA1;                            /*  GAM_R_AREA1     */
     volatile uint32_t  GAM_R_AREA2;                            /*  GAM_R_AREA2     */
     volatile uint32_t  GAM_R_AREA3;                            /*  GAM_R_AREA3     */
@@ -314,32 +1336,40 @@
     volatile uint8_t   dummy20[24];                            /*                  */
     volatile uint32_t  TCON_UPDATE;                            /*  TCON_UPDATE     */
     volatile uint32_t  TCON_TIM;                               /*  TCON_TIM        */
-#define VDC5_TCON_TIM_STVA1_COUNT 2
+
+/* #define VDC5_TCON_TIM_STVA1_COUNT (2) */
     volatile uint32_t  TCON_TIM_STVA1;                         /*  TCON_TIM_STVA1  */
     volatile uint32_t  TCON_TIM_STVA2;                         /*  TCON_TIM_STVA2  */
-#define VDC5_TCON_TIM_STVB1_COUNT 2
+
+/* #define VDC5_TCON_TIM_STVB1_COUNT (2) */
     volatile uint32_t  TCON_TIM_STVB1;                         /*  TCON_TIM_STVB1  */
     volatile uint32_t  TCON_TIM_STVB2;                         /*  TCON_TIM_STVB2  */
-#define VDC5_TCON_TIM_STH1_COUNT 2
+
+/* #define VDC5_TCON_TIM_STH1_COUNT (2) */
     volatile uint32_t  TCON_TIM_STH1;                          /*  TCON_TIM_STH1   */
     volatile uint32_t  TCON_TIM_STH2;                          /*  TCON_TIM_STH2   */
-#define VDC5_TCON_TIM_STB1_COUNT 2
+
+/* #define VDC5_TCON_TIM_STB1_COUNT (2) */
     volatile uint32_t  TCON_TIM_STB1;                          /*  TCON_TIM_STB1   */
     volatile uint32_t  TCON_TIM_STB2;                          /*  TCON_TIM_STB2   */
-#define VDC5_TCON_TIM_CPV1_COUNT 2
+
+/* #define VDC5_TCON_TIM_CPV1_COUNT (2) */
     volatile uint32_t  TCON_TIM_CPV1;                          /*  TCON_TIM_CPV1   */
     volatile uint32_t  TCON_TIM_CPV2;                          /*  TCON_TIM_CPV2   */
-#define VDC5_TCON_TIM_POLA1_COUNT 2
+
+/* #define VDC5_TCON_TIM_POLA1_COUNT (2) */
     volatile uint32_t  TCON_TIM_POLA1;                         /*  TCON_TIM_POLA1  */
     volatile uint32_t  TCON_TIM_POLA2;                         /*  TCON_TIM_POLA2  */
-#define VDC5_TCON_TIM_POLB1_COUNT 2
+
+/* #define VDC5_TCON_TIM_POLB1_COUNT (2) */
     volatile uint32_t  TCON_TIM_POLB1;                         /*  TCON_TIM_POLB1  */
     volatile uint32_t  TCON_TIM_POLB2;                         /*  TCON_TIM_POLB2  */
     volatile uint32_t  TCON_TIM_DE;                            /*  TCON_TIM_DE     */
     volatile uint8_t   dummy21[60];                            /*                  */
     volatile uint32_t  OUT_UPDATE;                             /*  OUT_UPDATE      */
     volatile uint32_t  OUT_SET;                                /*  OUT_SET         */
-#define VDC5_OUT_BRIGHT1_COUNT 2
+
+/* #define VDC5_OUT_BRIGHT1_COUNT (2) */
     volatile uint32_t  OUT_BRIGHT1;                            /*  OUT_BRIGHT1     */
     volatile uint32_t  OUT_BRIGHT2;                            /*  OUT_BRIGHT2     */
     volatile uint32_t  OUT_CONTRAST;                           /*  OUT_CONTRAST    */
@@ -347,7 +1377,8 @@
     volatile uint8_t   dummy22[12];                            /*                  */
     volatile uint32_t  OUT_CLK_PHASE;                          /*  OUT_CLK_PHASE   */
     volatile uint8_t   dummy23[88];                            /*                  */
-#define VDC5_SYSCNT_INT1_COUNT 6
+
+/* #define VDC5_SYSCNT_INT1_COUNT (6) */
     volatile uint32_t  SYSCNT_INT1;                            /*  SYSCNT_INT1     */
     volatile uint32_t  SYSCNT_INT2;                            /*  SYSCNT_INT2     */
     volatile uint32_t  SYSCNT_INT3;                            /*  SYSCNT_INT3     */
@@ -357,9 +1388,11 @@
     volatile uint16_t SYSCNT_PANEL_CLK;                       /*  SYSCNT_PANEL_CLK */
     volatile uint16_t SYSCNT_CLUT;                            /*  SYSCNT_CLUT     */
     volatile uint8_t   dummy24[356];                           /*                  */
+
 /* start of struct st_vdc5_from_sc0_scl0_update */
     volatile uint32_t  SC1_SCL0_UPDATE;                        /*  SC1_SCL0_UPDATE */
-#define VDC5_SC1_SCL0_FRC1_COUNT 7
+
+/* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */
     volatile uint32_t  SC1_SCL0_FRC1;                          /*  SC1_SCL0_FRC1   */
     volatile uint32_t  SC1_SCL0_FRC2;                          /*  SC1_SCL0_FRC2   */
     volatile uint32_t  SC1_SCL0_FRC3;                          /*  SC1_SCL0_FRC3   */
@@ -371,7 +1404,8 @@
     volatile uint32_t  SC1_SCL0_FRC9;                          /*  SC1_SCL0_FRC9   */
     volatile uint16_t SC1_SCL0_MON0;                          /*  SC1_SCL0_MON0   */
     volatile uint16_t SC1_SCL0_INT;                           /*  SC1_SCL0_INT    */
-#define VDC5_SC1_SC1_SCL0_DS1_COUNT 7
+
+/* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */
     volatile uint32_t  SC1_SCL0_DS1;                           /*  SC1_SCL0_DS1    */
     volatile uint32_t  SC1_SCL0_DS2;                           /*  SC1_SCL0_DS2    */
     volatile uint32_t  SC1_SCL0_DS3;                           /*  SC1_SCL0_DS3    */
@@ -379,7 +1413,8 @@
     volatile uint32_t  SC1_SCL0_DS5;                           /*  SC1_SCL0_DS5    */
     volatile uint32_t  SC1_SCL0_DS6;                           /*  SC1_SCL0_DS6    */
     volatile uint32_t  SC1_SCL0_DS7;                           /*  SC1_SCL0_DS7    */
-#define VDC5_SC1_SC1_SCL0_US1_COUNT 8
+
+/* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */
     volatile uint32_t  SC1_SCL0_US1;                           /*  SC1_SCL0_US1    */
     volatile uint32_t  SC1_SCL0_US2;                           /*  SC1_SCL0_US2    */
     volatile uint32_t  SC1_SCL0_US3;                           /*  SC1_SCL0_US3    */
@@ -393,7 +1428,8 @@
     volatile uint8_t   dummy27[16];                            /*                  */
     volatile uint32_t  SC1_SCL1_UPDATE;                        /*  SC1_SCL1_UPDATE */
     volatile uint8_t   dummy28[4];                             /*                  */
-#define VDC5_SC1_SCL1_WR1_COUNT 4
+
+/* #define VDC5_SC1_SCL1_WR1_COUNT (4) */
     volatile uint32_t  SC1_SCL1_WR1;                           /*  SC1_SCL1_WR1    */
     volatile uint32_t  SC1_SCL1_WR2;                           /*  SC1_SCL1_WR2    */
     volatile uint32_t  SC1_SCL1_WR3;                           /*  SC1_SCL1_WR3    */
@@ -405,37 +1441,46 @@
     volatile uint32_t  SC1_SCL1_WR8;                           /*  SC1_SCL1_WR8    */
     volatile uint32_t  SC1_SCL1_WR9;                           /*  SC1_SCL1_WR9    */
     volatile uint32_t  SC1_SCL1_WR10;                          /*  SC1_SCL1_WR10   */
+
 /* end of struct st_vdc5_from_sc0_scl0_update */
     volatile uint32_t  SC1_SCL1_WR11;                          /*  SC1_SCL1_WR11   */
     volatile uint32_t  SC1_SCL1_MON1;                          /*  SC1_SCL1_MON1   */
+
 /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
-#define VDC5_SC1_SCL1_PBUF0_COUNT 4
+
+/* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */
     volatile uint32_t  SC1_SCL1_PBUF0;                         /*  SC1_SCL1_PBUF0  */
     volatile uint32_t  SC1_SCL1_PBUF1;                         /*  SC1_SCL1_PBUF1  */
     volatile uint32_t  SC1_SCL1_PBUF2;                         /*  SC1_SCL1_PBUF2  */
     volatile uint32_t  SC1_SCL1_PBUF3;                         /*  SC1_SCL1_PBUF3  */
     volatile uint32_t  SC1_SCL1_PBUF_FLD;                      /*  SC1_SCL1_PBUF_FLD */
     volatile uint32_t  SC1_SCL1_PBUF_CNT;                      /*  SC1_SCL1_PBUF_CNT */
+
 /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
     volatile uint8_t   dummy30[44];                            /*                  */
+
 /* start of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR1_UPDATE;                             /*  GR1_UPDATE      */
     volatile uint32_t  GR1_FLM_RD;                             /*  GR1_FLM_RD      */
-#define VDC5_GR1_FLM1_COUNT 6
+
+/* #define VDC5_GR1_FLM1_COUNT (6) */
     volatile uint32_t  GR1_FLM1;                               /*  GR1_FLM1        */
     volatile uint32_t  GR1_FLM2;                               /*  GR1_FLM2        */
     volatile uint32_t  GR1_FLM3;                               /*  GR1_FLM3        */
     volatile uint32_t  GR1_FLM4;                               /*  GR1_FLM4        */
     volatile uint32_t  GR1_FLM5;                               /*  GR1_FLM5        */
     volatile uint32_t  GR1_FLM6;                               /*  GR1_FLM6        */
-#define VDC5_GR1_AB1_COUNT 3
+
+/* #define VDC5_GR1_AB1_COUNT (3) */
     volatile uint32_t  GR1_AB1;                                /*  GR1_AB1         */
     volatile uint32_t  GR1_AB2;                                /*  GR1_AB2         */
     volatile uint32_t  GR1_AB3;                                /*  GR1_AB3         */
+
 /* end of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR1_AB4;                                /*  GR1_AB4         */
     volatile uint32_t  GR1_AB5;                                /*  GR1_AB5         */
     volatile uint32_t  GR1_AB6;                                /*  GR1_AB6         */
+
 /* start of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR1_AB7;                                /*  GR1_AB7         */
     volatile uint32_t  GR1_AB8;                                /*  GR1_AB8         */
@@ -443,25 +1488,30 @@
     volatile uint32_t  GR1_AB10;                               /*  GR1_AB10        */
     volatile uint32_t  GR1_AB11;                               /*  GR1_AB11        */
     volatile uint32_t  GR1_BASE;                               /*  GR1_BASE        */
+
 /* end of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR1_CLUT;                               /*  GR1_CLUT        */
     volatile uint32_t  GR1_MON;                                /*  GR1_MON         */
     volatile uint8_t   dummy31[40];                            /*                  */
+
 /* start of struct st_vdc5_from_adj0_update */
     volatile uint32_t  ADJ1_UPDATE;                            /*  ADJ1_UPDATE     */
     volatile uint32_t  ADJ1_BKSTR_SET;                         /*  ADJ1_BKSTR_SET  */
-#define VDC5_ADJ1_ENH_TIM1_COUNT 3
+
+/* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */
     volatile uint32_t  ADJ1_ENH_TIM1;                          /*  ADJ1_ENH_TIM1   */
     volatile uint32_t  ADJ1_ENH_TIM2;                          /*  ADJ1_ENH_TIM2   */
     volatile uint32_t  ADJ1_ENH_TIM3;                          /*  ADJ1_ENH_TIM3   */
-#define VDC5_ADJ1_ENH_SHP1_COUNT 6
+
+/* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */
     volatile uint32_t  ADJ1_ENH_SHP1;                          /*  ADJ1_ENH_SHP1   */
     volatile uint32_t  ADJ1_ENH_SHP2;                          /*  ADJ1_ENH_SHP2   */
     volatile uint32_t  ADJ1_ENH_SHP3;                          /*  ADJ1_ENH_SHP3   */
     volatile uint32_t  ADJ1_ENH_SHP4;                          /*  ADJ1_ENH_SHP4   */
     volatile uint32_t  ADJ1_ENH_SHP5;                          /*  ADJ1_ENH_SHP5   */
     volatile uint32_t  ADJ1_ENH_SHP6;                          /*  ADJ1_ENH_SHP6   */
-#define VDC5_ADJ1_ENH_LTI1_COUNT 2
+
+/* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */
     volatile uint32_t  ADJ1_ENH_LTI1;                          /*  ADJ1_ENH_LTI1   */
     volatile uint32_t  ADJ1_ENH_LTI2;                          /*  ADJ1_ENH_LTI2   */
     volatile uint32_t  ADJ1_MTX_MODE;                          /*  ADJ1_MTX_MODE   */
@@ -471,11 +1521,13 @@
     volatile uint32_t  ADJ1_MTX_CBB_ADJ1;                      /*  ADJ1_MTX_CBB_ADJ1 */
     volatile uint32_t  ADJ1_MTX_CRR_ADJ0;                      /*  ADJ1_MTX_CRR_ADJ0 */
     volatile uint32_t  ADJ1_MTX_CRR_ADJ1;                      /*  ADJ1_MTX_CRR_ADJ1 */
+
 /* end of struct st_vdc5_from_adj0_update */
     volatile uint8_t   dummy32[48];                            /*                  */
     volatile uint32_t  GR_VIN_UPDATE;                          /*  GR_VIN_UPDATE   */
     volatile uint8_t   dummy33[28];                            /*                  */
-#define VDC5_GR_VIN_AB1_COUNT 7
+
+/* #define VDC5_GR_VIN_AB1_COUNT (7) */
     volatile uint32_t  GR_VIN_AB1;                             /*  GR_VIN_AB1      */
     volatile uint32_t  GR_VIN_AB2;                             /*  GR_VIN_AB2      */
     volatile uint32_t  GR_VIN_AB3;                             /*  GR_VIN_AB3      */
@@ -489,7 +1541,8 @@
     volatile uint32_t  GR_VIN_MON;                             /*  GR_VIN_MON      */
     volatile uint8_t   dummy36[40];                            /*                  */
     volatile uint32_t  OIR_SCL0_UPDATE;                        /*  OIR_SCL0_UPDATE */
-#define VDC5_OIR_SCL0_FRC1_COUNT 7
+
+/* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */
     volatile uint32_t  OIR_SCL0_FRC1;                          /*  OIR_SCL0_FRC1   */
     volatile uint32_t  OIR_SCL0_FRC2;                          /*  OIR_SCL0_FRC2   */
     volatile uint32_t  OIR_SCL0_FRC3;                          /*  OIR_SCL0_FRC3   */
@@ -498,7 +1551,8 @@
     volatile uint32_t  OIR_SCL0_FRC6;                          /*  OIR_SCL0_FRC6   */
     volatile uint32_t  OIR_SCL0_FRC7;                          /*  OIR_SCL0_FRC7   */
     volatile uint8_t   dummy37[12];                            /*                  */
-#define VDC5_OIR_SCL0_DS1_COUNT 3
+
+/* #define VDC5_OIR_SCL0_DS1_COUNT (3) */
     volatile uint32_t  OIR_SCL0_DS1;                           /*  OIR_SCL0_DS1    */
     volatile uint32_t  OIR_SCL0_DS2;                           /*  OIR_SCL0_DS2    */
     volatile uint32_t  OIR_SCL0_DS3;                           /*  OIR_SCL0_DS3    */
@@ -514,7 +1568,8 @@
     volatile uint8_t   dummy41[16];                            /*                  */
     volatile uint32_t  OIR_SCL1_UPDATE;                        /*  OIR_SCL1_UPDATE */
     volatile uint8_t   dummy42[4];                             /*                  */
-#define VDC5_OIR_SCL1_WR1_COUNT 4
+
+/* #define VDC5_OIR_SCL1_WR1_COUNT (4) */
     volatile uint32_t  OIR_SCL1_WR1;                           /*  OIR_SCL1_WR1    */
     volatile uint32_t  OIR_SCL1_WR2;                           /*  OIR_SCL1_WR2    */
     volatile uint32_t  OIR_SCL1_WR3;                           /*  OIR_SCL1_WR3    */
@@ -526,14 +1581,16 @@
     volatile uint8_t   dummy44[88];                            /*                  */
     volatile uint32_t  GR_OIR_UPDATE;                          /*  GR_OIR_UPDATE   */
     volatile uint32_t  GR_OIR_FLM_RD;                          /*  GR_OIR_FLM_RD   */
-#define VDC5_GR_OIR_FLM1_COUNT 6
+
+/* #define VDC5_GR_OIR_FLM1_COUNT (6) */
     volatile uint32_t  GR_OIR_FLM1;                            /*  GR_OIR_FLM1     */
     volatile uint32_t  GR_OIR_FLM2;                            /*  GR_OIR_FLM2     */
     volatile uint32_t  GR_OIR_FLM3;                            /*  GR_OIR_FLM3     */
     volatile uint32_t  GR_OIR_FLM4;                            /*  GR_OIR_FLM4     */
     volatile uint32_t  GR_OIR_FLM5;                            /*  GR_OIR_FLM5     */
     volatile uint32_t  GR_OIR_FLM6;                            /*  GR_OIR_FLM6     */
-#define VDC5_GR_OIR_AB1_COUNT 3
+
+/* #define VDC5_GR_OIR_AB1_COUNT (3) */
     volatile uint32_t  GR_OIR_AB1;                             /*  GR_OIR_AB1      */
     volatile uint32_t  GR_OIR_AB2;                             /*  GR_OIR_AB2      */
     volatile uint32_t  GR_OIR_AB3;                             /*  GR_OIR_AB3      */
@@ -546,11 +1603,12 @@
     volatile uint32_t  GR_OIR_BASE;                            /*  GR_OIR_BASE     */
     volatile uint32_t  GR_OIR_CLUT;                            /*  GR_OIR_CLUT     */
     volatile uint32_t  GR_OIR_MON;                             /*  GR_OIR_MON      */
-};
+} r_io_vdc5_t;
 
 
-struct st_vdc5_from_gr0_update
+typedef struct st_vdc5_from_gr0_update
 {
+ 
     volatile uint32_t  GR0_UPDATE;                             /*  GR0_UPDATE      */
     volatile uint32_t  GR0_FLM_RD;                             /*  GR0_FLM_RD      */
     volatile uint32_t  GR0_FLM1;                               /*  GR0_FLM1        */
@@ -562,22 +1620,24 @@
     volatile uint32_t  GR0_AB1;                                /*  GR0_AB1         */
     volatile uint32_t  GR0_AB2;                                /*  GR0_AB2         */
     volatile uint32_t  GR0_AB3;                                /*  GR0_AB3         */
-};
+} r_io_vdc5_from_gr0_update_t;
 
 
-struct st_vdc5_from_gr0_ab7
+typedef struct st_vdc5_from_gr0_ab7
 {
+ 
     volatile uint32_t  GR0_AB7;                                /*  GR0_AB7         */
     volatile uint32_t  GR0_AB8;                                /*  GR0_AB8         */
     volatile uint32_t  GR0_AB9;                                /*  GR0_AB9         */
     volatile uint32_t  GR0_AB10;                               /*  GR0_AB10        */
     volatile uint32_t  GR0_AB11;                               /*  GR0_AB11        */
     volatile uint32_t  GR0_BASE;                               /*  GR0_BASE        */
-};
+} r_io_vdc5_from_gr0_ab7_t;
 
 
-struct st_vdc5_from_adj0_update
+typedef struct st_vdc5_from_adj0_update
 {
+ 
     volatile uint32_t  ADJ0_UPDATE;                            /*  ADJ0_UPDATE     */
     volatile uint32_t  ADJ0_BKSTR_SET;                         /*  ADJ0_BKSTR_SET  */
     volatile uint32_t  ADJ0_ENH_TIM1;                          /*  ADJ0_ENH_TIM1   */
@@ -598,11 +1658,12 @@
     volatile uint32_t  ADJ0_MTX_CBB_ADJ1;                      /*  ADJ0_MTX_CBB_ADJ1 */
     volatile uint32_t  ADJ0_MTX_CRR_ADJ0;                      /*  ADJ0_MTX_CRR_ADJ0 */
     volatile uint32_t  ADJ0_MTX_CRR_ADJ1;                      /*  ADJ0_MTX_CRR_ADJ1 */
-};
+} r_io_vdc5_from_adj0_update_t;
 
 
-struct st_vdc5_from_sc0_scl0_update
+typedef struct st_vdc5_from_sc0_scl0_update
 {
+ 
     volatile uint32_t  SC0_SCL0_UPDATE;                        /*  SC0_SCL0_UPDATE */
     volatile uint32_t  SC0_SCL0_FRC1;                          /*  SC0_SCL0_FRC1   */
     volatile uint32_t  SC0_SCL0_FRC2;                          /*  SC0_SCL0_FRC2   */
@@ -646,951 +1707,82 @@
     volatile uint32_t  SC0_SCL1_WR8;                           /*  SC0_SCL1_WR8    */
     volatile uint32_t  SC0_SCL1_WR9;                           /*  SC0_SCL1_WR9    */
     volatile uint32_t  SC0_SCL1_WR10;                          /*  SC0_SCL1_WR10   */
-};
+} r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */;
 
 
-struct st_vdc5_from_sc0_scl1_pbuf0
+typedef struct st_vdc5_from_sc0_scl1_pbuf0
 {
+ 
     volatile uint32_t  SC0_SCL1_PBUF0;                         /*  SC0_SCL1_PBUF0  */
     volatile uint32_t  SC0_SCL1_PBUF1;                         /*  SC0_SCL1_PBUF1  */
     volatile uint32_t  SC0_SCL1_PBUF2;                         /*  SC0_SCL1_PBUF2  */
     volatile uint32_t  SC0_SCL1_PBUF3;                         /*  SC0_SCL1_PBUF3  */
     volatile uint32_t  SC0_SCL1_PBUF_FLD;                      /*  SC0_SCL1_PBUF_FLD */
     volatile uint32_t  SC0_SCL1_PBUF_CNT;                      /*  SC0_SCL1_PBUF_CNT */
-};
-
-
-#define VDC50   (*(struct st_vdc5    *)0xFCFF7400uL) /* VDC50 */
-#define VDC51   (*(struct st_vdc5    *)0xFCFF9400uL) /* VDC51 */
-
-
-/* Start of channnel array defines of VDC5 */
-
-/* Channnel array defines of VDC5 */
-/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
-#define VDC5_COUNT  2
-#define VDC5_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &VDC50, &VDC51 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-
-
-/* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */
-/*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
-#define VDC5n_FROM_GR2_AB7_ARRAY_COUNT  2
-#define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
-    &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
-#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
-#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
-#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */
-/*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
-#define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT  2
-#define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
-    &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
-#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
-#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
-#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */
-/*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
-#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT  2
-#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
-    &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
-#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
-#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
-#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */
-/*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
-#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT  2
-#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
-    &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
-#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
-#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
-#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */
-/*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
-#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT  2
-#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
-    &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
-#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
-#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
-#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */
-/*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
-#define VDC5n_FROM_GR0_AB7_ARRAY_COUNT  2
-#define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
-    &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
-#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
-#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
-#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */
-/*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
-#define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT  2
-#define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
-    &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
-#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
-#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
-#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
-
-
-/* End of channnel array defines of VDC5 */
+} r_io_vdc5_from_sc0_scl1_pbuf0_t;
 
 
-#define VDC50INP_UPDATE VDC50.INP_UPDATE
-#define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT
-#define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT
-#define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ
-#define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ
-#define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE
-#define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0
-#define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1
-#define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE
-#define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0
-#define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1
-#define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0
-#define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1
-#define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0
-#define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1
-#define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG
-#define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE
-#define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1
-#define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2
-#define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3
-#define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4
-#define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5
-#define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6
-#define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7
-#define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9
-#define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0
-#define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT
-#define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1
-#define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2
-#define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3
-#define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4
-#define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5
-#define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6
-#define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7
-#define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1
-#define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2
-#define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3
-#define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4
-#define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5
-#define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6
-#define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7
-#define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8
-#define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1
-#define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE
-#define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1
-#define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2
-#define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3
-#define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4
-#define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5
-#define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6
-#define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7
-#define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8
-#define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9
-#define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10
-#define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11
-#define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1
-#define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0
-#define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1
-#define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2
-#define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3
-#define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD
-#define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT
-#define VDC50GR0_UPDATE VDC50.GR0_UPDATE
-#define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD
-#define VDC50GR0_FLM1 VDC50.GR0_FLM1
-#define VDC50GR0_FLM2 VDC50.GR0_FLM2
-#define VDC50GR0_FLM3 VDC50.GR0_FLM3
-#define VDC50GR0_FLM4 VDC50.GR0_FLM4
-#define VDC50GR0_FLM5 VDC50.GR0_FLM5
-#define VDC50GR0_FLM6 VDC50.GR0_FLM6
-#define VDC50GR0_AB1 VDC50.GR0_AB1
-#define VDC50GR0_AB2 VDC50.GR0_AB2
-#define VDC50GR0_AB3 VDC50.GR0_AB3
-#define VDC50GR0_AB7 VDC50.GR0_AB7
-#define VDC50GR0_AB8 VDC50.GR0_AB8
-#define VDC50GR0_AB9 VDC50.GR0_AB9
-#define VDC50GR0_AB10 VDC50.GR0_AB10
-#define VDC50GR0_AB11 VDC50.GR0_AB11
-#define VDC50GR0_BASE VDC50.GR0_BASE
-#define VDC50GR0_CLUT VDC50.GR0_CLUT
-#define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE
-#define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET
-#define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1
-#define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2
-#define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3
-#define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1
-#define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2
-#define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3
-#define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4
-#define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5
-#define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6
-#define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1
-#define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2
-#define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE
-#define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0
-#define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1
-#define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0
-#define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1
-#define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0
-#define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1
-#define VDC50GR2_UPDATE VDC50.GR2_UPDATE
-#define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD
-#define VDC50GR2_FLM1 VDC50.GR2_FLM1
-#define VDC50GR2_FLM2 VDC50.GR2_FLM2
-#define VDC50GR2_FLM3 VDC50.GR2_FLM3
-#define VDC50GR2_FLM4 VDC50.GR2_FLM4
-#define VDC50GR2_FLM5 VDC50.GR2_FLM5
-#define VDC50GR2_FLM6 VDC50.GR2_FLM6
-#define VDC50GR2_AB1 VDC50.GR2_AB1
-#define VDC50GR2_AB2 VDC50.GR2_AB2
-#define VDC50GR2_AB3 VDC50.GR2_AB3
-#define VDC50GR2_AB4 VDC50.GR2_AB4
-#define VDC50GR2_AB5 VDC50.GR2_AB5
-#define VDC50GR2_AB6 VDC50.GR2_AB6
-#define VDC50GR2_AB7 VDC50.GR2_AB7
-#define VDC50GR2_AB8 VDC50.GR2_AB8
-#define VDC50GR2_AB9 VDC50.GR2_AB9
-#define VDC50GR2_AB10 VDC50.GR2_AB10
-#define VDC50GR2_AB11 VDC50.GR2_AB11
-#define VDC50GR2_BASE VDC50.GR2_BASE
-#define VDC50GR2_CLUT VDC50.GR2_CLUT
-#define VDC50GR2_MON VDC50.GR2_MON
-#define VDC50GR3_UPDATE VDC50.GR3_UPDATE
-#define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD
-#define VDC50GR3_FLM1 VDC50.GR3_FLM1
-#define VDC50GR3_FLM2 VDC50.GR3_FLM2
-#define VDC50GR3_FLM3 VDC50.GR3_FLM3
-#define VDC50GR3_FLM4 VDC50.GR3_FLM4
-#define VDC50GR3_FLM5 VDC50.GR3_FLM5
-#define VDC50GR3_FLM6 VDC50.GR3_FLM6
-#define VDC50GR3_AB1 VDC50.GR3_AB1
-#define VDC50GR3_AB2 VDC50.GR3_AB2
-#define VDC50GR3_AB3 VDC50.GR3_AB3
-#define VDC50GR3_AB4 VDC50.GR3_AB4
-#define VDC50GR3_AB5 VDC50.GR3_AB5
-#define VDC50GR3_AB6 VDC50.GR3_AB6
-#define VDC50GR3_AB7 VDC50.GR3_AB7
-#define VDC50GR3_AB8 VDC50.GR3_AB8
-#define VDC50GR3_AB9 VDC50.GR3_AB9
-#define VDC50GR3_AB10 VDC50.GR3_AB10
-#define VDC50GR3_AB11 VDC50.GR3_AB11
-#define VDC50GR3_BASE VDC50.GR3_BASE
-#define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT
-#define VDC50GR3_MON VDC50.GR3_MON
-#define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE
-#define VDC50GAM_SW VDC50.GAM_SW
-#define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1
-#define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2
-#define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3
-#define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4
-#define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5
-#define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6
-#define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7
-#define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8
-#define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9
-#define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10
-#define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11
-#define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12
-#define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13
-#define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14
-#define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15
-#define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16
-#define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1
-#define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2
-#define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3
-#define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4
-#define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5
-#define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6
-#define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7
-#define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8
-#define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE
-#define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1
-#define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2
-#define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3
-#define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4
-#define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5
-#define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6
-#define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7
-#define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8
-#define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9
-#define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10
-#define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11
-#define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12
-#define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13
-#define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14
-#define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15
-#define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16
-#define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1
-#define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2
-#define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3
-#define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4
-#define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5
-#define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6
-#define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7
-#define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8
-#define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE
-#define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1
-#define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2
-#define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3
-#define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4
-#define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5
-#define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6
-#define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7
-#define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8
-#define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9
-#define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10
-#define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11
-#define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12
-#define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13
-#define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14
-#define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15
-#define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16
-#define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1
-#define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2
-#define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3
-#define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4
-#define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5
-#define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6
-#define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7
-#define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8
-#define VDC50TCON_UPDATE VDC50.TCON_UPDATE
-#define VDC50TCON_TIM VDC50.TCON_TIM
-#define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1
-#define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2
-#define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1
-#define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2
-#define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1
-#define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2
-#define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1
-#define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2
-#define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1
-#define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2
-#define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1
-#define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2
-#define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1
-#define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2
-#define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE
-#define VDC50OUT_UPDATE VDC50.OUT_UPDATE
-#define VDC50OUT_SET VDC50.OUT_SET
-#define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1
-#define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2
-#define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST
-#define VDC50OUT_PDTHA VDC50.OUT_PDTHA
-#define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE
-#define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1
-#define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2
-#define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3
-#define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4
-#define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5
-#define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6
-#define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK
-#define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT
-#define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE
-#define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1
-#define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2
-#define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3
-#define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4
-#define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5
-#define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6
-#define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7
-#define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9
-#define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0
-#define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT
-#define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1
-#define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2
-#define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3
-#define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4
-#define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5
-#define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6
-#define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7
-#define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1
-#define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2
-#define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3
-#define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4
-#define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5
-#define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6
-#define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7
-#define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8
-#define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1
-#define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE
-#define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1
-#define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2
-#define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3
-#define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4
-#define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5
-#define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6
-#define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7
-#define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8
-#define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9
-#define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10
-#define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11
-#define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1
-#define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0
-#define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1
-#define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2
-#define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3
-#define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD
-#define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT
-#define VDC50GR1_UPDATE VDC50.GR1_UPDATE
-#define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD
-#define VDC50GR1_FLM1 VDC50.GR1_FLM1
-#define VDC50GR1_FLM2 VDC50.GR1_FLM2
-#define VDC50GR1_FLM3 VDC50.GR1_FLM3
-#define VDC50GR1_FLM4 VDC50.GR1_FLM4
-#define VDC50GR1_FLM5 VDC50.GR1_FLM5
-#define VDC50GR1_FLM6 VDC50.GR1_FLM6
-#define VDC50GR1_AB1 VDC50.GR1_AB1
-#define VDC50GR1_AB2 VDC50.GR1_AB2
-#define VDC50GR1_AB3 VDC50.GR1_AB3
-#define VDC50GR1_AB4 VDC50.GR1_AB4
-#define VDC50GR1_AB5 VDC50.GR1_AB5
-#define VDC50GR1_AB6 VDC50.GR1_AB6
-#define VDC50GR1_AB7 VDC50.GR1_AB7
-#define VDC50GR1_AB8 VDC50.GR1_AB8
-#define VDC50GR1_AB9 VDC50.GR1_AB9
-#define VDC50GR1_AB10 VDC50.GR1_AB10
-#define VDC50GR1_AB11 VDC50.GR1_AB11
-#define VDC50GR1_BASE VDC50.GR1_BASE
-#define VDC50GR1_CLUT VDC50.GR1_CLUT
-#define VDC50GR1_MON VDC50.GR1_MON
-#define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE
-#define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET
-#define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1
-#define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2
-#define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3
-#define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1
-#define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2
-#define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3
-#define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4
-#define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5
-#define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6
-#define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1
-#define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2
-#define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE
-#define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0
-#define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1
-#define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0
-#define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1
-#define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0
-#define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1
-#define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE
-#define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1
-#define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2
-#define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3
-#define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4
-#define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5
-#define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6
-#define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7
-#define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE
-#define VDC50GR_VIN_MON VDC50.GR_VIN_MON
-#define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE
-#define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1
-#define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2
-#define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3
-#define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4
-#define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5
-#define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6
-#define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7
-#define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1
-#define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2
-#define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3
-#define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7
-#define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1
-#define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2
-#define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3
-#define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8
-#define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1
-#define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE
-#define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1
-#define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2
-#define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3
-#define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4
-#define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5
-#define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6
-#define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7
-#define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE
-#define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD
-#define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1
-#define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2
-#define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3
-#define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4
-#define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5
-#define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6
-#define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1
-#define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2
-#define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3
-#define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7
-#define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8
-#define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9
-#define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10
-#define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11
-#define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE
-#define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT
-#define VDC50GR_OIR_MON VDC50.GR_OIR_MON
-#define VDC51INP_UPDATE VDC51.INP_UPDATE
-#define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT
-#define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT
-#define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ
-#define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ
-#define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE
-#define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0
-#define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1
-#define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE
-#define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0
-#define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1
-#define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0
-#define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1
-#define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0
-#define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1
-#define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG
-#define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE
-#define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1
-#define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2
-#define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3
-#define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4
-#define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5
-#define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6
-#define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7
-#define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9
-#define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0
-#define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT
-#define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1
-#define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2
-#define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3
-#define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4
-#define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5
-#define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6
-#define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7
-#define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1
-#define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2
-#define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3
-#define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4
-#define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5
-#define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6
-#define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7
-#define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8
-#define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1
-#define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE
-#define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1
-#define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2
-#define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3
-#define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4
-#define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5
-#define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6
-#define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7
-#define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8
-#define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9
-#define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10
-#define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11
-#define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1
-#define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0
-#define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1
-#define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2
-#define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3
-#define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD
-#define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT
-#define VDC51GR0_UPDATE VDC51.GR0_UPDATE
-#define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD
-#define VDC51GR0_FLM1 VDC51.GR0_FLM1
-#define VDC51GR0_FLM2 VDC51.GR0_FLM2
-#define VDC51GR0_FLM3 VDC51.GR0_FLM3
-#define VDC51GR0_FLM4 VDC51.GR0_FLM4
-#define VDC51GR0_FLM5 VDC51.GR0_FLM5
-#define VDC51GR0_FLM6 VDC51.GR0_FLM6
-#define VDC51GR0_AB1 VDC51.GR0_AB1
-#define VDC51GR0_AB2 VDC51.GR0_AB2
-#define VDC51GR0_AB3 VDC51.GR0_AB3
-#define VDC51GR0_AB7 VDC51.GR0_AB7
-#define VDC51GR0_AB8 VDC51.GR0_AB8
-#define VDC51GR0_AB9 VDC51.GR0_AB9
-#define VDC51GR0_AB10 VDC51.GR0_AB10
-#define VDC51GR0_AB11 VDC51.GR0_AB11
-#define VDC51GR0_BASE VDC51.GR0_BASE
-#define VDC51GR0_CLUT VDC51.GR0_CLUT
-#define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE
-#define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET
-#define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1
-#define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2
-#define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3
-#define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1
-#define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2
-#define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3
-#define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4
-#define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5
-#define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6
-#define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1
-#define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2
-#define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE
-#define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0
-#define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1
-#define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0
-#define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1
-#define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0
-#define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1
-#define VDC51GR2_UPDATE VDC51.GR2_UPDATE
-#define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD
-#define VDC51GR2_FLM1 VDC51.GR2_FLM1
-#define VDC51GR2_FLM2 VDC51.GR2_FLM2
-#define VDC51GR2_FLM3 VDC51.GR2_FLM3
-#define VDC51GR2_FLM4 VDC51.GR2_FLM4
-#define VDC51GR2_FLM5 VDC51.GR2_FLM5
-#define VDC51GR2_FLM6 VDC51.GR2_FLM6
-#define VDC51GR2_AB1 VDC51.GR2_AB1
-#define VDC51GR2_AB2 VDC51.GR2_AB2
-#define VDC51GR2_AB3 VDC51.GR2_AB3
-#define VDC51GR2_AB4 VDC51.GR2_AB4
-#define VDC51GR2_AB5 VDC51.GR2_AB5
-#define VDC51GR2_AB6 VDC51.GR2_AB6
-#define VDC51GR2_AB7 VDC51.GR2_AB7
-#define VDC51GR2_AB8 VDC51.GR2_AB8
-#define VDC51GR2_AB9 VDC51.GR2_AB9
-#define VDC51GR2_AB10 VDC51.GR2_AB10
-#define VDC51GR2_AB11 VDC51.GR2_AB11
-#define VDC51GR2_BASE VDC51.GR2_BASE
-#define VDC51GR2_CLUT VDC51.GR2_CLUT
-#define VDC51GR2_MON VDC51.GR2_MON
-#define VDC51GR3_UPDATE VDC51.GR3_UPDATE
-#define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD
-#define VDC51GR3_FLM1 VDC51.GR3_FLM1
-#define VDC51GR3_FLM2 VDC51.GR3_FLM2
-#define VDC51GR3_FLM3 VDC51.GR3_FLM3
-#define VDC51GR3_FLM4 VDC51.GR3_FLM4
-#define VDC51GR3_FLM5 VDC51.GR3_FLM5
-#define VDC51GR3_FLM6 VDC51.GR3_FLM6
-#define VDC51GR3_AB1 VDC51.GR3_AB1
-#define VDC51GR3_AB2 VDC51.GR3_AB2
-#define VDC51GR3_AB3 VDC51.GR3_AB3
-#define VDC51GR3_AB4 VDC51.GR3_AB4
-#define VDC51GR3_AB5 VDC51.GR3_AB5
-#define VDC51GR3_AB6 VDC51.GR3_AB6
-#define VDC51GR3_AB7 VDC51.GR3_AB7
-#define VDC51GR3_AB8 VDC51.GR3_AB8
-#define VDC51GR3_AB9 VDC51.GR3_AB9
-#define VDC51GR3_AB10 VDC51.GR3_AB10
-#define VDC51GR3_AB11 VDC51.GR3_AB11
-#define VDC51GR3_BASE VDC51.GR3_BASE
-#define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT
-#define VDC51GR3_MON VDC51.GR3_MON
-#define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE
-#define VDC51GAM_SW VDC51.GAM_SW
-#define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1
-#define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2
-#define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3
-#define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4
-#define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5
-#define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6
-#define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7
-#define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8
-#define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9
-#define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10
-#define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11
-#define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12
-#define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13
-#define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14
-#define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15
-#define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16
-#define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1
-#define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2
-#define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3
-#define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4
-#define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5
-#define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6
-#define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7
-#define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8
-#define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE
-#define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1
-#define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2
-#define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3
-#define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4
-#define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5
-#define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6
-#define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7
-#define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8
-#define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9
-#define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10
-#define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11
-#define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12
-#define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13
-#define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14
-#define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15
-#define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16
-#define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1
-#define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2
-#define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3
-#define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4
-#define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5
-#define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6
-#define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7
-#define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8
-#define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE
-#define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1
-#define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2
-#define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3
-#define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4
-#define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5
-#define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6
-#define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7
-#define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8
-#define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9
-#define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10
-#define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11
-#define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12
-#define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13
-#define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14
-#define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15
-#define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16
-#define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1
-#define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2
-#define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3
-#define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4
-#define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5
-#define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6
-#define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7
-#define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8
-#define VDC51TCON_UPDATE VDC51.TCON_UPDATE
-#define VDC51TCON_TIM VDC51.TCON_TIM
-#define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1
-#define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2
-#define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1
-#define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2
-#define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1
-#define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2
-#define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1
-#define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2
-#define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1
-#define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2
-#define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1
-#define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2
-#define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1
-#define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2
-#define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE
-#define VDC51OUT_UPDATE VDC51.OUT_UPDATE
-#define VDC51OUT_SET VDC51.OUT_SET
-#define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1
-#define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2
-#define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST
-#define VDC51OUT_PDTHA VDC51.OUT_PDTHA
-#define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE
-#define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1
-#define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2
-#define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3
-#define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4
-#define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5
-#define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6
-#define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK
-#define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT
-#define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE
-#define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1
-#define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2
-#define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3
-#define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4
-#define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5
-#define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6
-#define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7
-#define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9
-#define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0
-#define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT
-#define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1
-#define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2
-#define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3
-#define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4
-#define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5
-#define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6
-#define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7
-#define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1
-#define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2
-#define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3
-#define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4
-#define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5
-#define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6
-#define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7
-#define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8
-#define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1
-#define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE
-#define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1
-#define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2
-#define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3
-#define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4
-#define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5
-#define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6
-#define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7
-#define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8
-#define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9
-#define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10
-#define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11
-#define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1
-#define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0
-#define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1
-#define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2
-#define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3
-#define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD
-#define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT
-#define VDC51GR1_UPDATE VDC51.GR1_UPDATE
-#define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD
-#define VDC51GR1_FLM1 VDC51.GR1_FLM1
-#define VDC51GR1_FLM2 VDC51.GR1_FLM2
-#define VDC51GR1_FLM3 VDC51.GR1_FLM3
-#define VDC51GR1_FLM4 VDC51.GR1_FLM4
-#define VDC51GR1_FLM5 VDC51.GR1_FLM5
-#define VDC51GR1_FLM6 VDC51.GR1_FLM6
-#define VDC51GR1_AB1 VDC51.GR1_AB1
-#define VDC51GR1_AB2 VDC51.GR1_AB2
-#define VDC51GR1_AB3 VDC51.GR1_AB3
-#define VDC51GR1_AB4 VDC51.GR1_AB4
-#define VDC51GR1_AB5 VDC51.GR1_AB5
-#define VDC51GR1_AB6 VDC51.GR1_AB6
-#define VDC51GR1_AB7 VDC51.GR1_AB7
-#define VDC51GR1_AB8 VDC51.GR1_AB8
-#define VDC51GR1_AB9 VDC51.GR1_AB9
-#define VDC51GR1_AB10 VDC51.GR1_AB10
-#define VDC51GR1_AB11 VDC51.GR1_AB11
-#define VDC51GR1_BASE VDC51.GR1_BASE
-#define VDC51GR1_CLUT VDC51.GR1_CLUT
-#define VDC51GR1_MON VDC51.GR1_MON
-#define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE
-#define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET
-#define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1
-#define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2
-#define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3
-#define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1
-#define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2
-#define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3
-#define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4
-#define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5
-#define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6
-#define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1
-#define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2
-#define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE
-#define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0
-#define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1
-#define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0
-#define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1
-#define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0
-#define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1
-#define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE
-#define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1
-#define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2
-#define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3
-#define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4
-#define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5
-#define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6
-#define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7
-#define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE
-#define VDC51GR_VIN_MON VDC51.GR_VIN_MON
-#define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE
-#define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1
-#define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2
-#define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3
-#define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4
-#define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5
-#define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6
-#define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7
-#define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1
-#define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2
-#define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3
-#define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7
-#define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1
-#define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2
-#define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3
-#define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8
-#define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1
-#define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE
-#define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1
-#define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2
-#define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3
-#define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4
-#define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5
-#define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6
-#define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7
-#define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE
-#define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD
-#define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1
-#define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2
-#define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3
-#define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4
-#define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5
-#define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6
-#define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1
-#define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2
-#define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3
-#define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7
-#define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8
-#define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9
-#define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10
-#define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11
-#define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE
-#define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT
-#define VDC51GR_OIR_MON VDC51.GR_OIR_MON
+/* Channel array defines of VDC5 (2)*/
+#ifdef  DECLARE_VDC5_CHANNELS
+volatile struct st_vdc5*  VDC5[ VDC5_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC5_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC5_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_ab7*  VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_update*  VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS
+volatile struct st_vdc5_from_sc0_scl1_pbuf0*  VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_sc0_scl0_update*  VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_adj0_update*  VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_ab7*  VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_update*  VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */
+/* End of channel array defines of VDC5 (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h	Wed Jan 17 15:23:54 2018 +0000
@@ -18,29 +18,40 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : wdt_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef WDT_IODEFINE_H
 #define WDT_IODEFINE_H
-
-struct st_wdt
-{                                                          /* WDT              */
-    volatile uint16_t WTCSR;                                  /*  WTCSR           */
-    volatile uint16_t WTCNT;                                  /*  WTCNT           */
-    volatile uint16_t WRCSR;                                  /*  WRCSR           */
-};
-
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
 #define WDT     (*(struct st_wdt     *)0xFCFE0000uL) /* WDT */
 
 
-#define WDTWTCSR WDT.WTCSR
-#define WDTWTCNT WDT.WTCNT
-#define WDTWRCSR WDT.WRCSR
+#define WDTWTCSR (WDT.WTCSR)
+#define WDTWTCNT (WDT.WTCNT)
+#define WDTWRCSR (WDT.WRCSR)
+
+
+typedef struct st_wdt
+{
+                                                           /* WDT              */
+    volatile uint16_t WTCSR;                                  /*  WTCSR           */
+    volatile uint16_t WTCNT;                                  /*  WTCNT           */
+    volatile uint16_t WRCSR;                                  /*  WRCSR           */
+} r_io_wdt_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mmu_RZ_A1H.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,281 @@
+/**************************************************************************//**
+ * @file     mmu_RZ_A1H.c
+ * @brief    MMU Configuration for RZ_A1H Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf
+
+                                                     Memory Type
+0xffffffff |--------------------------|             ------------
+           |        Peripherals       |                Device
+0xfcf00000 |--------------------------|             ------------
+           |        Page Fault        |                Fault
+0xe8300000 |--------------------------|             ------------
+           |        Peripherals       |                Device
+0xe8000000 |--------------------------|             ------------
+           |        Page Fault        |                Fault
+0x60A00000 |--------------------------|             ------------
+           | On Chip RAM (10M) Mirror |                Fault
+0x60000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                Fault
+0x5c000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                Fault
+0x58000000 |--------------------------|             ------------
+           |        CS5 Mirror        |                Fault
+0x54000000 |--------------------------|             ------------
+           |        CS4 Mirror        |                Fault
+0x50000000 |--------------------------|             ------------
+           |        CS3 Mirror        |                Fault
+0x4c000000 |--------------------------|             ------------
+           |        CS2 Mirror        |                Fault
+0x48000000 |--------------------------|             ------------
+           |        CS1 Mirror        |                Fault
+0x44000000 |--------------------------|             ------------
+           |        CS0 Mirror        |                Fault
+0x40000000 |--------------------------|             ------------
+           |          BSC             |                 RW
+0x3ff00000 |--------------------------|             ------------
+           |      SPI_MIO_BASE        |                 RW
+0x3fe00000 |--------------------------|             ------------
+           |        Page Fault        |                Fault
+0x20A00000 |--------------------------|             ------------
+           |    On Chip RAM (10M)     |                 RW
+0x20000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                 RO
+0x1c000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                 RO
+0x18000000 |--------------------------|             ------------
+           |  CS5 User Area 64MB      |                 RW
+0x14000000 |--------------------------|             ------------
+           |  CS4 User Area 64MB      |                 RW
+0x10000000 |--------------------------|             ------------
+           |      CS3 SDRAM 64MB      |                 RW
+0x0c000000 |--------------------------|             ------------
+           |      CS2 SDRAM 64MB      |                 RW
+0x08000000 |--------------------------|             ------------
+           |  CS1 NOR Flash 64MB      |                 RO
+0x04000000 |--------------------------|             ------------
+           |  CS0 NOR Flash 64MB      |                 RO
+0x00000000 |--------------------------|             ------------
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+//There are no restrictions by privilege level (PL0 can access all memory)
+
+
+#include "RZ_A1H.h"
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RO_DATA$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$RW_IRAM1$$Base;
+#if !defined ( __ICCARM__ )
+extern uint32_t Image$$TTB$$ZI$$Base;
+#endif 
+
+#if defined( __CC_ARM )
+#elif defined( __ICCARM__ )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Base;
+extern uint32_t Image$$ZI_DATA_NC$$Base;
+#endif
+
+extern uint32_t Image$$VECTORS$$Limit;
+extern uint32_t Image$$RO_DATA$$Limit;
+extern uint32_t Image$$RW_DATA$$Limit;
+extern uint32_t Image$$RW_IRAM1$$Limit;
+#if defined( __CC_ARM )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Limit;
+extern uint32_t Image$$ZI_DATA_NC$$Limit;
+#endif
+
+#if defined( __ICCARM__ )
+#define VECTORS_SIZE    (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE    (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE    (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
+#define RW_IRAM1_SIZE   (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1)
+#else
+#define VECTORS_SIZE    (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE    (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE    (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
+#define RW_IRAM1_SIZE   (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
+#endif
+
+#if defined( __CC_ARM )
+#else
+#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
+#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
+#endif
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_NC;  //non-shareable, non-executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+#if defined ( __ICCARM__ )
+__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
+uint32_t Image$$VECTORS$$Base;
+uint32_t Image$$RO_DATA$$Base;
+uint32_t Image$$RW_DATA$$Base;
+uint32_t Image$$RW_IRAM1$$Base;
+
+uint32_t Image$$VECTORS$$Limit;
+uint32_t Image$$RO_DATA$$Limit;
+uint32_t Image$$RW_DATA$$Limit;
+uint32_t Image$$RW_IRAM1$$Limit;
+#endif
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+#if defined ( __ICCARM__ )
+#pragma section=".intvec"
+#pragma section=".rodata"
+#pragma section=".rwdata"
+#pragma section=".bss"
+
+    Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
+    Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
+    Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
+    Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
+    Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); 
+    Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
+    Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss");  
+    Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
+#endif
+    /*
+     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    section_normal_nc(Sect_Normal_NC, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Create 4GB of faulting entries
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+    // R7S72100 memory map.
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0    , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1    , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0       , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1       , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0        , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1        , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0           , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1           , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE  , 10, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE      ,  1, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE          ,  1, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0      ,  3, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1      , 49, Sect_Device_RW);
+
+#if defined( __ICCARM__ )
+    //Define Image
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
+#else
+    //Define Image
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
+#endif
+
+#if defined( __CC_ARM )
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE         ,              10, Sect_Normal_NC);
+#elif defined ( __ICCARM__ ) 
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE         ,              10, Sect_Normal_NC);
+
+#else
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
+#endif
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x0 (Inner WB WA)
+    ; 5     - NOS     0x0 (Non-shared)
+    ; 4:3   - RGN     0x1 (Outer WB WA)
+    ; 2     - IMP     0x0 (Implementation Defined)
+    ; 1     - S       0x0 (Non-shared)
+    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
+    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+    __ISB();
+}

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mmu_Renesas_RZ_A1.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,243 +0,0 @@
-/**************************************************************************//**
- * @file     mmu_Renesas_RZ_A1.c
- * @brief    MMU Startup File for
- *           mmu_Renesas_RZ_A1 Device Series
- * @version  V1.01
- * @date     2 Aug 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#define Renesas_RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
-#define Renesas_RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
-#define Renesas_RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
-#define Renesas_RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
-// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
-// Write-Through support *not* available
-// Write-Back support available.
-// Read allocation support available.
-// Write allocation support available.
-
-//Note: You should use the Shareable attribute carefully.
-//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.
-//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
-//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
-
-//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
-//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
-//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
-
-
-//Following MMU configuration is expected
-//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
-//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
-//Domain 0 is always the Client domain
-//Descriptors place all memory in domain 0
-//There are no restrictions by privilege level (PL0 can access all memory)
-
-#include <stdint.h>
-#include "MBRZA1H.h"
-
-//Import symbols from linker
-extern uint32_t Image$$VECTORS$$Base;
-extern uint32_t Image$$RO_DATA$$Base;
-extern uint32_t Image$$RW_DATA$$Base;
-extern uint32_t Image$$ZI_DATA$$Base;
-#if !defined ( __ICCARM__ )
-extern uint32_t Image$$TTB$$ZI$$Base;
-#endif 
-
-#if defined( __CC_ARM )
-#elif defined( __ICCARM__ )
-#else
-extern uint32_t Image$$RW_DATA_NC$$Base;
-extern uint32_t Image$$ZI_DATA_NC$$Base;
-#endif
-
-extern uint32_t Image$$VECTORS$$Limit;
-extern uint32_t Image$$RO_DATA$$Limit;
-extern uint32_t Image$$RW_DATA$$Limit;
-extern uint32_t Image$$ZI_DATA$$Limit;
-#if defined( __CC_ARM )
-#else
-extern uint32_t Image$$RW_DATA_NC$$Limit;
-extern uint32_t Image$$ZI_DATA_NC$$Limit;
-#endif
-
-#if defined( __ICCARM__ )
-#define VECTORS_SIZE    (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
-#define RO_DATA_SIZE    (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
-#define RW_DATA_SIZE    (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
-#define ZI_DATA_SIZE    (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1)
-#else
-#define VECTORS_SIZE    (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
-#define RO_DATA_SIZE    (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
-#define RW_DATA_SIZE    (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
-#define ZI_DATA_SIZE    (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
-#endif
-
-#if defined( __CC_ARM )
-#else
-#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
-#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
-#endif
-
-static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
-static uint32_t Sect_Normal_NC;  //non-shareable, non-executable, rw, domain 0, base addr 0
-static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
-static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
-static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
-static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
-static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
-
-/* Define global descriptors */
-static uint32_t Page_L1_4k  = 0x0;  //generic
-static uint32_t Page_L1_64k = 0x0;  //generic
-static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
-static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
-
-#if defined ( __ICCARM__ )
-__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
-uint32_t Image$$VECTORS$$Base;
-uint32_t Image$$RO_DATA$$Base;
-uint32_t Image$$RW_DATA$$Base;
-uint32_t Image$$ZI_DATA$$Base;
-
-uint32_t Image$$VECTORS$$Limit;
-uint32_t Image$$RO_DATA$$Limit;
-uint32_t Image$$RW_DATA$$Limit;
-uint32_t Image$$ZI_DATA$$Limit;
-#endif
-
-void create_translation_table(void)
-{
-    mmu_region_attributes_Type region;
-#if defined ( __ICCARM__ )
-#pragma section=".intvec"
-#pragma section=".rodata"
-#pragma section=".rwdata"
-#pragma section=".bss"
-
-    Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
-    Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
-    Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
-    Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
-    Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); 
-    Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
-    Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss");  
-    Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
-#endif
-    /*
-     * Generate descriptors. Refer to MBRZA1H.h to get information about attributes
-     *
-     */
-    //Create descriptors for Vectors, RO, RW, ZI sections
-    section_normal(Sect_Normal, region);
-    section_normal_cod(Sect_Normal_Cod, region);
-    section_normal_ro(Sect_Normal_RO, region);
-    section_normal_rw(Sect_Normal_RW, region);
-    //Create descriptors for peripherals
-    section_device_ro(Sect_Device_RO, region);
-    section_device_rw(Sect_Device_RW, region);
-    section_normal_nc(Sect_Normal_NC, region);
-    //Create descriptors for 64k pages
-    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
-    //Create descriptors for 4k pages
-    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
-
-    /*
-     *  Define MMU flat-map regions and attributes
-     *
-     */
-
-    //Create 4GB of faulting entries
-    __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
-
-    // R7S72100 memory map.
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0    , 64, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1    , 64, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0       , 64, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1       , 64, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0        , 64, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1        , 64, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0           , 64, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1           , 64, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE  , 10, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE      ,  1, Sect_Device_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE          ,  1, Sect_Device_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0      ,  3, Sect_Device_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1      , 49, Sect_Device_RW);
-
-#if defined( __ICCARM__ )
-    //Define Image
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_Cod);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
-#else
-    //Define Image
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_Cod);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
-#endif
-
-#if defined( __CC_ARM )
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
-#elif defined ( __ICCARM__ ) 
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
-
-#else
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
-#endif
-
-    /* Set location of level 1 page table
-    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
-    ; 13:7  - 0x0
-    ; 6     - IRGN[0] 0x0 (Inner WB WA)
-    ; 5     - NOS     0x0 (Non-shared)
-    ; 4:3   - RGN     0x1 (Outer WB WA)
-    ; 2     - IMP     0x0 (Implementation Defined)
-    ; 1     - S       0x0 (Non-shared)
-    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
-    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
-
-    /* Set up domain access control register
-    ; We set domain 0 to Client and all other domains to No Access.
-    ; All translation table entries specify domain 0 */
-    __set_DACR(1);
-}
-
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.c	Wed Jan 17 15:23:54 2018 +0000
@@ -33,7 +33,6 @@
 #include "MBRZA1H.h"
 #include "wdt_iodefine.h"
 #include "nvic_wrapper.h"
-#include "gic.h"
 
 /******************************************************************************
 Typedef definitions
@@ -71,7 +70,7 @@
 
 uint32_t NVIC_GetPriorityGrouping(void)
 {
-    return GIC_GetBinaryPoint(0);
+    return GIC_GetBinaryPoint();
 }
 
 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/os_tick_ostm.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,192 @@
+/**************************************************************************//**
+ * @file     os_tick_ostm.c
+ * @brief    CMSIS OS Tick implementation for OS Timer
+ * @version  V1.0.1
+ * @date     19. September 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifdef MBED_CONF_RTOS_PRESENT
+
+#include "os_tick.h"
+#include "irq_ctrl.h"
+
+#include <MBRZA1H.h>
+
+#include <cmsis.h>
+
+
+// Define OS TImer interrupt priority
+#ifndef OSTM_IRQ_PRIORITY
+#define OSTM_IRQ_PRIORITY           0xFFU
+#endif
+
+// Define OS Timer channel and interrupt number
+#define OSTM                        (OSTM0)
+#define OSTM_IRQn                   ((IRQn_ID_t)OSTMI0TINT_IRQn)
+
+
+static uint32_t OSTM_Clock;         // Timer tick frequency
+static uint8_t  OSTM_PendIRQ;       // Timer interrupt pending flag
+
+
+// Setup OS Tick.
+int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {
+  uint32_t clock;
+  uint32_t prio;
+  uint32_t bits;
+
+  if (freq == 0U) {
+    return (-1);
+  }
+  
+  OSTM_PendIRQ = 0U;
+
+  // Get CPG.FRQCR[IFC] bits
+  clock = (CPG.FRQCR >> 8) & 0x03;
+
+  // Determine Divider 2 output clock by using SystemCoreClock
+  if (clock == 0x03U) {
+    clock = (SystemCoreClock * 3U);
+  }
+  else if (clock == 0x01U) {
+    clock = (SystemCoreClock * 3U)/2U;
+  }
+  else {
+    clock = SystemCoreClock;
+  }
+
+  // Determine tick frequency
+  clock = clock / freq;
+
+  // Save frequency for later
+  OSTM_Clock = clock;
+
+  // Enable OSTM clock
+  CPG.STBCR5 &= ~(CPG_STBCR5_BIT_MSTP51);
+
+  // Stop the OSTM counter
+  OSTM.OSTMnTT  = 0x01U;
+
+  // Set interval timer mode and disable interrupts when counting starts
+  OSTM.OSTMnCTL = 0x00U;
+
+  // Set compare value
+  OSTM.OSTMnCMP = clock - 1U;
+
+  // Disable corresponding IRQ
+  IRQ_Disable     (OSTM_IRQn);
+  IRQ_ClearPending(OSTM_IRQn);
+
+  // Determine number of implemented priority bits
+  IRQ_SetPriority (OSTM_IRQn, 0xFFU);
+
+  prio = IRQ_GetPriority (OSTM_IRQn);
+
+  // At least bits [7:4] must be implemented
+  if ((prio & 0xF0U) == 0U) {
+    return (-1);
+  }
+
+  for (bits = 0; bits < 4; bits++) {
+    if ((prio & 0x01) != 0) {
+      break;
+    }
+    prio >>= 1;
+  }
+  
+  // Adjust configured priority to the number of implemented priority bits
+  prio = (OSTM_IRQ_PRIORITY << bits) & 0xFFUL;
+
+  // Set OSTM interrupt priority
+  IRQ_SetPriority(OSTM_IRQn, prio-1U);
+
+  // Set edge-triggered, non-secure, single CPU targeted IRQ
+  IRQ_SetMode (OSTM_IRQn, IRQ_MODE_TRIG_EDGE);
+
+  // Register tick interrupt handler function
+  IRQ_SetHandler(OSTM_IRQn, (IRQHandler_t)handler);
+
+  // Enable corresponding IRQ
+  IRQ_Enable (OSTM_IRQn);
+
+  return (0);
+}
+
+/// Enable OS Tick.
+int32_t  OS_Tick_Enable (void) {
+
+  if (OSTM_PendIRQ != 0U) {
+    OSTM_PendIRQ = 0U;
+    IRQ_SetPending (OSTM_IRQn);
+  }
+
+  // Start the OSTM counter
+  OSTM.OSTMnTS = 0x01U;
+
+  return (0);
+}
+
+/// Disable OS Tick.
+int32_t  OS_Tick_Disable (void) {
+
+  // Stop the OSTM counter
+  OSTM.OSTMnTT = 0x01U;
+
+  if (IRQ_GetPending(OSTM_IRQn) != 0) {
+    IRQ_ClearPending (OSTM_IRQn);
+    OSTM_PendIRQ = 1U;
+  }
+
+  return (0);
+}
+
+// Acknowledge OS Tick IRQ.
+int32_t OS_Tick_AcknowledgeIRQ (void) {
+  return (IRQ_ClearPending (OSTM_IRQn));
+}
+
+// Get OS Tick IRQ number.
+int32_t  OS_Tick_GetIRQn (void) {
+  return (OSTM_IRQn);
+}
+
+// Get OS Tick clock.
+uint32_t OS_Tick_GetClock (void) {
+  return (OSTM_Clock);
+}
+
+// Get OS Tick interval.
+uint32_t OS_Tick_GetInterval (void) {
+  return (OSTM.OSTMnCMP + 1U);
+}
+
+// Get OS Tick count value.
+uint32_t OS_Tick_GetCount (void) {
+  uint32_t cmp = OSTM.OSTMnCMP;
+  return  (cmp - OSTM.OSTMnCNT);
+}
+
+// Get OS Tick overflow status.
+uint32_t OS_Tick_GetOverflow (void) {
+  return (IRQ_GetPending(OSTM_IRQn));
+}
+
+#endif
+

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/pl310.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,128 +0,0 @@
-/**************************************************************************//**
- * @file     pl310.c
- * @brief    Implementation of PL310 PrimeCell Level 2 Cache Controller functions
- * @version
- * @date     3 December 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-#include "MBRZA1H.h"
-
-//Cache Sync operation
-void PL310_Sync(void)
-{
-    PL310->CACHE_SYNC = 0x0;
-}
-
-//return Cache controller cache ID
-int PL310_GetID (void)
-{
-    return PL310->CACHE_ID;
-}
-
-//return Cache controller cache Type
-int PL310_GetType (void)
-{
-    return PL310->CACHE_TYPE;
-}
-
-//Invalidate all cache by way
-void PL310_InvAllByWay (void)
-{
-    unsigned int assoc;
-
-    if (PL310->AUX_CNT & (1<<16))
-        assoc = 16;
-    else
-        assoc =  8;
-
-    PL310->INV_WAY = (1 << assoc) - 1;
-    while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
-
-    PL310_Sync();
-}
-
-//Clean and Invalidate all cache by way
-void PL310_CleanInvAllByWay (void)
-{
-    unsigned int assoc;
-
-    if (PL310->AUX_CNT & (1<<16))
-        assoc = 16;
-    else
-        assoc =  8;
-
-    PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
-    while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
-
-    PL310_Sync();
-}
-
-//Enable Cache
-void PL310_Enable(void)
-{
-    PL310->CONTROL = 0;
-    PL310->INTERRUPT_CLEAR = 0x000001FFuL;
-    PL310->DEBUG_CONTROL = 0;
-    PL310->DATA_LOCK_0_WAY = 0;
-    PL310->CACHE_SYNC = 0;
-
-    PL310->CONTROL = 0x01;
-    PL310_Sync();
-}
-//Disable Cache
-void PL310_Disable(void)
-{
-    PL310->CONTROL = 0x00;
-    PL310_Sync();
-}
-
-//Invalidate cache by physical address
-void PL310_InvPa (void *pa)
-{
-    PL310->INV_LINE_PA = (unsigned int)pa;
-    PL310_Sync();
-}
-
-//Clean cache by physical address
-void PL310_CleanPa (void *pa)
-{
-    PL310->CLEAN_LINE_PA = (unsigned int)pa;
-    PL310_Sync();
-}
-
-//Clean and invalidate cache by physical address
-void PL310_CleanInvPa (void *pa)
-{
-    PL310->CLEAN_INV_LINE_PA = (unsigned int)pa;
-    PL310_Sync();
-}
-
-

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/pl310.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,114 +0,0 @@
-/**************************************************************************//**
- * @file     pl310.h
- * @brief    Implementation of pl310 functions
- * @version
- * @date     11 June 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#ifndef __PL310
-#define __PL310
-
-typedef struct
-{
-  __I  uint32_t CACHE_ID;                   /*!< Offset: 0x0000   Cache ID Register               */
-  __I  uint32_t CACHE_TYPE;                 /*!< Offset: 0x0004   Cache Type Register             */
-       uint32_t RESERVED0[0x3e];
-  __IO uint32_t CONTROL;                    /*!< Offset: 0x0100   Control Register                */
-  __IO uint32_t AUX_CNT;                    /*!< Offset: 0x0104   Auxiliary Control               */
-       uint32_t RESERVED1[0x3e];
-  __IO uint32_t EVENT_CONTROL;              /*!< Offset: 0x0200   Event Counter Control           */
-  __IO uint32_t EVENT_COUNTER1_CONF;        /*!< Offset: 0x0204   Event Counter 1 Configuration   */
-  __IO uint32_t EVENT_COUNTER0_CONF;        /*!< Offset: 0x0208   Event Counter 1 Configuration   */
-       uint32_t RESERVED2[0x2];
-  __IO uint32_t INTERRUPT_MASK;             /*!< Offset: 0x0214   Interrupt Mask                  */
-  __I  uint32_t MASKED_INT_STATUS;          /*!< Offset: 0x0218   Masked Interrupt Status         */
-  __I  uint32_t RAW_INT_STATUS;             /*!< Offset: 0x021c   Raw Interrupt Status            */
-  __O  uint32_t INTERRUPT_CLEAR;            /*!< Offset: 0x0220   Interrupt Clear                 */
-       uint32_t RESERVED3[0x143];
-  __IO uint32_t CACHE_SYNC;                 /*!< Offset: 0x0730   Cache Sync                      */
-       uint32_t RESERVED4[0xf];
-  __IO uint32_t INV_LINE_PA;                /*!< Offset: 0x0770   Invalidate Line By PA           */
-       uint32_t RESERVED6[2];
-  __IO uint32_t INV_WAY;                    /*!< Offset: 0x077c   Invalidate by Way               */
-       uint32_t RESERVED5[0xc];
-  __IO uint32_t CLEAN_LINE_PA;              /*!< Offset: 0x07b0   Clean Line by PA                */
-       uint32_t RESERVED7[1];
-  __IO uint32_t CLEAN_LINE_INDEX_WAY;       /*!< Offset: 0x07b8   Clean Line by Index/Way         */
-  __IO uint32_t CLEAN_WAY;                  /*!< Offset: 0x07bc   Clean by Way                    */
-       uint32_t RESERVED8[0xc];
-  __IO uint32_t CLEAN_INV_LINE_PA;          /*!< Offset: 0x07f0   Clean and Invalidate Line by PA  */
-       uint32_t RESERVED9[1];
-  __IO uint32_t CLEAN_INV_LINE_INDEX_WAY;   /*!< Offset: 0x07f8   Clean and Invalidate Line by Index/Way  */
-  __IO uint32_t CLEAN_INV_WAY;              /*!< Offset: 0x07fc   Clean and Invalidate by Way     */
-       uint32_t RESERVED10[0x40];
-  __IO uint32_t DATA_LOCK_0_WAY;            /*!< Offset: 0x0900   Data Lockdown 0 by Way          */
-  __IO uint32_t INST_LOCK_0_WAY;            /*!< Offset: 0x0904   Instruction Lockdown 0 by Way   */
-  __IO uint32_t DATA_LOCK_1_WAY;            /*!< Offset: 0x0908   Data Lockdown 1 by Way          */
-  __IO uint32_t INST_LOCK_1_WAY;            /*!< Offset: 0x090c   Instruction Lockdown 1 by Way   */
-  __IO uint32_t DATA_LOCK_2_WAY;            /*!< Offset: 0x0910   Data Lockdown 2 by Way          */
-  __IO uint32_t INST_LOCK_2_WAY;            /*!< Offset: 0x0914   Instruction Lockdown 2 by Way   */
-  __IO uint32_t DATA_LOCK_3_WAY;            /*!< Offset: 0x0918   Data Lockdown 3 by Way          */
-  __IO uint32_t INST_LOCK_3_WAY;            /*!< Offset: 0x091c   Instruction Lockdown 3 by Way   */
-  __IO uint32_t DATA_LOCK_4_WAY;            /*!< Offset: 0x0920   Data Lockdown 4 by Way          */
-  __IO uint32_t INST_LOCK_4_WAY;            /*!< Offset: 0x0924   Instruction Lockdown 4 by Way   */
-  __IO uint32_t DATA_LOCK_5_WAY;            /*!< Offset: 0x0928   Data Lockdown 5 by Way          */
-  __IO uint32_t INST_LOCK_5_WAY;            /*!< Offset: 0x092c   Instruction Lockdown 5 by Way   */
-  __IO uint32_t DATA_LOCK_6_WAY;            /*!< Offset: 0x0930   Data Lockdown 5 by Way          */
-  __IO uint32_t INST_LOCK_6_WAY;            /*!< Offset: 0x0934   Instruction Lockdown 5 by Way   */
-  __IO uint32_t DATA_LOCK_7_WAY;            /*!< Offset: 0x0938   Data Lockdown 6 by Way          */
-  __IO uint32_t INST_LOCK_7_WAY;            /*!< Offset: 0x093c   Instruction Lockdown 6 by Way   */
-       uint32_t RESERVED11[0x4];
-  __IO uint32_t LOCK_LINE_EN;               /*!< Offset: 0x0950   Lockdown by Line Enable         */
-  __IO uint32_t UNLOCK_ALL_BY_WAY;          /*!< Offset: 0x0954   Unlock All Lines by Way         */
-       uint32_t RESERVED12[0xaa];
-  __IO uint32_t ADDRESS_FILTER_START;       /*!< Offset: 0x0c00   Address Filtering Start         */
-  __IO uint32_t ADDRESS_FILTER_END;         /*!< Offset: 0x0c04   Address Filtering End           */
-       uint32_t RESERVED13[0xce];
-  __IO uint32_t DEBUG_CONTROL;              /*!< Offset: 0x0f40   Debug Control Register          */
-
-} PL310_TypeDef;
-
-#define PL310           ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */
-
-extern int PL310_GetID (void);
-extern int PL310_GetType (void);
-extern void PL310_InvAllByWay (void);
-extern void PL310_CleanInvAllByWay(void);
-extern void PL310_Enable(void);
-extern void PL310_Disable(void);
-extern void PL310_InvPa (void *);
-extern void PL310_CleanPa (void *);
-extern void PL310_CleanInvPa (void *);
-
-#endif
-
-

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,521 +0,0 @@
-/**************************************************************************//**
- * @file     system_MBRZA1H.c
- * @brief    CMSIS Device System Source File for
- *           ARM Cortex-A9 Device Series
- * @version  V1.00
- * @date     09 January 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#include <stdint.h>
-#include "MBRZA1H.h"
-#include "RZ_A1_Init.h"
-
-
-#if defined(__ARMCC_VERSION)
-extern void $Super$$main(void);
-__asm void FPUEnable(void);
-#else 
-void FPUEnable(void); 
-
-#endif
-
-#define FRQCR_IFC_MSK          (0x0030)
-#define FRQCR_IFC_SHFT         (8)
-#define FRQCR_IFC_1P1          (0) /* x1/1 */
-#define FRQCR_IFC_2P3          (1) /* x2/3 */
-#define FRQCR_IFC_1P3          (3) /* x1/3 */
-
-uint32_t IRQNestLevel;
-unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
-uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the cache.
- *
- * @param  none
- * @return none
- *
- * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
- */
-#if defined(__ARMCC_VERSION)
-#pragma push
-#pragma arm
-
-void InitMemorySubsystem(void) {
-
-    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
-     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
-     * You are not required to invalidate the main TLB, even though it is recommended for safety
-     * reasons. This ensures compatibility with future revisions of the processor. */
-
-    unsigned int l2_id;
-
-    /* Invalidate undefined data */
-    __ca9u_inv_tlb_all();
-    __v7_inv_icache_all();
-    __v7_inv_dcache_all();
-    __v7_inv_btac();
-
-    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
-     * invalidate in order to flush the valid data to the next level cache.
-     */
-    __enable_mmu();
-
-    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
-    __enable_caches();
-    __enable_btac();
-
-    /* If present, you may also need to Invalidate and Enable L2 cache here */
-    l2_id = PL310_GetID();
-    if (l2_id)
-    {
-       PL310_InvAllByWay();
-       PL310_Enable();
-    }
-}
-#pragma pop
-
-#elif defined(__GNUC__) 
-
-void InitMemorySubsystem(void) { 
- 
-    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before 
-     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. 
-     * You are not required to invalidate the main TLB, even though it is recommended for safety 
-     * reasons. This ensures compatibility with future revisions of the processor. */ 
- 
-    unsigned int l2_id; 
- 
-    /* Invalidate undefined data */ 
-    __ca9u_inv_tlb_all(); 
-    __v7_inv_icache_all(); 
-    __v7_inv_dcache_all(); 
-    __v7_inv_btac(); 
- 
-    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and 
-     * invalidate in order to flush the valid data to the next level cache. 
-     */ 
-    __enable_mmu(); 
- 
-    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ 
-    __enable_caches(); 
-    __enable_btac(); 
- 
-    /* If present, you may also need to Invalidate and Enable L2 cache here */ 
-    l2_id = PL310_GetID(); 
-    if (l2_id) 
-    { 
-       PL310_InvAllByWay(); 
-       PL310_Enable(); 
-    } 
-} 
-#elif defined ( __ICCARM__ )
-
-void InitMemorySubsystem(void) { 
- 
-    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before 
-     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. 
-     * You are not required to invalidate the main TLB, even though it is recommended for safety 
-     * reasons. This ensures compatibility with future revisions of the processor. */ 
- 
-    unsigned int l2_id; 
- 
-    /* Invalidate undefined data */ 
-    __ca9u_inv_tlb_all(); 
-    __v7_inv_icache_all(); 
-    __v7_inv_dcache_all(); 
-    __v7_inv_btac(); 
- 
-    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and 
-     * invalidate in order to flush the valid data to the next level cache. 
-     */ 
-    __enable_mmu();
- 
-    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ 
-    __enable_caches(); 
-    __enable_btac(); 
- 
-    /* If present, you may also need to Invalidate and Enable L2 cache here */ 
-    l2_id = PL310_GetID(); 
-    if (l2_id) 
-    { 
-       PL310_InvAllByWay(); 
-       PL310_Enable(); 
-    } 
-} 
-#else 
-
-#endif 
-
-
-IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
-
-uint32_t IRQCount = sizeof IRQTable / 4;
-
-uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
-{
-    if (irq < IRQCount) {
-        IRQTable[irq] = handler;
-        return 0;
-    }
-    else {
-        return 1;
-    }
-}
-
-uint32_t InterruptHandlerUnregister (IRQn_Type irq)
-{
-    if (irq < IRQCount) {
-        IRQTable[irq] = 0;
-        return 0;
-    }
-    else {
-        return 1;
-    }
-}
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock.
- */
-void SystemCoreClockUpdate (void)
-{
-    uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
-
-    switch (frqcr_ifc) {
-        case FRQCR_IFC_1P1:
-            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
-            break;
-        case FRQCR_IFC_2P3:
-            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
-            break;
-        case FRQCR_IFC_1P3:
-            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK  / 3;
-            break;
-        default:
-            /* do nothing */
-            break;
-    }
-}
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-    IRQNestLevel = 0;
-/*       do not use global variables because this function is called before
-         reaching pre-main. RW section maybe overwritten afterwards.          */
-    RZ_A1_InitClock();
-    RZ_A1_InitBus();
-
-	//Configure GIC ICDICFR GIC_SetICDICFR()
-    GIC_Enable();
-    __enable_irq();
-
-}
-
-
-//Fault Status Register (IFSR/DFSR) definitions
-#define FSR_ALIGNMENT_FAULT                  0x01   //DFSR only. Fault on first lookup
-#define FSR_INSTRUCTION_CACHE_MAINTENANCE    0x04   //DFSR only - async/external
-#define FSR_SYNC_EXT_TTB_WALK_FIRST          0x0c   //sync/external
-#define FSR_SYNC_EXT_TTB_WALK_SECOND         0x0e   //sync/external
-#define FSR_SYNC_PARITY_TTB_WALK_FIRST       0x1c   //sync/external
-#define FSR_SYNC_PARITY_TTB_WALK_SECOND      0x1e   //sync/external
-#define FSR_TRANSLATION_FAULT_FIRST          0x05   //MMU Fault - internal
-#define FSR_TRANSLATION_FAULT_SECOND         0x07   //MMU Fault - internal
-#define FSR_ACCESS_FLAG_FAULT_FIRST          0x03   //MMU Fault - internal
-#define FSR_ACCESS_FLAG_FAULT_SECOND         0x06   //MMU Fault - internal
-#define FSR_DOMAIN_FAULT_FIRST               0x09   //MMU Fault - internal
-#define FSR_DOMAIN_FAULT_SECOND              0x0b   //MMU Fault - internal
-#define FSR_PERMISION_FAULT_FIRST            0x0f   //MMU Fault - internal
-#define FSR_PERMISION_FAULT_SECOND           0x0d   //MMU Fault - internal
-#define FSR_DEBUG_EVENT                      0x02   //internal
-#define FSR_SYNC_EXT_ABORT                   0x08   //sync/external
-#define FSR_TLB_CONFLICT_ABORT               0x10   //sync/external
-#define FSR_LOCKDOWN                         0x14   //internal
-#define FSR_COPROCESSOR_ABORT                0x1a   //internal
-#define FSR_SYNC_PARITY_ERROR                0x19   //sync/external
-#define FSR_ASYNC_EXTERNAL_ABORT             0x16   //DFSR only - async/external
-#define FSR_ASYNC_PARITY_ERROR               0x18   //DFSR only - async/external
-
-void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
-    uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
-
-    switch(FS) {
-        //Synchronous parity errors - retry
-        case FSR_SYNC_PARITY_ERROR:
-        case FSR_SYNC_PARITY_TTB_WALK_FIRST:
-        case FSR_SYNC_PARITY_TTB_WALK_SECOND:
-            return;
-
-        //Your code here. Value in DFAR is invalid for some fault statuses.
-        case FSR_ALIGNMENT_FAULT:
-        case FSR_INSTRUCTION_CACHE_MAINTENANCE:
-        case FSR_SYNC_EXT_TTB_WALK_FIRST:
-        case FSR_SYNC_EXT_TTB_WALK_SECOND:
-        case FSR_TRANSLATION_FAULT_FIRST:
-        case FSR_TRANSLATION_FAULT_SECOND:
-        case FSR_ACCESS_FLAG_FAULT_FIRST:
-        case FSR_ACCESS_FLAG_FAULT_SECOND:
-        case FSR_DOMAIN_FAULT_FIRST:
-        case FSR_DOMAIN_FAULT_SECOND:
-        case FSR_PERMISION_FAULT_FIRST:
-        case FSR_PERMISION_FAULT_SECOND:
-        case FSR_DEBUG_EVENT:
-        case FSR_SYNC_EXT_ABORT:
-        case FSR_TLB_CONFLICT_ABORT:
-        case FSR_LOCKDOWN:
-        case FSR_COPROCESSOR_ABORT:
-        case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
-        case FSR_ASYNC_PARITY_ERROR:   //DFAR invalid
-        default:
-            while(1);
-    }
-}
-
-void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
-    uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
-
-    switch(FS) {
-        //Synchronous parity errors - retry
-        case FSR_SYNC_PARITY_ERROR:
-        case FSR_SYNC_PARITY_TTB_WALK_FIRST:
-        case FSR_SYNC_PARITY_TTB_WALK_SECOND:
-            return;
-
-        //Your code here. Value in IFAR is invalid for some fault statuses.
-        case FSR_SYNC_EXT_TTB_WALK_FIRST:
-        case FSR_SYNC_EXT_TTB_WALK_SECOND:
-        case FSR_TRANSLATION_FAULT_FIRST:
-        case FSR_TRANSLATION_FAULT_SECOND:
-        case FSR_ACCESS_FLAG_FAULT_FIRST:
-        case FSR_ACCESS_FLAG_FAULT_SECOND:
-        case FSR_DOMAIN_FAULT_FIRST:
-        case FSR_DOMAIN_FAULT_SECOND:
-        case FSR_PERMISION_FAULT_FIRST:
-        case FSR_PERMISION_FAULT_SECOND:
-        case FSR_DEBUG_EVENT: //IFAR invalid
-        case FSR_SYNC_EXT_ABORT:
-        case FSR_TLB_CONFLICT_ABORT:
-        case FSR_LOCKDOWN:
-        case FSR_COPROCESSOR_ABORT:
-        default:
-            while(1);
-    }
-}
-
-//returns amount to decrement lr by
-//this will be 0 when we have emulated the instruction and want to execute the next instruction
-//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
-//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
-uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
-    const unsigned int THUMB = 2;
-    const unsigned int ARM = 4;
-    //Lazy VFP/NEON initialisation and switching
-
-    // (ARM ARM section A7.5) VFP data processing instruction?
-    // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
-    // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
-    // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
-    if ((state == ARM   && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
-        (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
-        if (((opcode & 0x00000E00) >> 9) == 5) {
-            FPUEnable();
-            return state;
-        }
-    }
-
-    // (ARM ARM section A7.4) NEON data processing instruction?
-    if ((state == ARM   && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
-        (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
-    // (ARM ARM section A7.7) NEON load/store instruction?
-        (state == ARM   && ((opcode >> 24) == 0xF4)) ||
-        (state == THUMB && ((opcode >> 24) == 0xF9))) {
-        FPUEnable();
-        return state;
-    }
-
-    //Add code here for other Undef cases
-    while(1);
-}
-
-#if defined(__ARMCC_VERSION)
-#pragma push
-#pragma arm
-//Critical section, called from undef handler, so systick is disabled
-__asm void FPUEnable(void) {
-        ARM
-
-        //Permit access to VFP/NEON, registers by modifying CPACR
-        MRC     p15,0,R1,c1,c0,2
-        ORR     R1,R1,#0x00F00000
-        MCR     p15,0,R1,c1,c0,2
-
-        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
-        ISB
-
-        //Enable VFP/NEON
-        VMRS    R1,FPEXC
-        ORR     R1,R1,#0x40000000
-        VMSR    FPEXC,R1
-
-        //Initialise VFP/NEON registers to 0
-        MOV     R2,#0
-        //Initialise D16 registers to 0
-        VMOV    D0, R2,R2
-        VMOV    D1, R2,R2
-        VMOV    D2, R2,R2
-        VMOV    D3, R2,R2
-        VMOV    D4, R2,R2
-        VMOV    D5, R2,R2
-        VMOV    D6, R2,R2
-        VMOV    D7, R2,R2
-        VMOV    D8, R2,R2
-        VMOV    D9, R2,R2
-        VMOV    D10,R2,R2
-        VMOV    D11,R2,R2
-        VMOV    D12,R2,R2
-        VMOV    D13,R2,R2
-        VMOV    D14,R2,R2
-        VMOV    D15,R2,R2
-        //Initialise D32 registers to 0
-        VMOV    D16,R2,R2
-        VMOV    D17,R2,R2
-        VMOV    D18,R2,R2
-        VMOV    D19,R2,R2
-        VMOV    D20,R2,R2
-        VMOV    D21,R2,R2
-        VMOV    D22,R2,R2
-        VMOV    D23,R2,R2
-        VMOV    D24,R2,R2
-        VMOV    D25,R2,R2
-        VMOV    D26,R2,R2
-        VMOV    D27,R2,R2
-        VMOV    D28,R2,R2
-        VMOV    D29,R2,R2
-        VMOV    D30,R2,R2
-        VMOV    D31,R2,R2
-        //Initialise FPSCR to a known state
-        VMRS    R2,FPSCR
-        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-        AND     R2,R2,R3
-        VMSR    FPSCR,R2
-
-        BX      LR
-}
-#pragma pop
-
-#elif defined(__GNUC__)
-void FPUEnable(void) {
-    __asm__ (
-        ".ARM;"
-
-        //Permit access to VFP/NEON, registers by modifying CPACR
-        "MRC     p15,0,R1,c1,c0,2;"
-        "ORR     R1,R1,#0x00F00000;"
-        "MCR     p15,0,R1,c1,c0,2;"
-
-        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
-        "ISB;"
-
-        //Enable VFP/NEON
-        "VMRS    R1,FPEXC;"
-        "ORR     R1,R1,#0x40000000;"
-        "VMSR    FPEXC,R1;"
-
-        //Initialise VFP/NEON registers to 0
-        "MOV     R2,#0;"
-        //Initialise D16 registers to 0
-        "VMOV    D0, R2,R2;"
-        "VMOV    D1, R2,R2;"
-        "VMOV    D2, R2,R2;"
-        "VMOV    D3, R2,R2;"
-        "VMOV    D4, R2,R2;"
-        "VMOV    D5, R2,R2;"
-        "VMOV    D6, R2,R2;"
-        "VMOV    D7, R2,R2;"
-        "VMOV    D8, R2,R2;"
-        "VMOV    D9, R2,R2;"
-        "VMOV    D10,R2,R2;"
-        "VMOV    D11,R2,R2;"
-        "VMOV    D12,R2,R2;"
-        "VMOV    D13,R2,R2;"
-        "VMOV    D14,R2,R2;"
-        "VMOV    D15,R2,R2;"
-        //Initialise D32 registers to 0
-        "VMOV    D16,R2,R2;"
-        "VMOV    D17,R2,R2;"
-        "VMOV    D18,R2,R2;"
-        "VMOV    D19,R2,R2;"
-        "VMOV    D20,R2,R2;"
-        "VMOV    D21,R2,R2;"
-        "VMOV    D22,R2,R2;"
-        "VMOV    D23,R2,R2;"
-        "VMOV    D24,R2,R2;"
-        "VMOV    D25,R2,R2;"
-        "VMOV    D26,R2,R2;"
-        "VMOV    D27,R2,R2;"
-        "VMOV    D28,R2,R2;"
-        "VMOV    D29,R2,R2;"
-        "VMOV    D30,R2,R2;"
-        "VMOV    D31,R2,R2;"
-
-        //Initialise FPSCR to a known state
-        "VMRS    R2,FPSCR;"
-        "LDR     R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-        "AND     R2,R2,R3;"
-        "VMSR    FPSCR,R2;"
-
-        //"BX      LR;"
-             :
-             :
-             :"r1", "r2", "r3");
-    return;
-}
-#else
-#endif
-

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,67 +0,0 @@
-/**************************************************************************//**
- * @file     system_MBRZA1H.h
- * @brief    CMSIS Device System Header File for
- *           ARMCA9 Device Series
- * @version  V1.00
- * @date     11 June 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __SYSTEM_MBRZA1H
-#define __SYSTEM_MBRZA1H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-typedef void(*IRQHandler)();
-uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
-uint32_t InterruptHandlerUnregister(IRQn_Type);
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the Systd short        int16_t;emCoreClock variable.
- */
-extern void SystemInit (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_MBRZA1H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_RZ_A1H.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,157 @@
+/******************************************************************************
+ * @file     system_RZ_A1H_H.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <RZ_A1H.h>
+#include "RZ_A1_Init.h"
+#include "irq_ctrl.h"
+
+#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
+#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
+#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
+
+/*
+ Port 0 (P0) MD pin assignment
+ P0_0: MD_BOOT0
+ P0_1: MD_BOOT1
+ P0_2: MD_CLK
+ P0_3: MD_CLKS
+ */
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  uint32_t freq;
+  uint16_t mode;
+  uint16_t ifc;
+
+  mode = (GPIO.PPR0 >> 2U) & 0x01U;
+
+  if (mode == 0) {
+    /* Clock Mode 0 */
+    /* CLKIN is between 10MHz and 13.33MHz */
+    /* Divider 1 uses 1/1 ratio, PLL x30 is ON */
+    freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
+  } else {
+    /* Clock Mode 1 */
+    /* CLKIN is 48MHz */
+    /* Divider 1 uses 1/4 ratio, PLL x32 is ON */
+    freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
+  }
+
+  /* Get CPG.FRQCR[IFC] bits */
+  ifc = (CPG.FRQCR >> 8U) & 0x03U;
+
+  /* Determine Divider 2 output clock */
+  if (ifc == 0x03U) {
+    /* Division ratio is 1/3 */
+    freq = (freq / 3U);
+  }
+  else {
+    if (ifc == 0x01U) {
+      /* Division ratio is 2/3 */
+      freq = (freq * 2U) / 3U;
+    }
+  }
+
+  SystemCoreClock = freq;
+}
+
+/*----------------------------------------------------------------------------
+  IRQ Handler Register/Unregister
+ *----------------------------------------------------------------------------*/
+uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
+{
+    return IRQ_SetHandler(irq, handler);
+}
+
+uint32_t InterruptHandlerUnregister (IRQn_Type irq)
+{
+    return IRQ_SetHandler(irq, (IRQHandler_t)NULL);
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/*       do not use global variables because this function is called before
+         reaching pre-main. RW section may be overwritten afterwards.          */
+  
+  // Enable SRAM write access
+  CPG.SYSCR3 = 0x0F;
+
+  RZ_A1_InitClock();
+  RZ_A1_InitBus();
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  L2C_InvAllByWay();
+  // Enable L2C
+  L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_RZ_A1H.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,81 @@
+/******************************************************************************
+ * @file     system_RZ_A1H.h
+ * @brief    CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_RZ_A1H_H
+#define __SYSTEM_RZ_A1H_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+typedef void(*IRQHandler)();         /*!< Type Definition for Interrupt Handlers */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Interrupt Handler Register.
+
+   Registers an Interrupt Handler into the IRQ Table.
+ */
+extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
+
+/**
+  \brief  Interrupt Handler Unregister.
+
+   Unregisters an Interrupt Handler from the IRQ Table.
+ */
+extern uint32_t InterruptHandlerUnregister(IRQn_Type);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_RZ_A1H_H */

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/vfp_neon_push_pop.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/vfp_neon_push_pop.h	Wed Jan 17 15:23:54 2018 +0000
@@ -6,7 +6,7 @@
 /* ARM armcc specific functions */
 #pragma push
 #pragma arm
-__STATIC_ASM void __vfp_neon_push(void) {
+static __asm void __vfp_neon_push(void) {
     ARM
 
     VMRS    R2,FPSCR
@@ -19,7 +19,7 @@
 
 #pragma push
 #pragma arm
-__STATIC_ASM void __vfp_neon_pop(void) {
+static __asm void __vfp_neon_pop(void) {
     ARM
 
     VLDMIA  SP!,{D16-D31}
@@ -34,7 +34,7 @@
 
 #pragma push
 #pragma arm
-__STATIC_ASM void __vfp_push(void) {
+static __asm void __vfp_push(void) {
     ARM
 
     VMRS    R2,FPSCR
@@ -46,7 +46,7 @@
 
 #pragma push
 #pragma arm
-__STATIC_ASM void __vfp_pop(void) {
+static __asm void __vfp_pop(void) {
     ARM
 
     VLDMIA  SP!,{D0-D15}
@@ -111,7 +111,7 @@
     "VSTMDB  SP!,{D0-D15};"
     "VSTMDB  SP!,{D16-D31};"
     :
-    : "i"(MODE_USR)
+    :
     : );
     return;
 }
@@ -127,7 +127,7 @@
     "VMSR    FPSCR,R2;"
     "ADD     SP,SP,#8;"
     :
-    : "i"(MODE_USR)
+    :
     : );
     return;
 }
@@ -141,7 +141,7 @@
     "STMDB   SP!,{R2,R4};"      // Push FPSCR, maintain 8-byte alignment
     "VSTMDB  SP!,{D0-D15};"
     :
-    : "i"(MODE_USR)
+    :
     : );
     return;
 }
@@ -156,7 +156,7 @@
     "VMSR    FPSCR,R2;"
     "ADD     SP,SP,#8;"
     :
-    : "i"(MODE_USR)
+    :
     : );
     return;
 }

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -87,6 +87,10 @@
                                                 /* 0x00000001 : Receive frame CRC error */
 #define EDMAC_EESIPR_INI_EtherC (0x00400000)    /* 0x00400000 : E-MAC status register */
 
+void ethernet_address(char *);
+void ethernet_set_link(int, int);
+
+
 /* Send descriptor */
 typedef struct tag_edmac_send_desc {
     uint32_t    td0;
@@ -532,12 +536,12 @@
 
 static void lan_reg_set(int32_t link) {
     /* MAC address setting */
-    ETHERMAHR0      = ((uint32_t)mac_addr[0] << 24)
-                    | ((uint32_t)mac_addr[1] << 16)
-                    | ((uint32_t)mac_addr[2] << 8)
-                    |  (uint32_t)mac_addr[3];
-    ETHERMALR0      = ((uint32_t)mac_addr[4] << 8)
-                    |  (uint32_t)mac_addr[5];
+    ETHERMAHR0      = ((uint8_t)mac_addr[0] << 24)
+                    | ((uint8_t)mac_addr[1] << 16)
+                    | ((uint8_t)mac_addr[2] << 8)
+                    |  (uint8_t)mac_addr[3];
+    ETHERMALR0      = ((uint8_t)mac_addr[4] << 8)
+                    |  (uint8_t)mac_addr[5];
 
     /* E-DMAC */
     ETHERTDLAR0     = (uint32_t)&p_eth_desc_dsend[0];
@@ -578,6 +582,7 @@
         ETHERECSIPR0   &= ~0x00000011;                     /* PFROIP Disable, ICDIP Disable */
         InterruptHandlerRegister(ETHERI_IRQn, INT_Ether);  /* Ethernet interrupt handler registration */
         GIC_SetPriority(ETHERI_IRQn, Interrupt_priority);  /* Ethernet interrupt priority */
+        GIC_SetConfiguration(ETHERI_IRQn, 1);
         GIC_EnableIRQ(ETHERI_IRQn);                        /* Enables the E-DMAC interrupt */
     }
 

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -166,6 +166,7 @@
     InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]);
     INTCICR1 &= ~(0x3 << shift);
     GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
+    GIC_SetConfiguration((IRQn_Type)(nIRQn_h + obj->ch), 1);
     obj->int_enable = 1;
     __enable_irq();
 

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1062,6 +1062,11 @@
         if (enable) {
             InterruptHandlerRegister(irqTable[i], handlerTable[i]);
             GIC_SetPriority(irqTable[i], 5);
+            if (i == 1) {
+                GIC_SetConfiguration(irqTable[i], 3);
+            } else {
+                GIC_SetConfiguration(irqTable[i], 1);
+            }
             GIC_EnableIRQ(irqTable[i]);
         } else {
             GIC_DisableIRQ(irqTable[i]);

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -268,10 +268,10 @@
         obj->pwm = pwm;
         if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) {
             obj->ch  = 2;
-            PWMPWPR_2_BYTE_L = 0x00;
+            PWMPWPR_2 = 0x00;
         } else {
             obj->ch  = 1;
-            PWMPWPR_1_BYTE_L = 0x00;
+            PWMPWPR_1 = 0x00;
         }
 
         // Wire pinout
@@ -493,7 +493,7 @@
 
         if (obj->ch == 2) {
             wk_last_cycle    = PWMPWCYR_2 & 0x03ff;
-            PWMPWCR_2_BYTE_L = 0xc0 | wk_cks;
+            PWMPWCR_2        = 0xc0 | wk_cks;
             PWMPWCYR_2       = (uint16_t)wk_cycle;
 
             // Set duty again
@@ -503,13 +503,13 @@
             set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle);
 
             // Counter Start
-            PWMPWCR_2_BYTE_L |= 0x08;
+            PWMPWCR_2 |= 0x08;
 
             // Save for future use
             period_ch2 = us;
         } else {
             wk_last_cycle    = PWMPWCYR_1 & 0x03ff;
-            PWMPWCR_1_BYTE_L = 0xc0 | wk_cks;
+            PWMPWCR_1        = 0xc0 | wk_cks;
             PWMPWCYR_1       = (uint16_t)wk_cycle;
 
             // Set duty again
@@ -519,7 +519,7 @@
             set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle);
 
             // Counter Start
-            PWMPWCR_1_BYTE_L |= 0x08;
+            PWMPWCR_1 |= 0x08;
 
             // Save for future use
             period_ch1 = us;

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -26,6 +26,7 @@
 
 #include "scif_iodefine.h"
 #include "cpg_iodefine.h"
+#include "mbed_critical.h"
 
 /******************************************************************************
  * INITIALIZATION
@@ -510,7 +511,7 @@
 
 static void uart_err_irq(IRQn_Type irq_num, uint32_t index) {
     serial_t *obj = uart_data[index].receiving_obj;
-    int was_masked, err_read;
+    int err_read;
     
     if (obj) {
         serial_irq_err_set(obj, 0);
@@ -525,11 +526,7 @@
         }
         serial_rx_abort_asynch(obj);
         
-#if defined ( __ICCARM__ )
-        was_masked = __disable_irq_iar();
-#else
-        was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+        core_util_critical_section_enter();
         if (obj->serial.uart->SCFSR & 0x93) {
             err_read = obj->serial.uart->SCFSR;
             obj->serial.uart->SCFSR = (err_read & ~0x93);
@@ -537,9 +534,7 @@
         if (obj->serial.uart->SCLSR & 1) {
             obj->serial.uart->SCLSR = 0;
         }
-        if (!was_masked) {
-            __enable_irq();
-        }
+        core_util_critical_section_exit();
     }
 }
 
@@ -679,21 +674,14 @@
 int serial_getc(serial_t *obj) {
     uint16_t err_read;
     int data;
-    int was_masked;
 
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
     if (obj->serial.uart->SCFSR & 0x93) {
         err_read = obj->serial.uart->SCFSR;
         obj->serial.uart->SCFSR = (err_read & ~0x93);
     }
     obj->serial.uart->SCSCR |= 0x0040;     // Set RIE
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 
     if (obj->serial.uart->SCLSR & 0x0001) {
         obj->serial.uart->SCLSR = 0u;      // ORER clear
@@ -702,16 +690,10 @@
     while (!serial_readable(obj));
     data = obj->serial.uart->SCFRDR & 0xff;
 
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
     err_read = obj->serial.uart->SCFSR;
     obj->serial.uart->SCFSR = (err_read & 0xfffD);     // Clear RDF
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 
     if (err_read & 0x80) {
         data = -1;  //err
@@ -727,20 +709,13 @@
 
 static void serial_put_done(serial_t *obj)
 {
-    int was_masked;
     volatile uint16_t dummy_read;
-    
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+
+    core_util_critical_section_enter();
     dummy_read = obj->serial.uart->SCFSR;
     obj->serial.uart->SCFSR = (dummy_read & 0xff9f);  // Clear TEND/TDFE
     obj->serial.uart->SCSCR |= 0x0080;     // Set TIE
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 }
 
 int serial_readable(serial_t *obj) {
@@ -752,20 +727,13 @@
 }
 
 void serial_clear(serial_t *obj) {
-    int was_masked;
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
 
     obj->serial.uart->SCFCR |=  0x06;          // TFRST = 1, RFRST = 1
     obj->serial.uart->SCFCR &= ~0x06;          // TFRST = 0, RFRST = 0
     obj->serial.uart->SCFSR &= ~0x0093u;       // ER, BRK, RDF, DR = 0
 
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 }
 
 void serial_pinout_tx(PinName tx) {
@@ -773,62 +741,35 @@
 }
 
 void serial_break_set(serial_t *obj) {
-    int was_masked;
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
     // TxD Output(L)
     obj->serial.uart->SCSPTR &= ~0x0001u;  // SPB2DT = 0
     obj->serial.uart->SCSCR &= ~0x0020u;   // TE = 0 (Output disable)
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 }
 
 void serial_break_clear(serial_t *obj) {
-    int was_masked;
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
     obj->serial.uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
     obj->serial.uart->SCSPTR |= 0x0001u; // SPB2DT = 1
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 }
 
 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
     // determine the UART to use
-    int was_masked;
 
     serial_flow_irq_set(obj, 0);
 
     if (type == FlowControlRTSCTS) {
-#if defined ( __ICCARM__ )
-        was_masked = __disable_irq_iar();
-#else
-        was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+        core_util_critical_section_enter();
         obj->serial.uart->SCFCR = 0x0008u;   // CTS/RTS enable
-        if (!was_masked) {
-            __enable_irq();
-        }
+        core_util_critical_section_exit();
         pinmap_pinout(rxflow, PinMap_UART_RTS);
         pinmap_pinout(txflow, PinMap_UART_CTS);
     } else {
-#if defined ( __ICCARM__ )
-        was_masked = __disable_irq_iar();
-#else
-        was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+        core_util_critical_section_enter();
         obj->serial.uart->SCFCR = 0x0000u; // CTS/RTS diable
-        if (!was_masked) {
-            __enable_irq();
-        }
+        core_util_critical_section_exit();
     }
 }
 

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -447,6 +447,7 @@
         if (enable) {
             InterruptHandlerRegister(irqTable[i], handlerTable[i]);
             GIC_SetPriority(irqTable[i], 5);
+            GIC_SetConfiguration(irqTable[i], 1);
             GIC_EnableIRQ(irqTable[i]);
         } else {
             GIC_DisableIRQ(irqTable[i]);

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c	Wed Jan 17 15:23:54 2018 +0000
@@ -21,6 +21,7 @@
 #include "RZ_A1_Init.h"
 #include "MBRZA1H.h"
 #include "vfp_neon_push_pop.h"
+#include "mbed_critical.h"
 
 #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn)
 #define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
@@ -62,6 +63,7 @@
     // INTC settings
     InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
     GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
+    GIC_SetConfiguration(US_TICKER_TIMER_IRQn, 3);
     GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
 }
 
@@ -92,21 +94,13 @@
 }
 
 uint32_t us_ticker_read() {
-    int check_irq_masked;
-
-#if defined ( __ICCARM__)
-    check_irq_masked = __disable_irq_iar();
-#else
-    check_irq_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
 
     __vfp_neon_push();
     us_ticker_read_last();
     __vfp_neon_pop();
 
-    if (!check_irq_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 
     /* clock to us */
     return (uint32_t)ticker_us_last64;

--- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/VKRZA1H.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/VKRZA1H.h	Wed Jan 17 15:23:54 2018 +0000
@@ -626,9 +626,9 @@
 #define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
 #define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
 
-#include <core_ca9.h>
+#include "core_ca.h"
 #include "system_VKRZA1H.h"
-
+#include "iodefine.h"
 
 /******************************************************************************/
 /*                Device Specific Peripheral Section                          */

--- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/serial_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/serial_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -23,6 +23,7 @@
 #include "cmsis.h"
 #include "pinmap.h"
 #include "gpio_api.h"
+#include "mbed_critical.h"
 
 #include "scif_iodefine.h"
 #include "cpg_iodefine.h"
@@ -570,21 +571,14 @@
 int serial_getc(serial_t *obj) {
     uint16_t err_read;
     int data;
-    int was_masked;
 
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
     if (obj->uart->SCFSR & 0x93) {
         err_read = obj->uart->SCFSR;
         obj->uart->SCFSR = (err_read & ~0x93);
     }
     obj->uart->SCSCR |= 0x0040;     // Set RIE
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 
     if (obj->uart->SCLSR & 0x0001) {
         obj->uart->SCLSR = 0u;      // ORER clear
@@ -593,16 +587,12 @@
     while (!serial_readable(obj));
     data = obj->uart->SCFRDR & 0xff;
 
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
+
     err_read = obj->uart->SCFSR;
     obj->uart->SCFSR = (err_read & 0xfffD);     // Clear RDF
-    if (!was_masked) {
-        __enable_irq();
-    }
+
+    core_util_critical_section_exit();
 
     if (err_read & 0x80) {
         data = -1;  //err
@@ -612,29 +602,16 @@
 
 void serial_putc(serial_t *obj, int c) {
     uint16_t dummy_read;
-    int was_masked;
 
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
     obj->uart->SCSCR |= 0x0080;     // Set TIE
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
     while (!serial_writable(obj));
     obj->uart->SCFTDR = c;
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
     dummy_read = obj->uart->SCFSR;
     obj->uart->SCFSR = (dummy_read & 0xff9f);  // Clear TEND/TDFE
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
     uart_data[obj->index].count++;
 }
 
@@ -647,20 +624,11 @@
 }
 
 void serial_clear(serial_t *obj) {
-    int was_masked;
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
-
+    core_util_critical_section_enter();
     obj->uart->SCFCR |=  0x06;          // TFRST = 1, RFRST = 1
     obj->uart->SCFCR &= ~0x06;          // TFRST = 0, RFRST = 0
     obj->uart->SCFSR &= ~0x0093u;       // ER, BRK, RDF, DR = 0
-
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 }
 
 void serial_pinout_tx(PinName tx) {
@@ -668,62 +636,34 @@
 }
 
 void serial_break_set(serial_t *obj) {
-    int was_masked;
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
     // TxD Output(L)
     obj->uart->SCSPTR &= ~0x0001u;  // SPB2DT = 0
     obj->uart->SCSCR &= ~0x0020u;   // TE = 0 (Output disable)
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 }
 
 void serial_break_clear(serial_t *obj) {
-    int was_masked;
-#if defined ( __ICCARM__ )
-    was_masked = __disable_irq_iar();
-#else
-    was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
     obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
     obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1
-    if (!was_masked) {
-        __enable_irq();
-    }
+    core_util_critical_section_exit();
 }
 
 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
     // determine the UART to use
-    int was_masked;
-
     serial_flow_irq_set(obj, 0);
 
     if (type == FlowControlRTSCTS) {
-#if defined ( __ICCARM__ )
-        was_masked = __disable_irq_iar();
-#else
-        was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+        core_util_critical_section_enter();
         obj->uart->SCFCR = 0x0008u;   // CTS/RTS enable
-        if (!was_masked) {
-            __enable_irq();
-        }
+        core_util_critical_section_exit();
         pinmap_pinout(rxflow, PinMap_UART_RTS);
         pinmap_pinout(txflow, PinMap_UART_CTS);
     } else {
-#if defined ( __ICCARM__ )
-        was_masked = __disable_irq_iar();
-#else
-        was_masked = __disable_irq();
-#endif /* __ICCARM__ */
+        core_util_critical_section_enter();
         obj->uart->SCFCR = 0x0000u; // CTS/RTS diable
-        if (!was_masked) {
-            __enable_irq();
-        }
+        core_util_critical_section_exit();
     }
 }
 

--- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c	Wed Jan 17 15:23:54 2018 +0000
@@ -20,6 +20,7 @@
 
 #include "RZ_A1_Init.h"
 #include "VKRZA1H.h"
+#include "mbed_critical.h"
 
 #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn)
 #define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
@@ -83,22 +84,14 @@
 uint32_t us_ticker_read() {
     uint64_t cnt_val64;
     uint64_t us_val64;
-    int check_irq_masked;
 
-#if defined ( __ICCARM__)
-    check_irq_masked = __disable_irq_iar();
-#else
-    check_irq_masked = __disable_irq();
-#endif /* __ICCARM__ */
+    core_util_critical_section_enter();
 
     cnt_val64        = ticker_read_counter64();
     us_val64         = (cnt_val64 / count_clock);
     ticker_us_last64 = us_val64;
 
-    if (!check_irq_masked) {
-        __enable_irq();
-    }
-
+    core_util_critical_section_exit();
     /* clock to us */
     return (uint32_t)us_val64;
 }

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/mbed_rtx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_MBED_RTX_H
+#define MBED_MBED_RTX_H
+
+#include <stdint.h>
+
+#define OS_IDLE_THREAD_STACK_SIZE   512
+
+#if defined(__CC_ARM)
+    extern char Image$$ARM_LIB_STACK$$Base[];
+    extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
+    extern char Image$$ARM_LIB_HEAP$$Base[];
+    #define ISR_STACK_START       ((unsigned char*)Image$$ARM_LIB_STACK$$Base)
+    #define ISR_STACK_SIZE        ((uint32_t)((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - (uint32_t)Image$$ARM_LIB_STACK$$Base))
+    #define INITIAL_SP            (Image$$ARM_LIB_STACK$$ZI$$Limit)
+    #define HEAP_START            ((unsigned char*)Image$$ARM_LIB_HEAP$$Base)
+    #define HEAP_SIZE             ((uint32_t)((uint32_t)ISR_STACK_START - (uint32_t)HEAP_START))
+#elif defined(__GNUC__)
+    extern uint32_t               __StackTop;
+    extern uint32_t               __StackLimit;
+    extern uint32_t               __end__;
+    #define ISR_STACK_START       ((unsigned char*)&__StackLimit)
+    #define ISR_STACK_SIZE        ((uint32_t)((uint32_t)&__StackTop - (uint32_t)&__StackLimit))
+    #define INITIAL_SP            (&__StackTop)
+    #define HEAP_START            ((unsigned char*)&__end__)
+    #define HEAP_SIZE             ((uint32_t)((uint32_t)ISR_STACK_START - (uint32_t)HEAP_START))
+#elif defined(__ICCARM__)
+    /* No region declarations needed */
+#else
+    #error "no toolchain defined"
+#endif
+
+#endif  // MBED_MBED_RTX_H

--- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -36,14 +36,16 @@
 
 #define MAX_SCAN_TIMEOUT (15000)
 
+static bool _inited = false;
+
 static rtw_result_t scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result )
 {
     wifi_scan_hdl *scan_handler = (wifi_scan_hdl *)malloced_scan_result->user_data;
     if (malloced_scan_result->scan_complete != RTW_TRUE) {
         if(scan_handler->ap_details && scan_handler->scan_num > scan_handler->ap_num){
-            nsapi_wifi_ap_t ap;    
+            nsapi_wifi_ap_t ap;
             rtw_scan_result_t* record = &malloced_scan_result->ap_details;
-            record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */    
+            record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */
             memset((void*)&ap, 0x00, sizeof(nsapi_wifi_ap_t));
             memcpy(ap.ssid, record->SSID.val, record->SSID.len);
             memcpy(ap.bssid, record->BSSID.octet, 6);
@@ -88,7 +90,7 @@
 {
     emac_interface_t *emac;
     int ret;
-    extern u32 GlobalDebugEnable; 
+    extern u32 GlobalDebugEnable;
 
     GlobalDebugEnable = debug?1:0;
     emac = wlan_emac_init_interface();
@@ -97,10 +99,13 @@
         return;
     }
     emac->ops.power_up(emac);
-    ret = mbed_lwip_init(emac);
-    if (ret != 0) {
-        printf("Error init RTWInterface!(%d)\r\n", ret);
-        return;
+    if (_inited == false) {
+        ret = mbed_lwip_init(emac);
+        if (ret != 0) {
+            printf("Error init RTWInterface!(%d)\r\n", ret);
+            return;
+        }
+        _inited = true;
     }
 }
 
@@ -130,6 +135,25 @@
  */
 nsapi_error_t RTWInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security)
 {
+    if(!ssid) {
+        return NSAPI_ERROR_PARAMETER;
+    }
+
+    switch (security) {
+        case NSAPI_SECURITY_WPA:
+        case NSAPI_SECURITY_WPA2:
+        case NSAPI_SECURITY_WPA_WPA2:
+        case NSAPI_SECURITY_WEP:
+            if((strlen(pass) < 8) || (strlen(pass) > 63)) { // 802.11 password 8-63 characters
+                return NSAPI_ERROR_PARAMETER;
+            }
+            break;
+        case NSAPI_SECURITY_NONE:
+            break;
+        default:
+            return NSAPI_ERROR_PARAMETER;
+    }
+
     strncpy(_ssid, ssid, 255);
     strncpy(_pass, pass, 255);
     _security = security;
@@ -158,7 +182,7 @@
             break;
         case NSAPI_SECURITY_NONE:
             sec = RTW_SECURITY_OPEN;
-            break;            
+            break;
         default:
             return NSAPI_ERROR_PARAMETER;
     }
@@ -167,7 +191,7 @@
         uint8_t pscan_config = PSCAN_ENABLE;
         wifi_set_pscan_chan(&_channel, &pscan_config, 1);
     }
-    
+
     ret = wifi_connect(_ssid, sec, _pass, strlen(_ssid), strlen(_pass), 0, (void *)NULL);
     if (ret != RTW_SUCCESS) {
         printf("failed: %d\r\n", ret);
@@ -218,7 +242,7 @@
 }
 
 nsapi_error_t RTWInterface::connect(const char *ssid, const char *pass,
-                           nsapi_security_t security, uint8_t channel)
+                            nsapi_security_t security, uint8_t channel)
 {
     set_credentials(ssid, pass, security);
     set_channel(channel);
@@ -230,9 +254,10 @@
     char essid[33];
 
     wlan_emac_link_change(false);
+    mbed_lwip_bringdown();
     if(wifi_is_connected_to_ap() != RTW_SUCCESS)
         return NSAPI_ERROR_NO_CONNECTION;
-    if(wifi_disconnect()<0){        
+    if(wifi_disconnect()<0){
         return NSAPI_ERROR_DEVICE_ERROR;
     }
     while(1){
@@ -281,4 +306,4 @@
 NetworkStack *RTWInterface::get_stack()
 {
     return nsapi_create_stack(&lwip_stack);
-}
\ No newline at end of file
+}

--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct	Wed Jan 17 15:23:54 2018 +0000
@@ -13,26 +13,26 @@
 LR_IRAM 0x10007000 (0x70000 - 0x7000) {
 
   IMAGE2_TABLE 0x10007000 FIXED {
-    *rtl8195a_init.o(.image2.ram.data*, +FIRST)
-    *rtl8195a_init.o(.image2.validate.rodata*)
+    *rtl8195a_init*.o(.image2.ram.data*, +FIRST)
+    *rtl8195a_init*.o(.image2.validate.rodata*)
   }
 
   ER_IRAM +0 FIXED {
-    *rtl8195a_crypto.o (+RO)
+    *rtl8195a_crypto*.o (+RO)
     *(i.mbedtls*)
     *libc.a (+RO)
     *rtx_*.o (+RO)
   }
 
   RW_IRAM1 +0 UNINIT FIXED {
-    *rtl8195a_crypto.o(+RW)
+    *rtl8195a_crypto*.o(+RW)
     *libc.a (+RW)
     *(.sdram.data*)
     *lib_peripheral_mbed_arm.ar (+RW)
   }
 
   RW_IRAM2 +0 UNINIT FIXED {
-    *rtl8195a_crypto.o(+ZI, COMMON)
+    *rtl8195a_crypto*.o(+ZI, COMMON)
     *libc.a (+ZI, COMMON)
     *(.bss.thread_stack_main)
     *lib_peripheral_mbed_arm.ar (+ZI, COMMON)
@@ -44,8 +44,8 @@
 
 LR_TCM 0x1FFF0000 0x10000 {
     TCM_OVERLAY 0x1FFF0000 0x10000 {
-        *lwip_mem.o(.bss*)
-        *lwip_memp.o(.bss*)
+        *lwip_mem*.o(.bss*)
+        *lwip_memp*.o(.bss*)
         *.o(.tcm.heap*)
     }
 }

--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c	Wed Jan 17 15:23:54 2018 +0000
@@ -15,17 +15,6 @@
  */
 #include "rtl8195a.h"
 
-#if defined(__CC_ARM)
-#include "cmsis_armcc.h"
-#elif (defined(__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
-#include "cmsis_armclang.h"
-#elif defined(__GNUC__)
-#include "cmsis_gcc.h"
-#else
-#include <cmsis_iar.h>
-#endif
-
-
 #if defined(__CC_ARM) || \
     (defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
 

--- a/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -56,7 +56,7 @@
 
 uint32_t flash_get_page_size(const flash_t *obj)
 {
-    return FLASH_PAGE_SIZE;
+    return 1;
 }
 
 uint32_t flash_get_start_address(const flash_t *obj)

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.s	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f051x8.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.2
-;* Date               : 26-June-2015
 ;* Description        : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.s	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f051x8.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.2
-;* Date               : 26-June-2015
 ;* Description        : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S	Wed Jan 17 15:23:54 2018 +0000
@@ -2,9 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f051x8.s
   * @author    MCD Application Team
-  * @version   V2.1.0
-  * @date      03-Oct-2014
-  * @brief     STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for Atollic TrueSTUDIO toolchain.
+  * @brief     STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -55,6 +53,10 @@
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
 
   .section .text.Reset_Handler
   .weak Reset_Handler
@@ -64,21 +66,35 @@
   mov   sp, r0          /* set stack pointer */
 
 /* Copy the data segment initializers from flash to SRAM */
-  movs r1, #0
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
   b LoopCopyDataInit
 
 CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
 
 LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
+  adds r4, r0, r3
+  cmp r4, r1
   bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h	Wed Jan 17 15:23:54 2018 +0000
@@ -46,11 +46,11 @@
 #define TIM_MST         TIM1
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
-#define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_RCC     __HAL_RCC_TIM1_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
-#define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM1_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM1_RELEASE_RESET()
 
 #define TIM_MST_16BIT  1 // 1=16-bit timer, 0=32-bit timer
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f051x8.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32F0xx devices.            
@@ -2805,56 +2803,108 @@
 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos             (0U)                                   
-#define GPIO_AFRL_AFRL0_Msk             (0xFU << GPIO_AFRL_AFRL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFRL0_Msk                    
-#define GPIO_AFRL_AFRL1_Pos             (4U)                                   
-#define GPIO_AFRL_AFRL1_Msk             (0xFU << GPIO_AFRL_AFRL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFRL1_Msk                    
-#define GPIO_AFRL_AFRL2_Pos             (8U)                                   
-#define GPIO_AFRL_AFRL2_Msk             (0xFU << GPIO_AFRL_AFRL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFRL2_Msk                    
-#define GPIO_AFRL_AFRL3_Pos             (12U)                                  
-#define GPIO_AFRL_AFRL3_Msk             (0xFU << GPIO_AFRL_AFRL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFRL3_Msk                    
-#define GPIO_AFRL_AFRL4_Pos             (16U)                                  
-#define GPIO_AFRL_AFRL4_Msk             (0xFU << GPIO_AFRL_AFRL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFRL4_Msk                    
-#define GPIO_AFRL_AFRL5_Pos             (20U)                                  
-#define GPIO_AFRL_AFRL5_Msk             (0xFU << GPIO_AFRL_AFRL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFRL5_Msk                    
-#define GPIO_AFRL_AFRL6_Pos             (24U)                                  
-#define GPIO_AFRL_AFRL6_Msk             (0xFU << GPIO_AFRL_AFRL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFRL6_Msk                    
-#define GPIO_AFRL_AFRL7_Pos             (28U)                                  
-#define GPIO_AFRL_AFRL7_Msk             (0xFU << GPIO_AFRL_AFRL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFRL7_Msk                    
-
+#define GPIO_AFRL_AFSEL0_Pos            (0U)                                   
+#define GPIO_AFRL_AFSEL0_Msk            (0xFU << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL1_Pos            (4U)                                   
+#define GPIO_AFRL_AFSEL1_Msk            (0xFU << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL2_Pos            (8U)                                   
+#define GPIO_AFRL_AFSEL2_Msk            (0xFU << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL3_Pos            (12U)                                  
+#define GPIO_AFRL_AFSEL3_Msk            (0xFU << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL4_Pos            (16U)                                  
+#define GPIO_AFRL_AFSEL4_Msk            (0xFU << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL5_Pos            (20U)                                  
+#define GPIO_AFRL_AFSEL5_Msk            (0xFU << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL6_Pos            (24U)                                  
+#define GPIO_AFRL_AFSEL6_Msk            (0xFU << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL7_Pos            (28U)                                  
+#define GPIO_AFRL_AFSEL7_Msk            (0xFU << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                GPIO_AFRL_AFSEL7_Msk  
+
+/* Legacy aliases */                  
+#define GPIO_AFRL_AFRL0_Pos             GPIO_AFRL_AFSEL0_Pos                                  
+#define GPIO_AFRL_AFRL0_Msk             GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1_Pos             GPIO_AFRL_AFSEL1_Pos
+#define GPIO_AFRL_AFRL1_Msk             GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2_Pos             GPIO_AFRL_AFSEL2_Pos
+#define GPIO_AFRL_AFRL2_Msk             GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3_Pos             GPIO_AFRL_AFSEL3_Pos
+#define GPIO_AFRL_AFRL3_Msk             GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4_Pos             GPIO_AFRL_AFSEL4_Pos
+#define GPIO_AFRL_AFRL4_Msk             GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5_Pos             GPIO_AFRL_AFSEL5_Pos
+#define GPIO_AFRL_AFRL5_Msk             GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6_Pos             GPIO_AFRL_AFSEL6_Pos
+#define GPIO_AFRL_AFRL6_Msk             GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7_Pos             GPIO_AFRL_AFSEL7_Pos
+#define GPIO_AFRL_AFRL7_Msk             GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFSEL7
+ 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos             (0U)                                   
-#define GPIO_AFRH_AFRH0_Msk             (0xFU << GPIO_AFRH_AFRH0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFRH0_Msk                    
-#define GPIO_AFRH_AFRH1_Pos             (4U)                                   
-#define GPIO_AFRH_AFRH1_Msk             (0xFU << GPIO_AFRH_AFRH1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFRH1_Msk                    
-#define GPIO_AFRH_AFRH2_Pos             (8U)                                   
-#define GPIO_AFRH_AFRH2_Msk             (0xFU << GPIO_AFRH_AFRH2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFRH2_Msk                    
-#define GPIO_AFRH_AFRH3_Pos             (12U)                                  
-#define GPIO_AFRH_AFRH3_Msk             (0xFU << GPIO_AFRH_AFRH3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFRH3_Msk                    
-#define GPIO_AFRH_AFRH4_Pos             (16U)                                  
-#define GPIO_AFRH_AFRH4_Msk             (0xFU << GPIO_AFRH_AFRH4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFRH4_Msk                    
-#define GPIO_AFRH_AFRH5_Pos             (20U)                                  
-#define GPIO_AFRH_AFRH5_Msk             (0xFU << GPIO_AFRH_AFRH5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFRH5_Msk                    
-#define GPIO_AFRH_AFRH6_Pos             (24U)                                  
-#define GPIO_AFRH_AFRH6_Msk             (0xFU << GPIO_AFRH_AFRH6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFRH6_Msk                    
-#define GPIO_AFRH_AFRH7_Pos             (28U)                                  
-#define GPIO_AFRH_AFRH7_Msk             (0xFU << GPIO_AFRH_AFRH7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFRH7_Msk                    
+#define GPIO_AFRH_AFSEL8_Pos            (0U)                                   
+#define GPIO_AFRH_AFSEL8_Msk            (0xFU << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL9_Pos            (4U)                                   
+#define GPIO_AFRH_AFSEL9_Msk            (0xFU << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL10_Pos           (8U)                                   
+#define GPIO_AFRH_AFSEL10_Msk           (0xFU << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10               GPIO_AFRH_AFSEL10_Msk                    
+#define GPIO_AFRH_AFSEL11_Pos           (12U)                                  
+#define GPIO_AFRH_AFSEL11_Msk           (0xFU << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11               GPIO_AFRH_AFSEL11_Msk                    
+#define GPIO_AFRH_AFSEL12_Pos           (16U)                                  
+#define GPIO_AFRH_AFSEL12_Msk           (0xFU << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12               GPIO_AFRH_AFSEL12_Msk                    
+#define GPIO_AFRH_AFSEL13_Pos           (20U)                                  
+#define GPIO_AFRH_AFSEL13_Msk           (0xFU << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13               GPIO_AFRH_AFSEL13_Msk                    
+#define GPIO_AFRH_AFSEL14_Pos           (24U)                                  
+#define GPIO_AFRH_AFSEL14_Msk           (0xFU << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14               GPIO_AFRH_AFSEL14_Msk                    
+#define GPIO_AFRH_AFSEL15_Pos           (28U)                                  
+#define GPIO_AFRH_AFSEL15_Msk           (0xFU << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15               GPIO_AFRH_AFSEL15_Msk                    
+
+/* Legacy aliases */                  
+#define GPIO_AFRH_AFRH0_Pos             GPIO_AFRH_AFSEL8_Pos
+#define GPIO_AFRH_AFRH0_Msk             GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1_Pos             GPIO_AFRH_AFSEL9_Pos
+#define GPIO_AFRH_AFRH1_Msk             GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2_Pos             GPIO_AFRH_AFSEL10_Pos
+#define GPIO_AFRH_AFRH2_Msk             GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3_Pos             GPIO_AFRH_AFSEL11_Pos
+#define GPIO_AFRH_AFRH3_Msk             GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4_Pos             GPIO_AFRH_AFSEL12_Pos
+#define GPIO_AFRH_AFRH4_Msk             GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5_Pos             GPIO_AFRH_AFSEL13_Pos
+#define GPIO_AFRH_AFRH5_Msk             GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6_Pos             GPIO_AFRH_AFSEL14_Pos
+#define GPIO_AFRH_AFRH6_Msk             GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7_Pos             GPIO_AFRH_AFSEL15_Pos
+#define GPIO_AFRH_AFRH7_Msk             GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFSEL15
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                   (0x00000001U)                          
@@ -3524,72 +3574,72 @@
 /*****************  Bit definition for RCC_APB2RSTR register  ****************/
 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)                          
 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
 #define RCC_APB2RSTR_ADCRST_Pos                  (9U)                          
 #define RCC_APB2RSTR_ADCRST_Msk                  (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC clock reset */
+#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC reset */
 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)                         
 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)                         
 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
 #define RCC_APB2RSTR_USART1RST_Pos               (14U)                         
 #define RCC_APB2RSTR_USART1RST_Msk               (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 clock reset */
+#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
 #define RCC_APB2RSTR_TIM15RST_Pos                (16U)                         
 #define RCC_APB2RSTR_TIM15RST_Msk                (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
-#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 reset */
 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)                         
 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)                         
 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
 #define RCC_APB2RSTR_DBGMCURST_Pos               (22U)                         
 #define RCC_APB2RSTR_DBGMCURST_Msk               (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU clock reset */
-
-/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU reset */
+
+/*!< Old ADC1 reset bit definition maintained for legacy purpose */
 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST          
 
 /*****************  Bit definition for RCC_APB1RSTR register  ****************/
 #define RCC_APB1RSTR_TIM2RST_Pos                 (0U)                          
 #define RCC_APB1RSTR_TIM2RST_Msk                 (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)                          
 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
 #define RCC_APB1RSTR_TIM6RST_Pos                 (4U)                          
 #define RCC_APB1RSTR_TIM6RST_Msk                 (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 reset */
 #define RCC_APB1RSTR_TIM14RST_Pos                (8U)                          
 #define RCC_APB1RSTR_TIM14RST_Msk                (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
-#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 reset */
 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)                         
 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
 #define RCC_APB1RSTR_SPI2RST_Pos                 (14U)                         
 #define RCC_APB1RSTR_SPI2RST_Msk                 (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
 #define RCC_APB1RSTR_USART2RST_Pos               (17U)                         
 #define RCC_APB1RSTR_USART2RST_Msk               (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)                         
 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
 #define RCC_APB1RSTR_I2C2RST_Pos                 (22U)                         
 #define RCC_APB1RSTR_I2C2RST_Msk                 (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 reset */
 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)                         
 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR clock reset */
+#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
 #define RCC_APB1RSTR_DACRST_Pos                  (29U)                         
 #define RCC_APB1RSTR_DACRST_Msk                  (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                      RCC_APB1RSTR_DACRST_Msk       /*!< DAC clock reset */
+#define RCC_APB1RSTR_DACRST                      RCC_APB1RSTR_DACRST_Msk       /*!< DAC reset */
 #define RCC_APB1RSTR_CECRST_Pos                  (30U)                         
 #define RCC_APB1RSTR_CECRST_Msk                  (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
-#define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC clock reset */
+#define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC reset */
 
 /******************  Bit definition for RCC_AHBENR register  *****************/
 #define RCC_AHBENR_DMAEN_Pos                     (0U)                          
@@ -3775,25 +3825,25 @@
 /*******************  Bit definition for RCC_AHBRSTR register  ***************/
 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)                         
 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
-#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)                         
 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
-#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)                         
 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
-#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
 #define RCC_AHBRSTR_GPIODRST_Pos                 (20U)                         
 #define RCC_AHBRSTR_GPIODRST_Msk                 (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
-#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD reset */
 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)                         
 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
-#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
 #define RCC_AHBRSTR_TSCRST_Pos                   (24U)                         
 #define RCC_AHBRSTR_TSCRST_Msk                   (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
-#define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS clock reset */
+#define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS reset */
 
 /* Old Bit definition maintained for legacy purpose */
-#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS reset */
 
 /*******************  Bit definition for RCC_CFGR2 register  *****************/
 /*!< PREDIV configuration */
@@ -3986,9 +4036,9 @@
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP_Pos               (18U)                                     
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -4020,6 +4070,11 @@
 #define RTC_CR_TSEDGE_Msk            (0x1U << RTC_CR_TSEDGE_Pos)               /*!< 0x00000008 */
 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk                         
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  *****************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
@@ -6636,6 +6691,9 @@
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
   ((INSTANCE) == TIM14)
 
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+  ((INSTANCE) == TIM1)
+
 /****************************** TSC Instances *********************************/
 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS STM32F0xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -112,11 +110,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.3
   */
 #define __STM32F0_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
 #define __STM32F0_DEVICE_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F0_DEVICE_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F0_DEVICE_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32F0_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F0_DEVICE_VERSION        ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
                                         |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c	Wed Jan 17 15:23:54 2018 +0000
@@ -212,7 +212,6 @@
     RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
     RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
     RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
     RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
     RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.  
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S	Wed Jan 17 15:23:54 2018 +0000
@@ -101,7 +101,7 @@
                 DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
                 DCD     0                              ; Reserved
                 DCD     TIM3_IRQHandler                ; TIM3
-                DCD     0                              ; Reserved
+                DCD     TIM6_IRQHandler                ; TIM6
                 DCD     0                              ; Reserved
                 DCD     TIM14_IRQHandler               ; TIM14
                 DCD     TIM15_IRQHandler               ; TIM15
@@ -120,7 +120,7 @@
 
                 AREA    |.text|, CODE, READONLY
 
-; Reset handler
+; Reset handler routine
 Reset_Handler    PROC
                  EXPORT  Reset_Handler                 [WEAK]
         IMPORT  __main
@@ -171,6 +171,7 @@
                 EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
                 EXPORT  TIM1_CC_IRQHandler             [WEAK]
                 EXPORT  TIM3_IRQHandler                [WEAK]
+                EXPORT  TIM6_IRQHandler                [WEAK]
                 EXPORT  TIM14_IRQHandler               [WEAK]
                 EXPORT  TIM15_IRQHandler               [WEAK]
                 EXPORT  TIM16_IRQHandler               [WEAK]
@@ -197,6 +198,7 @@
 TIM1_BRK_UP_TRG_COM_IRQHandler
 TIM1_CC_IRQHandler
 TIM3_IRQHandler
+TIM6_IRQHandler
 TIM14_IRQHandler
 TIM15_IRQHandler
 TIM16_IRQHandler

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S	Wed Jan 17 15:23:54 2018 +0000
@@ -74,7 +74,7 @@
                 DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
                 DCD     0                              ; Reserved
                 DCD     TIM3_IRQHandler                ; TIM3
-                DCD     0                              ; Reserved
+                DCD     TIM6_IRQHandler                ; TIM6
                 DCD     0                              ; Reserved
                 DCD     TIM14_IRQHandler               ; TIM14
                 DCD     TIM15_IRQHandler               ; TIM15
@@ -93,7 +93,7 @@
 
                 AREA    |.text|, CODE, READONLY
 
-; Reset handler
+; Reset handler routine
 Reset_Handler    PROC
                  EXPORT  Reset_Handler                 [WEAK]
         IMPORT  __main
@@ -144,6 +144,7 @@
                 EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
                 EXPORT  TIM1_CC_IRQHandler             [WEAK]
                 EXPORT  TIM3_IRQHandler                [WEAK]
+                EXPORT  TIM6_IRQHandler                [WEAK]
                 EXPORT  TIM14_IRQHandler               [WEAK]
                 EXPORT  TIM15_IRQHandler               [WEAK]
                 EXPORT  TIM16_IRQHandler               [WEAK]
@@ -170,6 +171,7 @@
 TIM1_BRK_UP_TRG_COM_IRQHandler
 TIM1_CC_IRQHandler
 TIM3_IRQHandler
+TIM6_IRQHandler
 TIM14_IRQHandler
 TIM15_IRQHandler
 TIM16_IRQHandler

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S	Wed Jan 17 15:23:54 2018 +0000
@@ -2,9 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f030x8.s
   * @author    MCD Application Team
-  * @version   V2.1.0
-  * @date      03-Oct-2014
-  * @brief     STM32F030x8 devices vector table for Atollic TrueSTUDIO toolchain.
+  * @brief     STM32F030x8 devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -55,6 +53,10 @@
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
 
   .section .text.Reset_Handler
   .weak Reset_Handler
@@ -64,21 +66,35 @@
   mov   sp, r0          /* set stack pointer */
 
 /* Copy the data segment initializers from flash to SRAM */
-  movs r1, #0
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
   b LoopCopyDataInit
 
 CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
 
 LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
+  adds r4, r0, r3
+  cmp r4, r1
   bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f030x8.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 03-Oct-2014
 ;* Description        : STM32F030x8 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,8 +13,6 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h	Wed Jan 17 15:23:54 2018 +0000
@@ -46,11 +46,11 @@
 #define TIM_MST         TIM1
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
-#define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_RCC     __HAL_RCC_TIM1_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
-#define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM1_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM1_RELEASE_RESET()
 
 #define TIM_MST_16BIT  1 // 1=16-bit timer, 0=32-bit timer
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f030x8.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32F0xx devices.            
@@ -2301,56 +2299,108 @@
 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos             (0U)                                   
-#define GPIO_AFRL_AFRL0_Msk             (0xFU << GPIO_AFRL_AFRL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFRL0_Msk                    
-#define GPIO_AFRL_AFRL1_Pos             (4U)                                   
-#define GPIO_AFRL_AFRL1_Msk             (0xFU << GPIO_AFRL_AFRL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFRL1_Msk                    
-#define GPIO_AFRL_AFRL2_Pos             (8U)                                   
-#define GPIO_AFRL_AFRL2_Msk             (0xFU << GPIO_AFRL_AFRL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFRL2_Msk                    
-#define GPIO_AFRL_AFRL3_Pos             (12U)                                  
-#define GPIO_AFRL_AFRL3_Msk             (0xFU << GPIO_AFRL_AFRL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFRL3_Msk                    
-#define GPIO_AFRL_AFRL4_Pos             (16U)                                  
-#define GPIO_AFRL_AFRL4_Msk             (0xFU << GPIO_AFRL_AFRL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFRL4_Msk                    
-#define GPIO_AFRL_AFRL5_Pos             (20U)                                  
-#define GPIO_AFRL_AFRL5_Msk             (0xFU << GPIO_AFRL_AFRL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFRL5_Msk                    
-#define GPIO_AFRL_AFRL6_Pos             (24U)                                  
-#define GPIO_AFRL_AFRL6_Msk             (0xFU << GPIO_AFRL_AFRL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFRL6_Msk                    
-#define GPIO_AFRL_AFRL7_Pos             (28U)                                  
-#define GPIO_AFRL_AFRL7_Msk             (0xFU << GPIO_AFRL_AFRL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFRL7_Msk                    
-
+#define GPIO_AFRL_AFSEL0_Pos            (0U)                                   
+#define GPIO_AFRL_AFSEL0_Msk            (0xFU << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL1_Pos            (4U)                                   
+#define GPIO_AFRL_AFSEL1_Msk            (0xFU << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL2_Pos            (8U)                                   
+#define GPIO_AFRL_AFSEL2_Msk            (0xFU << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL3_Pos            (12U)                                  
+#define GPIO_AFRL_AFSEL3_Msk            (0xFU << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL4_Pos            (16U)                                  
+#define GPIO_AFRL_AFSEL4_Msk            (0xFU << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL5_Pos            (20U)                                  
+#define GPIO_AFRL_AFSEL5_Msk            (0xFU << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL6_Pos            (24U)                                  
+#define GPIO_AFRL_AFSEL6_Msk            (0xFU << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL7_Pos            (28U)                                  
+#define GPIO_AFRL_AFSEL7_Msk            (0xFU << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                GPIO_AFRL_AFSEL7_Msk  
+
+/* Legacy aliases */                  
+#define GPIO_AFRL_AFRL0_Pos             GPIO_AFRL_AFSEL0_Pos                                  
+#define GPIO_AFRL_AFRL0_Msk             GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1_Pos             GPIO_AFRL_AFSEL1_Pos
+#define GPIO_AFRL_AFRL1_Msk             GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2_Pos             GPIO_AFRL_AFSEL2_Pos
+#define GPIO_AFRL_AFRL2_Msk             GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3_Pos             GPIO_AFRL_AFSEL3_Pos
+#define GPIO_AFRL_AFRL3_Msk             GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4_Pos             GPIO_AFRL_AFSEL4_Pos
+#define GPIO_AFRL_AFRL4_Msk             GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5_Pos             GPIO_AFRL_AFSEL5_Pos
+#define GPIO_AFRL_AFRL5_Msk             GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6_Pos             GPIO_AFRL_AFSEL6_Pos
+#define GPIO_AFRL_AFRL6_Msk             GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7_Pos             GPIO_AFRL_AFSEL7_Pos
+#define GPIO_AFRL_AFRL7_Msk             GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFSEL7
+ 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos             (0U)                                   
-#define GPIO_AFRH_AFRH0_Msk             (0xFU << GPIO_AFRH_AFRH0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFRH0_Msk                    
-#define GPIO_AFRH_AFRH1_Pos             (4U)                                   
-#define GPIO_AFRH_AFRH1_Msk             (0xFU << GPIO_AFRH_AFRH1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFRH1_Msk                    
-#define GPIO_AFRH_AFRH2_Pos             (8U)                                   
-#define GPIO_AFRH_AFRH2_Msk             (0xFU << GPIO_AFRH_AFRH2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFRH2_Msk                    
-#define GPIO_AFRH_AFRH3_Pos             (12U)                                  
-#define GPIO_AFRH_AFRH3_Msk             (0xFU << GPIO_AFRH_AFRH3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFRH3_Msk                    
-#define GPIO_AFRH_AFRH4_Pos             (16U)                                  
-#define GPIO_AFRH_AFRH4_Msk             (0xFU << GPIO_AFRH_AFRH4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFRH4_Msk                    
-#define GPIO_AFRH_AFRH5_Pos             (20U)                                  
-#define GPIO_AFRH_AFRH5_Msk             (0xFU << GPIO_AFRH_AFRH5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFRH5_Msk                    
-#define GPIO_AFRH_AFRH6_Pos             (24U)                                  
-#define GPIO_AFRH_AFRH6_Msk             (0xFU << GPIO_AFRH_AFRH6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFRH6_Msk                    
-#define GPIO_AFRH_AFRH7_Pos             (28U)                                  
-#define GPIO_AFRH_AFRH7_Msk             (0xFU << GPIO_AFRH_AFRH7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFRH7_Msk                    
+#define GPIO_AFRH_AFSEL8_Pos            (0U)                                   
+#define GPIO_AFRH_AFSEL8_Msk            (0xFU << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL9_Pos            (4U)                                   
+#define GPIO_AFRH_AFSEL9_Msk            (0xFU << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL10_Pos           (8U)                                   
+#define GPIO_AFRH_AFSEL10_Msk           (0xFU << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10               GPIO_AFRH_AFSEL10_Msk                    
+#define GPIO_AFRH_AFSEL11_Pos           (12U)                                  
+#define GPIO_AFRH_AFSEL11_Msk           (0xFU << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11               GPIO_AFRH_AFSEL11_Msk                    
+#define GPIO_AFRH_AFSEL12_Pos           (16U)                                  
+#define GPIO_AFRH_AFSEL12_Msk           (0xFU << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12               GPIO_AFRH_AFSEL12_Msk                    
+#define GPIO_AFRH_AFSEL13_Pos           (20U)                                  
+#define GPIO_AFRH_AFSEL13_Msk           (0xFU << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13               GPIO_AFRH_AFSEL13_Msk                    
+#define GPIO_AFRH_AFSEL14_Pos           (24U)                                  
+#define GPIO_AFRH_AFSEL14_Msk           (0xFU << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14               GPIO_AFRH_AFSEL14_Msk                    
+#define GPIO_AFRH_AFSEL15_Pos           (28U)                                  
+#define GPIO_AFRH_AFSEL15_Msk           (0xFU << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15               GPIO_AFRH_AFSEL15_Msk                    
+
+/* Legacy aliases */                  
+#define GPIO_AFRH_AFRH0_Pos             GPIO_AFRH_AFSEL8_Pos
+#define GPIO_AFRH_AFRH0_Msk             GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1_Pos             GPIO_AFRH_AFSEL9_Pos
+#define GPIO_AFRH_AFRH1_Msk             GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2_Pos             GPIO_AFRH_AFSEL10_Pos
+#define GPIO_AFRH_AFRH2_Msk             GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3_Pos             GPIO_AFRH_AFSEL11_Pos
+#define GPIO_AFRH_AFRH3_Msk             GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4_Pos             GPIO_AFRH_AFSEL12_Pos
+#define GPIO_AFRH_AFRH4_Msk             GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5_Pos             GPIO_AFRH_AFSEL13_Pos
+#define GPIO_AFRH_AFRH5_Msk             GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6_Pos             GPIO_AFRH_AFSEL14_Pos
+#define GPIO_AFRH_AFRH6_Msk             GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7_Pos             GPIO_AFRH_AFSEL15_Pos
+#define GPIO_AFRH_AFRH7_Msk             GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFSEL15
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                   (0x00000001U)                          
@@ -2990,63 +3040,63 @@
 /*****************  Bit definition for RCC_APB2RSTR register  ****************/
 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)                          
 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
 #define RCC_APB2RSTR_ADCRST_Pos                  (9U)                          
 #define RCC_APB2RSTR_ADCRST_Msk                  (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC clock reset */
+#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC reset */
 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)                         
 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)                         
 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
 #define RCC_APB2RSTR_USART1RST_Pos               (14U)                         
 #define RCC_APB2RSTR_USART1RST_Msk               (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 clock reset */
+#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
 #define RCC_APB2RSTR_TIM15RST_Pos                (16U)                         
 #define RCC_APB2RSTR_TIM15RST_Msk                (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
-#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 reset */
 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)                         
 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)                         
 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
 #define RCC_APB2RSTR_DBGMCURST_Pos               (22U)                         
 #define RCC_APB2RSTR_DBGMCURST_Msk               (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU clock reset */
-
-/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU reset */
+
+/*!< Old ADC1 reset bit definition maintained for legacy purpose */
 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST          
 
 /*****************  Bit definition for RCC_APB1RSTR register  ****************/
 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)                          
 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
 #define RCC_APB1RSTR_TIM6RST_Pos                 (4U)                          
 #define RCC_APB1RSTR_TIM6RST_Msk                 (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 reset */
 #define RCC_APB1RSTR_TIM14RST_Pos                (8U)                          
 #define RCC_APB1RSTR_TIM14RST_Msk                (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
-#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 reset */
 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)                         
 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
 #define RCC_APB1RSTR_SPI2RST_Pos                 (14U)                         
 #define RCC_APB1RSTR_SPI2RST_Msk                 (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
 #define RCC_APB1RSTR_USART2RST_Pos               (17U)                         
 #define RCC_APB1RSTR_USART2RST_Msk               (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)                         
 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
 #define RCC_APB1RSTR_I2C2RST_Pos                 (22U)                         
 #define RCC_APB1RSTR_I2C2RST_Msk                 (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 reset */
 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)                         
 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR clock reset */
+#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
 
 /******************  Bit definition for RCC_AHBENR register  *****************/
 #define RCC_AHBENR_DMAEN_Pos                     (0U)                          
@@ -3220,19 +3270,19 @@
 /*******************  Bit definition for RCC_AHBRSTR register  ***************/
 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)                         
 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
-#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)                         
 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
-#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)                         
 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
-#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
 #define RCC_AHBRSTR_GPIODRST_Pos                 (20U)                         
 #define RCC_AHBRSTR_GPIODRST_Msk                 (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
-#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD reset */
 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)                         
 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
-#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
 
 /*******************  Bit definition for RCC_CFGR2 register  *****************/
 /*!< PREDIV configuration */
@@ -3414,9 +3464,9 @@
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP_Pos               (18U)                                     
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -3448,6 +3498,11 @@
 #define RTC_CR_TSEDGE_Msk            (0x1U << RTC_CR_TSEDGE_Pos)               /*!< 0x00000008 */
 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk                         
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  *****************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
@@ -5322,7 +5377,10 @@
     
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
    ((INSTANCE) == TIM14)
-   
+
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+  ((INSTANCE) == TIM1)
+
 /******************** USART Instances : Synchronous mode **********************/
 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                      ((INSTANCE) == USART2))

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS STM32F0xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -112,11 +110,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.3
   */
 #define __STM32F0_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
 #define __STM32F0_DEVICE_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F0_DEVICE_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F0_DEVICE_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32F0_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F0_DEVICE_VERSION        ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
                                         |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c	Wed Jan 17 15:23:54 2018 +0000
@@ -213,7 +213,6 @@
     RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
     RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
     RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
     RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
     RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.  
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f031x6.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.2
-;* Date               : 26-June-2015
 ;* Description        : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f031x6.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.2
-;* Date               : 26-June-2015
 ;* Description        : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s	Wed Jan 17 15:23:54 2018 +0000
@@ -2,9 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f031x6.s
   * @author    MCD Application Team
-  * @version   V2.2.2
-  * @date      26-June-2015
-  * @brief     STM32F031x4/STM32F031x6 devices vector table for Atollic TrueSTUDIO toolchain.
+  * @brief     STM32F031x4/STM32F031x6 devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -55,6 +53,10 @@
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
 
   .section .text.Reset_Handler
   .weak Reset_Handler
@@ -64,21 +66,35 @@
   mov   sp, r0          /* set stack pointer */
 
 /* Copy the data segment initializers from flash to SRAM */
-  movs r1, #0
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
   b LoopCopyDataInit
 
 CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
 
 LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
+  adds r4, r0, r3
+  cmp r4, r1
   bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.s	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f031x6.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.2
-;* Date               : 26-June-2015
 ;* Description        : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,8 +13,6 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h	Wed Jan 17 15:23:54 2018 +0000
@@ -45,11 +45,11 @@
 
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
-#define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
-#define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
 
 #define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f031x6.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32F0xx devices.            
@@ -2359,56 +2357,108 @@
 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos             (0U)                                   
-#define GPIO_AFRL_AFRL0_Msk             (0xFU << GPIO_AFRL_AFRL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFRL0_Msk                    
-#define GPIO_AFRL_AFRL1_Pos             (4U)                                   
-#define GPIO_AFRL_AFRL1_Msk             (0xFU << GPIO_AFRL_AFRL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFRL1_Msk                    
-#define GPIO_AFRL_AFRL2_Pos             (8U)                                   
-#define GPIO_AFRL_AFRL2_Msk             (0xFU << GPIO_AFRL_AFRL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFRL2_Msk                    
-#define GPIO_AFRL_AFRL3_Pos             (12U)                                  
-#define GPIO_AFRL_AFRL3_Msk             (0xFU << GPIO_AFRL_AFRL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFRL3_Msk                    
-#define GPIO_AFRL_AFRL4_Pos             (16U)                                  
-#define GPIO_AFRL_AFRL4_Msk             (0xFU << GPIO_AFRL_AFRL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFRL4_Msk                    
-#define GPIO_AFRL_AFRL5_Pos             (20U)                                  
-#define GPIO_AFRL_AFRL5_Msk             (0xFU << GPIO_AFRL_AFRL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFRL5_Msk                    
-#define GPIO_AFRL_AFRL6_Pos             (24U)                                  
-#define GPIO_AFRL_AFRL6_Msk             (0xFU << GPIO_AFRL_AFRL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFRL6_Msk                    
-#define GPIO_AFRL_AFRL7_Pos             (28U)                                  
-#define GPIO_AFRL_AFRL7_Msk             (0xFU << GPIO_AFRL_AFRL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFRL7_Msk                    
-
+#define GPIO_AFRL_AFSEL0_Pos            (0U)                                   
+#define GPIO_AFRL_AFSEL0_Msk            (0xFU << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL1_Pos            (4U)                                   
+#define GPIO_AFRL_AFSEL1_Msk            (0xFU << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL2_Pos            (8U)                                   
+#define GPIO_AFRL_AFSEL2_Msk            (0xFU << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL3_Pos            (12U)                                  
+#define GPIO_AFRL_AFSEL3_Msk            (0xFU << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL4_Pos            (16U)                                  
+#define GPIO_AFRL_AFSEL4_Msk            (0xFU << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL5_Pos            (20U)                                  
+#define GPIO_AFRL_AFSEL5_Msk            (0xFU << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL6_Pos            (24U)                                  
+#define GPIO_AFRL_AFSEL6_Msk            (0xFU << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL7_Pos            (28U)                                  
+#define GPIO_AFRL_AFSEL7_Msk            (0xFU << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                GPIO_AFRL_AFSEL7_Msk  
+
+/* Legacy aliases */                  
+#define GPIO_AFRL_AFRL0_Pos             GPIO_AFRL_AFSEL0_Pos                                  
+#define GPIO_AFRL_AFRL0_Msk             GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1_Pos             GPIO_AFRL_AFSEL1_Pos
+#define GPIO_AFRL_AFRL1_Msk             GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2_Pos             GPIO_AFRL_AFSEL2_Pos
+#define GPIO_AFRL_AFRL2_Msk             GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3_Pos             GPIO_AFRL_AFSEL3_Pos
+#define GPIO_AFRL_AFRL3_Msk             GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4_Pos             GPIO_AFRL_AFSEL4_Pos
+#define GPIO_AFRL_AFRL4_Msk             GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5_Pos             GPIO_AFRL_AFSEL5_Pos
+#define GPIO_AFRL_AFRL5_Msk             GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6_Pos             GPIO_AFRL_AFSEL6_Pos
+#define GPIO_AFRL_AFRL6_Msk             GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7_Pos             GPIO_AFRL_AFSEL7_Pos
+#define GPIO_AFRL_AFRL7_Msk             GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFSEL7
+ 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos             (0U)                                   
-#define GPIO_AFRH_AFRH0_Msk             (0xFU << GPIO_AFRH_AFRH0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFRH0_Msk                    
-#define GPIO_AFRH_AFRH1_Pos             (4U)                                   
-#define GPIO_AFRH_AFRH1_Msk             (0xFU << GPIO_AFRH_AFRH1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFRH1_Msk                    
-#define GPIO_AFRH_AFRH2_Pos             (8U)                                   
-#define GPIO_AFRH_AFRH2_Msk             (0xFU << GPIO_AFRH_AFRH2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFRH2_Msk                    
-#define GPIO_AFRH_AFRH3_Pos             (12U)                                  
-#define GPIO_AFRH_AFRH3_Msk             (0xFU << GPIO_AFRH_AFRH3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFRH3_Msk                    
-#define GPIO_AFRH_AFRH4_Pos             (16U)                                  
-#define GPIO_AFRH_AFRH4_Msk             (0xFU << GPIO_AFRH_AFRH4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFRH4_Msk                    
-#define GPIO_AFRH_AFRH5_Pos             (20U)                                  
-#define GPIO_AFRH_AFRH5_Msk             (0xFU << GPIO_AFRH_AFRH5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFRH5_Msk                    
-#define GPIO_AFRH_AFRH6_Pos             (24U)                                  
-#define GPIO_AFRH_AFRH6_Msk             (0xFU << GPIO_AFRH_AFRH6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFRH6_Msk                    
-#define GPIO_AFRH_AFRH7_Pos             (28U)                                  
-#define GPIO_AFRH_AFRH7_Msk             (0xFU << GPIO_AFRH_AFRH7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFRH7_Msk                    
+#define GPIO_AFRH_AFSEL8_Pos            (0U)                                   
+#define GPIO_AFRH_AFSEL8_Msk            (0xFU << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL9_Pos            (4U)                                   
+#define GPIO_AFRH_AFSEL9_Msk            (0xFU << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL10_Pos           (8U)                                   
+#define GPIO_AFRH_AFSEL10_Msk           (0xFU << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10               GPIO_AFRH_AFSEL10_Msk                    
+#define GPIO_AFRH_AFSEL11_Pos           (12U)                                  
+#define GPIO_AFRH_AFSEL11_Msk           (0xFU << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11               GPIO_AFRH_AFSEL11_Msk                    
+#define GPIO_AFRH_AFSEL12_Pos           (16U)                                  
+#define GPIO_AFRH_AFSEL12_Msk           (0xFU << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12               GPIO_AFRH_AFSEL12_Msk                    
+#define GPIO_AFRH_AFSEL13_Pos           (20U)                                  
+#define GPIO_AFRH_AFSEL13_Msk           (0xFU << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13               GPIO_AFRH_AFSEL13_Msk                    
+#define GPIO_AFRH_AFSEL14_Pos           (24U)                                  
+#define GPIO_AFRH_AFSEL14_Msk           (0xFU << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14               GPIO_AFRH_AFSEL14_Msk                    
+#define GPIO_AFRH_AFSEL15_Pos           (28U)                                  
+#define GPIO_AFRH_AFSEL15_Msk           (0xFU << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15               GPIO_AFRH_AFSEL15_Msk                    
+
+/* Legacy aliases */                  
+#define GPIO_AFRH_AFRH0_Pos             GPIO_AFRH_AFSEL8_Pos
+#define GPIO_AFRH_AFRH0_Msk             GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1_Pos             GPIO_AFRH_AFSEL9_Pos
+#define GPIO_AFRH_AFRH1_Msk             GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2_Pos             GPIO_AFRH_AFSEL10_Pos
+#define GPIO_AFRH_AFRH2_Msk             GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3_Pos             GPIO_AFRH_AFSEL11_Pos
+#define GPIO_AFRH_AFRH3_Msk             GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4_Pos             GPIO_AFRH_AFSEL12_Pos
+#define GPIO_AFRH_AFRH4_Msk             GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5_Pos             GPIO_AFRH_AFSEL13_Pos
+#define GPIO_AFRH_AFRH5_Msk             GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6_Pos             GPIO_AFRH_AFSEL14_Pos
+#define GPIO_AFRH_AFRH6_Msk             GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7_Pos             GPIO_AFRH_AFSEL15_Pos
+#define GPIO_AFRH_AFRH7_Msk             GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFSEL15
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                   (0x00000001U)                          
@@ -3094,51 +3144,51 @@
 /*****************  Bit definition for RCC_APB2RSTR register  ****************/
 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)                          
 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
 #define RCC_APB2RSTR_ADCRST_Pos                  (9U)                          
 #define RCC_APB2RSTR_ADCRST_Msk                  (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC clock reset */
+#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC reset */
 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)                         
 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)                         
 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
 #define RCC_APB2RSTR_USART1RST_Pos               (14U)                         
 #define RCC_APB2RSTR_USART1RST_Msk               (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 clock reset */
+#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)                         
 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)                         
 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
 #define RCC_APB2RSTR_DBGMCURST_Pos               (22U)                         
 #define RCC_APB2RSTR_DBGMCURST_Msk               (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU clock reset */
-
-/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU reset */
+
+/*!< Old ADC1 reset bit definition maintained for legacy purpose */
 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST          
 
 /*****************  Bit definition for RCC_APB1RSTR register  ****************/
 #define RCC_APB1RSTR_TIM2RST_Pos                 (0U)                          
 #define RCC_APB1RSTR_TIM2RST_Msk                 (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)                          
 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
 #define RCC_APB1RSTR_TIM14RST_Pos                (8U)                          
 #define RCC_APB1RSTR_TIM14RST_Msk                (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
-#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 reset */
 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)                         
 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)                         
 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)                         
 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR clock reset */
+#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
 
 /******************  Bit definition for RCC_AHBENR register  *****************/
 #define RCC_AHBENR_DMAEN_Pos                     (0U)                          
@@ -3297,16 +3347,16 @@
 /*******************  Bit definition for RCC_AHBRSTR register  ***************/
 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)                         
 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
-#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)                         
 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
-#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)                         
 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
-#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)                         
 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
-#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
 
 /*******************  Bit definition for RCC_CFGR2 register  *****************/
 /*!< PREDIV configuration */
@@ -3489,9 +3539,9 @@
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP_Pos               (18U)                                     
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -3523,6 +3573,11 @@
 #define RTC_CR_TSEDGE_Msk            (0x1U << RTC_CR_TSEDGE_Pos)               /*!< 0x00000008 */
 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk                         
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  *****************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
@@ -5564,6 +5619,9 @@
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
   ((INSTANCE) == TIM14)
 
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+  ((INSTANCE) == TIM1)
+
 /*********************** UART Instances : IRDA mode ***************************/
 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS STM32F0xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -112,11 +110,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.3
   */
 #define __STM32F0_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
 #define __STM32F0_DEVICE_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F0_DEVICE_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F0_DEVICE_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32F0_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F0_DEVICE_VERSION        ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
                                         |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c	Wed Jan 17 15:23:54 2018 +0000
@@ -213,7 +213,6 @@
     RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
     RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
     RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
     RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
     RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.  
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.s	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f042x6.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.2
-;* Date               : 26-June-2015
 ;* Description        : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.s	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f042x6.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.2
-;* Date               : 26-June-2015
 ;* Description        : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.s	Wed Jan 17 15:23:54 2018 +0000
@@ -2,9 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f042x6.s
   * @author    MCD Application Team
-  * @version   V2.2.2
-  * @date      26-June-2015
-  * @brief     STM32F042x4/STM32F042x6 devices vector table for Atollic TrueSTUDIO toolchain.
+  * @brief     STM32F042x4/STM32F042x6 devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -55,6 +53,10 @@
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
 
 /**
  * @brief  This is the code that gets called when the processor first
@@ -78,8 +80,6 @@
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
-    MOVS R1, #0
-    MOVS R2, #1
     CMP R1, R2
     BNE ApplicationStart
 
@@ -96,21 +96,35 @@
 
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
-  movs r1, #0
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
   b LoopCopyDataInit
 
 CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
 
 LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
+  adds r4, r0, r3
+  cmp r4, r1
   bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.s	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.s	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f042x6.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.2
-;* Date               : 26-June-2015
 ;* Description        : STM32F042x4/STM32F042x6 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,8 +13,6 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h	Wed Jan 17 15:23:54 2018 +0000
@@ -45,11 +45,11 @@
 
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
-#define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
-#define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
 
 #define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f042x6.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32F0xx devices.            
@@ -6496,56 +6494,108 @@
 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos             (0U)                                   
-#define GPIO_AFRL_AFRL0_Msk             (0xFU << GPIO_AFRL_AFRL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFRL0_Msk                    
-#define GPIO_AFRL_AFRL1_Pos             (4U)                                   
-#define GPIO_AFRL_AFRL1_Msk             (0xFU << GPIO_AFRL_AFRL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFRL1_Msk                    
-#define GPIO_AFRL_AFRL2_Pos             (8U)                                   
-#define GPIO_AFRL_AFRL2_Msk             (0xFU << GPIO_AFRL_AFRL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFRL2_Msk                    
-#define GPIO_AFRL_AFRL3_Pos             (12U)                                  
-#define GPIO_AFRL_AFRL3_Msk             (0xFU << GPIO_AFRL_AFRL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFRL3_Msk                    
-#define GPIO_AFRL_AFRL4_Pos             (16U)                                  
-#define GPIO_AFRL_AFRL4_Msk             (0xFU << GPIO_AFRL_AFRL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFRL4_Msk                    
-#define GPIO_AFRL_AFRL5_Pos             (20U)                                  
-#define GPIO_AFRL_AFRL5_Msk             (0xFU << GPIO_AFRL_AFRL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFRL5_Msk                    
-#define GPIO_AFRL_AFRL6_Pos             (24U)                                  
-#define GPIO_AFRL_AFRL6_Msk             (0xFU << GPIO_AFRL_AFRL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFRL6_Msk                    
-#define GPIO_AFRL_AFRL7_Pos             (28U)                                  
-#define GPIO_AFRL_AFRL7_Msk             (0xFU << GPIO_AFRL_AFRL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFRL7_Msk                    
-
+#define GPIO_AFRL_AFSEL0_Pos            (0U)                                   
+#define GPIO_AFRL_AFSEL0_Msk            (0xFU << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL1_Pos            (4U)                                   
+#define GPIO_AFRL_AFSEL1_Msk            (0xFU << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL2_Pos            (8U)                                   
+#define GPIO_AFRL_AFSEL2_Msk            (0xFU << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL3_Pos            (12U)                                  
+#define GPIO_AFRL_AFSEL3_Msk            (0xFU << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL4_Pos            (16U)                                  
+#define GPIO_AFRL_AFSEL4_Msk            (0xFU << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL5_Pos            (20U)                                  
+#define GPIO_AFRL_AFSEL5_Msk            (0xFU << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL6_Pos            (24U)                                  
+#define GPIO_AFRL_AFSEL6_Msk            (0xFU << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL7_Pos            (28U)                                  
+#define GPIO_AFRL_AFSEL7_Msk            (0xFU << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                GPIO_AFRL_AFSEL7_Msk  
+
+/* Legacy aliases */                  
+#define GPIO_AFRL_AFRL0_Pos             GPIO_AFRL_AFSEL0_Pos                                  
+#define GPIO_AFRL_AFRL0_Msk             GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1_Pos             GPIO_AFRL_AFSEL1_Pos
+#define GPIO_AFRL_AFRL1_Msk             GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2_Pos             GPIO_AFRL_AFSEL2_Pos
+#define GPIO_AFRL_AFRL2_Msk             GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3_Pos             GPIO_AFRL_AFSEL3_Pos
+#define GPIO_AFRL_AFRL3_Msk             GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4_Pos             GPIO_AFRL_AFSEL4_Pos
+#define GPIO_AFRL_AFRL4_Msk             GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5_Pos             GPIO_AFRL_AFSEL5_Pos
+#define GPIO_AFRL_AFRL5_Msk             GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6_Pos             GPIO_AFRL_AFSEL6_Pos
+#define GPIO_AFRL_AFRL6_Msk             GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7_Pos             GPIO_AFRL_AFSEL7_Pos
+#define GPIO_AFRL_AFRL7_Msk             GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFSEL7
+ 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos             (0U)                                   
-#define GPIO_AFRH_AFRH0_Msk             (0xFU << GPIO_AFRH_AFRH0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFRH0_Msk                    
-#define GPIO_AFRH_AFRH1_Pos             (4U)                                   
-#define GPIO_AFRH_AFRH1_Msk             (0xFU << GPIO_AFRH_AFRH1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFRH1_Msk                    
-#define GPIO_AFRH_AFRH2_Pos             (8U)                                   
-#define GPIO_AFRH_AFRH2_Msk             (0xFU << GPIO_AFRH_AFRH2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFRH2_Msk                    
-#define GPIO_AFRH_AFRH3_Pos             (12U)                                  
-#define GPIO_AFRH_AFRH3_Msk             (0xFU << GPIO_AFRH_AFRH3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFRH3_Msk                    
-#define GPIO_AFRH_AFRH4_Pos             (16U)                                  
-#define GPIO_AFRH_AFRH4_Msk             (0xFU << GPIO_AFRH_AFRH4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFRH4_Msk                    
-#define GPIO_AFRH_AFRH5_Pos             (20U)                                  
-#define GPIO_AFRH_AFRH5_Msk             (0xFU << GPIO_AFRH_AFRH5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFRH5_Msk                    
-#define GPIO_AFRH_AFRH6_Pos             (24U)                                  
-#define GPIO_AFRH_AFRH6_Msk             (0xFU << GPIO_AFRH_AFRH6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFRH6_Msk                    
-#define GPIO_AFRH_AFRH7_Pos             (28U)                                  
-#define GPIO_AFRH_AFRH7_Msk             (0xFU << GPIO_AFRH_AFRH7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFRH7_Msk                    
+#define GPIO_AFRH_AFSEL8_Pos            (0U)                                   
+#define GPIO_AFRH_AFSEL8_Msk            (0xFU << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL9_Pos            (4U)                                   
+#define GPIO_AFRH_AFSEL9_Msk            (0xFU << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL10_Pos           (8U)                                   
+#define GPIO_AFRH_AFSEL10_Msk           (0xFU << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10               GPIO_AFRH_AFSEL10_Msk                    
+#define GPIO_AFRH_AFSEL11_Pos           (12U)                                  
+#define GPIO_AFRH_AFSEL11_Msk           (0xFU << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11               GPIO_AFRH_AFSEL11_Msk                    
+#define GPIO_AFRH_AFSEL12_Pos           (16U)                                  
+#define GPIO_AFRH_AFSEL12_Msk           (0xFU << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12               GPIO_AFRH_AFSEL12_Msk                    
+#define GPIO_AFRH_AFSEL13_Pos           (20U)                                  
+#define GPIO_AFRH_AFSEL13_Msk           (0xFU << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13               GPIO_AFRH_AFSEL13_Msk                    
+#define GPIO_AFRH_AFSEL14_Pos           (24U)                                  
+#define GPIO_AFRH_AFSEL14_Msk           (0xFU << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14               GPIO_AFRH_AFSEL14_Msk                    
+#define GPIO_AFRH_AFSEL15_Pos           (28U)                                  
+#define GPIO_AFRH_AFSEL15_Msk           (0xFU << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15               GPIO_AFRH_AFSEL15_Msk                    
+
+/* Legacy aliases */                  
+#define GPIO_AFRH_AFRH0_Pos             GPIO_AFRH_AFSEL8_Pos
+#define GPIO_AFRH_AFRH0_Msk             GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1_Pos             GPIO_AFRH_AFSEL9_Pos
+#define GPIO_AFRH_AFRH1_Msk             GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2_Pos             GPIO_AFRH_AFSEL10_Pos
+#define GPIO_AFRH_AFRH2_Msk             GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3_Pos             GPIO_AFRH_AFSEL11_Pos
+#define GPIO_AFRH_AFRH3_Msk             GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4_Pos             GPIO_AFRH_AFSEL12_Pos
+#define GPIO_AFRH_AFRH4_Msk             GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5_Pos             GPIO_AFRH_AFSEL13_Pos
+#define GPIO_AFRH_AFRH5_Msk             GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6_Pos             GPIO_AFRH_AFSEL14_Pos
+#define GPIO_AFRH_AFRH6_Msk             GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7_Pos             GPIO_AFRH_AFSEL15_Pos
+#define GPIO_AFRH_AFRH7_Msk             GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFSEL15
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                   (0x00000001U)                          
@@ -7264,69 +7314,69 @@
 /*****************  Bit definition for RCC_APB2RSTR register  ****************/
 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)                          
 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
 #define RCC_APB2RSTR_ADCRST_Pos                  (9U)                          
 #define RCC_APB2RSTR_ADCRST_Msk                  (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC clock reset */
+#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC reset */
 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)                         
 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)                         
 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
 #define RCC_APB2RSTR_USART1RST_Pos               (14U)                         
 #define RCC_APB2RSTR_USART1RST_Msk               (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 clock reset */
+#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)                         
 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)                         
 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
 #define RCC_APB2RSTR_DBGMCURST_Pos               (22U)                         
 #define RCC_APB2RSTR_DBGMCURST_Msk               (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU clock reset */
-
-/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU reset */
+
+/*!< Old ADC1 reset bit definition maintained for legacy purpose */
 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST          
 
 /*****************  Bit definition for RCC_APB1RSTR register  ****************/
 #define RCC_APB1RSTR_TIM2RST_Pos                 (0U)                          
 #define RCC_APB1RSTR_TIM2RST_Msk                 (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)                          
 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
 #define RCC_APB1RSTR_TIM14RST_Pos                (8U)                          
 #define RCC_APB1RSTR_TIM14RST_Msk                (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
-#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 reset */
 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)                         
 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
 #define RCC_APB1RSTR_SPI2RST_Pos                 (14U)                         
 #define RCC_APB1RSTR_SPI2RST_Msk                 (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
 #define RCC_APB1RSTR_USART2RST_Pos               (17U)                         
 #define RCC_APB1RSTR_USART2RST_Msk               (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)                         
 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
 #define RCC_APB1RSTR_USBRST_Pos                  (23U)                         
 #define RCC_APB1RSTR_USBRST_Msk                  (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                      RCC_APB1RSTR_USBRST_Msk       /*!< USB clock reset */
+#define RCC_APB1RSTR_USBRST                      RCC_APB1RSTR_USBRST_Msk       /*!< USB reset */
 #define RCC_APB1RSTR_CANRST_Pos                  (25U)                         
 #define RCC_APB1RSTR_CANRST_Msk                  (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
-#define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN clock reset */
+#define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN reset */
 #define RCC_APB1RSTR_CRSRST_Pos                  (27U)                         
 #define RCC_APB1RSTR_CRSRST_Msk                  (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST                      RCC_APB1RSTR_CRSRST_Msk       /*!< CRS clock reset */
+#define RCC_APB1RSTR_CRSRST                      RCC_APB1RSTR_CRSRST_Msk       /*!< CRS reset */
 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)                         
 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR clock reset */
+#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
 #define RCC_APB1RSTR_CECRST_Pos                  (30U)                         
 #define RCC_APB1RSTR_CECRST_Msk                  (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
-#define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC clock reset */
+#define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC reset */
 
 /******************  Bit definition for RCC_AHBENR register  *****************/
 #define RCC_AHBENR_DMAEN_Pos                     (0U)                          
@@ -7506,22 +7556,22 @@
 /*******************  Bit definition for RCC_AHBRSTR register  ***************/
 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)                         
 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
-#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)                         
 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
-#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)                         
 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
-#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)                         
 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
-#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
 #define RCC_AHBRSTR_TSCRST_Pos                   (24U)                         
 #define RCC_AHBRSTR_TSCRST_Msk                   (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
-#define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS clock reset */
+#define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS reset */
 
 /* Old Bit definition maintained for legacy purpose */
-#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS reset */
 
 /*******************  Bit definition for RCC_CFGR2 register  *****************/
 /*!< PREDIV configuration */
@@ -7733,9 +7783,9 @@
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP_Pos               (18U)                                     
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -7767,6 +7817,11 @@
 #define RTC_CR_TSEDGE_Msk            (0x1U << RTC_CR_TSEDGE_Pos)               /*!< 0x00000008 */
 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk                         
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  *****************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
@@ -10528,6 +10583,9 @@
   (((INSTANCE) == TIM1)    || \
    ((INSTANCE) == TIM14))
 
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+  ((INSTANCE) == TIM1)
+
 /****************************** TSC Instances *********************************/
 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS STM32F0xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -112,11 +110,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.3
   */
 #define __STM32F0_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
 #define __STM32F0_DEVICE_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F0_DEVICE_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F0_DEVICE_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32F0_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F0_DEVICE_VERSION        ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
                                         |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.  
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f070xb.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 05-December-2014
 ;* Description        : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f070xb.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 05-December-2014
 ;* Description        : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S	Wed Jan 17 15:23:54 2018 +0000
@@ -2,9 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f070xb.s
   * @author    MCD Application Team
-  * @version   V2.2.0
-  * @date      05-December-2014
-  * @brief     STM32F070xb/STM32F070x8 devices vector table for Atollic TrueSTUDIO toolchain.
+  * @brief     STM32F070xb/STM32F070x8 devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -55,7 +53,10 @@
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
-
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
 
   .section .text.Reset_Handler
   .weak Reset_Handler
@@ -65,21 +66,6 @@
   mov   sp, r0          /* set stack pointer */
 
 /* Copy the data segment initializers from flash to SRAM */
-  // Load from _sidata -> _sdata through _edata
-  // _sidata has a vma = lma in flash at the end of .text
-  // _sdata has a lma in flash but a vma of ram, so here we move it from where
-  // it was loaded (lma) into where it will be accessed (vma).
-  // Register Schema:
-  //  r0 = _sdata, r1 = _edata, r2 = _sidata
-  //  r3 = index (goes from 0 -> _sdata - _edata)
-  //  r4 = temp var for *(_sidata + r3) or (_sdata + r3)
-  // This is all equivalent to this C:
-  //  int index = 0;
-  //  extern uint32_t *_sdata, *_sidata;
-  //  while (_sdata + index < _edata) {
-  //    *_sdata[index] = *_sidata[index];
-  //    index += 1;
-  //  }
   ldr r0, =_sdata
   ldr r1, =_edata
   ldr r2, =_sidata
@@ -92,16 +78,28 @@
   adds r3, r3, #4
 
 LoopCopyDataInit:
-  // while (_sdata + r3 < _edata)
   adds r4, r0, r3
-  // if (r4 < r1) branch to CopyDataInit
   cmp r4, r1
   bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
 
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
-
+/* Call static constructors */
+  // bl __libc_init_array
 /* Call the application's entry point.*/
 //  bl main
   bl _start

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f070xb.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 05-December-2014
 ;* Description        : STM32F070xB devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,8 +13,6 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h	Wed Jan 17 15:23:54 2018 +0000
@@ -46,11 +46,11 @@
 #define TIM_MST         TIM1
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
-#define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_RCC     __HAL_RCC_TIM1_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
-#define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM1_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM1_RELEASE_RESET()
 
 #define TIM_MST_16BIT  1 // 1=16-bit timer, 0=32-bit timer
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f070xb.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32F0xx devices.            
@@ -2396,56 +2394,108 @@
 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos             (0U)                                   
-#define GPIO_AFRL_AFRL0_Msk             (0xFU << GPIO_AFRL_AFRL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFRL0_Msk                    
-#define GPIO_AFRL_AFRL1_Pos             (4U)                                   
-#define GPIO_AFRL_AFRL1_Msk             (0xFU << GPIO_AFRL_AFRL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFRL1_Msk                    
-#define GPIO_AFRL_AFRL2_Pos             (8U)                                   
-#define GPIO_AFRL_AFRL2_Msk             (0xFU << GPIO_AFRL_AFRL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFRL2_Msk                    
-#define GPIO_AFRL_AFRL3_Pos             (12U)                                  
-#define GPIO_AFRL_AFRL3_Msk             (0xFU << GPIO_AFRL_AFRL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFRL3_Msk                    
-#define GPIO_AFRL_AFRL4_Pos             (16U)                                  
-#define GPIO_AFRL_AFRL4_Msk             (0xFU << GPIO_AFRL_AFRL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFRL4_Msk                    
-#define GPIO_AFRL_AFRL5_Pos             (20U)                                  
-#define GPIO_AFRL_AFRL5_Msk             (0xFU << GPIO_AFRL_AFRL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFRL5_Msk                    
-#define GPIO_AFRL_AFRL6_Pos             (24U)                                  
-#define GPIO_AFRL_AFRL6_Msk             (0xFU << GPIO_AFRL_AFRL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFRL6_Msk                    
-#define GPIO_AFRL_AFRL7_Pos             (28U)                                  
-#define GPIO_AFRL_AFRL7_Msk             (0xFU << GPIO_AFRL_AFRL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFRL7_Msk                    
-
+#define GPIO_AFRL_AFSEL0_Pos            (0U)                                   
+#define GPIO_AFRL_AFSEL0_Msk            (0xFU << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL1_Pos            (4U)                                   
+#define GPIO_AFRL_AFSEL1_Msk            (0xFU << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL2_Pos            (8U)                                   
+#define GPIO_AFRL_AFSEL2_Msk            (0xFU << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL3_Pos            (12U)                                  
+#define GPIO_AFRL_AFSEL3_Msk            (0xFU << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL4_Pos            (16U)                                  
+#define GPIO_AFRL_AFSEL4_Msk            (0xFU << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL5_Pos            (20U)                                  
+#define GPIO_AFRL_AFSEL5_Msk            (0xFU << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL6_Pos            (24U)                                  
+#define GPIO_AFRL_AFSEL6_Msk            (0xFU << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL7_Pos            (28U)                                  
+#define GPIO_AFRL_AFSEL7_Msk            (0xFU << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                GPIO_AFRL_AFSEL7_Msk  
+
+/* Legacy aliases */                  
+#define GPIO_AFRL_AFRL0_Pos             GPIO_AFRL_AFSEL0_Pos                                  
+#define GPIO_AFRL_AFRL0_Msk             GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1_Pos             GPIO_AFRL_AFSEL1_Pos
+#define GPIO_AFRL_AFRL1_Msk             GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2_Pos             GPIO_AFRL_AFSEL2_Pos
+#define GPIO_AFRL_AFRL2_Msk             GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3_Pos             GPIO_AFRL_AFSEL3_Pos
+#define GPIO_AFRL_AFRL3_Msk             GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4_Pos             GPIO_AFRL_AFSEL4_Pos
+#define GPIO_AFRL_AFRL4_Msk             GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5_Pos             GPIO_AFRL_AFSEL5_Pos
+#define GPIO_AFRL_AFRL5_Msk             GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6_Pos             GPIO_AFRL_AFSEL6_Pos
+#define GPIO_AFRL_AFRL6_Msk             GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7_Pos             GPIO_AFRL_AFSEL7_Pos
+#define GPIO_AFRL_AFRL7_Msk             GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFSEL7
+ 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos             (0U)                                   
-#define GPIO_AFRH_AFRH0_Msk             (0xFU << GPIO_AFRH_AFRH0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFRH0_Msk                    
-#define GPIO_AFRH_AFRH1_Pos             (4U)                                   
-#define GPIO_AFRH_AFRH1_Msk             (0xFU << GPIO_AFRH_AFRH1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFRH1_Msk                    
-#define GPIO_AFRH_AFRH2_Pos             (8U)                                   
-#define GPIO_AFRH_AFRH2_Msk             (0xFU << GPIO_AFRH_AFRH2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFRH2_Msk                    
-#define GPIO_AFRH_AFRH3_Pos             (12U)                                  
-#define GPIO_AFRH_AFRH3_Msk             (0xFU << GPIO_AFRH_AFRH3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFRH3_Msk                    
-#define GPIO_AFRH_AFRH4_Pos             (16U)                                  
-#define GPIO_AFRH_AFRH4_Msk             (0xFU << GPIO_AFRH_AFRH4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFRH4_Msk                    
-#define GPIO_AFRH_AFRH5_Pos             (20U)                                  
-#define GPIO_AFRH_AFRH5_Msk             (0xFU << GPIO_AFRH_AFRH5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFRH5_Msk                    
-#define GPIO_AFRH_AFRH6_Pos             (24U)                                  
-#define GPIO_AFRH_AFRH6_Msk             (0xFU << GPIO_AFRH_AFRH6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFRH6_Msk                    
-#define GPIO_AFRH_AFRH7_Pos             (28U)                                  
-#define GPIO_AFRH_AFRH7_Msk             (0xFU << GPIO_AFRH_AFRH7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFRH7_Msk                    
+#define GPIO_AFRH_AFSEL8_Pos            (0U)                                   
+#define GPIO_AFRH_AFSEL8_Msk            (0xFU << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL9_Pos            (4U)                                   
+#define GPIO_AFRH_AFSEL9_Msk            (0xFU << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL10_Pos           (8U)                                   
+#define GPIO_AFRH_AFSEL10_Msk           (0xFU << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10               GPIO_AFRH_AFSEL10_Msk                    
+#define GPIO_AFRH_AFSEL11_Pos           (12U)                                  
+#define GPIO_AFRH_AFSEL11_Msk           (0xFU << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11               GPIO_AFRH_AFSEL11_Msk                    
+#define GPIO_AFRH_AFSEL12_Pos           (16U)                                  
+#define GPIO_AFRH_AFSEL12_Msk           (0xFU << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12               GPIO_AFRH_AFSEL12_Msk                    
+#define GPIO_AFRH_AFSEL13_Pos           (20U)                                  
+#define GPIO_AFRH_AFSEL13_Msk           (0xFU << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13               GPIO_AFRH_AFSEL13_Msk                    
+#define GPIO_AFRH_AFSEL14_Pos           (24U)                                  
+#define GPIO_AFRH_AFSEL14_Msk           (0xFU << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14               GPIO_AFRH_AFSEL14_Msk                    
+#define GPIO_AFRH_AFSEL15_Pos           (28U)                                  
+#define GPIO_AFRH_AFSEL15_Msk           (0xFU << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15               GPIO_AFRH_AFSEL15_Msk                    
+
+/* Legacy aliases */                  
+#define GPIO_AFRH_AFRH0_Pos             GPIO_AFRH_AFSEL8_Pos
+#define GPIO_AFRH_AFRH0_Msk             GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1_Pos             GPIO_AFRH_AFSEL9_Pos
+#define GPIO_AFRH_AFRH1_Msk             GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2_Pos             GPIO_AFRH_AFSEL10_Pos
+#define GPIO_AFRH_AFRH2_Msk             GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3_Pos             GPIO_AFRH_AFSEL11_Pos
+#define GPIO_AFRH_AFRH3_Msk             GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4_Pos             GPIO_AFRH_AFSEL12_Pos
+#define GPIO_AFRH_AFRH4_Msk             GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5_Pos             GPIO_AFRH_AFSEL13_Pos
+#define GPIO_AFRH_AFRH5_Msk             GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6_Pos             GPIO_AFRH_AFSEL14_Pos
+#define GPIO_AFRH_AFRH6_Msk             GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7_Pos             GPIO_AFRH_AFSEL15_Pos
+#define GPIO_AFRH_AFRH7_Msk             GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFSEL15
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                   (0x00000001U)                          
@@ -3120,75 +3170,75 @@
 /*****************  Bit definition for RCC_APB2RSTR register  ****************/
 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)                          
 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
 #define RCC_APB2RSTR_ADCRST_Pos                  (9U)                          
 #define RCC_APB2RSTR_ADCRST_Msk                  (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC clock reset */
+#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC reset */
 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)                         
 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)                         
 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
 #define RCC_APB2RSTR_USART1RST_Pos               (14U)                         
 #define RCC_APB2RSTR_USART1RST_Msk               (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 clock reset */
+#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
 #define RCC_APB2RSTR_TIM15RST_Pos                (16U)                         
 #define RCC_APB2RSTR_TIM15RST_Msk                (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
-#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 reset */
 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)                         
 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)                         
 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
 #define RCC_APB2RSTR_DBGMCURST_Pos               (22U)                         
 #define RCC_APB2RSTR_DBGMCURST_Msk               (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU clock reset */
-
-/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU reset */
+
+/*!< Old ADC1 reset bit definition maintained for legacy purpose */
 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST          
 
 /*****************  Bit definition for RCC_APB1RSTR register  ****************/
 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)                          
 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
 #define RCC_APB1RSTR_TIM6RST_Pos                 (4U)                          
 #define RCC_APB1RSTR_TIM6RST_Msk                 (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 reset */
 #define RCC_APB1RSTR_TIM7RST_Pos                 (5U)                          
 #define RCC_APB1RSTR_TIM7RST_Msk                 (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 clock reset */
+#define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 reset */
 #define RCC_APB1RSTR_TIM14RST_Pos                (8U)                          
 #define RCC_APB1RSTR_TIM14RST_Msk                (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
-#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 reset */
 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)                         
 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
 #define RCC_APB1RSTR_SPI2RST_Pos                 (14U)                         
 #define RCC_APB1RSTR_SPI2RST_Msk                 (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
 #define RCC_APB1RSTR_USART2RST_Pos               (17U)                         
 #define RCC_APB1RSTR_USART2RST_Msk               (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
 #define RCC_APB1RSTR_USART3RST_Pos               (18U)                         
 #define RCC_APB1RSTR_USART3RST_Msk               (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 clock reset */
+#define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 reset */
 #define RCC_APB1RSTR_USART4RST_Pos               (19U)                         
 #define RCC_APB1RSTR_USART4RST_Msk               (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_USART4RST                   RCC_APB1RSTR_USART4RST_Msk    /*!< USART 4 clock reset */
+#define RCC_APB1RSTR_USART4RST                   RCC_APB1RSTR_USART4RST_Msk    /*!< USART 4 reset */
 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)                         
 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
 #define RCC_APB1RSTR_I2C2RST_Pos                 (22U)                         
 #define RCC_APB1RSTR_I2C2RST_Msk                 (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 reset */
 #define RCC_APB1RSTR_USBRST_Pos                  (23U)                         
 #define RCC_APB1RSTR_USBRST_Msk                  (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                      RCC_APB1RSTR_USBRST_Msk       /*!< USB clock reset */
+#define RCC_APB1RSTR_USBRST                      RCC_APB1RSTR_USBRST_Msk       /*!< USB reset */
 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)                         
 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR clock reset */
+#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
 
 /******************  Bit definition for RCC_AHBENR register  *****************/
 #define RCC_AHBENR_DMAEN_Pos                     (0U)                          
@@ -3373,19 +3423,19 @@
 /*******************  Bit definition for RCC_AHBRSTR register  ***************/
 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)                         
 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
-#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)                         
 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
-#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)                         
 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
-#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
 #define RCC_AHBRSTR_GPIODRST_Pos                 (20U)                         
 #define RCC_AHBRSTR_GPIODRST_Msk                 (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
-#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD reset */
 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)                         
 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
-#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
 
 /*******************  Bit definition for RCC_CFGR2 register  *****************/
 /*!< PREDIV configuration */
@@ -3577,9 +3627,9 @@
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP_Pos               (18U)                                     
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -3623,6 +3673,11 @@
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  *****************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
@@ -5669,6 +5724,9 @@
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
   ((INSTANCE) == TIM14)
 
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+  ((INSTANCE) == TIM1)
+
 /******************** USART Instances : Synchronous mode **********************/
 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                      ((INSTANCE) == USART2) || \

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS STM32F0xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -112,11 +110,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.3
   */
 #define __STM32F0_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
 #define __STM32F0_DEVICE_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F0_DEVICE_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F0_DEVICE_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32F0_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F0_DEVICE_VERSION        ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
                                         |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c	Wed Jan 17 15:23:54 2018 +0000
@@ -216,7 +216,6 @@
     RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
     RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
     RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
     RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
     RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI;

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.  
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f072xb.s
 ;* Author             : MCD Application Team
-;* Version            : V2.0.0
-;* Date               : 20-May-2014
 ;* Description        : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_MICRO toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f072xb.s
 ;* Author             : MCD Application Team
-;* Version            : V2.0.0
-;* Date               : 20-May-2014
 ;* Description        : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_STD toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S	Wed Jan 17 15:23:54 2018 +0000
@@ -2,9 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f072xb.s
   * @author    MCD Application Team
-  * @version   V2.1.0
-  * @date      03-Oct-2014
-  * @brief     STM32F072x8/STM32F072xB devices vector table for Atollic TrueSTUDIO toolchain.
+  * @brief     STM32F072x8/STM32F072xB devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -55,6 +53,10 @@
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
 
   .section .text.Reset_Handler
   .weak Reset_Handler
@@ -64,28 +66,42 @@
   mov   sp, r0          /* set stack pointer */
 
 /* Copy the data segment initializers from flash to SRAM */
-  movs r1, #0
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
   b LoopCopyDataInit
 
 CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
 
 LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
+  adds r4, r0, r3
+  cmp r4, r1
   bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
 
 /* Call the clock system intitialization function.*/
-    bl  SystemInit
+  bl  SystemInit
 /* Call static constructors */
-    //bl __libc_init_array
+  //bl __libc_init_array
 /* Call the application's entry point.*/
-    //bl  main
+  //bl  main
 /**
  * Calling the crt0 'cold-start' entry point. There __libc_init_array is called
  * and when existing hardware_init_hook() and software_init_hook() before 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f072xb.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 03-Oct-2014
 ;* Description        : STM32F072x8/STM32F072xB devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,8 +13,6 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h	Wed Jan 17 15:23:54 2018 +0000
@@ -45,11 +45,11 @@
    
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
-#define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
-#define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
 
 #define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f072xb.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32F0xx devices.            
@@ -6934,56 +6932,108 @@
 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos             (0U)                                   
-#define GPIO_AFRL_AFRL0_Msk             (0xFU << GPIO_AFRL_AFRL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFRL0_Msk                    
-#define GPIO_AFRL_AFRL1_Pos             (4U)                                   
-#define GPIO_AFRL_AFRL1_Msk             (0xFU << GPIO_AFRL_AFRL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFRL1_Msk                    
-#define GPIO_AFRL_AFRL2_Pos             (8U)                                   
-#define GPIO_AFRL_AFRL2_Msk             (0xFU << GPIO_AFRL_AFRL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFRL2_Msk                    
-#define GPIO_AFRL_AFRL3_Pos             (12U)                                  
-#define GPIO_AFRL_AFRL3_Msk             (0xFU << GPIO_AFRL_AFRL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFRL3_Msk                    
-#define GPIO_AFRL_AFRL4_Pos             (16U)                                  
-#define GPIO_AFRL_AFRL4_Msk             (0xFU << GPIO_AFRL_AFRL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFRL4_Msk                    
-#define GPIO_AFRL_AFRL5_Pos             (20U)                                  
-#define GPIO_AFRL_AFRL5_Msk             (0xFU << GPIO_AFRL_AFRL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFRL5_Msk                    
-#define GPIO_AFRL_AFRL6_Pos             (24U)                                  
-#define GPIO_AFRL_AFRL6_Msk             (0xFU << GPIO_AFRL_AFRL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFRL6_Msk                    
-#define GPIO_AFRL_AFRL7_Pos             (28U)                                  
-#define GPIO_AFRL_AFRL7_Msk             (0xFU << GPIO_AFRL_AFRL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFRL7_Msk                    
-
+#define GPIO_AFRL_AFSEL0_Pos            (0U)                                   
+#define GPIO_AFRL_AFSEL0_Msk            (0xFU << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL1_Pos            (4U)                                   
+#define GPIO_AFRL_AFSEL1_Msk            (0xFU << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL2_Pos            (8U)                                   
+#define GPIO_AFRL_AFSEL2_Msk            (0xFU << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL3_Pos            (12U)                                  
+#define GPIO_AFRL_AFSEL3_Msk            (0xFU << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL4_Pos            (16U)                                  
+#define GPIO_AFRL_AFSEL4_Msk            (0xFU << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL5_Pos            (20U)                                  
+#define GPIO_AFRL_AFSEL5_Msk            (0xFU << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL6_Pos            (24U)                                  
+#define GPIO_AFRL_AFSEL6_Msk            (0xFU << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL7_Pos            (28U)                                  
+#define GPIO_AFRL_AFSEL7_Msk            (0xFU << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                GPIO_AFRL_AFSEL7_Msk  
+
+/* Legacy aliases */                  
+#define GPIO_AFRL_AFRL0_Pos             GPIO_AFRL_AFSEL0_Pos                                  
+#define GPIO_AFRL_AFRL0_Msk             GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1_Pos             GPIO_AFRL_AFSEL1_Pos
+#define GPIO_AFRL_AFRL1_Msk             GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2_Pos             GPIO_AFRL_AFSEL2_Pos
+#define GPIO_AFRL_AFRL2_Msk             GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3_Pos             GPIO_AFRL_AFSEL3_Pos
+#define GPIO_AFRL_AFRL3_Msk             GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4_Pos             GPIO_AFRL_AFSEL4_Pos
+#define GPIO_AFRL_AFRL4_Msk             GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5_Pos             GPIO_AFRL_AFSEL5_Pos
+#define GPIO_AFRL_AFRL5_Msk             GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6_Pos             GPIO_AFRL_AFSEL6_Pos
+#define GPIO_AFRL_AFRL6_Msk             GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7_Pos             GPIO_AFRL_AFSEL7_Pos
+#define GPIO_AFRL_AFRL7_Msk             GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFSEL7
+ 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos             (0U)                                   
-#define GPIO_AFRH_AFRH0_Msk             (0xFU << GPIO_AFRH_AFRH0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFRH0_Msk                    
-#define GPIO_AFRH_AFRH1_Pos             (4U)                                   
-#define GPIO_AFRH_AFRH1_Msk             (0xFU << GPIO_AFRH_AFRH1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFRH1_Msk                    
-#define GPIO_AFRH_AFRH2_Pos             (8U)                                   
-#define GPIO_AFRH_AFRH2_Msk             (0xFU << GPIO_AFRH_AFRH2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFRH2_Msk                    
-#define GPIO_AFRH_AFRH3_Pos             (12U)                                  
-#define GPIO_AFRH_AFRH3_Msk             (0xFU << GPIO_AFRH_AFRH3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFRH3_Msk                    
-#define GPIO_AFRH_AFRH4_Pos             (16U)                                  
-#define GPIO_AFRH_AFRH4_Msk             (0xFU << GPIO_AFRH_AFRH4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFRH4_Msk                    
-#define GPIO_AFRH_AFRH5_Pos             (20U)                                  
-#define GPIO_AFRH_AFRH5_Msk             (0xFU << GPIO_AFRH_AFRH5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFRH5_Msk                    
-#define GPIO_AFRH_AFRH6_Pos             (24U)                                  
-#define GPIO_AFRH_AFRH6_Msk             (0xFU << GPIO_AFRH_AFRH6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFRH6_Msk                    
-#define GPIO_AFRH_AFRH7_Pos             (28U)                                  
-#define GPIO_AFRH_AFRH7_Msk             (0xFU << GPIO_AFRH_AFRH7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFRH7_Msk                    
+#define GPIO_AFRH_AFSEL8_Pos            (0U)                                   
+#define GPIO_AFRH_AFSEL8_Msk            (0xFU << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL9_Pos            (4U)                                   
+#define GPIO_AFRH_AFSEL9_Msk            (0xFU << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL10_Pos           (8U)                                   
+#define GPIO_AFRH_AFSEL10_Msk           (0xFU << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10               GPIO_AFRH_AFSEL10_Msk                    
+#define GPIO_AFRH_AFSEL11_Pos           (12U)                                  
+#define GPIO_AFRH_AFSEL11_Msk           (0xFU << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11               GPIO_AFRH_AFSEL11_Msk                    
+#define GPIO_AFRH_AFSEL12_Pos           (16U)                                  
+#define GPIO_AFRH_AFSEL12_Msk           (0xFU << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12               GPIO_AFRH_AFSEL12_Msk                    
+#define GPIO_AFRH_AFSEL13_Pos           (20U)                                  
+#define GPIO_AFRH_AFSEL13_Msk           (0xFU << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13               GPIO_AFRH_AFSEL13_Msk                    
+#define GPIO_AFRH_AFSEL14_Pos           (24U)                                  
+#define GPIO_AFRH_AFSEL14_Msk           (0xFU << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14               GPIO_AFRH_AFSEL14_Msk                    
+#define GPIO_AFRH_AFSEL15_Pos           (28U)                                  
+#define GPIO_AFRH_AFSEL15_Msk           (0xFU << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15               GPIO_AFRH_AFSEL15_Msk                    
+
+/* Legacy aliases */                  
+#define GPIO_AFRH_AFRH0_Pos             GPIO_AFRH_AFSEL8_Pos
+#define GPIO_AFRH_AFRH0_Msk             GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1_Pos             GPIO_AFRH_AFSEL9_Pos
+#define GPIO_AFRH_AFRH1_Msk             GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2_Pos             GPIO_AFRH_AFSEL10_Pos
+#define GPIO_AFRH_AFRH2_Msk             GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3_Pos             GPIO_AFRH_AFSEL11_Pos
+#define GPIO_AFRH_AFRH3_Msk             GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4_Pos             GPIO_AFRH_AFSEL12_Pos
+#define GPIO_AFRH_AFRH4_Msk             GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5_Pos             GPIO_AFRH_AFSEL13_Pos
+#define GPIO_AFRH_AFRH5_Msk             GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6_Pos             GPIO_AFRH_AFSEL14_Pos
+#define GPIO_AFRH_AFRH6_Msk             GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7_Pos             GPIO_AFRH_AFSEL15_Pos
+#define GPIO_AFRH_AFRH7_Msk             GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFSEL15
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                   (0x00000001U)                          
@@ -7711,90 +7761,90 @@
 /*****************  Bit definition for RCC_APB2RSTR register  ****************/
 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)                          
 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
 #define RCC_APB2RSTR_ADCRST_Pos                  (9U)                          
 #define RCC_APB2RSTR_ADCRST_Msk                  (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC clock reset */
+#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC reset */
 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)                         
 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)                         
 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
 #define RCC_APB2RSTR_USART1RST_Pos               (14U)                         
 #define RCC_APB2RSTR_USART1RST_Msk               (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 clock reset */
+#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
 #define RCC_APB2RSTR_TIM15RST_Pos                (16U)                         
 #define RCC_APB2RSTR_TIM15RST_Msk                (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
-#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 reset */
 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)                         
 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)                         
 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
 #define RCC_APB2RSTR_DBGMCURST_Pos               (22U)                         
 #define RCC_APB2RSTR_DBGMCURST_Msk               (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU clock reset */
-
-/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU reset */
+
+/*!< Old ADC1 reset bit definition maintained for legacy purpose */
 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST          
 
 /*****************  Bit definition for RCC_APB1RSTR register  ****************/
 #define RCC_APB1RSTR_TIM2RST_Pos                 (0U)                          
 #define RCC_APB1RSTR_TIM2RST_Msk                 (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)                          
 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
 #define RCC_APB1RSTR_TIM6RST_Pos                 (4U)                          
 #define RCC_APB1RSTR_TIM6RST_Msk                 (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 reset */
 #define RCC_APB1RSTR_TIM7RST_Pos                 (5U)                          
 #define RCC_APB1RSTR_TIM7RST_Msk                 (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 clock reset */
+#define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 reset */
 #define RCC_APB1RSTR_TIM14RST_Pos                (8U)                          
 #define RCC_APB1RSTR_TIM14RST_Msk                (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
-#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 reset */
 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)                         
 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
 #define RCC_APB1RSTR_SPI2RST_Pos                 (14U)                         
 #define RCC_APB1RSTR_SPI2RST_Msk                 (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
 #define RCC_APB1RSTR_USART2RST_Pos               (17U)                         
 #define RCC_APB1RSTR_USART2RST_Msk               (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
 #define RCC_APB1RSTR_USART3RST_Pos               (18U)                         
 #define RCC_APB1RSTR_USART3RST_Msk               (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 clock reset */
+#define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 reset */
 #define RCC_APB1RSTR_USART4RST_Pos               (19U)                         
 #define RCC_APB1RSTR_USART4RST_Msk               (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_USART4RST                   RCC_APB1RSTR_USART4RST_Msk    /*!< USART 4 clock reset */
+#define RCC_APB1RSTR_USART4RST                   RCC_APB1RSTR_USART4RST_Msk    /*!< USART 4 reset */
 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)                         
 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
 #define RCC_APB1RSTR_I2C2RST_Pos                 (22U)                         
 #define RCC_APB1RSTR_I2C2RST_Msk                 (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 reset */
 #define RCC_APB1RSTR_USBRST_Pos                  (23U)                         
 #define RCC_APB1RSTR_USBRST_Msk                  (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                      RCC_APB1RSTR_USBRST_Msk       /*!< USB clock reset */
+#define RCC_APB1RSTR_USBRST                      RCC_APB1RSTR_USBRST_Msk       /*!< USB reset */
 #define RCC_APB1RSTR_CANRST_Pos                  (25U)                         
 #define RCC_APB1RSTR_CANRST_Msk                  (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
-#define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN clock reset */
+#define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN reset */
 #define RCC_APB1RSTR_CRSRST_Pos                  (27U)                         
 #define RCC_APB1RSTR_CRSRST_Msk                  (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST                      RCC_APB1RSTR_CRSRST_Msk       /*!< CRS clock reset */
+#define RCC_APB1RSTR_CRSRST                      RCC_APB1RSTR_CRSRST_Msk       /*!< CRS reset */
 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)                         
 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR clock reset */
+#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
 #define RCC_APB1RSTR_DACRST_Pos                  (29U)                         
 #define RCC_APB1RSTR_DACRST_Msk                  (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                      RCC_APB1RSTR_DACRST_Msk       /*!< DAC clock reset */
+#define RCC_APB1RSTR_DACRST                      RCC_APB1RSTR_DACRST_Msk       /*!< DAC reset */
 #define RCC_APB1RSTR_CECRST_Pos                  (30U)                         
 #define RCC_APB1RSTR_CECRST_Msk                  (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
-#define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC clock reset */
+#define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC reset */
 
 /******************  Bit definition for RCC_AHBENR register  *****************/
 #define RCC_AHBENR_DMAEN_Pos                     (0U)                          
@@ -8001,28 +8051,28 @@
 /*******************  Bit definition for RCC_AHBRSTR register  ***************/
 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)                         
 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
-#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)                         
 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
-#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)                         
 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
-#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
 #define RCC_AHBRSTR_GPIODRST_Pos                 (20U)                         
 #define RCC_AHBRSTR_GPIODRST_Msk                 (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
-#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD reset */
 #define RCC_AHBRSTR_GPIOERST_Pos                 (21U)                         
 #define RCC_AHBRSTR_GPIOERST_Msk                 (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
-#define RCC_AHBRSTR_GPIOERST                     RCC_AHBRSTR_GPIOERST_Msk      /*!< GPIOE clock reset */
+#define RCC_AHBRSTR_GPIOERST                     RCC_AHBRSTR_GPIOERST_Msk      /*!< GPIOE reset */
 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)                         
 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
-#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
 #define RCC_AHBRSTR_TSCRST_Pos                   (24U)                         
 #define RCC_AHBRSTR_TSCRST_Msk                   (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
-#define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS clock reset */
+#define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS reset */
 
 /* Old Bit definition maintained for legacy purpose */
-#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS reset */
 
 /*******************  Bit definition for RCC_CFGR2 register  *****************/
 /*!< PREDIV configuration */
@@ -8248,9 +8298,9 @@
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP_Pos               (18U)                                     
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -8294,6 +8344,11 @@
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  *****************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
@@ -11132,6 +11187,9 @@
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
   ((INSTANCE) == TIM14)
 
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+  ((INSTANCE) == TIM1)
+
 /****************************** TSC Instances *********************************/
 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS STM32F0xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -112,11 +110,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.3
   */
 #define __STM32F0_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
 #define __STM32F0_DEVICE_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F0_DEVICE_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F0_DEVICE_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32F0_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F0_DEVICE_VERSION        ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
                                         |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.  
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.S	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,244 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name          : startup_stm32f091xc.s
-;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 03-Oct-2014
-;* Description        : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_MICRO toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM0 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-                
-Stack_Mem       SPACE   Stack_Size
-__initial_sp    EQU     0x20008000 ; Top of RAM (32KB)
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000400
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit    EQU (__initial_sp - Stack_Size)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                   ; Top of Stack
-                DCD     Reset_Handler                  ; Reset Handler
-                DCD     NMI_Handler                    ; NMI Handler
-                DCD     HardFault_Handler              ; Hard Fault Handler
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     SVC_Handler                    ; SVCall Handler
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     PendSV_Handler                 ; PendSV Handler
-                DCD     SysTick_Handler                ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_VDDIO2_IRQHandler          ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TS
-                DCD     DMA1_Ch1_IRQHandler            ; DMA1 Channel 1
-                DCD     DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
-                DCD     DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     TIM14_IRQHandler               ; TIM14
-                DCD     TIM15_IRQHandler               ; TIM15
-                DCD     TIM16_IRQHandler               ; TIM16
-                DCD     TIM17_IRQHandler               ; TIM17
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     USART3_8_IRQHandler            ; USART3, USART4, USART5, USART6, USART7, USART8
-                DCD     CEC_CAN_IRQHandler             ; CEC and CAN
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_VDDIO2_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                 [WEAK]
-                EXPORT  DMA1_Ch1_IRQHandler            [WEAK]
-                EXPORT  DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK]
-                EXPORT  DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
-                EXPORT  TIM1_CC_IRQHandler             [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler                [WEAK]
-                EXPORT  TIM14_IRQHandler               [WEAK]
-                EXPORT  TIM15_IRQHandler               [WEAK]
-                EXPORT  TIM16_IRQHandler               [WEAK]
-                EXPORT  TIM17_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  USART3_8_IRQHandler            [WEAK]
-                EXPORT  CEC_CAN_IRQHandler             [WEAK]
-
-
-WWDG_IRQHandler
-PVD_VDDIO2_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Ch1_IRQHandler
-DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
-DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
-ADC1_COMP_IRQHandler
-TIM1_BRK_UP_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-TIM14_IRQHandler
-TIM15_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_8_IRQHandler
-CEC_CAN_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091xc.S	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,242 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f091xc.s
+;* Author             : MCD Application Team
+;* Description        : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_MICRO toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM0 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+                
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x20008000 ; Top of RAM (32KB)
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit    EQU (__initial_sp - Stack_Size)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                   ; Top of Stack
+                DCD     Reset_Handler                  ; Reset Handler
+                DCD     NMI_Handler                    ; NMI Handler
+                DCD     HardFault_Handler              ; Hard Fault Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     SVC_Handler                    ; SVCall Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     PendSV_Handler                 ; PendSV Handler
+                DCD     SysTick_Handler                ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                ; Window Watchdog
+                DCD     PVD_VDDIO2_IRQHandler          ; PVD through EXTI Line detect
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+                DCD     FLASH_IRQHandler               ; FLASH
+                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+                DCD     TSC_IRQHandler                 ; TS
+                DCD     DMA1_Ch1_IRQHandler            ; DMA1 Channel 1
+                DCD     DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
+                DCD     DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 
+                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                ; TIM2
+                DCD     TIM3_IRQHandler                ; TIM3
+                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
+                DCD     TIM7_IRQHandler                ; TIM7
+                DCD     TIM14_IRQHandler               ; TIM14
+                DCD     TIM15_IRQHandler               ; TIM15
+                DCD     TIM16_IRQHandler               ; TIM16
+                DCD     TIM17_IRQHandler               ; TIM17
+                DCD     I2C1_IRQHandler                ; I2C1
+                DCD     I2C2_IRQHandler                ; I2C2
+                DCD     SPI1_IRQHandler                ; SPI1
+                DCD     SPI2_IRQHandler                ; SPI2
+                DCD     USART1_IRQHandler              ; USART1
+                DCD     USART2_IRQHandler              ; USART2
+                DCD     USART3_8_IRQHandler            ; USART3, USART4, USART5, USART6, USART7, USART8
+                DCD     CEC_CAN_IRQHandler             ; CEC and CAN
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit  
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                [WEAK]
+                EXPORT  PVD_VDDIO2_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler                 [WEAK]
+                EXPORT  FLASH_IRQHandler               [WEAK]
+                EXPORT  RCC_CRS_IRQHandler             [WEAK]
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
+                EXPORT  TSC_IRQHandler                 [WEAK]
+                EXPORT  DMA1_Ch1_IRQHandler            [WEAK]
+                EXPORT  DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK]
+                EXPORT  DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK]
+                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
+                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+                EXPORT  TIM1_CC_IRQHandler             [WEAK]
+                EXPORT  TIM2_IRQHandler                [WEAK]
+                EXPORT  TIM3_IRQHandler                [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler                [WEAK]
+                EXPORT  TIM14_IRQHandler               [WEAK]
+                EXPORT  TIM15_IRQHandler               [WEAK]
+                EXPORT  TIM16_IRQHandler               [WEAK]
+                EXPORT  TIM17_IRQHandler               [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+                EXPORT  USART3_8_IRQHandler            [WEAK]
+                EXPORT  CEC_CAN_IRQHandler             [WEAK]
+
+
+WWDG_IRQHandler
+PVD_VDDIO2_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_CRS_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+TSC_IRQHandler
+DMA1_Ch1_IRQHandler
+DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+ADC1_COMP_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_8_IRQHandler
+CEC_CAN_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091rc.S	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,217 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name          : startup_stm32f091xc.s
-;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 03-Oct-2014
-;* Description        : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_STD toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM0 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*******************************************************************************
-
-__initial_sp    EQU     0x20008000 ; Top of RAM (32KB)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                   ; Top of Stack
-                DCD     Reset_Handler                  ; Reset Handler
-                DCD     NMI_Handler                    ; NMI Handler
-                DCD     HardFault_Handler              ; Hard Fault Handler
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     SVC_Handler                    ; SVCall Handler
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     PendSV_Handler                 ; PendSV Handler
-                DCD     SysTick_Handler                ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_VDDIO2_IRQHandler          ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TS
-                DCD     DMA1_Ch1_IRQHandler            ; DMA1 Channel 1
-                DCD     DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
-                DCD     DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     TIM14_IRQHandler               ; TIM14
-                DCD     TIM15_IRQHandler               ; TIM15
-                DCD     TIM16_IRQHandler               ; TIM16
-                DCD     TIM17_IRQHandler               ; TIM17
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     USART3_8_IRQHandler            ; USART3, USART4, USART5, USART6, USART7, USART8
-                DCD     CEC_CAN_IRQHandler             ; CEC and CAN
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_VDDIO2_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                 [WEAK]
-                EXPORT  DMA1_Ch1_IRQHandler            [WEAK]
-                EXPORT  DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK]
-                EXPORT  DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
-                EXPORT  TIM1_CC_IRQHandler             [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler                [WEAK]
-                EXPORT  TIM14_IRQHandler               [WEAK]
-                EXPORT  TIM15_IRQHandler               [WEAK]
-                EXPORT  TIM16_IRQHandler               [WEAK]
-                EXPORT  TIM17_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  USART3_8_IRQHandler            [WEAK]
-                EXPORT  CEC_CAN_IRQHandler             [WEAK]
-
-
-WWDG_IRQHandler
-PVD_VDDIO2_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Ch1_IRQHandler
-DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
-DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
-ADC1_COMP_IRQHandler
-TIM1_BRK_UP_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-TIM14_IRQHandler
-TIM15_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_8_IRQHandler
-CEC_CAN_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091xc.S	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,215 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f091xc.s
+;* Author             : MCD Application Team
+;* Description        : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_STD toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM0 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+__initial_sp    EQU     0x20008000 ; Top of RAM (32KB)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                   ; Top of Stack
+                DCD     Reset_Handler                  ; Reset Handler
+                DCD     NMI_Handler                    ; NMI Handler
+                DCD     HardFault_Handler              ; Hard Fault Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     SVC_Handler                    ; SVCall Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     PendSV_Handler                 ; PendSV Handler
+                DCD     SysTick_Handler                ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                ; Window Watchdog
+                DCD     PVD_VDDIO2_IRQHandler          ; PVD through EXTI Line detect
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+                DCD     FLASH_IRQHandler               ; FLASH
+                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+                DCD     TSC_IRQHandler                 ; TS
+                DCD     DMA1_Ch1_IRQHandler            ; DMA1 Channel 1
+                DCD     DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
+                DCD     DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 
+                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                ; TIM2
+                DCD     TIM3_IRQHandler                ; TIM3
+                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
+                DCD     TIM7_IRQHandler                ; TIM7
+                DCD     TIM14_IRQHandler               ; TIM14
+                DCD     TIM15_IRQHandler               ; TIM15
+                DCD     TIM16_IRQHandler               ; TIM16
+                DCD     TIM17_IRQHandler               ; TIM17
+                DCD     I2C1_IRQHandler                ; I2C1
+                DCD     I2C2_IRQHandler                ; I2C2
+                DCD     SPI1_IRQHandler                ; SPI1
+                DCD     SPI2_IRQHandler                ; SPI2
+                DCD     USART1_IRQHandler              ; USART1
+                DCD     USART2_IRQHandler              ; USART2
+                DCD     USART3_8_IRQHandler            ; USART3, USART4, USART5, USART6, USART7, USART8
+                DCD     CEC_CAN_IRQHandler             ; CEC and CAN
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit  
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                [WEAK]
+                EXPORT  PVD_VDDIO2_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler                 [WEAK]
+                EXPORT  FLASH_IRQHandler               [WEAK]
+                EXPORT  RCC_CRS_IRQHandler             [WEAK]
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
+                EXPORT  TSC_IRQHandler                 [WEAK]
+                EXPORT  DMA1_Ch1_IRQHandler            [WEAK]
+                EXPORT  DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK]
+                EXPORT  DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK]
+                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
+                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+                EXPORT  TIM1_CC_IRQHandler             [WEAK]
+                EXPORT  TIM2_IRQHandler                [WEAK]
+                EXPORT  TIM3_IRQHandler                [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler                [WEAK]
+                EXPORT  TIM14_IRQHandler               [WEAK]
+                EXPORT  TIM15_IRQHandler               [WEAK]
+                EXPORT  TIM16_IRQHandler               [WEAK]
+                EXPORT  TIM17_IRQHandler               [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+                EXPORT  USART3_8_IRQHandler            [WEAK]
+                EXPORT  CEC_CAN_IRQHandler             [WEAK]
+
+
+WWDG_IRQHandler
+PVD_VDDIO2_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_CRS_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+TSC_IRQHandler
+DMA1_Ch1_IRQHandler
+DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+ADC1_COMP_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_8_IRQHandler
+CEC_CAN_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S	Wed Jan 17 15:23:54 2018 +0000
@@ -2,9 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f091xc.s
   * @author    MCD Application Team
-  * @version   V2.1.0
-  * @date      03-Oct-2014
-  * @brief     STM32F091xC devices vector table for Atollic TrueSTUDIO toolchain.
+  * @brief     STM32F091xC devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -55,6 +53,10 @@
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
 
   .section .text.Reset_Handler
   .weak Reset_Handler
@@ -64,21 +66,35 @@
   mov   sp, r0          /* set stack pointer */
 
 /* Copy the data segment initializers from flash to SRAM */
-  movs r1, #0
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
   b LoopCopyDataInit
 
 CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
 
 LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
+  adds r4, r0, r3
+  cmp r4, r1
   bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
 
 /* Call the clock system intitialization function.*/
     bl  SystemInit

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S	Wed Jan 17 15:23:54 2018 +0000
@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f091xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 03-Oct-2014
 ;* Description        : STM32F091xc/STM32F098xc devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,8 +13,6 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h	Wed Jan 17 15:23:54 2018 +0000
@@ -45,11 +45,11 @@
    
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
-#define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
-#define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
 
 #define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f091xc.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32F0xx devices.            
@@ -7405,56 +7403,108 @@
 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos             (0U)                                   
-#define GPIO_AFRL_AFRL0_Msk             (0xFU << GPIO_AFRL_AFRL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFRL0_Msk                    
-#define GPIO_AFRL_AFRL1_Pos             (4U)                                   
-#define GPIO_AFRL_AFRL1_Msk             (0xFU << GPIO_AFRL_AFRL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFRL1_Msk                    
-#define GPIO_AFRL_AFRL2_Pos             (8U)                                   
-#define GPIO_AFRL_AFRL2_Msk             (0xFU << GPIO_AFRL_AFRL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFRL2_Msk                    
-#define GPIO_AFRL_AFRL3_Pos             (12U)                                  
-#define GPIO_AFRL_AFRL3_Msk             (0xFU << GPIO_AFRL_AFRL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFRL3_Msk                    
-#define GPIO_AFRL_AFRL4_Pos             (16U)                                  
-#define GPIO_AFRL_AFRL4_Msk             (0xFU << GPIO_AFRL_AFRL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFRL4_Msk                    
-#define GPIO_AFRL_AFRL5_Pos             (20U)                                  
-#define GPIO_AFRL_AFRL5_Msk             (0xFU << GPIO_AFRL_AFRL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFRL5_Msk                    
-#define GPIO_AFRL_AFRL6_Pos             (24U)                                  
-#define GPIO_AFRL_AFRL6_Msk             (0xFU << GPIO_AFRL_AFRL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFRL6_Msk                    
-#define GPIO_AFRL_AFRL7_Pos             (28U)                                  
-#define GPIO_AFRL_AFRL7_Msk             (0xFU << GPIO_AFRL_AFRL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFRL7_Msk                    
-
+#define GPIO_AFRL_AFSEL0_Pos            (0U)                                   
+#define GPIO_AFRL_AFSEL0_Msk            (0xFU << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL1_Pos            (4U)                                   
+#define GPIO_AFRL_AFSEL1_Msk            (0xFU << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL2_Pos            (8U)                                   
+#define GPIO_AFRL_AFSEL2_Msk            (0xFU << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL3_Pos            (12U)                                  
+#define GPIO_AFRL_AFSEL3_Msk            (0xFU << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL4_Pos            (16U)                                  
+#define GPIO_AFRL_AFSEL4_Msk            (0xFU << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL5_Pos            (20U)                                  
+#define GPIO_AFRL_AFSEL5_Msk            (0xFU << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL6_Pos            (24U)                                  
+#define GPIO_AFRL_AFSEL6_Msk            (0xFU << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL7_Pos            (28U)                                  
+#define GPIO_AFRL_AFSEL7_Msk            (0xFU << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                GPIO_AFRL_AFSEL7_Msk  
+
+/* Legacy aliases */                  
+#define GPIO_AFRL_AFRL0_Pos             GPIO_AFRL_AFSEL0_Pos                                  
+#define GPIO_AFRL_AFRL0_Msk             GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1_Pos             GPIO_AFRL_AFSEL1_Pos
+#define GPIO_AFRL_AFRL1_Msk             GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2_Pos             GPIO_AFRL_AFSEL2_Pos
+#define GPIO_AFRL_AFRL2_Msk             GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3_Pos             GPIO_AFRL_AFSEL3_Pos
+#define GPIO_AFRL_AFRL3_Msk             GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4_Pos             GPIO_AFRL_AFSEL4_Pos
+#define GPIO_AFRL_AFRL4_Msk             GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5_Pos             GPIO_AFRL_AFSEL5_Pos
+#define GPIO_AFRL_AFRL5_Msk             GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6_Pos             GPIO_AFRL_AFSEL6_Pos
+#define GPIO_AFRL_AFRL6_Msk             GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7_Pos             GPIO_AFRL_AFSEL7_Pos
+#define GPIO_AFRL_AFRL7_Msk             GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFSEL7
+ 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos             (0U)                                   
-#define GPIO_AFRH_AFRH0_Msk             (0xFU << GPIO_AFRH_AFRH0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFRH0_Msk                    
-#define GPIO_AFRH_AFRH1_Pos             (4U)                                   
-#define GPIO_AFRH_AFRH1_Msk             (0xFU << GPIO_AFRH_AFRH1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFRH1_Msk                    
-#define GPIO_AFRH_AFRH2_Pos             (8U)                                   
-#define GPIO_AFRH_AFRH2_Msk             (0xFU << GPIO_AFRH_AFRH2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFRH2_Msk                    
-#define GPIO_AFRH_AFRH3_Pos             (12U)                                  
-#define GPIO_AFRH_AFRH3_Msk             (0xFU << GPIO_AFRH_AFRH3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFRH3_Msk                    
-#define GPIO_AFRH_AFRH4_Pos             (16U)                                  
-#define GPIO_AFRH_AFRH4_Msk             (0xFU << GPIO_AFRH_AFRH4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFRH4_Msk                    
-#define GPIO_AFRH_AFRH5_Pos             (20U)                                  
-#define GPIO_AFRH_AFRH5_Msk             (0xFU << GPIO_AFRH_AFRH5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFRH5_Msk                    
-#define GPIO_AFRH_AFRH6_Pos             (24U)                                  
-#define GPIO_AFRH_AFRH6_Msk             (0xFU << GPIO_AFRH_AFRH6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFRH6_Msk                    
-#define GPIO_AFRH_AFRH7_Pos             (28U)                                  
-#define GPIO_AFRH_AFRH7_Msk             (0xFU << GPIO_AFRH_AFRH7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFRH7_Msk                    
+#define GPIO_AFRH_AFSEL8_Pos            (0U)                                   
+#define GPIO_AFRH_AFSEL8_Msk            (0xFU << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL9_Pos            (4U)                                   
+#define GPIO_AFRH_AFSEL9_Msk            (0xFU << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL10_Pos           (8U)                                   
+#define GPIO_AFRH_AFSEL10_Msk           (0xFU << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10               GPIO_AFRH_AFSEL10_Msk                    
+#define GPIO_AFRH_AFSEL11_Pos           (12U)                                  
+#define GPIO_AFRH_AFSEL11_Msk           (0xFU << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11               GPIO_AFRH_AFSEL11_Msk                    
+#define GPIO_AFRH_AFSEL12_Pos           (16U)                                  
+#define GPIO_AFRH_AFSEL12_Msk           (0xFU << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12               GPIO_AFRH_AFSEL12_Msk                    
+#define GPIO_AFRH_AFSEL13_Pos           (20U)                                  
+#define GPIO_AFRH_AFSEL13_Msk           (0xFU << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13               GPIO_AFRH_AFSEL13_Msk                    
+#define GPIO_AFRH_AFSEL14_Pos           (24U)                                  
+#define GPIO_AFRH_AFSEL14_Msk           (0xFU << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14               GPIO_AFRH_AFSEL14_Msk                    
+#define GPIO_AFRH_AFSEL15_Pos           (28U)                                  
+#define GPIO_AFRH_AFSEL15_Msk           (0xFU << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15               GPIO_AFRH_AFSEL15_Msk                    
+
+/* Legacy aliases */                  
+#define GPIO_AFRH_AFRH0_Pos             GPIO_AFRH_AFSEL8_Pos
+#define GPIO_AFRH_AFRH0_Msk             GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1_Pos             GPIO_AFRH_AFSEL9_Pos
+#define GPIO_AFRH_AFRH1_Msk             GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2_Pos             GPIO_AFRH_AFSEL10_Pos
+#define GPIO_AFRH_AFRH2_Msk             GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3_Pos             GPIO_AFRH_AFSEL11_Pos
+#define GPIO_AFRH_AFRH3_Msk             GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4_Pos             GPIO_AFRH_AFSEL12_Pos
+#define GPIO_AFRH_AFRH4_Msk             GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5_Pos             GPIO_AFRH_AFSEL13_Pos
+#define GPIO_AFRH_AFRH5_Msk             GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6_Pos             GPIO_AFRH_AFSEL14_Pos
+#define GPIO_AFRH_AFRH6_Msk             GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7_Pos             GPIO_AFRH_AFSEL15_Pos
+#define GPIO_AFRH_AFRH7_Msk             GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFSEL15
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                   (0x00000001U)                          
@@ -8169,99 +8219,99 @@
 /*****************  Bit definition for RCC_APB2RSTR register  ****************/
 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)                          
 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
 #define RCC_APB2RSTR_USART6RST_Pos               (5U)                          
 #define RCC_APB2RSTR_USART6RST_Msk               (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
-#define RCC_APB2RSTR_USART6RST                   RCC_APB2RSTR_USART6RST_Msk    /*!< USART6 clock reset */
+#define RCC_APB2RSTR_USART6RST                   RCC_APB2RSTR_USART6RST_Msk    /*!< USART6 reset */
 #define RCC_APB2RSTR_USART7RST_Pos               (6U)                          
 #define RCC_APB2RSTR_USART7RST_Msk               (0x1U << RCC_APB2RSTR_USART7RST_Pos) /*!< 0x00000040 */
-#define RCC_APB2RSTR_USART7RST                   RCC_APB2RSTR_USART7RST_Msk    /*!< USART7 clock reset */
+#define RCC_APB2RSTR_USART7RST                   RCC_APB2RSTR_USART7RST_Msk    /*!< USART7 reset */
 #define RCC_APB2RSTR_USART8RST_Pos               (7U)                          
 #define RCC_APB2RSTR_USART8RST_Msk               (0x1U << RCC_APB2RSTR_USART8RST_Pos) /*!< 0x00000080 */
-#define RCC_APB2RSTR_USART8RST                   RCC_APB2RSTR_USART8RST_Msk    /*!< USART8 clock reset */
+#define RCC_APB2RSTR_USART8RST                   RCC_APB2RSTR_USART8RST_Msk    /*!< USART8 reset */
 #define RCC_APB2RSTR_ADCRST_Pos                  (9U)                          
 #define RCC_APB2RSTR_ADCRST_Msk                  (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC clock reset */
+#define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC reset */
 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)                         
 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)                         
 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
 #define RCC_APB2RSTR_USART1RST_Pos               (14U)                         
 #define RCC_APB2RSTR_USART1RST_Msk               (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 clock reset */
+#define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
 #define RCC_APB2RSTR_TIM15RST_Pos                (16U)                         
 #define RCC_APB2RSTR_TIM15RST_Msk                (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
-#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 reset */
 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)                         
 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)                         
 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
 #define RCC_APB2RSTR_DBGMCURST_Pos               (22U)                         
 #define RCC_APB2RSTR_DBGMCURST_Msk               (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU clock reset */
-
-/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU reset */
+
+/*!< Old ADC1 reset bit definition maintained for legacy purpose */
 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST          
 
 /*****************  Bit definition for RCC_APB1RSTR register  ****************/
 #define RCC_APB1RSTR_TIM2RST_Pos                 (0U)                          
 #define RCC_APB1RSTR_TIM2RST_Msk                 (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)                          
 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
 #define RCC_APB1RSTR_TIM6RST_Pos                 (4U)                          
 #define RCC_APB1RSTR_TIM6RST_Msk                 (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 reset */
 #define RCC_APB1RSTR_TIM7RST_Pos                 (5U)                          
 #define RCC_APB1RSTR_TIM7RST_Msk                 (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 clock reset */
+#define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 reset */
 #define RCC_APB1RSTR_TIM14RST_Pos                (8U)                          
 #define RCC_APB1RSTR_TIM14RST_Msk                (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
-#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 reset */
 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)                         
 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
 #define RCC_APB1RSTR_SPI2RST_Pos                 (14U)                         
 #define RCC_APB1RSTR_SPI2RST_Msk                 (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
 #define RCC_APB1RSTR_USART2RST_Pos               (17U)                         
 #define RCC_APB1RSTR_USART2RST_Msk               (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
 #define RCC_APB1RSTR_USART3RST_Pos               (18U)                         
 #define RCC_APB1RSTR_USART3RST_Msk               (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 clock reset */
+#define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 reset */
 #define RCC_APB1RSTR_USART4RST_Pos               (19U)                         
 #define RCC_APB1RSTR_USART4RST_Msk               (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_USART4RST                   RCC_APB1RSTR_USART4RST_Msk    /*!< USART 4 clock reset */
+#define RCC_APB1RSTR_USART4RST                   RCC_APB1RSTR_USART4RST_Msk    /*!< USART 4 reset */
 #define RCC_APB1RSTR_USART5RST_Pos               (20U)                         
 #define RCC_APB1RSTR_USART5RST_Msk               (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_USART5RST                   RCC_APB1RSTR_USART5RST_Msk    /*!< USART 5 clock reset */
+#define RCC_APB1RSTR_USART5RST                   RCC_APB1RSTR_USART5RST_Msk    /*!< USART 5 reset */
 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)                         
 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
 #define RCC_APB1RSTR_I2C2RST_Pos                 (22U)                         
 #define RCC_APB1RSTR_I2C2RST_Msk                 (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 reset */
 #define RCC_APB1RSTR_CANRST_Pos                  (25U)                         
 #define RCC_APB1RSTR_CANRST_Msk                  (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
-#define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN clock reset */
+#define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN reset */
 #define RCC_APB1RSTR_CRSRST_Pos                  (27U)                         
 #define RCC_APB1RSTR_CRSRST_Msk                  (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST                      RCC_APB1RSTR_CRSRST_Msk       /*!< CRS clock reset */
+#define RCC_APB1RSTR_CRSRST                      RCC_APB1RSTR_CRSRST_Msk       /*!< CRS reset */
 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)                         
 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR clock reset */
+#define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
 #define RCC_APB1RSTR_DACRST_Pos                  (29U)                         
 #define RCC_APB1RSTR_DACRST_Msk                  (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                      RCC_APB1RSTR_DACRST_Msk       /*!< DAC clock reset */
+#define RCC_APB1RSTR_DACRST                      RCC_APB1RSTR_DACRST_Msk       /*!< DAC reset */
 #define RCC_APB1RSTR_CECRST_Pos                  (30U)                         
 #define RCC_APB1RSTR_CECRST_Msk                  (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
-#define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC clock reset */
+#define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC reset */
 
 /******************  Bit definition for RCC_AHBENR register  *****************/
 #define RCC_AHBENR_DMAEN_Pos                     (0U)                          
@@ -8480,28 +8530,28 @@
 /*******************  Bit definition for RCC_AHBRSTR register  ***************/
 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)                         
 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
-#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)                         
 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
-#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)                         
 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
-#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
 #define RCC_AHBRSTR_GPIODRST_Pos                 (20U)                         
 #define RCC_AHBRSTR_GPIODRST_Msk                 (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
-#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD reset */
 #define RCC_AHBRSTR_GPIOERST_Pos                 (21U)                         
 #define RCC_AHBRSTR_GPIOERST_Msk                 (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
-#define RCC_AHBRSTR_GPIOERST                     RCC_AHBRSTR_GPIOERST_Msk      /*!< GPIOE clock reset */
+#define RCC_AHBRSTR_GPIOERST                     RCC_AHBRSTR_GPIOERST_Msk      /*!< GPIOE reset */
 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)                         
 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
-#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
 #define RCC_AHBRSTR_TSCRST_Pos                   (24U)                         
 #define RCC_AHBRSTR_TSCRST_Msk                   (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
-#define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS clock reset */
+#define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS reset */
 
 /* Old Bit definition maintained for legacy purpose */
-#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
+#define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS reset */
 
 /*******************  Bit definition for RCC_CFGR2 register  *****************/
 /*!< PREDIV configuration */
@@ -8729,9 +8779,9 @@
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP_Pos               (18U)                                     
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -8775,6 +8825,11 @@
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  *****************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
@@ -11673,6 +11728,9 @@
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
   ((INSTANCE) == TIM14)
 
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+  ((INSTANCE) == TIM1)
+
 /****************************** TSC Instances *********************************/
 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
 

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS STM32F0xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -112,11 +110,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.3
   */
 #define __STM32F0_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
 #define __STM32F0_DEVICE_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F0_DEVICE_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F0_DEVICE_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32F0_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F0_DEVICE_VERSION        ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
                                         |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f0xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.  
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,203 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "mbed_wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "mbed_error.h"
-
-int adc_inited = 0;
-
-void analogin_init(analogin_t *obj, PinName pin) {
-    uint32_t function = (uint32_t)NC;
-
-    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
-    //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be between 0xF0 and 0xFF
-    if ((pin < 0xF0) || (pin >= 0x100)) {
-        // Normal channels
-        // Get the peripheral name from the pin and assign it to the object
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
-        // Get the functions (adc channel) from the pin and assign it to the object
-        function = pinmap_function(pin, PinMap_ADC);
-        // Configure GPIO
-        pinmap_pinout(pin, PinMap_ADC);
-    } else {
-        // Internal channels
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
-        function = pinmap_function(pin, PinMap_ADC_Internal);
-        // No GPIO configuration for internal channels
-    }
-    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-    MBED_ASSERT(function != (uint32_t)NC);
-
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // The ADC initialization is done once
-    if (adc_inited == 0) {
-        adc_inited = 1;
-
-        // Enable ADC clock
-        __ADC1_CLK_ENABLE();
-
-        // Configure ADC
-        obj->handle.State = HAL_ADC_STATE_RESET;
-        obj->handle.Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4;
-        obj->handle.Init.Resolution            = ADC_RESOLUTION12b;
-        obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-        obj->handle.Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD;
-        obj->handle.Init.EOCSelection          = EOC_SINGLE_CONV;
-        obj->handle.Init.LowPowerAutoWait      = DISABLE;
-        obj->handle.Init.LowPowerAutoPowerOff  = DISABLE;
-        obj->handle.Init.ContinuousConvMode    = DISABLE;
-        obj->handle.Init.DiscontinuousConvMode = DISABLE;
-        obj->handle.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
-        obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
-        obj->handle.Init.DMAContinuousRequests = DISABLE;
-        obj->handle.Init.Overrun               = OVR_DATA_OVERWRITTEN;
-        if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
-            error("Cannot initialize ADC");
-        }
-        // Run the ADC calibration
-        if (HAL_ADCEx_Calibration_Start(&obj->handle) != HAL_OK) {
-            error("Cannot Start ADC_Calibration");
-        }
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj) {
-    ADC_ChannelConfTypeDef sConfig;
-
-    // Configure ADC channel
-    sConfig.Rank         = ADC_RANK_CHANNEL_NUMBER;
-#if defined (TARGET_STM32F091RC)
-    sConfig.SamplingTime = ADC_SAMPLETIME_13CYCLES_5;
-#else
-    sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5;
-#endif
-
-    switch (obj->channel) {
-        case 0:
-            sConfig.Channel = ADC_CHANNEL_0;
-            break;
-        case 1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case 2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case 3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case 4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case 5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case 6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case 7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case 8:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case 9:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case 10:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case 11:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case 12:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case 13:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case 14:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case 15:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-        case 16:
-            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
-            break;
-        case 17:
-            sConfig.Channel = ADC_CHANNEL_VREFINT;
-            break;
-#ifdef ADC_CHANNEL_VBAT
-        case 18:
-            sConfig.Channel = ADC_CHANNEL_VBAT;
-            break;
-#endif
-        default:
-            return 0;
-    }
-
-    // Clear all channels as it is not done in HAL_ADC_ConfigChannel()
-    obj->handle.Instance->CHSELR = 0;
-
-    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
-
-    HAL_ADC_Start(&obj->handle); // Start conversion
-
-    // Wait end of conversion and get value
-    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
-        return (HAL_ADC_GetValue(&obj->handle));
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj) {
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj) {
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,190 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include <stdbool.h>
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    static bool adc_calibrated = false;
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
+    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // Configure ADC object structures
+    obj->handle.State = HAL_ADC_STATE_RESET;
+    obj->handle.Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4;
+    obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
+    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+    obj->handle.Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD;
+    obj->handle.Init.EOCSelection          = ADC_EOC_SINGLE_CONV;
+    obj->handle.Init.LowPowerAutoWait      = DISABLE;
+    obj->handle.Init.LowPowerAutoPowerOff  = DISABLE;
+    obj->handle.Init.ContinuousConvMode    = DISABLE;
+    obj->handle.Init.DiscontinuousConvMode = DISABLE;
+    obj->handle.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
+    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
+    obj->handle.Init.DMAContinuousRequests = DISABLE;
+    obj->handle.Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN;
+
+    __HAL_RCC_ADC1_CLK_ENABLE();
+
+    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+        error("Cannot initialize ADC");
+    }
+
+    // ADC calibration is done only once
+    if (!adc_calibrated) {
+        adc_calibrated = true;
+        HAL_ADCEx_Calibration_Start(&obj->handle);
+    }
+}
+
+uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    // Configure ADC channel
+    sConfig.Rank         = ADC_RANK_CHANNEL_NUMBER;
+#if defined (TARGET_STM32F091RC)
+    sConfig.SamplingTime = ADC_SAMPLETIME_13CYCLES_5;
+#else
+    sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5;
+#endif
+
+    switch (obj->channel) {
+        case 0:
+            sConfig.Channel = ADC_CHANNEL_0;
+            break;
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+            break;
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_VREFINT;
+            break;
+#ifdef ADC_CHANNEL_VBAT
+        case 18:
+            sConfig.Channel = ADC_CHANNEL_VBAT;
+            break;
+#endif
+        default:
+            return 0;
+    }
+
+    // Clear all channels as it is not done in HAL_ADC_ConfigChannel()
+    obj->handle.Instance->CHSELR = 0;
+
+    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+    HAL_ADC_Start(&obj->handle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+        return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+    } else {
+        return 0;
+    }
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h	Wed Jan 17 15:23:54 2018 +0000
@@ -136,6 +136,13 @@
 };
 #endif
 
+#if DEVICE_FLASH
+struct flash_s {
+    /*  nothing to be stored for now */
+    uint32_t dummy;
+};
+#endif
+
 #ifdef __cplusplus
 }
 #endif

--- a/targets/TARGET_STM/TARGET_STM32F0/device/Release_Notes_stm32f0xx_hal.html	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
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-<td style="padding: 0in;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.0
-/&nbsp;04-November-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and 
-enhancements implementation</span></span></li></ul><span style="font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Enhance HAL delay and time base implementation</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">:</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
-new templates
-stm32f0xx_hal_timebase_rtc_alarm_template.c,&nbsp;stm32f0xx_hal_timebase_rtc_wakeup_template.c
-and stm32f0xx_hal_timebase_tim_template.c which can be used to override
-the native
-HAL time base functions (defined as weak) to&nbsp;use either RTC or
-Timer as time
-base tick source. For more details about the usage of these drivers,
-please refer to HAL\HAL_TimeBase examples&nbsp;</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">and FreeRTOS-based applications</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black; font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0</span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL IWDG</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"><span class="Apple-converted-space">&nbsp;</span></span>driver: Overall driver rework&nbsp;for better implementation</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove&nbsp;</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_Start(),<span class="Apple-converted-space">&nbsp;</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_MspInit() and<span class="Apple-converted-space">&nbsp;</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_GetState()&nbsp;</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">APIs</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL WWDG</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"><span class="Apple-converted-space">&nbsp;</span></span>driver: Overall driver rework&nbsp;for better implementation</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove HAL_WWDG_Start(),<span class="Apple-converted-space">&nbsp;</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_WWDG_Start_IT(),</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span class="Apple-converted-space">&nbsp;</span>HAL_WWDG_MspDeInit() and<span class="Apple-converted-space">&nbsp;</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_WWDG_GetState() APIs&nbsp;</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Update the&nbsp;</span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US"></span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US"></span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US">HAL_WWDG_Refresh</span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US">(WWDG_HandleTypeDef *hwwdg, uint32_t counter) &nbsp;function and API &nbsp;by removing the &nbsp;"counter" parameter</span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span style="font-style: italic;">HAL CEC </span>driver:<span class="Apple-converted-space">&nbsp;</span>&nbsp;Overall driver rework with compatibility break versus previous HAL version</span><br><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove
-HAL CEC receive interrupt process function&nbsp;HAL_CEC_Receive_IT()
-and enable the "receive" &nbsp;mode during the Init phase</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Rename&nbsp;HAL_CEC_GetReceivedFrameSize() funtion to&nbsp;HAL_CEC_GetLastReceivedFrameSize()<br></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the&nbsp;<span></span>'InitiatorAddress'
-field from the&nbsp;CEC_InitTypeDef structure&nbsp;and manage
-it&nbsp;as a parameter in the HAL_CEC_Transmit_IT() function</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Move CEC Rx buffer pointer&nbsp;from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</span></li></ul></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">HAL TIM driver </span>: add </span><span style="font-size: 10pt; font-family: Verdana;">one field (AutoReloadPreload) in&nbsp;TIM_Base_InitTypeDef structure</span><br><br></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL Generic</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update HAL Driver compliancy with:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">MISRA
-C 2004 rule 14.8 (the statement forming the body of a 'switch',
-'while', 'do ... while', or 'for' statement shall be a compound
-statement)<br></span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL IWDG</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New simplified HAL IWDG driver: r</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">emove&nbsp;HAL_IWDG_Start(),&nbsp;HAL_IWDG_MspInit()
-and&nbsp;HAL_IWDG_GetState()&nbsp;APIs</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">API functions are:&nbsp;</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">HAL_IWDG_Init():&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">this function insures the configuration and the start of the IWDG
-counter</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">HAL_IWDG_Refresh():&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">this function insures the reload of the IWDG counter</span></li></ul></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Refer to the following example to identify the changes : IWDG_Reset, IWDG_WidowMode</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL WWDG</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New simplified HAL WWDG driver: remove&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">HAL_WWDG_Start(),&nbsp;HAL_WWDG_Start_IT(),&nbsp;HAL_WWDG_MspDeInit()
-and&nbsp;HAL_WWDG_GetState() APIs</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;"></span><span style="font-size: 11pt; font-family: &quot;Calibri&quot;,sans-serif; color: black;">HAL_WWDG_Refresh</span><span style="font-size: 10pt; font-family: Verdana;">() API to remove counter parameter</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt</span></li></ul><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">API
-functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(),
-HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Refer to the following example to identify the changes: WWDG_Example</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><b><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;" lang="EN-US">HAL CEC</span></b><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;" lang="EN-US"></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Overall driver rework with&nbsp;break of compatibility with HAL V1.4.0<br></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Rename HAL_CEC_GetReceivedFrameSize() function to&nbsp;HAL_CEC_GetLastReceivedFrameSize() function<br></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the&nbsp;<span></span>'InitiatorAddress'
-field from the&nbsp;CEC_InitTypeDef structure&nbsp;and manage
-it&nbsp;as a parameter in the HAL_CEC_Transmit_IT() function</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Move CEC Rx buffer pointer&nbsp;from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><o:p></o:p></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update driver to implement the new CEC state machine:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new&nbsp;</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">"rxState"</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span class="Apple-converted-space">&nbsp;</span>field in CEC_HandleTypeDef structure to provide the<span class="Apple-converted-space">&nbsp;</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">CEC<span class="Apple-converted-space">&nbsp;</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">state information related to Rx Operations</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC<span class="Apple-converted-space">&nbsp;</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">state information related to global Handle management and Tx Operations</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update CEC process to manage the new CEC states.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; color: black; font-size: 10pt;" lang="EN-US">Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">UART/USART</span></span><span style="font-size: 10pt; font-family: Verdana;">/</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">IRDA/SMARTCARD</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">IRQ Handler global optimization&nbsp;</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">New&nbsp;abort&nbsp;API: HAL_PPP_Abort(), HAL_PPP_Abort_IT() <br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Add error management in case of DMA transfer through
-       </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_DMA_Abort_IT() and DMA </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">XferAbortCallback()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">Polling management update:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">The user Timeout value must be estimated for the overall process
-duration</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SPI</span></b><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"></span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Polling mode:</span></li><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" statement to check on RXNE/TXE flage while transferring data</span></li></ul></ul></ul><ul style="margin-bottom: 0in;"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">&nbsp;Interrupt mode:</span></li><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Minimize access on SPI registers</span></li></ul></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">All modes:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update&nbsp;timeout management to check on global processes</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update error code management in all processes</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix regression in polling mode:<o:p></o:p></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and&nbsp;HAL_SPI_Transmit()<o:p></o:p></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix regression in interrupt mode:<o:p></o:p></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add to manage properly the&nbsp;overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Prevent&nbsp;data
-packing mode in reception for STM32F030x6, STM32F030x8,
-STM32F031x6,&nbsp;STM32F038xx, STM32F051x8 and STM32F058xx<br></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;" lang="EN-US">HAL DMA</span></b></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;" lang="EN-US">Global
-      driver code optimization to reduce memory footprint&nbsp;</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;" lang="EN-US">Add
-      new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to
-      register/unregister the different callbacks identified by the enum
-      typedef HAL_DMA_CallbackIDTypeDef</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;" lang="EN-US">Add
-      new Error Code HAL_DMA_ERROR_NOT_SUPPORTED</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;" lang="EN-US">Remove
-      DMA HAL_DMA_STATE_READY_HALF &amp; HAL_DMA_STATE_ERROR states in
-      HAL_DMA_StateTypeDef</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RTC</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Interrupt flag cleared before enabling the interrupt in HAL_RTCEx_SetWakeUpTimer_IT()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL I2C</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Disable I2C_OARx_EN bit&nbsp;before any configuration in OAR1 or 2 in HAL_I2C_Init()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Move I2C_NO_OPTION_FRAME in private section</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Use CMSIS bit for compilation switch&nbsp;instead of product switch</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Update HAL_I2C_Master_Sequential_Transmit_IT() function (wrong state check)</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add I2C_FIRST_AND_NEXT_FRAME option for I2C Sequential Transfer</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">On slave, reset&nbsp;LISTEN_TX state in case of direction change</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Remove GCC warnings<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span></span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">API update : add one field (AutoReloadPreload) in&nbsp;TIM_Base_InitTypeDef structure&nbsp;in order to set ARPE
-bit from&nbsp;TIMx_CR1 register</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New
-API : add&nbsp;2 macros (__HAL_TIM_ENABLE_OCxPRELOAD() and&nbsp;
-__HAL_TIM_DISABLE_OCxPRELOAD()) in order to set OCxPE bit
-from&nbsp;TIMx_CCMR1,&nbsp;TIMx_CCMR2 and TIMx_CCMR3 registers</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update TIM_SET_CAPTUREPOLARITY and TIM_RESET_CAPTUREPOLARITY&nbsp;definition&nbsp;to take into account CC4NP bit</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Use MODIFY_REG macro to avoid wrong initialisation in ConfigBreakDeadTime()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SMBUS</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Update SMBUS_Master_ISR() and SMBUS_Slave_ISR()&nbsp;to ensure storage of last receive data</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; font-weight: bold;" lang="EN-US">HAL
-     PCD&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;" lang="EN-US">Update
-     HAL_PCD_ActivateRemoteWakeup() and HAL_PCD_DeActivateRemoteWakeup() APIs
-     to add condition if LPM activated.</span><span style="font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;" lang="EN-US"><o:p></o:p></span></li></ul></ul>
-<span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL GPIO</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove LL_GPIO_SPEED_FREQ_VERY_HIGH (GPIO_SPEED_FREQ_VERY_HIGH does not exist for STM32F0xx serie)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_TIM</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove TIM_SMCR_OCCS compilation switch (useless for STM32F0xx serie)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_CRS</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update CRS_POSITION_XXX&nbsp; definitions&nbsp;</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">to use&nbsp;CMSIS&nbsp;definition instead of hardcoded values</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.0
-/ 27-May-2016<o:p></o:p></span></h3><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">First official release supporting the Low Level drivers for the STM32F0xx family:</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Low Layer drivers APIs provide register level programming:</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">they require deep knowledge of peripherals described in STM32F0xx Reference Manual.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Low Layer drivers are available for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"> ADC, COMP, Cortex, CRC, CRS, DAC, DMA, EXTI,
-GPIO, I2C, IWDG,&nbsp;PWR,<br>RCC,&nbsp;RTC, SPI,&nbsp;TIM, USART and WWDG peripherals</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> and additional Low Level Bus, System and Utilities APIs.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f0xx_ll_ppp.h files for PPP peripherals,<br>there is no configuration file and each stm32f0xx_ll_ppp.h file must be included in user code.</span></li></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">Maintenance release to fix known defects and enhancements implementation.</span></span></li></ul><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL generic</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">Updated HAL Driver compliancy with </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rules</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">:</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 5.2 (tmpreg" variable shall not be used inside MACRO)</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 10.3 (illegal explicit conversion from&nbsp;type "unsigned int" to "uint16_t *).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 10.5 (bitwise operators ~ and &lt;&lt;).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 11.5 (no cast that removes any const or volatile qualification from the type addressed by a pointer).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 12.6 (logical operators should not be confused with bitwise operators).<br></span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 14.3 </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">(a null statement shall only occur on a line by itself).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 14.9 ('if {expression}' / 'else' construct shall be followed by a compound statement).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 15.3 (all switch statements shall contain a final default clause).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 16.3 (identifiers shall be given for all of the parameters in a function prototype declaration).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 16.4 (identifiers used in the declaration and definition shall be identical).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">MISRA C 2004 rule 19.10 (in function-like macro definition, each instance of a parameter shall be enclosed in parenthesis).</span></li></ul></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">HAL</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Changed uwTick to global to allow overwrite of HAL_IncTick().</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">HAL COMP</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added delay in COMP startup time required to reach propagation delay specification</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">HAL CRC</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated devices supporting&nbsp;Programmable Polynomial features: defines and functions prototypes are available only for<br>STM32F071xB, STM32F072xB, STM32F078xx, STM32F091xC, STM32F098x devices.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_CRC_DeInit() function (restored IDR Register to Reset value).<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">HAL DMA</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added __HAL_DMA_GET_COUNTER</span><span style="font-size: 10pt; font-family: Verdana;">() macro returning the number of remaining data units in the current DMA Channel transfer.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Provided
-new function HAL_DMA_Abort_IT() to abort&nbsp;current DMA transfer
-under interrupt mode without polling for DMA enable bit.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">HAL GPIO</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated IS_GPIO_PIN() macro to cover full u32 bits.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">HAL I2C</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Used macro definition for I2C instances supporting Wakeup from Stop mode</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated polling flags management within I2C slave DMA drivers.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added support of repeated start feature in case of multimaster mode (allow master to keep I2C communication with slave).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated WaitOnFlag management (timeout measurement should be always cumulative).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Optimized HAL_I2C_XX_IRQHandler() functions (read status registers only once).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Reworked DMA end process and I2C error management during DMA transfer.<br></span></li></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">HAL PWR</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Aligned EWUPx pins and PWR functions with CMSIS definitions</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;" lang="EN-US">HAL IRDA</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Modified IRDA_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Modified EIE bit setting in Tx and Rx transfers (Interrupt mode).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated IRDA_SetConfig() function following UART Baudrate calculation update.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Reviewed IRDA state machine to avoid cases where IRDA state is overwritten by IRDA IRQ.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RCC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Performed optimizations for HAL_RCC_ClockConfig(), HAL_RCCEx_PeriphCLKConfig functions.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_RCC_OscConfig() function (Reset HSEON/LSEON and HSEBYP/LSEBYP bits before configuring the HSE/LSE).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_RCC_OscConfig() function to enable PWR only if necessary for LSE configuration.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Corrected CRS interrupt sources.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Modified reset of Backup domain only if the RTC Clock source selection is modified from reset value.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added missing HAL IRQHandler and callbacks API for CRS management.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added missing RCC_CFGR_PLLNODIV definition for STM32F030x4/6 devices.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed HSI48State from structure RCC_OscInitTypeDef when device does not support HSI48.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed RCC_HSI48_OFF.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed flag RCC_FLAG_RMV which is write only.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Modified AHBPrescTable and </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">APBPrescTable in HAL.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">R</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">enamed&nbsp;</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">RCC_CRS_SYNCWARM to&nbsp;RCC_CRS_SYNCWARN.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">R</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">enamed </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">RCC_CRS_TRIMOV to&nbsp;RCC_CRS_TRIMOVF.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL SPI</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated HAL_SPI_TransmitReceive() function </span><span style="font-size: 10pt; font-family: Verdana;">in&nbsp;slave mode </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">to </span><span style="font-size: 10pt; font-family: Verdana;">receive correctly the CRC when NSS pulse activated.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added missing __IO in SPI_HandleTypeDef definition.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated IS_SPI_CRC_POLYNOMIAL macro definition as polynomial value should be odd only.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated
-SPI_2linesTxISR_8BIT() and SPI_2linesTxISR_16BIT() functions: added
-return so that SPI_2linesTxISR_8BITCRC() or SPI_2linesTxISR_16BITCRC()
-function is called from HAL_SPI_TransmitReceive_IT() when CRC is
-activated.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL TIM</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Used </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">IS_TIM_HALL_INTERFACE_INSTANCE </span><span style="font-size: 10pt; font-family: Verdana;">macro instead of&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">IS_TIM_XOR_INSTANCE </span><span style="font-size: 10pt; font-family: Verdana;">macro in<br>HAL_TIMEx_HallSensor_xxx() functions.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_TIM_ConfigOCrefClear() function to allow TIM_CLEARINPUTSOURCE_OCREFCLR as new ClearInputSource.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL UART-USART</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated UART Baudrate calculation (UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated USART_SetConfig() function following UART Baudrate calculation update.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Aligned UART-USART Stop Bits with others STM32 series.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Renamed IS_UART_WAKEUP_INSTANCE&nbsp;to IS_UART_WAKEUP_FROMSTOP_INSTANCE.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Modified UART_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Reviewed UART state machine to avoid cases where UART state is overwritten by UART IRQ.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL USB</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Corrected double buffer implementation in PCD_SET_EP_DBUF1_CNT() macro.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Added missing USB_CNTR_SOFM when setting wInterrupt_Mask global variable used in HAL_PCD_Init.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL SMARTCARD</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Aligned&nbsp;</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SMARTCARD</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> Stop Bits with others&nbsp;</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32 series</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Modified SMARTCARD_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated SMARTCARD_SetConfig() function following UART Baudrate calculation update.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Reviewed SMARTCARD state machine to avoid cases where SMARTCARD state is overwritten by SMARTCARD IRQ.</span></li></ul></ul><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.1
-/ 29-January-2016<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and 
-enhancements implementation</span></span></li></ul><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;"></span></span><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL Generic</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated HAL Driver compliancy with:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).</span></li><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.5 (bitwise operators ~ and &lt;&lt;).</span></li><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated HAL weak empty callbacks to prevent unused argument compilation warnings.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Updated stm32f3xx_hal_msp.c files:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Removed reference to MicroXplorer.</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated stm32f3xx_hal_conf.h files:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Set HSE_STARTUP_TIMEOUT value to 100ms instead of 5000ms</span></li></ul></ul></ul><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL ADC</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Corrected ADC_CHANNEL_VREFINT enabling in the CCR register.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected assert param of nb of discontinuous conversions when discontinuous mode is enabled.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed Flag EOS in HAL_ADC_GetValue().</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CAN</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Corrected missing __HAL_UNLOCK when all Mailboxes are busy.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added ERRI bit clear besides to clearing LEC bits in CAN_ESR register, in case of Error interrupt.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CORTEX</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Removed __HAL_CORTEX_SYSTICKCLK_CONFIG macro, replaced by HAL_SYSTICK_CLKSourceConfig() function.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CRC</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated CRC HAL_CRC_Calculate() and HAL_CRC_Accumulate() comments, handling input data pointers that are not * uint32_t.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL FLASH</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Added FLASH API HAL_FLASHEx_OBGetUserData() to get the value saved in User data option byte.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Aligned Return value of HAL_FLASH_EndOfOperationCallback function (0xFFFFFFF) when process is finished.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL GPIO</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated GPIO Output Speed literals naming to ensure HAL full compatibility.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added GPIOD support for STM32070x6 devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Modified ADC poll for event to return timeout instead of error.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2C</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Corrected wrong management of AF after NACK.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Aligned I2C driver with new state machine definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected interrupt disabling in I2C_SlaveReceive_ISR() function.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Modified HAL_I2C_Master_Transmit to handle sending data of size 0.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Renamed I2C_CR1_DFN to I2C_CR1_DNF.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PCD</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated call to Double Buffering Counter Function.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PWR</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Added do { } while(0) in __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() multi statement macro.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RCC</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Performed optimizations for HAL_RCC_ClockConfig() function.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected invertion in LSE drive capability Bit definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Performed optimizations for internal oscillators and PLL startup time.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added GPIOD support for STM32070x6 devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed GPIOE support for STM32F030xC devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add RCC_USBCLKSOURCE_NONE when HSI48 is not present.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected definition for flag RCC_FLAG_V18PWRRST.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added missing macro __HAL_RCC_LSEDRIVE_CONFIG.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Aligned naming of macros related to CRS_CFGR register.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected __HAL_RCC_CRS_CLEAR_IT()/__HAL_RCC_CRS_CLEAR_FLAG() macros.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed Bit PLLNODIV for STM32F030x6 devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Review implementation to automatically enable backup domain.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added RCC_IT_HSI48RDY definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Renamed __HAL_RCC_MCO_CONFIG() to __HAL_RCC_MCO1_CONFIG().</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RTC</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Aligned different HAL_RTC_XXIRQHandler() implementations.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Check the behavior of flag WUTWF and corrected update of wakeup counter registers.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added subsecond fration formula in HAL_RTC_GetTime() function.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Updated Bits mask literals used in macros definition.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL TIM</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Corrected __HAL_TIM_SET_PRESCALER timer prescaler definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Protected SMCR register of possible overwrite in HAL_TIM_ConfigOCrefClear().</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected assert checks in HAL_TIM_ConfigClockSource().</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL TSC</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated IO default state management.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL UART-USART</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Corrected behavior of HAL_UART_IRQ_Handler() (removed enabling/disabling of ERR IT source).</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected UART_FLAG_SBKF definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected values used for max allowed baudrates constant definitions.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed
-USART_CR2_LINEN/USART_CR3_IREN/USART_CR3_SCEN/USART_CR1_UESM bits
-definitions for STM32F030x6, STM32F030x8, STM32F070xB, STM32F070x6,
-STM32F030xC.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL WWDG</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Aligned WWDG registers Bits naming between all families.</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0
-/ 26-June-2015<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and 
-enhancements implementation</span></span></li></ul><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;"></span></span><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">Complete HAL API alignment (macro/function renaming)</span></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL Generic</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update HAL drivers to be MISRA/C++ compliant.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Initialized handle lock in HAL_PPP_Init().</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add SYSCFG define macros to manage FM+ on GPIOs.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Use uint32_t instead of uint8_t/uint_16.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL ADC</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update ADC state machine. Missing state in function "HAL_ADCEx_Calibration_Start().</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Align ADC_SOFTWARE_START literal on STM32L0xx.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_ADC_PollForConversion(): update to return error status in case of ADC-DMA mode.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_ADC_Init(): ADC resolution must be changed only when ADC is disabled.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">ADC_ConversionStop(): correct wrong timeout value.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_ADC_AnalogWDGConfig(): Add missing assert param.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Remove channel for monitoring VBAT power supply pin on F0 Value line devices.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Move
-sampling time setting into ADC init stucture (keep setting into ADC
-channel init stucture with comments of obsolete setting).</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Move
-__HAL_UNLOCK() before peripheral activation because if an interruption
-occurs between ADC enable &amp; __HAL_UNLOCK(), IRQ handler will be
-executed while HAL still locked.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">ADC_DMAConvCplt(): Add call to ADC error callback in case of error.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Rename local variables for compliancy with coding rules (tmpHALstatus ==&gt; tmp_hal_status).</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Simplify __HAL_ADC_GET_IT_SOURCE().</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add use of POSITION_VAL.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add optimization of ADC stabilization delays.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CAN</span>&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add management of CAN Slave start bank in HAL_CAN_ConfigFilter().</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Unlock the CAN process when communication error occurred.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Replace “uint32_t Data[8]” by “uint8_t Data[8]” in structures&nbsp; CanTxMsgTypeDef and CanRxMsgTypeDef.</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"><span style="color: black;"></span><o:p></o:p></span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CEC</span>&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new API HAL_CEC_GetReceivedFrameSize() </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to get size of received frame</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CORTEX</span>&nbsp;</span></li><ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new macro <span style="font-style: italic;">IS_NVIC_DEVICE_IRQ()</span> to 
-check on negative values of IRQn </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">parameter</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CRC</span>&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macros __HAL_CRC_GET_IDR() and __HAL_CRC_SET_IDR().</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update __HAL_CRC_SET_IDR macro in resorting to WRITE_REG instead of MODIFY_REG (cycles gain at execution).</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL DAC</span>&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and 
-</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">DAC_FLAG_DMAUDR</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">2.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL DMA</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Correct __HAL_DMA_GET_IT_SOURCE brief comments.</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL FLASH</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">FLASH_OB_GetRDP(): update function to return the FLASH Read Protection level (OB_RDP_LEVEL_x).</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">FLASH_OB_RDP_LevelConfig(): update function to set the FLASH Read Protection level (OB_RDP_LEVEL_x).</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add missing macro __HAL_FLASH_GET_LATENCY.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Disable WRP not compliant with other family.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add FLASH_BANK1_END defines.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Remove WRP defines for few defines under devices swicthes.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add switch to handle option bits BOOT_SEL &amp; nBOOT1 not present on STM32F030xC &amp; STM32F070x6.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL GPIO</span>&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f0xx_hal_gpio_ex.h: add IR as possible GPIO alternate function 1 for STM32F030x6.</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2C</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_I2C_ER_IRQHandler(): handle NACK test during wait on flag treatment.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2S</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_I2S_DMAStop(): Correctt DMA Stop function which stops both Rx and Tx channels regardless which one was set-up.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL IRDA</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_IRDA_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PWR</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add macros __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() and __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() comments.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RCC</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Implement workaround to cover RCC limitation regarding Peripheral enable delay.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_RCC_OscConfig(): correct test on LSEState.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add defines for RCC_System_Clock_Source_Status.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Follow specific procedure to enable HSE.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add macros to get the enable or disable status of peripheral clock.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_RCCEx_PeriphCLKConfig(): reset backup domain only if RTC clock source has been changed.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add interface HAL_RCCEx_GetPeriphCLKFreq.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RTC</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add missing RTC_FLAG_INIT in flag list.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_RTC_DeInit(): add switch products condition around WakeUp timer registers (WUTWF,WUTR).</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Remove RTC_FLAG_INIT as currently unused.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMARTCARD</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add missing IDLE flag management.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Align SMARTCARD_Last_Bit defines.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SPI</span>&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix issue related to missing reset of the Dma Tx callback inside the function HAL_SPI_TransmitReceive_DMA().<br>In
-that case only RX callback are used and the call of TX callback can
-close the communication before the end of the RX processing.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SPI_2linesRxISR_8BIT():
-correct issue on RX 2lines with DataSize8bit, even buffer size and CRC
-8bit (SPI_RXFIFO_THRESHOLD is not set).</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fit bit update add BSY flag check for all the process.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
-__IO (volatile) to the "State" member of the SPI_HandleTypeDef
-struct.&nbsp;to&nbsp;missing reset of the Dma Tx callback inside the
-function
-HAL_SPI_TransmitReceive_DMA().</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL TIM</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add __HAL_TIM_SET_CAPTUREPOLARITY, TIM_SET_CAPTUREPOLARITY, TIM_RESET_CAPTUREPOLARITY macros.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL UART</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add macro to control CTS and RTS from the customer applications.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">UART_DMATransmitCplt(): change implementation to remove WaitOnFlag in ISR.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Change DMA TX management to remove WaitOnFlag in ISR.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add DMA circular mode support for the communication peripherals.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add UART NVIC configuration in the HAL_UART_MspInit().</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add the UARTx_IRQHandler() in the stm32fxxx_it.c and the prototype in the stm32fxxx_it.h.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Modify UART DMA implementation issue (missed clear the TC bit in the SR).</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add a OVR flag clear prior resuming DMA RX transfer.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_UART_DMAResume(): Remove UART_CheckIdleState() call and replace it by unlock + return(HAL_OK).</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_UART_DMAStop(): remove LOCK/UNLOCK calls.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_UART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL USART</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_USART_IRQHandler(): Correct parameters values of __HAL_USART_CLEAR_IT().</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Replace xxxITxxx defines by xxxCLEARxxxF defines in __HAL_USART_CLEAR_IT calls.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_USART_Init(): update to reach max frequencies (enable oversampling by 8).</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_USART_DMAPause()/HAL_USART_DMAResume(): add of a OVR flag clear prior resuming DMA RX transfer.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_USART_DMAResume(): Remove UART_CheckIdleState() call and replace it by just an Unlock + ret(HAL_OK).</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_USART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1
-/ 09-January-2015</span></h3><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL&nbsp;</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f0xx_hal.h: add missing define for USART3_RX/TX DMA remap on channel3 &amp; channel2 for STM32F070xB only</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL GPIO</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f0xx_hal_gpio_ex.h: add&nbsp;I2C1 as possible GPIO alternate function 3 for STM32F070xB</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RCC</span></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f0xx_hal_rcc_ex.h: add missing&nbsp;USART2_CLK_ENABLE/DISABLE() macros for&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F070x6</span></li></ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC</span></span> 
-<ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f0xx_hal_rtc_ex.h/.c: 
-Enable RTC periodic Wakeup timer feature on </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F070xB 
-&amp; </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F030xC</span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f0xx_hal_rtc_ex.c: 
-remove </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_RTCEx_Tamper3EventCallback() 
-API for </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F070xB 
-&amp; </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F030xC, since 
-there is no TAMPER3 on those products.</span></li></ul>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL UART</span></span> 
-<ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f0xx_hal_uart_ex.c/.h: 
-add HAL_RS485Ex_Init() API for </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F0xx Value 
-Line devices</span></li></ul></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0
-/ 05-December-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL generic</span>&nbsp;</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HandleTypeDef.ErrorCode must be typed uint32_t</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update HAL drivers to ensure compliancy w/ C++</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Case mismatch between #include typo and effective file name generating compiler errors under Linux</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Correct various issues for documentation generation (group name, </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">doxygen tags, </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">etc..)</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Missing support of I2C_PAx_FMP of F04xx devices<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL ADC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Improve HAL ADC comments</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Correct issue observed with ADC start simultaneous commands</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Remove&nbsp;macro __HAL_ADC_OFR_CHANNEL()&nbsp;since&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OFRx register</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> is not available on F0 devices.<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL&nbsp;CAN&nbsp;</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as __IO uint32 instead of <span style="font-weight: bold;">enum HAL_CAN_ErrorTypeDef</span> to fix C++ compilation issue<span style="font-weight: bold;"><br></span></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CEC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change<span style="font-weight: bold;"> ErrorCode </span>field declaration from&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">uint32_t &nbsp;to</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> __IO uint32_t</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">correct CEC state:&nbsp;Ready to Receive state lost upon Transmission end</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL&nbsp;COMP&nbsp;</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">State&nbsp;</span>field is now declared as&nbsp;uint32_t instead of <span style="font-weight: bold;">enum&nbsp;HAL_COMP_StateTypeDef</span> to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change HAL_COMP_GetState() type declaration from HAL_COMP_StateTypeDef to uint32_t </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to fix C++ compilation issue</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CRC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Wrong @ref in CRCLength field description for documentation generation&nbsp;</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL DAC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_DAC_Stop_DMA() code clean up</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Use of internal macro MODIFY_REG() to update CR register<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL DMA&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DMA channel remap register renamed for compatibility with other STM32 devices.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Correct wrong comments in __HAL_DMA_GET_FLAG and __HAL_DMA_CLEAR_FLAG macros description</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL FLASH&nbsp;</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix in macro IS_OPTIONBYTE(VALUE) when all option_OB are selected</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum&nbsp;FLASH_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change HAL_FLASH_GetError() type declaration from&nbsp;FLASH_ErrorTypeDef to uint32_t </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Clean the error context to FLASH_ERROR_NONE before starting new Flash operation</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Put all the clear flags in the FLASH_SetSerrorCode()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Stop&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the programming procedure in case of error detected </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">in HAL_FLASH_Program()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Check error before doing new procedure in&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_FLASH_IRQhandler() </span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL GPIO&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">correct Typo in 'How to use this driver' section &amp; update comments</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add assert on GPIO PIN in HAL_GPIO_DeInit()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add assert </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">on GPIO AF instance to protect HAL_GPIO_Init() </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">from impossible AF configuration</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Rename internal macro GET_GPIO_INDEX() into GPIO_GET_INDEX()<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Reset </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Interrupt mode registers&nbsp;only in HAL_GPIO_DeInit()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2C</span></span><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_I2C_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2S&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_I2S_ErrorTypeDef</span> to fix C++ compilation issue.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change <span style="font-weight: bold;">HAL_I2S_GetError</span>() type declaration from&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_I2S_ErrorTypeDef </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> to uint32_t </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to fix C++ compilation issue.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add use of UNUSED(tmpreg) in __HAL_I2S_CLEAR_OVRFLAG() &amp; __HAL_I2S_CLEAR_UDRFLAG to </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">fix&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Unused variable" warning w/ TrueSTUDIO</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Typo in 'I2S HAL driver macros list' section of stm32f0xx_hal_i2s.c</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Missing doxygen tags for I2S_HandleTypeDef fields description (documentation generation)</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL IRDA&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_IRDA_ErrorTypeDef</span> to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Missing doxygen tags for IRDA_HandleTypeDef fields description</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PWR&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new API&nbsp;to manage&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SLEEPONEXIT and SEVONPEND bits of SCR register:</span></li></ul></ul><ul style="margin-left: 80px;"><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_PWR_DisableSleepOnExit()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_PWR_EnableSleepOnExit()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_PWR_EnableSEVOnPend()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_PWR_DisableSEVOnPend()</span></li></ul><ul style="margin-top: 0cm; list-style-type: square;"><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Removed useless regulator parameter setting for F0 family&nbsp;in core of HAL_PWR_EnterSLEEPMode()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RCC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add a comment in the 'How to use this driver' section to mention the Peripheral enable delay</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Move __HAL_RCC_USART2_CONFIG() &amp;&nbsp;__HAL_RCC_GET_USART2_SOURCE() from stm32f0xx_hal_rcc.h to </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f0xx_hal_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">rcc_ex.h since this feature is not supported on all F0 devices </span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change <span style="font-weight: bold;">HAL_RCCEx_CRSWaitSynchronization</span>() type declaration from </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">RCC_CRSStatusTypeDef</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> to uint32_t </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to fix C++ compilation issue</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RTC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Enhance @note describing the use of HAL RTC APIs&nbsp;</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMARTCARD</span></span><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_SMARTCARD_ErrorTypeDef</span> to fix C++ compilation issue</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMBUS</span></span><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode &amp; PreviousState </span>fields are now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_SMBUS_ErrorTypeDef</span> &amp; <span style="font-weight: bold;">HAL_SMBUS_StateTypeDef </span>to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change <span style="font-weight: bold;">HAL_SMBUS_GetState</span>() type declaration from&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_SMBUS_StateTypeDef<span style="font-weight: bold;"> </span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> to uint32_t </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to fix C++ compilation issue</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SPI&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_SPI_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">fix&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">"Unused variable" warning w/ TrueSTUDIO</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add DMA circular mode support on SPI HAL driver.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Internal
-fucntion renaming:&nbsp;HAL_SPI_DMATransmitCplt(),
-HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() &amp;
-HAL_SPI_DMAError() renamed respectively into </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SPI_DMATransmitCplt(),&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SPI_DMAReceiveCplt(),&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SPI_DMATransmitReceiveCplt() &amp;&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SPI_DMAError().</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Remove unused HAL_StatusTypeDef SPI_EndRxTxTransaction() prototype<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">uint32_t driver alignment for compatibility with other STM32 devices<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new API <span style="font-weight: bold;">HAL_SPI_GetError</span>(), which was missing on STM32F0xx family<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL UART/USART&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">structure UART_WakeUpTypeDef moved to stm32f0xx_hal_uart_ex.h since wakeup feature is not available on all F0 devices.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_U(S)ART_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">unused HAL_USART_SetConfig() prototype to be removed from stm32f0xx_hal_usart.h</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add missing API&nbsp;HAL_StatusTypeDef <span style="font-weight: bold;">HAL_LIN_SendBreak</span>()<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">correct wrong USART_IT_CM value</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">correct issue with Lin mode data length</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new value for&nbsp;Stop bit definition: UART_STOPBITS_1_5<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL USB&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span><span style="font-weight: bold;"></span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Wrong comment in HAL_PCD_Dev(Connect/Disconnect) functions description</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Correct _HAL_PCD_CLEAR_FLAG() macros definition <br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL WWDG&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new&nbsp;macro to manage WWDG IT &amp; correction:</span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_WWDG_DISABLE_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_WWDG_GET_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">__HAL_WWDG_GET_IT_SOURCE()</span><br></span></li></ul></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0
-/ 03-October-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL generic</span>&nbsp;</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">general improvement of Doxygen Tags for CHM UM generation</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new devices </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">STM32F091xC</span>,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">STM32F098xx</span> in </span><span style="font-size: 10pt; font-family: Verdana;">STM32F0xx HAL drivers</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">minor corrections for Pdf/Chm UM generation</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Correction for MISRA&nbsp;</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">[F098xx] Remove PVD IT line wrapper</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">FLAG&amp;IT assert macros to be removed</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Bad macro name in stm32F0xx_hal.c/.h files</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">uint32_t Alignement&nbsp;in HAL driver</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL </span>update&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">(for </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F091xC/</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F098xx)</span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new define for HAL IRDA Enveloppe source Selection</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro IS_HAL_SYSCFG_IRDA_ENV_SEL()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines for ISR Wrapper (HAL_SYSCFG_ITLINE0, etc..)</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_GET_PENDING_IT()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_SYSCFG_IRDA_ENV_SELECTION()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_SYSCFG_GET_IRDA_ENV_SELECTION()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL COMP&nbsp;</span></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Missing assert param IS_COMP_TRIGGERMODE</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL Cortex&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">remove Macro not supported by cortex-M0 in stm32f0xx.h</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL DMA&nbsp;</span></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines for DMAx Channel remapping (DMAx_CHANNELx_RMP)</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines for </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DMAx channels </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">remap bit field definition</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macros: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">IS_HAL_DMA1_REMAP(), IS_HAL_DMA2_REMAP()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">: __HAL_DMA_GET_TC_FLAG_INDEX(), that returns specified transfer complete flag index</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_DMA_GET_HT_FLAG_INDEX(), that returns specified half transfer complete flag index</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">: __HAL_DMA_GET_TE_FLAG_INDEX(), that returns specified transfer error flag index</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_DMA_GET_FLAG()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_DMA_CLEAR_FLAG()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_DMA1_REMAP(), __HAL_DMA2_REMAP()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Bit definition name error for&nbsp;HAL_DMA1_CH2 remap on STM32F091xC</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_DMA_PollForTransfer updated</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL GPIO&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">BSRR regsiter should not be split in BSRRH/BSRRL</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">rework GPIO_GET_SOURCE</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines for AF functions selection</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2S&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Supp ClockSource in Init</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL IRDA&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Incorrect definition for IS_IRDA_REQUEST_PARAMETER macro</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL IWDG&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Use WRITE_REG instead of SET_BIT</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PWR&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Functions for VDDIO2 management missing in all F09xx, F07xx, F04xx</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Calibri;">PVD feature need falling/rising Event modes</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update defines name&nbsp;PWR_MODE_EVT/PWR_MODE_IT_RISING/PWR_MODE_IT_FALLING/PWR_MODE_IT_RISING_FALLING&nbsp;to PWR_<span style="font-weight: bold;">PVD</span>_MODE_<span style="font-weight: bold;">NORMAL/</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PWR_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">PVD</span>_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">MODE_IT_RISING/PWR_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">PVD</span>_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">MODE_IT_FALLING/PWR_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">PVD</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_MODE_IT_RISING_FALLING</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines PWR_PVD_MODE_EVENT_RISING, PWR_PVD_MODE_EVENT_FALLING, PWR_PVD_MODE_EVENT_RISING_FALLING<span style="font-weight: bold;"><br></span></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update macro IS_PWR_PVD_MODE()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change macro name: __HAL</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_PVD_EXTI_ENABLE_IT(), __HAL</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_PVD_EXTI_DISABLE_IT(), __HAL</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_PVD_EXTI_GENERATE_SWIT(), __HAL</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_PVD_EXTI_GET_FLAG(),&nbsp; __HAL</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_PVD_EXTI_CLEAR_FLAG()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
-new macro __HAL_PWR_PVD_EXTI_ENABLE_EVENT(),
-__HAL_PWR_PVD_EXTI_DISABLE_EVENT(),
-__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(),
-__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RCC&nbsp;</span></span><ul><li><span style="font-family: Calibri;">Defect correction:</span><span style="font-family: Calibri;"></span></li><ul><li><span style="font-family: Calibri;">HAL_RCC_OscConfig: HSERDY has to be checked also in by pass mode</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li></ul><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F091xC/</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F098xx</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li></ul><ul><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">New structure RCC_PeriphCLKInitTypeDef</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
-defines for RCC new peripheral clock selection: RCC_PERIPHCLK_USART1,
-RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_CEC,
-RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USART3</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add macro IS_RCC_PERIPHCLK()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
-defines for USART3 clock source selection (RCC_USART3CLKSOURCE_PCLK1,
-RCC_USART3CLKSOURCE_SYSCLK, CC_USART3CLKSOURCE_LSE,
-CC_USART3CLKSOURCE_HSI</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add macro IS_RCC_USART3CLKSOURCE()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add macro __HAL_RCC_GET_USART3_SOURCE()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add macro __HAL_RCC_USART3_CONFIG()<br></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">add clock enable macros for new UART: __USART5_CLK_ENABLE,&nbsp; __USART6_CLK_ENABLE, __USART7_CLK_ENABLE, __USART8_CLK_ENABLE</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">add clock disable macros for new UART: __USART5_CLK_DISABLE,&nbsp; __USART6_CLK_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DISABLE</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">, __USART7_CLK_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DISABLE</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">, __USART8_CLK_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DISABLE</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">add Force reset macros for new UART: __USART5_FORCE_RESET, __USART6_FORCE_RESET, __USART7_FORCE_RESET, __USART8_FORCE_RESET</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">add Release reset macros for new UART: __USART5_RELEASE_RESET, __USART6_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">RELEASE</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_RESET, __USART7_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">RELEASE</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_RESET, __USART8_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">RELEASE</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_RESET</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;</span></li></ul></ul></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMARTCARD&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change&nbsp;SMARTCARD_AdvFeatureConfig() from exported to static private function</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F091xC/</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F098xx:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro __HAL_SMARTCARD_GETCLOCKSOURCE() for USART1, USART2, USART3, USAR</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMBUS&nbsp;</span>&nbsp;</span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change&nbsp;SMARTCARD_AdvFeatureConfig() from exported to static private function</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SPI&nbsp;</span></span></p></li><ul style="font-family: Lucida Sans;" class="MsoChpDefault"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Function HAL_SPI_TransmitReceive muse use SPI_FLAG_RXNE to read CRC</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Function HAL_SPI_IRQHandler, in case of error the state must be reset to ready<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL TIM&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Missed/Unused assert param to be added/removed</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Trigger interrupt should be activated when working with a slave mode</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Break interrupt should be activated in HAL_TIMEx_OCN_Start_IT</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Wrong CCMR register cleared in HAL_TIM_IRQHandler for Input Capture event Channel 3 and 4</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">missing assert in HAL_TIMEx_ConfigBreakDeadTime</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">URS_ENABLE/ URS_DISABLE macros</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL UART/USART&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change UART TX-IT implementation to remove WaitOnFlag in ISR</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F091xC/</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F098xx:</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro __HAL_UART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro __HAL_USART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL USB&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Bad IN/OUT EndPoint parameter array size</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL WWDG&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">improvements from other families</span></p></li></ul></ul><div style="margin-left: 40px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Defect Correction<br><br></span></u></b>
-
-<table class="MsoNormalTable" style="width: 652.45pt; border-collapse: collapse;" border="0" cellpadding="0" cellspacing="0" width="870">
- <tbody><tr style="height: 15pt;">
-  
-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 124.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="166">
-  <p class="MsoNormal"><span style="color: black;">STM32F0xx_HAL_Driver<o:p></o:p></span></p>
-  </td>
-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 49.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="66">
-  <p class="MsoNormal"><span style="color: black;">Defect<o:p></o:p></span></p>
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-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 68.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="92">
-  <p class="MsoNormal"><span style="color: black;">PWR<o:p></o:p></span></p>
-  </td>
-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 366.75pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="489">
-  <p class="MsoNormal"><span style="color: black;">PVD feature need falling/rising Event modes<o:p></o:p></span></p>
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- </tr>
- <tr style="height: 15pt;">
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-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 124.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="166">
-  <p class="MsoNormal"><span style="color: black;">STM32F0xx_HAL_Driver<o:p></o:p></span></p>
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-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 49.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="66">
-  <p class="MsoNormal"><span style="color: black;">Defect<o:p></o:p></span></p>
-  </td>
-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 68.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="92">
-  <p class="MsoNormal"><span style="color: black;">COMP<o:p></o:p></span></p>
-  </td>
-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 366.75pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="489">
-  <p class="MsoNormal"><span style="color: black;">Missing assert param IS_COMP_TRIGGERMODE&nbsp;<o:p></o:p></span></p>
-  </td>
- </tr>
- 
- <tr style="height: 15pt;">
-  
-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 124.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="166">
-  <p class="MsoNormal"><span style="color: black;">STM32F0xx_HAL_Driver<o:p></o:p></span></p>
-  </td>
-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 49.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="66">
-  <p class="MsoNormal"><span style="color: black;">Defect<o:p></o:p></span></p>
-  </td>
-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 68.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="92">
-  <p class="MsoNormal"><span style="color: black;">RCC<o:p></o:p></span></p>
-  </td>
-  <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 366.75pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="489">
-  <p class="MsoNormal"><span style="color: black;">HAL_RCC_OscConfig: HSERDY has to be checked also in by
-  pass mode<o:p></o:p></span></p>
-  </td>
- </tr>
-</tbody></table>
-<br></div><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1
-/ 18-June-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL generic</span> update<br></span></p><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix flag clear procedure: use atomic write operation </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">"=" </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">instead of ready-modify-write operation "|=" or "&amp;="</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix
-on Timeout management, Timeout value set to 0 passed to API
-automatically exits the function after checking the flag without any
-wait.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
-new macro __HAL_RESET_HANDLE_STATE to reset a given handle state.</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CEC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Process no more locked during the transmission in interrupt mode.</span>&nbsp;</li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL COMP</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add <span style="font-style: italic;">NonInvertingInput</span> field in the <span style="font-style: italic;">COMP_InitTypeDef</span> structure.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines <span style="font-style: italic;">COMP_NONINVERTINGINPUT_IO1</span> and <span style="font-style: italic;">COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED</span><br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL DMA</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix in&nbsp;<span style="font-style: italic;">HAL_DMA_PollForTransfer()</span> to set error code <span style="font-style: italic;">HAL_DMA_ERROR_TE </span>in case of <span style="font-style: italic;">HAL_ERROR</span> status</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2C</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
-management of NACK event in Master transmitter mode and Slave
-transmitter/receiver modes (only in polling mode), in that case the
-current transfer is stopped.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2S</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">I2S clock source change: new define <span style="font-style: italic;">I2S_CLOCK_SYSCLK</span>, remove<span style="font-style: italic;"> I2S_CLOCK_PLL</span></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Improvement done in I2S transfer/receive processes <br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL IRDA</span> update<br></span></p><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new enum typedef <span style="font-style: italic;">IRDA_ClockSourceTypeDef</span></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro <span style="font-style: italic;">__HAL_IRDA_GETCLOCKSOURCE</span></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_IRDA_Transmit_IT()</span> to enable IRDA_IT_TXE instead of IRDA_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Process no more locked during the transmission in interrupt mode.</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-  <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PCD </span>update</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></p>
-              </li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-    <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro <span style="font-style: italic;">__HAL_USB_EXTI_GENERATE_SWIT</span></span></p>
-  </li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PWR</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix in <span style="font-style: italic;">HAL_PWR_EnterSTANDBYMode()</span> to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RCC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add USB peripheral and clocking macros for STM32F078xx device.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix HSI Calibration issue when selected as SYSCLK </span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMARTCARD</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_SMARTCARD_Transmit_IT()</span> to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Process no more locked during the transmission in interrupt mode.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMBUS</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix Slave acknowledge issue: Slave should ack each bit and so stretch the line till the bit is not ack</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL TIM</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix macro __HAL_TIM_PRESCALER</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL TSC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix define&nbsp;<span style="font-style: italic;">TSC_ACQ_MODE_SYNCHRO</span></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL UART</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_LIN_Init()</span> parameter BreakDetectLength to uint32_t</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_UART_Transmit_IT()</span> to enable UART_IT_TXE instead of UART_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Process no more locked during the transmission in interrupt mode.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL USART</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change <span style="font-style: italic;">USART_InitTypeDef</span> fields to uint32_t type</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Rename __USART_ENABLE and __USART_DISABLE macros to respectively </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_USART_ENABLE and __HAL_USART_DISABLE</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_USART_Transmit_IT()</span> to enable USART_IT_TXE instead of USART_IT_TC.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Process no more locked during the transmission in interrupt mode.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_USART_TransmitReceive_DMA()</span> to manage DMA half transfer mode</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
-/ 20-May-2014<o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official
-release of STM32F0xx HAL drivers for </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F030x4/x6, </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F030x8,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F031x4/x6</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">, &nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F051x4/x6/x8</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F071x8/xB,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"> </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F042x4/x6,
-</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F072x8/xB, &nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F038xx,
-</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"> STM32F048xx</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F058xx and STM32F078xx
-</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">devices.</span></li></ul><br><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-<div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistribution
-and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:</span><br>
-</font>
-<ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
-of source code must retain the above copyright notice, this list of
-conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
-in binary form must reproduce the above copyright notice, this list of
-conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the
-documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the
-name of STMicroelectronics nor the names of its contributors may be
-used to endorse or promote products derived</span></font><small><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> from this software without specific prior written permission.</span></small><br></li></ol><font size="-1">
-<span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
-<span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font> </div>
-<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span>
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;"> Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
-</td>
-</tr>
-<tr><td style="padding: 0in;" valign="top"></td></tr></tbody>
-</table>
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
-</div>
-</body></html>
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--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32_hal_legacy.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
+  * @version V1.8.1
+  * @date    14-April-2017
   * @brief   This file contains aliases definition for the STM32Cube HAL constants 
   *          macros and functions maintained for legacy purpose.
   ******************************************************************************
@@ -138,7 +138,9 @@
 #define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
 #define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
 #define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
-#define COMP_LPTIMCONNECTION_ENABLED   COMP_LPTIMCONNECTION_IN1_ENABLED    /*!< COMPX output is connected to LPTIM input 1 */
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
 #define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
 #if defined(STM32F373xC) || defined(STM32F378xx)
 #define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
@@ -265,7 +267,6 @@
 #define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7      
 #define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67  
 #define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67 
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32  
 #define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76   
 #define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6     
 #define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7      
@@ -457,6 +458,78 @@
   * @}
   */
 
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+  
+#if defined(STM32H7)
+ #define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+ #define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+ #define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+ #define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+ #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+ #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+
+  #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 
+  #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 
+
+ #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+ #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+ #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+ #define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+ #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+ #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+ #define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+ #define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+ #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+
+#endif /* STM32H7  */
+  
+  
+/**
+  * @}
+  */ 
+  
+  
 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
   * @{
   */
@@ -670,7 +743,6 @@
 #define FORMAT_BCD                  RTC_FORMAT_BCD
 
 #define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
 #define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
 #define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
 #define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
@@ -678,9 +750,6 @@
 #define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
 #define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE 
 #define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE 
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
 #define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT 
 #define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT 
 
@@ -1312,7 +1381,6 @@
 #define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
 #define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
 #define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
 #define __HAL_ADC_JSQR                                   ADC_JSQR
 
 #define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
@@ -1785,20 +1853,20 @@
 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
 
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  
-#define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
@@ -1815,7 +1883,7 @@
 #define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
 #define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
 #define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
 #define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
@@ -2410,7 +2478,6 @@
 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 
 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED   
-#define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET  
 #define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  
 #define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
 #define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  
@@ -2443,8 +2510,6 @@
 #define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
 #define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
 #define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
 #define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
 #define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
 #define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
@@ -2466,8 +2531,6 @@
 #define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
 #define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
 #define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
 #define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
 #define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
 #define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
@@ -2692,7 +2755,10 @@
 #define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
 #define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
 
+#if defined(STM32WB)
+#else
 #define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
 
 #define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
 #define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
@@ -2788,7 +2854,6 @@
 #define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
 #define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
 #define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
-
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   HAL module driver.
   *          This is the common part of the HAL initialization
   *
@@ -70,10 +68,10 @@
   * @{
   */
 /** 
-  * @brief STM32F0xx HAL Driver version number V1.5.0
+  * @brief STM32F0xx HAL Driver version number V1.7.0
   */
 #define __STM32F0xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F0xx_HAL_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __STM32F0xx_HAL_VERSION_SUB1   (0x07) /*!< [23:16] sub1 version */
 #define __STM32F0xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32F0xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F0xx_HAL_VERSION         ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\
@@ -232,7 +230,7 @@
   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
   *       The function is declared as __Weak  to be overwritten  in case of other
   *       implementation  in user file.
-  * @param TickPriority: Tick interrupt priority.
+  * @param TickPriority Tick interrupt priority.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
@@ -307,14 +305,21 @@
   *       is incremented.
   * @note ThiS function is declared as __weak to be overwritten in case of other
   *       implementations in user file.
-  * @param Delay: specifies the delay time length, in milliseconds.
+  * @param Delay specifies the delay time length, in milliseconds.
   * @retval None
   */
 __weak void HAL_Delay(__IO uint32_t Delay)
 {
-  uint32_t tickstart = 0U;
-  tickstart = HAL_GetTick();
-  while((HAL_GetTick() - tickstart) < Delay)
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+  
+  /* Add a period to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+     wait++;
+  }
+  
+  while((HAL_GetTick() - tickstart) < wait)
   {
   }
 }
@@ -380,6 +385,33 @@
 }
 
 /**
+  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+   return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+   return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+   return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
   * @brief  Enable the Debug Module during STOP mode       
   * @retval None
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   This file contains all the functions prototypes for the HAL 
   *          module driver.
   ******************************************************************************
@@ -378,7 +376,7 @@
 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
 /** @defgroup HAL_Pin_remap HAL Pin remap 
   * @brief  Pin remapping enable/disable macros
-  * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping
+  * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping
   * @{   
   */
 #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__)          do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__)));                 \
@@ -393,7 +391,7 @@
 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
 
 /** @brief  Fast-mode Plus driving capability enable/disable macros
-  * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
+  * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
   *                          That you can find above these macros.
   */
 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
@@ -482,7 +480,7 @@
 /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
   * @brief  selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
   * @note This feature is applicable on STM32F09x
-  * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL
+  * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL
   * @{  
   */
 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__)  do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
@@ -532,6 +530,9 @@
 uint32_t          HAL_GetHalVersion(void);
 uint32_t          HAL_GetREVID(void);
 uint32_t          HAL_GetDEVID(void);
+uint32_t          HAL_GetUIDw0(void);
+uint32_t          HAL_GetUIDw1(void);
+uint32_t          HAL_GetUIDw2(void);
 void              HAL_DBGMCU_EnableDBGStopMode(void);
 void              HAL_DBGMCU_DisableDBGStopMode(void);
 void              HAL_DBGMCU_EnableDBGStandbyMode(void);

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_adc.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC)
   *          peripheral:
@@ -355,7 +353,7 @@
   * @note   This function configures the ADC within 2 scopes: scope of entire 
   *         ADC and scope of regular group. For parameters details, see comments 
   *         of structure "ADC_InitTypeDef".
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
@@ -581,7 +579,7 @@
   *         bypassed without error reporting: it can be the intended behaviour in
   *         case of reset of a single ADC while the other ADCs sharing the same 
   *         common group is still running.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
@@ -697,7 +695,7 @@
     
 /**
   * @brief  Initializes the ADC MSP.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
@@ -712,7 +710,7 @@
 
 /**
   * @brief  DeInitializes the ADC MSP.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
@@ -754,7 +752,7 @@
 /**
   * @brief  Enables ADC, starts conversion of regular group.
   *         Interruptions enabled in this function: None.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
@@ -819,7 +817,7 @@
 
 /**
   * @brief  Stop ADC conversion of regular group, disable ADC peripheral.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
@@ -872,8 +870,8 @@
   *         performed on each conversion. Nevertheless, polling can still 
   *         be performed on the complete sequence (ADC init
   *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
-  * @param  hadc: ADC handle
-  * @param  Timeout: Timeout value in millisecond.
+  * @param  hadc ADC handle
+  * @param  Timeout Timeout value in millisecond.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
@@ -988,12 +986,12 @@
 
 /**
   * @brief  Poll for conversion event.
-  * @param  hadc: ADC handle
-  * @param  EventType: the ADC event type.
+  * @param  hadc ADC handle
+  * @param  EventType the ADC event type.
   *          This parameter can be one of the following values:
   *            @arg ADC_AWD_EVENT: ADC Analog watchdog event
   *            @arg ADC_OVR_EVENT: ADC Overrun event
-  * @param  Timeout: Timeout value in millisecond.
+  * @param  Timeout Timeout value in millisecond.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
@@ -1069,7 +1067,7 @@
   *            parameter "EOCSelection"
   *          - overrun (if available)
   *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
@@ -1150,7 +1148,7 @@
 /**
   * @brief  Stop ADC conversion of regular group, disable interruption of 
   *         end-of-conversion, disable ADC peripheral.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
@@ -1201,9 +1199,9 @@
   *          - DMA half transfer
   *          - overrun
   *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc: ADC handle
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
+  * @param  hadc ADC handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from ADC peripheral to memory.
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@@ -1292,7 +1290,7 @@
   * @brief  Stop ADC conversion of regular group, disable ADC DMA transfer, disable 
   *         ADC peripheral.
   *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
@@ -1374,7 +1372,7 @@
   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
   *         model polling: @ref HAL_ADC_PollForConversion() 
   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval ADC group regular conversion data
   */
 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
@@ -1391,7 +1389,7 @@
 
 /**
   * @brief  Handles ADC interrupt request.  
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
@@ -1507,7 +1505,7 @@
 
 /**
   * @brief  Conversion complete callback in non blocking mode 
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
@@ -1522,7 +1520,7 @@
 
 /**
   * @brief  Conversion DMA half-transfer callback in non blocking mode 
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
@@ -1537,7 +1535,7 @@
 
 /**
   * @brief  Analog watchdog callback in non blocking mode. 
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
@@ -1553,7 +1551,7 @@
 /**
   * @brief  ADC error callback in non blocking mode
   *        (ADC conversion with interruption or transfer by DMA)
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
@@ -1606,8 +1604,8 @@
   *         The setting of these parameters is conditioned to ADC state.
   *         For parameters constraints, see comments of structure 
   *         "ADC_ChannelConfTypeDef".
-  * @param  hadc: ADC handle
-  * @param  sConfig: Structure of ADC channel for regular group.
+  * @param  hadc ADC handle
+  * @param  sConfig Structure of ADC channel for regular group.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
@@ -1739,8 +1737,8 @@
   *         The setting of these parameters is conditioned to ADC state.
   *         For parameters constraints, see comments of structure 
   *         "ADC_AnalogWDGConfTypeDef".
-  * @param  hadc: ADC handle
-  * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
+  * @param  hadc ADC handle
+  * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
@@ -1862,7 +1860,7 @@
   *         For example:                                                         
   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL state
   */
 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
@@ -1876,7 +1874,7 @@
 
 /**
   * @brief  Return the ADC error code
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval ADC Error Code
   */
 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
@@ -1906,7 +1904,7 @@
   *         flag ADC_FLAG_RDY is not usable.
   *         Therefore, this function must be called under condition of
   *         "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
@@ -1971,7 +1969,7 @@
   * @brief  Disable the selected ADC.
   * @note   Prerequisite condition to use this function: ADC conversions must be
   *         stopped.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
@@ -2028,7 +2026,7 @@
   * @brief  Stop ADC conversion.
   * @note   Prerequisite condition to use this function: ADC conversions must be
   *         stopped to disable the ADC.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
@@ -2079,7 +2077,7 @@
 
 /**
   * @brief  DMA transfer complete callback. 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
@@ -2140,7 +2138,7 @@
 
 /**
   * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
@@ -2154,7 +2152,7 @@
 
 /**
   * @brief  DMA error callback 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void ADC_DMAError(DMA_HandleTypeDef *hdma)   

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file containing functions prototypes of ADC HAL library.
   ******************************************************************************
   * @attention
@@ -332,7 +330,6 @@
   */ 
 #define ADC_EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)
 #define ADC_EOC_SEQ_CONV            ((uint32_t) ADC_ISR_EOS)
-#define ADC_EOC_SINGLE_SEQ_CONV     ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS))  /*!< reserved for future use */
 /**
   * @}
   */ 
@@ -463,7 +460,7 @@
 
 /**
   * @brief Enable the ADC peripheral
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #define __HAL_ADC_ENABLE(__HANDLE__)                                           \
@@ -471,7 +468,7 @@
 
 /**
   * @brief Disable the ADC peripheral
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #define __HAL_ADC_DISABLE(__HANDLE__)                                          \
@@ -482,8 +479,8 @@
 
 /**
   * @brief Enable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
   *          This parameter can be any combination of the following values:
   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
   *            @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
@@ -498,8 +495,8 @@
 
 /**
   * @brief Disable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
   *          This parameter can be any combination of the following values:
   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
   *            @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
@@ -513,8 +510,8 @@
   (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
 
 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC interrupt source to check
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC interrupt source to check
   *          This parameter can be any combination of the following values:
   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
   *            @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
@@ -529,8 +526,8 @@
     
 /**
   * @brief Get the selected ADC's flag status.
-  * @param __HANDLE__: ADC handle
-  * @param __FLAG__: ADC flag
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
   *          This parameter can be any combination of the following values:
   *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
   *            @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
@@ -545,8 +542,8 @@
 
 /**
   * @brief Clear the ADC's pending flags
-  * @param __HANDLE__: ADC handle
-  * @param __FLAG__: ADC flag
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
   *          This parameter can be any combination of the following values:
   *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
   *            @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
@@ -561,7 +558,7 @@
   (((__HANDLE__)->Instance->ISR) = (__FLAG__))
 
 /** @brief  Reset ADC handle state
-  * @param  __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval None
   */
 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
@@ -583,7 +580,7 @@
 
 /**
   * @brief Verification of hardware constraints before ADC can be enabled
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
   */
 #define ADC_ENABLING_CONDITIONS(__HANDLE__)                                        \
@@ -594,7 +591,7 @@
 
 /**
   * @brief Verification of hardware constraints before ADC can be disabled
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
   */
 #define ADC_DISABLING_CONDITIONS(__HANDLE__)                                   \
@@ -604,7 +601,7 @@
 
 /**
   * @brief Verification of ADC state: enabled or disabled
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (ADC enabled) or RESET (ADC disabled)
   */
 /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are   */
@@ -619,7 +616,7 @@
 /**
   * @brief Test if conversion trigger of regular group is software start
   *        or external trigger.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (software start) or RESET (external trigger)
   */
 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
@@ -627,7 +624,7 @@
 
 /**
   * @brief Check if no conversion on going on regular group
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (conversion is on going) or RESET (no conversion is on going)
   */
 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                          \
@@ -637,7 +634,7 @@
 /**
   * @brief Returns resolution bits in CFGR1 register: RES[1:0].
   *        Returned value is among parameters to @ref ADC_Resolution.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #define ADC_GET_RESOLUTION(__HANDLE__)                                         \
@@ -646,7 +643,7 @@
 /**
   * @brief Returns ADC sample time bits in SMPR register: SMP[2:0].
   *        Returned value is among parameters to @ref ADC_Resolution.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #define ADC_GET_SAMPLINGTIME(__HANDLE__)                                       \
@@ -663,7 +660,7 @@
 
 /**
   * @brief Clear ADC error code (set it to error code: "no error")
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
@@ -672,7 +669,7 @@
 
 /**
   * @brief Configure the channel number into channel selection register
-  * @param _CHANNEL_: ADC Channel
+  * @param _CHANNEL_ ADC Channel
   * @retval None
   */
 /* This function converts ADC channels from numbers (see defgroup ADC_channels) 
@@ -702,7 +699,7 @@
 
 /**
   * @brief Set the ADC's sample time
-  * @param _SAMPLETIME_: Sample time parameter.
+  * @param _SAMPLETIME_ Sample time parameter.
   * @retval None
   */
 /* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter       */
@@ -715,7 +712,7 @@
 
 /**
   * @brief Set the Analog Watchdog 1 channel.
-  * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1.
+  * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1.
   * @retval None
   */
 #define ADC_CFGR_AWDCH(_CHANNEL_)                                              \
@@ -723,7 +720,7 @@
 
 /**
   * @brief Enable ADC discontinuous conversion mode for regular group
-  * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
+  * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode.
   * @retval None
   */
 #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_)                 \
@@ -731,7 +728,7 @@
   
 /**
   * @brief Enable the ADC auto off mode.
-  * @param _AUTOOFF_: Auto off bit enable or disable.
+  * @param _AUTOOFF_ Auto off bit enable or disable.
   * @retval None
   */
 #define ADC_CFGR1_AUTOOFF(_AUTOOFF_)                                           \
@@ -739,7 +736,7 @@
       
 /**
   * @brief Enable the ADC auto delay mode.
-  * @param _AUTOWAIT_: Auto delay bit enable or disable.
+  * @param _AUTOWAIT_ Auto delay bit enable or disable.
   * @retval None
   */
 #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_)                                         \
@@ -747,7 +744,7 @@
 
 /**
   * @brief Enable ADC continuous conversion mode.
-  * @param _CONTINUOUS_MODE_: Continuous mode.
+  * @param _CONTINUOUS_MODE_ Continuous mode.
   * @retval None
   */
 #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_)                                \
@@ -755,7 +752,7 @@
     
 /**
   * @brief Enable ADC overrun mode.
-  * @param _OVERRUN_MODE_: Overrun mode.
+  * @param _OVERRUN_MODE_ Overrun mode.
   * @retval Overun bit setting to be programmed into CFGR register
   */
 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant                   */
@@ -768,7 +765,7 @@
 
 /**
   * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
-  * @param _SCAN_MODE_: Scan conversion mode.
+  * @param _SCAN_MODE_ Scan conversion mode.
   * @retval None
   */
 /* Note: Scan mode set using this macro (instead of parameter direct set)     */
@@ -782,7 +779,7 @@
 
 /**
   * @brief Enable the ADC DMA continuous request.
-  * @param _DMACONTREQ_MODE_: DMA continuous request mode.
+  * @param _DMACONTREQ_MODE_ DMA continuous request mode.
   * @retval None
   */
 #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_)                                \
@@ -790,7 +787,7 @@
 
 /**
   * @brief Configure the analog watchdog high threshold into register TR.
-  * @param _Threshold_: Threshold value
+  * @param _Threshold_ Threshold value
   * @retval None
   */
 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_)                                     \
@@ -804,8 +801,8 @@
   *        If resolution 8 bits, shift of 4 ranks on the left.
   *        If resolution 6 bits, shift of 6 ranks on the left.
   *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
-  * @param __HANDLE__: ADC handle
-  * @param _Threshold_: Value to be shifted
+  * @param __HANDLE__ ADC handle
+  * @param _Threshold_ Value to be shifted
   * @retval None
   */
 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_)            \
@@ -833,8 +830,7 @@
                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
 
 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
-                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)       || \
-                                             ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV)  )
+                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)  )
 
 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED)  || \
                              ((OVR) == ADC_OVR_DATA_OVERWRITTEN)  )

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,15 +2,13 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_adc_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC)
   *          peripheral:
   *           + Operation functions
   *             ++ Calibration (ADC automatic self-calibration)
   *          Other functions (generic functions) are available in file 
-  *          "stm32l1xx_hal_adc.c".
+  *          "stm32f0xx_hal_adc.c".
   *
   @verbatim
   [..] 
@@ -109,13 +107,14 @@
   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
   * @note   Calibration factor can be read after calibration, using function
   *         HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
 {
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  uint32_t tickstart=0U;
+  uint32_t tickstart = 0U;
+  uint32_t backup_setting_adc_dma_transfer = 0; /* Note: Variable not declared as volatile because register read is already declared as volatile */
   
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -131,6 +130,15 @@
                       HAL_ADC_STATE_REG_BUSY,
                       HAL_ADC_STATE_BUSY_INTERNAL);
     
+    /* Disable ADC DMA transfer request during calibration */
+    /* Note: Specificity of this STM32 serie: Calibration factor is           */
+    /*       available in data register and also transfered by DMA.           */
+    /*       To not insert ADC calibration factor among ADC conversion data   */
+    /*       in array variable, DMA transfer must be disabled during          */
+    /*       calibration.                                                     */
+    backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
+    CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
+
     /* Start ADC calibration */
     hadc->Instance->CR |= ADC_CR_ADCAL;
 
@@ -153,6 +161,9 @@
       }
     }
     
+    /* Restore ADC DMA transfer request after calibration */
+    SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
+
     /* Set ADC state */
     ADC_STATE_CLR_SET(hadc->State,
                       HAL_ADC_STATE_BUSY_INTERNAL,

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_adc_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of ADC HAL Extension module.
   ******************************************************************************
   * @attention
@@ -153,7 +151,7 @@
   *        VrefInt/TempSensor/Vbat
   *        Note: On STM32F0, availability of internal channel Vbat depends on
   *              devices lines.
-  * @param __CHANNEL__: ADC channel
+  * @param __CHANNEL__ ADC channel
   * @retval None
   */
 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
@@ -175,7 +173,7 @@
   *        VrefInt/TempSensor/Vbat.
   *        Note: On STM32F0, availability of internal channel Vbat depends on
   *              devices lines.
-  * @param __CHANNEL__: ADC channel
+  * @param __CHANNEL__ ADC channel
   * @retval Bit of register ADC_CCR
   */
 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_can.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   CAN HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Controller Area Network (CAN) peripheral:
@@ -28,9 +26,13 @@
       (#) Initialise and configure the CAN using HAL_CAN_Init() function.   
                  
       (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
-           
+
+      (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
+
       (#) Receive a CAN frame using HAL_CAN_Receive() function.
 
+      (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+
      *** Polling mode IO operation ***
      =================================
      [..]    
@@ -157,10 +159,10 @@
   */
   
 /**
-  * @brief  Initializes the CAN peripheral according to the specified
-  *         parameters in the CAN_InitStruct.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
+  * @brief Initializes the CAN peripheral according to the specified
+  *        parameters in the CAN_InitStruct.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *             the configuration information for the specified CAN.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
@@ -200,18 +202,18 @@
   hcan->State = HAL_CAN_STATE_BUSY;
   
   /* Exit from sleep mode */
-  hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+  CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
 
   /* Request initialisation */
-  hcan->Instance->MCR |= CAN_MCR_INRQ ;
+  SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
 
   /* Get tick */
   tickstart = HAL_GetTick();   
   
   /* Wait the acknowledge */
-  while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+  while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
   {
-    if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+    if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
     {
       hcan->State= HAL_CAN_STATE_TIMEOUT;
       /* Process unlocked */
@@ -221,95 +223,97 @@
   }
 
   /* Check acknowledge */
-  if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+  if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
   {
     /* Set the time triggered communication mode */
     if (hcan->Init.TTCM == ENABLE)
     {
-      hcan->Instance->MCR |= CAN_MCR_TTCM;
+      SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
     }
     else
     {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+      CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
     }
 
     /* Set the automatic bus-off management */
     if (hcan->Init.ABOM == ENABLE)
     {
-      hcan->Instance->MCR |= CAN_MCR_ABOM;
+      SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
     }
     else
     {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+      CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
     }
 
     /* Set the automatic wake-up mode */
     if (hcan->Init.AWUM == ENABLE)
     {
-      hcan->Instance->MCR |= CAN_MCR_AWUM;
+      SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
     }
     else
     {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+      CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
     }
 
     /* Set the no automatic retransmission */
     if (hcan->Init.NART == ENABLE)
     {
-      hcan->Instance->MCR |= CAN_MCR_NART;
+      SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
     }
     else
     {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
+      CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
     }
 
     /* Set the receive FIFO locked mode */
     if (hcan->Init.RFLM == ENABLE)
     {
-      hcan->Instance->MCR |= CAN_MCR_RFLM;
+      SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
     }
     else
     {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+      CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
     }
 
     /* Set the transmit FIFO priority */
     if (hcan->Init.TXFP == ENABLE)
     {
-      hcan->Instance->MCR |= CAN_MCR_TXFP;
+      SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
     }
     else
     {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+      CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
     }
 
     /* Set the bit timing register */
-    hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
-                ((uint32_t)hcan->Init.SJW) | \
-                ((uint32_t)hcan->Init.BS1) | \
-                ((uint32_t)hcan->Init.BS2) | \
-               ((uint32_t)hcan->Init.Prescaler - 1U);
+    WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |
+                                              hcan->Init.SJW            |
+                                              hcan->Init.BS1            |
+                                              hcan->Init.BS2            |
+                                              (hcan->Init.Prescaler - 1U) ));
 
     /* Request leave initialisation */
-    hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
 
     /* Get tick */
     tickstart = HAL_GetTick();   
    
     /* Wait the acknowledge */
-    while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+    while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
     {
-      if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+      if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
       {
-       hcan->State= HAL_CAN_STATE_TIMEOUT;
+         hcan->State= HAL_CAN_STATE_TIMEOUT;
+
        /* Process unlocked */
        __HAL_UNLOCK(hcan);
-        return HAL_TIMEOUT;
+
+       return HAL_TIMEOUT;
       }
     }
 
     /* Check acknowledged */
-    if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+    if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
     {
       status = CAN_INITSTATUS_SUCCESS;
     }
@@ -339,15 +343,15 @@
 /**
   * @brief  Configures the CAN reception filter according to the specified
   *         parameters in the CAN_FilterInitStruct.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
-  * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
+  * @param  sFilterConfig pointer to a CAN_FilterConfTypeDef structure that
   *         contains the filter configuration information.
   * @retval None
   */
 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
 {
-  uint32_t filternbrbitpos = 0;
+  uint32_t filternbrbitpos = 0U;
   
   /* Check the parameters */
   assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
@@ -360,81 +364,80 @@
   filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
 
   /* Initialisation mode for the filter */
-  hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT;
-
   /* Select the start slave bank */
-  hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
-  hcan->Instance->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U);
-  
-  /* Filter Deactivation */
-  hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos;
+  MODIFY_REG(hcan->Instance->FMR                         ,
+             CAN_FMR_CAN2SB                              ,
+             CAN_FMR_FINIT                              |
+             (uint32_t)(sFilterConfig->BankNumber << 8U)   );  /* Filter Deactivation */
+  CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
 
   /* Filter Scale */
   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
   {
     /* 16-bit scale for the filter */
-    hcan->Instance->FS1R &= ~(uint32_t)filternbrbitpos;
+    CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
 
     /* First 16-bit identifier and First 16-bit mask */
     /* Or First 16-bit identifier and Second 16-bit identifier */
     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+       ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
 
     /* Second 16-bit identifier and Second 16-bit mask */
     /* Or Third 16-bit identifier and Fourth 16-bit identifier */
     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+       ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
   }
 
   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
   {
     /* 32-bit scale for the filter */
-    hcan->Instance->FS1R |= filternbrbitpos;
+    SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
+
     /* 32-bit identifier or First 32-bit identifier */
     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+       ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
     /* 32-bit mask or Second 32-bit identifier */
     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+       ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
   }
 
   /* Filter Mode */
   if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
   {
     /*Id/Mask mode for the filter*/
-    hcan->Instance->FM1R &= ~(uint32_t)filternbrbitpos;
+    CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
   }
   else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
   {
     /*Identifier list mode for the filter*/
-    hcan->Instance->FM1R |= (uint32_t)filternbrbitpos;
+    SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
   }
 
   /* Filter FIFO assignment */
   if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
   {
     /* FIFO 0 assignation for the filter */
-    hcan->Instance->FFA1R &= ~(uint32_t)filternbrbitpos;
+    CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
   }
-
-  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
+  else
   {
     /* FIFO 1 assignation for the filter */
-    hcan->Instance->FFA1R |= (uint32_t)filternbrbitpos;
+    SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
   }
   
   /* Filter activation */
   if (sFilterConfig->FilterActivation == ENABLE)
   {
-    hcan->Instance->FA1R |= filternbrbitpos;
+    SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
   }
 
   /* Leave the initialisation mode for the filter */
-  hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_FINIT);
+  CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
   
   /* Return function status */
   return HAL_OK;
@@ -442,7 +445,7 @@
 
 /**
   * @brief  Deinitializes the CANx peripheral registers to their default reset values. 
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.  
   * @retval HAL status
   */
@@ -475,7 +478,7 @@
 
 /**
   * @brief  Initializes the CAN MSP.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.  
   * @retval None
   */
@@ -491,7 +494,7 @@
 
 /**
   * @brief  DeInitializes the CAN MSP.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.  
   * @retval None
   */
@@ -528,9 +531,9 @@
 
 /**
   * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.  
-  * @param  Timeout: Timeout duration.
+  * @param  Timeout Timeout duration.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
@@ -542,37 +545,43 @@
   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-  
+
   if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
      ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
      ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
-  {  
+  {
     /* Process locked */
     __HAL_LOCK(hcan);
-    
-    if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
+
+    /* Change CAN state */
+    switch(hcan->State)
     {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+      case(HAL_CAN_STATE_BUSY_RX0):
+          hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+          break;
+      case(HAL_CAN_STATE_BUSY_RX1):
+          hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+          break;
+      case(HAL_CAN_STATE_BUSY_RX0_RX1):
+          hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+          break;
+      default: /* HAL_CAN_STATE_READY */
+          hcan->State = HAL_CAN_STATE_BUSY_TX;
+          break;
+    }
+
+    /* Select one empty transmit mailbox */
+    if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+    {
+      transmitmailbox = CAN_TXMAILBOX_0;
+    }
+    else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+    {
+      transmitmailbox = CAN_TXMAILBOX_1;
     }
     else
     {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX;
-    }
-    
-    /* Select one empty transmit mailbox */
-    if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
-    {
-      transmitmailbox = 0U;
-    }
-    else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
-    {
-      transmitmailbox = 1U;
-    }
-      else
-    {
-      transmitmailbox = 2U;
+      transmitmailbox = CAN_TXMAILBOX_2;
     }
 
     /* Set up the Id */
@@ -580,15 +589,15 @@
     if (hcan->pTxMsg->IDE == CAN_ID_STD)
     {
       assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
-                                                  hcan->pTxMsg->RTR);
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
+                                                           hcan->pTxMsg->RTR);
     }
     else
     {
       assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
-                                                  hcan->pTxMsg->IDE | \
-                                                  hcan->pTxMsg->RTR);
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
+                                                           hcan->pTxMsg->IDE | \
+                                                           hcan->pTxMsg->RTR);
     }
     
     /* Set up the DLC */
@@ -597,16 +606,17 @@
     hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
 
     /* Set up the data field */
-    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24U) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16U) |
-                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8U) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[0]));
-    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24U) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16U) |
-                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8U) |
-                                             ((uint32_t)hcan->pTxMsg->Data[4]));
+    WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
+    WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
+
     /* Request transmission */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+    SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
   
     /* Get tick */
     tickstart = HAL_GetTick();   
@@ -617,26 +627,37 @@
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
       {
-        if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+        if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
         {
           hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+          /* Cancel transmission */
+          __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+
           /* Process unlocked */
           __HAL_UNLOCK(hcan);
           return HAL_TIMEOUT;
         }
       }
     }
-    if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+
+    /* Change CAN state */
+    switch(hcan->State)
     {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_RX;
+      case(HAL_CAN_STATE_BUSY_TX_RX0):
+          hcan->State = HAL_CAN_STATE_BUSY_RX0;
+          break;
+      case(HAL_CAN_STATE_BUSY_TX_RX1):
+          hcan->State = HAL_CAN_STATE_BUSY_RX1;
+          break;
+      case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+          hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+          break;
+      default: /* HAL_CAN_STATE_BUSY_TX */
+          hcan->State = HAL_CAN_STATE_READY;
+          break;
     }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_READY;
-    }
-    
+
     /* Process unlocked */
     __HAL_UNLOCK(hcan);
     
@@ -647,7 +668,7 @@
   {
     /* Change CAN state */
     hcan->State = HAL_CAN_STATE_ERROR; 
-    
+
     /* Return function status */
     return HAL_ERROR;
   }
@@ -655,7 +676,7 @@
 
 /**
   * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.  
   * @retval HAL status
   */
@@ -667,7 +688,7 @@
   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-  
+
   if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
      ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
      ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
@@ -676,92 +697,94 @@
     __HAL_LOCK(hcan);
     
     /* Select one empty transmit mailbox */
-    if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+    if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
     {
-      transmitmailbox = 0U;
+      transmitmailbox = CAN_TXMAILBOX_0;
     }
-    else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+    else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
     {
-      transmitmailbox = 1U;
+      transmitmailbox = CAN_TXMAILBOX_1;
     }
     else
     {
-      transmitmailbox = 2U;
+      transmitmailbox = CAN_TXMAILBOX_2;
     }
 
     /* Set up the Id */
     hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
     if(hcan->pTxMsg->IDE == CAN_ID_STD)
     {
-      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
-                                                hcan->pTxMsg->RTR);
+      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
+                                                           hcan->pTxMsg->RTR);
     }
     else
     {
       assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
-                                                hcan->pTxMsg->IDE | \
-                                                hcan->pTxMsg->RTR);
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
+                                                           hcan->pTxMsg->IDE |                         \
+                                                           hcan->pTxMsg->RTR);
     }
-  
+
     /* Set up the DLC */
     hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
     hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
     hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
 
     /* Set up the data field */
-    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24U) | 
-                                           ((uint32_t)hcan->pTxMsg->Data[2] << 16U) |
-                                           ((uint32_t)hcan->pTxMsg->Data[1] << 8U) | 
-                                           ((uint32_t)hcan->pTxMsg->Data[0]));
-    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24U) | 
-                                           ((uint32_t)hcan->pTxMsg->Data[6] << 16U) |
-                                           ((uint32_t)hcan->pTxMsg->Data[5] << 8U) |
-                                           ((uint32_t)hcan->pTxMsg->Data[4]));
-  
-    if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
+    WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
+    WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
+                                                                ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
+
+    /* Change CAN state */
+    switch(hcan->State)
     {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+      case(HAL_CAN_STATE_BUSY_RX0):
+          hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+          break;
+      case(HAL_CAN_STATE_BUSY_RX1):
+          hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+          break;
+      case(HAL_CAN_STATE_BUSY_RX0_RX1):
+          hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+          break;
+      default: /* HAL_CAN_STATE_READY */
+          hcan->State = HAL_CAN_STATE_BUSY_TX;
+          break;
     }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX;
-    }
-    
+
     /* Set CAN error code to none */
     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(hcan);
-    
-    /* Enable Error warning Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
-    
-    /* Enable Error passive Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
-    
-    /* Enable Bus-off Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
-    
-    /* Enable Last error code Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
-    
-    /* Enable Error Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
-    
-    /* Enable Transmit mailbox empty Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
-    
+
     /* Request transmission */
     hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+    /* Enable interrupts: */
+    /*  - Enable Error warning Interrupt */
+    /*  - Enable Error passive Interrupt */
+    /*  - Enable Bus-off Interrupt */
+    /*  - Enable Last error code Interrupt */
+    /*  - Enable Error Interrupt */
+    /*  - Enable Transmit mailbox empty Interrupt */
+    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+                              CAN_IT_EPV |
+                              CAN_IT_BOF |
+                              CAN_IT_LEC |
+                              CAN_IT_ERR |
+                              CAN_IT_TME  );
   }
   else
   {
     /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR; 
+    hcan->State = HAL_CAN_STATE_ERROR;
 
     /* Return function status */
     return HAL_ERROR;
@@ -772,34 +795,85 @@
 
 /**
   * @brief  Receives a correct CAN frame.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.  
-  * @param  FIFONumber:    FIFO number.
-  * @param  Timeout:       Timeout duration.
+  * @param  FIFONumber    FIFO number.
+  * @param  Timeout       Timeout duration.
   * @retval HAL status
-  * @retval None
   */
 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
-   
+  uint32_t tickstart = 0U;
+  CanRxMsgTypeDef* pRxMsg = NULL;
+
   /* Check the parameters */
   assert_param(IS_CAN_FIFO(FIFONumber));
-  
+
   /* Process locked */
   __HAL_LOCK(hcan);
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
+
+  /* Check if CAN state is not busy for RX FIFO0 */
+  if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) ||         \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) ||      \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) ||     \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
   {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+
+    return HAL_BUSY;
+  }
+
+  /* Check if CAN state is not busy for RX FIFO1 */
+  if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) ||         \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) ||      \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) ||     \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+
+    return HAL_BUSY;
   }
-  else
+
+  /* Change CAN state */
+  if (FIFONumber == CAN_FIFO0)
   {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_RX;
+    switch(hcan->State)
+    {
+      case(HAL_CAN_STATE_BUSY_TX):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+        break;
+      case(HAL_CAN_STATE_BUSY_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+        break;
+      case(HAL_CAN_STATE_BUSY_TX_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+        break;
+      default: /* HAL_CAN_STATE_READY */
+        hcan->State = HAL_CAN_STATE_BUSY_RX0;
+        break;
+    }
   }
-    
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    switch(hcan->State)
+    {
+      case(HAL_CAN_STATE_BUSY_TX):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+        break;
+      case(HAL_CAN_STATE_BUSY_RX0):
+        hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+        break;
+      case(HAL_CAN_STATE_BUSY_TX_RX0):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+        break;
+      default: /* HAL_CAN_STATE_READY */
+        hcan->State = HAL_CAN_STATE_BUSY_RX1;
+        break;
+    }
+  }
+
   /* Get tick */
   tickstart = HAL_GetTick();   
   
@@ -809,41 +883,54 @@
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
       {
         hcan->State = HAL_CAN_STATE_TIMEOUT;
+
         /* Process unlocked */
         __HAL_UNLOCK(hcan);
+
         return HAL_TIMEOUT;
       }
     }
   }
-  
+
+  /* Set RxMsg pointer */
+  if(FIFONumber == CAN_FIFO0)
+  {
+    pRxMsg = hcan->pRxMsg;
+  }
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    pRxMsg = hcan->pRx1Msg;
+  }
+
   /* Get the Id */
-  hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  if (hcan->pRxMsg->IDE == CAN_ID_STD)
+  pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  if (pRxMsg->IDE == CAN_ID_STD)
   {
-    hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+    pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
   }
   else
   {
-    hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+    pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
   }
-  
-  hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
   /* Get the DLC */
-  hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+  pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
   /* Get the FMI */
-  hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+  pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
+  /* Get the FIFONumber */
+  pRxMsg->FIFONumber = FIFONumber;
   /* Get the data field */
-  hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
-  hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
-  hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
-  hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
-  hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
-  hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
-  hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
-  hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+  pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
+  pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
+  pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
+  pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
+  pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
+  pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
+  pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
+  pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
   
   /* Release the FIFO */
   if(FIFONumber == CAN_FIFO0)
@@ -856,16 +943,43 @@
     /* Release FIFO1 */
     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
   }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+
+  /* Change CAN state */
+  if (FIFONumber == CAN_FIFO0)
   {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
+    switch(hcan->State)
+    {
+      case(HAL_CAN_STATE_BUSY_TX_RX0):
+        hcan->State = HAL_CAN_STATE_BUSY_TX;
+        break;
+      case(HAL_CAN_STATE_BUSY_RX0_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_RX1;
+        break;
+      case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+        break;
+      default: /* HAL_CAN_STATE_BUSY_RX0 */
+        hcan->State = HAL_CAN_STATE_READY;
+        break;
+    }
   }
-  else
+  else /* FIFONumber == CAN_FIFO1 */
   {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
+    switch(hcan->State)
+    {
+      case(HAL_CAN_STATE_BUSY_TX_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_TX;
+        break;
+      case(HAL_CAN_STATE_BUSY_RX0_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_RX0;
+        break;
+      case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+        break;
+      default: /* HAL_CAN_STATE_BUSY_RX1 */
+        hcan->State = HAL_CAN_STATE_READY;
+        break;
+    }
   }
   
   /* Process unlocked */
@@ -877,69 +991,108 @@
 
 /**
   * @brief  Receives a correct CAN frame.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.  
-  * @param  FIFONumber:    FIFO number.
+  * @param  FIFONumber    FIFO number.
   * @retval HAL status
-  * @retval None
   */
 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
 {
   /* Check the parameters */
   assert_param(IS_CAN_FIFO(FIFONumber));
-  
-  if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
+
+  /* Process locked */
+  __HAL_LOCK(hcan);
+
+  /* Check if CAN state is not busy for RX FIFO0 */
+  if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) ||        \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) ||      \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) ||     \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
   {
-    /* Process locked */
-    __HAL_LOCK(hcan);
-  
-    if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_RX;
-    }
-    
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-    
-    /* Enable Error warning Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
-      
-    /* Enable Error passive Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
-      
-    /* Enable Bus-off Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
-      
-    /* Enable Last error code Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
-      
-    /* Enable Error Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+
+    return HAL_BUSY;
+  }
 
+  /* Check if CAN state is not busy for RX FIFO1 */
+  if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) ||        \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) ||      \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) ||     \
+                                    (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+  {
     /* Process unlocked */
     __HAL_UNLOCK(hcan);
 
-    if(FIFONumber == CAN_FIFO0)
+    return HAL_BUSY;
+  }
+
+  /* Change CAN state */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    switch(hcan->State)
     {
-      /* Enable FIFO 0 message pending Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
+      case(HAL_CAN_STATE_BUSY_TX):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+        break;
+      case(HAL_CAN_STATE_BUSY_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+        break;
+      case(HAL_CAN_STATE_BUSY_TX_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+        break;
+      default: /* HAL_CAN_STATE_READY */
+        hcan->State = HAL_CAN_STATE_BUSY_RX0;
+        break;
     }
-    else
+  }
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    switch(hcan->State)
     {
-      /* Enable FIFO 1 message pending Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
+      case(HAL_CAN_STATE_BUSY_TX):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+        break;
+      case(HAL_CAN_STATE_BUSY_RX0):
+        hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+        break;
+      case(HAL_CAN_STATE_BUSY_TX_RX0):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+        break;
+      default: /* HAL_CAN_STATE_READY */
+        hcan->State = HAL_CAN_STATE_BUSY_RX1;
+        break;
     }
-    
+  }
+
+  /* Set CAN error code to none */
+  hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+  /* Enable interrupts: */
+  /*  - Enable Error warning Interrupt */
+  /*  - Enable Error passive Interrupt */
+  /*  - Enable Bus-off Interrupt */
+  /*  - Enable Last error code Interrupt */
+  /*  - Enable Error Interrupt */
+  __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+                            CAN_IT_EPV |
+                            CAN_IT_BOF |
+                            CAN_IT_LEC |
+                            CAN_IT_ERR);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hcan);
+
+  if(FIFONumber == CAN_FIFO0)
+  {
+    /* Enable FIFO 0 overrun and message pending Interrupt */
+    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
   }
   else
   {
-    return HAL_BUSY;
+    /* Enable FIFO 1 overrun and message pending Interrupt */
+    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
   }
   
   /* Return function status */
@@ -948,7 +1101,7 @@
 
 /**
   * @brief  Enters the Sleep (low power) mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval HAL status.
   */
@@ -963,10 +1116,13 @@
   hcan->State = HAL_CAN_STATE_BUSY; 
     
   /* Request Sleep mode */
-   hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+  MODIFY_REG(hcan->Instance->MCR,
+             CAN_MCR_INRQ       ,
+             CAN_MCR_SLEEP       );
    
   /* Sleep mode status */
-  if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+  if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
+      HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)   )
   {
     /* Process unlocked */
     __HAL_UNLOCK(hcan);
@@ -979,7 +1135,8 @@
   tickstart = HAL_GetTick();   
   
   /* Wait the acknowledge */
-  while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+  while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
+         HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)   )
   {
     if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
     {
@@ -1003,7 +1160,7 @@
 /**
   * @brief  Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
   *         is in the normal mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval HAL status.
   */
@@ -1018,23 +1175,26 @@
   hcan->State = HAL_CAN_STATE_BUSY;  
  
   /* Wake up request */
-  hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+  CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
     
   /* Get tick */
   tickstart = HAL_GetTick();   
   
   /* Sleep mode status */
-  while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+  while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
   {
     if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
     {
       hcan->State= HAL_CAN_STATE_TIMEOUT;
+
       /* Process unlocked */
       __HAL_UNLOCK(hcan);
+
       return HAL_TIMEOUT;
     }
   }
-  if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+
+  if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
   {
     /* Process unlocked */
     __HAL_UNLOCK(hcan);
@@ -1055,27 +1215,67 @@
 
 /**
   * @brief  Handles CAN interrupt request  
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval None
   */
 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
 {
+  uint32_t errorcode = HAL_CAN_ERROR_NONE;
+
+  /* Check Overrun flag for FIFO0 */
+  if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0))    &&
+     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0)))
+  {
+    /* Set CAN error code to FOV0 error */
+    errorcode |= HAL_CAN_ERROR_FOV0;
+
+    /* Clear FIFO0 Overrun Flag */
+    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+  }
+
+  /* Check Overrun flag for FIFO1 */
+  if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1))    &&
+     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1)))
+  {
+    /* Set CAN error code to FOV1 error */
+    errorcode |= HAL_CAN_ERROR_FOV1;
+
+    /* Clear FIFO1 Overrun Flag */
+    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+  }
+
   /* Check End of transmission flag */
   if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
   {
+    /* Check Transmit request completion status */
     if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
        (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
        (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
     {
-      /* Call transmit function */
-      CAN_Transmit_IT(hcan);
+      /* Check Transmit success */
+      if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) ||
+         (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) ||
+         (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2)))
+      {
+        /* Call transmit function */
+        CAN_Transmit_IT(hcan);
+      }
+      else /* Transmit failure */
+      {
+        /* Set CAN error code to TXFAIL error */
+        errorcode |= HAL_CAN_ERROR_TXFAIL;
+      }
+
+      /* Clear transmission status flags (RQCPx and TXOKx) */
+      SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0  | CAN_TSR_RQCP1  | CAN_TSR_RQCP2 | \
+                                   CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
     }
   }
   
   /* Check End of reception flag for FIFO0 */
   if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
-     (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
+     (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U))
   {
     /* Call receive function */
     CAN_Receive_IT(hcan, CAN_FIFO0);
@@ -1083,12 +1283,15 @@
   
   /* Check End of reception flag for FIFO1 */
   if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
-     (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
+     (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U))
   {
     /* Call receive function */
     CAN_Receive_IT(hcan, CAN_FIFO1);
   }
   
+  /* Set error code in handle */
+  hcan->ErrorCode |= errorcode;
+
   /* Check Error Warning Flag */
   if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG))    &&
      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
@@ -1106,7 +1309,7 @@
   {
     /* Set CAN error code to EPV error */
     hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
-    /* No need for clear of Error Passive Flag as read-only */
+    /* No need for clear of Error Passive Flag as read-only */ 
   }
   
   /* Check Bus-Off Flag */
@@ -1155,16 +1358,40 @@
     }
 
     /* Clear Last error code Flag */ 
-    hcan->Instance->ESR &= ~(CAN_ESR_LEC);
+    CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
   }
 
   /* Call the Error call Back in case of Errors */
   if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
   {
     /* Clear ERRI Flag */ 
-    hcan->Instance->MSR |= CAN_MSR_ERRI; 
+    SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
+
     /* Set the CAN state ready to be able to start again the process */
     hcan->State = HAL_CAN_STATE_READY;
+
+    /* Disable interrupts: */
+    /*  - Disable Error warning Interrupt */
+    /*  - Disable Error passive Interrupt */
+    /*  - Disable Bus-off Interrupt */
+    /*  - Disable Last error code Interrupt */
+    /*  - Disable Error Interrupt */
+    /*  - Disable FIFO 0 message pending Interrupt */
+    /*  - Disable FIFO 0 Overrun Interrupt */
+    /*  - Disable FIFO 1 message pending Interrupt */
+    /*  - Disable FIFO 1 Overrun Interrupt */
+    /*  - Disable Transmit mailbox empty Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+                               CAN_IT_EPV |
+                               CAN_IT_BOF |
+                               CAN_IT_LEC |
+                               CAN_IT_ERR |
+                               CAN_IT_FMP0|
+                               CAN_IT_FOV0|
+                               CAN_IT_FMP1|
+                               CAN_IT_FOV1|
+                               CAN_IT_TME  );
+
     /* Call Error callback function */
     HAL_CAN_ErrorCallback(hcan);
   }  
@@ -1172,7 +1399,7 @@
 
 /**
   * @brief  Transmission  complete callback in non blocking mode 
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval None
   */
@@ -1188,7 +1415,7 @@
 
 /**
   * @brief  Transmission  complete callback in non blocking mode 
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval None
   */
@@ -1204,7 +1431,7 @@
 
 /**
   * @brief  Error CAN callback.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval None
   */
@@ -1240,7 +1467,7 @@
 
 /**
   * @brief  return the CAN state
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval HAL state
   */
@@ -1252,7 +1479,7 @@
 
 /**
   * @brief  Return the CAN error code
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval CAN Error Code
   */
@@ -1274,9 +1501,10 @@
  *
  * @{
  */
+
 /**
   * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.  
   * @retval HAL status
   */
@@ -1287,33 +1515,36 @@
   
   if(hcan->State == HAL_CAN_STATE_BUSY_TX)
   {   
-    /* Disable Error warning Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
-    
-    /* Disable Error passive Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
-    
-    /* Disable Bus-off Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
-    
-    /* Disable Last error code Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
-    
-    /* Disable Error Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+    /* Disable interrupts: */
+    /*  - Disable Error warning Interrupt */
+    /*  - Disable Error passive Interrupt */
+    /*  - Disable Bus-off Interrupt */
+    /*  - Disable Last error code Interrupt */
+    /*  - Disable Error Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+                               CAN_IT_EPV |
+                               CAN_IT_BOF |
+                               CAN_IT_LEC |
+                               CAN_IT_ERR );
   }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+
+  /* Change CAN state */
+  switch(hcan->State)
   {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_RX;
+    case(HAL_CAN_STATE_BUSY_TX_RX0):
+      hcan->State = HAL_CAN_STATE_BUSY_RX0;
+      break;
+    case(HAL_CAN_STATE_BUSY_TX_RX1):
+      hcan->State = HAL_CAN_STATE_BUSY_RX1;
+      break;
+    case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+      hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+      break;
+    default: /* HAL_CAN_STATE_BUSY_TX */
+      hcan->State = HAL_CAN_STATE_READY;
+      break;
   }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
-  
+
   /* Transmission complete callback */ 
   HAL_CAN_TxCpltCallback(hcan);
   
@@ -1322,84 +1553,122 @@
 
 /**
   * @brief  Receives a correct CAN frame.
-  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan       Pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.  
-  * @param  FIFONumber: Specify the FIFO number    
+  * @param  FIFONumber Specify the FIFO number    
   * @retval HAL status
   * @retval None
   */
 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
 {
+  CanRxMsgTypeDef* pRxMsg = NULL;
+
+  /* Set RxMsg pointer */
+  if(FIFONumber == CAN_FIFO0)
+  {
+    pRxMsg = hcan->pRxMsg;
+  }
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    pRxMsg = hcan->pRx1Msg;
+  }
+
   /* Get the Id */
-  hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  if (hcan->pRxMsg->IDE == CAN_ID_STD)
+  pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  if (pRxMsg->IDE == CAN_ID_STD)
   {
-    hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+    pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
   }
   else
   {
-    hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+    pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
   }
-  
-  hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
   /* Get the DLC */
-  hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+  pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
   /* Get the FMI */
-  hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+  pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
+  /* Get the FIFONumber */
+  pRxMsg->FIFONumber = FIFONumber;
   /* Get the data field */
-  hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
-  hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
-  hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
-  hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
-  hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
-  hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
-  hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
-  hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+  pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
+  pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
+  pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
+  pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
+  pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
+  pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
+  pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
+  pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
+
   /* Release the FIFO */
   /* Release FIFO0 */
   if (FIFONumber == CAN_FIFO0)
   {
     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
     
-    /* Disable FIFO 0 message pending Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
+    /* Disable FIFO 0 overrun and message pending Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
   }
   /* Release FIFO1 */
   else /* FIFONumber == CAN_FIFO1 */
   {
     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
     
-    /* Disable FIFO 1 message pending Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
+    /* Disable FIFO 1 overrun and message pending Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
   }
   
-  if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+  if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1))
   {   
-    /* Disable Error warning Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
-    
-    /* Disable Error passive Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
-    
-    /* Disable Bus-off Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
-    
-    /* Disable Last error code Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
-    
-    /* Disable Error Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+    /* Disable interrupts: */
+    /*  - Disable Error warning Interrupt */
+    /*  - Disable Error passive Interrupt */
+    /*  - Disable Bus-off Interrupt */
+    /*  - Disable Last error code Interrupt */
+    /*  - Disable Error Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+                               CAN_IT_EPV |
+                               CAN_IT_BOF |
+                               CAN_IT_LEC |
+                               CAN_IT_ERR );
   }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+
+  /* Change CAN state */
+  if (FIFONumber == CAN_FIFO0)
   {
-    /* Disable CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
+    switch(hcan->State)
+    {
+      case(HAL_CAN_STATE_BUSY_TX_RX0):
+        hcan->State = HAL_CAN_STATE_BUSY_TX;
+        break;
+      case(HAL_CAN_STATE_BUSY_RX0_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_RX1;
+        break;
+      case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+        break;
+      default: /* HAL_CAN_STATE_BUSY_RX0 */
+        hcan->State = HAL_CAN_STATE_READY;
+        break;
+    }
   }
-  else
+  else /* FIFONumber == CAN_FIFO1 */
   {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
+    switch(hcan->State)
+    {
+      case(HAL_CAN_STATE_BUSY_TX_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_TX;
+        break;
+      case(HAL_CAN_STATE_BUSY_RX0_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_RX0;
+        break;
+      case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+        break;
+      default: /* HAL_CAN_STATE_BUSY_RX1 */
+        hcan->State = HAL_CAN_STATE_READY;
+        break;
+    }
   }
 
   /* Receive complete callback */ 
@@ -1408,6 +1677,7 @@
   /* Return function status */
   return HAL_OK;
 }
+
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_can.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of CAN HAL module.
   ******************************************************************************
   * @attention
@@ -59,20 +57,24 @@
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup CAN_Exported_Types CAN Exported Types
   * @{
-  */
+  */  
 /** 
   * @brief  HAL State structures definition  
   */ 
 typedef enum
 {
   HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
-  HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */  
-  HAL_CAN_STATE_BUSY              = 0x02U,  /*!< CAN process is ongoing              */     
-  HAL_CAN_STATE_BUSY_TX           = 0x12U,  /*!< CAN process is ongoing              */   
-  HAL_CAN_STATE_BUSY_RX           = 0x22U,  /*!< CAN process is ongoing              */ 
-  HAL_CAN_STATE_BUSY_TX_RX        = 0x32U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
+  HAL_CAN_STATE_BUSY              = 0x02U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX           = 0x12U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_RX0          = 0x22U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_RX1          = 0x32U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX_RX0       = 0x42U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX_RX1       = 0x52U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_RX0_RX1      = 0x62U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX_RX0_RX1   = 0x72U,  /*!< CAN process is ongoing              */
   HAL_CAN_STATE_TIMEOUT           = 0x03U,  /*!< CAN in Timeout state                */
-  HAL_CAN_STATE_ERROR             = 0x04U   /*!< CAN error state                     */  
+  HAL_CAN_STATE_ERROR             = 0x04U   /*!< CAN error state                     */
 
 }HAL_CAN_StateTypeDef;
 
@@ -140,7 +142,7 @@
                                        second one for a 16-bit configuration).
                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 
 
-  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
                                        This parameter can be a value of @ref CAN_filter_FIFO */
   
   uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized. 
@@ -180,7 +182,7 @@
   uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
                           This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
 
-  uint8_t Data[8];  /*!< Contains the data to be transmitted. 
+  uint8_t Data[8];   /*!< Contains the data to be transmitted. 
                           This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
    
 }CanTxMsgTypeDef;
@@ -205,7 +207,7 @@
   uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
                              This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
 
-  uint8_t Data[8];     /*!< Contains the data to be received. 
+  uint8_t Data[8];      /*!< Contains the data to be received. 
                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
 
   uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
@@ -227,8 +229,10 @@
   
   CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
 
-  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
-  
+  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure for RX FIFO0 msg */
+
+  CanRxMsgTypeDef*            pRx1Msg;    /*!< Pointer to reception structure for RX FIFO1 msg */
+
   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
   
   __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
@@ -250,16 +254,19 @@
 /** @defgroup CAN_Error_Code CAN Error Code
   * @{
   */
-#define HAL_CAN_ERROR_NONE              (0x00000000U)  /*!< No error             */
-#define HAL_CAN_ERROR_EWG               (0x00000001U)  /*!< EWG error            */   
-#define HAL_CAN_ERROR_EPV               (0x00000002U)  /*!< EPV error            */
-#define HAL_CAN_ERROR_BOF               (0x00000004U)  /*!< BOF error            */
-#define HAL_CAN_ERROR_STF               (0x00000008U)  /*!< Stuff error          */
-#define HAL_CAN_ERROR_FOR               (0x00000010U)  /*!< Form error           */
-#define HAL_CAN_ERROR_ACK               (0x00000020U)  /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR                (0x00000040U)  /*!< Bit recessive        */
-#define HAL_CAN_ERROR_BD                (0x00000080U)  /*!< LEC dominant         */
-#define HAL_CAN_ERROR_CRC               (0x00000100U)  /*!< LEC transfer error   */
+#define HAL_CAN_ERROR_NONE          (0x00000000U)  /*!< No error             */
+#define HAL_CAN_ERROR_EWG           (0x00000001U)  /*!< EWG error            */   
+#define HAL_CAN_ERROR_EPV           (0x00000002U)  /*!< EPV error            */
+#define HAL_CAN_ERROR_BOF           (0x00000004U)  /*!< BOF error            */
+#define HAL_CAN_ERROR_STF           (0x00000008U)  /*!< Stuff error          */
+#define HAL_CAN_ERROR_FOR           (0x00000010U)  /*!< Form error           */
+#define HAL_CAN_ERROR_ACK           (0x00000020U)  /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR            (0x00000040U)  /*!< Bit recessive        */
+#define HAL_CAN_ERROR_BD            (0x00000080U)  /*!< LEC dominant         */
+#define HAL_CAN_ERROR_CRC           (0x00000100U)  /*!< LEC transfer error   */
+#define HAL_CAN_ERROR_FOV0          (0x00000200U)  /*!< FIFO0 overrun error  */
+#define HAL_CAN_ERROR_FOV1          (0x00000400U)  /*!< FIFO1 overrun error  */
+#define HAL_CAN_ERROR_TXFAIL        (0x00000800U)  /*!< Transmit failure     */
 /**
   * @}
   */
@@ -273,10 +280,10 @@
   * @}
   */
 
-/** @defgroup CAN_operating_mode CAN operating mode
+/** @defgroup CAN_operating_mode CAN Operating Mode
   * @{
   */
-#define CAN_MODE_NORMAL             (0x00000000U)                     /*!< Normal mode   */
+#define CAN_MODE_NORMAL             (0x00000000U)                              /*!< Normal mode   */
 #define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
 #define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
 #define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
@@ -285,10 +292,10 @@
   */
 
 
-/** @defgroup CAN_synchronisation_jump_width CAN synchronisation jump width
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
   * @{
   */
-#define CAN_SJW_1TQ                 (0x00000000U)     /*!< 1 time quantum */
+#define CAN_SJW_1TQ                 (0x00000000U)              /*!< 1 time quantum */
 #define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
 #define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
 #define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
@@ -296,10 +303,10 @@
   * @}
   */
 
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN time quantum in bit segment 1
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
   * @{
   */
-#define CAN_BS1_1TQ                 (0x00000000U)                                       /*!< 1 time quantum  */
+#define CAN_BS1_1TQ                 (0x00000000U)                                                /*!< 1 time quantum  */
 #define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
 #define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
 #define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
@@ -315,15 +322,14 @@
 #define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
 #define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
 #define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-
 /**
   * @}
   */
 
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN time quantum in bit segment 2
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
   * @{
   */
-#define CAN_BS2_1TQ                 (0x00000000U)                       /*!< 1 time quantum */
+#define CAN_BS2_1TQ                 (0x00000000U)                                /*!< 1 time quantum */
 #define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
 #define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
 #define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
@@ -331,72 +337,65 @@
 #define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
 #define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
 #define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
-
 /**
   * @}
   */
 
-/** @defgroup CAN_filter_mode CAN filter mode
+/** @defgroup CAN_filter_mode CAN Filter Mode
   * @{
   */
 #define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00U)  /*!< Identifier mask mode */
 #define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01U)  /*!< Identifier list mode */
-
 /**
   * @}
   */
 
-/** @defgroup CAN_filter_scale CAN filter scale
+/** @defgroup CAN_filter_scale CAN Filter Scale
   * @{
   */
 #define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00U)  /*!< Two 16-bit filters */
 #define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01U)  /*!< One 32-bit filter  */
-
 /**
   * @}
   */
 
-/** @defgroup CAN_filter_FIFO CAN filter FIFO
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
   * @{
   */
 #define CAN_FILTER_FIFO0             ((uint8_t)0x00U)  /*!< Filter FIFO 0 assignment for filter x */
 #define CAN_FILTER_FIFO1             ((uint8_t)0x01U)  /*!< Filter FIFO 1 assignment for filter x */
-
 /**
   * @}
   */
 
-/** @defgroup CAN_identifier_type  CAN identifier type
+/** @defgroup CAN_identifier_type CAN Identifier Type
   * @{
   */
 #define CAN_ID_STD             (0x00000000U)  /*!< Standard Id */
 #define CAN_ID_EXT             (0x00000004U)  /*!< Extended Id */
-
 /**
   * @}
   */
 
-/** @defgroup CAN_remote_transmission_request CAN remote transmission request
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
   * @{
   */
 #define CAN_RTR_DATA                (0x00000000U)  /*!< Data frame */
 #define CAN_RTR_REMOTE              (0x00000002U)  /*!< Remote frame */
-
 /**
   * @}
   */
 
-/** @defgroup CAN_receive_FIFO_number_constants CAN receive FIFO number constants
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
   * @{
   */
 #define CAN_FIFO0                   ((uint8_t)0x00U)  /*!< CAN FIFO 0 used to receive */
 #define CAN_FIFO1                   ((uint8_t)0x01U)  /*!< CAN FIFO 1 used to receive */
-
 /**
   * @}
   */
 
-/** @defgroup CAN_flags CAN flags
+/** @defgroup CAN_flags CAN Flags
   * @{
   */
 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
@@ -423,22 +422,25 @@
 #define CAN_FLAG_FOV1              (0x00000404U)  /*!< FIFO 1 Overrun flag */
 
 /* Operating Mode Flags */
-#define CAN_FLAG_WKU               (0x00000103U)  /*!< Wake up flag           */
-#define CAN_FLAG_SLAK              (0x00000101U)  /*!< Sleep acknowledge flag */
-#define CAN_FLAG_SLAKI             (0x00000104U)  /*!< Sleep acknowledge flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
+#define CAN_FLAG_INAK              (0x00000100U)  /*!< Initialization acknowledge flag */
+#define CAN_FLAG_SLAK              (0x00000101U)  /*!< Sleep acknowledge flag          */
+#define CAN_FLAG_ERRI              (0x00000102U)  /*!< Error flag                      */
+#define CAN_FLAG_WKU               (0x00000103U)  /*!< Wake up flag                    */
+#define CAN_FLAG_SLAKI             (0x00000104U)  /*!< Sleep acknowledge flag          */
+/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible. 
          In this case the SLAK bit can be polled.*/
 
 /* Error Flags */
 #define CAN_FLAG_EWG               (0x00000300U)  /*!< Error warning flag   */
 #define CAN_FLAG_EPV               (0x00000301U)  /*!< Error passive flag   */
 #define CAN_FLAG_BOF               (0x00000302U)  /*!< Bus-Off flag         */
+
 /**
   * @}
   */
 
   
-/** @defgroup CAN_interrupts CAN interrupts
+/** @defgroup CAN_interrupts CAN Interrupts
   * @{
   */ 
 #define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
@@ -465,7 +467,7 @@
 /**
   * @}
   */
-  
+
 /** @defgroup CAN_Mailboxes CAN Mailboxes
 * @{
 */   
@@ -476,7 +478,7 @@
 /**
   * @}
   */
-  
+
 /**
   * @}
   */
@@ -485,42 +487,42 @@
 /** @defgroup CAN_Exported_Macros CAN Exported Macros
   * @{
   */
-  
+
 /** @brief  Reset CAN handle state
-  * @param  __HANDLE__: CAN handle.
+  * @param  __HANDLE__ CAN handle.
   * @retval None
   */
 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
 
 /**
   * @brief  Enable the specified CAN interrupts.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __INTERRUPT__: CAN Interrupt
+  * @param  __HANDLE__ CAN handle.
+  * @param  __INTERRUPT__ CAN Interrupt
   * @retval None
   */
 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the specified CAN interrupts.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __INTERRUPT__: CAN Interrupt
+  * @param  __HANDLE__ CAN handle.
+  * @param  __INTERRUPT__ CAN Interrupt
   * @retval None
   */
 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
 
 /**
   * @brief  Return the number of pending received messages.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @param  __HANDLE__ CAN handle.
+  * @param  __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
   * @retval The number of pending message.
   */
 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
 ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
 
 /** @brief  Check whether the specified CAN flag is set or not.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
@@ -552,9 +554,9 @@
  ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
 
 /** @brief  Clear the specified CAN pending flag.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
@@ -578,16 +580,16 @@
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
  (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
  (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
+ (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
 
 
 /** @brief  Check if the specified CAN interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
-  *          This parameter can be one of the following values:
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __INTERRUPT__ specifies the CAN interrupt source to check.
+  *         This parameter can be one of the following values:
   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
   *            @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
   *            @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
@@ -597,21 +599,19 @@
 
 /**
   * @brief  Check the transmission status of a CAN Frame.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+  * @param  __HANDLE__ CAN handle.
+  * @param  __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
   * @retval The new status of transmission  (TRUE or FALSE).
   */
 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
-
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
 
-
-/**
+ /**
   * @brief  Release the specified receive FIFO.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @param  __HANDLE__ CAN handle.
+  * @param  __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
   * @retval None
   */
 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
@@ -619,8 +619,8 @@
 
 /**
   * @brief  Cancel a transmit request.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
   * @retval None
   */
 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
@@ -630,8 +630,8 @@
 
 /**
   * @brief  Enable or disables the DBG Freeze for CAN.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __NEWSTATE__: new state of the CAN peripheral. 
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __NEWSTATE__ new state of the CAN peripheral. 
   *         This parameter can be: ENABLE (CAN reception/transmission is frozen
   *         during debug. Reception FIFOs can still be accessed/controlled normally) 
   *         or DISABLE (CAN is working during debug).
@@ -641,14 +641,14 @@
 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 
 
 /**
-  * @}
-  */
-   
+ * @}
+ */  
+ 
 /* Exported functions --------------------------------------------------------*/  
 /** @addtogroup CAN_Exported_Functions CAN Exported Functions
   * @{
   */
-
+  
 /** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 
  *  @brief    Initialization and Configuration functions 
  * @{
@@ -661,14 +661,13 @@
 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
 /**
-  * @}
-  */
-
+ * @}
+ */ 
+ 
 /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
- *  @brief    I/O operation functions
+ *  @brief    I/O operation functions 
  * @{
  */
-  
 /* IO operation functions *****************************************************/
 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
@@ -676,31 +675,28 @@
 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-
 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-
 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
 /**
-  * @}
-  */
-
+ * @}
+ */ 
+ 
 /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
  *  @brief   CAN Peripheral State functions 
  * @{
- */  
+ */
 /* Peripheral State and Error functions ***************************************/
 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-
 /**
-  * @}
-  */
-
+ * @}
+ */ 
+ 
 /**
-  * @}
-  */
+ * @}
+ */ 
 
 /* Private types -------------------------------------------------------------*/
 /** @defgroup CAN_Private_Types CAN Private Types
@@ -730,27 +726,37 @@
   * @}
   */
 
-/* Private macros ------------------------------------------------------------*/
+/* Private Macros -----------------------------------------------------------*/
 /** @defgroup CAN_Private_Macros CAN Private Macros
   * @{
   */
+
 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
                            ((MODE) == CAN_MODE_LOOPBACK)|| \
                            ((MODE) == CAN_MODE_SILENT) || \
                            ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+
 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
                          ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+
 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+
 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
+
 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
                                   ((MODE) == CAN_FILTERMODE_IDLIST))
+
 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
                                     ((SCALE) == CAN_FILTERSCALE_32BIT))
+
 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
                                   ((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
 
 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
 #define IS_CAN_STDID(STDID)   ((STDID) <= (0x7FFU))
@@ -759,17 +765,30 @@
 
 #define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
                                 ((IDTYPE) == CAN_ID_EXT))
+
 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
 
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
 /**
   * @}
   */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
-  * @{
-  */
+/* End of private macros -----------------------------------------------------*/
 
 /**
   * @}
@@ -778,10 +797,6 @@
 /**
   * @}
   */
-  
-/**
-  * @}
-  */  
 
 #endif /* STM32F072xB || STM32F042x6 || STM32F048xx  || STM32F078xx || STM32F091xC || STM32F098xx */
 
@@ -793,4 +808,3 @@
 
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_cec.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   CEC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the High Definition Multimedia Interface 
@@ -78,6 +76,13 @@
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f0xx_hal.h"
 
+#ifdef HAL_CEC_MODULE_ENABLED
+
+#if defined(STM32F042x6) || defined(STM32F048xx) ||\
+    defined(STM32F051x8) || defined(STM32F058xx) ||\
+    defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\
+    defined(STM32F091xC) || defined (STM32F098xx)
+
 /** @addtogroup STM32F0xx_HAL_Driver
   * @{
   */
@@ -86,12 +91,7 @@
   * @brief HAL CEC module driver
   * @{
   */
-#ifdef HAL_CEC_MODULE_ENABLED
 
-#if defined(STM32F042x6) || defined(STM32F048xx) ||\
-    defined(STM32F051x8) || defined(STM32F058xx) ||\
-    defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\
-    defined(STM32F091xC) || defined (STM32F098xx)
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /** @defgroup CEC_Private_Constants CEC Private Constants
@@ -144,7 +144,7 @@
 /**
   * @brief Initializes the CEC mode according to the specified
   *         parameters in the CEC_InitTypeDef and creates the associated handle .
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
@@ -214,7 +214,7 @@
 
 /**
   * @brief DeInitializes the CEC peripheral 
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
@@ -267,8 +267,8 @@
 
 /**
   * @brief Initializes the Own Address of the CEC device
-  * @param hcec: CEC handle
-  * @param  CEC_OwnAddress: The CEC own address.  
+  * @param hcec CEC handle
+  * @param  CEC_OwnAddress The CEC own address.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
@@ -314,7 +314,7 @@
 
 /**
   * @brief CEC MSP Init
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval None
   */
  __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
@@ -328,7 +328,7 @@
 
 /**
   * @brief CEC MSP DeInit
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval None
   */
  __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
@@ -380,11 +380,11 @@
 
 /**
   * @brief Send data in interrupt mode 
-  * @param hcec: CEC handle 
-  * @param InitiatorAddress: Initiator address
-  * @param DestinationAddress: destination logical address      
-  * @param pData: pointer to input byte data buffer
-  * @param Size: amount of data to be sent in bytes (without counting the header).
+  * @param hcec CEC handle 
+  * @param InitiatorAddress Initiator address
+  * @param DestinationAddress destination logical address      
+  * @param pData pointer to input byte data buffer
+  * @param Size amount of data to be sent in bytes (without counting the header).
   *              0 means only the header is sent (ping operation).
   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
   * @retval HAL status
@@ -440,7 +440,7 @@
 
 /**
   * @brief Get size of the received frame.
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval Frame size
   */
 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
@@ -450,8 +450,8 @@
 
 /**
   * @brief Change Rx Buffer.
-  * @param hcec: CEC handle
-  * @param Rxbuffer: Rx Buffer
+  * @param hcec CEC handle
+  * @param Rxbuffer Rx Buffer
   * @note  This function can be called only inside the HAL_CEC_RxCpltCallback() 
   * @retval Frame size
   */
@@ -462,7 +462,7 @@
   
 /**
   * @brief This function handles CEC interrupt requests.
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval None
   */
 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
@@ -567,7 +567,7 @@
 
 /**
   * @brief Tx Transfer completed callback
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval None
   */
  __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
@@ -581,8 +581,8 @@
 
 /**
   * @brief Rx Transfer completed callback
-  * @param hcec: CEC handle
-  * @param RxFrameSize: Size of frame
+  * @param hcec CEC handle
+  * @param RxFrameSize Size of frame
   * @retval None
   */
 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
@@ -597,7 +597,7 @@
 
 /**
   * @brief CEC error callbacks
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval None
   */
  __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
@@ -628,7 +628,7 @@
   */
 /**
   * @brief return the CEC state
-  * @param hcec: pointer to a CEC_HandleTypeDef structure that contains
+  * @param hcec pointer to a CEC_HandleTypeDef structure that contains
   *              the configuration information for the specified CEC module.
   * @retval HAL state
   */
@@ -643,7 +643,7 @@
 
 /**
   * @brief  Return the CEC error code
-  * @param  hcec : pointer to a CEC_HandleTypeDef structure that contains
+  * @param  hcec pointer to a CEC_HandleTypeDef structure that contains
   *              the configuration information for the specified CEC.
   * @retval CEC Error Code
   */
@@ -659,18 +659,18 @@
 /**
   * @}
   */
-  
-#endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */
-       /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
-       /* defined(STM32F091xC) || defined (STM32F098xx) */
 
-#endif /* HAL_CEC_MODULE_ENABLED */
 /**
   * @}
   */
 
 /**
   * @}
-  */
+  */  
+#endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */
+       /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
+       /* defined(STM32F091xC) || defined (STM32F098xx) */
+
+#endif /* HAL_CEC_MODULE_ENABLED */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_cec.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of CEC HAL module.
   ******************************************************************************
   * @attention
@@ -431,7 +429,7 @@
   */
 
 /** @brief  Reset CEC handle gstate & RxState
-  * @param  __HANDLE__: CEC handle.
+  * @param  __HANDLE__ CEC handle.
   * @retval None
   */
 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
@@ -440,8 +438,8 @@
                                                      } while(0)
 
 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
-  * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the CEC Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
   *            @arg CEC_FLAG_TXERR: Tx Error.
   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
@@ -460,8 +458,8 @@
 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__)) 
 
 /** @brief  Clears the interrupt or status flag when raised (write at 1)
-  * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __FLAG__: specifies the interrupt/status flag to clear.
+  * @param  __HANDLE__ specifies the CEC Handle.
+  * @param  __FLAG__ specifies the interrupt/status flag to clear.
   *        This parameter can be one of the following values:
   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
   *            @arg CEC_FLAG_TXERR: Tx Error.
@@ -481,8 +479,8 @@
 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__)) 
 
 /** @brief  Enables the specified CEC interrupt.
-  * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __INTERRUPT__: specifies the CEC interrupt to enable.
+  * @param  __HANDLE__ specifies the CEC Handle.
+  * @param  __INTERRUPT__ specifies the CEC interrupt to enable.
   *          This parameter can be one of the following values:
   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 
   *            @arg CEC_IT_TXERR: Tx Error IT Enable 
@@ -502,8 +500,8 @@
 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))  
 
 /** @brief  Disables the specified CEC interrupt.
-  * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __INTERRUPT__: specifies the CEC interrupt to disable.
+  * @param  __HANDLE__ specifies the CEC Handle.
+  * @param  __INTERRUPT__ specifies the CEC interrupt to disable.
   *          This parameter can be one of the following values:
   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 
   *            @arg CEC_IT_TXERR: Tx Error IT Enable 
@@ -523,8 +521,8 @@
 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))  
 
 /** @brief  Checks whether or not the specified CEC interrupt is enabled.
-  * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __INTERRUPT__: specifies the CEC interrupt to check.
+  * @param  __HANDLE__ specifies the CEC Handle.
+  * @param  __INTERRUPT__ specifies the CEC interrupt to check.
   *          This parameter can be one of the following values:
   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 
   *            @arg CEC_IT_TXERR: Tx Error IT Enable 
@@ -544,52 +542,52 @@
 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
 
 /** @brief  Enables the CEC device
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval none 
   */
 #define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)
 
 /** @brief  Disables the CEC device
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval none 
   */
 #define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)
 
 /** @brief  Set Transmission Start flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval none 
   */
 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)
 
 /** @brief  Set Transmission End flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval none 
   * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.  
   */
 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)
 
 /** @brief  Get Transmission Start flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval FlagStatus 
   */
 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
 
 /** @brief  Get Transmission End flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval FlagStatus 
   */
 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)   
 
 /** @brief  Clear OAR register
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval none 
   */
 #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
 
 /** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)
   *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
-  * @param  __HANDLE__: specifies the CEC Handle. 
-  * @param  __ADDRESS__: Own Address value (CEC logical address is identified by bit position)                   
+  * @param  __HANDLE__ specifies the CEC Handle. 
+  * @param  __ADDRESS__ Own Address value (CEC logical address is identified by bit position)                   
   * @retval none 
   */
 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
@@ -704,21 +702,21 @@
   *       The message size is the payload size: without counting the header, 
   *       it varies from 0 byte (ping operation, one header only, no payload) to 
   *       15 bytes (1 opcode and up to 14 operands following the header). 
-  * @param  __SIZE__: CEC message size.               
+  * @param  __SIZE__ CEC message size.               
   * @retval Test result (TRUE or FALSE).
   */
 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)  
                                                  
 /** @brief Check CEC device Own Address Register (OAR) setting.
   *        OAR address is written in a 15-bit field within CEC_CFGR register. 
-  * @param  __ADDRESS__: CEC own address.               
+  * @param  __ADDRESS__ CEC own address.               
   * @retval Test result (TRUE or FALSE).
   */
 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
 
 /** @brief Check CEC initiator or destination logical address setting.
   *        Initiator and destination addresses are coded over 4 bits. 
-  * @param  __ADDRESS__: CEC initiator or logical address.               
+  * @param  __ADDRESS__ CEC initiator or logical address.               
   * @retval Test result (TRUE or FALSE).
   */
 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU) 

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_comp.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   COMP HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the COMP peripheral:
@@ -188,7 +186,7 @@
 /* Literal set to maximum value (refer to device datasheet,                   */
 /* parameter "tSTART").                                                       */
 /* Unit: us                                                                   */
-#define LL_COMP_DELAY_STARTUP_US          (60U)  /*!< Delay for COMP startup time */
+#define COMP_DELAY_STARTUP_US           (60U)  /*!< Delay for COMP startup time */
 
 /* CSR register reset value */ 
 #define COMP_CSR_RESET_VALUE            (0x00000000U)
@@ -230,7 +228,7 @@
   *         parameters in the COMP_InitTypeDef and create the associated handle.
   * @note   If the selected comparator is locked, initialization can't be performed.
   *         To unlock the configuration, perform a system reset.
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
@@ -316,7 +314,7 @@
   * @brief  DeInitializes the COMP peripheral 
   * @note   Deinitialization can't be performed if the COMP configuration is locked.
   *         To unlock the configuration, perform a system reset.
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
@@ -357,7 +355,7 @@
 
 /**
   * @brief  Initializes the COMP MSP.
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval None
   */
 __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
@@ -372,7 +370,7 @@
 
 /**
   * @brief  DeInitializes COMP MSP.
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval None
   */
 __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
@@ -406,7 +404,7 @@
 
 /**
   * @brief  Start the comparator 
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
@@ -438,7 +436,7 @@
       hcomp->State = HAL_COMP_STATE_BUSY;
       
       /* Delay for COMP startup time */
-      wait_loop_index = (LL_COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000U));
+      wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000U));
       while(wait_loop_index != 0U)
       {
         wait_loop_index--;
@@ -455,7 +453,7 @@
 
 /**
   * @brief  Stop the comparator 
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
@@ -495,7 +493,7 @@
 
 /**
   * @brief  Enables the interrupt and starts the comparator
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
@@ -542,7 +540,7 @@
 
 /**
   * @brief  Disable the interrupt and Stop the comparator 
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
@@ -559,7 +557,7 @@
 
 /**
   * @brief  Comparator IRQ Handler 
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval HAL status
   */
 void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
@@ -598,7 +596,7 @@
 
 /**
   * @brief  Lock the selected comparator configuration. 
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
@@ -643,7 +641,7 @@
   *             voltage than the inverting input
   *           - Comparator output is low when the non-inverting input is at a higher
   *             voltage than the inverting input
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH.
   *       
   */
@@ -670,7 +668,7 @@
 
 /**
   * @brief  Comparator callback.
-  * @param  hcomp: COMP handle
+  * @param  hcomp COMP handle
   * @retval None
   */
 __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
@@ -705,7 +703,7 @@
 
 /**
   * @brief  Return the COMP state
-  * @param  hcomp : COMP handle
+  * @param  hcomp COMP handle
   * @retval HAL state
   */
 uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_comp.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of COMP HAL module.
   ******************************************************************************
   * @attention
@@ -262,14 +260,14 @@
   */
 
 /** @brief  Reset COMP handle state
-  * @param  __HANDLE__: COMP handle.
+  * @param  __HANDLE__ COMP handle.
   * @retval None
   */
 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
 
 /**
   * @brief  Enable the specified comparator.
-  * @param  __HANDLE__: COMP handle.
+  * @param  __HANDLE__ COMP handle.
   * @retval None
   */
 #define __HAL_COMP_ENABLE(__HANDLE__)                 (((__HANDLE__)->Instance == COMP1) ?    \
@@ -278,7 +276,7 @@
 
 /**
   * @brief  Disable the specified comparator.
-  * @param  __HANDLE__: COMP handle.
+  * @param  __HANDLE__ COMP handle.
   * @retval None
   */
 #define __HAL_COMP_DISABLE(__HANDLE__)                (((__HANDLE__)->Instance == COMP1) ?    \
@@ -287,7 +285,7 @@
 
 /**
   * @brief  Lock the specified comparator configuration.
-  * @param  __HANDLE__: COMP handle.
+  * @param  __HANDLE__ COMP handle.
   * @retval None
   */
 #define __HAL_COMP_LOCK(__HANDLE__)                   (((__HANDLE__)->Instance == COMP1) ?    \
@@ -463,8 +461,8 @@
 #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
 
 /** @brief  Check whether the specified COMP flag is set or not.
-  * @param  __HANDLE__: specifies the COMP Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the COMP Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg COMP_FLAG_LOCK:  lock flag
   * @retval The new state of __FLAG__ (TRUE or FALSE).
@@ -564,7 +562,7 @@
   */
 /**
   * @brief  Get the specified EXTI line for a comparator instance.
-  * @param  __INSTANCE__: specifies the COMP instance.
+  * @param  __INSTANCE__ specifies the COMP instance.
   * @retval value of @ref COMP_ExtiLine
   */
 #define COMP_GET_EXTI_LINE(__INSTANCE__)             (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_conf.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   HAL configuration file.
   ******************************************************************************
   * @attention
@@ -85,7 +83,7 @@
   *        (when HSE is used as system clock source, directly or through the PLL).  
   */
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE            8000000U  /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 /**
@@ -93,7 +91,7 @@
   *        Timeout value 
   */
 #if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
+  #define HSE_STARTUP_TIMEOUT  100U      /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
 /**
@@ -102,7 +100,7 @@
   *        (when HSI is used as system clock source, directly or through the PLL). 
   */
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (8000000U) /*!< Value of the Internal oscillator in Hz*/
+  #define HSI_VALUE            8000000U  /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
@@ -110,14 +108,14 @@
   *        Timeout value 
   */
 #if !defined  (HSI_STARTUP_TIMEOUT) 
- #define HSI_STARTUP_TIMEOUT   (5000U) /*!< Time out for HSI start up */
+  #define HSI_STARTUP_TIMEOUT  5000U     /*!< Time out for HSI start up */
 #endif /* HSI_STARTUP_TIMEOUT */  
 
 /**
   * @brief Internal High Speed oscillator for ADC (HSI14) value.
   */
 #if !defined  (HSI14_VALUE) 
-#define HSI14_VALUE (14000000U) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+  #define HSI14_VALUE          14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
 #endif /* HSI14_VALUE */
@@ -126,7 +124,7 @@
   * @brief Internal High Speed oscillator for USB (HSI48) value.
   */
 #if !defined  (HSI48_VALUE) 
-#define HSI48_VALUE (48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+  #define HSI48_VALUE          48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
 #endif /* HSI48_VALUE */
@@ -135,22 +133,22 @@
   * @brief Internal Low Speed oscillator (LSI) value.
   */
 #if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (40000U)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+  #define LSI_VALUE            40000U    
+#endif /* LSI_VALUE */                   /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
 /**
   * @brief External Low Speed oscillator (LSE) value.
   */
 #if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+  #define LSE_VALUE            32768U    /*!< Value of the External Low Speed oscillator in Hz */
 #endif /* LSE_VALUE */
 
 /**
   * @brief Time out for LSE start up value in ms.
   */
 #if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+  #define LSE_STARTUP_TIMEOUT  5000U     /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
 
@@ -161,14 +159,15 @@
 /**
   * @brief This is the HAL system configuration section
   */     
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */           
-#define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U)   /*!< tick interrupt priority (lowest by default)             */
+#define  VDD_VALUE                    3300U  /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default)             */
                                                                               /*  Warning: Must be set to higher priority for HAL_Delay()  */
                                                                               /*  and HAL_GetTick() usage under interrupt context          */
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     0
-#define  DATA_CACHE_ENABLE            0
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     0U
+#define  DATA_CACHE_ENABLE            0U
+#define  USE_SPI_CRC                  1U
 
 /* ########################## Assert Selection ############################## */
 /**
@@ -177,15 +176,6 @@
   */
 /*#define USE_FULL_ASSERT    1*/
 
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
 /* Includes ------------------------------------------------------------------*/
 /**
   * @brief Include module's header file 

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_cortex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   CORTEX HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the CORTEX:
@@ -140,13 +138,13 @@
 
 /**
   * @brief  Sets the priority of an interrupt.
-  * @param  IRQn: External interrupt number .
+  * @param  IRQn External interrupt number .
   *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
-  * @param  PreemptPriority: The preemption priority for the IRQn channel.
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file)
+  * @param  PreemptPriority The preemption priority for the IRQn channel.
   *         This parameter can be a value between 0 and 3.
   *         A lower priority value indicates a higher priority
-  * @param  SubPriority: the subpriority level for the IRQ channel.
+  * @param  SubPriority the subpriority level for the IRQ channel.
   *         with stm32f0xx devices, this parameter is a dummy value and it is ignored, because 
   *         no subpriority supported in Cortex M0 based products.   
   * @retval None
@@ -205,7 +203,7 @@
 /**
   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
   *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
   * @retval status:  - 0  Function succeeded.
   *                  - 1  Function failed.
   */
@@ -236,7 +234,7 @@
 
 /**
   * @brief  Gets the priority of an interrupt.
-  * @param  IRQn: External interrupt number.
+  * @param  IRQn External interrupt number.
   *         This parameter can be an enumerator of IRQn_Type enumeration
   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
   * @retval None
@@ -299,7 +297,7 @@
 
 /**
   * @brief  Configures the SysTick clock source.
-  * @param  CLKSource: specifies the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
   *         This parameter can be one of the following values:
   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_cortex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of CORTEX HAL module.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_crc.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   CRC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -13,19 +11,19 @@
   *         
   @verbatim
  ===============================================================================
-            ##### How to use this driver #####
+                     ##### How to use this driver #####
  ===============================================================================
     [..]
-         (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
-         (#) Initialize CRC calculator
+         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+         (+) Initialize CRC calculator
              (++)specify generating polynomial (IP default or non-default one)
              (++)specify initialization value (IP default or non-default one)
              (++)specify input data format
              (++)specify input or output data inversion mode if any
-         (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the 
+         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the 
              input data buffer starting with the previously computed CRC as 
              initialization value
-         (#) Use HAL_CRC_Calculate() function to compute the CRC value of the 
+         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the 
              input data buffer starting with the defined initialization value 
              (default or non-default) to initiate CRC calculation
 
@@ -57,7 +55,7 @@
   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
-  ******************************************************************************  
+  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -67,7 +65,7 @@
   * @{
   */
 
-/** @defgroup CRC CRC 
+/** @defgroup CRC CRC
   * @brief CRC HAL module driver.
   * @{
   */
@@ -87,34 +85,35 @@
 /**
   * @}
   */
-  
-/* Exported functions ---------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
 /** @defgroup CRC_Exported_Functions CRC Exported Functions
   * @{
   */
 
-/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions 
+/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
  *  @brief    Initialization and Configuration functions. 
  *
 @verbatim    
  ===============================================================================
-            ##### Initialization and Configuration functions #####
+            ##### Initialization and de-initialization functions #####
  ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Initialize the CRC according to the specified parameters 
           in the CRC_InitTypeDef and create the associated handle
       (+) DeInitialize the CRC peripheral
-      (+) Initialize the CRC MSP
-      (+) DeInitialize CRC MSP 
+      (+) Initialize the CRC MSP (MCU Specific Package)
+      (+) DeInitialize the CRC MSP
  
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the CRC according to the specified
-  *         parameters in the CRC_InitTypeDef and creates the associated handle.
-  * @param  hcrc: CRC handle
+  * @brief  Initialize the CRC according to the specified
+  *         parameters in the CRC_InitTypeDef and initialize the associated handle.
+  * @param  hcrc CRC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
@@ -132,6 +131,7 @@
   {   
     /* Allocate lock resource and initialize it */
     hcrc->Lock = HAL_UNLOCKED;
+
     /* Init the low level hardware */
     HAL_CRC_MspInit(hcrc);
   }
@@ -181,8 +181,8 @@
 }
 
 /**
-  * @brief  DeInitializes the CRC peripheral. 
-  * @param  hcrc: CRC handle
+  * @brief  DeInitialize the CRC peripheral. 
+  * @param  hcrc CRC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
@@ -205,6 +205,9 @@
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_BUSY;
   
+  /* Reset CRC calculation unit */
+  __HAL_CRC_DR_RESET(hcrc);
+  
   /* Reset IDR register content */
   CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
 
@@ -223,7 +226,7 @@
 
 /**
   * @brief  Initializes the CRC MSP.
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
   * @retval None
   */
 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
@@ -237,8 +240,8 @@
 }
 
 /**
-  * @brief  DeInitializes the CRC MSP.
-  * @param  hcrc: CRC handle
+  * @brief  DeInitialize the CRC MSP.
+  * @param  hcrc CRC handle
   * @retval None
   */
 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
@@ -263,12 +266,12 @@
                       ##### Peripheral Control functions #####
  ===============================================================================  
     [..]  This section provides functions allowing to:
-      (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
-          using combination of the previous CRC value and the new one.
+      (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
+          using the combination of the previous CRC value and the new one
           
-          or
+       [..]  or
           
-      (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+      (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
           independently of the previous CRC value.
 
 @endverbatim
@@ -278,16 +281,16 @@
 /**                  
   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
   *         starting with the previously computed CRC as initialization value.
-  * @param  hcrc: CRC handle
-  * @param  pBuffer: pointer to the input data buffer, exact input data format is
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer, exact input data format is
   *         provided by hcrc->InputDataFormat.  
-  * @param  BufferLength: input data buffer length (number of bytes if pBuffer
+  * @param  BufferLength input data buffer length (number of bytes if pBuffer
   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
   *         number of words if pBuffer type is * uint32_t).
   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
   *        Input buffer pointers with other types simply need to be cast in uint32_t
-  *        and the API will internally adjust its input data processing based on the  
-  *        handle field hcrc->InputDataFormat.              
+  *        and the API will internally adjust its input data processing based on the
+  *        handle field hcrc->InputDataFormat.
   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
   */
 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
@@ -319,9 +322,9 @@
     case CRC_INPUTDATA_FORMAT_HALFWORDS: 
       temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
       break;
-    
+      
     default:
-      break;
+      break;          
   }
   
   /* Change CRC peripheral state */    
@@ -338,15 +341,15 @@
 /**                  
   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
   *         starting with hcrc->Instance->INIT as initialization value.
-  * @param  hcrc: CRC handle
-  * @param  pBuffer: pointer to the input data buffer, exact input data format is
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer, exact input data format is
   *         provided by hcrc->InputDataFormat.  
-  * @param  BufferLength: input data buffer length (number of bytes if pBuffer
+  * @param  BufferLength input data buffer length (number of bytes if pBuffer
   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
   *         number of words if pBuffer type is * uint32_t).
   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
   *        Input buffer pointers with other types simply need to be cast in uint32_t
-  *        and the API will internally adjust its input data processing based on the  
+  *        and the API will internally adjust its input data processing based on the
   *        handle field hcrc->InputDataFormat. 
   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
   */  
@@ -385,9 +388,9 @@
       /* Specific 16-bit input data handling  */
       temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
       break;
-
+      
     default:
-      break;
+      break;         
   }
 
   /* Change CRC peripheral state */    
@@ -399,6 +402,7 @@
   /* Return the CRC computed value */ 
   return temp;
 }
+  
 /**
   * @}
   */
@@ -411,20 +415,20 @@
                       ##### Peripheral State functions #####
  ===============================================================================  
     [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
+    This subsection permits to get in run-time the status of the peripheral.
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Returns the CRC state.
-  * @param  hcrc: CRC handle
+  * @brief  Return the CRC handle state.
+  * @param  hcrc CRC handle
   * @retval HAL state
   */
 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
 {
+  /* Return CRC handle state */
   return hcrc->State;
 }
 
@@ -436,15 +440,16 @@
   * @}
   */
 
-/** @addtogroup CRC_Private_Functions CRC Private Functions
+/** @defgroup CRC_Private_Functions CRC Private Functions
   * @{
   */
+
 /**             
   * @brief  Enter 8-bit input data to the CRC calculator.
   *         Specific data handling to optimize processing time.  
-  * @param  hcrc: CRC handle
-  * @param  pBuffer: pointer to the input data buffer
-  * @param  BufferLength: input data buffer length
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer
+  * @param  BufferLength input data buffer length
   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
   */
 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
@@ -456,23 +461,23 @@
     * handling by the IP */
    for(i = 0U; i < (BufferLength/4U); i++)
    {
-      hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24U) | ((uint32_t)pBuffer[4*i+1]<<16U) | ((uint32_t)pBuffer[4*i+2]<<8U) | (uint32_t)pBuffer[4*i+3];      
+      hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1]<<16U) | ((uint32_t)pBuffer[4U*i+2]<<8U) | (uint32_t)pBuffer[4U*i+3];      
    }
    /* last bytes specific handling */
-   if ((BufferLength%4) != 0U)
+   if ((BufferLength%4U) != 0U)
    {
-     if  (BufferLength%4 == 1U)
+     if  (BufferLength%4U == 1U)
      {
-       *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
+       *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
      }
-     if  (BufferLength%4 == 2U)
+     if  (BufferLength%4U == 2U)
      {
-       *(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8U) | (uint16_t)pBuffer[4*i+1];
+       *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
      }
-     if  (BufferLength%4 == 3U)
+     if  (BufferLength%4U == 3U)
      {
-       *(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8U) | (uint16_t)pBuffer[4*i+1];
-       *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];       
+       *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+       *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];       
      }
    }
   
@@ -485,38 +490,35 @@
 /**             
   * @brief  Enter 16-bit input data to the CRC calculator.
   *         Specific data handling to optimize processing time.  
-  * @param  hcrc: CRC handle
-  * @param  pBuffer: pointer to the input data buffer
-  * @param  BufferLength: input data buffer length
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer
+  * @param  BufferLength input data buffer length
   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
   */  
 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
 {
-  uint32_t i = 0;  /* input data buffer index */
+  uint32_t i = 0U;  /* input data buffer index */
   
   /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
    * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure 
    * a correct type handling by the IP */
-  for(i = 0; i < (BufferLength/2); i++)
+  for(i = 0U; i < (BufferLength/2U); i++)
   {
-    hcrc->Instance->DR = (pBuffer[2*i]<<16U) | pBuffer[2*i+1];     
+    hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1];     
   }
-  if ((BufferLength%2) != 0U)
+  if ((BufferLength%2U) != 0U)
   {
-    *(uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; 
+       *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i]; 
   }
    
   /* Return the CRC computed value */ 
   return hcrc->Instance->DR;
 }
-/**
-  * @}
-  */
 
 /**
   * @}
   */
-
+  
 #endif /* HAL_CRC_MODULE_ENABLED */
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_crc.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of CRC HAL module.
   ******************************************************************************
   * @attention
@@ -224,37 +222,37 @@
   */
 
 /** @brief Reset CRC handle state
-  * @param  __HANDLE__: CRC handle.
+  * @param  __HANDLE__ CRC handle.
   * @retval None
   */
 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
 
 /**
   * @brief  Reset CRC Data Register.
-  * @param  __HANDLE__: CRC handle
+  * @param  __HANDLE__ CRC handle
   * @retval None.
   */
 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
 
 /**
   * @brief  Set CRC INIT non-default value
-  * @param  __HANDLE__    : CRC handle
-  * @param  __INIT__      : 32-bit initial value  
+  * @param  __HANDLE__ CRC handle
+  * @param  __INIT__   32-bit initial value  
   * @retval None.
   */
 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))    
 
 /**
   * @brief Stores a 8-bit data in the Independent Data(ID) register.
-  * @param __HANDLE__: CRC handle
-  * @param __VALUE__: 8-bit value to be stored in the ID register
+  * @param __HANDLE__ CRC handle
+  * @param __VALUE__ 8-bit value to be stored in the ID register
   * @retval None
   */
 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
 
 /**
   * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
-  * @param __HANDLE__: CRC handle
+  * @param __HANDLE__ CRC handle
   * @retval 8-bit value of the ID register 
   */
 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_crc_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Extended CRC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the CRC peripheral:
@@ -96,7 +94,7 @@
 
 /**
   * @brief  Extended initialization to set generating polynomial
-  * @param  hcrc: CRC handle             
+  * @param  hcrc CRC handle             
   * @retval HAL status
   */             
 HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc)
@@ -126,8 +124,8 @@
 
 /**
   * @brief  Set the Reverse Input data mode.
-  * @param  hcrc: CRC handle
-  * @param  InputReverseMode: Input Data inversion mode
+  * @param  hcrc CRC handle
+  * @param  InputReverseMode Input Data inversion mode
   *         This parameter can be one of the following values:
   *          @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
   *          @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
@@ -154,8 +152,8 @@
 
 /**
   * @brief  Set the Reverse Output data mode.
-  * @param  hcrc: CRC handle
-  * @param  OutputReverseMode: Output Data inversion mode
+  * @param  hcrc CRC handle
+  * @param  OutputReverseMode Output Data inversion mode
   *         This parameter can be one of the following values:
   *          @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
   *          @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)            
@@ -182,12 +180,12 @@
 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx)
 /**
   * @brief  Initializes the CRC polynomial if different from default one.
-  * @param  hcrc: CRC handle
-  * @param  Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)
+  * @param  hcrc CRC handle
+  * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long)
   *         This parameter is written in normal representation, e.g.
   *         for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 
   *         for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021     
-  * @param  PolyLength: CRC polynomial length 
+  * @param  PolyLength CRC polynomial length 
   *         This parameter can be one of the following values:
   *          @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
   *          @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_crc_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of CRC HAL extension module.
   ******************************************************************************
   * @attention
@@ -133,14 +131,14 @@
     
 /**
   * @brief  Set CRC output reversal
-  * @param  __HANDLE__    : CRC handle
+  * @param  __HANDLE__ CRC handle
   * @retval None.
   */
 #define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)   
 
 /**
   * @brief  Unset CRC output reversal
-  * @param  __HANDLE__    : CRC handle
+  * @param  __HANDLE__ CRC handle
   * @retval None.
   */
 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))   
@@ -148,8 +146,8 @@
 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
 /**
   * @brief  Set CRC non-default polynomial
-  * @param  __HANDLE__    : CRC handle
-  * @param  __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial  
+  * @param  __HANDLE__ CRC handle
+  * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial  
   * @retval None.
   */
 #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_dac.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -257,7 +255,7 @@
 /**
   * @brief  Initialize the DAC peripheral according to the specified parameters
   *         in the DAC_InitStruct and initialize the associated handle.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval HAL status
   */
@@ -295,7 +293,7 @@
 
 /**
   * @brief  Deinitialize the DAC peripheral registers to their default reset values.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval HAL status
   */
@@ -331,7 +329,7 @@
 
 /**
   * @brief  Initialize the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -347,7 +345,7 @@
 
 /**
   * @brief  DeInitialize the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.  
   * @retval None
   */
@@ -385,9 +383,9 @@
 
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -408,9 +406,9 @@
 
 /**
   * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
@@ -433,15 +431,15 @@
 
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  pData: The destination peripheral Buffer address.
-  * @param  Length: The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment: Specifies the data alignment for DAC channel.
+  * @param  pData The destination peripheral Buffer address.
+  * @param  Length The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment Specifies the data alignment for DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@@ -466,9 +464,9 @@
 
 /**
   * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected   
@@ -531,7 +529,7 @@
 
 /**
   * @brief  Handles DAC interrupt request  
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -546,18 +544,18 @@
 
 /**
   * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
-  * @param  Alignment: Specifies the data alignment.
+  * @param  Alignment Specifies the data alignment.
   *          This parameter can be one of the following values:
   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data: Data to be loaded in the selected data holding register.
+  * @param  Data Data to be loaded in the selected data holding register.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
@@ -588,7 +586,7 @@
 
 /**
   * @brief  Conversion complete callback in non blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -604,7 +602,7 @@
 
 /**
   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -620,7 +618,7 @@
 
 /**
   * @brief  Error DAC callback for Channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -636,7 +634,7 @@
 
 /**
   * @brief  DMA underrun DAC callback for channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -671,9 +669,9 @@
 
 /**
   * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -694,10 +692,10 @@
 
 /**
   * @brief  Configures the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure.
-  * @param  Channel: The selected DAC channel. 
+  * @param  sConfig DAC configuration structure.
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -739,7 +737,7 @@
 
 /**
   * @brief  return the DAC handle state
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval HAL state
   */
@@ -752,7 +750,7 @@
 
 /**
   * @brief  Return the DAC error code
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval DAC Error Code
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of DAC HAL module.
   ******************************************************************************
   * @attention
@@ -180,30 +178,30 @@
   */
 
 /** @brief Reset DAC handle state
-  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __HANDLE__ specifies the DAC handle.
   * @retval None
   */
 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
 
 /** @brief Enable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __DAC_Channel__: specifies the DAC channel
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __DAC_Channel__ specifies the DAC channel
   * @retval None
   */
 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
 ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
 
 /** @brief Disable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __DAC_Channel__: specifies the DAC channel.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __DAC_Channel__ specifies the DAC channel.
   * @retval None
   */
 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
 ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
  
 /** @brief Enable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __INTERRUPT__ specifies the DAC interrupt.
   *          This parameter can be any combination of the following values:
   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@@ -212,8 +210,8 @@
 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
 
 /** @brief Disable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __INTERRUPT__ specifies the DAC interrupt.
   *          This parameter can be any combination of the following values:
   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
   * @retval None
@@ -221,8 +219,8 @@
 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
 
 /** @brief  Check whether the specified DAC interrupt source is enabled or not
-  * @param __HANDLE__: DAC handle
-  * @param __INTERRUPT__: DAC interrupt source to check
+  * @param __HANDLE__ DAC handle
+  * @param __INTERRUPT__ DAC interrupt source to check
   *          This parameter can be any combination of the following values:
   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@@ -231,8 +229,8 @@
 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /** @brief  Get the selected DAC's flag status
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the DAC flag to get.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __FLAG__ specifies the DAC flag to get.
   *          This parameter can be any combination of the following values:
   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
   * @retval None
@@ -240,8 +238,8 @@
 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the DAC's flag
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the DAC flag to clear.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __FLAG__ specifies the DAC flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
   * @retval None
@@ -284,19 +282,19 @@
 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) 
 
 /** @brief Set DHR12R1 alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
 
 /** @brief  Set DHR12R2 alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
 
 /** @brief  Set DHR12RD alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_dac_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   DAC HAL module driver.
   *          This file provides firmware functions to manage the extended 
   *          functionalities of the DAC peripheral.  
@@ -116,10 +114,10 @@
 
 /**
   * @brief  Configures the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure.
-  * @param  Channel: The selected DAC channel. 
+  * @param  sConfig DAC configuration structure.
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -171,10 +169,10 @@
 
 /**
   * @brief  Configures the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure.
-  * @param  Channel: The selected DAC channel. 
+  * @param  sConfig DAC configuration structure.
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   * @retval HAL status
@@ -226,9 +224,9 @@
 
 /**
   * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -259,9 +257,9 @@
 
 /**
   * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
     * @retval The selected DAC channel data output value.
@@ -292,9 +290,9 @@
 
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -345,15 +343,15 @@
 
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  pData: The destination peripheral Buffer address.
-  * @param  Length: The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment: Specifies the data alignment for DAC channel.
+  * @param  pData The destination peripheral Buffer address.
+  * @param  Length The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment Specifies the data alignment for DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@@ -512,14 +510,14 @@
 
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  * @param  pData: The destination peripheral Buffer address.
-  * @param  Length: The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment: Specifies the data alignment for DAC channel.
+  * @param  pData The destination peripheral Buffer address.
+  * @param  Length The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment Specifies the data alignment for DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@@ -602,7 +600,7 @@
 
 /**
   * @brief  Handles DAC interrupt request  
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -660,7 +658,7 @@
 
 /**
   * @brief  Handles DAC interrupt request  
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -709,7 +707,7 @@
 
 /**
   * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -724,7 +722,7 @@
 
 /**
   * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -737,7 +735,7 @@
 
 /**
   * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -768,7 +766,7 @@
 
 /**
   * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -783,7 +781,7 @@
 
 /**
   * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -796,7 +794,7 @@
 
 /**
   * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -870,7 +868,7 @@
       
 /**
   * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval The selected DAC channel data output value.
   */
@@ -894,7 +892,7 @@
 
 /**
   * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval The selected DAC channel data output value.
   */
@@ -915,12 +913,12 @@
 
 /**
   * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            DAC_CHANNEL_1 / DAC_CHANNEL_2
-  * @param  Amplitude: Select max triangle amplitude. 
+  * @param  Amplitude Select max triangle amplitude. 
   *          This parameter can be one of the following values:
   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
@@ -963,12 +961,12 @@
 
 /**
   * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC. 
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            DAC_CHANNEL_1 / DAC_CHANNEL_2
-  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation. 
+  * @param  Amplitude Unmask DAC channel LFSR for noise wave generation. 
   *          This parameter can be one of the following values: 
   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation  
@@ -1035,15 +1033,15 @@
 
 /**
   * @brief  Set the specified data holding register value for dual DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *               the configuration information for the specified DAC.
-  * @param  Alignment: Specifies the data alignment for dual channel DAC.
+  * @param  Alignment Specifies the data alignment for dual channel DAC.
   *          This parameter can be one of the following values:
   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
-  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
+  * @param  Data1 Data for DAC Channel2 to be loaded in the selected data holding register.
+  * @param  Data2 Data for DAC Channel1 to be loaded in the selected data  holding register.
   * @note   In dual mode, a unique register access is required to write in both
   *          DAC channels at the same time.
   * @retval HAL status
@@ -1103,7 +1101,7 @@
 
 /**
   * @brief  Conversion complete callback in non blocking mode for Channel2 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -1119,7 +1117,7 @@
 
 /**
   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -1135,7 +1133,7 @@
 
 /**
   * @brief  Error DAC callback for Channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -1151,7 +1149,7 @@
 
 /**
   * @brief  DMA underrun DAC callback for channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_dac_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of DAC HAL Extension module.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_def.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   This file contains HAL common defines, enumeration, macros and 
   *          structures definitions. 
   ******************************************************************************
@@ -46,7 +44,9 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f0xx.h"
+#if defined(USE_HAL_LEGACY)
 #include "stm32_hal_legacy.h"
+#endif
 #include <stdio.h>
 
 /* Exported types ------------------------------------------------------------*/
@@ -87,7 +87,7 @@
 #define UNUSED(x) ((void)(x))                            
                             
 /** @brief Reset the Handle's State field.
-  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @param __HANDLE__ specifies the Peripheral Handle.
   * @note  This macro can be used for the following purpose:
   *          - When the Handle is declared as local variable; before passing it as parameter
   *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
@@ -124,7 +124,7 @@
                                     }while (0)
 #endif /* USE_RTOS */
 
-#if  defined ( __GNUC__ ) && !defined ( __CC_ARM )
+#if  defined ( __GNUC__ )
   #ifndef __weak
     #define __weak   __attribute__((weak))
   #endif /* __weak */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_dma.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   DMA HAL module driver.
   *    
   *         This file provides firmware functions to manage the following 
@@ -149,7 +147,7 @@
 /**
   * @brief  Initialize the DMA according to the specified
   *         parameters in the DMA_InitTypeDef and initialize the associated handle.
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Channel.  
   * @retval HAL status
   */
@@ -217,7 +215,7 @@
   
 /**
   * @brief  DeInitialize the DMA peripheral 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Channel.  
   * @retval HAL status
   */
@@ -290,11 +288,11 @@
 
 /**
   * @brief  Start the DMA Transfer.
-  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Channel.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Channel.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -337,11 +335,11 @@
 
 /**
   * @brief  Start the DMA Transfer with interrupt enabled.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Channel.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -396,8 +394,8 @@
 
 /**
   * @brief  Abort the DMA Transfer.
-  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Channel.                  
+  * @param  hdma  pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.                  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
@@ -422,8 +420,8 @@
 
 /**
   * @brief  Abort the DMA Transfer in Interrupt mode.
-  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Stream.
+  * @param  hdma  pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
@@ -466,10 +464,10 @@
 
 /**
   * @brief  Polling for transfer complete.
-  * @param  hdma:    pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma    pointer to a DMA_HandleTypeDef structure that contains
   *                  the configuration information for the specified DMA Channel.
-  * @param  CompleteLevel: Specifies the DMA level complete.  
-  * @param  Timeout:       Timeout duration.
+  * @param  CompleteLevel Specifies the DMA level complete.  
+  * @param  Timeout       Timeout duration.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
@@ -569,7 +567,7 @@
 
 /**
   * @brief  Handle DMA interrupt request.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Channel.  
   * @retval None
   */
@@ -657,11 +655,11 @@
 
 /**
   * @brief  Register callbacks
-  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
   *                               the configuration information for the specified DMA Stream.
-  * @param  CallbackID:           User Callback identifer
+  * @param  CallbackID           User Callback identifer
   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
-  * @param  pCallback:            pointer to private callback function which has pointer to 
+  * @param  pCallback            pointer to private callback function which has pointer to 
   *                               a DMA_HandleTypeDef structure as parameter.
   * @retval HAL status
   */                          
@@ -710,9 +708,9 @@
 
 /**
   * @brief  UnRegister callbacks
-  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
   *                               the configuration information for the specified DMA Stream.
-  * @param  CallbackID:           User Callback identifer
+  * @param  CallbackID           User Callback identifer
   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
   * @retval HAL status
   */              
@@ -788,7 +786,7 @@
 
 /**
   * @brief  Returns the DMA state.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Channel.  
   * @retval HAL state
   */
@@ -799,7 +797,7 @@
 
 /**
   * @brief  Return the DMA error code
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *              the configuration information for the specified DMA Channel.
   * @retval DMA Error Code
   */
@@ -822,11 +820,11 @@
 
 /**
   * @brief  Set the DMA Transfer parameters.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Channel.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -837,7 +835,7 @@
   /* Configure DMA Channel data length */
   hdma->Instance->CNDTR = DataLength;
   
-  /* Peripheral to Memory */
+  /* Memory to Peripheral */
   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
   {   
     /* Configure DMA Channel destination address */
@@ -846,7 +844,7 @@
     /* Configure DMA Channel source address */
     hdma->Instance->CMAR = SrcAddress;
   }
-  /* Memory to Peripheral */
+  /* Peripheral to Memory */
   else
   {
     /* Configure DMA Channel source address */
@@ -859,7 +857,7 @@
 
 /**
   * @brief  set the DMA base address and channel index depending on DMA instance
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Stream. 
   * @retval None
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_dma.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
@@ -365,21 +363,21 @@
   */
 
 /** @brief  Reset DMA handle state
-  * @param  __HANDLE__: DMA handle.
+  * @param  __HANDLE__ DMA handle.
   * @retval None
   */
 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 
 /**
   * @brief  Enable the specified DMA Channel.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval None
   */
 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
 
 /**
   * @brief  Disable the specified DMA Channel.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval None
   */
 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
@@ -389,8 +387,8 @@
 
 /**
   * @brief  Enables the specified DMA Channel interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__ DMA handle
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
   *          This parameter can be any combination of the following values:
   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
@@ -401,8 +399,8 @@
 
 /**
   * @brief  Disables the specified DMA Channel interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__ DMA handle
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
   *          This parameter can be any combination of the following values:
   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
@@ -413,8 +411,8 @@
 
 /**
   * @brief  Checks whether the specified DMA Channel interrupt is enabled or disabled.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
@@ -425,7 +423,7 @@
 
 /**
   * @brief  Returns the number of remaining data units in the current DMAy Channelx transfer.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   *   
   * @retval The number of remaining data units in the current DMA Channel transfer.
   */
@@ -433,7 +431,7 @@
 
 #if defined(SYSCFG_CFGR1_DMA_RMP)
 /** @brief  DMA remapping enable/disable macros
-  * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
+  * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping
   */
 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__)   do {assert_param(IS_DMA_REMAP((__DMA_REMAP__)));                  \
                                                            SYSCFG->CFGR1 |= (__DMA_REMAP__);                              \

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_dma_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of DMA HAL Extension module.
   ******************************************************************************
   * @attention
@@ -523,7 +521,7 @@
 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
 /**
   * @brief  Returns the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer complete flag index.
   */      
 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@@ -537,7 +535,7 @@
 
 /**
   * @brief  Returns the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified half transfer complete flag index.
   */      
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@@ -551,7 +549,7 @@
 
 /**
   * @brief  Returns the current DMA Channel transfer error flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@@ -565,7 +563,7 @@
 
 /**
   * @brief  Return the current DMA Channel Global interrupt flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
@@ -579,8 +577,8 @@
 
 /**
   * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
@@ -593,8 +591,8 @@
 
 /**
   * @brief  Clears the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
@@ -607,7 +605,7 @@
 #elif defined(STM32F091xC) || defined(STM32F098xx)
 /**
   * @brief  Returns the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer complete flag index.
   */      
 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@@ -626,7 +624,7 @@
 
 /**
   * @brief  Returns the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified half transfer complete flag index.
   */      
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@@ -645,7 +643,7 @@
 
 /**
   * @brief  Returns the current DMA Channel transfer error flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@@ -664,7 +662,7 @@
 
 /**
   * @brief  Return the current DMA Channel Global interrupt flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
@@ -683,8 +681,8 @@
 
 /**
   * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
@@ -699,8 +697,8 @@
 
 /**
   * @brief  Clears the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
@@ -715,7 +713,7 @@
 #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
 /**
   * @brief  Returns the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer complete flag index.
   */      
 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@@ -727,7 +725,7 @@
 
 /**
   * @brief  Returns the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified half transfer complete flag index.
   */      
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@@ -739,7 +737,7 @@
 
 /**
   * @brief  Returns the current DMA Channel transfer error flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@@ -751,7 +749,7 @@
 
 /**
   * @brief  Return the current DMA Channel Global interrupt flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
@@ -763,8 +761,8 @@
 
 /**
   * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
@@ -777,8 +775,8 @@
 
 /**
   * @brief  Clears the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_flash.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the internal FLASH memory:
@@ -436,7 +434,7 @@
 
 /**
   * @brief  FLASH end of operation interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
   *                 - Mass Erase: No return value expected
   *                 - Pages Erase: Address of the page which has been erased 
   *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
@@ -455,7 +453,7 @@
 
 /**
   * @brief  FLASH operation error interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
   *                 - Mass Erase: No return value expected
   *                 - Pages Erase: Address of the page which returned an error
   *                 - Program: Address which was selected for data program

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_flash.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of Flash HAL module.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_flash_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Extended FLASH HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -921,26 +919,23 @@
   */
 static uint32_t FLASH_OB_GetRDP(void)
 {
-  uint32_t readstatus = OB_RDP_LEVEL_0;
-  uint32_t tmp_reg = 0;
+  uint32_t tmp_reg = 0U;
   
   /* Read RDP level bits */
   tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2));
 
   if (tmp_reg == FLASH_OBR_RDPRT1)
   {
-    readstatus = OB_RDP_LEVEL_1;
+    return OB_RDP_LEVEL_1;
   }
   else if (tmp_reg == FLASH_OBR_RDPRT2)
   {
-    readstatus = OB_RDP_LEVEL_2;
+    return OB_RDP_LEVEL_2;
   }
   else 
   {
-    readstatus = OB_RDP_LEVEL_0;
+    return OB_RDP_LEVEL_0;
   }
-
-  return readstatus;
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_flash_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of Flash HAL Extended module.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_gpio.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   GPIO HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -180,8 +178,8 @@
 
 /**
   * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
-  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
   *         the configuration information for the specified GPIO peripheral.
   * @retval None
   */
@@ -305,8 +303,8 @@
 
 /**
   * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
-  * @param  GPIO_Pin: specifies the port bit to be written.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+  * @param  GPIO_Pin specifies the port bit to be written.
   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
   * @retval None
   */
@@ -386,8 +384,8 @@
 
 /**
   * @brief  Read the specified input port pin.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
-  * @param  GPIO_Pin: specifies the port bit to read.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+  * @param  GPIO_Pin specifies the port bit to read.
   *         This parameter can be GPIO_PIN_x where x can be (0..15).
   * @retval The input port pin value.
   */
@@ -415,10 +413,10 @@
   *         accesses. In this way, there is no risk of an IRQ occurring between
   *         the read and the modify access.
   *
-  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32F0 family
-  * @param  GPIO_Pin: specifies the port bit to be written.
+  * @param  GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family
+  * @param  GPIO_Pin specifies the port bit to be written.
   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @param  PinState: specifies the value to be written to the selected bit.
+  * @param  PinState specifies the value to be written to the selected bit.
   *          This parameter can be one of the GPIO_PinState enum values:
   *            @arg GPIO_PIN_RESET: to clear the port pin
   *            @arg GPIO_PIN_SET: to set the port pin
@@ -442,8 +440,8 @@
   
 /**
   * @brief  Toggle the specified GPIO pin.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
-  * @param  GPIO_Pin: specifies the pin to be toggled.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+  * @param  GPIO_Pin specifies the pin to be toggled.
   * @retval None
   */
 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@@ -460,8 +458,8 @@
 *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
 * @note   The configuration of the locked GPIO pins can no longer be modified
 *         until the next reset.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
-  * @param  GPIO_Pin: specifies the port bits to be locked.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+  * @param  GPIO_Pin specifies the port bits to be locked.
 *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
 * @retval None
 */
@@ -496,7 +494,7 @@
 
 /**
   * @brief  Handle EXTI interrupt request.
-  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
   * @retval None
   */
 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
@@ -511,7 +509,7 @@
 
 /**
   * @brief  EXTI line detection callback.
-  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
   * @retval None
   */
 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_gpio.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of GPIO HAL module.
   ******************************************************************************
   * @attention
@@ -181,7 +179,7 @@
   
 /**
   * @brief  Check whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
   *         This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
@@ -189,7 +187,7 @@
 
 /**
   * @brief  Clear the EXTI's line pending flags.
-  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
@@ -197,7 +195,7 @@
 
 /**
   * @brief  Check whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
   *          This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
@@ -205,7 +203,7 @@
 
 /**
   * @brief  Clear the EXTI's line pending bits.
-  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
@@ -213,7 +211,7 @@
 
 /**
   * @brief  Generate a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
   *          This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval None
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_gpio_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of GPIO HAL Extension module.
   ******************************************************************************
   * @attention
@@ -76,6 +74,7 @@
 #define GPIO_AF0_TIM14        ((uint8_t)0x00U)  /*!< AF0: TIM14 Alternate Function mapping     */
 #define GPIO_AF0_USART1       ((uint8_t)0x00U)  /*!< AF0: USART1 Alternate Function mapping    */
 #define GPIO_AF0_IR           ((uint8_t)0x00U)  /*!< AF0: IR Alternate Function mapping        */
+#define GPIO_AF0_TIM3         ((uint8_t)0x00U)  /*!< AF0: TIM3 Alternate Function mapping      */
 
 /* AF 1 */
 #define GPIO_AF1_TIM3         ((uint8_t)0x01U)  /*!< AF1: TIM3 Alternate Function mapping      */
@@ -123,6 +122,7 @@
 #define GPIO_AF0_TIM14        ((uint8_t)0x00U)  /*!< AF0: TIM14 Alternate Function mapping     */
 #define GPIO_AF0_USART1       ((uint8_t)0x00U)  /*!< AF0: USART1 Alternate Function mapping    */
 #define GPIO_AF0_IR           ((uint8_t)0x00U)  /*!< AF0: IR Alternate Function mapping        */
+#define GPIO_AF0_TIM3         ((uint8_t)0x00U)  /*!< AF0: TIM3 Alternate Function mapping      */
 
 /* AF 1 */
 #define GPIO_AF1_TIM3         ((uint8_t)0x01U)  /*!< AF1: TIM3 Alternate Function mapping      */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_i2c.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   I2C HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -238,7 +236,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f0xx_hal.h"
@@ -366,7 +364,7 @@
   */
 
 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions 
+ *  @brief    Initialization and Configuration functions
  *
 @verbatim
  ===============================================================================
@@ -406,7 +404,7 @@
 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
 {
   /* Check the I2C handle allocation */
-  if(hi2c == NULL)
+  if (hi2c == NULL)
   {
     return HAL_ERROR;
   }
@@ -421,7 +419,7 @@
   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
 
-  if(hi2c->State == HAL_I2C_STATE_RESET)
+  if (hi2c->State == HAL_I2C_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hi2c->Lock = HAL_UNLOCKED;
@@ -444,7 +442,7 @@
   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
 
   /* Configure I2Cx: Own Address1 and ack own address1 mode */
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
   {
     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
   }
@@ -455,7 +453,7 @@
 
   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
   /* Configure I2Cx: Addressing Master mode */
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
   {
     hi2c->Instance->CR2 = (I2C_CR2_ADD10);
   }
@@ -493,7 +491,7 @@
 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
 {
   /* Check the I2C handle allocation */
-  if(hi2c == NULL)
+  if (hi2c == NULL)
   {
     return HAL_ERROR;
   }
@@ -557,7 +555,7 @@
   */
 
 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- *  @brief   Data transfers functions 
+ *  @brief   Data transfers functions
  *
 @verbatim
  ===============================================================================
@@ -569,7 +567,7 @@
 
     (#) There are two modes of transfer:
        (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function 
+            The status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode : The communication is performed using Interrupts
             or DMA. These functions return the status of the transfer startup.
@@ -630,7 +628,7 @@
 {
   uint32_t tickstart = 0U;
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -638,7 +636,7 @@
     /* Init tickstart for timeout management*/
     tickstart = HAL_GetTick();
 
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -646,7 +644,7 @@
     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
     hi2c->Mode      = HAL_I2C_MODE_MASTER;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-    
+
     /* Prepare transfer parameters */
     hi2c->pBuffPtr  = pData;
     hi2c->XferCount = Size;
@@ -654,7 +652,7 @@
 
     /* Send Slave Address */
     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
@@ -665,12 +663,12 @@
       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
     }
 
-    while(hi2c->XferCount > 0U)
+    while (hi2c->XferCount > 0U)
     {
       /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
           return HAL_ERROR;
         }
@@ -684,15 +682,15 @@
       hi2c->XferCount--;
       hi2c->XferSize--;
 
-      if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
+      if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
       {
         /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
 
-        if(hi2c->XferCount > MAX_NBYTE_SIZE)
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
         {
           hi2c->XferSize = MAX_NBYTE_SIZE;
           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -707,9 +705,9 @@
 
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
     /* Wait until STOPF flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         return HAL_ERROR;
       }
@@ -754,15 +752,15 @@
 {
   uint32_t tickstart = 0U;
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {    
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
     /* Process Locked */
     __HAL_LOCK(hi2c);
 
     /* Init tickstart for timeout management*/
     tickstart = HAL_GetTick();
 
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -778,7 +776,7 @@
 
     /* Send Slave Address */
     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
@@ -789,12 +787,12 @@
       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
     }
 
-    while(hi2c->XferCount > 0U)
+    while (hi2c->XferCount > 0U)
     {
       /* Wait until RXNE flag is set */
-      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
           return HAL_ERROR;
         }
@@ -809,15 +807,15 @@
       hi2c->XferSize--;
       hi2c->XferCount--;
 
-      if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+      if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
       {
         /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
 
-        if(hi2c->XferCount > MAX_NBYTE_SIZE)
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
         {
           hi2c->XferSize = MAX_NBYTE_SIZE;
           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -832,9 +830,9 @@
 
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
     /* Wait until STOPF flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         return HAL_ERROR;
       }
@@ -843,7 +841,7 @@
         return HAL_TIMEOUT;
       }
     }
-    
+
     /* Clear STOP Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 
@@ -865,7 +863,7 @@
 }
 
 /**
-  * @brief  Transmits in slave mode an amount of data in blocking mode. 
+  * @brief  Transmits in slave mode an amount of data in blocking mode.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @param  pData Pointer to data buffer
@@ -877,15 +875,15 @@
 {
   uint32_t tickstart = 0U;
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
     /* Init tickstart for timeout management*/
     tickstart = HAL_GetTick();
 
@@ -902,7 +900,7 @@
     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
 
     /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -910,13 +908,13 @@
     }
 
     /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
 
     /* If 10bit addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
     {
       /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
       {
         /* Disable Address Acknowledge */
         hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -924,26 +922,26 @@
       }
 
       /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
     }
 
     /* Wait until DIR flag is set Transmitter mode */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
 
-    while(hi2c->XferCount > 0U)
+    while (hi2c->XferCount > 0U)
     {
       /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
         /* Disable Address Acknowledge */
         hi2c->Instance->CR2 |= I2C_CR2_NACK;
 
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
           return HAL_ERROR;
         }
@@ -959,16 +957,16 @@
     }
 
     /* Wait until STOP flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
 
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
-	/* Normal use case for Transmitter mode */
-	/* A NACK is generated to confirm the end of transfer */
-	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+        /* Normal use case for Transmitter mode */
+        /* A NACK is generated to confirm the end of transfer */
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
       }
       else
       {
@@ -977,10 +975,10 @@
     }
 
     /* Clear STOP flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
-
-    /* Wait until BUSY flag is reset */ 
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -1017,9 +1015,9 @@
 {
   uint32_t tickstart = 0U;
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {  
-    if((pData == NULL) || (Size == 0U))
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
@@ -1042,7 +1040,7 @@
     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
 
     /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -1050,33 +1048,33 @@
     }
 
     /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
 
     /* Wait until DIR flag is reset Receiver mode */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
 
-    while(hi2c->XferCount > 0U)
+    while (hi2c->XferCount > 0U)
     {
       /* Wait until RXNE flag is set */
-      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
         /* Disable Address Acknowledge */
         hi2c->Instance->CR2 |= I2C_CR2_NACK;
 
         /* Store Last receive data if any */
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
         {
           /* Read data from RXDR */
           (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
           hi2c->XferCount--;
         }
 
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
         {
           return HAL_TIMEOUT;
         }
@@ -1092,12 +1090,12 @@
     }
 
     /* Wait until STOP flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
 
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         return HAL_ERROR;
       }
@@ -1108,10 +1106,10 @@
     }
 
     /* Clear STOP flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -1149,9 +1147,9 @@
 {
   uint32_t xfermode = 0U;
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
@@ -1168,8 +1166,8 @@
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->XferISR     = I2C_Master_ISR_IT;
-    
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       xfermode = I2C_RELOAD_MODE;
@@ -1185,7 +1183,7 @@
     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
 
     /* Process Unlocked */
-    __HAL_UNLOCK(hi2c); 
+    __HAL_UNLOCK(hi2c);
 
     /* Note : The I2C interrupts must be enabled after unlocking current process
               to avoid the risk of I2C interrupt handle execution before current
@@ -1218,9 +1216,9 @@
 {
   uint32_t xfermode = 0U;
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
@@ -1237,8 +1235,8 @@
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->XferISR     = I2C_Master_ISR_IT;
-    
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       xfermode = I2C_RELOAD_MODE;
@@ -1252,7 +1250,7 @@
     /* Send Slave Address */
     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
@@ -1283,7 +1281,7 @@
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -1323,7 +1321,7 @@
 }
 
 /**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt 
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @param  pData Pointer to data buffer
@@ -1332,7 +1330,7 @@
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -1385,9 +1383,9 @@
 {
   uint32_t xfermode = 0U;
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
@@ -1404,8 +1402,8 @@
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->XferISR     = I2C_Master_ISR_DMA;
-    
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       xfermode = I2C_RELOAD_MODE;
@@ -1416,7 +1414,7 @@
       xfermode = I2C_AUTOEND_MODE;
     }
 
-    if(hi2c->XferSize > 0U)
+    if (hi2c->XferSize > 0U)
     {
       /* Set the I2C DMA transfer complete callback */
       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
@@ -1454,7 +1452,7 @@
     {
       /* Update Transfer ISR function pointer */
       hi2c->XferISR = I2C_Master_ISR_IT;
-      
+
       /* Send Slave Address */
       /* Set NBYTES to write and generate START condition */
       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
@@ -1493,9 +1491,9 @@
 {
   uint32_t xfermode = 0U;
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
@@ -1512,8 +1510,8 @@
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->XferISR     = I2C_Master_ISR_DMA;
-    
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       xfermode = I2C_RELOAD_MODE;
@@ -1524,7 +1522,7 @@
       xfermode = I2C_AUTOEND_MODE;
     }
 
-    if(hi2c->XferSize > 0U)
+    if (hi2c->XferSize > 0U)
     {
       /* Set the I2C DMA transfer complete callback */
       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
@@ -1541,7 +1539,7 @@
 
       /* Send Slave Address */
       /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
 
       /* Update XferCount value */
       hi2c->XferCount -= hi2c->XferSize;
@@ -1562,7 +1560,7 @@
     {
       /* Update Transfer ISR function pointer */
       hi2c->XferISR = I2C_Master_ISR_IT;
-      
+
       /* Send Slave Address */
       /* Set NBYTES to read and generate START condition */
       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
@@ -1596,12 +1594,12 @@
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
-    }   
+    }
     /* Process Locked */
     __HAL_LOCK(hi2c);
 
@@ -1642,7 +1640,7 @@
     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
 
     /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
 
     return HAL_OK;
   }
@@ -1662,12 +1660,12 @@
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
-    }   
+    }
     /* Process Locked */
     __HAL_LOCK(hi2c);
 
@@ -1737,9 +1735,9 @@
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
@@ -1750,7 +1748,7 @@
     /* Init tickstart for timeout management*/
     tickstart = HAL_GetTick();
 
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -1765,9 +1763,9 @@
     hi2c->XferISR   = NULL;
 
     /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
@@ -1782,7 +1780,7 @@
     }
 
     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -1796,9 +1794,9 @@
     do
     {
       /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
           return HAL_ERROR;
         }
@@ -1813,15 +1811,15 @@
       hi2c->XferCount--;
       hi2c->XferSize--;
 
-      if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
+      if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
       {
         /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
 
-        if(hi2c->XferCount > MAX_NBYTE_SIZE)
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
         {
           hi2c->XferSize = MAX_NBYTE_SIZE;
           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -1833,13 +1831,14 @@
         }
       }
 
-    }while(hi2c->XferCount > 0U);
+    }
+    while (hi2c->XferCount > 0U);
 
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */ 
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         return HAL_ERROR;
       }
@@ -1889,9 +1888,9 @@
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
@@ -1902,7 +1901,7 @@
     /* Init tickstart for timeout management*/
     tickstart = HAL_GetTick();
 
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -1917,9 +1916,9 @@
     hi2c->XferISR   = NULL;
 
     /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
@@ -1935,7 +1934,7 @@
 
     /* Send Slave Address */
     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
@@ -1949,7 +1948,7 @@
     do
     {
       /* Wait until RXNE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
       {
         return HAL_TIMEOUT;
       }
@@ -1959,15 +1958,15 @@
       hi2c->XferSize--;
       hi2c->XferCount--;
 
-      if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+      if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
       {
         /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
 
-        if(hi2c->XferCount > MAX_NBYTE_SIZE)
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
         {
           hi2c->XferSize = MAX_NBYTE_SIZE;
           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -1978,13 +1977,14 @@
           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
         }
       }
-    }while(hi2c->XferCount > 0U);
+    }
+    while (hi2c->XferCount > 0U);
 
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */ 
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         return HAL_ERROR;
       }
@@ -2033,14 +2033,14 @@
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
-    
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
@@ -2060,8 +2060,8 @@
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->XferISR     = I2C_Master_ISR_IT;
-    
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       xfermode = I2C_RELOAD_MODE;
@@ -2073,9 +2073,9 @@
     }
 
     /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
@@ -2090,12 +2090,12 @@
     }
 
     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
 
     /* Process Unlocked */
-    __HAL_UNLOCK(hi2c); 
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process 
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
               to avoid the risk of I2C interrupt handle execution before current
               process unlock */
 
@@ -2132,14 +2132,14 @@
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
-    
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
@@ -2159,8 +2159,8 @@
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->XferISR     = I2C_Master_ISR_IT;
-    
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       xfermode = I2C_RELOAD_MODE;
@@ -2172,9 +2172,9 @@
     }
 
     /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
@@ -2189,7 +2189,7 @@
     }
 
     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -2230,14 +2230,14 @@
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
 
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
@@ -2257,8 +2257,8 @@
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->XferISR     = I2C_Master_ISR_DMA;
-    
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       xfermode = I2C_RELOAD_MODE;
@@ -2270,9 +2270,9 @@
     }
 
     /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
@@ -2346,14 +2346,14 @@
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
 
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
@@ -2374,7 +2374,7 @@
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->XferISR     = I2C_Master_ISR_DMA;
 
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       xfermode = I2C_RELOAD_MODE;
@@ -2386,9 +2386,9 @@
     }
 
     /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
@@ -2416,7 +2416,7 @@
     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
 
     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
 
     /* Update XferCount value */
     hi2c->XferCount -= hi2c->XferSize;
@@ -2458,9 +2458,9 @@
 
   __IO uint32_t I2C_Trials = 0U;
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
     }
@@ -2474,16 +2474,16 @@
     do
     {
       /* Generate Start */
-      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
+      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
 
       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
       /* Wait until STOPF flag is set or a NACK flag is set*/
       tickstart = HAL_GetTick();
-      while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
+      while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
       {
-      	if(Timeout != HAL_MAX_DELAY)
-      	{
-          if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
           {
             /* Device is ready */
             hi2c->State = HAL_I2C_STATE_READY;
@@ -2491,14 +2491,14 @@
             __HAL_UNLOCK(hi2c);
             return HAL_TIMEOUT;
           }
-        } 
+        }
       }
 
       /* Check if the NACKF flag has not been set */
       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
       {
-        /* Wait until STOPF flag is reset */ 
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -2517,7 +2517,7 @@
       else
       {
         /* Wait until STOPF flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -2535,8 +2535,8 @@
         /* Generate Stop */
         hi2c->Instance->CR2 |= I2C_CR2_STOP;
 
-        /* Wait until STOPF flag is reset */ 
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -2544,7 +2544,8 @@
         /* Clear STOP Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
       }
-    }while(I2C_Trials < Trials);
+    }
+    while (I2C_Trials < Trials);
 
     hi2c->State = HAL_I2C_STATE_READY;
 
@@ -2579,7 +2580,7 @@
   /* Check the parameters */
   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -2595,7 +2596,7 @@
     hi2c->XferISR     = I2C_Master_ISR_IT;
 
     /* If size > MAX_NBYTE_SIZE, use reload mode */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       xfermode = I2C_RELOAD_MODE;
@@ -2645,7 +2646,7 @@
   /* Check the parameters */
   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -2661,7 +2662,7 @@
     hi2c->XferISR     = I2C_Master_ISR_IT;
 
     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
       xfermode = I2C_RELOAD_MODE;
@@ -2673,7 +2674,7 @@
     }
 
     /* Send Slave Address and set NBYTES to read */
-    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
+    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -2706,9 +2707,9 @@
   /* Check the parameters */
   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
-  if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+  if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
@@ -2718,10 +2719,10 @@
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
     /* and then toggle the HAL slave RX state to TX state */
-    if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
     {
       /* Disable associated Interrupts */
       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
@@ -2741,11 +2742,11 @@
     hi2c->XferOptions = XferOptions;
     hi2c->XferISR     = I2C_Slave_ISR_IT;
 
-    if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
     {
       /* Clear ADDR flag after prepare the transfer parameters */
       /* This action will generate an acknowledge to the Master */
-      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
     }
 
     /* Process Unlocked */
@@ -2780,9 +2781,9 @@
   /* Check the parameters */
   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
-  if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+  if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
@@ -2792,15 +2793,15 @@
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
     /* and then toggle the HAL slave TX state to RX state */
-    if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
     {
       /* Disable associated Interrupts */
       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
     }
-    
+
     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2815,11 +2816,11 @@
     hi2c->XferOptions = XferOptions;
     hi2c->XferISR     = I2C_Slave_ISR_IT;
 
-    if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
     {
       /* Clear ADDR flag after prepare the transfer parameters */
       /* This action will generate an acknowledge to the Master */
-      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
     }
 
     /* Process Unlocked */
@@ -2847,7 +2848,7 @@
   */
 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     hi2c->State = HAL_I2C_STATE_LISTEN;
     hi2c->XferISR = I2C_Slave_ISR_IT;
@@ -2875,7 +2876,7 @@
   uint32_t tmp;
 
   /* Disable Address listen mode only if a transfer is not ongoing */
-  if(hi2c->State == HAL_I2C_STATE_LISTEN)
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)
   {
     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
@@ -2904,7 +2905,7 @@
   */
 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
 {
-  if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+  if (hi2c->Mode == HAL_I2C_MODE_MASTER)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -2923,7 +2924,7 @@
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
-    /* Note : The I2C interrupts must be enabled after unlocking current process 
+    /* Note : The I2C interrupts must be enabled after unlocking current process
               to avoid the risk of I2C interrupt handle execution before current
               process unlock */
     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
@@ -2944,7 +2945,7 @@
 
 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
  * @{
- */   
+ */
 
 /**
   * @brief  This function handles I2C event interrupt request.
@@ -2959,7 +2960,7 @@
   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
 
   /* I2C events treatment -------------------------------------*/
-  if(hi2c->XferISR != NULL)
+  if (hi2c->XferISR != NULL)
   {
     hi2c->XferISR(hi2c, itflags, itsources);
   }
@@ -2977,7 +2978,7 @@
   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
 
   /* I2C Bus error interrupt occurred ------------------------------------*/
-  if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+  if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
   {
     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
 
@@ -2986,7 +2987,7 @@
   }
 
   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
-  if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+  if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
   {
     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
 
@@ -2995,7 +2996,7 @@
   }
 
   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
-  if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+  if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
   {
     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
 
@@ -3004,7 +3005,7 @@
   }
 
   /* Call the Error Callback in case of Error detected */
-  if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
+  if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
   {
     I2C_ITError(hi2c, hi2c->ErrorCode);
   }
@@ -3077,8 +3078,8 @@
   * @brief  Slave Address Match callback.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
-  * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
-  * @param  AddrMatchCode: Address Match Code
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  AddrMatchCode Address Match Code
   * @retval None
   */
 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
@@ -3228,7 +3229,7 @@
 
 /**
   * @}
-  */  
+  */
 
 /**
   * @}
@@ -3246,14 +3247,14 @@
   * @param  ITSources Interrupt sources enabled.
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
 {
   uint16_t devaddress = 0U;
 
   /* Process Locked */
   __HAL_LOCK(hi2c);
 
-  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+  if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
   {
     /* Clear NACK Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3266,27 +3267,27 @@
     /* Flush TX register */
     I2C_Flush_TXDR(hi2c);
   }
-  else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+  else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
   {
     /* Read data from RXDR */
     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
     hi2c->XferSize--;
     hi2c->XferCount--;
   }
-  else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+  else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
   {
     /* Write data to TXDR */
     hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
     hi2c->XferSize--;
-    hi2c->XferCount--;	
+    hi2c->XferCount--;
   }
-  else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+  else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
   {
-    if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+    if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
     {
       devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-      
-      if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
       {
         hi2c->XferSize = MAX_NBYTE_SIZE;
         I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -3294,7 +3295,7 @@
       else
       {
         hi2c->XferSize = hi2c->XferCount;
-        if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
         {
           I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
         }
@@ -3307,7 +3308,7 @@
     else
     {
       /* Call TxCpltCallback() if no stop mode is set */
-      if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
       {
         /* Call I2C Master Sequential complete process */
         I2C_ITMasterSequentialCplt(hi2c);
@@ -3320,14 +3321,14 @@
       }
     }
   }
-  else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+  else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
   {
-    if(hi2c->XferCount == 0U)
+    if (hi2c->XferCount == 0U)
     {
-      if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
       {
         /* Generate a stop condition in case of no transfer option */
-        if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
         {
           /* Generate Stop */
           hi2c->Instance->CR2 |= I2C_CR2_STOP;
@@ -3347,7 +3348,7 @@
     }
   }
 
-  if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+  if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
   {
     /* Call I2C Master complete process */
     I2C_ITMasterCplt(hi2c, ITFlags);
@@ -3367,26 +3368,26 @@
   * @param  ITSources Interrupt sources enabled.
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
 {
   /* Process locked */
   __HAL_LOCK(hi2c);
-  
-  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+
+  if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
   {
     /* Check that I2C transfer finished */
     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
     /* Mean XferCount == 0*/
     /* So clear Flag NACKF only */
-    if(hi2c->XferCount == 0U)
+    if (hi2c->XferCount == 0U)
     {
-      if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
-        (hi2c->State == HAL_I2C_STATE_LISTEN))
+      if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
+          (hi2c->State == HAL_I2C_STATE_LISTEN))
       {
         /* Call I2C Listen complete process */
         I2C_ITListenCplt(hi2c, ITFlags);
       }
-      else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
+      else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
       {
         /* Clear NACK Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3414,9 +3415,9 @@
       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
     }
   }
-  else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+  else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
   {
-    if(hi2c->XferCount > 0U)
+    if (hi2c->XferCount > 0U)
     {
       /* Read data from RXDR */
       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
@@ -3424,24 +3425,24 @@
       hi2c->XferCount--;
     }
 
-    if((hi2c->XferCount == 0U) && \
-       (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
+    if ((hi2c->XferCount == 0U) && \
+        (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
     {
       /* Call I2C Slave Sequential complete process */
       I2C_ITSlaveSequentialCplt(hi2c);
-   }
+    }
   }
-  else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+  else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
   {
     I2C_ITAddrCplt(hi2c, ITFlags);
   }
-  else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+  else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
   {
     /* Write data to TXDR only if XferCount not reach "0" */
     /* A TXIS flag can be set, during STOP treatment      */
     /* Check if all Datas have already been sent */
     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
-    if(hi2c->XferCount > 0U)
+    if (hi2c->XferCount > 0U)
     {
       /* Write data to TXDR */
       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
@@ -3450,7 +3451,7 @@
     }
     else
     {
-      if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
+      if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
       {
         /* Last Byte is Transmitted */
         /* Call I2C Slave Sequential complete process */
@@ -3460,7 +3461,7 @@
   }
 
   /* Check if STOPF is set */
-  if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+  if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
   {
     /* Call I2C Slave complete process */
     I2C_ITSlaveCplt(hi2c, ITFlags);
@@ -3480,7 +3481,7 @@
   * @param  ITSources Interrupt sources enabled.
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
 {
   uint16_t devaddress = 0U;
   uint32_t xfermode = 0U;
@@ -3488,14 +3489,14 @@
   /* Process Locked */
   __HAL_LOCK(hi2c);
 
-  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+  if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
   {
     /* Clear NACK Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 
     /* Set corresponding Error Code */
     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-    
+
     /* No need to generate STOP, it is automatically done */
     /* But enable STOP interrupt, to treat it */
     /* Error callback will be send during stop flag treatment */
@@ -3504,18 +3505,18 @@
     /* Flush TX register */
     I2C_Flush_TXDR(hi2c);
   }
-  else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+  else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
   {
     /* Disable TC interrupt */
     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
-    
-    if(hi2c->XferCount != 0U)
+
+    if (hi2c->XferCount != 0U)
     {
       /* Recover Slave address */
       devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-      
+
       /* Prepare the new XferSize to transfer */
-      if(hi2c->XferCount > MAX_NBYTE_SIZE)
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
       {
         hi2c->XferSize = MAX_NBYTE_SIZE;
         xfermode = I2C_RELOAD_MODE;
@@ -3533,7 +3534,7 @@
       hi2c->XferCount -= hi2c->XferSize;
 
       /* Enable DMA Request */
-      if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
       {
         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
       }
@@ -3549,7 +3550,7 @@
       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
     }
   }
-  else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+  else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
   {
     /* Call I2C Master complete process */
     I2C_ITMasterCplt(hi2c, ITFlags);
@@ -3569,18 +3570,18 @@
   * @param  ITSources Interrupt sources enabled.
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
 {
   /* Process locked */
   __HAL_LOCK(hi2c);
-  
-  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+
+  if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
   {
     /* Check that I2C transfer finished */
     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
     /* Mean XferCount == 0 */
     /* So clear Flag NACKF only */
-    if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
+    if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
     {
       /* Clear NACK Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3590,17 +3591,17 @@
       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
       /* Clear NACK Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-      
+
       /* Set ErrorCode corresponding to a Non-Acknowledge */
       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
     }
   }
-  else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+  else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
   {
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
   }
-  else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+  else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
   {
     /* Call I2C Slave complete process */
     I2C_ITSlaveCplt(hi2c, ITFlags);
@@ -3626,12 +3627,12 @@
   */
 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
 {
-  I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+  I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
 
   /* Wait until TXIS flag is set */
-  if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
   {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     {
       return HAL_ERROR;
     }
@@ -3642,7 +3643,7 @@
   }
 
   /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
   {
     /* Send Memory Address */
     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
@@ -3654,9 +3655,9 @@
     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
 
     /* Wait until TXIS flag is set */
-    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         return HAL_ERROR;
       }
@@ -3665,18 +3666,18 @@
         return HAL_TIMEOUT;
       }
     }
-    
+
     /* Send LSB of Memory Address */
     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
   }
 
   /* Wait until TCR flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
 
-return HAL_OK;
+  return HAL_OK;
 }
 
 /**
@@ -3693,12 +3694,12 @@
   */
 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
 {
-  I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+  I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
 
   /* Wait until TXIS flag is set */
-  if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
   {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     {
       return HAL_ERROR;
     }
@@ -3709,7 +3710,7 @@
   }
 
   /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
   {
     /* Send Memory Address */
     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
@@ -3721,9 +3722,9 @@
     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
 
     /* Wait until TXIS flag is set */
-    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
         return HAL_ERROR;
       }
@@ -3732,17 +3733,17 @@
         return HAL_TIMEOUT;
       }
     }
-    
+
     /* Send LSB of Memory Address */
     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
   }
 
   /* Wait until TC flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
-  
+
   return HAL_OK;
 }
 
@@ -3763,7 +3764,7 @@
   UNUSED(ITFlags);
 
   /* In case of Listen state, need to inform upper layer of address match code event */
-  if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+  if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
   {
     transferdirection = I2C_GET_DIR(hi2c);
     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
@@ -3771,19 +3772,19 @@
     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
 
     /* If 10bits addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
     {
-      if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+      if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
       {
         slaveaddrcode = ownadd1code;
         hi2c->AddrEventCount++;
-        if(hi2c->AddrEventCount == 2U)
+        if (hi2c->AddrEventCount == 2U)
         {
           /* Reset Address Event counter */
           hi2c->AddrEventCount = 0U;
 
           /* Clear ADDR flag */
-          __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
 
           /* Process Unlocked */
           __HAL_UNLOCK(hi2c);
@@ -3885,7 +3886,7 @@
   /* Reset I2C handle mode */
   hi2c->Mode = HAL_I2C_MODE_NONE;
 
-  if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
   {
     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
     hi2c->State         = HAL_I2C_STATE_LISTEN;
@@ -3901,7 +3902,7 @@
     HAL_I2C_SlaveTxCpltCallback(hi2c);
   }
 
-  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
   {
     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
     hi2c->State         = HAL_I2C_STATE_LISTEN;
@@ -3937,7 +3938,7 @@
   hi2c->XferISR       = NULL;
   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
 
-  if((ITFlags & I2C_FLAG_AF) != RESET)
+  if ((ITFlags & I2C_FLAG_AF) != RESET)
   {
     /* Clear NACK Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3950,16 +3951,16 @@
   I2C_Flush_TXDR(hi2c);
 
   /* Disable Interrupts */
-  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
+  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
 
   /* Call the corresponding callback to inform upper layer of End of Transfer */
-  if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
+  if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
   {
     /* Call the corresponding callback to inform upper layer of End of Transfer */
     I2C_ITError(hi2c, hi2c->ErrorCode);
   }
   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
-  else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
   {
     hi2c->State = HAL_I2C_STATE_READY;
 
@@ -3985,7 +3986,7 @@
     }
   }
   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
-  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
   {
     hi2c->State = HAL_I2C_STATE_READY;
 
@@ -4022,7 +4023,7 @@
   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 
   /* Clear ADDR flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
 
   /* Disable all interrupts */
   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
@@ -4037,26 +4038,26 @@
   I2C_Flush_TXDR(hi2c);
 
   /* If a DMA is ongoing, Update handle size context */
-  if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
-     ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
+  if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
+      ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
   {
     hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
   }
 
   /* All data are not transferred, so set error code accordingly */
-  if(hi2c->XferCount != 0U)
+  if (hi2c->XferCount != 0U)
   {
     /* Set ErrorCode corresponding to a Non-Acknowledge */
     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
   }
 
   /* Store Last receive data if any */
-  if(((ITFlags & I2C_FLAG_RXNE) != RESET))
+  if (((ITFlags & I2C_FLAG_RXNE) != RESET))
   {
     /* Read data from RXDR */
     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
 
-    if((hi2c->XferSize > 0U))
+    if ((hi2c->XferSize > 0U))
     {
       hi2c->XferSize--;
       hi2c->XferCount--;
@@ -4070,19 +4071,19 @@
   hi2c->Mode = HAL_I2C_MODE_NONE;
   hi2c->XferISR = NULL;
 
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
   {
     /* Call the corresponding callback to inform upper layer of End of Transfer */
     I2C_ITError(hi2c, hi2c->ErrorCode);
 
     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-    if(hi2c->State == HAL_I2C_STATE_LISTEN)
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
     {
       /* Call I2C Listen complete process */
       I2C_ITListenCplt(hi2c, ITFlags);
     }
   }
-  else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
   {
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->State = HAL_I2C_STATE_READY;
@@ -4094,7 +4095,7 @@
     HAL_I2C_ListenCpltCallback(hi2c);
   }
   /* Call the corresponding callback to inform upper layer of End of Transfer */
-  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
   {
     hi2c->State = HAL_I2C_STATE_READY;
 
@@ -4132,12 +4133,12 @@
   hi2c->XferISR = NULL;
 
   /* Store Last receive data if any */
-  if(((ITFlags & I2C_FLAG_RXNE) != RESET))
+  if (((ITFlags & I2C_FLAG_RXNE) != RESET))
   {
     /* Read data from RXDR */
     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
 
-    if((hi2c->XferSize > 0U))
+    if ((hi2c->XferSize > 0U))
     {
       hi2c->XferSize--;
       hi2c->XferCount--;
@@ -4177,9 +4178,9 @@
   hi2c->ErrorCode |= ErrorCode;
 
   /* Disable Interrupts */
-  if((hi2c->State == HAL_I2C_STATE_LISTEN)         ||
-     (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
-     (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  if ((hi2c->State == HAL_I2C_STATE_LISTEN)         ||
+      (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+      (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
   {
     /* Disable all interrupts, except interrupts related to LISTEN state */
     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
@@ -4193,10 +4194,10 @@
   {
     /* Disable all interrupts */
     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-    
+
     /* If state is an abort treatment on goind, don't change state */
     /* This change will be do later */
-    if(hi2c->State != HAL_I2C_STATE_ABORT)
+    if (hi2c->State != HAL_I2C_STATE_ABORT)
     {
       /* Set HAL_I2C_STATE_READY */
       hi2c->State         = HAL_I2C_STATE_READY;
@@ -4206,7 +4207,7 @@
   }
 
   /* Abort DMA TX transfer if any */
-  if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+  if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
   {
     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
 
@@ -4218,14 +4219,14 @@
     __HAL_UNLOCK(hi2c);
 
     /* Abort DMA TX */
-    if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+    if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
     {
       /* Call Directly XferAbortCallback function in case of error */
       hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
     }
   }
   /* Abort DMA RX transfer if any */
-  else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+  else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
   {
     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
 
@@ -4237,16 +4238,16 @@
     __HAL_UNLOCK(hi2c);
 
     /* Abort DMA RX */
-    if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+    if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
     {
       /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
       hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
     }
   }
-  else if(hi2c->State == HAL_I2C_STATE_ABORT)
+  else if (hi2c->State == HAL_I2C_STATE_ABORT)
   {
     hi2c->State = HAL_I2C_STATE_READY;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
@@ -4272,13 +4273,13 @@
 {
   /* If a pending TXIS flag is set */
   /* Write a dummy data in TXDR to clear it */
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
   {
-     hi2c->Instance->TXDR = 0x00U;
+    hi2c->Instance->TXDR = 0x00U;
   }
 
   /* Flush TX register if not empty */
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
   {
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
   }
@@ -4291,13 +4292,13 @@
   */
 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Disable DMA Request */
   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
 
   /* If last transfer, enable STOP interrupt */
-  if(hi2c->XferCount == 0U)
+  if (hi2c->XferCount == 0U)
   {
     /* Enable STOP interrupt */
     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
@@ -4309,7 +4310,7 @@
     hi2c->pBuffPtr += hi2c->XferSize;
 
     /* Set the XferSize to transfer */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
     }
@@ -4348,13 +4349,13 @@
   */
 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Disable DMA Request */
   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
 
   /* If last transfer, enable STOP interrupt */
-  if(hi2c->XferCount == 0U)
+  if (hi2c->XferCount == 0U)
   {
     /* Enable STOP interrupt */
     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
@@ -4366,7 +4367,7 @@
     hi2c->pBuffPtr += hi2c->XferSize;
 
     /* Set the XferSize to transfer */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
     }
@@ -4405,7 +4406,7 @@
   */
 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Disable Acknowledge */
   hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -4417,12 +4418,12 @@
 /**
   * @brief DMA I2C communication abort callback
   *        (To be called at end of DMA Abort procedure).
-  * @param hdma: DMA handle.
+  * @param hdma DMA handle.
   * @retval None
   */
 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Disable Acknowledge */
   hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -4432,10 +4433,10 @@
   hi2c->hdmarx->XferAbortCallback = NULL;
 
   /* Check if come from abort from user */
-  if(hi2c->State == HAL_I2C_STATE_ABORT)
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
   {
     hi2c->State = HAL_I2C_STATE_READY;
-    
+
     /* Call the corresponding callback to inform upper layer of End of Transfer */
     HAL_I2C_AbortCpltCallback(hi2c);
   }
@@ -4458,14 +4459,14 @@
   */
 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
 {
-  while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
   {
     /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
       {
-        hi2c->State= HAL_I2C_STATE_READY;
+        hi2c->State = HAL_I2C_STATE_READY;
         hi2c->Mode = HAL_I2C_MODE_NONE;
 
         /* Process Unlocked */
@@ -4487,21 +4488,21 @@
   */
 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
   {
     /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
     {
       return HAL_ERROR;
     }
 
     /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
       {
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        hi2c->State= HAL_I2C_STATE_READY;
+        hi2c->State = HAL_I2C_STATE_READY;
         hi2c->Mode = HAL_I2C_MODE_NONE;
 
         /* Process Unlocked */
@@ -4524,19 +4525,19 @@
   */
 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
   {
     /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
     {
       return HAL_ERROR;
     }
 
     /* Check for the Timeout */
-    if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+    if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
     {
       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State= HAL_I2C_STATE_READY;
+      hi2c->State = HAL_I2C_STATE_READY;
       hi2c->Mode = HAL_I2C_MODE_NONE;
 
       /* Process Unlocked */
@@ -4558,16 +4559,16 @@
   */
 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
   {
     /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
     {
       return HAL_ERROR;
     }
 
     /* Check if a STOPF is detected */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
     {
       /* Clear STOP Flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@@ -4576,7 +4577,7 @@
       I2C_RESET_CR2(hi2c);
 
       hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-      hi2c->State= HAL_I2C_STATE_READY;
+      hi2c->State = HAL_I2C_STATE_READY;
       hi2c->Mode = HAL_I2C_MODE_NONE;
 
       /* Process Unlocked */
@@ -4586,10 +4587,10 @@
     }
 
     /* Check for the Timeout */
-    if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+    if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
     {
       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State= HAL_I2C_STATE_READY;
+      hi2c->State = HAL_I2C_STATE_READY;
 
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
@@ -4610,18 +4611,18 @@
   */
 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
   {
     /* Wait until STOP Flag is reset */
     /* AutoEnd should be initiate after AF */
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
     {
       /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if (Timeout != HAL_MAX_DELAY)
       {
-      if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+        if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
         {
-          hi2c->State= HAL_I2C_STATE_READY;
+          hi2c->State = HAL_I2C_STATE_READY;
           hi2c->Mode = HAL_I2C_MODE_NONE;
 
           /* Process Unlocked */
@@ -4644,7 +4645,7 @@
     I2C_RESET_CR2(hi2c);
 
     hi2c->ErrorCode = HAL_I2C_ERROR_AF;
-    hi2c->State= HAL_I2C_STATE_READY;
+    hi2c->State = HAL_I2C_STATE_READY;
     hi2c->Mode = HAL_I2C_MODE_NONE;
 
     /* Process Unlocked */
@@ -4690,8 +4691,8 @@
   tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
 
   /* update tmpreg */
-  tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
-            (uint32_t)Mode | (uint32_t)Request);
+  tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \
+                       (uint32_t)Mode | (uint32_t)Request);
 
   /* update CR2 register */
   hi2c->Instance->CR2 = tmpreg;
@@ -4708,28 +4709,28 @@
 {
   uint32_t tmpisr = 0U;
 
-  if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
-     (hi2c->XferISR == I2C_Slave_ISR_DMA))
+  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+      (hi2c->XferISR == I2C_Slave_ISR_DMA))
   {
-    if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
     {
       /* Enable ERR, STOP, NACK and ADDR interrupts */
       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
     }
 
-    if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+    if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
     {
       /* Enable ERR and NACK interrupts */
       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
     }
 
-    if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+    if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
     {
       /* Enable STOP interrupts */
       tmpisr |= I2C_IT_STOPI;
     }
-    
-    if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+
+    if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
     {
       /* Enable TC interrupts */
       tmpisr |= I2C_IT_TCI;
@@ -4737,31 +4738,31 @@
   }
   else
   {
-    if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
     {
       /* Enable ERR, STOP, NACK, and ADDR interrupts */
       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
     }
 
-    if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
     {
       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
     }
 
-    if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
     {
       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
     }
 
-    if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+    if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
     {
       /* Enable STOP interrupts */
       tmpisr |= I2C_IT_STOPI;
     }
   }
-  
+
   /* Enable interrupts only at the end */
   /* to avoid the risk of I2C interrupt handle execution before */
   /* all interrupts requested done */
@@ -4781,49 +4782,49 @@
 {
   uint32_t tmpisr = 0U;
 
-  if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
   {
     /* Disable TC and TXI interrupts */
     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
 
-    if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+    if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
     {
       /* Disable NACK and STOP interrupts */
       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
     }
   }
 
-  if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
   {
     /* Disable TC and RXI interrupts */
     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
 
-    if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+    if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
     {
       /* Disable NACK and STOP interrupts */
       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
     }
   }
 
-  if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
   {
     /* Disable ADDR, NACK and STOP interrupts */
     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
   }
 
-  if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+  if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
   {
     /* Enable ERR and NACK interrupts */
     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
   }
 
-  if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+  if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
   {
     /* Enable STOP interrupts */
     tmpisr |= I2C_IT_STOPI;
   }
-  
-  if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+
+  if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
   {
     /* Enable TC interrupts */
     tmpisr |= I2C_IT_TCI;

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_i2c.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of I2C HAL module.
   ******************************************************************************
   * @attention
@@ -40,11 +38,11 @@
 #define __STM32F0xx_HAL_I2C_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_hal_def.h"  
+#include "stm32f0xx_hal_def.h"
 
 /** @addtogroup STM32F0xx_HAL_Driver
   * @{
@@ -52,7 +50,7 @@
 
 /** @addtogroup I2C
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup I2C_Exported_Types I2C Exported Types
@@ -60,13 +58,13 @@
   */
 
 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
-  * @brief  I2C Configuration Structure definition  
+  * @brief  I2C Configuration Structure definition
   * @{
   */
 typedef struct
 {
   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
-                                  This parameter calculated by referring to I2C initialization 
+                                  This parameter calculated by referring to I2C initialization
                                          section in Reference manual */
 
   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
@@ -90,9 +88,9 @@
   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
                                   This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
 
-}I2C_InitTypeDef;
+} I2C_InitTypeDef;
 
-/** 
+/**
   * @}
   */
 
@@ -122,7 +120,7 @@
   *             0  : Ready (no Tx operation ongoing)\n
   *             1  : Busy (Tx operation ongoing)
   * @{
-  */ 
+  */
 typedef enum
 {
   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
@@ -139,7 +137,7 @@
   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
   HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
 
-}HAL_I2C_StateTypeDef;
+} HAL_I2C_StateTypeDef;
 
 /**
   * @}
@@ -170,9 +168,9 @@
   HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
   HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
 
-}HAL_I2C_ModeTypeDef;
+} HAL_I2C_ModeTypeDef;
 
-/** 
+/**
   * @}
   */
 
@@ -213,7 +211,7 @@
 
   __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
 
-  HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */
 
   DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
 
@@ -228,7 +226,7 @@
   __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
 
   __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
-}I2C_HandleTypeDef;
+} I2C_HandleTypeDef;
 /**
   * @}
   */
@@ -313,7 +311,7 @@
 /**
   * @}
   */
-  
+
 /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
   * @{
   */
@@ -431,7 +429,7 @@
   * @retval None
   */
 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
- 
+
 /** @brief  Check whether the specified I2C interrupt source is enabled or not.
   * @param  __HANDLE__ specifies the I2C Handle.
   * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
@@ -506,7 +504,7 @@
 #define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
 
 /** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
-  * @param  __HANDLE__: specifies the I2C Handle. 
+  * @param  __HANDLE__ specifies the I2C Handle.
   * @retval None
   */
 #define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
@@ -527,7 +525,7 @@
   */
 /* Initialization and de-initialization functions******************************/
 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
 /**
@@ -538,7 +536,7 @@
   * @{
   */
 /* IO operation functions  ****************************************************/
- /******* Blocking mode: Polling */
+/******* Blocking mode: Polling */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -547,7 +545,7 @@
 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
 
- /******* Non-Blocking mode: Interrupt */
+/******* Non-Blocking mode: Interrupt */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
@@ -563,7 +561,7 @@
 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
 
- /******* Non-Blocking mode: DMA */
+/******* Non-Blocking mode: DMA */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
@@ -604,11 +602,11 @@
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup I2C_Private_Constants I2C Private Constants
@@ -617,7 +615,7 @@
 
 /**
   * @}
-  */ 
+  */
 
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup I2C_Private_Macro I2C Private Macros
@@ -681,7 +679,7 @@
                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
 /**
   * @}
-  */ 
+  */
 
 /* Private Functions ---------------------------------------------------------*/
 /** @defgroup I2C_Private_Functions I2C Private Functions
@@ -690,15 +688,15 @@
 /* Private functions are defined in stm32f0xx_hal_i2c.c file */
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,10 +2,8 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_i2c_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   I2C Extended HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of I2C Extended peripheral:
   *           + Extended features functions
   *
@@ -96,7 +94,7 @@
                       ##### Extended features functions #####
  ===============================================================================
     [..] This section provides functions allowing to:
-      (+) Configure Noise Filters 
+      (+) Configure Noise Filters
       (+) Configure Wake Up Feature
 
 @endverbatim
@@ -116,7 +114,7 @@
   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -162,7 +160,7 @@
   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -206,12 +204,12 @@
   *                the configuration information for the specified I2Cx peripheral.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
 {
   /* Check the parameters */
   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -245,12 +243,12 @@
   *                the configuration information for the specified I2Cx peripheral.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
 {
   /* Check the parameters */
   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -263,7 +261,7 @@
     /* Enable wakeup from stop mode */
     hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
 
-    __HAL_I2C_ENABLE(hi2c); 
+    __HAL_I2C_ENABLE(hi2c);
 
     hi2c->State = HAL_I2C_STATE_READY;
 

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_i2c_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of I2C HAL Extended module.
   ******************************************************************************
   * @attention
@@ -40,7 +38,7 @@
 #define __STM32F0xx_HAL_I2C_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -52,7 +50,7 @@
 
 /** @addtogroup I2CEx
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
@@ -64,7 +62,7 @@
 /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
   * @{
   */
-#define I2C_ANALOGFILTER_ENABLE         (0x00000000U)
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
 #define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
 /**
   * @}
@@ -73,7 +71,7 @@
 /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
   * @{
   */
-#define I2C_FMP_NOT_SUPPORTED           (0xAAAA0000U)                                   /*!< Fast Mode Plus not supported       */
+#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
 #if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
 #define I2C_FASTMODEPLUS_PA9            SYSCFG_CFGR1_I2C_FMP_PA9                        /*!< Enable Fast Mode Plus on PA9       */
 #define I2C_FASTMODEPLUS_PA10           SYSCFG_CFGR1_I2C_FMP_PA10                       /*!< Enable Fast Mode Plus on PA10      */
@@ -101,7 +99,7 @@
 
 /**
   * @}
-  */ 
+  */
 
 /* Exported macro ------------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
@@ -154,7 +152,7 @@
                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)))
 /**
   * @}
-  */ 
+  */
 
 /* Private Functions ---------------------------------------------------------*/
 /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_i2s.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   I2S HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -212,7 +210,7 @@
 /**
   * @brief Initializes the I2S according to the specified parameters 
   *         in the I2S_InitTypeDef and create the associated handle.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL status
   */
@@ -331,7 +329,7 @@
 
 /**
   * @brief DeInitializes the I2S peripheral 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL status
   */
@@ -365,7 +363,7 @@
 
 /**
   * @brief I2S MSP Init
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
@@ -381,7 +379,7 @@
 
 /**
   * @brief I2S MSP DeInit
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
@@ -443,15 +441,15 @@
 
 /**
   * @brief Transmit an amount of data in blocking mode
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param pData a 16-bit pointer to data buffer.
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
   *       the Size parameter means the number of 16-bit data length. 
-  * @param  Timeout: Timeout duration
+  * @param  Timeout Timeout duration
   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
   *       between Master and Slave(example: audio streaming).
   * @retval HAL status
@@ -531,15 +529,15 @@
 
 /**
   * @brief Receive an amount of data in blocking mode 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param pData a 16-bit pointer to data buffer.
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
   *       the Size parameter means the number of 16-bit data length. 
-  * @param Timeout: Timeout duration
+  * @param Timeout Timeout duration
   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
   *       between Master and Slave(example: audio streaming).
   * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
@@ -612,10 +610,10 @@
 
 /**
   * @brief Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param pData a 16-bit pointer to data buffer.
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
@@ -677,10 +675,10 @@
 
 /**
   * @brief Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param pData a 16-bit pointer to the Receive data buffer.
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
@@ -744,10 +742,10 @@
 
 /**
   * @brief Transmit an amount of data in non-blocking mode with DMA
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Transmit data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param pData a 16-bit pointer to the Transmit data buffer.
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
@@ -825,10 +823,10 @@
 
 /**
   * @brief Receive an amount of data in non-blocking mode with DMA 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param pData a 16-bit pointer to the Receive data buffer.
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
@@ -915,7 +913,7 @@
 
 /**
   * @brief Pauses the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL status
   */
@@ -943,7 +941,7 @@
 
 /**
   * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL status
   */
@@ -978,7 +976,7 @@
 
 /**
   * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL status
   */
@@ -1019,7 +1017,7 @@
 
 /**
   * @brief  This function handles I2S interrupt request.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
@@ -1073,7 +1071,7 @@
 
 /**
   * @brief Tx Transfer Half completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
@@ -1089,7 +1087,7 @@
 
 /**
   * @brief Tx Transfer completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
@@ -1105,7 +1103,7 @@
 
 /**
   * @brief Rx Transfer half completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
@@ -1121,7 +1119,7 @@
 
 /**
   * @brief Rx Transfer completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
@@ -1137,7 +1135,7 @@
 
 /**
   * @brief I2S error callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
@@ -1172,7 +1170,7 @@
 
 /**
   * @brief  Return the I2S state
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL state
   */
@@ -1183,7 +1181,7 @@
 
 /**
   * @brief  Return the I2S error code
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval I2S Error Code
   */
@@ -1204,7 +1202,7 @@
   */
 /**
   * @brief DMA I2S transmit process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1225,7 +1223,7 @@
 
 /**
   * @brief DMA I2S transmit process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1238,7 +1236,7 @@
 
 /**
   * @brief DMA I2S receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1258,7 +1256,7 @@
 
 /**
   * @brief DMA I2S receive process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1271,7 +1269,7 @@
 
 /**
   * @brief DMA I2S communication error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1293,7 +1291,7 @@
 
 /**
   * @brief Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
@@ -1315,7 +1313,7 @@
 
 /**
 * @brief Receive an amount of data in non-blocking mode with Interrupt
-* @param hi2s: I2S handle
+* @param hi2s I2S handle
   * @retval None
 */
 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
@@ -1337,11 +1335,11 @@
 
 /**
   * @brief This function handles I2S Communication Timeout.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param Flag: Flag checked
-  * @param State: Value of the flag expected
-  * @param Timeout: Duration of the timeout
+  * @param Flag Flag checked
+  * @param State Value of the flag expected
+  * @param Timeout Duration of the timeout
   * @retval HAL status
   */
 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_i2s.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of I2S HAL module.
   ******************************************************************************
   * @attention
@@ -293,21 +291,21 @@
   */
 
 /** @brief  Reset I2S handle state
-  * @param  __HANDLE__: I2S handle.
+  * @param  __HANDLE__ I2S handle.
   * @retval None
   */
 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
 
 /** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__: specifies the I2S Handle. 
+  * @param  __HANDLE__ specifies the I2S Handle. 
   * @retval None
   */
 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
 
 /** @brief  Enable or disable the specified I2S interrupts.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
   *        This parameter can be one of the following values:
   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
@@ -318,9 +316,9 @@
 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
  
 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
+  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
@@ -330,8 +328,8 @@
 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
@@ -345,7 +343,7 @@
 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   * @retval None
   */                                                                                                   
 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
@@ -355,7 +353,7 @@
                                                UNUSED(tmpreg); \
                                               }while(0)
 /** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   * @retval None
   */                                                                                                   
 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_irda.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   IRDA HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the IrDA (Infrared Data Association) Peripheral
@@ -266,7 +264,7 @@
 /**
   * @brief Initialize the IRDA mode according to the specified
   *        parameters in the IRDA_InitTypeDef and initialize the associated handle.
-  * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
   *               the configuration information for the specified IRDA module.
   * @retval HAL status
   */
@@ -319,7 +317,7 @@
 
 /**
   * @brief DeInitialize the IRDA peripheral.
-  * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
   *               the configuration information for the specified IRDA module.
   * @retval HAL status
   */
@@ -353,7 +351,7 @@
 
 /**
   * @brief Initialize the IRDA MSP.
-  * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
   *               the configuration information for the specified IRDA module.
   * @retval None
   */
@@ -369,7 +367,7 @@
 
 /**
   * @brief DeInitialize the IRDA MSP.
-  * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
   *               the configuration information for the specified IRDA module.
   * @retval None
   */
@@ -1653,7 +1651,7 @@
 
 /**
   * @brief  Rx Half Transfer complete callback.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
@@ -2025,7 +2023,7 @@
 
 /**
   * @brief  DMA IRDA receive process complete callback.
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA module.
   * @retval None
   */
@@ -2055,7 +2053,7 @@
 
 /**
   * @brief DMA IRDA receive process half complete callback.
-  * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
   *              the configuration information for the specified DMA module.
   * @retval None
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_irda.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   This file contains all the functions prototypes for the IRDA 
   *          firmware library.
   ******************************************************************************
@@ -361,22 +359,10 @@
 #define IRDA_IT_TC                          ((uint16_t)0x0626U)     /*!< IRDA Transmission complete interruption        */
 #define IRDA_IT_RXNE                        ((uint16_t)0x0525U)     /*!< IRDA Read data register not empty interruption */
 #define IRDA_IT_IDLE                        ((uint16_t)0x0424U)     /*!< IRDA Idle interruption                         */
-
-/**       Elements values convention: 000000000XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)
-  *           - XX  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  */
-#define IRDA_IT_ERR                         ((uint16_t)0x0060U)       /*!< IRDA Error interruption        */
-
-/**       Elements values convention: 0000ZZZZ00000000b
-  *           - ZZZZ  : Flag position in the ISR register(4bits)
-  */
-#define IRDA_IT_ORE                         ((uint16_t)0x0300U)      /*!< IRDA Overrun error interruption */
-#define IRDA_IT_NE                          ((uint16_t)0x0200U)      /*!< IRDA Noise error interruption   */
-#define IRDA_IT_FE                          ((uint16_t)0x0100U)      /*!< IRDA Frame error interruption   */
+#define IRDA_IT_ERR                         ((uint16_t)0x0060U)     /*!< IRDA Error interruption                        */
+#define IRDA_IT_ORE                         ((uint16_t)0x0300U)     /*!< IRDA Overrun error interruption                */
+#define IRDA_IT_NE                          ((uint16_t)0x0200U)     /*!< IRDA Noise error interruption                  */
+#define IRDA_IT_FE                          ((uint16_t)0x0100U)     /*!< IRDA Frame error interruption                  */
 /**
   * @}
   */
@@ -413,7 +399,7 @@
   */
 
 /** @brief  Reset IRDA handle state.
-  * @param  __HANDLE__: IRDA handle.
+  * @param  __HANDLE__ IRDA handle.
   * @retval None
   */
 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
@@ -422,7 +408,7 @@
                                                      } while(0)
 
 /** @brief  Flush the IRDA DR register.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
@@ -432,8 +418,8 @@
       } while(0)
 
 /** @brief  Clear the specified IRDA pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg @ref IRDA_CLEAR_PEF
   *            @arg @ref IRDA_CLEAR_FEF
@@ -446,39 +432,39 @@
 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
 
 /** @brief  Clear the IRDA PE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
 
 
 /** @brief  Clear the IRDA FE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
 
 /** @brief  Clear the IRDA NE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
 
 /** @brief  Clear the IRDA ORE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
 
 /** @brief  Clear the IRDA IDLE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
 
 /** @brief  Check whether the specified IRDA flag is set or not.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
   *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
@@ -498,8 +484,8 @@
 
 
 /** @brief  Enable the specified IRDA interrupt.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
@@ -514,8 +500,8 @@
                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
 
 /** @brief  Disable the specified IRDA interrupt.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
@@ -531,8 +517,8 @@
 
 
 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  * @param  __IT__: specifies the IRDA interrupt source to check.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __IT__ specifies the IRDA interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
@@ -547,8 +533,8 @@
 #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
 
 /** @brief  Check whether the specified IRDA interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  * @param  __IT__: specifies the IRDA interrupt source to check.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __IT__ specifies the IRDA interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
@@ -563,8 +549,8 @@
 
 
 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
   *                       to clear the corresponding interrupt
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
@@ -578,8 +564,8 @@
 
 
 /** @brief  Set a specific IRDA request flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  * @param  __REQ__: specifies the request flag to set
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __REQ__ specifies the request flag to set
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
   *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
@@ -590,25 +576,25 @@
 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
 
 /** @brief  Enable the IRDA one bit sample method.
-  * @param  __HANDLE__: specifies the IRDA Handle.  
+  * @param  __HANDLE__ specifies the IRDA Handle.  
   * @retval None
   */
 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
 /** @brief  Disable the IRDA one bit sample method.
-  * @param  __HANDLE__: specifies the IRDA Handle.  
+  * @param  __HANDLE__ specifies the IRDA Handle.  
   * @retval None
   */
 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable UART/USART associated to IRDA Handle.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable UART/USART associated to IRDA Handle.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
@@ -623,20 +609,20 @@
   */
 
 /** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
-  * @param  __BAUDRATE__: specifies the IRDA Baudrate set by the user.
+  * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.
   * @retval True or False
   */
 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
 
 /** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
-  * @param  __PRESCALER__: specifies the IRDA prescaler value set by the user.
+  * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.
   * @retval True or False
   */
 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
 
 /**
   * @brief Ensure that IRDA frame parity is valid.
-  * @param __PARITY__: IRDA frame parity. 
+  * @param __PARITY__ IRDA frame parity. 
   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
   */ 
 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
@@ -645,14 +631,14 @@
 
 /**
   * @brief Ensure that IRDA communication mode is valid.
-  * @param __MODE__: IRDA communication mode. 
+  * @param __MODE__ IRDA communication mode. 
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */ 
 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
 
 /**
   * @brief Ensure that IRDA power mode is valid.
-  * @param __MODE__: IRDA power mode. 
+  * @param __MODE__ IRDA power mode. 
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */ 
 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
@@ -660,7 +646,7 @@
 
 /**
   * @brief Ensure that IRDA state is valid.
-  * @param __STATE__: IRDA state mode. 
+  * @param __STATE__ IRDA state mode. 
   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
   */ 
 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
@@ -668,7 +654,7 @@
 
 /**
   * @brief Ensure that IRDA associated UART/USART mode is valid.
-  * @param __MODE__: IRDA associated UART/USART mode. 
+  * @param __MODE__ IRDA associated UART/USART mode. 
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */ 
 #define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
@@ -676,7 +662,7 @@
 
 /**
   * @brief Ensure that IRDA sampling rate is valid.
-  * @param __ONEBIT__: IRDA sampling rate. 
+  * @param __ONEBIT__ IRDA sampling rate. 
   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
   */ 
 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
@@ -684,7 +670,7 @@
 
 /**
   * @brief Ensure that IRDA DMA TX mode is valid.
-  * @param __DMATX__: IRDA DMA TX mode. 
+  * @param __DMATX__ IRDA DMA TX mode. 
   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
   */ 
 #define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
@@ -692,7 +678,7 @@
 
 /**
   * @brief Ensure that IRDA DMA RX mode is valid.
-  * @param __DMARX__: IRDA DMA RX mode. 
+  * @param __DMARX__ IRDA DMA RX mode. 
   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
   */ 
 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
@@ -700,7 +686,7 @@
 
 /**
   * @brief Ensure that IRDA request is valid.
-  * @param __PARAM__: IRDA request. 
+  * @param __PARAM__ IRDA request. 
   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
   */ 
 #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_irda_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of IRDA HAL Extended module.
   ******************************************************************************
   * @attention
@@ -95,8 +93,8 @@
   */
 
 /** @brief  Report the IRDA clock source.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  * @param  __CLOCKSOURCE__: output variable.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __CLOCKSOURCE__ output variable.
   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
   */
 
@@ -315,7 +313,7 @@
   *         by the reception API().
   *         This masking operation is not carried out in the case of
   *         DMA transfers.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
   */
 #if defined (STM32F042x6) || defined (STM32F048xx) || \
@@ -389,7 +387,7 @@
 
 /**
   * @brief Ensure that IRDA frame length is valid.
-  * @param __LENGTH__: IRDA frame length. 
+  * @param __LENGTH__ IRDA frame length. 
   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
   */ 
 #if defined (STM32F042x6) || defined (STM32F048xx) || \

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_iwdg.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   IWDG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Independent Watchdog (IWDG) peripheral:

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_iwdg.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of IWDG HAL module.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_pcd.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   PCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
@@ -132,7 +130,7 @@
 /**
   * @brief  Initializes the PCD according to the specified
   *         parameters in the PCD_InitTypeDef and create the associated handle.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
@@ -213,7 +211,7 @@
 
 /**
   * @brief  DeInitializes the PCD peripheral 
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
@@ -239,7 +237,7 @@
 
 /**
   * @brief  Initializes the PCD MSP.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
@@ -254,7 +252,7 @@
 
 /**
   * @brief  DeInitializes PCD MSP.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
@@ -288,7 +286,7 @@
   
 /**
   * @brief  Start the USB device.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
@@ -301,7 +299,7 @@
 
 /**
   * @brief  Stop the USB device.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
@@ -323,7 +321,7 @@
 
 /**
   * @brief  This function handles PCD interrupt request.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
@@ -401,8 +399,8 @@
 
 /**
   * @brief  Data out stage callbacks
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
   * @retval None
   */
  __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -418,8 +416,8 @@
 
 /**
   * @brief  Data IN stage callbacks
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
   * @retval None
   */
  __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -434,7 +432,7 @@
 }
 /**
   * @brief  Setup stage callback
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
  __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
@@ -449,7 +447,7 @@
 
 /**
   * @brief  USB Start Of Frame callbacks
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
  __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
@@ -464,7 +462,7 @@
 
 /**
   * @brief  USB Reset callbacks
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
  __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
@@ -479,7 +477,7 @@
 
 /**
   * @brief  Suspend event callbacks
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
  __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
@@ -494,7 +492,7 @@
 
 /**
   * @brief  Resume event callbacks
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
  __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
@@ -509,8 +507,8 @@
 
 /**
   * @brief  Incomplete ISO OUT callbacks
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
   * @retval None
   */
  __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -526,8 +524,8 @@
 
 /**
   * @brief  Incomplete ISO IN  callbacks
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
   * @retval None
   */
  __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -543,7 +541,7 @@
 
 /**
   * @brief  Connection event callbacks
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
  __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
@@ -558,7 +556,7 @@
 
 /**
   * @brief  Disconnection event callbacks
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
  __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
@@ -591,7 +589,7 @@
 
 /**
   * @brief  Connect the USB device 
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
@@ -607,7 +605,7 @@
 
 /**
   * @brief  Disconnect the USB device 
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
@@ -623,8 +621,8 @@
 
 /**
   * @brief  Set the USB Device address 
-  * @param  hpcd: PCD handle
-  * @param  address: new device address
+  * @param  hpcd PCD handle
+  * @param  address new device address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
@@ -646,10 +644,10 @@
 }
 /**
   * @brief  Open and configure an endpoint
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  ep_mps: endpoint max packert size
-  * @param  ep_type: endpoint type   
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  ep_mps endpoint max packert size
+  * @param  ep_type endpoint type   
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
@@ -754,8 +752,8 @@
 
 /**
   * @brief  Deactivate an endpoint
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -825,10 +823,10 @@
 
 /**
   * @brief  Receive an amount of data  
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the reception buffer   
-  * @param  len: amount of data to be received
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the reception buffer   
+  * @param  len amount of data to be received
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
@@ -845,8 +843,6 @@
   ep->is_in = 0U;
   ep->num = ep_addr & 0x7FU;
    
-  __HAL_LOCK(hpcd); 
-   
   /* Multi packet transfer*/
   if (ep->xfer_len > ep->maxpacket)
   {
@@ -873,15 +869,13 @@
   
   PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
   
-  __HAL_UNLOCK(hpcd); 
-  
   return HAL_OK;
 }
 
 /**
   * @brief  Get Received Data Size
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
   * @retval Data Size
   */
 uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -890,10 +884,10 @@
 }
 /**
   * @brief  Send an amount of data  
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the transmission buffer   
-  * @param  len: amount of data to be sent
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the transmission buffer   
+  * @param  len amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
@@ -910,8 +904,6 @@
   ep->is_in = 1U;
   ep->num = ep_addr & 0x7FU;
   
-  __HAL_LOCK(hpcd); 
-  
   /*Multi packet transfer*/
   if (ep->xfer_len > ep->maxpacket)
   {
@@ -951,16 +943,14 @@
   }
 
   PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
-  
-  __HAL_UNLOCK(hpcd);
      
   return HAL_OK;
 }
 
 /**
   * @brief  Set a STALL condition over an endpoint
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -1005,8 +995,8 @@
 
 /**
   * @brief  Clear a STALL condition over in an endpoint
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -1045,8 +1035,8 @@
 
 /**
   * @brief  Flush an endpoint
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -1056,7 +1046,7 @@
 
 /**
   * @brief  HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
-* @param  hpcd: PCD handle
+* @param  hpcd PCD handle
 * @retval HAL status
 */
 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
@@ -1077,7 +1067,7 @@
 
 /**
 * @brief  HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
-* @param  hpcd: PCD handle
+* @param  hpcd PCD handle
 * @retval HAL status
 */
 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
@@ -1116,7 +1106,7 @@
 
 /**
   * @brief  Return the PCD state
-  * @param  hpcd : PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL state
   */
 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
@@ -1136,10 +1126,10 @@
   */
 /**
   * @brief Copy a buffer from user memory area to packet memory area (PMA)
-  * @param   USBx: USB peripheral instance register address.
-  * @param   pbUsrBuf: pointer to user memory area.
-  * @param   wPMABufAddr: address into PMA.
-  * @param   wNBytes: no. of bytes to be copied.
+  * @param   USBx USB peripheral instance register address.
+  * @param   pbUsrBuf pointer to user memory area.
+  * @param   wPMABufAddr address into PMA.
+  * @param   wNBytes no. of bytes to be copied.
   * @retval None
   */
 void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
@@ -1162,28 +1152,37 @@
 
 /**
   * @brief Copy a buffer from user memory area to packet memory area (PMA)
-  * @param   USBx: USB peripheral instance register address.
+  * @param   USBx USB peripheral instance register address.
   * @param   pbUsrBuf    = pointer to user memory area.
-  * @param   wPMABufAddr: address into PMA.
-  * @param   wNBytes: no. of bytes to be copied.
+  * @param   wPMABufAddr address into PMA.
+  * @param   wNBytes no. of bytes to be copied.
   * @retval None
   */
 void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
 {
-  uint32_t n =  ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
+  uint32_t n = (uint32_t)wNBytes >> 1U;
   uint32_t i;
   uint16_t *pdwVal;
+  uint32_t temp;
   pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
+  
   for (i = n; i != 0U; i--)
   {
-    *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++;
-    pbUsrBuf++;
+    temp = *pdwVal++;
+    *pbUsrBuf++ = ((temp >> 0) & 0xFF);
+    *pbUsrBuf++ = ((temp >> 8) & 0xFF);
+  }
+  
+  if (wNBytes % 2)
+  {
+    temp = *pdwVal++;
+    *pbUsrBuf++ = ((temp >> 0) & 0xFF);
   }
 }
 
 /**
   * @brief  This function handles PCD Endpoint interrupt request.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
@@ -1241,7 +1240,7 @@
         {
           /* Get SETUP Packet*/
           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-          PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);       
+          PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
           /* SETUP bit kept frozen while CTR_RX = 1*/ 
           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 
           

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_pcd.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
@@ -386,9 +384,9 @@
 
 /**
   * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wType: Endpoint Type.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wType Endpoint Type.
   * @retval None
   */
 #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
@@ -396,8 +394,8 @@
 
 /**
   * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval Endpoint Type
   */
 #define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
@@ -406,9 +404,9 @@
 /**
   * @brief free buffer used from the application realizing it to the line
           toggles bit SW_BUF in the double buffered endpoint register
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  bDir: Direction
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  bDir Direction
   * @retval None
   */
 #define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
@@ -425,8 +423,8 @@
 
 /**
   * @brief gets direction of the double buffered endpoint
-  * @param   USBx: USB peripheral instance register address.
-  * @param   bEpNum: Endpoint Number.
+  * @param   USBx USB peripheral instance register address.
+  * @param   bEpNum Endpoint Number.
   * @retval EP_DBUF_OUT, EP_DBUF_IN,
   *         EP_DBUF_ERR if the endpoint counter not yet programmed.
   */
@@ -442,9 +440,9 @@
 
 /**
   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wState: new state
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wState new state
   * @retval None
   */
 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
@@ -465,9 +463,9 @@
 
 /**
   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wState: new state
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wState new state
   * @retval None
   */
 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
@@ -489,10 +487,10 @@
 
 /**
   * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wStaterx: new state.
-  * @param  wStatetx: new state.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wStaterx new state.
+  * @param  wStatetx new state.
   * @retval None
   */
 #define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
@@ -525,8 +523,8 @@
 /**
   * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
   *         /STAT_RX[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval status
   */
 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
@@ -534,8 +532,8 @@
 
 /**
   * @brief  sets directly the VALID tx/rx-status into the endpoint register
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval None
   */
 #define PCD_SET_EP_TX_VALID(USBx, bEpNum)     (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
@@ -543,8 +541,8 @@
 
 /**
   * @brief  checks stall condition in an endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval TRUE = endpoint in stall condition.
   */
 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
@@ -554,8 +552,8 @@
 
 /**
   * @brief  set & clear EP_KIND bit.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval None
   */
 #define PCD_SET_EP_KIND(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
@@ -565,8 +563,8 @@
 
 /**
   * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval None
   */
 #define PCD_SET_OUT_STATUS(USBx, bEpNum)    PCD_SET_EP_KIND((USBx), (bEpNum))
@@ -574,8 +572,8 @@
 
 /**
   * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval None
   */
 #define PCD_SET_EP_DBUF(USBx, bEpNum)   PCD_SET_EP_KIND((USBx), (bEpNum))
@@ -583,8 +581,8 @@
 
 /**
   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval None
   */
 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
@@ -594,8 +592,8 @@
 
 /**
   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval None
   */
 #define PCD_RX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
@@ -605,8 +603,8 @@
 
 /**
   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval None
   */
 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
@@ -620,9 +618,9 @@
       
 /**
   * @brief  Sets address in an endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  bAddr: Address.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  bAddr Address.
   * @retval None
   */
 #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
@@ -630,8 +628,8 @@
 
 /**
   * @brief  Gets address in an endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval None
   */
 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
@@ -644,9 +642,9 @@
 
 /**
   * @brief  sets address of the tx/rx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wAddr: address to be set (must be word aligned).
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wAddr address to be set (must be word aligned).
   * @retval None
   */
 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
@@ -654,8 +652,8 @@
 
 /**
   * @brief  Gets address of the tx/rx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval address of the buffer.
   */
 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
@@ -663,9 +661,9 @@
 
 /**
   * @brief  Sets counter of rx buffer with no. of blocks.
-  * @param  dwReg: Register
-  * @param  wCount: Counter.
-  * @param  wNBlocks: no. of Blocks.
+  * @param  dwReg Register
+  * @param  wCount Counter.
+  * @param  wNBlocks no. of Blocks.
   * @retval None
   */
 #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
@@ -708,9 +706,9 @@
 
 /**
   * @brief  sets counter for the tx/rx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wCount: Counter value.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wCount Counter value.
   * @retval None
   */
 #define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
@@ -721,8 +719,8 @@
 
 /**
   * @brief  gets counter of the tx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval Counter value
   */
 #define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
@@ -730,9 +728,9 @@
 
 /**
   * @brief  Sets buffer 0/1 address in a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wBuf0Addr: buffer 0 address.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wBuf0Addr buffer 0 address.
   * @retval Counter value
   */
 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
@@ -740,10 +738,10 @@
 
 /**
   * @brief  Sets addresses in a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wBuf0Addr: buffer 0 address.
-  * @param  wBuf1Addr = buffer 1 address.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wBuf0Addr buffer 0 address.
+  * @param  wBuf1Addr buffer 1 address.
   * @retval None
   */
 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
@@ -753,8 +751,8 @@
 
 /**
   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval None
   */
 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
@@ -762,11 +760,11 @@
 
 /**
   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  bDir: endpoint dir  EP_DBUF_OUT = OUT 
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  bDir endpoint dir  EP_DBUF_OUT = OUT 
   *         EP_DBUF_IN  = IN 
-  * @param  wCount: Counter value 
+  * @param  wCount Counter value 
   * @retval None
   */
 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)  { \
@@ -797,8 +795,8 @@
 
 /**
   * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
   * @retval None
   */
 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_pcd_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Extended PCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
@@ -81,12 +79,12 @@
 
 /**
   * @brief Configure PMA for EP
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  ep_kind: endpoint Kind
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  ep_kind endpoint Kind
   *                @arg USB_SNG_BUF: Single Buffer used
   *                @arg USB_DBL_BUF: Double Buffer used
-  * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
+  * @param  pmaadress EP address in The PMA: In case of single buffer endpoint
   *                   this parameter is 16-bit value providing the address
   *                   in PMA allocated to endpoint.
   *                   In case of double buffer endpoint this parameter

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_pcd_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of PCD HAL Extension module.
   ******************************************************************************
   * @attention
@@ -36,8 +34,8 @@
   */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_PCD_EX_H
-#define __STM32L0xx_HAL_PCD_EX_H
+#ifndef __STM32F0xx_HAL_PCD_EX_H
+#define __STM32F0xx_HAL_PCD_EX_H
 
 #ifdef __cplusplus
  extern "C" {

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_pwr.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   PWR HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Power Controller (PWR) peripheral:
@@ -241,7 +239,7 @@
 
 /**
   * @brief Enables the WakeUp PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
+  * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
   *         This parameter can be value of :
   *           @ref PWREx_WakeUp_Pins
   * @retval None
@@ -256,7 +254,7 @@
 
 /**
   * @brief Disables the WakeUp PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+  * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
   *         This parameter can be values of :
   *           @ref PWREx_WakeUp_Pins
   * @retval None
@@ -272,11 +270,11 @@
 /**
   * @brief Enters Sleep mode.
   * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
-  * @param Regulator: Specifies the regulator state in SLEEP mode.
+  * @param Regulator Specifies the regulator state in SLEEP mode.
   *           On STM32F0 devices, this parameter is a dummy value and it is ignored
   *           as regulator can't be modified in this mode. Parameter is kept for platform
   *           compatibility.
-  * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
+  * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
   *           When WFI entry is used, tick interrupt have to be disabled if not desired as 
   *           the interrupt wake up source.
   *           This parameter can be one of the following values:
@@ -317,11 +315,11 @@
   *         startup delay is incurred when waking up from Stop mode.
   *         By keeping the internal regulator ON during Stop mode, the consumption
   *         is higher although the startup time is reduced.
-  * @param Regulator: Specifies the regulator state in STOP mode.
+  * @param Regulator Specifies the regulator state in STOP mode.
   *          This parameter can be one of the following values:
   *            @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
   *            @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
-  * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
   *          This parameter can be one of the following values:
   *            @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
   *            @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_pwr.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of PWR HAL module.
   ******************************************************************************
   * @attention
@@ -104,7 +102,7 @@
   */
 
 /** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *           This parameter can be one of the following values:
   *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
   *                  was received from the WKUP pin or from the RTC alarm (Alarm A),
@@ -126,7 +124,7 @@
 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the PWR's pending flags.
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be one of the following values:
   *            @arg PWR_FLAG_WU: Wake Up flag
   *            @arg PWR_FLAG_SB: StandBy flag

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_pwr_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Extended PWR HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Power Controller (PWR) peripheral:
@@ -116,7 +114,7 @@
     defined (STM32F042x6) || defined (STM32F072xB)
 /**
   * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+  * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
   *        information for the PVD.
   * @note Refer to the electrical characteristics of your device datasheet for
   *         more details about the voltage threshold corresponding to each

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_pwr_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of PWR HAL Extension module.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_rcc.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -986,7 +984,7 @@
 #endif
 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
 {
-  GPIO_InitTypeDef gpio = {0U};
+  GPIO_InitTypeDef gpio;
 
   /* Check the parameters */
   assert_param(IS_RCC_MCO(RCC_MCOx));
@@ -1068,7 +1066,7 @@
   const uint8_t aPLLMULFactorTable[16] = { 2U,  3U,  4U,  5U,  6U,  7U,  8U,  9U,
                                          10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
   const uint8_t aPredivFactorTable[16] = { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
-                                           9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U};
+                                           9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
 
   uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
   uint32_t sysclockfreq = 0U;

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_rcc.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of RCC HAL module.
   ******************************************************************************
   * @attention
@@ -68,12 +66,12 @@
 #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
 #define CLOCKSWITCH_TIMEOUT_VALUE  (5000U)  /* 5 s    */
 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
-#define HSI14_TIMEOUT_VALUE        (2U)      /* 2 ms (minimum Tick + 1) */
+#define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
+#define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
+#define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
+#define HSI14_TIMEOUT_VALUE        (2U)      /* 2 ms (minimum Tick + 1U) */
 #if defined(RCC_HSI48_SUPPORT)
-#define HSI48_TIMEOUT_VALUE        (2U)      /* 2 ms (minimum Tick + 1) */
+#define HSI48_TIMEOUT_VALUE        (2U)      /* 2 ms (minimum Tick + 1U) */
 #endif /* RCC_HSI48_SUPPORT */
 /**
   * @}
@@ -83,11 +81,11 @@
   * @{
   */
 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
-#define RCC_CR_OFFSET             0x00U
-#define RCC_CFGR_OFFSET           0x04U
-#define RCC_CIR_OFFSET            0x08U
-#define RCC_BDCR_OFFSET           0x20U
-#define RCC_CSR_OFFSET            0x24U
+#define RCC_CR_OFFSET             0x00
+#define RCC_CFGR_OFFSET           0x04
+#define RCC_CIR_OFFSET            0x08
+#define RCC_BDCR_OFFSET           0x20
+#define RCC_CSR_OFFSET            0x24
 
 /**
   * @}
@@ -114,30 +112,30 @@
 #define RCC_CFGR_HPRE_BITNUMBER           4U
 #define RCC_CFGR_PPRE_BITNUMBER           8U
 /* Flags in the CFGR2 register */
-#define RCC_CFGR2_PREDIV_BITNUMBER        0U
+#define RCC_CFGR2_PREDIV_BITNUMBER        0
 /* Flags in the CR register */
-#define RCC_CR_HSIRDY_BitNumber           1U
-#define RCC_CR_HSERDY_BitNumber           17U
-#define RCC_CR_PLLRDY_BitNumber           25U
+#define RCC_CR_HSIRDY_BitNumber           1
+#define RCC_CR_HSERDY_BitNumber           17
+#define RCC_CR_PLLRDY_BitNumber           25
 /* Flags in the CR2 register */
-#define RCC_CR2_HSI14RDY_BitNumber        1U
-#define RCC_CR2_HSI48RDY_BitNumber       16U
+#define RCC_CR2_HSI14RDY_BitNumber        1
+#define RCC_CR2_HSI48RDY_BitNumber       16
 /* Flags in the BDCR register */
-#define RCC_BDCR_LSERDY_BitNumber         1U
+#define RCC_BDCR_LSERDY_BitNumber         1
 /* Flags in the CSR register */
-#define RCC_CSR_LSIRDY_BitNumber          1U
-#define RCC_CSR_V18PWRRSTF_BitNumber      23U
-#define RCC_CSR_RMVF_BitNumber            24U
-#define RCC_CSR_OBLRSTF_BitNumber         25U
-#define RCC_CSR_PINRSTF_BitNumber         26U
-#define RCC_CSR_PORRSTF_BitNumber         27U
-#define RCC_CSR_SFTRSTF_BitNumber         28U
-#define RCC_CSR_IWDGRSTF_BitNumber        29U
-#define RCC_CSR_WWDGRSTF_BitNumber        30U
-#define RCC_CSR_LPWRRSTF_BitNumber        31U
+#define RCC_CSR_LSIRDY_BitNumber          1
+#define RCC_CSR_V18PWRRSTF_BitNumber      23
+#define RCC_CSR_RMVF_BitNumber            24
+#define RCC_CSR_OBLRSTF_BitNumber         25
+#define RCC_CSR_PINRSTF_BitNumber         26
+#define RCC_CSR_PORRSTF_BitNumber         27
+#define RCC_CSR_SFTRSTF_BitNumber         28
+#define RCC_CSR_IWDGRSTF_BitNumber        29
+#define RCC_CSR_WWDGRSTF_BitNumber        30
+#define RCC_CSR_LPWRRSTF_BitNumber        31
 /* Flags in the HSITRIM register */
-#define RCC_CR_HSITRIM_BitNumber          3U
-#define RCC_HSI14TRIM_BIT_NUMBER          3U
+#define RCC_CR_HSITRIM_BitNumber          3
+#define RCC_HSI14TRIM_BIT_NUMBER          3
 #define RCC_FLAG_MASK                    ((uint8_t)0x1FU)
 
 /**
@@ -244,20 +242,22 @@
                                        This parameter can be a value of @ref RCC_HSI_Config */
 
   uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
 
   uint32_t HSI14State;             /*!< The new state of the HSI14.
                                         This parameter can be a value of @ref RCC_HSI14_Config */
 
   uint32_t HSI14CalibrationValue;  /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
-                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
 
   uint32_t LSIState;              /*!< The new state of the LSI.
                                        This parameter can be a value of @ref RCC_LSI_Config */
 
+#if defined(RCC_HSI48_SUPPORT)
   uint32_t HSI48State;            /*!< The new state of the HSI48.
                                        This parameter can be a value of @ref RCC_HSI48_Config */
 
+#endif /* RCC_HSI48_SUPPORT */
   RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */     
 
 } RCC_OscInitTypeDef;
@@ -352,7 +352,7 @@
 /** @defgroup RCC_HSI14_Config RCC HSI14 Config
   * @{
   */
-#define RCC_HSI14_OFF                    ((uint32_t)0x00000000U)
+#define RCC_HSI14_OFF                    (0x00000000U)
 #define RCC_HSI14_ON                     RCC_CR2_HSI14ON
 #define RCC_HSI14_ADC_CONTROL            (~RCC_CR2_HSI14DIS)
 
@@ -641,56 +641,56 @@
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_SRAM_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_GPIOA_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
 #define __HAL_RCC_GPIOB_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
@@ -744,35 +744,35 @@
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_PWR_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
 #define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
@@ -818,56 +818,56 @@
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_DBGMCU_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
 #define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
@@ -1074,7 +1074,7 @@
                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
                       }                                                     \
-                    }while(0)
+                    }while(0U)
 
 /**
   * @brief  Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
@@ -1133,7 +1133,7 @@
                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
                       }                                                     \
-                    }while(0)
+                    }while(0U)
 
 /**
   * @}
@@ -1267,7 +1267,7 @@
                   do { \
                     MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
                     MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \
-                  } while(0)
+                  } while(0U)
 
 
 /** @brief  Get oscillator clock selected as PLL input clock

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_rcc_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Extended RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities RCC extension peripheral:
@@ -61,9 +59,9 @@
   * @{
   */
 /* Bit position in register */
-#define CRS_CFGR_FELIM_BITNUMBER    16U
-#define CRS_CR_TRIM_BITNUMBER       8U
-#define CRS_ISR_FECAP_BITNUMBER     16U
+#define CRS_CFGR_FELIM_BITNUMBER    16
+#define CRS_CR_TRIM_BITNUMBER       8
+#define CRS_ISR_FECAP_BITNUMBER     16
 /**
   * @}
   */
@@ -387,7 +385,9 @@
   */
 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
 {
+  /* frequency == 0 : means that no available frequency for the peripheral */
   uint32_t frequency = 0U;
+  
   uint32_t srcclk = 0U;
 #if defined(USB)
   uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U;
@@ -418,11 +418,6 @@
       {
         frequency = HSE_VALUE / 32U;
       }
-      /* Clock not enabled for RTC*/
-      else
-      {
-        frequency = 0U;
-      }
       break;
     }
   case RCC_PERIPHCLK_USART1:
@@ -450,11 +445,6 @@
       {
         frequency = LSE_VALUE;
       }
-      /* Clock not enabled for USART1*/
-      else
-      {
-        frequency = 0U;
-      }
       break;
     }
 #if defined(RCC_CFGR3_USART2SW)
@@ -483,11 +473,6 @@
       {
         frequency = LSE_VALUE;
       }
-      /* Clock not enabled for USART2*/
-      else
-      {
-        frequency = 0U;
-      }
       break;
     }
 #endif /* RCC_CFGR3_USART2SW */
@@ -517,11 +502,6 @@
       {
         frequency = LSE_VALUE;
       }
-      /* Clock not enabled for USART3*/
-      else
-      {
-        frequency = 0U;
-      }
       break;
     }
 #endif /* RCC_CFGR3_USART3SW */
@@ -540,11 +520,6 @@
       {
         frequency = HAL_RCC_GetSysClockFreq();
       }
-      /* Clock not enabled for I2C1*/
-      else
-      {
-        frequency = 0U;
-      }
       break;
     }
 #if defined(USB)
@@ -580,7 +555,7 @@
           /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */
           frequency = (HSI_VALUE / predivfactor) * pllmull;
 #else
-          /* HSI used as PLL clock source : frequency = HSI/2 * PLLMUL */
+          /* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */
           frequency = (HSI_VALUE >> 1U) * pllmull;
 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */
         }
@@ -592,11 +567,6 @@
         frequency = HSI48_VALUE;
       }
 #endif /* RCC_CR2_HSI48ON */
-      /* Clock not enabled for USB*/
-      else
-      {
-        frequency = 0U;
-      }
       break;
     }
 #endif /* USB */
@@ -616,11 +586,6 @@
       {
         frequency = LSE_VALUE;
       }
-      /* Clock not enabled for CEC */
-      else
-      {
-        frequency = 0U;
-      }
       break;
     }
 #endif /* CEC */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_rcc_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of RCC HAL Extension module.
   ******************************************************************************
   * @attention
@@ -600,14 +598,14 @@
 typedef struct
 {
   uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
-                                     This parameter must be a number between 0 and 0xFFFF */
+                                     This parameter must be a number between 0 and 0xFFFFU */
 
   uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
-                                     This parameter must be a number between 0 and 0x3F */
+                                     This parameter must be a number between 0 and 0x3FU */
 
   uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter 
                                                                     value latched in the time of the last SYNC event.
-                                    This parameter must be a number between 0 and 0xFFFF */
+                                    This parameter must be a number between 0 and 0xFFFFU */
 
   uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 
                                                                     frequency error counter latched in the time of the last SYNC event. 
@@ -839,7 +837,7 @@
 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
   * @{
   */
-#define RCC_CRS_SYNC_SOURCE_GPIO       ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
+#define RCC_CRS_SYNC_SOURCE_GPIO       (0x00000000U) /*!< Synchro Signal source GPIO */
 #define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
 #define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
 /**
@@ -849,7 +847,7 @@
 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
   * @{
   */
-#define RCC_CRS_SYNC_DIV1        ((uint32_t)0x00000000U)                   /*!< Synchro Signal not divided (default) */
+#define RCC_CRS_SYNC_DIV1        (0x00000000U)                   /*!< Synchro Signal not divided (default) */
 #define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
 #define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
 #define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
@@ -864,7 +862,7 @@
 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
   * @{
   */
-#define RCC_CRS_SYNC_POLARITY_RISING   ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
+#define RCC_CRS_SYNC_POLARITY_RISING   (0x00000000U) /*!< Synchro Active on rising edge (default) */
 #define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
 /**
   * @}
@@ -873,7 +871,7 @@
 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
   * @{
   */
-#define RCC_CRS_RELOADVALUE_DEFAULT    ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 
+#define RCC_CRS_RELOADVALUE_DEFAULT    (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 
                                                                     to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
 /**
   * @}
@@ -882,7 +880,7 @@
 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
   * @{
   */
-#define RCC_CRS_ERRORLIMIT_DEFAULT     ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
+#define RCC_CRS_ERRORLIMIT_DEFAULT     (0x00000022U) /*!< Default Frequency error limit */
 /**
   * @}
   */
@@ -890,7 +888,7 @@
 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
   * @{
   */
-#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 
                                                                       The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
                                                                       corresponds to a higher output frequency */  
 /**
@@ -900,7 +898,7 @@
 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
   * @{
   */
-#define RCC_CRS_FREQERRORDIR_UP        ((uint32_t)0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
+#define RCC_CRS_FREQERRORDIR_UP        (0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
 #define RCC_CRS_FREQERRORDIR_DOWN      ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
 /**
   * @}
@@ -962,7 +960,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
 
@@ -976,7 +974,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
 
@@ -993,7 +991,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_TSC_CLK_DISABLE()          (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
 
@@ -1010,7 +1008,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_DMA2_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
 
@@ -1033,7 +1031,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 
@@ -1054,7 +1052,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
 
@@ -1075,7 +1073,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
 
@@ -1096,14 +1094,14 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
 #define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
@@ -1123,7 +1121,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_DAC1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
 
@@ -1142,7 +1140,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_CEC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
 
@@ -1160,21 +1158,21 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_USART3_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_USART4_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
@@ -1192,7 +1190,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_USB_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
 
@@ -1208,7 +1206,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
 
 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB  || */
@@ -1222,7 +1220,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_CRS_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
 
@@ -1236,7 +1234,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_USART5_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
 
@@ -1258,7 +1256,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_TIM15_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
 
@@ -1275,7 +1273,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_USART6_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
 
@@ -1289,14 +1287,14 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_USART8_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_USART7_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
 #define __HAL_RCC_USART8_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
@@ -1942,7 +1940,7 @@
                                                  { \
                                                    WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
                                                  } \
-                                               } while(0)
+                                               } while(0U)
 
 /**
   * @brief  Check whether the specified CRS flag is set or not.
@@ -1982,7 +1980,7 @@
                                                  { \
                                                    WRITE_REG(CRS->ICR, (__FLAG__)); \
                                                  } \
-                                               } while(0)
+                                               } while(0U)
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_rtc.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   RTC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Real Time Clock (RTC) peripheral:
@@ -146,7 +144,7 @@
 /**
   * @brief  Initialize the RTC according to the specified parameters 
   *         in the RTC_InitTypeDef structure and initialize the associated handle.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
@@ -205,7 +203,21 @@
     
     /* Exit Initialization mode */
     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-    
+
+    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
     hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
     hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); 
     
@@ -221,7 +233,7 @@
 
 /**
   * @brief  DeInitialize the RTC peripheral.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @note   This function doesn't reset the RTC Backup Data registers.
   * @retval HAL status
   */
@@ -339,7 +351,7 @@
 
 /**
   * @brief  Initialize the RTC MSP.
-  * @param  hrtc: RTC handle  
+  * @param  hrtc RTC handle  
   * @retval None
   */
 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
@@ -354,7 +366,7 @@
 
 /**
   * @brief  DeInitialize the RTC MSP.
-  * @param  hrtc: RTC handle 
+  * @param  hrtc RTC handle 
   * @retval None
   */
 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
@@ -387,9 +399,9 @@
 
 /**
   * @brief  Set RTC current time.
-  * @param  hrtc: RTC handle
-  * @param  sTime: Pointer to Time structure
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  hrtc RTC handle
+  * @param  sTime Pointer to Time structure
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
   *            @arg RTC_FORMAT_BIN: Binary data format 
   *            @arg RTC_FORMAT_BCD: BCD data format
@@ -473,7 +485,7 @@
     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
      
     /* Clear the bits to be configured */
-    hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
+    hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
 
     /* Configure the RTC_CR register */
     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
@@ -511,12 +523,12 @@
 
 /**
   * @brief  Get RTC current time.
-  * @param  hrtc: RTC handle
-  * @param  sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned 
+  * @param  hrtc RTC handle
+  * @param  sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned 
   *                with input format (BIN or BCD), also SubSeconds field returning the
   *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
   *                factor to be used for second fraction ratio computation.
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
   *            @arg RTC_FORMAT_BIN: Binary data format 
   *            @arg RTC_FORMAT_BCD: BCD data format
@@ -566,9 +578,9 @@
 
 /**
   * @brief  Set RTC current date.
-  * @param  hrtc: RTC handle
-  * @param  sDate: Pointer to date structure
-  * @param  Format: specifies the format of the entered parameters.
+  * @param  hrtc RTC handle
+  * @param  sDate Pointer to date structure
+  * @param  Format specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
   *            @arg RTC_FORMAT_BIN: Binary data format 
   *            @arg RTC_FORMAT_BCD: BCD data format
@@ -674,9 +686,9 @@
 
 /**
   * @brief  Get RTC current date.
-  * @param  hrtc: RTC handle
-  * @param  sDate: Pointer to Date structure
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  hrtc RTC handle
+  * @param  sDate Pointer to Date structure
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
   *            @arg RTC_FORMAT_BIN :  Binary data format 
   *            @arg RTC_FORMAT_BCD :  BCD data format
@@ -731,9 +743,9 @@
   */
 /**
   * @brief  Set the specified RTC Alarm.
-  * @param  hrtc: RTC handle
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  hrtc RTC handle
+  * @param  sAlarm Pointer to Alarm structure
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
   *             @arg RTC_FORMAT_BIN: Binary data format 
   *             @arg RTC_FORMAT_BCD: BCD data format
@@ -876,9 +888,9 @@
 
 /**
   * @brief  Set the specified RTC Alarm with Interrupt.
-  * @param  hrtc: RTC handle
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  hrtc RTC handle
+  * @param  sAlarm Pointer to Alarm structure
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
   *             @arg RTC_FORMAT_BIN: Binary data format 
   *             @arg RTC_FORMAT_BCD: BCD data format
@@ -1028,8 +1040,8 @@
 
 /**
   * @brief  Deactivate the specified RTC Alarm.
-  * @param  hrtc: RTC handle
-  * @param  Alarm: Specifies the Alarm.
+  * @param  hrtc RTC handle
+  * @param  Alarm Specifies the Alarm.
   *          This parameter can be one of the following values:
   *            @arg RTC_ALARM_A:  AlarmA
   * @retval HAL status
@@ -1085,12 +1097,12 @@
            
 /**
   * @brief  Get the RTC Alarm value and masks.
-  * @param  hrtc: RTC handle
-  * @param  sAlarm: Pointer to Date structure
-  * @param  Alarm: Specifies the Alarm.
+  * @param  hrtc RTC handle
+  * @param  sAlarm Pointer to Date structure
+  * @param  Alarm Specifies the Alarm.
   *          This parameter can be one of the following values:
   *             @arg RTC_ALARM_A: AlarmA
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
   *             @arg RTC_FORMAT_BIN: Binary data format 
   *             @arg RTC_FORMAT_BCD: BCD data format
@@ -1132,7 +1144,7 @@
 
 /**
   * @brief  Handle Alarm interrupt request.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval None
   */
 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
@@ -1160,7 +1172,7 @@
 
 /**
   * @brief  Alarm A callback.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval None
   */
 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1175,8 +1187,8 @@
 
 /**
   * @brief  Handle AlarmA Polling request.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
+  * @param  hrtc RTC handle
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -1235,7 +1247,7 @@
   *         The software must then wait until it is set again before reading
   *         the calendar, which means that the calendar registers have been
   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
@@ -1279,7 +1291,7 @@
   */
 /**
   * @brief  Return the RTC handle state.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval HAL state
   */
 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
@@ -1303,7 +1315,7 @@
   * @brief  Enter the RTC Initialization mode.
   * @note   The RTC Initialization mode is write protected, use the
   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
@@ -1334,7 +1346,7 @@
 
 /**
   * @brief  Convert a 2 digit decimal to BCD format.
-  * @param  Value: Byte to be converted
+  * @param  Value Byte to be converted
   * @retval Converted byte
   */
 uint8_t RTC_ByteToBcd2(uint8_t Value)
@@ -1352,7 +1364,7 @@
 
 /**
   * @brief  Convert from 2 digit BCD to Binary.
-  * @param  Value: BCD value to be converted
+  * @param  Value BCD value to be converted
   * @retval Converted word
   */
 uint8_t RTC_Bcd2ToByte(uint8_t Value)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_rtc.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of RTC HAL module.
   ******************************************************************************
   * @attention
@@ -202,8 +200,8 @@
 /** @defgroup RTC_Hour_Formats RTC Hour Formats
   * @{
   */ 
-#define RTC_HOURFORMAT_24              (0x00000000U)
-#define RTC_HOURFORMAT_12              (0x00000040U)
+#define RTC_HOURFORMAT_24              0x00000000U
+#define RTC_HOURFORMAT_12              0x00000040U
 
 /**
   * @}
@@ -212,8 +210,8 @@
 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
   * @{
   */ 
-#define RTC_OUTPUT_POLARITY_HIGH       (0x00000000U)
-#define RTC_OUTPUT_POLARITY_LOW        (0x00100000U)
+#define RTC_OUTPUT_POLARITY_HIGH       0x00000000U
+#define RTC_OUTPUT_POLARITY_LOW        0x00100000U
 /**
   * @}
   */ 
@@ -221,8 +219,8 @@
 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
   * @{
   */ 
-#define RTC_OUTPUT_TYPE_OPENDRAIN      (0x00000000U)
-#define RTC_OUTPUT_TYPE_PUSHPULL       (0x00040000U)
+#define RTC_OUTPUT_TYPE_OPENDRAIN      0x00000000U
+#define RTC_OUTPUT_TYPE_PUSHPULL       0x00040000U
 /**
   * @}
   */ 
@@ -230,8 +228,8 @@
 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
   * @{
   */ 
-#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00U)
-#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40U)
+#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
 /**
   * @}
   */ 
@@ -239,9 +237,9 @@
 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
   * @{
   */ 
-#define RTC_DAYLIGHTSAVING_SUB1H       (0x00020000U)
-#define RTC_DAYLIGHTSAVING_ADD1H       (0x00010000U)
-#define RTC_DAYLIGHTSAVING_NONE        (0x00000000U)
+#define RTC_DAYLIGHTSAVING_SUB1H       0x00020000U
+#define RTC_DAYLIGHTSAVING_ADD1H       0x00010000U
+#define RTC_DAYLIGHTSAVING_NONE        0x00000000U
 /**
   * @}
   */
@@ -249,8 +247,8 @@
 /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
   * @{
   */ 
-#define RTC_STOREOPERATION_RESET        (0x00000000U)
-#define RTC_STOREOPERATION_SET          (0x00040000U)
+#define RTC_STOREOPERATION_RESET        0x00000000U
+#define RTC_STOREOPERATION_SET          0x00040000U
 /**
   * @}
   */
@@ -258,8 +256,8 @@
 /** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
   * @{
   */ 
-#define RTC_FORMAT_BIN                      (0x000000000U)
-#define RTC_FORMAT_BCD                      (0x000000001U)
+#define RTC_FORMAT_BIN                      0x000000000U
+#define RTC_FORMAT_BCD                      0x000000001U
 /**
   * @}
   */
@@ -268,18 +266,18 @@
   * @{
   */ 
 /* Coded in BCD format */
-#define RTC_MONTH_JANUARY              ((uint8_t)0x01U)
-#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02U)
-#define RTC_MONTH_MARCH                ((uint8_t)0x03U)
-#define RTC_MONTH_APRIL                ((uint8_t)0x04U)
-#define RTC_MONTH_MAY                  ((uint8_t)0x05U)
-#define RTC_MONTH_JUNE                 ((uint8_t)0x06U)
-#define RTC_MONTH_JULY                 ((uint8_t)0x07U)
-#define RTC_MONTH_AUGUST               ((uint8_t)0x08U)
-#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09U)
-#define RTC_MONTH_OCTOBER              ((uint8_t)0x10U)
-#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11U)
-#define RTC_MONTH_DECEMBER             ((uint8_t)0x12U)
+#define RTC_MONTH_JANUARY              ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
+#define RTC_MONTH_MARCH                ((uint8_t)0x03)
+#define RTC_MONTH_APRIL                ((uint8_t)0x04)
+#define RTC_MONTH_MAY                  ((uint8_t)0x05)
+#define RTC_MONTH_JUNE                 ((uint8_t)0x06)
+#define RTC_MONTH_JULY                 ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST               ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
 /**
   * @}
   */ 
@@ -287,13 +285,13 @@
 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
   * @{
   */   
-#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01U)
-#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02U)
-#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03U)
-#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04U)
-#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05U)
-#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06U)
-#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07U)
+#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
 /**
   * @}
   */ 
@@ -301,8 +299,8 @@
 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
   * @{
   */ 
-#define RTC_ALARMDATEWEEKDAYSEL_DATE      (0x00000000U)
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   (0x40000000U)
+#define RTC_ALARMDATEWEEKDAYSEL_DATE      0x00000000U
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   0x40000000U
 /**
   * @}
   */ 
@@ -310,12 +308,12 @@
 /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
   * @{
   */ 
-#define RTC_ALARMMASK_NONE                (0x00000000U)
+#define RTC_ALARMMASK_NONE                0x00000000U
 #define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
 #define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
 #define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
 #define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL                 (0x80808080U)
+#define RTC_ALARMMASK_ALL                 0x80808080U
 /**
   * @}
   */ 
@@ -332,38 +330,38 @@
 /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
   * @{
   */ 
-#define RTC_ALARMSUBSECONDMASK_ALL         (0x00000000U)  /*!< All Alarm SS fields are masked. 
+#define RTC_ALARMSUBSECONDMASK_ALL         0x00000000U  /*!< All Alarm SS fields are masked. 
                                                                         There is no comparison on sub seconds 
                                                                         for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1      (0x01000000U)  /*!< SS[14:1] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_1      0x01000000U  /*!< SS[14:1] are don't care in Alarm 
                                                                         comparison. Only SS[0] is compared.    */
-#define RTC_ALARMSUBSECONDMASK_SS14_2      (0x02000000U)  /*!< SS[14:2] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_2      0x02000000U  /*!< SS[14:2] are don't care in Alarm 
                                                                         comparison. Only SS[1:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_3      (0x03000000U)  /*!< SS[14:3] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_3      0x03000000U  /*!< SS[14:3] are don't care in Alarm 
                                                                         comparison. Only SS[2:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_4      (0x04000000U)  /*!< SS[14:4] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_4      0x04000000U  /*!< SS[14:4] are don't care in Alarm 
                                                                         comparison. Only SS[3:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_5      (0x05000000U)  /*!< SS[14:5] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_5      0x05000000U  /*!< SS[14:5] are don't care in Alarm 
                                                                         comparison. Only SS[4:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_6      (0x06000000U)  /*!< SS[14:6] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_6      0x06000000U  /*!< SS[14:6] are don't care in Alarm 
                                                                         comparison. Only SS[5:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_7      (0x07000000U)  /*!< SS[14:7] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_7      0x07000000U  /*!< SS[14:7] are don't care in Alarm 
                                                                         comparison. Only SS[6:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_8      (0x08000000U)  /*!< SS[14:8] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_8      0x08000000U  /*!< SS[14:8] are don't care in Alarm 
                                                                         comparison. Only SS[7:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_9      (0x09000000U)  /*!< SS[14:9] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_9      0x09000000U  /*!< SS[14:9] are don't care in Alarm 
                                                                         comparison. Only SS[8:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_10     (0x0A000000U)  /*!< SS[14:10] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_10     0x0A000000U  /*!< SS[14:10] are don't care in Alarm 
                                                                         comparison. Only SS[9:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_11     (0x0B000000U)  /*!< SS[14:11] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_11     0x0B000000U  /*!< SS[14:11] are don't care in Alarm 
                                                                         comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12     (0x0C000000U)  /*!< SS[14:12] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_12     0x0C000000U  /*!< SS[14:12] are don't care in Alarm 
                                                                         comparison.Only SS[11:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_13     (0x0D000000U)  /*!< SS[14:13] are don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14_13     0x0D000000U  /*!< SS[14:13] are don't care in Alarm 
                                                                         comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14        (0x0E000000U)  /*!< SS[14] is don't care in Alarm 
+#define RTC_ALARMSUBSECONDMASK_SS14        0x0E000000U  /*!< SS[14] is don't care in Alarm 
                                                                         comparison.Only SS[13:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_NONE        (0x0F000000U)  /*!< SS[14:0] are compared and must match 
+#define RTC_ALARMSUBSECONDMASK_NONE        0x0F000000U  /*!< SS[14:0] are compared and must match 
                                                                         to activate alarm. */
 /**
   * @}
@@ -372,13 +370,13 @@
 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
   * @{
   */
-#define RTC_IT_TS                         (0x00008000U)
-#define RTC_IT_WUT                        (0x00004000U)
-#define RTC_IT_ALRA                       (0x00001000U)
-#define RTC_IT_TAMP                       (0x00000004U) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1                      (0x00020000U) /*only for RTC_ISR flag check*/
-#define RTC_IT_TAMP2                      (0x00040000U) /*only for RTC_ISR flag check*/
-#define RTC_IT_TAMP3                      (0x00080000U) /*only for RTC_ISR flag check*/
+#define RTC_IT_TS                         0x00008000U
+#define RTC_IT_WUT                        0x00004000U
+#define RTC_IT_ALRA                       0x00001000U
+#define RTC_IT_TAMP                       0x00000004U /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1                      0x00020000U /*only for RTC_ISR flag check*/
+#define RTC_IT_TAMP2                      0x00040000U /*only for RTC_ISR flag check*/
+#define RTC_IT_TAMP3                      0x00080000U /*only for RTC_ISR flag check*/
 /**
   * @}
   */
@@ -386,20 +384,20 @@
 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
   * @{
   */
-#define RTC_FLAG_RECALPF                  (0x00010000U)
-#define RTC_FLAG_TAMP3F                   (0x00008000U)
-#define RTC_FLAG_TAMP2F                   (0x00004000U)
-#define RTC_FLAG_TAMP1F                   (0x00002000U)
-#define RTC_FLAG_TSOVF                    (0x00001000U)
-#define RTC_FLAG_TSF                      (0x00000800U)
-#define RTC_FLAG_WUTF                     (0x00000400U)
-#define RTC_FLAG_ALRAF                    (0x00000100U)
-#define RTC_FLAG_INITF                    (0x00000040U)
-#define RTC_FLAG_RSF                      (0x00000020U)
-#define RTC_FLAG_INITS                    (0x00000010U)
-#define RTC_FLAG_SHPF                     (0x00000008U)
-#define RTC_FLAG_WUTWF                    (0x00000004U)
-#define RTC_FLAG_ALRAWF                   (0x00000001U)
+#define RTC_FLAG_RECALPF                  0x00010000U
+#define RTC_FLAG_TAMP3F                   0x00008000U
+#define RTC_FLAG_TAMP2F                   0x00004000U
+#define RTC_FLAG_TAMP1F                   0x00002000U
+#define RTC_FLAG_TSOVF                    0x00001000U
+#define RTC_FLAG_TSF                      0x00000800U
+#define RTC_FLAG_WUTF                     0x00000400U
+#define RTC_FLAG_ALRAF                    0x00000100U
+#define RTC_FLAG_INITF                    0x00000040U
+#define RTC_FLAG_RSF                      0x00000020U
+#define RTC_FLAG_INITS                    0x00000010U
+#define RTC_FLAG_SHPF                     0x00000008U
+#define RTC_FLAG_WUTWF                    0x00000004U
+#define RTC_FLAG_ALRAWF                   0x00000001U
 /**
   * @}
   */
@@ -414,14 +412,14 @@
   */
 
 /** @brief Reset RTC handle state
-  * @param  __HANDLE__: RTC handle.
+  * @param  __HANDLE__ RTC handle.
   * @retval None
   */
 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
 
 /**
   * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
@@ -432,7 +430,7 @@
 
 /**
   * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
@@ -442,22 +440,22 @@
  
 /**
   * @brief  Enable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
 
 /**
   * @brief  Disable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
 
 /**
   * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
   *          This parameter can be any combination of the following values:
   *             @arg RTC_IT_ALRA: Alarm A interrupt
   * @retval None
@@ -466,8 +464,8 @@
 
 /**
   * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
   *         This parameter can be any combination of the following values:
   *            @arg RTC_IT_ALRA: Alarm A interrupt
   * @retval None
@@ -476,8 +474,8 @@
 
 /**
   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt to check.
   *         This parameter can be:
   *            @arg RTC_IT_ALRA: Alarm A interrupt
   * @retval None
@@ -486,8 +484,8 @@
 
 /**
   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
   *         This parameter can be:
   *            @arg RTC_IT_ALRA: Alarm A interrupt
   * @retval None
@@ -496,8 +494,8 @@
 
 /**
   * @brief  Get the selected RTC Alarm's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
   *         This parameter can be:
   *            @arg RTC_FLAG_ALRAF
   *            @arg RTC_FLAG_ALRAWF
@@ -507,8 +505,8 @@
 
 /**
   * @brief  Clear the RTC Alarm's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
   *         This parameter can be:
   *            @arg RTC_FLAG_ALRAF
   * @retval None
@@ -674,10 +672,10 @@
   * @{
   */
 /* Masks Definition */
-#define RTC_TR_RESERVED_MASK    (0x007F7F7FU)
-#define RTC_DR_RESERVED_MASK    (0x00FFFF3FU) 
-#define RTC_INIT_MASK           (0xFFFFFFFFU)  
-#define RTC_RSF_MASK            (0xFFFFFF5FU)
+#define RTC_TR_RESERVED_MASK    0x007F7F7FU
+#define RTC_DR_RESERVED_MASK    0x00FFFF3FU
+#define RTC_INIT_MASK           0xFFFFFFFFU
+#define RTC_RSF_MASK            0xFFFFFF5FU
 #define RTC_FLAGS_MASK          ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
                                              RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF       | \
                                              RTC_FLAG_WUTF  | RTC_FLAG_ALRAF      | \

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_rtc_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Extended RTC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Real Time Clock (RTC) Extended peripheral:
@@ -136,15 +134,15 @@
 /**
   * @brief  Set TimeStamp.
   * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  hrtc: RTC handle
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+  * @param  hrtc RTC handle
+  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
   *         activated.
   *          This parameter can be one of the following values:
   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
   *                                        rising edge of the related pin.
   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
   *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
+  * @param  RTC_TimeStampPin specifies the RTC TimeStamp Pin.
   *          This parameter can be one of the following values:
   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
   * @retval HAL status
@@ -189,16 +187,16 @@
 
 /**
   * @brief  Set TimeStamp with Interrupt.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is 
   *         activated.
   *          This parameter can be one of the following values:
   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
   *                                        rising edge of the related pin.
   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
   *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
+  * @param  RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
   *          This parameter can be one of the following values:
   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
   * @retval HAL status
@@ -250,7 +248,7 @@
 
 /**
   * @brief  Deactivate TimeStamp.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
@@ -287,11 +285,11 @@
 
 /**
   * @brief  Get the RTC TimeStamp value.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
 
-  * @param  sTimeStamp: Pointer to Time structure
-  * @param  sTimeStampDate: Pointer to Date structure  
-  * @param  Format: specifies the format of the entered parameters.
+  * @param  sTimeStamp Pointer to Time structure
+  * @param  sTimeStampDate Pointer to Date structure  
+  * @param  Format specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
   *             @arg RTC_FORMAT_BIN: Binary data format 
   *             @arg RTC_FORMAT_BCD: BCD data format
@@ -344,8 +342,8 @@
 /**
   * @brief  Set Tamper
   * @note   By calling this API we disable the tamper interrupt for all tampers.
-  * @param  hrtc: RTC handle
-  * @param  sTamper: Pointer to Tamper Structure.
+  * @param  hrtc RTC handle
+  * @param  sTamper Pointer to Tamper Structure.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
@@ -392,9 +390,9 @@
 /**
   * @brief  Sets Tamper with interrupt.
   * @note   By calling this API we force the tamper interrupt for all tampers.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sTamper: Pointer to RTC Tamper.
+  * @param  sTamper Pointer to RTC Tamper.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
@@ -449,8 +447,8 @@
 
 /**
   * @brief  Deactivate Tamper.
-  * @param  hrtc: RTC handle
-  * @param  Tamper: Selected tamper pin.
+  * @param  hrtc RTC handle
+  * @param  Tamper Selected tamper pin.
   *          This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
   * @retval HAL status
   */
@@ -476,7 +474,7 @@
 
 /**
   * @brief  Handle TimeStamp interrupt request.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval None
   */
 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -548,7 +546,7 @@
 
 /**
   * @brief  TimeStamp callback. 
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval None
   */
 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
@@ -563,7 +561,7 @@
 
 /**
   * @brief  Tamper 1 callback.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval None
   */
 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
@@ -578,7 +576,7 @@
 
 /**
   * @brief  Tamper 2 callback. 
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval None
   */
 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
@@ -594,7 +592,7 @@
 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
 /**
   * @brief  Tamper 3 callback. 
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval None
   */
 __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
@@ -610,8 +608,8 @@
 
 /**
   * @brief  Handle TimeStamp polling request.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
+  * @param  hrtc RTC handle
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -649,8 +647,8 @@
 
 /**
   * @brief  Handle Tamper 1 Polling.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
+  * @param  hrtc RTC handle
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -681,8 +679,8 @@
 
 /**
   * @brief  Handle Tamper 2 Polling.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
+  * @param  hrtc RTC handle
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -714,8 +712,8 @@
 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
 /**
   * @brief  Handle Tamper 3 Polling.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
+  * @param  hrtc RTC handle
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -766,9 +764,9 @@
 
 /**
   * @brief  Set wake up timer.
-  * @param  hrtc: RTC handle
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock
+  * @param  hrtc RTC handle
+  * @param  WakeUpCounter Wake up counter
+  * @param  WakeUpClock Wake up clock
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -855,9 +853,9 @@
 
 /**
   * @brief  Set wake up timer with interrupt.
-  * @param  hrtc: RTC handle
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock  
+  * @param  hrtc RTC handle
+  * @param  WakeUpCounter Wake up counter
+  * @param  WakeUpClock Wake up clock  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -956,7 +954,7 @@
 
 /**
   * @brief  Deactivate wake up timer counter.
-  * @param  hrtc: RTC handle 
+  * @param  hrtc RTC handle 
   * @retval HAL status
   */
 uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -1008,7 +1006,7 @@
 
 /**
   * @brief  Get wake up timer counter.
-  * @param  hrtc: RTC handle 
+  * @param  hrtc RTC handle 
   * @retval Counter value
   */
 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -1019,7 +1017,7 @@
 
 /**
   * @brief  Handle Wake Up Timer interrupt request.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval None
   */
 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -1047,7 +1045,7 @@
 
 /**
   * @brief  Wake Up Timer callback.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval None
   */
 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1063,8 +1061,8 @@
 
 /**
   * @brief  Handle Wake Up Timer Polling.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
+  * @param  hrtc RTC handle
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -1127,11 +1125,11 @@
 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
 /**
   * @brief  Write a data in a specified RTC Backup data register.
-  * @param  hrtc: RTC handle 
-  * @param  BackupRegister: RTC Backup data Register number.
+  * @param  hrtc RTC handle 
+  * @param  BackupRegister RTC Backup data Register number.
   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to 
   *                                 specify the register.
-  * @param  Data: Data to be written in the specified RTC Backup data register.                     
+  * @param  Data Data to be written in the specified RTC Backup data register.                     
   * @retval None
   */
 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
@@ -1150,8 +1148,8 @@
 
 /**
   * @brief  Reads data from the specified RTC Backup data Register.
-  * @param  hrtc: RTC handle 
-  * @param  BackupRegister: RTC Backup data Register number.
+  * @param  hrtc RTC handle 
+  * @param  BackupRegister RTC Backup data Register number.
   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to 
   *                                 specify the register.                   
   * @retval Read value
@@ -1173,17 +1171,17 @@
 
 /**
   * @brief  Set the Smooth calibration parameters.
-  * @param  hrtc: RTC handle  
-  * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
+  * @param  hrtc RTC handle  
+  * @param  SmoothCalibPeriod Select the Smooth Calibration Period.
   *          This parameter can be can be one of the following values :
   *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
   *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
   *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
-  * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+  * @param  SmoothCalibPlusPulses Select to Set or reset the CALP bit.
   *          This parameter can be one of the following values:
   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
-  * @param  SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+  * @param  SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
   *          This parameter can be one any value from 0 to 0x000001FF.
   * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses 
   *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
@@ -1249,12 +1247,12 @@
 /**
   * @brief  Configure the Synchronization Shift Control Settings.
   * @note   When REFCKON is set, firmware must not write to Shift control register. 
-  * @param  hrtc: RTC handle    
-  * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
+  * @param  hrtc RTC handle    
+  * @param  ShiftAdd1S Select to add or not 1 second to the time calendar.
   *          This parameter can be one of the following values :
   *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. 
   *             @arg RTC_SHIFTADD1S_RESET: No effect.
-  * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
+  * @param  ShiftSubFS Select the number of Second Fractions to substitute.
   *          This parameter can be one any value from 0 to 0x7FFF.
   * @retval HAL status
   */
@@ -1344,8 +1342,8 @@
 
 /**
   * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: RTC handle
-  * @param  CalibOutput : Select the Calibration output Selection .
+  * @param  hrtc RTC handle
+  * @param  CalibOutput Select the Calibration output Selection .
   *          This parameter can be one of the following values:
   *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
   *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
@@ -1386,7 +1384,7 @@
 
 /**
   * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
@@ -1415,7 +1413,7 @@
 
 /**
   * @brief  Enable the RTC reference clock detection.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
@@ -1464,7 +1462,7 @@
 
 /**
   * @brief  Disable the RTC reference clock detection.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
@@ -1513,7 +1511,7 @@
 
 /**
   * @brief  Enable the Bypass Shadow feature.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @note   When the Bypass Shadow is enabled the calendar value are taken
   *         directly from the Calendar counter.
   * @retval HAL status
@@ -1545,7 +1543,7 @@
 
 /**
   * @brief  Disable the Bypass Shadow feature.
-  * @param  hrtc: RTC handle
+  * @param  hrtc RTC handle
   * @note   When the Bypass Shadow is enabled the calendar value are taken
   *         directly from the Calendar counter.
   * @retval HAL status

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_rtc_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of RTC HAL Extended module.
   ******************************************************************************
   * @attention
@@ -98,10 +96,10 @@
 /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
   * @{
   */
-#define RTC_OUTPUT_DISABLE             (0x00000000U)
-#define RTC_OUTPUT_ALARMA              (0x00200000U)
+#define RTC_OUTPUT_DISABLE             0x00000000U
+#define RTC_OUTPUT_ALARMA              0x00200000U
 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-#define RTC_OUTPUT_WAKEUP              (0x00600000U)
+#define RTC_OUTPUT_WAKEUP              0x00600000U
 #endif
 
 /**
@@ -112,11 +110,11 @@
 /** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition
   * @{
   */
-#define RTC_BKP_DR0                       (0x00000000U)
-#define RTC_BKP_DR1                       (0x00000001U)
-#define RTC_BKP_DR2                       (0x00000002U)
-#define RTC_BKP_DR3                       (0x00000003U)
-#define RTC_BKP_DR4                       (0x00000004U)
+#define RTC_BKP_DR0                       0x00000000U
+#define RTC_BKP_DR1                       0x00000001U
+#define RTC_BKP_DR2                       0x00000002U
+#define RTC_BKP_DR3                       0x00000003U
+#define RTC_BKP_DR4                       0x00000004U
 /**
   * @}
   */
@@ -125,8 +123,8 @@
 /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
   * @{
   */
-#define RTC_TIMESTAMPEDGE_RISING          (0x00000000U)
-#define RTC_TIMESTAMPEDGE_FALLING         (0x00000008U)
+#define RTC_TIMESTAMPEDGE_RISING          0x00000000U
+#define RTC_TIMESTAMPEDGE_FALLING         0x00000008U
 
 /**
   * @}
@@ -135,7 +133,7 @@
 /** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
   * @{
   */
-#define RTC_TIMESTAMPPIN_DEFAULT              (0x00000000U)
+#define RTC_TIMESTAMPPIN_DEFAULT              0x00000000U
 
 /**
   * @}
@@ -160,8 +158,8 @@
 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definition
   * @{
   */
-#define RTC_TAMPERTRIGGER_RISINGEDGE       (0x00000000U)
-#define RTC_TAMPERTRIGGER_FALLINGEDGE      (0x00000002U)
+#define RTC_TAMPERTRIGGER_RISINGEDGE       0x00000000U
+#define RTC_TAMPERTRIGGER_FALLINGEDGE      0x00000002U
 #define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
 #define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
 
@@ -173,13 +171,13 @@
 /** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definition
   * @{
   */
-#define RTC_TAMPERFILTER_DISABLE   (0x00000000U)  /*!< Tamper filter is disabled */
+#define RTC_TAMPERFILTER_DISABLE   0x00000000U  /*!< Tamper filter is disabled */
 
-#define RTC_TAMPERFILTER_2SAMPLE   (0x00000800U)  /*!< Tamper is activated after 2
+#define RTC_TAMPERFILTER_2SAMPLE   0x00000800U  /*!< Tamper is activated after 2
                                                                 consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE   (0x00001000U)  /*!< Tamper is activated after 4
+#define RTC_TAMPERFILTER_4SAMPLE   0x00001000U  /*!< Tamper is activated after 4
                                                                 consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE   (0x00001800U)  /*!< Tamper is activated after 8
+#define RTC_TAMPERFILTER_8SAMPLE   0x00001800U  /*!< Tamper is activated after 8
                                                                 consecutive samples at the active level. */
 
 /**
@@ -189,21 +187,21 @@
 /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definition  
   * @{
   */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  (0x00000000U)  /*!< Each of the tamper inputs are sampled
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000U  /*!< Each of the tamper inputs are sampled
                                                                              with a frequency =  RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  (0x00000100U)  /*!< Each of the tamper inputs are sampled
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  0x00000100U  /*!< Each of the tamper inputs are sampled
                                                                              with a frequency =  RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   (0x00000200U)  /*!< Each of the tamper inputs are sampled
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   0x00000200U  /*!< Each of the tamper inputs are sampled
                                                                              with a frequency =  RTCCLK / 8192  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (0x00000300U)  /*!< Each of the tamper inputs are sampled
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   0x00000300U  /*!< Each of the tamper inputs are sampled
                                                                              with a frequency =  RTCCLK / 4096  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   (0x00000400U)  /*!< Each of the tamper inputs are sampled
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   0x00000400U  /*!< Each of the tamper inputs are sampled
                                                                              with a frequency =  RTCCLK / 2048  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (0x00000500U)  /*!< Each of the tamper inputs are sampled
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   0x00000500U  /*!< Each of the tamper inputs are sampled
                                                                              with a frequency =  RTCCLK / 1024  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (0x00000600U)  /*!< Each of the tamper inputs are sampled
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    0x00000600U  /*!< Each of the tamper inputs are sampled
                                                                              with a frequency =  RTCCLK / 512   */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    (0x00000700U)  /*!< Each of the tamper inputs are sampled
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    0x00000700U  /*!< Each of the tamper inputs are sampled
                                                                              with a frequency =  RTCCLK / 256   */
 
 /**
@@ -213,13 +211,13 @@
 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definition
   * @{
   */
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK (0x00000000U)  /*!< Tamper pins are pre-charged before
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U  /*!< Tamper pins are pre-charged before
                                                                          sampling during 1 RTCCLK cycle */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK (0x00002000U)  /*!< Tamper pins are pre-charged before
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK 0x00002000U  /*!< Tamper pins are pre-charged before
                                                                          sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK (0x00004000U)  /*!< Tamper pins are pre-charged before
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK 0x00004000U  /*!< Tamper pins are pre-charged before
                                                                          sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (0x00006000U)  /*!< Tamper pins are pre-charged before
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK 0x00006000U  /*!< Tamper pins are pre-charged before
                                                                          sampling during 8 RTCCLK cycles */
 
 /**
@@ -230,7 +228,7 @@
   * @{
   */
 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAFCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE (0x00000000U)        /*!< TimeStamp on Tamper Detection event is not saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U        /*!< TimeStamp on Tamper Detection event is not saved */
 
 /**
   * @}
@@ -239,7 +237,7 @@
 /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definition
   * @{
   */
-#define RTC_TAMPER_PULLUP_ENABLE  (0x00000000U)            /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_ENABLE  0x00000000U            /*!< Tamper pins are pre-charged before sampling */
 #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)   /*!< Tamper pins are not pre-charged before sampling */
 
 /**
@@ -250,12 +248,12 @@
 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definition
   * @{
   */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        (0x00000000U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         (0x00000001U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         (0x00000002U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         (0x00000003U)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      (0x00000004U)
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      (0x00000006U)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        0x00000000U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         0x00000001U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         0x00000002U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         0x00000003U
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      0x00000004U
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      0x00000006U
 
 
 /**
@@ -266,11 +264,11 @@
 /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definition
   * @{
   */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC   (0x00000000U) /*!<  If RTCCLK = 32768 Hz, Smooth calibation
+#define RTC_SMOOTHCALIB_PERIOD_32SEC   0x00000000U /*!<  If RTCCLK = 32768 Hz, Smooth calibation
                                                                     period is 32s,  else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC   (0x00002000U) /*!<  If RTCCLK = 32768 Hz, Smooth calibation
+#define RTC_SMOOTHCALIB_PERIOD_16SEC   0x00002000U /*!<  If RTCCLK = 32768 Hz, Smooth calibation
                                                                     period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC    (0x00004000U) /*!<  If RTCCLK = 32768 Hz, Smooth calibation
+#define RTC_SMOOTHCALIB_PERIOD_8SEC    0x00004000U /*!<  If RTCCLK = 32768 Hz, Smooth calibation
                                                                     period is 8s, else 2exp18 RTCCLK seconds */
 
 /**
@@ -280,10 +278,10 @@
 /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definition
   * @{
   */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET    (0x00008000U) /*!<  The number of RTCCLK pulses added
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET    0x00008000U /*!<  The number of RTCCLK pulses added
                                                                        during a X -second window = Y - CALM[8:0]
                                                                        with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  (0x00000000U) /*!<  The number of RTCCLK pulses subbstited
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  0x00000000U /*!<  The number of RTCCLK pulses subbstited
                                                                        during a 32-second window =   CALM[8:0] */
 
 /**
@@ -292,8 +290,8 @@
  /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
   * @{
   */
-#define RTC_CALIBOUTPUT_512HZ            (0x00000000U)
-#define RTC_CALIBOUTPUT_1HZ              (0x00080000U)
+#define RTC_CALIBOUTPUT_512HZ            0x00000000U
+#define RTC_CALIBOUTPUT_1HZ              0x00080000U
 
 /**
   * @}
@@ -302,8 +300,8 @@
 /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definition
   * @{
   */
-#define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000U)
-#define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000U)
+#define RTC_SHIFTADD1S_RESET      0x00000000U
+#define RTC_SHIFTADD1S_SET        0x80000000U
 
 /**
   * @}
@@ -325,22 +323,22 @@
 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
 /**
   * @brief  Enable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
 
 /**
   * @brief  Disable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
 
 /**
   * @brief  Enable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
   *         This parameter can be:
   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
   * @retval None
@@ -349,8 +347,8 @@
 
 /**
   * @brief  Disable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
   *         This parameter can be:
   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
   * @retval None
@@ -359,8 +357,8 @@
 
 /**
   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
   *         This parameter can be:
   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
   * @retval None
@@ -369,8 +367,8 @@
 
 /**
   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
   *         This parameter can be:
   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
   * @retval None
@@ -379,8 +377,8 @@
 
 /**
   * @brief  Get the selected RTC WakeUpTimer's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
   *          This parameter can be:
   *             @arg RTC_FLAG_WUTF
   *             @arg RTC_FLAG_WUTWF
@@ -390,8 +388,8 @@
 
 /**
   * @brief  Clear the RTC Wake Up timer's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
   *         This parameter can be:
   *            @arg RTC_FLAG_WUTF
   * @retval None
@@ -489,22 +487,22 @@
   */
 /**
   * @brief  Enable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                        ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
 
 /**
   * @brief  Disable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
 
 /**
   * @brief  Enable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -513,8 +511,8 @@
 
 /**
   * @brief  Disable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. 
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. 
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -523,8 +521,8 @@
 
 /**
   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -533,8 +531,8 @@
 
 /**
   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -543,8 +541,8 @@
 
 /**
   * @brief  Get the selected RTC TimeStamp's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
   *         This parameter can be:
   *            @arg RTC_FLAG_TSF   
   *            @arg RTC_FLAG_TSOVF     
@@ -554,8 +552,8 @@
 
 /**
   * @brief  Clear the RTC Time Stamp's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag to clear.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Alarm Flag to clear.
   *          This parameter can be:
   *             @arg RTC_FLAG_TSF  
   * @retval None
@@ -573,28 +571,28 @@
 
 /**
   * @brief  Enable the RTC Tamper1 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
 
 /**
   * @brief  Disable the RTC Tamper1 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
 
 /**
   * @brief  Enable the RTC Tamper2 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
 
 /**
   * @brief  Disable the RTC Tamper2 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
@@ -602,14 +600,14 @@
 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
 /**
   * @brief  Enable the RTC Tamper3 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E))
 
 /**
   * @brief  Disable the RTC Tamper3 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E))
@@ -617,8 +615,8 @@
 #endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
 /**
   * @brief  Enable the RTC Tamper interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
   *          This parameter can be any combination of the following values:
   *            @arg RTC_IT_TAMP: Tamper interrupt
   * @retval None
@@ -627,8 +625,8 @@
 
 /**
   * @brief  Disable the RTC Tamper interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. 
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. 
   *         This parameter can be any combination of the following values:
   *            @arg RTC_IT_TAMP: Tamper interrupt
   * @retval None
@@ -638,8 +636,8 @@
 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
 /**
   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
   *         This parameter can be:
   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
@@ -651,8 +649,8 @@
 
 /**
   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
   *         This parameter can be:
   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
@@ -664,8 +662,8 @@
 
 /**
   * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
   *         This parameter can be:
   *            @arg RTC_IT_TAMP: Tamper interrupt
   * @retval None
@@ -675,8 +673,8 @@
 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
 /**
   * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag is pending or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.
   *          This parameter can be:
   *             @arg RTC_FLAG_TAMP1F 
   *             @arg RTC_FLAG_TAMP2F
@@ -688,8 +686,8 @@
 
 /**
   * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag to clear.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
   *          This parameter can be:
   *             @arg RTC_FLAG_TAMP1F
   *             @arg RTC_FLAG_TAMP2F
@@ -702,8 +700,8 @@
 
 /**
   * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag is pending or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.
   *          This parameter can be:
   *             @arg RTC_FLAG_TAMP1F 
   *             @arg RTC_FLAG_TAMP2F  
@@ -714,8 +712,8 @@
 
 /**
   * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag to clear.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
   *          This parameter can be:
   *             @arg RTC_FLAG_TAMP1F
   *             @arg RTC_FLAG_TAMP2F 
@@ -824,36 +822,36 @@
 
 /**
   * @brief  Enable the RTC calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
 
 /**
   * @brief  Disable the calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
 
 /**
   * @brief  Enable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
 
 /**
   * @brief  Disable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
 
 /**
   * @brief  Get the selected RTC shift operation's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.
   *          This parameter can be:
   *             @arg RTC_FLAG_SHPF   
   * @retval None

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_smartcard.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   SMARTCARD HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the SMARTCARD peripheral:
@@ -1300,7 +1298,7 @@
 
 /**
   * @brief Handle SMARTCARD interrupt requests.
-  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                    the configuration information for the specified SMARTCARD module.
   * @retval None
   */
@@ -1664,7 +1662,7 @@
 
 /**
   * @brief Configure the SMARTCARD associated USART peripheral.
-  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                    the configuration information for the specified SMARTCARD module.
   * @retval HAL status
   */
@@ -1759,7 +1757,7 @@
 
 /**
   * @brief Configure the SMARTCARD associated USART peripheral advanced features.
-  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                    the configuration information for the specified SMARTCARD module.
   * @retval None
   */
@@ -1821,7 +1819,7 @@
 
 /**
   * @brief Check the SMARTCARD Idle State.
-  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                    the configuration information for the specified SMARTCARD module.
   * @retval HAL status
   */
@@ -2169,7 +2167,7 @@
 
 /**
   * @brief Send an amount of data in non-blocking mode.
-  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for the specified SMARTCARD module.
   *         Function called under interruption only, once
   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
@@ -2242,7 +2240,7 @@
 
 /**
   * @brief Receive an amount of data in non-blocking mode.
-  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for the specified SMARTCARD module.
   *         Function called under interruption only, once
   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT().

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_smartcard.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of SMARTCARD HAL module.
   ******************************************************************************
   * @attention
@@ -581,27 +579,27 @@
   */
 
 /** @brief  Reset SMARTCARD handle states.
-  * @param  __HANDLE__: SMARTCARD handle.
+  * @param  __HANDLE__ SMARTCARD handle.
   * @retval None
   */
 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
-                                                          } while(0)
+                                                          } while(0U)
 
 /** @brief  Flush the Smartcard Data registers.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
   */
 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                                 \
     do{                                                                              \
       SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
       SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
-      } while(0)
+      } while(0U)
 
 /** @brief  Clear the specified SMARTCARD pending flag.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
@@ -616,39 +614,39 @@
 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
 
 /** @brief  Clear the SMARTCARD PE pending flag.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
 
 
 /** @brief  Clear the SMARTCARD FE pending flag.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
 
 /** @brief  Clear the SMARTCARD NE pending flag.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
 
 /** @brief  Clear the SMARTCARD ORE pending flag.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
 
 /** @brief  Clear the SMARTCARD IDLE pending flag.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
 
 /** @brief  Check whether the specified Smartcard flag is set or not.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
   *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
@@ -669,8 +667,8 @@
 
 
 /** @brief  Enable the specified SmartCard interrupt.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
   *          This parameter can be one of the following values:
   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
@@ -682,13 +680,13 @@
   *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
   * @retval None
   */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
-                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                 ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
 
 /** @brief  Disable the specified SmartCard interrupt.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
   *          This parameter can be one of the following values:
   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
@@ -700,14 +698,14 @@
   *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
   * @retval None
   */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
-                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                 ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
 
 
 /** @brief  Check whether the specified SmartCard interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __IT__: specifies the SMARTCARD interrupt to check.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __IT__ specifies the SMARTCARD interrupt to check.
   *          This parameter can be one of the following values:
   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
@@ -724,8 +722,8 @@
 #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
 
 /** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __IT__: specifies the SMARTCARD interrupt source to check.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __IT__ specifies the SMARTCARD interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
@@ -737,14 +735,14 @@
   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \
-                                                           (((((uint8_t)(__IT__)) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((__IT__) & 0xFFU) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \
+                                                           (((((__IT__) & 0xFFU) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \
                                                            (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
 
 
 /** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
   *                       to clear the corresponding interrupt.
   *          This parameter can be one of the following values:
   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
@@ -760,8 +758,8 @@
 #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
 
 /** @brief  Set a specific SMARTCARD request flag.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __REQ__: specifies the request flag to set
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __REQ__ specifies the request flag to set
   *          This parameter can be one of the following values:
   *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
   *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
@@ -771,25 +769,25 @@
 #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
 
 /** @brief  Enable the SMARTCARD one bit sample method.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.  
   * @retval None
   */     
 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
 /** @brief  Disable the SMARTCARD one bit sample method.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.  
   * @retval None
   */      
 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable the USART associated to the SMARTCARD Handle.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
   */
 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
   */
 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
@@ -806,42 +804,42 @@
 /** @brief  Check the Baud rate range. 
   * @note   The maximum Baud Rate is derived from the maximum clock on F0 (48 MHz)
   *         divided by the oversampling used on the SMARTCARD (i.e. 16).
-  * @param  __BAUDRATE__: Baud rate set by the configuration function.
+  * @param  __BAUDRATE__ Baud rate set by the configuration function.
   * @retval Test result (TRUE or FALSE)
   */
 #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 3000001U)
 
 /** @brief  Check the block length range.
   * @note   The maximum SMARTCARD block length is 0xFF.
-  * @param  __LENGTH__: block length.
+  * @param  __LENGTH__ block length.
   * @retval Test result (TRUE or FALSE)
   */
 #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
 
 /** @brief  Check the receiver timeout value. 
   * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
-  * @param  __TIMEOUTVALUE__: receiver timeout value.
+  * @param  __TIMEOUTVALUE__ receiver timeout value.
   * @retval Test result (TRUE or FALSE)
   */
 #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
 
 /** @brief  Check the SMARTCARD autoretry counter value. 
   * @note   The maximum number of retransmissions is 0x7.
-  * @param  __COUNT__: number of retransmissions.
+  * @param  __COUNT__ number of retransmissions.
   * @retval Test result (TRUE or FALSE)
   */
 #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)
 
 /**
   * @brief Ensure that SMARTCARD frame length is valid.
-  * @param __LENGTH__: SMARTCARD frame length. 
+  * @param __LENGTH__ SMARTCARD frame length. 
   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
   */ 
 #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
 
 /**
   * @brief Ensure that SMARTCARD frame number of stop bits is valid.
-  * @param __STOPBITS__: SMARTCARD frame number of stop bits. 
+  * @param __STOPBITS__ SMARTCARD frame number of stop bits. 
   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
   */ 
 #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
@@ -849,7 +847,7 @@
 
 /**
   * @brief Ensure that SMARTCARD frame parity is valid.
-  * @param __PARITY__: SMARTCARD frame parity. 
+  * @param __PARITY__ SMARTCARD frame parity. 
   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
   */ 
 #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
@@ -857,28 +855,28 @@
 
 /**
   * @brief Ensure that SMARTCARD communication mode is valid.
-  * @param __MODE__: SMARTCARD communication mode. 
+  * @param __MODE__ SMARTCARD communication mode. 
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */ 
 #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U))
 
 /**
   * @brief Ensure that SMARTCARD frame polarity is valid.
-  * @param __CPOL__: SMARTCARD frame polarity. 
+  * @param __CPOL__ SMARTCARD frame polarity. 
   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
   */ 
 #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
 
 /**
   * @brief Ensure that SMARTCARD frame phase is valid.
-  * @param __CPHA__: SMARTCARD frame phase. 
+  * @param __CPHA__ SMARTCARD frame phase. 
   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
   */
 #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
 
 /**
   * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
-  * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting. 
+  * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. 
   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
   */
 #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
@@ -886,7 +884,7 @@
 
 /**
   * @brief Ensure that SMARTCARD frame sampling is valid.
-  * @param __ONEBIT__: SMARTCARD frame sampling. 
+  * @param __ONEBIT__ SMARTCARD frame sampling. 
   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
   */
 #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
@@ -894,7 +892,7 @@
 
 /**
   * @brief Ensure that SMARTCARD NACK transmission setting is valid.
-  * @param __NACK__: SMARTCARD NACK transmission setting. 
+  * @param __NACK__ SMARTCARD NACK transmission setting. 
   * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
   */
 #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
@@ -902,7 +900,7 @@
 
 /**
   * @brief Ensure that SMARTCARD receiver timeout setting is valid.
-  * @param __TIMEOUT__: SMARTCARD receiver timeout setting. 
+  * @param __TIMEOUT__ SMARTCARD receiver timeout setting. 
   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
   */
 #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
@@ -910,7 +908,7 @@
 
 /**
   * @brief Ensure that SMARTCARD advanced features initialization is valid.
-  * @param __INIT__: SMARTCARD advanced features initialization. 
+  * @param __INIT__ SMARTCARD advanced features initialization. 
   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
   */
 #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
@@ -924,7 +922,7 @@
 
 /**
   * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
-  * @param __TXINV__: SMARTCARD frame TX inversion setting. 
+  * @param __TXINV__ SMARTCARD frame TX inversion setting. 
   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
   */
 #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
@@ -932,7 +930,7 @@
 
 /**
   * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
-  * @param __RXINV__: SMARTCARD frame RX inversion setting. 
+  * @param __RXINV__ SMARTCARD frame RX inversion setting. 
   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
   */
 #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
@@ -940,7 +938,7 @@
 
 /**
   * @brief Ensure that SMARTCARD frame data inversion setting is valid.
-  * @param __DATAINV__: SMARTCARD frame data inversion setting. 
+  * @param __DATAINV__ SMARTCARD frame data inversion setting. 
   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
   */
 #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
@@ -948,7 +946,7 @@
 
 /**
   * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
-  * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting. 
+  * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. 
   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
   */
 #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
@@ -956,7 +954,7 @@
 
 /**
   * @brief Ensure that SMARTCARD frame overrun setting is valid.
-  * @param __OVERRUN__: SMARTCARD frame overrun setting. 
+  * @param __OVERRUN__ SMARTCARD frame overrun setting. 
   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
   */
 #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
@@ -964,7 +962,7 @@
 
 /**
   * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
-  * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting. 
+  * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. 
   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
   */
 #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
@@ -972,7 +970,7 @@
 
 /**
   * @brief Ensure that SMARTCARD frame MSB first setting is valid.
-  * @param __MSBFIRST__: SMARTCARD frame MSB first setting. 
+  * @param __MSBFIRST__ SMARTCARD frame MSB first setting. 
   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
   */
 #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
@@ -980,7 +978,7 @@
 
 /**
   * @brief Ensure that SMARTCARD request parameter is valid.
-  * @param __PARAM__: SMARTCARD request parameter. 
+  * @param __PARAM__ SMARTCARD request parameter. 
   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
   */
 #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_smartcard_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   SMARTCARD HAL module driver.
   *          This file provides extended firmware functions to manage the following
   *          functionalities of the SmartCard.
@@ -101,9 +99,9 @@
 
 /**
   * @brief Update on the fly the SMARTCARD block length in RTOR register.
-  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                    the configuration information for the specified SMARTCARD module.
-  * @param BlockLength: SMARTCARD block length (8-bit long at most)
+  * @param BlockLength SMARTCARD block length (8-bit long at most)
   * @retval None
   */
 void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
@@ -113,9 +111,9 @@
 
 /**
   * @brief Update on the fly the receiver timeout value in RTOR register.
-  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                    the configuration information for the specified SMARTCARD module.
-  * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
+  * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
   *                     value must be less or equal to 0x0FFFFFFFF.
   * @retval None
   */
@@ -127,7 +125,7 @@
 
 /**
   * @brief Enable the SMARTCARD receiver timeout feature.
-  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                    the configuration information for the specified SMARTCARD module.
   * @retval HAL status
   */
@@ -159,7 +157,7 @@
 
 /**
   * @brief Disable the SMARTCARD receiver timeout feature.
-  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                    the configuration information for the specified SMARTCARD module.
   * @retval HAL status
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_smartcard_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of SMARTCARD HAL Extended module.
   ******************************************************************************
   * @attention
@@ -65,8 +63,8 @@
   */
   
 /** @brief  Report the SMARTCARD clock source.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __CLOCKSOURCE__: output variable.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __CLOCKSOURCE__ output variable.
   * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
   */
 #if defined(STM32F031x6) || defined(STM32F038xx)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,25 +2,23 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_smbus.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   SMBUS HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the System Management Bus (SMBus) peripheral,
   *          based on I2C principles of operation :
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *           + Peripheral State and Errors functions
-  *         
+  *
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
   ==============================================================================
     [..]
     The SMBUS HAL driver can be used as follows:
-    
+
     (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
-        SMBUS_HandleTypeDef  hsmbus; 
+        SMBUS_HandleTypeDef  hsmbus;
 
     (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
         (##) Enable the SMBUSx interface clock
@@ -28,7 +26,7 @@
             (+++) Enable the clock for the SMBUS GPIOs
             (+++) Configure SMBUS pins as alternate function open-drain
         (##) NVIC configuration if you need to use interrupt process
-            (+++) Configure the SMBUSx interrupt priority 
+            (+++) Configure the SMBUSx interrupt priority
             (+++) Enable the NVIC SMBUS IRQ Channel
 
     (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
@@ -92,7 +90,7 @@
      [..]
        (@) You can refer to the SMBUS HAL driver header file for more useful macros
 
-            
+
   @endverbatim
   ******************************************************************************
   * @attention
@@ -121,8 +119,8 @@
   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
-  ******************************************************************************  
-  */ 
+  ******************************************************************************
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f0xx_hal.h"
@@ -156,7 +154,7 @@
 /**
   * @}
   */
-  
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -170,6 +168,10 @@
 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
 
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
+
 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
 /**
   * @}
@@ -182,19 +184,19 @@
   */
 
 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions 
+ *  @brief    Initialization and Configuration functions
  *
-@verbatim    
+@verbatim
  ===============================================================================
               ##### Initialization and de-initialization functions #####
  ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and 
+    [..]  This subsection provides a set of functions allowing to initialize and
           deinitialize the SMBUSx peripheral:
 
-      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures 
+      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
           all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
 
-      (+) Call the function HAL_SMBUS_Init() to configure the selected device with 
+      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
           the selected configuration:
         (++) Clock Timing
         (++) Bus Timeout
@@ -210,28 +212,31 @@
         (++) Peripheral mode
 
 
-      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration 
-          of the selected SMBUSx peripheral.       
+      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
+          of the selected SMBUSx peripheral.
+
+      (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
+          HAL_SMBUS_ConfigDigitalFilter().
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initialize the SMBUS according to the specified parameters 
+  * @brief  Initialize the SMBUS according to the specified parameters
   *         in the SMBUS_InitTypeDef and initialize the associated handle.
   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
   *                the configuration information for the specified SMBUS.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
-{ 
+{
   /* Check the SMBUS handle allocation */
-  if(hsmbus == NULL)
+  if (hsmbus == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
   assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
@@ -245,7 +250,7 @@
   assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
   assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
 
-  if(hsmbus->State == HAL_SMBUS_STATE_RESET)
+  if (hsmbus->State == HAL_SMBUS_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hsmbus->Lock = HAL_UNLOCKED;
@@ -253,17 +258,17 @@
     /* Init the low level hardware : GPIO, CLOCK, NVIC */
     HAL_SMBUS_MspInit(hsmbus);
   }
-  
+
   hsmbus->State = HAL_SMBUS_STATE_BUSY;
-  
+
   /* Disable the selected SMBUS peripheral */
   __HAL_SMBUS_DISABLE(hsmbus);
-  
-  /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/  
+
+  /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
   /* Configure SMBUSx: Frequency range */
   hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
-  
-  /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/  
+
+  /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
   /* Configure SMBUSx: Bus Timeout  */
   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
@@ -272,10 +277,10 @@
   /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
   /* Configure SMBUSx: Own Address1 and ack own address1 mode */
   hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-  
-  if(hsmbus->Init.OwnAddress1 != 0U)
+
+  if (hsmbus->Init.OwnAddress1 != 0U)
   {
-    if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+    if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
     {
       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
     }
@@ -287,41 +292,41 @@
 
   /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
   /* Configure SMBUSx: Addressing Master mode */
-  if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
+  if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
   {
     hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
   }
   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
   /* AUTOEND and NACK bit will be manage during Transfer process */
   hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-  
-  /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/  
+
+  /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
   /* Configure SMBUSx: Dual mode and Own Address2 */
   hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
 
   /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
   /* Configure SMBUSx: Generalcall and NoStretch mode */
   hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
-  
+
   /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
-  if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
-     && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
+  if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
+      && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
   {
     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
   }
 
   /* Enable the selected SMBUS peripheral */
   __HAL_SMBUS_ENABLE(hsmbus);
-  
+
   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
   hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
   hsmbus->State = HAL_SMBUS_STATE_READY;
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitialize the SMBUS peripheral. 
+  * @brief  DeInitialize the SMBUS peripheral.
   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
   *                the configuration information for the specified SMBUS.
   * @retval HAL status
@@ -329,29 +334,29 @@
 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
 {
   /* Check the SMBUS handle allocation */
-  if(hsmbus == NULL)
+  if (hsmbus == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
-  
+
   hsmbus->State = HAL_SMBUS_STATE_BUSY;
-  
+
   /* Disable the SMBUS Peripheral Clock */
   __HAL_SMBUS_DISABLE(hsmbus);
-  
+
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
   HAL_SMBUS_MspDeInit(hsmbus);
-  
+
   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
   hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
   hsmbus->State = HAL_SMBUS_STATE_RESET;
-  
-   /* Release Lock */
+
+  /* Release Lock */
   __HAL_UNLOCK(hsmbus);
-  
+
   return HAL_OK;
 }
 
@@ -361,14 +366,14 @@
   *                the configuration information for the specified SMBUS.
   * @retval None
   */
- __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsmbus);
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SMBUS_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -377,14 +382,112 @@
   *                the configuration information for the specified SMBUS.
   * @retval None
   */
- __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsmbus);
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SMBUS_MspDeInit could be implemented in the user file
-   */ 
+   */
+}
+
+/**
+  * @brief  Configure Analog noise filter.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  AnalogFilter This parameter can be one of the following values:
+  *         @arg @ref SMBUS_ANALOGFILTER_ENABLE
+  *         @arg @ref SMBUS_ANALOGFILTER_DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Reset ANOFF bit */
+    hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hsmbus->Instance->CR1 |= AnalogFilter;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure Digital noise filter.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Get the old register value */
+    tmpreg = hsmbus->Instance->CR1;
+
+    /* Reset I2C DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
+
+    /* Store the new register value */
+    hsmbus->Instance->CR1 = tmpreg;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
 }
 
 /**
@@ -392,14 +495,14 @@
   */
 
 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- *  @brief   Data transfers functions 
+ *  @brief   Data transfers functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                       ##### IO operation functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to manage the SMBUS data 
+    This subsection provides a set of functions allowing to manage the SMBUS data
     transfers.
 
     (#) Blocking mode function to check if device is ready for usage is :
@@ -408,7 +511,7 @@
     (#) There is only one mode of transfer:
        (++) Non-Blocking mode : The communication is performed using Interrupts.
             These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the 
+            The end of the data processing will be indicated through the
             dedicated SMBUS IRQ when using Interrupt mode.
 
     (#) Non-Blocking mode functions with Interrupt are :
@@ -446,15 +549,15 @@
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{   
+{
   /* Check the parameters */
   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
-  if(hsmbus->State == HAL_SMBUS_STATE_READY)
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hsmbus);
-    
+
     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
     /* Prepare transfer parameters */
@@ -464,12 +567,12 @@
 
     /* In case of Quick command, remove autoend mode */
     /* Manage the stop generation by software */
-    if(hsmbus->pBuffPtr == NULL)
+    if (hsmbus->pBuffPtr == NULL)
     {
       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
     }
 
-    if(Size > MAX_NBYTE_SIZE)
+    if (Size > MAX_NBYTE_SIZE)
     {
       hsmbus->XferSize = MAX_NBYTE_SIZE;
     }
@@ -477,50 +580,54 @@
     {
       hsmbus->XferSize = Size;
     }
-    
+
     /* Send Slave Address */
     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+    if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
     {
-      SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+      SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
     }
     else
     {
       /* If transfer direction not change, do not generate Restart Condition */
       /* Mean Previous state is same as current state */
-      if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
       {
-        SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+        SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
       }
       /* Else transfer direction change, so generate Restart with new transfer direction */
       else
       {
-        SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+        /* Convert OTHER_xxx XferOptions if any */
+        SMBUS_ConvertOtherXferOptions(hsmbus);
+
+        /* Handle Transfer */
+        SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
       }
 
       /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
-      if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+      if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
       {
         hsmbus->XferSize--;
         hsmbus->XferCount--;
       }
     }
-    
+
     /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus); 
+    __HAL_UNLOCK(hsmbus);
 
-    /* Note : The SMBUS interrupts must be enabled after unlocking current process 
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
               to avoid the risk of SMBUS interrupt handle execution before current
               process unlock */
     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
-    
+
     return HAL_OK;
   }
   else
   {
     return HAL_BUSY;
-  } 
+  }
 }
 
 /**
@@ -539,27 +646,27 @@
   /* Check the parameters */
   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
-  if(hsmbus->State == HAL_SMBUS_STATE_READY)
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hsmbus);
-    
+
     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-    
+
     /* Prepare transfer parameters */
     hsmbus->pBuffPtr = pData;
     hsmbus->XferCount = Size;
     hsmbus->XferOptions = XferOptions;
-    
+
     /* In case of Quick command, remove autoend mode */
     /* Manage the stop generation by software */
-    if(hsmbus->pBuffPtr == NULL)
+    if (hsmbus->pBuffPtr == NULL)
     {
       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
     }
-    
-    if(Size > MAX_NBYTE_SIZE)
+
+    if (Size > MAX_NBYTE_SIZE)
     {
       hsmbus->XferSize = MAX_NBYTE_SIZE;
     }
@@ -567,42 +674,46 @@
     {
       hsmbus->XferSize = Size;
     }
-    
+
     /* Send Slave Address */
     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+    if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
     {
-      SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+      SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
     }
     else
     {
       /* If transfer direction not change, do not generate Restart Condition */
       /* Mean Previous state is same as current state */
-      if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
       {
-        SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+        SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
       }
       /* Else transfer direction change, so generate Restart with new transfer direction */
       else
       {
-        SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+        /* Convert OTHER_xxx XferOptions if any */
+        SMBUS_ConvertOtherXferOptions(hsmbus);
+
+        /* Handle Transfer */
+        SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
       }
     }
-    
+
     /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus); 
+    __HAL_UNLOCK(hsmbus);
 
-    /* Note : The SMBUS interrupts must be enabled after unlocking current process 
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
               to avoid the risk of SMBUS interrupt handle execution before current
               process unlock */
     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
-    
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
-  } 
+    return HAL_BUSY;
+  }
 }
 
 /**
@@ -616,18 +727,18 @@
   */
 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
 {
-  if(hsmbus->State == HAL_SMBUS_STATE_READY)
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hsmbus);
-    
+
     /* Keep the same state as previous */
     /* to perform as well the call of the corresponding end of transfer callback */
-    if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
     {
       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
     }
-    else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
     {
       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
     }
@@ -638,32 +749,32 @@
       return HAL_ERROR;
     }
     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-    
+
     /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
     SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
-    
+
     /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus); 
+    __HAL_UNLOCK(hsmbus);
 
-    /* Note : The SMBUS interrupts must be enabled after unlocking current process 
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
               to avoid the risk of SMBUS interrupt handle execution before current
               process unlock */
-    if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
     {
       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
     }
-    else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
     {
       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
     }
-    
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
-  } 
+    return HAL_BUSY;
+  }
 }
 
 /**
@@ -680,11 +791,11 @@
   /* Check the parameters */
   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
-  if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+  if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
   {
-    if((pData == NULL) || (Size == 0U)) 
+    if ((pData == NULL) || (Size == 0U))
     {
-      return  HAL_ERROR;                                    
+      return  HAL_ERROR;
     }
 
     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
@@ -692,10 +803,10 @@
 
     /* Process Locked */
     __HAL_LOCK(hsmbus);
-    
+
     hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-    
+
     /* Set SBC bit to manage Acknowledge at each bit */
     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
 
@@ -704,11 +815,13 @@
 
     /* Prepare transfer parameters */
     hsmbus->pBuffPtr = pData;
-    hsmbus->XferSize = Size;
     hsmbus->XferCount = Size;
     hsmbus->XferOptions = XferOptions;
 
-    if(Size > MAX_NBYTE_SIZE)
+    /* Convert OTHER_xxx XferOptions if any */
+    SMBUS_ConvertOtherXferOptions(hsmbus);
+
+    if (Size > MAX_NBYTE_SIZE)
     {
       hsmbus->XferSize = MAX_NBYTE_SIZE;
     }
@@ -718,32 +831,32 @@
     }
 
     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+    if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
     {
-      SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+      SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
     }
     else
     {
       /* Set NBYTE to transmit */
-      SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+      SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
 
       /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
-      if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+      if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
       {
         hsmbus->XferSize--;
         hsmbus->XferCount--;
       }
     }
-    
+
     /* Clear ADDR flag after prepare the transfer parameters */
     /* This action will generate an acknowledge to the HOST */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
 
     /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus); 
+    __HAL_UNLOCK(hsmbus);
 
-    /* Note : The SMBUS interrupts must be enabled after unlocking current process 
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
               to avoid the risk of SMBUS interrupt handle execution before current
               process unlock */
     /* REnable ADDR interrupt */
@@ -753,8 +866,8 @@
   }
   else
   {
-    return HAL_ERROR; 
-  } 
+    return HAL_ERROR;
+  }
 }
 
 /**
@@ -771,22 +884,22 @@
   /* Check the parameters */
   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
-  if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+  if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
   {
-    if((pData == NULL) || (Size == 0U)) 
+    if ((pData == NULL) || (Size == 0U))
     {
-      return  HAL_ERROR;                                    
+      return  HAL_ERROR;
     }
-    
+
     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
 
     /* Process Locked */
     __HAL_LOCK(hsmbus);
-    
+
     hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-    
+
     /* Set SBC bit to manage Acknowledge at each bit */
     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
 
@@ -798,13 +911,16 @@
     hsmbus->XferSize = Size;
     hsmbus->XferCount = Size;
     hsmbus->XferOptions = XferOptions;
-    
+
+    /* Convert OTHER_xxx XferOptions if any */
+    SMBUS_ConvertOtherXferOptions(hsmbus);
+
     /* Set NBYTE to receive */
     /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
     /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
     /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
     /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
-    if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+    if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
     {
       SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
     }
@@ -815,12 +931,12 @@
 
     /* Clear ADDR flag after prepare the transfer parameters */
     /* This action will generate an acknowledge to the HOST */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
 
     /* Process Unlocked */
-    __HAL_UNLOCK(hsmbus); 
+    __HAL_UNLOCK(hsmbus);
 
-    /* Note : The SMBUS interrupts must be enabled after unlocking current process 
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
               to avoid the risk of SMBUS interrupt handle execution before current
               process unlock */
     /* REnable ADDR interrupt */
@@ -830,7 +946,7 @@
   }
   else
   {
-    return HAL_ERROR; 
+    return HAL_ERROR;
   }
 }
 
@@ -843,10 +959,10 @@
 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
 {
   hsmbus->State = HAL_SMBUS_STATE_LISTEN;
-  
+
   /* Enable the Address Match interrupt */
   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
-  
+
   return HAL_OK;
 }
 
@@ -859,13 +975,13 @@
 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
 {
   /* Disable Address listen mode only if a transfer is not ongoing */
-  if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+  if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
   {
     hsmbus->State = HAL_SMBUS_STATE_READY;
-  
+
     /* Disable the Address Match interrupt */
     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
-  
+
     return HAL_OK;
   }
   else
@@ -883,7 +999,7 @@
 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
 {
   /* Enable SMBus alert */
-  hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;   
+  hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
 
   /* Clear ALERT flag */
   __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
@@ -891,7 +1007,7 @@
   /* Enable Alert Interrupt */
   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
 
-  return HAL_OK; 
+  return HAL_OK;
 }
 /**
   * @brief  Disable the SMBUS alert mode with Interrupt.
@@ -902,16 +1018,16 @@
 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
 {
   /* Enable SMBus alert */
-  hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;   
-  
+  hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
+
   /* Disable Alert Interrupt */
   SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
 
-  return HAL_OK; 
+  return HAL_OK;
 }
 
 /**
-  * @brief  Check if target device is ready for communication. 
+  * @brief  Check if target device is ready for communication.
   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
   *                the configuration information for the specified SMBUS.
   * @param  DevAddress Target device address: The device 7 bits address value
@@ -921,72 +1037,72 @@
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{  
+{
   uint32_t tickstart = 0U;
-  
+
   __IO uint32_t SMBUS_Trials = 0U;
- 
-  if(hsmbus->State == HAL_SMBUS_STATE_READY)
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
   {
-    if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+    if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
     {
       return HAL_BUSY;
     }
 
     /* Process Locked */
     __HAL_LOCK(hsmbus);
-    
+
     hsmbus->State = HAL_SMBUS_STATE_BUSY;
     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-    
+
     do
     {
       /* Generate Start */
-      hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
-      
+      hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
+
       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
       /* Wait until STOPF flag is set or a NACK flag is set*/
       tickstart = HAL_GetTick();
-      while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
+      while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
       {
-        if(Timeout != HAL_MAX_DELAY)
-        {    
-          if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
           {
             /* Device is ready */
             hsmbus->State = HAL_SMBUS_STATE_READY;
-        
+
             /* Process Unlocked */
             __HAL_UNLOCK(hsmbus);
             return HAL_TIMEOUT;
           }
-        } 
+        }
       }
-      
+
       /* Check if the NACKF flag has not been set */
       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
       {
-        /* Wait until STOPF flag is reset */ 
-        if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)      
+        /* Wait until STOPF flag is reset */
+        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
-        
+
         /* Clear STOP Flag */
         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
 
         /* Device is ready */
         hsmbus->State = HAL_SMBUS_STATE_READY;
-        
+
         /* Process Unlocked */
         __HAL_UNLOCK(hsmbus);
-        
+
         return HAL_OK;
       }
       else
       {
-        /* Wait until STOPF flag is reset */ 
-        if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)      
+        /* Wait until STOPF flag is reset */
+        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -997,31 +1113,32 @@
         /* Clear STOP Flag, auto generated with autoend*/
         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
       }
-      
+
       /* Check if the maximum allowed number of trials has been reached */
       if (SMBUS_Trials++ == Trials)
       {
         /* Generate Stop */
         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
-        
-        /* Wait until STOPF flag is reset */ 
-        if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)      
+
+        /* Wait until STOPF flag is reset */
+        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
-        
+
         /* Clear STOP Flag */
         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-      }      
-    }while(SMBUS_Trials < Trials);
+      }
+    }
+    while (SMBUS_Trials < Trials);
 
     hsmbus->State = HAL_SMBUS_STATE_READY;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hsmbus);
-        
+
     return HAL_TIMEOUT;
-  }      
+  }
   else
   {
     return HAL_BUSY;
@@ -1044,28 +1161,28 @@
 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
 {
   uint32_t tmpisrvalue = 0U;
-  
+
   /* Use a local variable to store the current ISR flags */
   /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
   tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
-    
+
   /* SMBUS in mode Transmitter ---------------------------------------------------*/
-  if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
-  {     
+  if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+  {
     /* Slave mode selected */
     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
     {
       SMBUS_Slave_ISR(hsmbus);
     }
     /* Master mode selected */
-    else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
     {
       SMBUS_Master_ISR(hsmbus);
     }
   }
-    
+
   /* SMBUS in mode Receiver ----------------------------------------------------*/
-  if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+  if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
   {
     /* Slave mode selected */
     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
@@ -1073,15 +1190,15 @@
       SMBUS_Slave_ISR(hsmbus);
     }
     /* Master mode selected */
-    else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
     {
       SMBUS_Master_ISR(hsmbus);
     }
-  } 
-      
-   /* SMBUS in mode Listener Only --------------------------------------------------*/
+  }
+
+  /* SMBUS in mode Listener Only --------------------------------------------------*/
   if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
-     && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
+      && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
   {
     if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
     {
@@ -1098,79 +1215,7 @@
   */
 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
 {
-  /* SMBUS Bus error interrupt occurred ------------------------------------*/
-  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
-  { 
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
-   
-    /* Clear BERR flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
-  }
-  
-  /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
-  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
-  { 
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
-
-    /* Clear OVR flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
-  }
-
-  /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
-  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
-  { 
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
-
-    /* Clear ARLO flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
-  }
-
-  /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
-  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
-  { 
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
-
-    /* Clear TIMEOUT flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
-  }
-
-  /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
-  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
-  { 
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
-
-    /* Clear ALERT flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
-  }
-
-  /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
-  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
-  { 
-    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
-
-    /* Clear PEC error flag */
-    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
-  }
-  
-  /* Call the Error Callback in case of Error detected */
-  if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
-  {
-    /* Do not Reset the HAL state in case of ALERT error */
-    if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
-    {
-      if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
-         || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
-      {
-        /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
-        /* keep HAL_SMBUS_STATE_LISTEN if set */
-        hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
-        hsmbus->State = HAL_SMBUS_STATE_LISTEN;
-      }
-    }
-    
-    /* Call the Error callback to prevent upper layer */
-    HAL_SMBUS_ErrorCallback(hsmbus);
-  }
+  SMBUS_ITErrorHandler(hsmbus);
 }
 
 /**
@@ -1179,14 +1224,14 @@
   *                the configuration information for the specified SMBUS.
   * @retval None
   */
- __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsmbus);
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -1210,14 +1255,14 @@
   *                the configuration information for the specified SMBUS.
   * @retval None
   */
- __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsmbus);
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -1240,8 +1285,8 @@
   * @brief  Slave Address Match callback.
   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
   *                the configuration information for the specified SMBUS.
-  * @param  TransferDirection: Master request Transfer Direction (Write/Read)
-  * @param  AddrMatchCode: Address Match Code
+  * @param  TransferDirection Master request Transfer Direction (Write/Read)
+  * @param  AddrMatchCode Address Match Code
   * @retval None
   */
 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
@@ -1267,7 +1312,7 @@
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsmbus);
 
-    /* NOTE : This function should not be modified, when the callback is needed,
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
    */
 }
@@ -1278,29 +1323,29 @@
   *                the configuration information for the specified SMBUS.
   * @retval None
   */
- __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsmbus);
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SMBUS_ErrorCallback() could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @}
-  */  
+  */
 
-/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 
- *  @brief   Peripheral State and Errors functions 
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @brief   Peripheral State and Errors functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
             ##### Peripheral State and Errors functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection permit to get in run-time the status of the peripheral 
+    This subsection permits to get in run-time the status of the peripheral
     and the data flow.
 
 @endverbatim
@@ -1332,14 +1377,14 @@
 
 /**
   * @}
-  */  
+  */
 
 /**
   * @}
-  */  
+  */
 
 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
- *  @brief   Data transfers Private functions 
+ *  @brief   Data transfers Private functions
   * @{
   */
 
@@ -1349,42 +1394,45 @@
   *                the configuration information for the specified SMBUS.
   * @retval HAL status
   */
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) 
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
 {
   uint16_t DevAddress;
 
   /* Process Locked */
   __HAL_LOCK(hsmbus);
-  
-  if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+
+  if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
   {
     /* Clear NACK Flag */
     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-    
+
     /* Set corresponding Error Code */
     /* No need to generate STOP, it is automatically done */
     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hsmbus);
-    
-    /* Call the Error callback to prevent upper layer */
+
+    /* Call the Error callback to inform upper layer */
     HAL_SMBUS_ErrorCallback(hsmbus);
   }
-  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
   {
+    /* Check and treat errors if errors occurs during STOP process */
+    SMBUS_ITErrorHandler(hsmbus);
+
     /* Call the corresponding callback to inform upper layer of End of Transfer */
-    if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
     {
       /* Disable Interrupt */
       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
 
       /* Clear STOP Flag */
       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-      
+
       /* Clear Configuration Register 2 */
       SMBUS_RESET_CR2(hsmbus);
-    
+
       /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
       /* Disable the selected SMBUS peripheral */
       __HAL_SMBUS_DISABLE(hsmbus);
@@ -1394,21 +1442,21 @@
 
       /* Process Unlocked */
       __HAL_UNLOCK(hsmbus);
-  
+
       /* REenable the selected SMBUS peripheral */
       __HAL_SMBUS_ENABLE(hsmbus);
 
       HAL_SMBUS_MasterTxCpltCallback(hsmbus);
     }
-    else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
     {
       /* Store Last receive data if any */
-      if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+      if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
       {
         /* Read data from RXDR */
         (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
 
-        if((hsmbus->XferSize > 0U))
+        if ((hsmbus->XferSize > 0U))
         {
           hsmbus->XferSize--;
           hsmbus->XferCount--;
@@ -1420,64 +1468,64 @@
 
       /* Clear STOP Flag */
       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-      
+
       /* Clear Configuration Register 2 */
       SMBUS_RESET_CR2(hsmbus);
-    
+
       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
       hsmbus->State = HAL_SMBUS_STATE_READY;
 
       /* Process Unlocked */
       __HAL_UNLOCK(hsmbus);
-  
+
       HAL_SMBUS_MasterRxCpltCallback(hsmbus);
     }
   }
-  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
-  {  
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+  {
     /* Read data from RXDR */
     (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
     hsmbus->XferSize--;
     hsmbus->XferCount--;
   }
-  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
   {
     /* Write data to TXDR */
     hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
     hsmbus->XferSize--;
-    hsmbus->XferCount--;	
+    hsmbus->XferCount--;
   }
-  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
   {
-    if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
+    if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
     {
       DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
-      
-      if(hsmbus->XferCount > MAX_NBYTE_SIZE)
-      {    
+
+      if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+      {
         SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
         hsmbus->XferSize = MAX_NBYTE_SIZE;
       }
       else
       {
         hsmbus->XferSize = hsmbus->XferCount;
-        SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+        SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
         /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
         /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
-        if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+        if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
         {
           hsmbus->XferSize--;
           hsmbus->XferCount--;
         }
       }
     }
-    else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U))
+    else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U))
     {
       /* Call TxCpltCallback() if no stop mode is set */
-      if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+      if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
       {
         /* Call the corresponding callback to inform upper layer of End of Transfer */
-        if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+        if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
         {
           /* Disable Interrupt */
           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
@@ -1486,10 +1534,10 @@
 
           /* Process Unlocked */
           __HAL_UNLOCK(hsmbus);
-      
+
           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
         }
-        else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+        else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
         {
           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
           hsmbus->PreviousState = hsmbus->State;
@@ -1497,30 +1545,30 @@
 
           /* Process Unlocked */
           __HAL_UNLOCK(hsmbus);
-      
+
           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
         }
       }
     }
   }
-  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
   {
-    if(hsmbus->XferCount == 0U)
+    if (hsmbus->XferCount == 0U)
     {
       /* Specific use case for Quick command */
-      if(hsmbus->pBuffPtr == NULL)
+      if (hsmbus->pBuffPtr == NULL)
       {
         /* Generate a Stop command */
         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
       }
       /* Call TxCpltCallback() if no stop mode is set */
-      else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+      else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
       {
         /* No Generate Stop, to permit restart mode */
         /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
-        
+
         /* Call the corresponding callback to inform upper layer of End of Transfer */
-        if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+        if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
         {
           /* Disable Interrupt */
           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
@@ -1529,10 +1577,10 @@
 
           /* Process Unlocked */
           __HAL_UNLOCK(hsmbus);
-      
+
           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
         }
-        else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+        else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
         {
           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
           hsmbus->PreviousState = hsmbus->State;
@@ -1540,39 +1588,39 @@
 
           /* Process Unlocked */
           __HAL_UNLOCK(hsmbus);
-      
+
           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
         }
       }
     }
   }
-    
+
   /* Process Unlocked */
-  __HAL_UNLOCK(hsmbus); 
-  
-  return HAL_OK; 
-}  
+  __HAL_UNLOCK(hsmbus);
+
+  return HAL_OK;
+}
 /**
   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
   *                the configuration information for the specified SMBUS.
   * @retval HAL status
   */
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) 
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
 {
   uint8_t TransferDirection = 0U;
   uint16_t SlaveAddrCode = 0U;
 
   /* Process Locked */
   __HAL_LOCK(hsmbus);
-  
-  if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+
+  if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
   {
     /* Check that SMBUS transfer finished */
     /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
     /* Mean XferCount == 0*/
     /* So clear Flag NACKF only */
-    if(hsmbus->XferCount == 0U)
+    if (hsmbus->XferCount == 0U)
     {
       /* Clear NACK Flag */
       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
@@ -1594,58 +1642,58 @@
 
       /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
-      
+
       /* Set ErrorCode corresponding to a Non-Acknowledge */
       hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
 
       /* Process Unlocked */
       __HAL_UNLOCK(hsmbus);
-    
-      /* Call the Error callback to prevent upper layer */
+
+      /* Call the Error callback to inform upper layer */
       HAL_SMBUS_ErrorCallback(hsmbus);
     }
   }
-  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
   {
     TransferDirection = SMBUS_GET_DIR(hsmbus);
     SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
-      
+
     /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
     /* Other ADDRInterrupt will be treat in next Listen usecase */
     __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(hsmbus);
 
     /* Call Slave Addr callback */
     HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
   }
-  else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
+  else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
   {
-    if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
     {
       /* Read data from RXDR */
       (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
       hsmbus->XferSize--;
       hsmbus->XferCount--;
 
-      if(hsmbus->XferCount == 1U)
+      if (hsmbus->XferCount == 1U)
       {
         /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
         /* or only the last Byte of Transfer */
         /* So reset the RELOAD bit mode */
         hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
-        SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+        SMBUS_TransferConfig(hsmbus, 0U , 1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
       }
-      else if(hsmbus->XferCount == 0U)
+      else if (hsmbus->XferCount == 0U)
       {
         /* Last Byte is received, disable Interrupt */
         SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
-        
+
         /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
         hsmbus->PreviousState = hsmbus->State;
         hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
-        
+
         /* Process Unlocked */
         __HAL_UNLOCK(hsmbus);
 
@@ -1660,13 +1708,13 @@
         /* Ack last Byte Read */
         hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
       }
-    }    
-    else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+    }
+    else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
     {
-      if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
+      if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
       {
-        if(hsmbus->XferCount > MAX_NBYTE_SIZE)
-        {    
+        if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+        {
           SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
           hsmbus->XferSize = MAX_NBYTE_SIZE;
         }
@@ -1676,7 +1724,7 @@
           SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
           /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
           /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
-          if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+          if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
           {
             hsmbus->XferSize--;
             hsmbus->XferCount--;
@@ -1685,21 +1733,21 @@
       }
     }
   }
-  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
   {
     /* Write data to TXDR only if XferCount not reach "0" */
     /* A TXIS flag can be set, during STOP treatment      */
     /* Check if all Data have already been sent */
     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
-    if(hsmbus->XferCount > 0U)
+    if (hsmbus->XferCount > 0U)
     {
       /* Write data to TXDR */
       hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
       hsmbus->XferCount--;
       hsmbus->XferSize--;
     }
-    
-    if(hsmbus->XferCount == 0U)
+
+    if (hsmbus->XferCount == 0U)
     {
       /* Last Byte is Transmitted */
       /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
@@ -1716,17 +1764,17 @@
   }
 
   /* Check if STOPF is set */
-  if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+  if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
   {
-    if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+    if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
     {
       /* Store Last receive data if any */
-      if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+      if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
       {
         /* Read data from RXDR */
         (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
 
-        if((hsmbus->XferSize > 0U))
+        if ((hsmbus->XferSize > 0U))
         {
           hsmbus->XferSize--;
           hsmbus->XferCount--;
@@ -1744,30 +1792,30 @@
 
       /* Clear Configuration Register 2 */
       SMBUS_RESET_CR2(hsmbus);
-    
+
       /* Clear STOP Flag */
       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
 
-     /* Clear ADDR flag */
-     __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+      /* Clear ADDR flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
 
       hsmbus->XferOptions = 0U;
       hsmbus->PreviousState = hsmbus->State;
       hsmbus->State = HAL_SMBUS_STATE_READY;
-    
+
       /* Process Unlocked */
       __HAL_UNLOCK(hsmbus);
 
-      /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
+      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
       HAL_SMBUS_ListenCpltCallback(hsmbus);
     }
   }
 
   /* Process Unlocked */
   __HAL_UNLOCK(hsmbus);
-  
-  return HAL_OK;     
-}  
+
+  return HAL_OK;
+}
 /**
   * @brief  Manage the enabling of Interrupts.
   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
@@ -1775,40 +1823,40 @@
   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
   * @retval HAL status
   */
-static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) 
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
 {
   uint32_t tmpisr = 0U;
 
-  if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+  if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
   {
     /* Enable ERR interrupt */
     tmpisr |= SMBUS_IT_ERRI;
   }
-  
-  if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+
+  if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
   {
     /* Enable ADDR, STOP interrupt */
     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
   }
-  
-  if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+
+  if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
   {
     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
   }
-  
-  if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+
+  if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
   {
     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
   }
-  
+
   /* Enable interrupts only at the end */
   /* to avoid the risk of SMBUS interrupt handle execution before */
   /* all interrupts requested done */
   __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
 
-  return HAL_OK;     
+  return HAL_OK;
 }
 /**
   * @brief  Manage the disabling of Interrupts.
@@ -1817,60 +1865,60 @@
   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
   * @retval HAL status
   */
-static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) 
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
 {
   uint32_t tmpisr = 0U;
 
-  if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
+  if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY))
   {
     /* Disable ERR interrupt */
     tmpisr |= SMBUS_IT_ERRI;
   }
-  
-  if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+
+  if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
   {
     /* Disable TC, STOP, NACK, TXI interrupt */
     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
-    
-    if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
-       && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+
+    if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+        && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
     {
       /* Disable ERR interrupt */
       tmpisr |= SMBUS_IT_ERRI;
     }
-    
-    if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+
+    if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
     {
       /* Disable STOPI, NACKI */
       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
     }
   }
-  
-  if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+
+  if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
   {
     /* Disable TC, STOP, NACK, RXI interrupt */
     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
-    
-    if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
-       && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+
+    if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+        && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
     {
       /* Disable ERR interrupt */
       tmpisr |= SMBUS_IT_ERRI;
     }
 
-    if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+    if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
     {
       /* Disable STOPI, NACKI */
       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
     }
   }
-  
-  if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+
+  if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
   {
     /* Enable ADDR, STOP interrupt */
     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
 
-    if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) 
+    if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
     {
       /* Disable ERR interrupt */
       tmpisr |= SMBUS_IT_ERRI;
@@ -1881,9 +1929,95 @@
   /* to avoid a breaking situation like at "t" time */
   /* all disable interrupts request are not done */
   __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
-  
+
   return HAL_OK;
 }
+
+/**
+  * @brief  SMBUS interrupts error handler.
+  * @param  hsmbus SMBUS handle.
+  * @retval None
+  */
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+  uint32_t itflags   = READ_REG(hsmbus->Instance->ISR);
+  uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
+
+  /* SMBUS Bus error interrupt occurred ------------------------------------*/
+  if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+  }
+
+  /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+  }
+
+  /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+  if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+  }
+
+  /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+  if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+    /* Clear TIMEOUT flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+  }
+
+  /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+  if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+    /* Clear ALERT flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+  }
+
+  /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+  if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+    /* Clear PEC error flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+  }
+
+  /* Call the Error Callback in case of Error detected */
+  if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
+  {
+    /* Do not Reset the HAL state in case of ALERT error */
+    if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+    {
+      if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+          || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+      {
+        /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+        /* keep HAL_SMBUS_STATE_LISTEN if set */
+        hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+        hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+      }
+    }
+
+    /* Call the Error callback to inform upper layer */
+    HAL_SMBUS_ErrorCallback(hsmbus);
+  }
+}
+
 /**
   * @brief  Handle SMBUS Communication Timeout.
   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
@@ -1893,26 +2027,26 @@
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)  
-{  
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
   uint32_t tickstart = HAL_GetTick();
-  
+
   /* Wait until flag is set */
-  if(Status == RESET)
-  {    
-    while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+  if (Status == RESET)
+  {
+    while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
     {
       /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if (Timeout != HAL_MAX_DELAY)
       {
-        if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+        if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
         {
           hsmbus->PreviousState = hsmbus->State;
-          hsmbus->State= HAL_SMBUS_STATE_READY;
-        
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
           /* Process Unlocked */
           __HAL_UNLOCK(hsmbus);
-        
+
           return HAL_TIMEOUT;
         }
       }
@@ -1920,25 +2054,25 @@
   }
   else
   {
-    while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
+    while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
     {
       /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if (Timeout != HAL_MAX_DELAY)
       {
-        if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+        if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
         {
           hsmbus->PreviousState = hsmbus->State;
-          hsmbus->State= HAL_SMBUS_STATE_READY;
-        
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
           /* Process Unlocked */
           __HAL_UNLOCK(hsmbus);
-        
+
           return HAL_TIMEOUT;
         }
       }
     }
   }
-  return HAL_OK;      
+  return HAL_OK;
 }
 
 /**
@@ -1964,25 +2098,64 @@
 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
 {
   uint32_t tmpreg = 0U;
-  
+
   /* Check the parameters */
   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
   assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
   assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
-    
+
   /* Get the CR2 register value */
   tmpreg = hsmbus->Instance->CR2;
-  
+
   /* clear tmpreg specific bits */
   tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
-  
+
   /* update tmpreg */
-  tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \
-              (uint32_t)Mode | (uint32_t)Request);
-    
+  tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U) & I2C_CR2_NBYTES) | \
+                       (uint32_t)Mode | (uint32_t)Request);
+
   /* update CR2 register */
-  hsmbus->Instance->CR2 = tmpreg;  
-}  
+  hsmbus->Instance->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
+  * @param  hsmbus SMBUS handle.
+  * @retval None
+  */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to SMBUS_FIRST_FRAME                  */
+  if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
+  /* it request implicitly to generate a restart condition      */
+  /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
+  else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
+  /* it request implicitly to generate a restart condition             */
+  /* then generate a stop condition at the end of transfer             */
+  /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
+  else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
+  /* it request implicitly to generate a restart condition               */
+  /* then generate a stop condition at the end of transfer               */
+  /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
+  else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
+  }
+}
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_smbus.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of SMBUS HAL module.
   ******************************************************************************
   * @attention
@@ -40,11 +38,11 @@
 #define __STM32F0xx_HAL_SMBUS_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_hal_def.h"  
+#include "stm32f0xx_hal_def.h"
 
 /** @addtogroup STM32F0xx_HAL_Driver
   * @{
@@ -52,25 +50,25 @@
 
 /** @addtogroup SMBUS
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
   * @{
-  */ 
-  
+  */
+
 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
-  * @brief  SMBUS Configuration Structure definition  
+  * @brief  SMBUS Configuration Structure definition
   * @{
   */
 typedef struct
 {
   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
-                                     This parameter calculated by referring to SMBUS initialization 
+                                     This parameter calculated by referring to SMBUS initialization
                                             section in Reference manual */
   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
                                      This parameter can be a value of @ref SMBUS_Analog_Filter */
-    
+
   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
                                      This parameter can be a 7-bit or 10-bit address. */
 
@@ -99,51 +97,51 @@
                                      This parameter can be a value of @ref SMBUS_peripheral_mode */
 
   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
-  																		(Enable bits and different timeout values)
-                                     This parameter calculated by referring to SMBUS initialization 
+                                      (Enable bits and different timeout values)
+                                     This parameter calculated by referring to SMBUS initialization
                                          section in Reference manual */
 } SMBUS_InitTypeDef;
-/** 
+/**
   * @}
   */
 
 /** @defgroup HAL_state_definition HAL state definition
-  * @brief  HAL State definition  
+  * @brief  HAL State definition
   * @{
-  */ 
+  */
 #define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
 #define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
 #define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
-#define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */ 
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */ 
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
-#define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */  
-#define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */      
+#define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
+#define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
 #define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */
-/** 
+/**
   * @}
   */
 
 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
-  * @brief  SMBUS Error Code definition  
+  * @brief  SMBUS Error Code definition
   * @{
-  */ 
+  */
 #define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
 #define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
-#define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */   
+#define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
 #define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
 #define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
 #define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
 #define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
 #define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
 #define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
-/** 
+/**
   * @}
   */
 
-/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition 
-  * @brief  SMBUS handle Structure definition  
+/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
+  * @brief  SMBUS handle Structure definition
   * @{
   */
 typedef struct
@@ -168,11 +166,11 @@
 
   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
 
-}SMBUS_HandleTypeDef;
+} SMBUS_HandleTypeDef;
 /**
   * @}
   */
-  
+
 /**
   * @}
   */
@@ -292,12 +290,24 @@
   * @{
   */
 
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
 #define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
-#define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE 
+#define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
+#define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
+#define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
+#define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
 /**
   * @}
   */
@@ -328,7 +338,7 @@
   *        Elements values convention: 0xXXXXYYYY
   *           - XXXXXXXX  : Flag mask
   * @{
-  */ 
+  */
 
 #define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
 #define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
@@ -357,8 +367,8 @@
 /* Exported macros ------------------------------------------------------------*/
 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
   * @{
-  */  
-  
+  */
+
 /** @brief  Reset SMBUS handle state.
   * @param  __HANDLE__ specifies the SMBUS Handle.
   * @retval None
@@ -376,7 +386,7 @@
   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
-  *   
+  *
   * @retval None
   */
 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
@@ -392,11 +402,11 @@
   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
-  *   
+  *
   * @retval None
   */
 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
- 
+
 /** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
   * @param  __HANDLE__ specifies the SMBUS Handle.
   * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
@@ -408,7 +418,7 @@
   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
-  *   
+  *
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
@@ -417,69 +427,69 @@
   * @param  __HANDLE__ specifies the SMBUS Handle.
   * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
-  *            @arg @ref SMBUS_FLAG_TXE	    Transmit data register empty
+  *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
   *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
   *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref SMBUS_FLAG_AF 	    NACK received flag
+  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
-  *            @arg @ref SMBUS_FLAG_TC	    Transfer complete (master mode)
-  *            @arg @ref SMBUS_FLAG_TCR	    Transfer complete reload
+  *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
   *            @arg @ref SMBUS_FLAG_BERR    Bus error
   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
-  *            @arg @ref SMBUS_FLAG_OVR	    Overrun/Underrun            
+  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
-  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 
+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
   *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
   *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
-  *   
+  *
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
 #define SMBUS_FLAG_MASK  (0x0001FFFFU)
 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
-    
+
 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
   * @param  __HANDLE__ specifies the SMBUS Handle.
   * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref SMBUS_FLAG_AF 	    NACK received flag
+  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
   *            @arg @ref SMBUS_FLAG_BERR    Bus error
   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
-  *            @arg @ref SMBUS_FLAG_OVR	    Overrun/Underrun            
+  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
-  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 
+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
-  *   
+  *
   * @retval None
   */
 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
- 
+
 /** @brief  Enable the specified SMBUS peripheral.
-  * @param  __HANDLE__ specifies the SMBUS Handle. 
+  * @param  __HANDLE__ specifies the SMBUS Handle.
   * @retval None
   */
 #define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
 
 /** @brief  Disable the specified SMBUS peripheral.
-  * @param  __HANDLE__ specifies the SMBUS Handle. 
+  * @param  __HANDLE__ specifies the SMBUS Handle.
   * @retval None
   */
 #define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
 
 /** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
-  * @param  __HANDLE__ specifies the SMBUS Handle. 
+  * @param  __HANDLE__ specifies the SMBUS Handle.
   * @retval None
   */
 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
 
 /**
   * @}
-  */ 
-  
-  
+  */
+
+
 /* Private constants ---------------------------------------------------------*/
 
 /* Private macros ------------------------------------------------------------*/
@@ -490,6 +500,8 @@
 #define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
                                                           ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
 
+#define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
+
 #define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
                                                           ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
 
@@ -503,7 +515,7 @@
                                                          ((MASK) == SMBUS_OA2_MASK04)    || \
                                                          ((MASK) == SMBUS_OA2_MASK05)    || \
                                                          ((MASK) == SMBUS_OA2_MASK06)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK07))  
+                                                         ((MASK) == SMBUS_OA2_MASK07))
 
 #define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
                                                          ((CALL) == SMBUS_GENERALCALL_ENABLE))
@@ -521,12 +533,13 @@
 #define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \
                                                           ((MODE) == SMBUS_AUTOEND_MODE)                         || \
                                                           ((MODE) == SMBUS_SOFTEND_MODE)                         || \
+                                                          ((MODE) == SMBUS_SENDPEC_MODE)                         || \
                                                           ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
-                               
-                              
+
+
 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
                                                           ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
                                                           ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
@@ -538,7 +551,13 @@
                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
                                                           ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
-                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)               || \
+                                                          IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
+                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
 
 #define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
 #define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
@@ -560,16 +579,7 @@
 
 /**
   * @}
-  */ 
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
-  * @{
   */
-/* Private functions are defined in stm32f0xx_hal_smbus.c file */
-/**
-  * @}
-  */ 
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
@@ -579,12 +589,14 @@
 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
  * @{
  */
-  
+
 /* Initialization and de-initialization functions  **********************************/
 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
 
 /**
   * @}
@@ -593,7 +605,7 @@
 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
  * @{
  */
-    
+
 /* IO operation functions  *****************************************************/
 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
  * @{
@@ -640,7 +652,7 @@
   * @}
   */
 
-/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
  *  @{
  */
 
@@ -654,7 +666,7 @@
 
 /**
   * @}
-  */ 
+  */
 
 /* Private Functions ---------------------------------------------------------*/
 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
@@ -663,23 +675,19 @@
 /* Private functions are defined in stm32f0xx_hal_smbus.c file */
 /**
   * @}
-  */ 
-
-/**
-  * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_spi.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   SPI HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
@@ -60,9 +58,24 @@
           (##) HAL_SPI_DeInit()
           (##) HAL_SPI_Init()
      [..]
-       Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
-       the following table resume the max SPI frequency reached with data size 8bits/16bits,
-       according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+       The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
+       modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
+       maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
+       the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
+
+     [..]
+       Data buffer address alignment restriction:
+      (#) In case more than 1 byte is requested to be transferred, the HAL SPI uses 16-bit access for data buffer.
+          But there is no support for unaligned accesses on the Cortex-M0 processor.
+          So, if the user wants to transfer more than 1 byte, it shall ensure that 16-bit aligned address is used for:
+          (##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT()
+          (##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT()
+      (#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA()
+          and HAL_SPI_TransmitReceive_DMA().
+
+  @endverbatim
+
+  Additional table :
 
        DataSize = SPI_DATASIZE_8BIT:
        +----------------------------------------------------------------------------------------------+
@@ -120,7 +133,6 @@
             (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
             (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
 
-  @endverbatim
   ******************************************************************************
   * @attention
   *
@@ -262,7 +274,7 @@
 /**
   * @brief  Initialize the SPI according to the specified parameters
   *         in the SPI_InitTypeDef and initialize the associated handle.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval HAL status
   */
@@ -349,7 +361,7 @@
 
   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
-  Communication speed, First bit, CRC calculation state */
+  Communication speed, First bit and CRC calculation state */
   WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
                                   hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
                                   hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation));
@@ -361,7 +373,7 @@
   }
 #endif /* USE_SPI_CRC */
 
-  /* Configure : NSS management, TI Mode and Rx Fifo Threshold */
+  /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */
   WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
                                   hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
 
@@ -387,7 +399,7 @@
 
 /**
   * @brief  De-Initialize the SPI peripheral.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval HAL status
   */
@@ -421,7 +433,7 @@
 
 /**
   * @brief  Initialize the SPI MSP.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -437,7 +449,7 @@
 
 /**
   * @brief  De-Initialize the SPI MSP.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -490,11 +502,11 @@
 
 /**
   * @brief  Transmit an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @param  Timeout: Timeout duration
+  * @param  pData pointer to data buffer
+  * @param  Size amount of data to be sent
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -502,6 +514,13 @@
   uint32_t tickstart = 0U;
   HAL_StatusTypeDef errorcode = HAL_OK;
 
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+  {
+    /* in this case, 16-bit access is performed on Data
+       So, check Data is 16-bit aligned address */
+    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
+  }
+
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 
@@ -561,7 +580,7 @@
   /* Transmit data in 16 Bit mode */
   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
   {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
     {
       hspi->Instance->DR = *((uint16_t *)pData);
       pData += sizeof(uint16_t);
@@ -591,7 +610,7 @@
   /* Transmit data in 8 Bit mode */
   else
   {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
     {
       if (hspi->TxXferCount > 1U)
       {
@@ -669,11 +688,11 @@
 
 /**
   * @brief  Receive an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be received
-  * @param  Timeout: Timeout duration
+  * @param  pData pointer to data buffer
+  * @param  Size amount of data to be received
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -684,6 +703,13 @@
   uint32_t tickstart = 0U;
   HAL_StatusTypeDef errorcode = HAL_OK;
 
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+  {
+    /* in this case, 16-bit access is performed on Data
+       So, check Data is 16-bit aligned address */
+    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
+  }
+
   if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
   {
     hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -733,7 +759,7 @@
   }
 #endif /* USE_SPI_CRC */
 
-  /* Set the Rx Fido threshold */
+  /* Set the Rx FiFo threshold */
   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
   {
     /* set fiforxthresold according the reception data length: 16bit */
@@ -899,12 +925,12 @@
 
 /**
   * @brief  Transmit and Receive an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @param  Size: amount of data to be sent and received
-  * @param  Timeout: Timeout duration
+  * @param  pTxData pointer to transmission data buffer
+  * @param  pRxData pointer to reception data buffer
+  * @param  Size amount of data to be sent and received
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
@@ -919,6 +945,14 @@
   uint32_t txallowed = 1U;
   HAL_StatusTypeDef errorcode = HAL_OK;
 
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+  {
+    /* in this case, 16-bit access is performed on Data
+       So, check Data is 16-bit aligned address */
+    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
+    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
+  }
+
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 
@@ -971,8 +1005,8 @@
   }
 #endif /* USE_SPI_CRC */
 
-  /* Set the Rx Fido threshold */
-  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
+  /* Set the Rx Fifo threshold */
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
   {
     /* set fiforxthreshold according the reception data length: 16bit */
     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -1191,16 +1225,23 @@
 
 /**
   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
+  * @param  pData pointer to data buffer
+  * @param  Size amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
   HAL_StatusTypeDef errorcode = HAL_OK;
 
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+  {
+    /* in this case, 16-bit access is performed on Data
+       So, check Data is 16-bit aligned address */
+    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
+  }
+
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 
@@ -1274,16 +1315,23 @@
 
 /**
   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
+  * @param  pData pointer to data buffer
+  * @param  Size amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
   HAL_StatusTypeDef errorcode = HAL_OK;
 
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+  {
+    /* in this case, 16-bit access is performed on Data
+       So, check Data is 16-bit aligned address */
+    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
+  }
+
   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
   {
     hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1319,16 +1367,16 @@
   hspi->TxXferCount = 0U;
   hspi->TxISR       = NULL;
 
-  /* check the data size to adapt Rx threshold and the set the function for IT treatment */
+  /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
   {
-    /* set fiforxthresold according the reception data length: 16 bit */
+    /* Set fiforxthresold according the reception data length: 16 bit */
     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
     hspi->RxISR = SPI_RxISR_16BIT;
   }
   else
   {
-    /* set fiforxthresold according the reception data length: 8 bit */
+    /* Set fiforxthresold according the reception data length: 8 bit */
     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
     hspi->RxISR = SPI_RxISR_8BIT;
   }
@@ -1378,11 +1426,11 @@
 
 /**
   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @param  Size: amount of data to be sent and received
+  * @param  pTxData pointer to transmission data buffer
+  * @param  pRxData pointer to reception data buffer
+  * @param  Size amount of data to be sent and received
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -1390,6 +1438,14 @@
   uint32_t tmp = 0U, tmp1 = 0U;
   HAL_StatusTypeDef errorcode = HAL_OK;
 
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+  {
+    /* in this case, 16-bit access is performed on Data
+       So, check Data is 16-bit aligned address */
+    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
+    assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
+  }
+
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 
@@ -1456,15 +1512,15 @@
   }
 #endif /* USE_SPI_CRC */
 
-  /* check if packing mode is enabled and if there is more than 2 data to receive */
+  /* Check if packing mode is enabled and if there is more than 2 data to receive */
   if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
   {
-    /* set fiforxthresold according the reception data length: 16 bit */
+    /* Set fiforxthresold according the reception data length: 16 bit */
     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
   }
   else
   {
-    /* set fiforxthresold according the reception data length: 8 bit */
+    /* Set fiforxthresold according the reception data length: 8 bit */
     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
   }
 
@@ -1486,16 +1542,19 @@
 
 /**
   * @brief  Transmit an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
+  * @param  pData pointer to data buffer
+  * @param  Size amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
   HAL_StatusTypeDef errorcode = HAL_OK;
 
+  /* check tx dma handle */
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 
@@ -1555,7 +1614,7 @@
   hspi->hdmatx->XferAbortCallback = NULL;
 
   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-  /* packing mode is enabled only if the DMA setting is HALWORD */
+  /* Packing mode is enabled only if the DMA setting is HALWORD */
   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
   {
     /* Check the even/odd of the data size + crc if enabled */
@@ -1595,20 +1654,28 @@
 
 /**
   * @brief  Receive an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
+  * @param  pData pointer to data buffer
   * @note   When the CRC feature is enabled the pData Length must be Size + 1.
-  * @param  Size: amount of data to be sent
+  * @param  Size amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
   HAL_StatusTypeDef errorcode = HAL_OK;
 
+  /* check rx dma handle */
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+
   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
   {
     hspi->State = HAL_SPI_STATE_BUSY_RX;
+
+    /* check tx dma handle */
+    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
     return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
   }
@@ -1656,7 +1723,7 @@
 #endif /* USE_SPI_CRC */
 
 #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6)|| defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
-  /* packing mode management is enabled by the DMA settings */
+  /* Packing mode management is enabled by the DMA settings */
   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
   {
     /* Restriction the DMA data received is not allowed in this mode */
@@ -1668,14 +1735,14 @@
   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
   {
-    /* set fiforxthresold according the reception data length: 16bit */
+    /* Set fiforxthresold according the reception data length: 16bit */
     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
   }
   else
   {
-    /* set fiforxthresold according the reception data length: 8bit */
+    /* Set fiforxthresold according the reception data length: 8bit */
     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-    
+
     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
     {
       /* set fiforxthresold according the reception data length: 16bit */
@@ -1730,12 +1797,12 @@
 
 /**
   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
+  * @param  pTxData pointer to transmission data buffer
+  * @param  pRxData pointer to reception data buffer
   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
-  * @param  Size: amount of data to be sent
+  * @param  Size amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
@@ -1744,6 +1811,10 @@
   uint32_t tmp = 0U, tmp1 = 0U;
   HAL_StatusTypeDef errorcode = HAL_OK;
 
+  /* check rx & tx dma handles */
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 
@@ -1802,18 +1873,19 @@
   }
 #endif
 
+
   /* Reset the threshold bit */
   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
 
-  /* the packing mode management is enabled by the DMA settings according the spi data size */
+  /* The packing mode management is enabled by the DMA settings according the spi data size */
   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
   {
-    /* set fiforxthreshold according the reception data length: 16bit */
+    /* Set fiforxthreshold according the reception data length: 16bit */
     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
   }
   else
   {
-    /* set fiforxthresold according the reception data length: 8bit */
+    /* Set fiforxthresold according the reception data length: 8bit */
     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
 
     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
@@ -1832,7 +1904,7 @@
 
     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
     {
-      /* set fiforxthresold according the reception data length: 16bit */
+      /* Set fiforxthresold according the reception data length: 16bit */
       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
 
       if ((hspi->RxXferCount & 0x1U) == 0x0U)
@@ -1918,25 +1990,46 @@
 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
 {
   HAL_StatusTypeDef errorcode;
+  __IO uint32_t count, resetcount;
 
   /* Initialized local variable  */
   errorcode = HAL_OK;
+  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+  count = resetcount;
 
   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
   {
     hspi->TxISR = SPI_AbortTx_ISR;
-    while (hspi->State != HAL_SPI_STATE_ABORT)
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
     {
+      if (count-- == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
     }
+    while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
   }
 
   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
   {
     hspi->RxISR = SPI_AbortRx_ISR;
-    while (hspi->State != HAL_SPI_STATE_ABORT)
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
     {
+      if (count-- == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
     }
+    while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
   }
 
   /* Clear ERRIE interrupts in case of DMA Mode */
@@ -2052,26 +2145,47 @@
 {
   HAL_StatusTypeDef errorcode;
   uint32_t abortcplt ;
+  __IO uint32_t count, resetcount;
 
   /* Initialized local variable  */
   errorcode = HAL_OK;
   abortcplt = 1U;
+  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+  count = resetcount;
 
   /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
   {
     hspi->TxISR = SPI_AbortTx_ISR;
-    while (hspi->State != HAL_SPI_STATE_ABORT)
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
     {
+      if (count-- == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
     }
+    while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
   }
 
   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
   {
     hspi->RxISR = SPI_AbortRx_ISR;
-    while (hspi->State != HAL_SPI_STATE_ABORT)
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
     {
+      if (count-- == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
     }
+    while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
   }
 
   /* Clear ERRIE interrupts in case of DMA Mode */
@@ -2213,7 +2327,7 @@
 
 /**
   * @brief  Pause the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for the specified SPI module.
   * @retval HAL status
   */
@@ -2233,7 +2347,7 @@
 
 /**
   * @brief  Resume the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for the specified SPI module.
   * @retval HAL status
   */
@@ -2253,7 +2367,7 @@
 
 /**
   * @brief Stop the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for the specified SPI module.
   * @retval HAL status
   */
@@ -2284,7 +2398,7 @@
 
 /**
   * @brief  Handle SPI interrupt request.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for the specified SPI module.
   * @retval None
   */
@@ -2380,7 +2494,7 @@
 
 /**
   * @brief Tx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -2396,7 +2510,7 @@
 
 /**
   * @brief Rx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -2412,7 +2526,7 @@
 
 /**
   * @brief Tx and Rx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -2428,7 +2542,7 @@
 
 /**
   * @brief Tx Half Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -2444,7 +2558,7 @@
 
 /**
   * @brief Rx Half Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -2460,7 +2574,7 @@
 
 /**
   * @brief Tx and Rx Half Transfer callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -2476,7 +2590,7 @@
 
 /**
   * @brief SPI error callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -2529,7 +2643,7 @@
 
 /**
   * @brief  Return the SPI handle state.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval SPI state
   */
@@ -2541,7 +2655,7 @@
 
 /**
   * @brief  Return the SPI error code.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval SPI error code in bitmap format
   */
@@ -2566,7 +2680,7 @@
 
 /**
   * @brief DMA SPI transmit process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA module.
   * @retval None
   */
@@ -2613,7 +2727,7 @@
 
 /**
   * @brief DMA SPI receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA module.
   * @retval None
   */
@@ -2704,7 +2818,7 @@
 
 /**
   * @brief  DMA SPI transmit receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA module.
   * @retval None
   */
@@ -2789,7 +2903,7 @@
 
 /**
   * @brief  DMA SPI half transmit process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA module.
   * @retval None
   */
@@ -2802,7 +2916,7 @@
 
 /**
   * @brief  DMA SPI half receive process complete callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA module.
   * @retval None
   */
@@ -2815,7 +2929,7 @@
 
 /**
   * @brief  DMA SPI half transmit receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA module.
   * @retval None
   */
@@ -2828,7 +2942,7 @@
 
 /**
   * @brief  DMA SPI communication error callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA module.
   * @retval None
   */
@@ -2986,7 +3100,7 @@
 
 /**
   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3036,7 +3150,7 @@
 #if (USE_SPI_CRC != 0U)
 /**
   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3068,7 +3182,7 @@
 
 /**
   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3114,7 +3228,7 @@
 
 /**
   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3148,7 +3262,7 @@
 #if (USE_SPI_CRC != 0U)
 /**
   * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3172,7 +3286,7 @@
 
 /**
   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3210,7 +3324,7 @@
 #if (USE_SPI_CRC != 0U)
 /**
   * @brief  Manage the CRC 8-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3235,7 +3349,7 @@
 
 /**
   * @brief  Manage the receive 8-bit in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3268,7 +3382,7 @@
 #if (USE_SPI_CRC != 0U)
 /**
   * @brief  Manage the CRC 16-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3291,7 +3405,7 @@
 
 /**
   * @brief  Manage the 16-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3324,7 +3438,7 @@
 
 /**
   * @brief  Handle the data 8-bit transmit in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3348,7 +3462,7 @@
 
 /**
   * @brief  Handle the data 16-bit transmit in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3374,12 +3488,12 @@
 
 /**
   * @brief Handle SPI Communication Timeout.
-  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param hspi pointer to a SPI_HandleTypeDef structure that contains
   *              the configuration information for SPI module.
-  * @param Flag: SPI flag to check
-  * @param State: flag state to check
-  * @param Timeout: Timeout duration
-  * @param Tickstart: tick start value
+  * @param Flag SPI flag to check
+  * @param State flag state to check
+  * @param Timeout Timeout duration
+  * @param Tickstart tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
@@ -3426,12 +3540,12 @@
 
 /**
   * @brief Handle SPI FIFO Communication Timeout.
-  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param hspi pointer to a SPI_HandleTypeDef structure that contains
   *              the configuration information for SPI module.
-  * @param Fifo: Fifo to check
-  * @param State: Fifo state to check
-  * @param Timeout: Timeout duration
-  * @param Tickstart: tick start value
+  * @param Fifo Fifo to check
+  * @param State Fifo state to check
+  * @param Timeout Timeout duration
+  * @param Tickstart tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
@@ -3487,10 +3601,10 @@
 
 /**
   * @brief  Handle the check of the RX transaction complete.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
-  * @param  Timeout: Timeout duration
-  * @param  Tickstart: tick start value
+  * @param  Timeout Timeout duration
+  * @param  Tickstart tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
@@ -3524,9 +3638,9 @@
 
 /**
   * @brief  Handle the check of the RXTX or TX transaction complete.
-  * @param  hspi: SPI handle
-  * @param  Timeout: Timeout duration
-  * @param  Tickstart: tick start value
+  * @param  hspi SPI handle
+  * @param  Timeout Timeout duration
+  * @param  Tickstart tick start value
   * @retval HAL status
   */
 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
@@ -3537,18 +3651,26 @@
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
     return HAL_TIMEOUT;
   }
+
   /* Control the BSY flag */
   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
   {
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
     return HAL_TIMEOUT;
   }
+
+  /* Control if the RX fifo is empty */
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    return HAL_TIMEOUT;
+  }
   return HAL_OK;
 }
 
 /**
   * @brief  Handle the end of the RXTX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3605,7 +3727,7 @@
 
 /**
   * @brief  Handle the end of the RX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3647,7 +3769,7 @@
 
 /**
   * @brief  Handle the end of the TX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
@@ -3686,21 +3808,32 @@
 
 /**
   * @brief  Handle abort a Rx transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
 {
+  __IO uint32_t count;
+
   /* Disable SPI Peripheral */
   __HAL_SPI_DISABLE(hspi);
 
+  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
 
-  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+  /* Check RXNEIE is disabled */
+  do
   {
+    if (count-- == 0U)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+      break;
+    }
   }
+  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
 
   /* Control the BSY flag */
   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
@@ -3719,18 +3852,29 @@
 
 /**
   * @brief  Handle abort a Tx or Rx/Tx transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval None
   */
 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
 {
+  __IO uint32_t count;
+
+  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
 
-  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+  /* Check TXEIE is disabled */
+  do
   {
+    if (count-- == 0U)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+      break;
+    }
   }
+  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
 
   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
   {

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_spi.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of SPI HAL module.
   ******************************************************************************
   * @attention
@@ -99,7 +97,7 @@
                                      This parameter can be a value of @ref SPI_CRC_Calculation */
 
   uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
-                                     This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
+                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
 
   uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
                                      CRC Length is only used with Data8 and Data16, not other data size
@@ -253,7 +251,7 @@
   */
 #define SPI_NSS_SOFT                    SPI_CR1_SSM
 #define SPI_NSS_HARD_INPUT              (0x00000000U)
-#define SPI_NSS_HARD_OUTPUT             (0x00040000U)
+#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
 /**
   * @}
   */
@@ -271,13 +269,13 @@
   * @{
   */
 #define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4         (0x00000008U)
-#define SPI_BAUDRATEPRESCALER_8         (0x00000010U)
-#define SPI_BAUDRATEPRESCALER_16        (0x00000018U)
-#define SPI_BAUDRATEPRESCALER_32        (0x00000020U)
-#define SPI_BAUDRATEPRESCALER_64        (0x00000028U)
-#define SPI_BAUDRATEPRESCALER_128       (0x00000030U)
-#define SPI_BAUDRATEPRESCALER_256       (0x00000038U)
+#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
+#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
 /**
   * @}
   */
@@ -368,10 +366,10 @@
 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
   * @{
   */
-#define SPI_FTLVL_EMPTY           (0x00000000U)
-#define SPI_FTLVL_QUARTER_FULL    (0x00000800U)
-#define SPI_FTLVL_HALF_FULL       (0x00001000U)
-#define SPI_FTLVL_FULL            (0x00001800U)
+#define SPI_FTLVL_EMPTY                 (0x00000000U)
+#define SPI_FTLVL_QUARTER_FULL          (0x00000800U)
+#define SPI_FTLVL_HALF_FULL             (0x00001000U)
+#define SPI_FTLVL_FULL                  (0x00001800U)
 
 /**
   * @}
@@ -380,10 +378,10 @@
 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
   * @{
   */
-#define SPI_FRLVL_EMPTY           (0x00000000U)
-#define SPI_FRLVL_QUARTER_FULL    (0x00000200U)
-#define SPI_FRLVL_HALF_FULL       (0x00000400U)
-#define SPI_FRLVL_FULL            (0x00000600U)
+#define SPI_FRLVL_EMPTY                 (0x00000000U)
+#define SPI_FRLVL_QUARTER_FULL          (0x00000200U)
+#define SPI_FRLVL_HALF_FULL             (0x00000400U)
+#define SPI_FRLVL_FULL                  (0x00000600U)
 /**
   * @}
   */
@@ -391,36 +389,47 @@
 /**
   * @}
   */
-  
+
 /* Exported macros -----------------------------------------------------------*/
 /** @defgroup SPI_Exported_Macros SPI Exported Macros
   * @{
   */
 
 /** @brief  Reset SPI handle state.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
 
-/** @brief  Enable or disable the specified SPI interrupts.
-  * @param  __HANDLE__: specifies the SPI Handle.
+/** @brief  Enable the specified SPI interrupts.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
   *         This parameter can be one of the following values:
   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
   *            @arg SPI_IT_ERR: Error interrupt enable
   * @retval None
   */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief  Disable the specified SPI interrupts.
+  * @param  __HANDLE__ specifies the SPI handle.
+  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
 
 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
+  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
@@ -430,9 +439,9 @@
 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
@@ -448,27 +457,27 @@
 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
 
 /** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)       \
-  do{                                              \
-    __IO uint32_t tmpreg_modf = 0x00U;             \
-    tmpreg_modf = (__HANDLE__)->Instance->SR;      \
-    (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
-    UNUSED(tmpreg_modf);                           \
-  } while(0)
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
+  do{                                                    \
+    __IO uint32_t tmpreg_modf = 0x00U;                   \
+    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
+    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
+    UNUSED(tmpreg_modf);                                 \
+  } while(0U)
 
 /** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
@@ -478,10 +487,10 @@
     tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
     tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
     UNUSED(tmpreg_ovr);                            \
-  } while(0)
+  } while(0U)
 
 /** @brief  Clear the SPI FRE pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
@@ -490,21 +499,21 @@
   __IO uint32_t tmpreg_fre = 0x00U;                \
   tmpreg_fre = (__HANDLE__)->Instance->SR;         \
   UNUSED(tmpreg_fre);                              \
-  }while(0)
+  }while(0U)
 
 /** @brief  Enable the SPI peripheral.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
+#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
 
 /** @brief  Disable the SPI peripheral.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
 
 /**
   * @}
@@ -516,26 +525,26 @@
   */
 
 /** @brief  Set the SPI transmit-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
 
 /** @brief  Set the SPI receive-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
 
 /** @brief  Reset the CRC calculation of the SPI.
-  * @param  __HANDLE__: specifies the SPI Handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
-                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
+                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
 
 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
                            ((MODE) == SPI_MODE_MASTER))
@@ -600,6 +609,10 @@
 
 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
 
+#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
+
+#define IS_SPI_16BIT_ALIGNED_ADDRESS(DATA) (((uint32_t)(DATA) % 2U) == 0U)
+
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_spi_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Extended SPI HAL module driver.
   *          This file provides firmware functions to manage the following
   *          SPI peripheral extended functionalities :
@@ -57,7 +55,7 @@
 /** @defgroup SPIEx_Private_Constants SPIEx Private Constants
   * @{
   */
-#define SPI_FIFO_SIZE       4U
+#define SPI_FIFO_SIZE       4
 /**
   * @}
   */
@@ -72,8 +70,8 @@
   */
 
 /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
- *  @brief   Data transfers functions
- *
+  *  @brief   Data transfers functions
+  *
 @verbatim
   ==============================================================================
                       ##### IO operation functions #####
@@ -91,7 +89,7 @@
 
 /**
   * @brief Flush the RX fifo.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for the specified SPI module.
   * @retval HAL status
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -1,39 +1,37 @@
 /**
- ******************************************************************************
- * @file    stm32f0xx_hal_spi_ex.h
- * @author  MCD Application Team
- * @version V1.5.0
- * @date    04-November-2016
- * @brief   Header file of SPI HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of STMicroelectronics nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
+  ******************************************************************************
+  * @file    stm32f0xx_hal_spi_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SPI HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F0xx_HAL_SPI_EX_H
@@ -56,7 +54,7 @@
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
-/* Exported macros ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup SPIEx_Exported_Functions
   * @{

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_tim.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   TIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Timer (TIM) peripheral:
@@ -199,7 +197,7 @@
 /**
   * @brief  Initializes the TIM Time base Unit according to the specified
   *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim : TIM Base handle
+  * @param  htim TIM Base handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
@@ -239,7 +237,7 @@
 
 /**
   * @brief  DeInitializes the TIM Base peripheral 
-  * @param  htim : TIM Base handle
+  * @param  htim TIM Base handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
@@ -266,7 +264,7 @@
 
 /**
   * @brief  Initializes the TIM Base MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
@@ -281,7 +279,7 @@
 
 /**
   * @brief  DeInitializes TIM Base MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
@@ -297,7 +295,7 @@
 
 /**
   * @brief  Starts the TIM Base generation.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval HAL status
 */
 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
@@ -320,7 +318,7 @@
 
 /**
   * @brief  Stops the TIM Base generation.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval HAL status
 */
 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
@@ -343,7 +341,7 @@
 
 /**
   * @brief  Starts the TIM Base generation in interrupt mode.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval HAL status
 */
 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
@@ -363,7 +361,7 @@
 
 /**
   * @brief  Stops the TIM Base generation in interrupt mode.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval HAL status
 */
 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
@@ -382,9 +380,9 @@
 
 /**
   * @brief  Starts the TIM Base generation in DMA mode.
-  * @param  htim : TIM handle
-  * @param  pData : The source Buffer address.
-  * @param  Length : The length of data to be transferred from memory to peripheral.
+  * @param  htim TIM handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
   * @retval HAL status
 */
 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
@@ -428,7 +426,7 @@
 
 /**
   * @brief  Stops the TIM Base generation in DMA mode.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval HAL status
 */
 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
@@ -477,7 +475,7 @@
 /**
   * @brief  Initializes the TIM Output Compare according to the specified
   *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim : TIM Output Compare handle
+  * @param  htim TIM Output Compare handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
@@ -517,7 +515,7 @@
 
 /**
   * @brief  DeInitializes the TIM peripheral 
-  * @param  htim : TIM Output Compare handle
+  * @param  htim TIM Output Compare handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
@@ -544,7 +542,7 @@
 
 /**
   * @brief  Initializes the TIM Output Compare MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
@@ -559,7 +557,7 @@
 
 /**
   * @brief  DeInitializes TIM Output Compare MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -574,8 +572,8 @@
 
 /**
   * @brief  Starts the TIM Output Compare signal generation.
-  * @param  htim : TIM Output Compare handle 
-  * @param  Channel : TIM Channel to be enabled
+  * @param  htim TIM Output Compare handle 
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -606,8 +604,8 @@
 
 /**
   * @brief  Stops the TIM Output Compare signal generation.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -638,8 +636,8 @@
 
 /**
   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim : TIM OC handle
-  * @param  Channel : TIM Channel to be enabled
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -704,8 +702,8 @@
 
 /**
   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be disabled
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -770,15 +768,15 @@
 
 /**
   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be enabled
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData : The source Buffer address.
-  * @param  Length : The length of data to be transferred from memory to TIM peripheral
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
 */
 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -889,8 +887,8 @@
 
 /**
   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be disabled
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -984,7 +982,7 @@
 /**
   * @brief  Initializes the TIM PWM Time Base according to the specified
   *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
@@ -1024,7 +1022,7 @@
 
 /**
   * @brief  DeInitializes the TIM peripheral 
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
@@ -1051,7 +1049,7 @@
 
 /**
   * @brief  Initializes the TIM PWM MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
@@ -1066,7 +1064,7 @@
 
 /**
   * @brief  DeInitializes TIM PWM MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1081,8 +1079,8 @@
 
 /**
   * @brief  Starts the PWM signal generation.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1113,8 +1111,8 @@
 
 /**
   * @brief  Stops the PWM signal generation.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1148,8 +1146,8 @@
 
 /**
   * @brief  Starts the PWM signal generation in interrupt mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be enabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1214,8 +1212,8 @@
 
 /**
   * @brief  Stops the PWM signal generation in interrupt mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1280,15 +1278,15 @@
 
 /**
   * @brief  Starts the TIM PWM signal generation in DMA mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData : The source Buffer address.
-  * @param  Length : The length of data to be transferred from memory to TIM peripheral
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
 */
 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -1399,8 +1397,8 @@
 
 /**
   * @brief  Stops the TIM PWM signal generation in DMA mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1494,7 +1492,7 @@
 /**
   * @brief  Initializes the TIM Input Capture Time base according to the specified
   *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim : TIM Input Capture handle
+  * @param  htim TIM Input Capture handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
@@ -1534,7 +1532,7 @@
 
 /**
   * @brief  DeInitializes the TIM peripheral 
-  * @param  htim : TIM Input Capture handle
+  * @param  htim TIM Input Capture handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
@@ -1561,7 +1559,7 @@
 
 /**
   * @brief  Initializes the TIM Input Capture MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
@@ -1576,7 +1574,7 @@
 
 /**
   * @brief  DeInitializes TIM Input Capture MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1591,8 +1589,8 @@
 
 /**
   * @brief  Starts the TIM Input Capture measurement.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1617,8 +1615,8 @@
 
 /**
   * @brief  Stops the TIM Input Capture measurement.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1643,8 +1641,8 @@
 
 /**
   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1702,8 +1700,8 @@
 
 /**
   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1762,15 +1760,15 @@
 
 /**
   * @brief  Starts the TIM Input Capture measurement in DMA mode.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData : The destination Buffer address.
-  * @param  Length : The length of data to be transferred from TIM peripheral to memory.
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
   * @retval HAL status
 */
 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -1877,8 +1875,8 @@
 
 /**
   * @brief  Stops the TIM Input Capture measurement in DMA mode.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be disabled
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1966,8 +1964,8 @@
 /**
   * @brief  Initializes the TIM One Pulse Time Base according to the specified
   *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim : TIM OnePulse handle
-  * @param  OnePulseMode : Select the One pulse mode.
+  * @param  htim TIM OnePulse handle
+  * @param  OnePulseMode Select the One pulse mode.
   *         This parameter can be one of the following values:
   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
@@ -2017,7 +2015,7 @@
 
 /**
   * @brief  DeInitializes the TIM One Pulse 
-  * @param  htim : TIM One Pulse handle
+  * @param  htim TIM One Pulse handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
@@ -2044,7 +2042,7 @@
 
 /**
   * @brief  Initializes the TIM One Pulse MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
@@ -2059,7 +2057,7 @@
 
 /**
   * @brief  DeInitializes TIM One Pulse MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2074,8 +2072,8 @@
 
 /**
   * @brief  Starts the TIM One Pulse signal generation.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be enabled
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2107,8 +2105,8 @@
 
 /**
   * @brief  Stops the TIM One Pulse signal generation.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be disable
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be disable
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2140,8 +2138,8 @@
 
 /**
   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be enabled
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2179,8 +2177,8 @@
 
 /**
   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be enabled
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2242,8 +2240,8 @@
   */
 /**
   * @brief  Initializes the TIM Encoder Interface and create the associated handle.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  sConfig : TIM Encoder Interface configuration structure
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
@@ -2336,7 +2334,7 @@
 
 /**
   * @brief  DeInitializes the TIM Encoder interface 
-  * @param  htim : TIM Encoder handle
+  * @param  htim TIM Encoder handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
@@ -2363,7 +2361,7 @@
 
 /**
   * @brief  Initializes the TIM Encoder Interface MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
@@ -2378,7 +2376,7 @@
 
 /**
   * @brief  DeInitializes TIM Encoder Interface MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2393,8 +2391,8 @@
 
 /**
   * @brief  Starts the TIM Encoder Interface.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2435,8 +2433,8 @@
 
 /**
   * @brief  Stops the TIM Encoder Interface.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be disabled
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2479,8 +2477,8 @@
 
 /**
   * @brief  Starts the TIM Encoder Interface in interrupt mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2527,8 +2525,8 @@
 
 /**
   * @brief  Stops the TIM Encoder Interface in interrupt mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be disabled
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2578,15 +2576,15 @@
 
 /**
   * @brief  Starts the TIM Encoder Interface in DMA mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @param  pData1 : The destination Buffer address for IC1.
-  * @param  pData2 : The destination Buffer address for IC2.
-  * @param  Length : The length of data to be transferred from TIM peripheral to memory.
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
   * @retval HAL status
 */
 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
@@ -2698,8 +2696,8 @@
 
 /**
   * @brief  Stops the TIM Encoder Interface in DMA mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2765,7 +2763,7 @@
   */
 /**
   * @brief  This function handles TIM interrupts requests.
-  * @param  htim : TIM  handle
+  * @param  htim TIM  handle
   * @retval None
   */
 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
@@ -2921,9 +2919,9 @@
 /**
   * @brief  Initializes the TIM Output Compare Channels according to the specified
   *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim : TIM Output Compare handle
-  * @param  sConfig : TIM Output Compare configuration structure
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2990,9 +2988,9 @@
 /**
   * @brief  Initializes the TIM Input Capture Channels according to the specified
   *         parameters in the TIM_IC_InitTypeDef.
-  * @param  htim : TIM IC handle
-  * @param  sConfig : TIM Input Capture configuration structure
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3086,9 +3084,9 @@
 /**
   * @brief  Initializes the TIM PWM  channels according to the specified
   *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim : TIM handle
-  * @param  sConfig : TIM PWM configuration structure
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3184,13 +3182,13 @@
 /**
   * @brief  Initializes the TIM One Pulse Channels according to the specified
   *         parameters in the TIM_OnePulse_InitTypeDef.
-  * @param  htim : TIM One Pulse handle
-  * @param  sConfig : TIM One Pulse configuration structure
-  * @param  OutputChannel : TIM Channels to be enabled
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @param  InputChannel : TIM Channels to be enabled
+  * @param  InputChannel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3296,8 +3294,8 @@
 
 /**
   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral 
-  * @param  htim : TIM handle
-  * @param  BurstBaseAddress : TIM Base address from where the DMA will start the Data write
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
   *         This parameter can be one of the following values:
   *            @arg TIM_DMABASE_CR1 
   *            @arg TIM_DMABASE_CR2
@@ -3318,7 +3316,7 @@
   *            @arg TIM_DMABASE_CCR4
   *            @arg TIM_DMABASE_BDTR
   *            @arg TIM_DMABASE_DCR
-  * @param  BurstRequestSrc : TIM DMA Request sources
+  * @param  BurstRequestSrc TIM DMA Request sources
   *         This parameter can be one of the following values:
   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
@@ -3327,19 +3325,66 @@
   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
   *            @arg TIM_DMA_COM: TIM Commutation DMA source
   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer : The Buffer address.
-  * @param  BurstLength : DMA Burst length. This parameter can be one value
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                              uint32_t* BurstBuffer, uint32_t  BurstLength)
+                                              uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_DCR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+                                                   uint32_t* BurstBuffer, uint32_t  BurstLength,  uint32_t  DataLength)
 {
   /* Check the parameters */
   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
 
   if((htim->State == HAL_TIM_STATE_BUSY))
   {
@@ -3367,7 +3412,7 @@
       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
     }
     break;
     case TIM_DMA_CC1:
@@ -3379,7 +3424,7 @@
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
     }
     break;
     case TIM_DMA_CC2:
@@ -3391,7 +3436,7 @@
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
     }
     break;
     case TIM_DMA_CC3:
@@ -3403,7 +3448,7 @@
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
     }
     break;
     case TIM_DMA_CC4:
@@ -3415,7 +3460,7 @@
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
     }
     break;
     case TIM_DMA_COM:
@@ -3427,7 +3472,7 @@
       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
     }
     break;
     case TIM_DMA_TRIGGER:
@@ -3439,7 +3484,7 @@
       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
     }
     break;
     default:
@@ -3459,8 +3504,8 @@
 
 /**
   * @brief  Stops the TIM DMA Burst mode 
-  * @param  htim : TIM handle
-  * @param  BurstRequestSrc : TIM DMA Request sources to disable
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
@@ -3519,8 +3564,8 @@
 
 /**
   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory 
-  * @param  htim : TIM handle
-  * @param  BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will starts the Data read
   *         This parameter can be one of the following values:
   *            @arg TIM_DMABASE_CR1 
   *            @arg TIM_DMABASE_CR2
@@ -3541,7 +3586,7 @@
   *            @arg TIM_DMABASE_CCR4
   *            @arg TIM_DMABASE_BDTR
   *            @arg TIM_DMABASE_DCR
-  * @param  BurstRequestSrc : TIM DMA Request sources
+  * @param  BurstRequestSrc TIM DMA Request sources
   *         This parameter can be one of the following values:
   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
@@ -3550,19 +3595,66 @@
   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
   *            @arg TIM_DMA_COM: TIM Commutation DMA source
   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer : The Buffer address.
-  * @param  BurstLength : DMA Burst length. This parameter can be one value
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
                                              uint32_t  *BurstBuffer, uint32_t  BurstLength)
 {
+return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will starts the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_DCR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+                                                  uint32_t  *BurstBuffer, uint32_t  BurstLength, uint32_t  DataLength)
+{
   /* Check the parameters */
   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
 
   if((htim->State == HAL_TIM_STATE_BUSY))
   {
@@ -3590,7 +3682,7 @@
       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
+       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
     }
     break;
     case TIM_DMA_CC1:
@@ -3602,7 +3694,7 @@
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
     }
     break;
     case TIM_DMA_CC2:
@@ -3614,7 +3706,7 @@
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
     }
     break;
     case TIM_DMA_CC3:
@@ -3626,7 +3718,7 @@
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
     }
     break;
     case TIM_DMA_CC4:
@@ -3638,7 +3730,7 @@
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
     }
     break;
     case TIM_DMA_COM:
@@ -3650,7 +3742,7 @@
       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
     }
     break;
     case TIM_DMA_TRIGGER:
@@ -3662,7 +3754,7 @@
       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
     }
     break;
     default:
@@ -3683,8 +3775,8 @@
 
 /**
   * @brief  Stop the DMA burst reading 
-  * @param  htim : TIM handle
-  * @param  BurstRequestSrc : TIM DMA Request sources to disable.
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
@@ -3743,8 +3835,8 @@
 
 /**
   * @brief  Generate a software event
-  * @param  htim : TIM handle
-  * @param  EventSource : specifies the event source.
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
   *          This parameter can be one of the following values:
   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
@@ -3785,10 +3877,10 @@
 
 /**
   * @brief  Configures the OCRef clear feature
-  * @param  htim : TIM handle
-  * @param  sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
   *         contains the OCREF clear feature and parameters for the TIM peripheral.
-  * @param  Channel : specifies the TIM Channel
+  * @param  Channel specifies the TIM Channel
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1
   *            @arg TIM_CHANNEL_2: TIM Channel 2
@@ -3919,8 +4011,8 @@
 
 /**
   * @brief   Configures the clock source to be used
-  * @param  htim : TIM handle
-  * @param  sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
   *         contains the clock source information for the TIM peripheral.
   * @retval HAL status
   */ 
@@ -4089,8 +4181,8 @@
 /**
   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
   *         or a XOR combination between CH1_input, CH2_input & CH3_input
-  * @param  htim : TIM handle.
-  * @param  TI1_Selection : Indicate whether or not channel 1 is connected to the
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
   *         output of a XOR gate.
   *          This parameter can be one of the following values:
   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
@@ -4123,8 +4215,8 @@
 
 /**
   * @brief  Configures the TIM in Slave mode
-  * @param  htim : TIM handle.
-  * @param  sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
   *         contains the selected trigger (internal trigger input, filtered
   *         timer input or external trigger input) and the ) and the Slave 
   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
@@ -4158,8 +4250,8 @@
 
 /**
   * @brief  Configures the TIM in Slave mode in interrupt mode
-  * @param  htim: TIM handle.
-  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
   *         contains the selected trigger (internal trigger input, filtered
   *         timer input or external trigger input) and the ) and the Slave 
   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
@@ -4194,8 +4286,8 @@
 
 /**
   * @brief  Read the captured value from Capture Compare unit
-  * @param  htim : TIM handle.
-  * @param  Channel : TIM Channels to be enabled
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1 : TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2 : TIM Channel 2 selected
@@ -4287,7 +4379,7 @@
 
 /**
   * @brief  Period elapsed callback in non blocking mode 
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
@@ -4302,7 +4394,7 @@
 }
 /**
   * @brief  Output Compare callback in non blocking mode 
-  * @param  htim : TIM OC handle
+  * @param  htim TIM OC handle
   * @retval None
   */
 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
@@ -4316,7 +4408,7 @@
 }
 /**
   * @brief  Input Capture callback in non blocking mode 
-  * @param  htim : TIM IC handle
+  * @param  htim TIM IC handle
   * @retval None
   */
 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
@@ -4331,7 +4423,7 @@
 
 /**
   * @brief  PWM Pulse finished callback in non blocking mode 
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
@@ -4346,7 +4438,7 @@
 
 /**
   * @brief  Hall Trigger detection callback in non blocking mode 
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
@@ -4361,7 +4453,7 @@
 
 /**
   * @brief  Timer error callback in non blocking mode 
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
@@ -4395,7 +4487,7 @@
 
 /**
   * @brief  Return the TIM Base state
-  * @param  htim : TIM Base handle
+  * @param  htim TIM Base handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
@@ -4405,7 +4497,7 @@
 
 /**
   * @brief  Return the TIM OC state
-  * @param  htim : TIM Ouput Compare handle
+  * @param  htim TIM Ouput Compare handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
@@ -4415,7 +4507,7 @@
 
 /**
   * @brief  Return the TIM PWM state
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
@@ -4425,7 +4517,7 @@
 
 /**
   * @brief  Return the TIM Input Capture state
-  * @param  htim : TIM IC handle
+  * @param  htim TIM IC handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
@@ -4435,7 +4527,7 @@
 
 /**
   * @brief  Return the TIM One Pulse Mode state
-  * @param  htim : TIM OPM handle
+  * @param  htim TIM OPM handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
@@ -4445,7 +4537,7 @@
 
 /**
   * @brief  Return the TIM Encoder Mode state
-  * @param  htim : TIM Encoder handle
+  * @param  htim TIM Encoder handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
@@ -4467,7 +4559,7 @@
 
 /**
   * @brief  TIM DMA error callback 
-  * @param  hdma : pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 void TIM_DMAError(DMA_HandleTypeDef *hdma)
@@ -4481,7 +4573,7 @@
 
 /**
   * @brief  TIM DMA Delay Pulse complete callback.
-  * @param  hdma : pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
@@ -4513,7 +4605,7 @@
 }
 /**
   * @brief  TIM DMA Capture complete callback.
-  * @param  hdma : pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
@@ -4546,7 +4638,7 @@
 
 /**
   * @brief  TIM DMA Period Elapse complete callback.
-  * @param  hdma : pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
@@ -4560,7 +4652,7 @@
 
 /**
   * @brief  TIM DMA Trigger callback.
-  * @param  hdma : pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
@@ -4574,8 +4666,8 @@
 
 /**
   * @brief  Time Base configuration
-  * @param  TIMx : TIM periheral
-  * @param  Structure : TIM Base configuration structure
+  * @param  TIMx TIM periheral
+  * @param  Structure TIM Base configuration structure
   * @retval None
   */
 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
@@ -4623,7 +4715,7 @@
 /**
   * @brief  Time Ouput Compare 1 configuration
   * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config : The ouput configuration structure
+  * @param  OC_Config The ouput configuration structure
   * @retval None
   */
 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4697,7 +4789,7 @@
 /**
   * @brief  Time Ouput Compare 2 configuration
   * @param  TIMx  to select the TIM peripheral
-  * @param  OC_Config : The ouput configuration structure
+  * @param  OC_Config The ouput configuration structure
   * @retval None
   */
 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4773,7 +4865,7 @@
 /**
   * @brief  Time Ouput Compare 3 configuration
   * @param  TIMx  to select the TIM peripheral
-  * @param  OC_Config : The ouput configuration structure
+  * @param  OC_Config The ouput configuration structure
   * @retval None
   */
 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4847,7 +4939,7 @@
 /**
   * @brief  Time Ouput Compare 4 configuration
   * @param  TIMx  to select the TIM peripheral
-  * @param  OC_Config : The ouput configuration structure
+  * @param  OC_Config The ouput configuration structure
   * @retval None
   */
 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -5029,17 +5121,17 @@
 /**
   * @brief  Configure the TI1 as Input.
   * @param  TIMx  to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICPOLARITY_RISING
   *            @arg TIM_ICPOLARITY_FALLING
   *            @arg TIM_ICPOLARITY_BOTHEDGE 
-  * @param  TIM_ICSelection : specifies the input to be used.
+  * @param  TIM_ICSelection specifies the input to be used.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1.
   *            @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2.
   *            @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter : Specifies the Input Capture Filter.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
   * @retval None
   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 
@@ -5084,12 +5176,12 @@
 /**
   * @brief  Configure the Polarity and Filter for TI1.
   * @param  TIMx  to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICPOLARITY_RISING
   *            @arg TIM_ICPOLARITY_FALLING
   *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICFilter : Specifies the Input Capture Filter.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
   * @retval None
   */
@@ -5119,17 +5211,17 @@
 /**
   * @brief  Configure the TI2 as Input.
   * @param  TIMx  to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICPOLARITY_RISING
   *            @arg TIM_ICPOLARITY_FALLING
   *            @arg TIM_ICPOLARITY_BOTHEDGE 
-  * @param  TIM_ICSelection : specifies the input to be used.
+  * @param  TIM_ICSelection specifies the input to be used.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2.
   *            @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1.
   *            @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter : Specifies the Input Capture Filter.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
   * @retval None
   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 
@@ -5167,12 +5259,12 @@
 /**
   * @brief  Configure the Polarity and Filter for TI2.
   * @param  TIMx  to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICPOLARITY_RISING
   *            @arg TIM_ICPOLARITY_FALLING
   *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICFilter : Specifies the Input Capture Filter.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
   * @retval None
   */
@@ -5202,17 +5294,17 @@
 /**
   * @brief  Configure the TI3 as Input.
   * @param  TIMx  to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICPOLARITY_RISING
   *            @arg TIM_ICPOLARITY_FALLING
   *            @arg TIM_ICPOLARITY_BOTHEDGE 
-  * @param  TIM_ICSelection : specifies the input to be used.
+  * @param  TIM_ICSelection specifies the input to be used.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3.
   *            @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4.
   *            @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter : Specifies the Input Capture Filter.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
   * @retval None
   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 
@@ -5250,17 +5342,17 @@
 /**
   * @brief  Configure the TI4 as Input.
   * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICPOLARITY_RISING
   *            @arg TIM_ICPOLARITY_FALLING
   *            @arg TIM_ICPOLARITY_BOTHEDGE 
-  * @param  TIM_ICSelection : specifies the input to be used.
+  * @param  TIM_ICSelection specifies the input to be used.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4.
   *            @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3.
   *            @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter : Specifies the Input Capture Filter.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 
   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be 
@@ -5298,7 +5390,7 @@
 /**
   * @brief  Selects the Input Trigger source
   * @param  TIMx  to select the TIM peripheral
-  * @param  InputTriggerSource : The Input Trigger source.
+  * @param  InputTriggerSource The Input Trigger source.
   *          This parameter can be one of the following values:
   *            @arg TIM_TS_ITR0 : Internal Trigger 0
   *            @arg TIM_TS_ITR1 : Internal Trigger 1
@@ -5326,17 +5418,17 @@
 /**
   * @brief  Configures the TIMx External Trigger (ETR).
   * @param  TIMx  to select the TIM peripheral
-  * @param  TIM_ExtTRGPrescaler : The external Trigger Prescaler.
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
   *          This parameter can be one of the following values:
   *            @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
   *            @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
   *            @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
   *            @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity : The external Trigger Polarity.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
   *          This parameter can be one of the following values:
   *            @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
   *            @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
-  * @param  ExtTRGFilter : External Trigger Filter.
+  * @param  ExtTRGFilter External Trigger Filter.
   *          This parameter must be a value between 0x00 and 0x0F
   * @retval None
   */
@@ -5360,13 +5452,13 @@
 /**
   * @brief  Enables or disables the TIM Capture Compare Channel x.
   * @param  TIMx  to select the TIM peripheral
-  * @param  Channel : specifies the TIM Channel
+  * @param  Channel specifies the TIM Channel
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1 : TIM Channel 1
   *            @arg TIM_CHANNEL_2 : TIM Channel 2
   *            @arg TIM_CHANNEL_3 : TIM Channel 3
   *            @arg TIM_CHANNEL_4 : TIM Channel 4
-  * @param  ChannelState : specifies the TIM Channel CCxE bit new state.
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
   * @retval None
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_tim.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of TIM HAL module.
   ******************************************************************************
   * @attention
@@ -1094,12 +1092,14 @@
                                    ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                    ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
 
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
 
 /** @brief Set TIM IC prescaler
-  * @param  __HANDLE__: TIM handle
-  * @param  __CHANNEL__: specifies TIM Channel
-  * @param  __ICPSC__: specifies the prescaler value.
+  * @param  __HANDLE__ TIM handle
+  * @param  __CHANNEL__ specifies TIM Channel
+  * @param  __ICPSC__ specifies the prescaler value.
   * @retval None
   */
 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
@@ -1109,8 +1109,8 @@
  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
 
 /** @brief Reset TIM IC prescaler
-  * @param  __HANDLE__: TIM handle
-  * @param  __CHANNEL__: specifies TIM Channel
+  * @param  __HANDLE__ TIM handle
+  * @param  __CHANNEL__ specifies TIM Channel
   * @retval None
   */
 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
@@ -1121,9 +1121,9 @@
 
 
 /** @brief Set TIM IC polarity
-  * @param  __HANDLE__: TIM handle
-  * @param  __CHANNEL__: specifies TIM Channel
-  * @param  __POLARITY__: specifies TIM Channel Polarity
+  * @param  __HANDLE__ TIM handle
+  * @param  __CHANNEL__ specifies TIM Channel
+  * @param  __POLARITY__ specifies TIM Channel Polarity
   * @retval None
   */
 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
@@ -1133,8 +1133,8 @@
  ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 12U)))
 
 /** @brief Reset TIM IC polarity
-  * @param  __HANDLE__: TIM handle
-  * @param  __CHANNEL__: specifies TIM Channel
+  * @param  __HANDLE__ TIM handle
+  * @param  __CHANNEL__ specifies TIM Channel
   * @retval None
   */
 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
@@ -1168,28 +1168,28 @@
   */
 
 /** @brief  Reset TIM handle state
-  * @param  __HANDLE__: TIM handle.
+  * @param  __HANDLE__ TIM handle.
   * @retval None
   */
 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
 
 /**
   * @brief  Enable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
+  * @param  __HANDLE__ TIM handle
   * @retval None
  */
 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
 
 /**
   * @brief  Enable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
+  * @param  __HANDLE__ TIM handle
   * @retval None
   */
 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
 
 /**
   * @brief  Disable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
+  * @param  __HANDLE__ TIM handle
   * @retval None
   */
 #define __HAL_TIM_DISABLE(__HANDLE__) \
@@ -1206,7 +1206,7 @@
    channels have been disabled */
 /**
   * @brief  Disable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
+  * @param  __HANDLE__ TIM handle
   * @retval None
   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
   */
@@ -1221,10 +1221,19 @@
                             } \
                         } while(0)
 
+/* The Main Output Enable of a timer instance is disabled unconditionally */                          
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled uncondiotionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
 /**
   * @brief  Enables the specified TIM interrupt.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
   *          This parameter can be one of the following values:
   *            @arg TIM_IT_UPDATE: Update interrupt
   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
@@ -1240,8 +1249,8 @@
 
 /**
   * @brief  Disables the specified TIM interrupt.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __INTERRUPT__: specifies the TIM interrupt source to disable.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
   *          This parameter can be one of the following values:
   *            @arg TIM_IT_UPDATE: Update interrupt
   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
@@ -1257,8 +1266,8 @@
 
 /**
   * @brief  Enables the specified DMA request.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __DMA__: specifies the TIM DMA request to enable.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
   *          This parameter can be one of the following values:
   *            @arg TIM_DMA_UPDATE: Update DMA request
   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
@@ -1273,8 +1282,8 @@
 
 /**
   * @brief  Disables the specified DMA request.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __DMA__: specifies the TIM DMA request to disable.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
   *          This parameter can be one of the following values:
   *            @arg TIM_DMA_UPDATE: Update DMA request
   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
@@ -1289,8 +1298,8 @@
 
 /**
   * @brief  Checks whether the specified TIM interrupt flag is set or not.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __FLAG__: specifies the TIM interrupt flag to check.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
   *        This parameter can be one of the following values:
   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
@@ -1310,8 +1319,8 @@
 
 /**
   * @brief  Clears the specified TIM interrupt flag.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __FLAG__: specifies the TIM interrupt flag to clear.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
   *        This parameter can be one of the following values:
   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
@@ -1331,23 +1340,23 @@
 
 /**
   * @brief  Checks whether the specified TIM interrupt has occurred or not.
-  * @param  __HANDLE__: TIM handle
-  * @param  __INTERRUPT__: specifies the TIM interrupt source to check.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
   * @retval The state of TIM_IT (SET or RESET).
   */
 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /**
   * @brief Clear the TIM interrupt pending bits
-  * @param  __HANDLE__: TIM handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
   * @retval None
   */
 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
 
 /**
   * @brief  Indicates whether or not the TIM Counter is used as downcounter
-  * @param  __HANDLE__: TIM handle.
+  * @param  __HANDLE__ TIM handle.
   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
   * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
 mode.
@@ -1356,8 +1365,8 @@
 
 /**
   * @brief  Sets the TIM active prescaler register value on update event.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __PRESC__: specifies the active prescaler register new value.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the active prescaler register new value.
   * @retval None
   */
 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
@@ -1365,14 +1374,14 @@
 /**
   * @brief  Sets the TIM Capture Compare Register value on runtime without
   *         calling another time ConfigChannel function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __COMPARE__: specifies the Capture Compare register new value.
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
   * @retval None
   */
 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
@@ -1380,30 +1389,30 @@
 
 /**
   * @brief  Gets the TIM Capture Compare Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
-  * @retval None
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
   */
 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
   (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
 
 /**
   * @brief  Sets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __COUNTER__: specifies the Counter register new value.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
   * @retval None
   */
 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
 
 /**
   * @brief  Gets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
   */
 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
    ((__HANDLE__)->Instance->CNT)
@@ -1411,8 +1420,8 @@
 /**
   * @brief  Sets the TIM Autoreload Register value on runtime without calling 
   *         another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __AUTORELOAD__: specifies the Counter register new value.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
   * @retval None
   */
 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
@@ -1423,8 +1432,8 @@
 
 /**
   * @brief  Gets the TIM Autoreload Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
   */
 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
    ((__HANDLE__)->Instance->ARR)
@@ -1432,12 +1441,12 @@
 /**
   * @brief  Sets the TIM Clock Division value on runtime without calling 
   *         another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CKD__: specifies the clock division value.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
   *          This parameter can be one of the following value:
-  *            @arg TIM_CLOCKDIVISION_DIV1
-  *            @arg TIM_CLOCKDIVISION_DIV2
-  *            @arg TIM_CLOCKDIVISION_DIV4 
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
   * @retval None
   */
 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
@@ -1449,16 +1458,19 @@
 
 /**
   * @brief  Gets the TIM Clock Division value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
   */
 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
    ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
 
 /**
   * @brief  Sets the TIM Output compare preload.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1474,8 +1486,8 @@
 
 /**
   * @brief  Resets the TIM Output compare preload.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1493,14 +1505,14 @@
 /**
   * @brief  Sets the TIM Input Capture prescaler on runtime without calling 
   *         another time HAL_TIM_IC_ConfigChannel() function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICPSC_DIV1: no prescaler
   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
@@ -1516,14 +1528,18 @@
 
 /**
   * @brief  Gets the TIM Input Capture prescaler on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
-  * @retval None
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
   */
 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
@@ -1533,7 +1549,7 @@
 
 /**
   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register
-  * @param  __HANDLE__: TIM handle.
+  * @param  __HANDLE__ TIM handle.
   * @note  When the USR bit of the TIMx_CR1 register is set, only counter 
   *        overflow/underflow generates an update interrupt or DMA request (if
   *        enabled)
@@ -1544,7 +1560,7 @@
 
 /**
   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register
-  * @param  __HANDLE__: TIM handle.
+  * @param  __HANDLE__ TIM handle.
   * @note  When the USR bit of the TIMx_CR1 register is reset, any of the 
   *        following events generate an update interrupt or DMA request (if 
   *        enabled):
@@ -1558,14 +1574,14 @@
 
 /**
   * @brief  Sets the TIM Capture x input polarity on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __POLARITY__: Polarity for TIx source   
+  * @param  __POLARITY__ Polarity for TIx source   
   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
@@ -1739,9 +1755,13 @@
 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+                                                   uint32_t  *BurstBuffer, uint32_t  BurstLength, uint32_t  DataLength);
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+                                                  uint32_t  *BurstBuffer, uint32_t  BurstLength, uint32_t  DataLength);
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_tim_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   TIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Timer Extended peripheral:
@@ -153,8 +151,8 @@
   */
 /**
   * @brief  Initializes the TIM Hall Sensor Interface and create the associated handle.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  sConfig : TIM Hall Sensor configuration structure
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
@@ -233,7 +231,7 @@
 
 /**
   * @brief  DeInitializes the TIM Hall Sensor interface 
-  * @param  htim : TIM Hall Sensor handle
+  * @param  htim TIM Hall Sensor handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
@@ -260,7 +258,7 @@
 
 /**
   * @brief  Initializes the TIM Hall Sensor MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
@@ -275,7 +273,7 @@
 
 /**
   * @brief  DeInitializes TIM Hall Sensor MSP.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
@@ -290,7 +288,7 @@
 
 /**
   * @brief  Starts the TIM Hall Sensor Interface.
-  * @param  htim : TIM Hall Sensor handle
+  * @param  htim TIM Hall Sensor handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
@@ -311,7 +309,7 @@
 
 /**
   * @brief  Stops the TIM Hall sensor Interface.
-  * @param  htim : TIM Hall Sensor handle
+  * @param  htim TIM Hall Sensor handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
@@ -332,7 +330,7 @@
 
 /**
   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
-  * @param  htim : TIM Hall Sensor handle
+  * @param  htim TIM Hall Sensor handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
@@ -356,7 +354,7 @@
 
 /**
   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
@@ -380,9 +378,9 @@
 
 /**
   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
-  * @param  htim : TIM Hall Sensor handle
-  * @param  pData : The destination Buffer address.
-  * @param  Length : The length of data to be transferred from TIM peripheral to memory.
+  * @param  htim TIM Hall Sensor handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
@@ -429,7 +427,7 @@
 
 /**
   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
@@ -479,8 +477,8 @@
 /**
   * @brief  Starts the TIM Output Compare signal generation on the complementary
   *         output.
-  * @param  htim : TIM Output Compare handle 
-  * @param  Channel : TIM Channel to be enabled
+  * @param  htim TIM Output Compare handle 
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -509,8 +507,8 @@
 /**
   * @brief  Stops the TIM Output Compare signal generation on the complementary
   *         output.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -539,8 +537,8 @@
 /**
   * @brief  Starts the TIM Output Compare signal generation in interrupt mode 
   *         on the complementary output.
-  * @param  htim : TIM OC handle
-  * @param  Channel : TIM Channel to be enabled
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -606,8 +604,8 @@
 /**
   * @brief  Stops the TIM Output Compare signal generation in interrupt mode 
   *         on the complementary output.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be disabled
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -679,15 +677,15 @@
 /**
   * @brief  Starts the TIM Output Compare signal generation in DMA mode 
   *         on the complementary output.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be enabled
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData : The source Buffer address.
-  * @param  Length : The length of data to be transferred from memory to TIM peripheral
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -796,8 +794,8 @@
 /**
   * @brief  Stops the TIM Output Compare signal generation in DMA mode 
   *         on the complementary output.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be disabled
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -896,8 +894,8 @@
 
 /**
   * @brief  Starts the PWM signal generation on the complementary output.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be enabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -925,8 +923,8 @@
 
 /**
   * @brief  Stops the PWM signal generation on the complementary output.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -955,8 +953,8 @@
 /**
   * @brief  Starts the PWM signal generation in interrupt mode on the 
   *         complementary output.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1022,8 +1020,8 @@
 /**
   * @brief  Stops the PWM signal generation in interrupt mode on the 
   *         complementary output.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1095,15 +1093,15 @@
 /**
   * @brief  Starts the TIM PWM signal generation in DMA mode on the 
   *         complementary output
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be enabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData : The source Buffer address.
-  * @param  Length : The length of data to be transferred from memory to TIM peripheral
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -1212,8 +1210,8 @@
 /**
   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
   *         output
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1301,8 +1299,8 @@
 /**
   * @brief  Starts the TIM One Pulse signal generation on the complemetary 
   *         output.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channel to be enabled
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1326,8 +1324,8 @@
 /**
   * @brief  Stops the TIM One Pulse signal generation on the complementary 
   *         output.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channel to be disabled
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1355,8 +1353,8 @@
 /**
   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
   *         complementary channel.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channel to be enabled
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1386,8 +1384,8 @@
 /**
   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
   *         complementary channel.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channel to be disabled
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1445,15 +1443,15 @@
   *        configured in Hall sensor interface, this interface Timer will generate the 
   *        commutation at its TRGO output (connected to Timer used in this function) each time 
   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @param  htim : TIM handle
-  * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
   *          This parameter can be one of the following values:
   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
   *            @arg TIM_TS_NONE: No trigger is needed 
-  * @param  CommutationSource : the Commutation Event source
+  * @param  CommutationSource the Commutation Event source
   *          This parameter can be one of the following values:
   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
@@ -1494,15 +1492,15 @@
   *        configured in Hall sensor interface, this interface Timer will generate the 
   *        commutation at its TRGO output (connected to Timer used in this function) each time 
   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @param  htim : TIM handle
-  * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
   *          This parameter can be one of the following values:
   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
   *            @arg TIM_TS_NONE: No trigger is needed 
-  * @param  CommutationSource : the Commutation Event source
+  * @param  CommutationSource the Commutation Event source
   *          This parameter can be one of the following values:
   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
@@ -1547,15 +1545,15 @@
   *        commutation at its TRGO output (connected to Timer used in this function) each time 
   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
   * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
-  * @param  htim : TIM handle
-  * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
   *          This parameter can be one of the following values:
   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
   *            @arg TIM_TS_NONE: No trigger is needed 
-  * @param  CommutationSource : the Commutation Event source
+  * @param  CommutationSource the Commutation Event source
   *          This parameter can be one of the following values:
   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
@@ -1599,8 +1597,8 @@
 
 /**
   * @brief  Configures the TIM in master mode.
-  * @param  htim : TIM handle.
-  * @param  sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
   *         contains the selected trigger output (TRGO) and the Master/Slave 
   *         mode.
   * @retval HAL status
@@ -1636,8 +1634,8 @@
 /**
   * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
   *          and the AOE(automatic output enable).
-  * @param  htim : TIM handle
-  * @param  sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
   *         contains the BDTR Register configuration  information for the TIM peripheral.
   * @retval HAL status
   */    
@@ -1686,8 +1684,8 @@
 
 /**
   * @brief  Configures the TIM14 Remapping input capabilities.
-  * @param  htim : TIM handle.
-  * @param  Remap : specifies the TIM remapping source.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
   *          This parameter can be one of the following values:
   *            @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
   *            @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
@@ -1725,10 +1723,10 @@
     defined(STM32F091xC) || defined (STM32F098xx)
 /**
   * @brief  Configures the OCRef clear feature
-  * @param  htim: TIM handle
-  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
   *         contains the OCREF clear feature and parameters for the TIM peripheral. 
-  * @param  Channel: specifies the TIM Channel
+  * @param  Channel specifies the TIM Channel
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1
   *            @arg TIM_CHANNEL_2: TIM Channel 2
@@ -1890,7 +1888,7 @@
 
 /**
   * @brief  Hall commutation changed callback in non blocking mode 
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
@@ -1905,7 +1903,7 @@
 
 /**
   * @brief  Hall Break detection callback in non blocking mode 
-  * @param  htim : TIM handle
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
@@ -1920,7 +1918,7 @@
 
 /**
   * @brief  TIM DMA Commutation callback.
-  * @param  hdma : pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
@@ -1953,7 +1951,7 @@
 
 /**
   * @brief  Return the TIM Hall Sensor interface state
-  * @param  htim : TIM Hall Sensor handle
+  * @param  htim TIM Hall Sensor handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
@@ -1976,12 +1974,12 @@
 /**
   * @brief  Enables or disables the TIM Capture Compare Channel xN.
   * @param  TIMx  to select the TIM peripheral
-  * @param  Channel : specifies the TIM Channel
+  * @param  Channel specifies the TIM Channel
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1
   *            @arg TIM_CHANNEL_2: TIM Channel 2
   *            @arg TIM_CHANNEL_3: TIM Channel 3
-  * @param  ChannelNState : specifies the TIM Channel CCxNE bit new state.
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
   * @retval None
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_tim_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of TIM HAL Extended module.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_tsc.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Touch Sensing Controller (TSC) peripheral:
   *           + Initialization and DeInitialization
@@ -153,7 +151,7 @@
 /**
   * @brief  Initializes the TSC peripheral according to the specified parameters 
   *         in the TSC_InitTypeDef structure.           
-  * @param  htsc: TSC handle
+  * @param  htsc TSC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
@@ -241,7 +239,7 @@
 
 /**
   * @brief  Deinitializes the TSC peripheral registers to their default reset values.
-  * @param  htsc: TSC handle  
+  * @param  htsc TSC handle  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
@@ -273,7 +271,7 @@
 
 /**
   * @brief  Initializes the TSC MSP.
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.  
   * @retval None
   */
@@ -289,7 +287,7 @@
 
 /**
   * @brief  DeInitializes the TSC MSP.
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.  
   * @retval None
   */
@@ -327,7 +325,7 @@
 
 /**
   * @brief  Starts the acquisition.
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
   * @retval HAL status
   */
@@ -370,7 +368,7 @@
 
 /**
   * @brief  Enables the interrupt and starts the acquisition
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
   * @retval HAL status.
   */
@@ -424,7 +422,7 @@
 
 /**
   * @brief  Stops the acquisition previously launched in polling mode
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
   * @retval HAL status
   */
@@ -457,7 +455,7 @@
 
 /**
   * @brief  Stops the acquisition previously launched in interrupt mode
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
   * @retval HAL status
   */
@@ -493,9 +491,9 @@
 
 /**
   * @brief  Gets the acquisition status for a group
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
-  * @param  gx_index: Index of the group
+  * @param  gx_index Index of the group
   * @retval Group status
   */
 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
@@ -510,9 +508,9 @@
 
 /**
   * @brief  Gets the acquisition measure for a group
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
-  * @param  gx_index: Index of the group
+  * @param  gx_index Index of the group
   * @retval Acquisition measure
   */
 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
@@ -545,9 +543,9 @@
 
 /**
   * @brief  Configures TSC IOs
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
-  * @param  config: pointer to the configuration structure.
+  * @param  config pointer to the configuration structure.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
@@ -582,9 +580,9 @@
 
 /**
   * @brief  Discharge TSC IOs
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
-  * @param  choice: enable or disable
+  * @param  choice enable or disable
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
@@ -634,7 +632,7 @@
 
 /**
   * @brief  Return the TSC state
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
   * @retval HAL state
   */
@@ -670,7 +668,7 @@
   * @brief  Start acquisition and wait until completion
   * @note   There is no need of a timeout parameter as the max count error is already
   *         managed by the TSC peripheral.
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
   * @retval HAL state
   */
@@ -696,7 +694,7 @@
 
 /**
   * @brief  Handles TSC interrupt request  
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
   * @retval None
   */
@@ -742,7 +740,7 @@
  
 /**
   * @brief  Acquisition completed callback in non blocking mode 
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
   * @retval None
   */
@@ -758,7 +756,7 @@
 
 /**
   * @brief  Error callback in non blocking mode
-  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  * @param  htsc pointer to a TSC_HandleTypeDef structure that contains
   *         the configuration information for the specified TSC.
   * @retval None
   */
@@ -786,7 +784,7 @@
       
 /**
   * @brief  Utility function used to set the acquired groups mask
-  * @param  iomask: Channels IOs mask
+  * @param  iomask Channels IOs mask
   * @retval Acquired groups mask
   */
 static uint32_t TSC_extract_groups(uint32_t iomask)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_tsc.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   This file contains all the functions prototypes for the TSC firmware 
   *          library.
   ******************************************************************************
@@ -439,189 +437,189 @@
  */
 
 /** @brief  Reset TSC handle state
-  * @param  __HANDLE__: TSC handle.
+  * @param  __HANDLE__ TSC handle.
   * @retval None
   */
 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
 
 /**
   * @brief Enable the TSC peripheral.
-  * @param  __HANDLE__: TSC handle
+  * @param  __HANDLE__ TSC handle
   * @retval None
   */
 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
 
 /**
   * @brief Disable the TSC peripheral.
-  * @param  __HANDLE__: TSC handle
+  * @param  __HANDLE__ TSC handle
   * @retval None
   */
 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
 
 /**
   * @brief Start acquisition
-  * @param  __HANDLE__: TSC handle
+  * @param  __HANDLE__ TSC handle
   * @retval None
   */
 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
 
 /**
   * @brief Stop acquisition
-  * @param  __HANDLE__: TSC handle
+  * @param  __HANDLE__ TSC handle
   * @retval None
   */
 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
 
 /**
   * @brief Set IO default mode to output push-pull low
-  * @param  __HANDLE__: TSC handle
+  * @param  __HANDLE__ TSC handle
   * @retval None
   */
 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
 
 /**
   * @brief Set IO default mode to input floating
-  * @param  __HANDLE__: TSC handle
+  * @param  __HANDLE__ TSC handle
   * @retval None
   */
 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
 
 /**
   * @brief Set synchronization polarity to falling edge
-  * @param  __HANDLE__: TSC handle
+  * @param  __HANDLE__ TSC handle
   * @retval None
   */
 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
 
 /**
   * @brief Set synchronization polarity to rising edge and high level
-  * @param  __HANDLE__: TSC handle
+  * @param  __HANDLE__ TSC handle
   * @retval None
   */
 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
 
 /**
   * @brief Enable TSC interrupt.
-  * @param  __HANDLE__: TSC handle
-  * @param  __INTERRUPT__: TSC interrupt
+  * @param  __HANDLE__ TSC handle
+  * @param  __INTERRUPT__ TSC interrupt
   * @retval None
   */
 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
 
 /**
   * @brief Disable TSC interrupt.
-  * @param  __HANDLE__: TSC handle
-  * @param  __INTERRUPT__: TSC interrupt
+  * @param  __HANDLE__ TSC handle
+  * @param  __INTERRUPT__ TSC interrupt
   * @retval None
   */
 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
 
 /** @brief Check if the specified TSC interrupt source is enabled or disabled.
-  * @param  __HANDLE__: TSC Handle
-  * @param  __INTERRUPT__: TSC interrupt
+  * @param  __HANDLE__ TSC Handle
+  * @param  __INTERRUPT__ TSC interrupt
   * @retval SET or RESET
   */
 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /**
   * @brief Get the selected TSC's flag status.
-  * @param  __HANDLE__: TSC handle
-  * @param  __FLAG__: TSC flag
+  * @param  __HANDLE__ TSC handle
+  * @param  __FLAG__ TSC flag
   * @retval SET or RESET
   */
 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
 
 /**
   * @brief Clear the TSC's pending flag.
-  * @param  __HANDLE__: TSC handle
-  * @param  __FLAG__: TSC flag
+  * @param  __HANDLE__ TSC handle
+  * @param  __FLAG__ TSC flag
   * @retval None
   */
 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
 
 /**
   * @brief Enable schmitt trigger hysteresis on a group of IOs
-  * @param  __HANDLE__: TSC handle
-  * @param  __GX_IOY_MASK__: IOs mask
+  * @param  __HANDLE__ TSC handle
+  * @param  __GX_IOY_MASK__ IOs mask
   * @retval None
   */
 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
 
 /**
   * @brief Disable schmitt trigger hysteresis on a group of IOs
-  * @param  __HANDLE__: TSC handle
-  * @param  __GX_IOY_MASK__: IOs mask
+  * @param  __HANDLE__ TSC handle
+  * @param  __GX_IOY_MASK__ IOs mask
   * @retval None
   */
 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 
 /**
   * @brief Open analog switch on a group of IOs
-  * @param  __HANDLE__: TSC handle
-  * @param  __GX_IOY_MASK__: IOs mask
+  * @param  __HANDLE__ TSC handle
+  * @param  __GX_IOY_MASK__ IOs mask
   * @retval None
   */
 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 
 /**
   * @brief Close analog switch on a group of IOs
-  * @param  __HANDLE__: TSC handle
-  * @param  __GX_IOY_MASK__: IOs mask
+  * @param  __HANDLE__ TSC handle
+  * @param  __GX_IOY_MASK__ IOs mask
   * @retval None
   */
 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
 
 /**
   * @brief Enable a group of IOs in channel mode
-  * @param  __HANDLE__: TSC handle
-  * @param  __GX_IOY_MASK__: IOs mask
+  * @param  __HANDLE__ TSC handle
+  * @param  __GX_IOY_MASK__ IOs mask
   * @retval None
   */
 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
 
 /**
   * @brief Disable a group of channel IOs
-  * @param  __HANDLE__: TSC handle
-  * @param  __GX_IOY_MASK__: IOs mask
+  * @param  __HANDLE__ TSC handle
+  * @param  __GX_IOY_MASK__ IOs mask
   * @retval None
   */
 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 
 /**
   * @brief Enable a group of IOs in sampling mode
-  * @param  __HANDLE__: TSC handle
-  * @param  __GX_IOY_MASK__: IOs mask
+  * @param  __HANDLE__ TSC handle
+  * @param  __GX_IOY_MASK__ IOs mask
   * @retval None
   */
 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
 
 /**
   * @brief Disable a group of sampling IOs
-  * @param  __HANDLE__: TSC handle
-  * @param  __GX_IOY_MASK__: IOs mask
+  * @param  __HANDLE__ TSC handle
+  * @param  __GX_IOY_MASK__ IOs mask
   * @retval None
   */
 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 
 /**
   * @brief Enable acquisition groups
-  * @param  __HANDLE__: TSC handle
-  * @param  __GX_MASK__: Groups mask
+  * @param  __HANDLE__ TSC handle
+  * @param  __GX_MASK__ Groups mask
   * @retval None
   */
 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
 
 /**
   * @brief Disable acquisition groups
-  * @param  __HANDLE__: TSC handle
-  * @param  __GX_MASK__: Groups mask
+  * @param  __HANDLE__ TSC handle
+  * @param  __GX_MASK__ Groups mask
   * @retval None
   */
 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
 
 /** @brief Gets acquisition group status
-  * @param  __HANDLE__: TSC Handle
-  * @param  __GX_INDEX__: Group index
+  * @param  __HANDLE__ TSC Handle
+  * @param  __GX_INDEX__ Group index
   * @retval SET or RESET
   */
 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_uart.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   UART HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -287,7 +285,7 @@
 /**
   * @brief Initialize the UART mode according to the specified
   *        parameters in the UART_InitTypeDef and initialize the associated handle.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
@@ -366,7 +364,7 @@
 /**
   * @brief Initialize the half-duplex mode according to the specified
   *        parameters in the UART_InitTypeDef and creates the associated handle.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
@@ -439,9 +437,9 @@
 /**
   * @brief Initialize the multiprocessor mode according to the specified
   *        parameters in the UART_InitTypeDef and initialize the associated handle.
-  * @param huart: UART handle.
-  * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
-  * @param WakeUpMethod: specifies the UART wakeup method.
+  * @param huart UART handle.
+  * @param Address UART node address (4-, 6-, 7- or 8-bit long).
+  * @param WakeUpMethod specifies the UART wakeup method.
   *        This parameter can be one of the following values:
   *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
   *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
@@ -531,7 +529,7 @@
 
 /**
   * @brief DeInitialize the UART peripheral.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
@@ -569,7 +567,7 @@
 
 /**
   * @brief Initialize the UART MSP.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval None
   */
 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
@@ -584,7 +582,7 @@
 
 /**
   * @brief DeInitialize the UART MSP.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval None
   */
 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
@@ -680,10 +678,10 @@
 
 /**
   * @brief Send an amount of data in blocking mode.
-  * @param huart: UART handle.
-  * @param pData: Pointer to data buffer.
-  * @param Size: Amount of data to be sent.
-  * @param Timeout: Timeout duration.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer.
+  * @param Size Amount of data to be sent.
+  * @param Timeout Timeout duration.
   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
   *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
@@ -764,10 +762,10 @@
 
 /**
   * @brief Receive an amount of data in blocking mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be received.
-  * @param Timeout: Timeout duration.
+  * @param huart UART handle.
+  * @param pData pointer to data buffer.
+  * @param Size amount of data to be received.
+  * @param Timeout Timeout duration.
   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
   *         (as received data will be handled using u16 pointer cast). Depending on compilation chain,
@@ -851,9 +849,9 @@
 
 /**
   * @brief Send an amount of data in interrupt mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be sent.
+  * @param huart UART handle.
+  * @param pData pointer to data buffer.
+  * @param Size amount of data to be sent.
   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
   *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
@@ -907,9 +905,9 @@
 
 /**
   * @brief Receive an amount of data in interrupt mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be received.
+  * @param huart UART handle.
+  * @param pData pointer to data buffer.
+  * @param Size amount of data to be received.
   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
   *         (as received data will be handled using u16 pointer cast). Depending on compilation chain,
@@ -969,9 +967,9 @@
 
 /**
   * @brief Send an amount of data in DMA mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be sent.
+  * @param huart UART handle.
+  * @param pData pointer to data buffer.
+  * @param Size amount of data to be sent.
   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
   *         (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
@@ -1044,9 +1042,9 @@
 
 /**
   * @brief Receive an amount of data in DMA mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be received.
+  * @param huart UART handle.
+  * @param pData pointer to data buffer.
+  * @param Size amount of data to be received.
   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
   *         (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
@@ -1121,7 +1119,7 @@
 
 /**
   * @brief Pause the DMA Transfer.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
@@ -1154,7 +1152,7 @@
 
 /**
   * @brief Resume the DMA Transfer.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
@@ -1188,7 +1186,7 @@
 
 /**
   * @brief Stop the DMA Transfer.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
@@ -1652,7 +1650,7 @@
 
 /**
   * @brief Handle UART interrupt request.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval None
   */
 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
@@ -1806,7 +1804,7 @@
 
 /**
   * @brief Tx Transfer completed callback.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval None
   */
 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
@@ -1821,7 +1819,7 @@
 
 /**
   * @brief  Tx Half Transfer completed callback.
-  * @param  huart: UART handle.
+  * @param  huart UART handle.
   * @retval None
   */
 __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
@@ -1836,7 +1834,7 @@
 
 /**
   * @brief Rx Transfer completed callback.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval None
   */
 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
@@ -1851,7 +1849,7 @@
 
 /**
   * @brief  Rx Half Transfer completed callback.
-  * @param  huart: UART handle.
+  * @param  huart UART handle.
   * @retval None
   */
 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
@@ -1866,7 +1864,7 @@
 
 /**
   * @brief UART error callback.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval None
   */
 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
@@ -1949,7 +1947,7 @@
 /**
   * @brief Enable UART in mute mode (does not mean UART enters mute mode;
   * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
@@ -1970,7 +1968,7 @@
 /**
   * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
   *         as it may not have been in mute mode at this very moment).
-  * @param  huart: UART handle.
+  * @param  huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
@@ -1991,7 +1989,7 @@
 /**
   * @brief Enter UART mute mode (means UART actually enters mute mode).
   * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval None
   */
 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
@@ -2001,7 +1999,7 @@
 
 /**
   * @brief  Enable the UART transmitter and disable the UART receiver.
-  * @param  huart: UART handle.
+  * @param  huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
@@ -2025,7 +2023,7 @@
 
 /**
   * @brief  Enable the UART receiver and disable the UART transmitter.
-  * @param  huart: UART handle.
+  * @param  huart UART handle.
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
@@ -2105,7 +2103,7 @@
 
 /**
   * @brief Configure the UART peripheral.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
@@ -2210,7 +2208,7 @@
 
 /**
   * @brief Configure the UART peripheral advanced features.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval None
   */
 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_uart.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of UART HAL module.
   ******************************************************************************
   * @attention
@@ -408,19 +406,16 @@
   */
 
 /** @defgroup UART_IT   UART IT
-  *       Elements values convention: 000000000XXYYYYYb
+  *       Elements values convention: 0000ZZZZ0XXYYYYYb
   *           - YYYYY  : Interrupt source position in the XX register (5bits)
   *           - XX  : Interrupt source register (2bits)
   *                 - 01: CR1 register
   *                 - 10: CR2 register
   *                 - 11: CR3 register
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
   * @{
   */
 #define UART_IT_ERR                         (0x0060U)                  /*!< UART error interruption         */   
-
-/**       Elements values convention: 0000ZZZZ00000000b
-  *           - ZZZZ  : Flag position in the ISR register(4bits)
-  */
 #define UART_IT_ORE                         (0x0300U)                  /*!< UART overrun error interruption */ 
 #define UART_IT_NE                          (0x0200U)                  /*!< UART noise error interruption   */ 
 #define UART_IT_FE                          (0x0100U)                  /*!< UART frame error interruption   */ 
@@ -585,7 +580,7 @@
   */
 
 /** @brief  Reset UART handle states.
-  * @param  __HANDLE__: UART handle.
+  * @param  __HANDLE__ UART handle.
   * @retval None
   */
 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
@@ -594,8 +589,8 @@
                                                      } while(0)
 
 /** @brief  Clear the specified UART pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag           
   *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag          
@@ -635,38 +630,38 @@
 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
 
 /** @brief  Clear the UART PE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
 
 /** @brief  Clear the UART FE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
 
 /** @brief  Clear the UART NE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
 
 /** @brief  Clear the UART ORE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
 
 /** @brief  Clear the UART IDLE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
 
 /** @brief  Check whether the specified UART flag is set or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   @if STM32F030x6
   @elseif STM32F030x8
@@ -722,8 +717,8 @@
 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Enable the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
   *          This parameter can be one of the following values:
   @if STM32F030x6
   @elseif STM32F030x8
@@ -757,8 +752,8 @@
 
 
 /** @brief  Disable the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
   *          This parameter can be one of the following values:
   @if STM32F030x6
   @elseif STM32F030x8
@@ -791,8 +786,8 @@
                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
 
 /** @brief  Check whether the specified UART interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __IT__: specifies the UART interrupt to check.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __IT__ specifies the UART interrupt to check.
   *          This parameter can be one of the following values:
   @if STM32F030x6
   @elseif STM32F030x8
@@ -825,8 +820,8 @@
 #define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
 
 /** @brief  Check whether the specified UART interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __IT__: specifies the UART interrupt source to check.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __IT__ specifies the UART interrupt source to check.
   *          This parameter can be one of the following values:
   @if STM32F030x6
   @elseif STM32F030x8
@@ -858,8 +853,8 @@
                                                        (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK)))
 
 /** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
   *                       to clear the corresponding interrupt
   *          This parameter can be one of the following values:
   *            @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
@@ -900,8 +895,8 @@
 #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
 
 /** @brief  Set a specific UART request flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __REQ__: specifies the request flag to set
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __REQ__ specifies the request flag to set
   *          This parameter can be one of the following values:
   *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
   *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
@@ -920,25 +915,25 @@
 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
 
 /** @brief  Enable the UART one bit sample method.
-  * @param  __HANDLE__: specifies the UART Handle.  
+  * @param  __HANDLE__ specifies the UART Handle.  
   * @retval None
   */     
 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
 /** @brief  Disable the UART one bit sample method.
-  * @param  __HANDLE__: specifies the UART Handle.  
+  * @param  __HANDLE__ specifies the UART Handle.  
   * @retval None
   */      
 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable UART.
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable UART.
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
@@ -952,7 +947,7 @@
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).                                                                                                                  
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
@@ -970,7 +965,7 @@
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
@@ -988,7 +983,7 @@
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
@@ -1006,7 +1001,7 @@
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
@@ -1025,21 +1020,21 @@
   */
 
 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
-  * @param  __PCLK__: UART clock.
-  * @param  __BAUD__: Baud rate set by the user.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
   * @retval Division result
   */
 #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__)   ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
 
 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
-  * @param  __PCLK__: UART clock.
-  * @param  __BAUD__: Baud rate set by the user.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
   * @retval Division result
   */
 #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__)  (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
 
 /** @brief  Check UART Baud rate.
-  * @param  __BAUDRATE__: Baudrate specified by the user.
+  * @param  __BAUDRATE__ Baudrate specified by the user.
   *         The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) 
   *         divided by the smallest oversampling used on the USART (i.e. 8)
   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
@@ -1047,20 +1042,20 @@
 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000001U)
 
 /** @brief  Check UART assertion time.
-  * @param  __TIME__: 5-bit value assertion time.
+  * @param  __TIME__ 5-bit value assertion time.
   * @retval Test result (TRUE or FALSE).
   */
 #define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1F)
 
 /** @brief  Check UART deassertion time.
-  * @param  __TIME__: 5-bit value deassertion time.
+  * @param  __TIME__ 5-bit value deassertion time.
   * @retval Test result (TRUE or FALSE).
   */
 #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
 
 /**
   * @brief Ensure that UART frame number of stop bits is valid.
-  * @param __STOPBITS__: UART frame number of stop bits. 
+  * @param __STOPBITS__ UART frame number of stop bits. 
   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
   */
 #ifdef USART_SMARTCARD_SUPPORT
@@ -1075,7 +1070,7 @@
 
 /**
   * @brief Ensure that UART frame parity is valid.
-  * @param __PARITY__: UART frame parity. 
+  * @param __PARITY__ UART frame parity. 
   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
   */ 
 #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
@@ -1084,7 +1079,7 @@
 
 /**
   * @brief Ensure that UART hardware flow control is valid.
-  * @param __CONTROL__: UART hardware flow control. 
+  * @param __CONTROL__ UART hardware flow control. 
   * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
   */ 
 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
@@ -1095,14 +1090,14 @@
 
 /**
   * @brief Ensure that UART communication mode is valid.
-  * @param __MODE__: UART communication mode. 
+  * @param __MODE__ UART communication mode. 
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */ 
 #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
 
 /**
   * @brief Ensure that UART state is valid.
-  * @param __STATE__: UART state. 
+  * @param __STATE__ UART state. 
   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
   */ 
 #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
@@ -1110,7 +1105,7 @@
 
 /**
   * @brief Ensure that UART oversampling is valid.
-  * @param __SAMPLING__: UART oversampling. 
+  * @param __SAMPLING__ UART oversampling. 
   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
   */ 
 #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
@@ -1118,7 +1113,7 @@
 
 /**
   * @brief Ensure that UART frame sampling is valid.
-  * @param __ONEBIT__: UART frame sampling. 
+  * @param __ONEBIT__ UART frame sampling. 
   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
   */
 #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
@@ -1126,7 +1121,7 @@
 
 /**
   * @brief Ensure that Address Length detection parameter is valid.
-  * @param __ADDRESS__: UART Adress length value. 
+  * @param __ADDRESS__ UART Adress length value. 
   * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
   */
 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
@@ -1134,7 +1129,7 @@
 
 /**
   * @brief Ensure that UART receiver timeout setting is valid.
-  * @param __TIMEOUT__: UART receiver timeout setting. 
+  * @param __TIMEOUT__ UART receiver timeout setting. 
   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
   */
 #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
@@ -1142,7 +1137,7 @@
 
 /**
   * @brief Ensure that UART DMA TX state is valid.
-  * @param __DMATX__: UART DMA TX state. 
+  * @param __DMATX__ UART DMA TX state. 
   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
   */
 #define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
@@ -1150,7 +1145,7 @@
 
 /**
   * @brief Ensure that UART DMA RX state is valid.
-  * @param __DMARX__: UART DMA RX state. 
+  * @param __DMARX__ UART DMA RX state. 
   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
   */
 #define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
@@ -1158,7 +1153,7 @@
 
 /**
   * @brief Ensure that UART half-duplex state is valid.
-  * @param __HDSEL__: UART half-duplex state. 
+  * @param __HDSEL__ UART half-duplex state. 
   * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
   */
 #define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
@@ -1166,7 +1161,7 @@
 
 /**
   * @brief Ensure that UART wake-up method is valid.
-  * @param __WAKEUP__: UART wake-up method . 
+  * @param __WAKEUP__ UART wake-up method . 
   * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
   */
 #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
@@ -1174,7 +1169,7 @@
 
 /**
   * @brief Ensure that UART advanced features initialization is valid.
-  * @param __INIT__: UART advanced features initialization. 
+  * @param __INIT__ UART advanced features initialization. 
   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
   */
 #define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
@@ -1189,7 +1184,7 @@
 
 /**
   * @brief Ensure that UART frame TX inversion setting is valid.
-  * @param __TXINV__: UART frame TX inversion setting. 
+  * @param __TXINV__ UART frame TX inversion setting. 
   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
   */
 #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
@@ -1197,7 +1192,7 @@
 
 /**
   * @brief Ensure that UART frame RX inversion setting is valid.
-  * @param __RXINV__: UART frame RX inversion setting. 
+  * @param __RXINV__ UART frame RX inversion setting. 
   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
   */
 #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
@@ -1205,7 +1200,7 @@
 
 /**
   * @brief Ensure that UART frame data inversion setting is valid.
-  * @param __DATAINV__: UART frame data inversion setting. 
+  * @param __DATAINV__ UART frame data inversion setting. 
   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
   */
 #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
@@ -1213,7 +1208,7 @@
 
 /**
   * @brief Ensure that UART frame RX/TX pins swap setting is valid.
-  * @param __SWAP__: UART frame RX/TX pins swap setting. 
+  * @param __SWAP__ UART frame RX/TX pins swap setting. 
   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
   */
 #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
@@ -1221,7 +1216,7 @@
 
 /**
   * @brief Ensure that UART frame overrun setting is valid.
-  * @param __OVERRUN__: UART frame overrun setting. 
+  * @param __OVERRUN__ UART frame overrun setting. 
   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
   */
 #define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
@@ -1229,7 +1224,7 @@
 
 /**
   * @brief Ensure that UART auto Baud rate state is valid.
-  * @param __AUTOBAUDRATE__: UART auto Baud rate state. 
+  * @param __AUTOBAUDRATE__ UART auto Baud rate state. 
   * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
   */
 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
@@ -1237,7 +1232,7 @@
 
 /**
   * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
-  * @param __DMA__: UART DMA enabling or disabling on error setting. 
+  * @param __DMA__ UART DMA enabling or disabling on error setting. 
   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
   */
 #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
@@ -1245,7 +1240,7 @@
 
 /**
   * @brief Ensure that UART frame MSB first setting is valid.
-  * @param __MSBFIRST__: UART frame MSB first setting. 
+  * @param __MSBFIRST__ UART frame MSB first setting. 
   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
   */
 #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
@@ -1253,7 +1248,7 @@
 
 /**
   * @brief Ensure that UART mute mode state is valid.
-  * @param __MUTE__: UART mute mode state. 
+  * @param __MUTE__ UART mute mode state. 
   * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
   */
 #define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
@@ -1261,7 +1256,7 @@
 
 /**
   * @brief Ensure that UART driver enable polarity is valid.
-  * @param __POLARITY__: UART driver enable polarity. 
+  * @param __POLARITY__ UART driver enable polarity. 
   * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
   */
 #define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_uart_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Extended UART HAL module driver.
   *          This file provides firmware functions to manage the following extended
   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
@@ -165,16 +163,16 @@
 /**
   * @brief Initialize the RS485 Driver enable feature according to the specified
   *         parameters in the UART_InitTypeDef and creates the associated handle.
-  * @param huart: UART handle.
-  * @param Polarity: select the driver enable polarity.
+  * @param huart UART handle.
+  * @param Polarity select the driver enable polarity.
   *        This parameter can be one of the following values:
   *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
   *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
-  * @param AssertionTime: Driver Enable assertion time:
+  * @param AssertionTime Driver Enable assertion time:
   *                         5-bit value defining the time between the activation of the DE (Driver Enable)
   *                         signal and the beginning of the start bit. It is expressed in sample time
   *                         units (1/8 or 1/16 bit time, depending on the oversampling rate)
-  * @param DeassertionTime: Driver Enable deassertion time:
+  * @param DeassertionTime Driver Enable deassertion time:
   *                         5-bit value defining the time between the end of the last stop bit, in a
   *                         transmitted message, and the de-activation of the DE (Driver Enable) signal.
   *                         It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
@@ -249,8 +247,8 @@
 /**
   * @brief Initialize the LIN mode according to the specified
   *        parameters in the UART_InitTypeDef and creates the associated handle .
-  * @param huart: UART handle.
-  * @param BreakDetectLength: specifies the LIN break detection length.
+  * @param huart UART handle.
+  * @param BreakDetectLength specifies the LIN break detection length.
   *        This parameter can be one of the following values:
   *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
   *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
@@ -349,7 +347,7 @@
 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
 /**
   * @brief  UART wakeup from Stop mode callback.
-  * @param  huart: UART handle.
+  * @param  huart UART handle.
   * @retval None
   */
 __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
@@ -393,8 +391,8 @@
 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
 /**
   * @brief Set Wakeup from Stop mode interrupt flag selection.
-  * @param huart: UART handle.
-  * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
+  * @param huart UART handle.
+  * @param WakeUpSelection address match, Start Bit detection or RXNE bit status.
   * This parameter can be one of the following values:
   *      @arg @ref UART_WAKEUP_ON_ADDRESS
   *      @arg @ref UART_WAKEUP_ON_STARTBIT
@@ -454,7 +452,7 @@
 /**
   * @brief Enable UART Stop Mode.
   * @note  The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
@@ -480,7 +478,7 @@
 
 /**
   * @brief Disable UART Stop Mode.
-  * @param huart: UART handle.
+  * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
@@ -512,8 +510,8 @@
   *        long).
   * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 
   *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
-  * @param huart: UART handle.
-  * @param AddressLength: this parameter can be one of the following values:
+  * @param huart UART handle.
+  * @param AddressLength this parameter can be one of the following values:
   *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
   *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
   * @retval HAL status
@@ -548,7 +546,7 @@
 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
 /**
   * @brief  Transmit break characters.
-  * @param  huart: UART handle.
+  * @param  huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
@@ -588,8 +586,8 @@
 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
 /**
   * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
-  * @param huart: UART handle.
-  * @param WakeUpSelection: UART wake up from stop mode parameters.
+  * @param huart UART handle.
+  * @param WakeUpSelection UART wake up from stop mode parameters.
   * @retval None
   */
 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_uart_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of UART HAL Extended module.
   ******************************************************************************
   * @attention
@@ -283,7 +281,7 @@
   */
 
 /** @brief  Flush the UART Data registers.
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
 #if !defined(STM32F030x6) && !defined(STM32F030x8) 
@@ -309,8 +307,8 @@
   */
 
 /** @brief  Report the UART clock source.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __CLOCKSOURCE__: output variable.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
   * @retval UART clocking source, written in __CLOCKSOURCE__.
   */
 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
@@ -619,7 +617,7 @@
   *         by the reception API().
   *         This masking operation is not carried out in the case of
   *         DMA transfers.
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
   */
 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
@@ -693,7 +691,7 @@
 
 /**
   * @brief Ensure that UART frame length is valid.
-  * @param __LENGTH__: UART frame length. 
+  * @param __LENGTH__ UART frame length. 
   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
   */
 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
@@ -711,7 +709,7 @@
 
 /**
   * @brief Ensure that UART auto Baud rate detection mode is valid.
-  * @param __MODE__: UART auto Baud rate detection mode. 
+  * @param __MODE__ UART auto Baud rate detection mode. 
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */
 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
@@ -732,7 +730,7 @@
 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6)  && !defined(STM32F070xB)  && !defined(STM32F030xC)
 /**
   * @brief Ensure that UART LIN state is valid.
-  * @param __LIN__: UART LIN state. 
+  * @param __LIN__ UART LIN state. 
   * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
   */
 #define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
@@ -740,7 +738,7 @@
 
 /**
   * @brief Ensure that UART LIN break detection length is valid.
-  * @param __LENGTH__: UART LIN break detection length. 
+  * @param __LENGTH__ UART LIN break detection length. 
   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
   */
 #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
@@ -749,7 +747,7 @@
 
 /**
   * @brief Ensure that UART request parameter is valid.
-  * @param __PARAM__: UART request parameter. 
+  * @param __PARAM__ UART request parameter. 
   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
   */
 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6)  && !defined(STM32F070xB)  && !defined(STM32F030xC)
@@ -768,7 +766,7 @@
 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB)  && !defined(STM32F030xC)
 /**
   * @brief Ensure that UART stop mode state is valid.
-  * @param __STOPMODE__: UART stop mode state. 
+  * @param __STOPMODE__ UART stop mode state. 
   * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
   */
 #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
@@ -776,7 +774,7 @@
 
 /**
   * @brief Ensure that UART wake-up selection is valid.
-  * @param __WAKE__: UART wake-up selection. 
+  * @param __WAKE__ UART wake-up selection. 
   * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
   */
 #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_usart.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   USART HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
@@ -369,7 +367,7 @@
 
 /**
   * @brief Initialize the USART MSP.
-  * @param husart: USART handle.
+  * @param husart USART handle.
   * @retval None
   */
 __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
@@ -384,7 +382,7 @@
 
 /**
   * @brief DeInitialize the USART MSP.
-  * @param husart: USART handle.
+  * @param husart USART handle.
   * @retval None
   */
 __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
@@ -1108,7 +1106,6 @@
     /* Enable the USART transmit DMA channel: the transmit channel is used in order
        to generate in the non-blocking mode the clock to the slave device,
        this mode isn't a simplex receive mode but a full-duplex receive mode */
-    tmp = (uint32_t*)&pRxData;
     /* Set the USART DMA Tx Complete and Error callback to Null */
     husart->hdmatx->XferErrorCallback = NULL;
     husart->hdmatx->XferHalfCpltCallback = NULL;
@@ -1720,7 +1717,7 @@
 
 /**
   * @brief  Tx Transfer completed callback.
-  * @param  husart: USART handle.
+  * @param  husart USART handle.
   * @retval None
   */
 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
@@ -1735,7 +1732,7 @@
 
 /**
   * @brief  Tx Half Transfer completed callback.
-  * @param  husart: USART handle.
+  * @param  husart USART handle.
   * @retval None
   */
 __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1750,7 +1747,7 @@
 
 /**
   * @brief  Rx Transfer completed callback.
-  * @param  husart: USART handle.
+  * @param  husart USART handle.
   * @retval None
   */
 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
@@ -1765,7 +1762,7 @@
 
 /**
   * @brief  Rx Half Transfer completed callback.
-  * @param  husart: USART handle.
+  * @param  husart USART handle.
   * @retval None
   */
 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1780,7 +1777,7 @@
 
 /**
   * @brief  Tx/Rx Transfers completed callback for the non-blocking process.
-  * @param  husart: USART handle.
+  * @param  husart USART handle.
   * @retval None
   */
 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
@@ -1795,7 +1792,7 @@
 
 /**
   * @brief  USART error callback.
-  * @param  husart: USART handle.
+  * @param  husart USART handle.
   * @retval None
   */
 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
@@ -1846,7 +1843,7 @@
 
 /**
   * @brief  Return the USART handle state.
-  * @param  husart : pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart pointer to a USART_HandleTypeDef structure that contains
   *                  the configuration information for the specified USART.
   * @retval USART handle state
   */
@@ -1857,7 +1854,7 @@
 
 /**
   * @brief  Return the USART error code.
-  * @param  husart : pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart pointer to a USART_HandleTypeDef structure that contains
   *                  the configuration information for the specified USART.
   * @retval USART handle Error Code
   */
@@ -2014,7 +2011,7 @@
 
 /**
   * @brief  DMA USART communication error callback.
-  * @param  hdma: DMA handle.
+  * @param  hdma DMA handle.
   * @retval None
   */
 static void USART_DMAError(DMA_HandleTypeDef *hdma)
@@ -2166,7 +2163,7 @@
 
 /**
   * @brief Configure the USART peripheral.
-  * @param husart: USART handle.
+  * @param husart USART handle.
   * @retval HAL status
   */
 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
@@ -2244,7 +2241,7 @@
 
 /**
   * @brief Check the USART Idle State.
-  * @param husart: USART handle.
+  * @param husart USART handle.
   * @retval HAL status
   */
 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
@@ -2430,7 +2427,7 @@
   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
   * @note   Function called under interruption only, once
   *         interruptions have been enabled by HAL_USART_TransmitReceive_IT().
-  * @param husart: USART handle.
+  * @param husart USART handle.
   * @retval HAL status
   */
 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_usart.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of USART HAL module.
   ******************************************************************************
   * @attention
@@ -308,14 +306,14 @@
   */
 
 /** @brief  Reset USART handle state.
-  * @param  __HANDLE__: USART handle.
+  * @param  __HANDLE__ USART handle.
   * @retval None
   */
 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
 
 /** @brief  Check whether the specified USART flag is set or not.
-  * @param  __HANDLE__: specifies the USART Handle
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the USART Handle
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   @if STM32F030x6
   @elseif STM32F030x8
@@ -341,8 +339,8 @@
 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the specified USART pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg @ref USART_CLEAR_PEF
   *            @arg @ref USART_CLEAR_FEF
@@ -356,38 +354,38 @@
 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
 
 /** @brief  Clear the USART PE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None
   */
 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
 
 /** @brief  Clear the USART FE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None
   */
 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
 
 /** @brief  Clear the USART NE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None
   */
 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
 
 /** @brief  Clear the USART ORE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None
   */
 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
 
 /** @brief  Clear the USART IDLE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None
   */
 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
 
 /** @brief  Enable the specified USART interrupt.
-  * @param  __HANDLE__: specifies the USART Handle.
-  * @param  __INTERRUPT__: specifies the USART interrupt source to enable.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __INTERRUPT__ specifies the USART interrupt source to enable.
   *          This parameter can be one of the following values:
   *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
   *            @arg @ref USART_IT_TC   Transmission complete interrupt
@@ -397,13 +395,13 @@
   *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
   * @retval None
   */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
-                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & 0xFF) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((((__INTERRUPT__) & 0xFF) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                             ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
 
 /** @brief  Disable the specified USART interrupt.
-  * @param  __HANDLE__: specifies the USART Handle.
-  * @param  __INTERRUPT__: specifies the USART interrupt source to disable.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __INTERRUPT__ specifies the USART interrupt source to disable.
   *          This parameter can be one of the following values:
   *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
   *            @arg @ref USART_IT_TC   Transmission complete interrupt
@@ -413,14 +411,14 @@
   *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
   * @retval None
   */
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
-                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & 0xFF) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((((__INTERRUPT__) & 0xFF) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                             ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
 
 
 /** @brief  Check whether the specified USART interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the USART Handle.
-  * @param  __IT__: specifies the USART interrupt source to check.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __IT__ specifies the USART interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
   *            @arg @ref USART_IT_TC  Transmission complete interrupt
@@ -435,8 +433,8 @@
 #define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
 
 /** @brief  Check whether the specified USART interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the USART Handle.
-  * @param  __IT__: specifies the USART interrupt source to check.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __IT__ specifies the USART interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
   *            @arg @ref USART_IT_TC  Transmission complete interrupt
@@ -454,8 +452,8 @@
 
 
 /** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
   *                       to clear the corresponding interrupt.
   *          This parameter can be one of the following values:
   *            @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
@@ -470,8 +468,8 @@
 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
 
 /** @brief  Set a specific USART request flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  * @param  __REQ__: specifies the request flag to set.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __REQ__ specifies the request flag to set.
   *          This parameter can be one of the following values:
   *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
   @if STM32F030x6
@@ -488,25 +486,25 @@
 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (__REQ__))
 
 /** @brief  Enable the USART one bit sample method.
-  * @param  __HANDLE__: specifies the USART Handle.  
+  * @param  __HANDLE__ specifies the USART Handle.  
   * @retval None
   */
 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
 /** @brief  Disable the USART one bit sample method.
-  * @param  __HANDLE__: specifies the USART Handle.  
+  * @param  __HANDLE__ specifies the USART Handle.  
   * @retval None
   */
 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable USART.
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None
   */
 #define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable USART.
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None
   */
 #define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
@@ -521,7 +519,7 @@
   */
 
 /** @brief  Check USART Baud rate.
-  * @param  __BAUDRATE__: Baudrate specified by the user.
+  * @param  __BAUDRATE__ Baudrate specified by the user.
   *         The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
   *         divided by the smallest oversampling used on the USART (i.e. 8)
   * @retval Test result (TRUE or FALSE).
@@ -530,7 +528,7 @@
 
 /**
   * @brief Ensure that USART frame number of stop bits is valid.
-  * @param __STOPBITS__: USART frame number of stop bits. 
+  * @param __STOPBITS__ USART frame number of stop bits. 
   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
   */
 #ifdef USART_SMARTCARD_SUPPORT
@@ -545,7 +543,7 @@
 
 /**
   * @brief Ensure that USART frame parity is valid.
-  * @param __PARITY__: USART frame parity. 
+  * @param __PARITY__ USART frame parity. 
   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
   */ 
 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
@@ -554,14 +552,14 @@
 
 /**
   * @brief Ensure that USART communication mode is valid.
-  * @param __MODE__: USART communication mode. 
+  * @param __MODE__ USART communication mode. 
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */ 
 #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
 
 /**
   * @brief Ensure that USART clock state is valid.
-  * @param __CLOCK__: USART clock state. 
+  * @param __CLOCK__ USART clock state. 
   * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
   */ 
 #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
@@ -569,21 +567,21 @@
 
 /**
   * @brief Ensure that USART frame polarity is valid.
-  * @param __CPOL__: USART frame polarity. 
+  * @param __CPOL__ USART frame polarity. 
   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
   */ 
 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
 
 /**
   * @brief Ensure that USART frame phase is valid.
-  * @param __CPHA__: USART frame phase. 
+  * @param __CPHA__ USART frame phase. 
   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
   */
 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
 
 /**
   * @brief Ensure that USART frame last bit clock pulse setting is valid.
-  * @param __LASTBIT__: USART frame last bit clock pulse setting. 
+  * @param __LASTBIT__ USART frame last bit clock pulse setting. 
   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
   */
 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_usart_ex.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of USART HAL Extended module.
   ******************************************************************************
   * @attention
@@ -125,7 +123,7 @@
   */
 
 /** @brief  Flush the USART Data registers.
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None  
   */
 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6)  && !defined(STM32F070xB)  && !defined(STM32F030xC)
@@ -151,8 +149,8 @@
   */
 
 /** @brief  Report the USART clock source.
-  * @param  __HANDLE__: specifies the USART Handle.
-  * @param  __CLOCKSOURCE__: output variable.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
   * @retval the USART clocking source, written in __CLOCKSOURCE__.
   */
 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
@@ -460,7 +458,7 @@
   *         by the reception API().
   *         This masking operation is not carried out in the case of
   *         DMA transfers.
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
   */
 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
@@ -535,7 +533,7 @@
 
 /**
   * @brief Ensure that USART frame length is valid.
-  * @param __LENGTH__: USART frame length. 
+  * @param __LENGTH__ USART frame length. 
   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
   */
 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
@@ -553,7 +551,7 @@
 
 /**
   * @brief Ensure that USART request parameter is valid.
-  * @param __PARAM__: USART request parameter. 
+  * @param __PARAM__ USART request parameter. 
   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
   */
 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6)  && !defined(STM32F070xB)  && !defined(STM32F030xC)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_wwdg.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   WWDG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Window Watchdog (WWDG) peripheral:

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_wwdg.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    04-November-2016
   * @brief   Header file of WWDG HAL module.
   ******************************************************************************
   * @attention
@@ -176,7 +174,7 @@
 
 /**
   * @brief  Enable the WWDG early wakeup interrupt.
-  * @param  __HANDLE__: WWDG handle
+  * @param  __HANDLE__ WWDG handle
   * @param  __INTERRUPT__  specifies the interrupt to enable.
   *         This parameter can be one of the following values:
   *            @arg WWDG_IT_EWI: Early wakeup interrupt

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_adc.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   ADC LL module driver
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_adc.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of ADC LL module.
   ******************************************************************************
   * @attention
@@ -87,8 +85,8 @@
                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3U))  )
 
 /* Definition of ADC group regular trigger bits information.                  */
-#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */
-#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */
 
 
 
@@ -100,18 +98,18 @@
 /*   GPIO pins) and internal channels (connected to internal paths)           */
 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR1_AWDCH)
 #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_CHSELR_CHSEL)
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
 
 /* Channel differentiation between external and internal channels */
-#define ADC_CHANNEL_ID_INTERNAL_CH         ((uint32_t)0x80000000U) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000U) /* Marker of internal channel */
 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)
 
 /* Definition of channels ID number information to be inserted into           */
 /* channels literals definition.                                              */
-#define ADC_CHANNEL_0_NUMBER               ((uint32_t)0x00000000U)
+#define ADC_CHANNEL_0_NUMBER               (0x00000000U)
 #define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR1_AWDCH_0)
 #define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR1_AWDCH_1                    )
 #define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
@@ -161,7 +159,7 @@
 /*   selection of ADC group (ADC group regular).                              */
 
 /* Internal register offset for ADC analog watchdog channel configuration */
-#define ADC_AWD_CR1_REGOFFSET              ((uint32_t)0x00000000U)
+#define ADC_AWD_CR1_REGOFFSET              (0x00000000U)
 
 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)
 
@@ -174,28 +172,28 @@
 
 
 /* ADC registers bits positions */
-#define ADC_CFGR1_RES_BITOFFSET_POS        ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */
-#define ADC_CFGR1_AWDSGL_BITOFFSET_POS     ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */
-#define ADC_TR_HT_BITOFFSET_POS            ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
-#define ADC_CHSELR_CHSEL0_BITOFFSET_POS    ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */
-#define ADC_CHSELR_CHSEL1_BITOFFSET_POS    ((uint32_t) 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */
-#define ADC_CHSELR_CHSEL2_BITOFFSET_POS    ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */
-#define ADC_CHSELR_CHSEL3_BITOFFSET_POS    ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */
-#define ADC_CHSELR_CHSEL4_BITOFFSET_POS    ((uint32_t) 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */
-#define ADC_CHSELR_CHSEL5_BITOFFSET_POS    ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */
-#define ADC_CHSELR_CHSEL6_BITOFFSET_POS    ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */
-#define ADC_CHSELR_CHSEL7_BITOFFSET_POS    ((uint32_t) 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */
-#define ADC_CHSELR_CHSEL8_BITOFFSET_POS    ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */
-#define ADC_CHSELR_CHSEL9_BITOFFSET_POS    ((uint32_t) 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */
-#define ADC_CHSELR_CHSEL10_BITOFFSET_POS   ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */
-#define ADC_CHSELR_CHSEL11_BITOFFSET_POS   ((uint32_t)11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */
-#define ADC_CHSELR_CHSEL12_BITOFFSET_POS   ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */
-#define ADC_CHSELR_CHSEL13_BITOFFSET_POS   ((uint32_t)13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */
-#define ADC_CHSELR_CHSEL14_BITOFFSET_POS   ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */
-#define ADC_CHSELR_CHSEL15_BITOFFSET_POS   ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */
-#define ADC_CHSELR_CHSEL16_BITOFFSET_POS   ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */
-#define ADC_CHSELR_CHSEL17_BITOFFSET_POS   ((uint32_t)17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */
-#define ADC_CHSELR_CHSEL18_BITOFFSET_POS   ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */
+#define ADC_CFGR1_RES_BITOFFSET_POS        ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */
+#define ADC_CFGR1_AWDSGL_BITOFFSET_POS     (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */
+#define ADC_TR_HT_BITOFFSET_POS            (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
+#define ADC_CHSELR_CHSEL0_BITOFFSET_POS    ( 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */
+#define ADC_CHSELR_CHSEL1_BITOFFSET_POS    ( 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */
+#define ADC_CHSELR_CHSEL2_BITOFFSET_POS    ( 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */
+#define ADC_CHSELR_CHSEL3_BITOFFSET_POS    ( 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */
+#define ADC_CHSELR_CHSEL4_BITOFFSET_POS    ( 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */
+#define ADC_CHSELR_CHSEL5_BITOFFSET_POS    ( 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */
+#define ADC_CHSELR_CHSEL6_BITOFFSET_POS    ( 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */
+#define ADC_CHSELR_CHSEL7_BITOFFSET_POS    ( 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */
+#define ADC_CHSELR_CHSEL8_BITOFFSET_POS    ( 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */
+#define ADC_CHSELR_CHSEL9_BITOFFSET_POS    ( 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */
+#define ADC_CHSELR_CHSEL10_BITOFFSET_POS   (10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */
+#define ADC_CHSELR_CHSEL11_BITOFFSET_POS   (11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */
+#define ADC_CHSELR_CHSEL12_BITOFFSET_POS   (12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */
+#define ADC_CHSELR_CHSEL13_BITOFFSET_POS   (13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */
+#define ADC_CHSELR_CHSEL14_BITOFFSET_POS   (14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */
+#define ADC_CHSELR_CHSEL15_BITOFFSET_POS   (15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */
+#define ADC_CHSELR_CHSEL16_BITOFFSET_POS   (16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */
+#define ADC_CHSELR_CHSEL17_BITOFFSET_POS   (17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */
+#define ADC_CHSELR_CHSEL18_BITOFFSET_POS   (18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */
 
 
 /* ADC registers bits groups */
@@ -204,14 +202,14 @@
 
 /* ADC internal channels related definitions */
 /* Internal voltage reference VrefInt */
-#define VREFINT_CAL_ADDR                   ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define VREFINT_CAL_VREF                   ((uint32_t) 3300U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF                   ( 3300U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
 /* Temperature sensor */
-#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL_VREFANALOG          ((uint32_t) 3300U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG          ( 3300U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
 
 
 /**
@@ -219,19 +217,6 @@
   */
 
 
-#if  defined(USE_FULL_LL_DRIVER)
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Macros ADC Private Macros
-  * @{
-  */
-
-
-/**
-  * @}
-  */
-
-#endif
-
 /* Exported types ------------------------------------------------------------*/
 #if defined(USE_FULL_LL_DRIVER)
 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
@@ -384,7 +369,7 @@
 /* List of ADC registers intended to be used (most commonly) with             */
 /* DMA transfer.                                                              */
 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
-#define LL_ADC_DMA_REG_REGULAR_DATA          ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
 /**
   * @}
   */
@@ -397,7 +382,7 @@
 /*       If they are not listed below, they do not require any specific       */
 /*       path enable. In this case, Access to measurement path is done        */
 /*       only by selecting the corresponding ADC internal channel.            */
-#define LL_ADC_PATH_INTERNAL_NONE          ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_NONE          (0x00000000U)/*!< ADC measurement pathes all disabled */
 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */
 #if defined(ADC_CCR_VBATEN)
@@ -412,7 +397,7 @@
   */
 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CFGR2_CKMODE_1)                                  /*!< ADC synchronous clock derived from AHB clock divided by 4 */
 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CFGR2_CKMODE_0)                                  /*!< ADC synchronous clock derived from AHB clock divided by 2 */
-#define LL_ADC_CLOCK_ASYNC                 ((uint32_t)0x00000000U)                               /*!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. */
+#define LL_ADC_CLOCK_ASYNC                 (0x00000000U)                               /*!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. */
 /**
   * @}
   */
@@ -420,7 +405,7 @@
 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
   * @{
   */
-#define LL_ADC_RESOLUTION_12B              ((uint32_t)0x00000000U)             /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_12B              (0x00000000U)             /*!< ADC resolution 12 bits */
 #define LL_ADC_RESOLUTION_10B              (                  ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
 #define LL_ADC_RESOLUTION_8B               (ADC_CFGR1_RES_1                  ) /*!< ADC resolution  8 bits */
 #define LL_ADC_RESOLUTION_6B               (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution  6 bits */
@@ -431,7 +416,7 @@
 /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
   * @{
   */
-#define LL_ADC_DATA_ALIGN_RIGHT            ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
 #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR1_ALIGN)      /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
 /**
   * @}
@@ -440,7 +425,7 @@
 /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
   * @{
   */
-#define LL_ADC_LP_MODE_NONE                ((uint32_t)0x00000000U)             /*!< No ADC low power mode activated */
+#define LL_ADC_LP_MODE_NONE                (0x00000000U)             /*!< No ADC low power mode activated */
 #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR1_WAIT)                    /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
 #define LL_ADC_LP_AUTOPOWEROFF             (ADC_CFGR1_AUTOFF)                  /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). Note: On STM32F0, if enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) during auto wait phase. */
 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF    (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
@@ -451,7 +436,7 @@
 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
   * @{
   */
-#define LL_ADC_GROUP_REGULAR               ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_REGULAR               (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
 /**
   * @}
   */
@@ -490,7 +475,7 @@
 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
   * @{
   */
-#define LL_ADC_REG_TRIG_SOFTWARE           ((uint32_t)0x00000000U)                                                   /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000U)                                                             /*!< ADC group regular conversion trigger internal: SW start. */
 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4       (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
@@ -513,7 +498,7 @@
 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
 * @{
 */
-#define LL_ADC_REG_CONV_SINGLE             ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_SINGLE             (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR1_CONT)        /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
 /**
   * @}
@@ -522,7 +507,7 @@
 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
   * @{
   */
-#define LL_ADC_REG_DMA_TRANSFER_NONE       ((uint32_t)0x00000000U)              /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000U)              /*!< ADC conversions are not transferred by DMA */
 #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                   ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
 /**
@@ -532,7 +517,7 @@
 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
 * @{
 */
-#define LL_ADC_REG_OVR_DATA_PRESERVED      ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
+#define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR1_OVRMOD)     /*!< ADC group regular behavior in case of overrun: data overwritten */
 /**
   * @}
@@ -541,7 +526,7 @@
 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION  ADC group regular - Sequencer scan direction
   * @{
   */
-#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD    ((uint32_t)0x00000000U)/*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
+#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD    (0x00000000U)/*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD   (ADC_CFGR1_SCANDIR)    /*!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
 /**
   * @}
@@ -550,7 +535,7 @@
 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
   * @{
   */
-#define LL_ADC_REG_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000U)                                                          /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000U)                                                          /*!< ADC group regular sequencer discontinuous mode disable */
 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (ADC_CFGR1_DISCEN)                                                               /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
 /**
   * @}
@@ -559,7 +544,7 @@
 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
   * @{
   */
-#define LL_ADC_SAMPLINGTIME_1CYCLE_5       ((uint32_t)0x00000000U)                               /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000U)                               /*!< Sampling time 1.5 ADC clock cycle */
 #define LL_ADC_SAMPLINGTIME_7CYCLES_5      (ADC_SMPR_SMP_0)                                      /*!< Sampling time 7.5 ADC clock cycles */
 #define LL_ADC_SAMPLINGTIME_13CYCLES_5     (ADC_SMPR_SMP_1)                                      /*!< Sampling time 13.5 ADC clock cycles */
 #define LL_ADC_SAMPLINGTIME_28CYCLES_5     (ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)                     /*!< Sampling time 28.5 ADC clock cycles */
@@ -582,7 +567,7 @@
 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
   * @{
   */
-#define LL_ADC_AWD_DISABLE                 ((uint32_t)0x00000000U)                                                                    /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_DISABLE                 (0x00000000U)                                                                    /*!< ADC analog watchdog monitoring disabled */
 #define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                    ADC_CFGR1_AWDEN                   )   /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
 #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
 #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
@@ -654,13 +639,13 @@
 /* Delay set to maximum value (refer to device datasheet,                     */
 /* parameter "tSTART").                                                       */
 /* Unit: us                                                                   */
-#define LL_ADC_DELAY_VREFINT_STAB_US       ((uint32_t)  10U)  /*!< Delay for internal voltage reference stabilization time */
+#define LL_ADC_DELAY_VREFINT_STAB_US       (  10U)  /*!< Delay for internal voltage reference stabilization time */
 
 /* Delay for temperature sensor stabilization time.                           */
 /* Literal set to maximum value (refer to device datasheet,                   */
 /* parameter "tSTART").                                                       */
 /* Unit: us                                                                   */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ((uint32_t)  10U)  /*!< Delay for temperature sensor stabilization time */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    (  10U)  /*!< Delay for temperature sensor stabilization time */
 
 /* Delay required between ADC end of calibration and ADC enable.              */
 /* Note: On this STM32 serie, a minimum number of ADC clock cycles            */
@@ -669,7 +654,7 @@
 /*       equivalent number of CPU cycles, by taking into account              */
 /*       ratio of CPU clock versus ADC clock prescalers.                      */
 /* Unit: ADC clock cycles.                                                    */
-#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 2U)  /*!< Delay required between ADC end of calibration and ADC enable */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2U)  /*!< Delay required between ADC end of calibration and ADC enable */
 
 /**
   * @}
@@ -821,7 +806,7 @@
   * @note   Example:
   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
-  * @param  __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_ADC_CHANNEL_0
   *         @arg @ref LL_ADC_CHANNEL_1
@@ -1190,7 +1175,7 @@
   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
   */
 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
-  (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))
+  (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))
 
 /**
   * @brief  Helper macro to convert the ADC conversion data from
@@ -1255,7 +1240,7 @@
   *         internal voltage reference VrefInt.
   *         Otherwise, this macro performs the processing to scale
   *         ADC conversion data to 12 bits.
-  * @param  __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
   *         of internal voltage reference VrefInt (unit: digital value).
   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
   *         @arg @ref LL_ADC_RESOLUTION_12B
@@ -2701,7 +2686,7 @@
   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
-  * @param  AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
   * @retval None
   */
 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
@@ -2712,7 +2697,7 @@
   /* data is not shifted.                                                     */
   MODIFY_REG(ADCx->TR,
              AWDThresholdsHighLow,
-             AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & ((uint32_t)0x00000010U)));
+             AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & 0x00000010U));
 }
 
 /**
@@ -2747,7 +2732,7 @@
   /* both thresholds), data is not shifted.                                   */
   return (uint32_t)(READ_BIT(ADCx->TR,
                              (AWDThresholdsHighLow | ADC_TR_LT))
-                    >> ((~AWDThresholdsHighLow) & ((uint32_t)0x00000010U))
+                    >> ((~AWDThresholdsHighLow) & 0x00000010U)
                    );
 }
 
@@ -2896,7 +2881,8 @@
   * @note   On this STM32 serie, setting of this feature is conditioned to
   *         ADC state:
   *         ADC must be enabled without conversion on going on group regular,
-  *         without conversion stop command on going on group regular.
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
   * @param  ADCx ADC instance
   * @retval None

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_bus.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of BUS LL module.
 
   @verbatim                

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_comp.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   COMP LL module driver
   ******************************************************************************
   * @attention
@@ -295,7 +293,7 @@
 
 /**
   * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
-  * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure
+  * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure
   *                         whose fields will be set to default values.
   * @retval None
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_comp.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of COMP LL module.
   ******************************************************************************
   * @attention
@@ -716,7 +714,7 @@
   *         to reach reach propagation delay specification.
   *         Refer to device datasheet, parameter "tSTART".
   * @rmtoll CSR      COMP1EN        LL_COMP_Enable\n
-  *                  COMP2EN        LL_COMP_Enable
+  *         CSR      COMP2EN        LL_COMP_Enable
   * @param  COMPx Comparator instance
   * @retval None
   */
@@ -728,7 +726,7 @@
 /**
   * @brief  Disable comparator instance.
   * @rmtoll CSR      COMP1EN        LL_COMP_Disable\n
-  *                  COMP2EN        LL_COMP_Disable
+  *         CSR      COMP2EN        LL_COMP_Disable
   * @param  COMPx Comparator instance
   * @retval None
   */
@@ -741,7 +739,7 @@
   * @brief  Get comparator enable state
   *         (0: COMP is disabled, 1: COMP is enabled)
   * @rmtoll CSR      COMP1EN        LL_COMP_IsEnabled\n
-  *                  COMP2EN        LL_COMP_IsEnabled
+  *         CSR      COMP2EN        LL_COMP_IsEnabled
   * @param  COMPx Comparator instance
   * @retval State of bit (1 or 0).
   */
@@ -755,7 +753,7 @@
   * @note   Once locked, comparator configuration can be accessed in read-only.
   * @note   The only way to unlock the comparator is a device hardware reset.
   * @rmtoll CSR      COMP1LOCK      LL_COMP_Lock\n
-  *                  COMP2LOCK      LL_COMP_Lock
+  *         CSR      COMP2LOCK      LL_COMP_Lock
   * @param  COMPx Comparator instance
   * @retval None
   */
@@ -770,7 +768,7 @@
   * @note   Once locked, comparator configuration can be accessed in read-only.
   * @note   The only way to unlock the comparator is a device hardware reset.
   * @rmtoll CSR      COMP1LOCK      LL_COMP_IsLocked\n
-  *                  COMP2LOCK      LL_COMP_IsLocked
+  *         CSR      COMP2LOCK      LL_COMP_IsLocked
   * @param  COMPx Comparator instance
   * @retval State of bit (1 or 0).
   */
@@ -794,7 +792,7 @@
   *          - Comparator output is low when the input plus
   *            is at a higher voltage than the input minus
   * @rmtoll CSR      COMP1OUT       LL_COMP_ReadOutputLevel\n
-  *                  COMP2OUT       LL_COMP_ReadOutputLevel
+  *         CSR      COMP2OUT       LL_COMP_ReadOutputLevel
   * @param  COMPx Comparator instance
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_cortex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of CORTEX LL module.
   @verbatim
   ==============================================================================
@@ -83,8 +81,8 @@
 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
   * @{
   */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     ((uint32_t)0x00000000U)                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK          ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_crc.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   CRC LL module driver.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_crc.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of CRC LL module.
   ******************************************************************************
   * @attention
@@ -71,7 +69,7 @@
 /** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
   * @{
   */
-#define LL_CRC_POLYLENGTH_32B              (uint32_t)0x00000000U                    /*!< 32 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */
 #define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
 #define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
 #define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
@@ -83,7 +81,7 @@
 /** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
   * @{
   */
-#define LL_CRC_INDATA_REVERSE_NONE         (uint32_t)0x00000000U                    /*!< Input Data bit order not affected */
+#define LL_CRC_INDATA_REVERSE_NONE         0x00000000U                              /*!< Input Data bit order not affected */
 #define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
 #define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
 #define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
@@ -94,7 +92,7 @@
 /** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
   * @{
   */
-#define LL_CRC_OUTDATA_REVERSE_NONE        (uint32_t)0x00000000U                     /*!< Output Data bit order not affected */
+#define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                               /*!< Output Data bit order not affected */
 #define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
 /**
   * @}
@@ -106,7 +104,7 @@
   *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
   * @{
   */
-#define LL_CRC_DEFAULT_CRC32_POLY          (uint32_t)0x04C11DB7U                     /*!< Default CRC generating polynomial value */
+#define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */
 /**
   * @}
   */
@@ -115,7 +113,7 @@
 /** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
   * @{
   */
-#define LL_CRC_DEFAULT_CRC_INITVALUE       (uint32_t)0xFFFFFFFFU                     /*!< Default CRC computation initialization value */
+#define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_crs.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   CRS LL module driver.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_crs.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of CRS LL module.
   ******************************************************************************
   * @attention
@@ -58,23 +56,7 @@
 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup CRS_LL_Private_Constants CRS Private Constants
-  * @{
-  */
-
-/* Defines used for the bit position in the register and perform offsets*/
-#define CRS_POSITION_TRIM        (uint32_t)8U   /* bit position in CR reg */
-#define CRS_POSITION_FECAP       (uint32_t)16U  /* bit position in ISR reg */
-#define CRS_POSITION_RELOAD      (uint32_t)0U   /* bit position in CFGR reg */
-#define CRS_POSITION_FELIM       (uint32_t)16U  /* bit position in CFGR reg */
-
-
-/**
-  * @}
-  */
-
 /* Private macros ------------------------------------------------------------*/
 
 /* Exported types ------------------------------------------------------------*/
@@ -317,7 +299,7 @@
   */
 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
 {
-  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
 }
 
 /**
@@ -327,7 +309,7 @@
   */
 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
 {
-  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
+  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
 }
 
 /**
@@ -362,7 +344,7 @@
   */
 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
 {
-  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
 }
 
 /**
@@ -372,7 +354,7 @@
   */
 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
 {
-  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
 }
 
 /**
@@ -484,10 +466,10 @@
   */
 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
 {
-  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
   MODIFY_REG(CRS->CFGR, 
              CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, 
-             ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
+             ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
 }
 
 /**
@@ -528,7 +510,7 @@
   */
 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
 {
-  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_dac.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   DAC LL module driver
   ******************************************************************************
   * @attention
@@ -40,7 +38,7 @@
 #include "stm32f0xx_ll_dac.h"
 #include "stm32f0xx_ll_bus.h"
 
-#ifdef  USE_FULL_ASSERT
+#ifdef USE_FULL_ASSERT
   #include "stm32_assert.h"
 #else
   #define assert_param(expr) ((void)0U)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_dac.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of DAC LL module.
   ******************************************************************************
   * @attention
@@ -70,8 +68,8 @@
 /* - channel bits position into register SWTRIG                               */
 /* - channel register offset of data holding register DHRx                    */
 /* - channel register offset of data output register DORx                     */
-#define DAC_CR_CH1_BITOFFSET           ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET           ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CH1_BITOFFSET           0U    /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET           16U   /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
 #define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
 
 #define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
@@ -82,43 +80,43 @@
 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1)
 #endif /* DAC_CHANNEL2_SUPPORT */
 
-#define DAC_REG_DHR12R1_REGOFFSET      ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET      ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET       ((uint32_t)0x02000000U) /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12R1_REGOFFSET      0x00000000U             /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET      0x00100000U             /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET       0x02000000U             /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
 #if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_REG_DHR12R2_REGOFFSET      ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
-#define DAC_REG_DHR12L2_REGOFFSET      ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R2_REGOFFSET       ((uint32_t)0x05000000U) /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12R2_REGOFFSET      0x00030000U             /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET      0x00400000U             /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET       0x05000000U             /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
 #endif /* DAC_CHANNEL2_SUPPORT */
-#define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
-#define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
-#define DAC_REG_DHR8RX_REGOFFSET_MASK  ((uint32_t)0x0F000000U)
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
+#define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000U
 #define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
 
-#define DAC_REG_DOR1_REGOFFSET         ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
+#define DAC_REG_DOR1_REGOFFSET         0x00000000U             /* Register DORx channel 1 taken as reference */
 #if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_REG_DOR2_REGOFFSET         ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
+#define DAC_REG_DOR2_REGOFFSET         0x10000000U             /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
 #else
 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET)
 #endif /* DAC_CHANNEL2_SUPPORT */
 
-#define DAC_REG_REGOFFSET_MASK_POSBIT0 ((uint32_t)0x0000000FU) /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
+#define DAC_REG_REGOFFSET_MASK_POSBIT0             0x0000000FU  /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
 
-#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS ((uint32_t)16U) /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
-#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS ((uint32_t)20U) /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS  ((uint32_t)24U) /* Position of bits register offset of DHR8Rx  channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS    ((uint32_t)28U) /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
+#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS           16U   /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS           20U   /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS            24U   /* Position of bits register offset of DHR8Rx  channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS              28U   /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
 
 /* DAC registers bits positions */
 #if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
-#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
-#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS  ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                16U  /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                20U  /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                  8U  /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
 #endif /* DAC_CHANNEL2_SUPPORT */
 
 /* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS           ((uint32_t)4095U)                     /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+#define DAC_DIGITAL_SCALE_12BITS                        4095U  /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
 
 /**
   * @}
@@ -238,7 +236,7 @@
 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM4_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM6_TRGO          ((uint32_t)0x00000000U)                            /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
@@ -249,7 +247,7 @@
 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
   * @{
   */
-#define LL_DAC_WAVE_AUTO_GENERATION_NONE     ((uint32_t)0x00000000U) /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000U             /*!< DAC channel wave auto generation mode disabled. */
 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (DAC_CR_WAVE1_0)        /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)        /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
 /**
@@ -259,7 +257,7 @@
 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
   * @{
   */
-#define LL_DAC_NOISE_LFSR_UNMASK_BIT0      ((uint32_t)0x00000000U)                                             /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000U                                                         /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
@@ -278,7 +276,7 @@
 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
   * @{
   */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1        ((uint32_t)0x00000000U)                                             /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000U                                                         /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
 #define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
 #define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
 #define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
@@ -297,7 +295,7 @@
 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
   * @{
   */
-#define LL_DAC_OUTPUT_BUFFER_ENABLE        ((uint32_t)0x00000000U) /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000U             /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
 #define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_CR_BOFF1)          /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
 /**
   * @}
@@ -307,8 +305,8 @@
 /** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
   * @{
   */
-#define LL_DAC_RESOLUTION_12B              ((uint32_t)0x00000000U) /*!< DAC channel resolution 12 bits */
-#define LL_DAC_RESOLUTION_8B               ((uint32_t)0x00000002U) /*!< DAC channel resolution 8 bits */
+#define LL_DAC_RESOLUTION_12B              0x00000000U             /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B               0x00000002U             /*!< DAC channel resolution 8 bits */
 /**
   * @}
   */
@@ -346,7 +344,7 @@
 /* Literal set to maximum value (refer to device datasheet,                   */
 /* parameter "tWAKEUP").                                                      */
 /* Unit: us                                                                   */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 15U)  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             15U  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
 
 /* Delay for DAC channel voltage settling time.                               */
 /* Note: DAC channel startup time depends on board application environment:   */
@@ -359,7 +357,7 @@
 /* Literal set to maximum value (refer to device datasheet,                   */
 /* parameter "tSETTLING").                                                    */
 /* Unit: us                                                                   */
-#define LL_DAC_DELAY_VOLTAGE_SETTLING_US  ((uint32_t) 12U)  /*!< Delay for DAC channel voltage settling time */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US                    12U  /*!< Delay for DAC channel voltage settling time */
 /**
   * @}
   */
@@ -479,7 +477,7 @@
   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
   */
 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
-  (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
+  ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
 
 /**
   * @brief  Helper macro to calculate the DAC conversion data (unit: digital

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_dma.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   DMA LL module driver.
   ******************************************************************************
   * @attention
@@ -83,7 +81,7 @@
                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
 
-#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= (uint32_t)0x0000FFFFU)
+#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
 
 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      (((__VALUE__) == LL_DMA_REQUEST_0)  || \
@@ -359,7 +357,7 @@
 
 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
   /*--------------------------- DMAx CSELR Configuration -----------------------
-   * Configure the peripheral base address with parameter :
+   * Configure the DMA request for DMA instance on Channel x with parameter :
    * - PeriphRequest: DMA_CSELR[31:0] bits
    */
   LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
@@ -376,15 +374,15 @@
 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
 {
   /* Set DMA_InitStruct fields to default values */
-  DMA_InitStruct->PeriphOrM2MSrcAddress  = (uint32_t)0x00000000U;
-  DMA_InitStruct->MemoryOrM2MDstAddress  = (uint32_t)0x00000000U;
+  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
+  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
-  DMA_InitStruct->NbData                 = (uint32_t)0x00000000U;
+  DMA_InitStruct->NbData                 = 0x00000000U;
 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
   DMA_InitStruct->PeriphRequest          = LL_DMA_REQUEST_0;
 #endif

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_dma.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of DMA LL module.
   ******************************************************************************
   * @attention
@@ -280,19 +278,19 @@
 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
   * @{
   */
-#define LL_DMA_CHANNEL_1                  ((uint32_t)0x00000001U) /*!< DMA Channel 1 */
-#define LL_DMA_CHANNEL_2                  ((uint32_t)0x00000002U) /*!< DMA Channel 2 */
-#define LL_DMA_CHANNEL_3                  ((uint32_t)0x00000003U) /*!< DMA Channel 3 */
-#define LL_DMA_CHANNEL_4                  ((uint32_t)0x00000004U) /*!< DMA Channel 4 */
-#define LL_DMA_CHANNEL_5                  ((uint32_t)0x00000005U) /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_1                  0x00000001U /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2                  0x00000002U /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3                  0x00000003U /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4                  0x00000004U /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5                  0x00000005U /*!< DMA Channel 5 */
 #if defined(DMA1_Channel6)
-#define LL_DMA_CHANNEL_6                  ((uint32_t)0x00000006U) /*!< DMA Channel 6 */
+#define LL_DMA_CHANNEL_6                  0x00000006U /*!< DMA Channel 6 */
 #endif
 #if defined(DMA1_Channel7)
-#define LL_DMA_CHANNEL_7                  ((uint32_t)0x00000007U) /*!< DMA Channel 7 */
+#define LL_DMA_CHANNEL_7                  0x00000007U /*!< DMA Channel 7 */
 #endif
 #if defined(USE_FULL_LL_DRIVER)
-#define LL_DMA_CHANNEL_ALL                ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
+#define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
 #endif /*USE_FULL_LL_DRIVER*/
 /**
   * @}
@@ -301,7 +299,7 @@
 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
   * @{
   */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
 /**
@@ -311,7 +309,7 @@
 /** @defgroup DMA_LL_EC_MODE Transfer mode
   * @{
   */
-#define LL_DMA_MODE_NORMAL                ((uint32_t)0x00000000U) /*!< Normal Mode                  */
+#define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
 #define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
 /**
   * @}
@@ -321,7 +319,7 @@
   * @{
   */
 #define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
-#define LL_DMA_PERIPH_NOINCREMENT         ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
+#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
 /**
   * @}
   */
@@ -330,7 +328,7 @@
   * @{
   */
 #define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
-#define LL_DMA_MEMORY_NOINCREMENT         ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
+#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
 /**
   * @}
   */
@@ -338,7 +336,7 @@
 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
   * @{
   */
-#define LL_DMA_PDATAALIGN_BYTE            ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
 #define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
 #define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
 /**
@@ -348,7 +346,7 @@
 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
   * @{
   */
-#define LL_DMA_MDATAALIGN_BYTE            ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
 #define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
 #define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
 /**
@@ -358,7 +356,7 @@
 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
   * @{
   */
-#define LL_DMA_PRIORITY_LOW               ((uint32_t)0x00000000U) /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
 #define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
 #define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
 #define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
@@ -370,22 +368,22 @@
 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
   * @{
   */
-#define LL_DMA_REQUEST_0                  ((uint32_t)0x00000000U) /*!< DMA peripheral request 0  */
-#define LL_DMA_REQUEST_1                  ((uint32_t)0x00000001U) /*!< DMA peripheral request 1  */
-#define LL_DMA_REQUEST_2                  ((uint32_t)0x00000002U) /*!< DMA peripheral request 2  */
-#define LL_DMA_REQUEST_3                  ((uint32_t)0x00000003U) /*!< DMA peripheral request 3  */
-#define LL_DMA_REQUEST_4                  ((uint32_t)0x00000004U) /*!< DMA peripheral request 4  */
-#define LL_DMA_REQUEST_5                  ((uint32_t)0x00000005U) /*!< DMA peripheral request 5  */
-#define LL_DMA_REQUEST_6                  ((uint32_t)0x00000006U) /*!< DMA peripheral request 6  */
-#define LL_DMA_REQUEST_7                  ((uint32_t)0x00000007U) /*!< DMA peripheral request 7  */
-#define LL_DMA_REQUEST_8                  ((uint32_t)0x00000008U) /*!< DMA peripheral request 8  */
-#define LL_DMA_REQUEST_9                  ((uint32_t)0x00000009U) /*!< DMA peripheral request 9  */
-#define LL_DMA_REQUEST_10                 ((uint32_t)0x0000000AU) /*!< DMA peripheral request 10 */
-#define LL_DMA_REQUEST_11                 ((uint32_t)0x0000000BU) /*!< DMA peripheral request 11 */
-#define LL_DMA_REQUEST_12                 ((uint32_t)0x0000000CU) /*!< DMA peripheral request 12 */
-#define LL_DMA_REQUEST_13                 ((uint32_t)0x0000000DU) /*!< DMA peripheral request 13 */
-#define LL_DMA_REQUEST_14                 ((uint32_t)0x0000000EU) /*!< DMA peripheral request 14 */
-#define LL_DMA_REQUEST_15                 ((uint32_t)0x0000000FU) /*!< DMA peripheral request 15 */
+#define LL_DMA_REQUEST_0                  0x00000000U /*!< DMA peripheral request 0  */
+#define LL_DMA_REQUEST_1                  0x00000001U /*!< DMA peripheral request 1  */
+#define LL_DMA_REQUEST_2                  0x00000002U /*!< DMA peripheral request 2  */
+#define LL_DMA_REQUEST_3                  0x00000003U /*!< DMA peripheral request 3  */
+#define LL_DMA_REQUEST_4                  0x00000004U /*!< DMA peripheral request 4  */
+#define LL_DMA_REQUEST_5                  0x00000005U /*!< DMA peripheral request 5  */
+#define LL_DMA_REQUEST_6                  0x00000006U /*!< DMA peripheral request 6  */
+#define LL_DMA_REQUEST_7                  0x00000007U /*!< DMA peripheral request 7  */
+#define LL_DMA_REQUEST_8                  0x00000008U /*!< DMA peripheral request 8  */
+#define LL_DMA_REQUEST_9                  0x00000009U /*!< DMA peripheral request 9  */
+#define LL_DMA_REQUEST_10                 0x0000000AU /*!< DMA peripheral request 10 */
+#define LL_DMA_REQUEST_11                 0x0000000BU /*!< DMA peripheral request 11 */
+#define LL_DMA_REQUEST_12                 0x0000000CU /*!< DMA peripheral request 12 */
+#define LL_DMA_REQUEST_13                 0x0000000DU /*!< DMA peripheral request 13 */
+#define LL_DMA_REQUEST_14                 0x0000000EU /*!< DMA peripheral request 14 */
+#define LL_DMA_REQUEST_15                 0x0000000FU /*!< DMA peripheral request 15 */
 /**
   * @}
   */
@@ -1054,7 +1052,8 @@
 
 /**
   * @brief  Configure the Source and Destination addresses.
-  * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
   * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
   *         CMAR         MA            LL_DMA_ConfigAddresses
   * @param  DMAx DMAx Instance
@@ -1080,24 +1079,21 @@
   /* Direction Memory to Periph */
   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
   {
-    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
-               SrcAddress);
-    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
-               DstAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
   }
   /* Direction Periph to Memory and Memory to Memory */
   else
   {
-    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
-               SrcAddress);
-    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
-               DstAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
   }
 }
 
 /**
   * @brief  Set the Memory address.
   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
   * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
   * @param  DMAx DMAx Instance
   * @param  Channel This parameter can be one of the following values:
@@ -1113,13 +1109,13 @@
   */
 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
 {
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
-             MemoryAddress);
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
 }
 
 /**
   * @brief  Set the Peripheral address.
   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
   * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
   * @param  DMAx DMAx Instance
   * @param  Channel This parameter can be one of the following values:
@@ -1135,8 +1131,7 @@
   */
 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
 {
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
-             PeriphAddress);
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
 }
 
 /**
@@ -1156,8 +1151,7 @@
   */
 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
 {
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
-                   DMA_CMAR_MA));
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
 }
 
 /**
@@ -1177,13 +1171,13 @@
   */
 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
 {
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
-                   DMA_CPAR_PA));
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
 }
 
 /**
   * @brief  Set the Memory to Memory Source address.
   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
   * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
   * @param  DMAx DMAx Instance
   * @param  Channel This parameter can be one of the following values:
@@ -1199,13 +1193,13 @@
   */
 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
 {
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
-             MemoryAddress);
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
 }
 
 /**
   * @brief  Set the Memory to Memory Destination address.
   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
   * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
   * @param  DMAx DMAx Instance
   * @param  Channel This parameter can be one of the following values:
@@ -1221,8 +1215,7 @@
   */
 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
 {
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
-             MemoryAddress);
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
 }
 
 /**
@@ -1242,8 +1235,7 @@
   */
 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
 {
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
-                   DMA_CPAR_PA));
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
 }
 
 /**
@@ -1263,8 +1255,7 @@
   */
 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
 {
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
-                   DMA_CMAR_MA));
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
 }
 
 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
@@ -1695,7 +1686,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
 }
 
 /**
@@ -1706,7 +1697,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
 }
 
 /**
@@ -1717,7 +1708,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
 }
 
 /**
@@ -1728,7 +1719,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
 }
 
 /**
@@ -1739,7 +1730,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
 }
 
 #if defined(DMA1_Channel6)
@@ -1751,7 +1742,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
 }
 #endif
 
@@ -1764,7 +1755,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
 }
 #endif
 
@@ -1776,7 +1767,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
 }
 
 /**
@@ -1787,7 +1778,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
 }
 
 /**
@@ -1798,7 +1789,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
 }
 
 /**
@@ -1809,7 +1800,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
 }
 
 /**
@@ -1820,7 +1811,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
 }
 
 #if defined(DMA1_Channel6)
@@ -1832,7 +1823,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
 }
 #endif
 
@@ -1845,7 +1836,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
 }
 #endif
 
@@ -1857,7 +1848,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
 }
 
 /**
@@ -1868,7 +1859,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
 }
 
 /**
@@ -1879,7 +1870,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
 }
 
 /**
@@ -1890,7 +1881,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
 }
 
 /**
@@ -1901,7 +1892,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
 }
 
 #if defined(DMA1_Channel6)
@@ -1913,7 +1904,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
 }
 #endif
 
@@ -1926,7 +1917,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
 }
 #endif
 
@@ -1938,7 +1929,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
 }
 
 /**
@@ -1949,7 +1940,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
 }
 
 /**
@@ -1960,7 +1951,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
 }
 
 /**
@@ -1971,7 +1962,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
 }
 
 /**
@@ -1982,7 +1973,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
 }
 
 #if defined(DMA1_Channel6)
@@ -1994,7 +1985,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
 }
 #endif
 
@@ -2007,7 +1998,7 @@
   */
 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
 {
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
 }
 #endif
 

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_exti.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   EXTI LL module driver.
   ******************************************************************************
   * @attention
@@ -115,7 +113,7 @@
   LL_EXTI_WriteReg(FTSR,  0x00000000U);
   /* Software interrupt event register set to default reset values */
   LL_EXTI_WriteReg(SWIER, 0x00000000U);
-  /* Pending register set to default reset values */
+  /* Pending register clear */
   LL_EXTI_WriteReg(PR,    0x007BFFFFU);
 
   return SUCCESS;

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_exti.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of EXTI LL module.
   ******************************************************************************
   * @attention
@@ -122,7 +120,9 @@
 #define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
 #endif
 #define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
 #define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
+#endif
 #define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
 #if defined(EXTI_IMR_IM20)
 #define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
@@ -161,10 +161,10 @@
 #define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
 
 
-#define LL_EXTI_LINE_ALL               ((uint32_t)0xFFFFFFFFU)  /*!< All Extended line */
+#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
 
 #if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE              ((uint32_t)0x00000000U)  /*!< None Extended line */
+#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
 #endif /*USE_FULL_LL_DRIVER*/
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_gpio.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   GPIO LL module driver.
   ******************************************************************************
   * @attention
@@ -62,7 +60,7 @@
 /** @addtogroup GPIO_LL_Private_Macros
   * @{
   */
-#define IS_LL_GPIO_PIN(__VALUE__)          ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
 
 #define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
                                             ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
@@ -74,8 +72,7 @@
 
 #define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
 
 #define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
                                             ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
@@ -166,7 +163,7 @@
 /**
   * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
   * @param  GPIOx GPIO Port
-  * @param  GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+  * @param  GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
   *         that contains the configuration information for the specified GPIO peripheral.
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
@@ -243,7 +240,7 @@
 
 /**
   * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
-  * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
   *                          whose fields will be set to default values.
   * @retval None
   */
@@ -280,4 +277,3 @@
 #endif /* USE_FULL_LL_DRIVER */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_gpio.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of GPIO LL module.
   ******************************************************************************
   * @attention
@@ -152,7 +150,7 @@
 /** @defgroup GPIO_LL_EC_MODE Mode
   * @{
   */
-#define LL_GPIO_MODE_INPUT                 ((uint32_t)0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
 #define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */
 #define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode */
 #define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */
@@ -163,7 +161,7 @@
 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
   * @{
   */
-#define LL_GPIO_OUTPUT_PUSHPULL            ((uint32_t)0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
 #define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
 /**
   * @}
@@ -172,23 +170,20 @@
 /** @defgroup GPIO_LL_EC_SPEED Output Speed
   * @{
   */
-#define LL_GPIO_SPEED_FREQ_LOW             ((uint32_t)0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
 #define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEEDR0_1 /*!< Select I/O fast output speed   */
-#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEEDR0   /*!< Select I/O high output speed   */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEEDR0   /*!< Select I/O high output speed   */
 /**
   * @}
   */
 #define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
 #define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
-#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
-#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
-
+#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_HIGH
 
 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
   * @{
   */
-#define LL_GPIO_PULL_NO                    ((uint32_t)0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
 #define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
 #define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
 /**
@@ -198,14 +193,14 @@
 /** @defgroup GPIO_LL_EC_AF Alternate Function
   * @{
   */
-#define LL_GPIO_AF_0                       ((uint32_t)0x0000000U) /*!< Select alternate function 0 */
-#define LL_GPIO_AF_1                       ((uint32_t)0x0000001U) /*!< Select alternate function 1 */
-#define LL_GPIO_AF_2                       ((uint32_t)0x0000002U) /*!< Select alternate function 2 */
-#define LL_GPIO_AF_3                       ((uint32_t)0x0000003U) /*!< Select alternate function 3 */
-#define LL_GPIO_AF_4                       ((uint32_t)0x0000004U) /*!< Select alternate function 4 */
-#define LL_GPIO_AF_5                       ((uint32_t)0x0000005U) /*!< Select alternate function 5 */
-#define LL_GPIO_AF_6                       ((uint32_t)0x0000006U) /*!< Select alternate function 6 */
-#define LL_GPIO_AF_7                       ((uint32_t)0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
 /**
   * @}
   */
@@ -422,7 +417,6 @@
   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
   * @retval None
   */
 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
@@ -459,7 +453,6 @@
   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
   */
 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
 {
@@ -559,7 +552,7 @@
   */
 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
 {
-  MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFRL0),
+  MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
              ((((Pin * Pin) * Pin) * Pin) * Alternate));
 }
 
@@ -589,7 +582,7 @@
 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
 {
   return (uint32_t)(READ_BIT(GPIOx->AFR[0],
-                             ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFRL0)) / (((Pin * Pin) * Pin) * Pin));
+                             ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
 }
 
 /**
@@ -620,7 +613,7 @@
   */
 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
 {
-  MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFRH0),
+  MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
              (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
 }
 
@@ -651,7 +644,7 @@
 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
 {
   return (uint32_t)(READ_BIT(GPIOx->AFR[1],
-                             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFRH0)) / ((((Pin >> 8U) *
+                             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
                                  (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
 }
 

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_i2c.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   I2C LL module driver.
   ******************************************************************************
   * @attention
@@ -73,7 +71,7 @@
 
 #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
 
-#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= (uint32_t)0x000003FFU)
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
 
 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
                                                  ((__VALUE__) == LL_I2C_NACK))
@@ -184,7 +182,12 @@
    */
   LL_I2C_DisableOwnAddress1(I2Cx);
   LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
-  LL_I2C_EnableOwnAddress1(I2Cx);
+
+  /* OwnAdress1 == 0 is reserved for General Call address */
+  if (I2C_InitStruct->OwnAddress1 != 0U)
+  {
+    LL_I2C_EnableOwnAddress1(I2Cx);
+  }
 
   /*---------------------------- I2Cx MODE Configuration -----------------------
   * Configure I2Cx peripheral mode with parameter :

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_i2c.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of I2C LL module.
   ******************************************************************************
   * @attention
@@ -63,16 +61,6 @@
 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
   * @{
   */
-/* Defines used for the bit position in the register and perform offsets */
-#define I2C_POSITION_CR1_DNF            (uint32_t)8U
-#define I2C_POSITION_CR2_NBYTES         (uint32_t)16U
-#define I2C_POSITION_TIMINGR_PRESC      (uint32_t)28U
-#define I2C_POSITION_TIMINGR_SCLDEL     (uint32_t)20U
-#define I2C_POSITION_TIMINGR_SDADEL     (uint32_t)16U
-#define I2C_POSITION_TIMINGR_SCLH       (uint32_t)8U
-#define I2C_POSITION_TIMINGR_SCLL       (uint32_t)0U
-#define I2C_POSITION_ISR_ADDCODE        (uint32_t)17U
-#define I2C_POSITION_TIMEOUTR_TIMEOUTB  (uint32_t)16U
 /**
   * @}
   */
@@ -198,9 +186,9 @@
 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
   * @{
   */
-#define LL_I2C_MODE_I2C                    ((uint32_t)0x00000000U)  /*!< I2C Master or Slave mode                                    */
+#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                                    */
 #define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge                              */
-#define LL_I2C_MODE_SMBUS_DEVICE           ((uint32_t)0x00000000U)  /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode (Default address not acknowledge) */
 #define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge                    */
 /**
   * @}
@@ -209,7 +197,7 @@
 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
   * @{
   */
-#define LL_I2C_ANALOGFILTER_ENABLE          ((uint32_t)0x00000000U) /*!< Analog filter is enabled.  */
+#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
 #define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
 /**
   * @}
@@ -218,7 +206,7 @@
 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
   * @{
   */
-#define LL_I2C_ADDRESSING_MODE_7BIT         ((uint32_t) 0x00000000U) /*!< Master operates in 7-bit addressing mode. */
+#define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
 #define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
 /**
   * @}
@@ -227,7 +215,7 @@
 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
   * @{
   */
-#define LL_I2C_OWNADDRESS1_7BIT             ((uint32_t)0x00000000U) /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
 #define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
 /**
   * @}
@@ -251,7 +239,7 @@
 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
   * @{
   */
-#define LL_I2C_ACK                          ((uint32_t) 0x00000000U) /*!< ACK is sent after current received byte. */
+#define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
 #define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
 /**
   * @}
@@ -260,7 +248,7 @@
 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
   * @{
   */
-#define LL_I2C_ADDRSLAVE_7BIT               ((uint32_t)0x00000000U)  /*!< Slave Address in 7-bit. */
+#define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
 #define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
 /**
   * @}
@@ -269,7 +257,7 @@
 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
   * @{
   */
-#define LL_I2C_REQUEST_WRITE                ((uint32_t)0x00000000U)  /*!< Master request a write transfer. */
+#define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
 #define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
 /**
   * @}
@@ -280,7 +268,7 @@
   */
 #define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD                                      /*!< Enable I2C Reload mode.                                   */
 #define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND                                     /*!< Enable I2C Automatic end mode with no HW PEC comparison.  */
-#define LL_I2C_MODE_SOFTEND                 ((uint32_t)0x00000000U)                             /*!< Enable I2C Software end mode with no HW PEC comparison.   */
+#define LL_I2C_MODE_SOFTEND                 0x00000000U                                         /*!< Enable I2C Software end mode with no HW PEC comparison.   */
 #define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD                                  /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND                                 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND                                 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
@@ -293,7 +281,7 @@
 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
   * @{
   */
-#define LL_I2C_GENERATE_NOSTARTSTOP         ((uint32_t)0x00000000U)                                      /*!< Don't Generate Stop and Start condition.                */
+#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U                                                  /*!< Don't Generate Stop and Start condition.                */
 #define LL_I2C_GENERATE_STOP                I2C_CR2_STOP                                                 /*!< Generate Stop condition (Size should be set to 0).      */
 #define LL_I2C_GENERATE_START_READ          (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Start for read request.                        */
 #define LL_I2C_GENERATE_START_WRITE         I2C_CR2_START                                                /*!< Generate Start for write request.                       */
@@ -308,7 +296,7 @@
 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
   * @{
   */
-#define LL_I2C_DIRECTION_WRITE              ((uint32_t)0x00000000U)  /*!< Write transfer request by master, slave enters receiver mode.  */
+#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master, slave enters receiver mode.  */
 #define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master, slave enters transmitter mode.*/
 /**
   * @}
@@ -317,8 +305,8 @@
 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
   * @{
   */
-#define LL_I2C_DMA_REG_DATA_TRANSMIT        ((uint32_t)0x00000000U)  /*!< Get address of data register used for transmission */
-#define LL_I2C_DMA_REG_DATA_RECEIVE         ((uint32_t)0x00000001U)  /*!< Get address of data register used for reception */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for reception */
 /**
   * @}
   */
@@ -326,7 +314,7 @@
 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
   * @{
   */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW  ((uint32_t) 0x00000000U) /*!< TimeoutA is used to detect SCL low level timeout.              */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect SCL low level timeout.              */
 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
 /**
   * @}
@@ -388,11 +376,11 @@
   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
   */
 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)   \
-        ((((uint32_t)(__PRESCALER__)         << I2C_POSITION_TIMINGR_PRESC)  & I2C_TIMINGR_PRESC)   | \
-         (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL)  | \
-         (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL)  | \
-         (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH)   & I2C_TIMINGR_SCLH)    | \
-         (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_POSITION_TIMINGR_SCLL)   & I2C_TIMINGR_SCLL))
+        ((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
+         (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
+         (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
+         (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
+         (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
 /**
   * @}
   */
@@ -463,7 +451,7 @@
   */
 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
 {
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_POSITION_CR1_DNF));
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
 }
 
 /**
@@ -479,7 +467,7 @@
   */
 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
 {
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_POSITION_CR1_DNF);
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
 }
 
 /**
@@ -490,7 +478,7 @@
   */
 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
 {
-  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_POSITION_CR1_DNF);
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
 }
 
 /**
@@ -922,7 +910,7 @@
   */
 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
 {
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_POSITION_TIMINGR_PRESC);
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
 }
 
 /**
@@ -933,7 +921,7 @@
   */
 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
 {
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_POSITION_TIMINGR_SCLL);
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
 }
 
 /**
@@ -944,7 +932,7 @@
   */
 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
 {
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_POSITION_TIMINGR_SCLH);
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
 }
 
 /**
@@ -955,7 +943,7 @@
   */
 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
 {
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_POSITION_TIMINGR_SDADEL);
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
 }
 
 /**
@@ -966,7 +954,7 @@
   */
 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
 {
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_POSITION_TIMINGR_SCLDEL);
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
 }
 
 /**
@@ -1114,7 +1102,7 @@
                                                uint32_t TimeoutB)
 {
   MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
-             TimeoutA | TimeoutAMode | (TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB));
+             TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
 }
 
 /**
@@ -1189,7 +1177,7 @@
   */
 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
 {
-  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB);
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
 }
 
 /**
@@ -1202,7 +1190,7 @@
   */
 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
 {
-  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_POSITION_TIMEOUTR_TIMEOUTB);
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
 }
 
 /**
@@ -1938,7 +1926,7 @@
   */
 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
 {
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_POSITION_CR2_NBYTES);
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
 }
 
 /**
@@ -1949,7 +1937,7 @@
   */
 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
 {
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_POSITION_CR2_NBYTES);
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
 }
 
 /**
@@ -2122,7 +2110,7 @@
 {
   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
-             SlaveAddr | SlaveAddrSize | TransferSize << I2C_POSITION_CR2_NBYTES | EndMode | Request);
+             SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
 }
 
 /**
@@ -2148,7 +2136,7 @@
   */
 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
 {
-  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_POSITION_ISR_ADDCODE << 1);
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_iwdg.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of IWDG LL module.
   ******************************************************************************
   * @attention
@@ -64,10 +62,10 @@
   * @{
   */
 
-#define LL_IWDG_KEY_RELOAD                 ((uint32_t)0x0000AAAAU)               /*!< IWDG Reload Counter Enable   */
-#define LL_IWDG_KEY_ENABLE                 ((uint32_t)0x0000CCCCU)               /*!< IWDG Peripheral Enable       */
-#define LL_IWDG_KEY_WR_ACCESS_ENABLE       ((uint32_t)0x00005555U)               /*!< IWDG KR Write Access Enable  */
-#define LL_IWDG_KEY_WR_ACCESS_DISABLE      ((uint32_t)0x00000000U)               /*!< IWDG KR Write Access Disable */
+#define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
+#define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
 
 /**
   * @}
@@ -96,7 +94,7 @@
 /** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
   * @{
   */
-#define LL_IWDG_PRESCALER_4                ((uint32_t)0x00000000U)               /*!< Divider by 4   */
+#define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
 #define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
 #define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
 #define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_pwr.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   PWR LL module driver.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_pwr.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of PWR LL module.
   ******************************************************************************
   * @attention
@@ -58,11 +56,8 @@
 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-
 /* Private constants ---------------------------------------------------------*/
-
 /* Private macros ------------------------------------------------------------*/
-
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
@@ -85,30 +80,30 @@
   */
 #define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
 #define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
-#if defined (PWR_PVD_SUPPORT)
+#if defined(PWR_PVD_SUPPORT)
 #define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
-#endif
-#if defined (PWR_CSR_VREFINTRDYF)
+#endif /* PWR_PVD_SUPPORT */
+#if defined(PWR_CSR_VREFINTRDYF)
 #define LL_PWR_CSR_VREFINTRDYF             PWR_CSR_VREFINTRDYF    /*!< VREFINT ready flag */
-#endif
+#endif /* PWR_CSR_VREFINTRDYF */
 #define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
 #define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
-#if defined (PWR_CSR_EWUP3)
+#if defined(PWR_CSR_EWUP3)
 #define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
 #endif /* PWR_CSR_EWUP3 */
-#if defined (PWR_CSR_EWUP4)
+#if defined(PWR_CSR_EWUP4)
 #define LL_PWR_CSR_EWUP4                   PWR_CSR_EWUP4          /*!< Enable WKUP pin 4 */
 #endif /* PWR_CSR_EWUP4 */
-#if defined (PWR_CSR_EWUP5)
+#if defined(PWR_CSR_EWUP5)
 #define LL_PWR_CSR_EWUP5                   PWR_CSR_EWUP5          /*!< Enable WKUP pin 5 */
 #endif /* PWR_CSR_EWUP5 */
-#if defined (PWR_CSR_EWUP6)
+#if defined(PWR_CSR_EWUP6)
 #define LL_PWR_CSR_EWUP6                   PWR_CSR_EWUP6          /*!< Enable WKUP pin 6 */
 #endif /* PWR_CSR_EWUP6 */
-#if defined (PWR_CSR_EWUP7)
+#if defined(PWR_CSR_EWUP7)
 #define LL_PWR_CSR_EWUP7                   PWR_CSR_EWUP7          /*!< Enable WKUP pin 7 */
 #endif /* PWR_CSR_EWUP7 */
-#if defined (PWR_CSR_EWUP8)
+#if defined(PWR_CSR_EWUP8)
 #define LL_PWR_CSR_EWUP8                   PWR_CSR_EWUP8          /*!< Enable WKUP pin 8 */
 #endif /* PWR_CSR_EWUP8 */
 /**
@@ -119,9 +114,9 @@
 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
   * @{
   */
-#define LL_PWR_MODE_STOP_MAINREGU          ((uint32_t)0x00000000U)        /*!< Enter Stop mode when the CPU enters deepsleep */
-#define LL_PWR_MODE_STOP_LPREGU            (PWR_CR_LPDS)                  /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */
-#define LL_PWR_MODE_STANDBY                (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
 /**
   * @}
   */
@@ -130,14 +125,14 @@
 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
  * @{
  */
-#define LL_PWR_REGU_DSMODE_MAIN       ((uint32_t)0x00000000U)        /*!< Voltage regulator in main mode during deepsleep mode */
-#define LL_PWR_REGU_DSMODE_LOW_POWER  (PWR_CR_LPDS)                  /*!< Voltage regulator in low-power mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
 /**
- * @}
- */
+  * @}
+  */
 #endif /* PWR_CR_LPDS */
 
-#if defined (PWR_PVD_SUPPORT)
+#if defined(PWR_PVD_SUPPORT)
 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
   * @{
   */
@@ -152,29 +147,28 @@
 /**
   * @}
   */
-#endif
-
+#endif /* PWR_PVD_SUPPORT */
 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
-* @{
-*/
+  * @{
+  */
 #define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
 #define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC13 */
-#if defined (PWR_CSR_EWUP3)
+#if defined(PWR_CSR_EWUP3)
 #define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PE6 or PA2 according to device */
 #endif /* PWR_CSR_EWUP3 */
-#if defined (PWR_CSR_EWUP4)
+#if defined(PWR_CSR_EWUP4)
 #define LL_PWR_WAKEUP_PIN4                 (PWR_CSR_EWUP4)        /*!< WKUP pin 4 : LLG TBD */
 #endif /* PWR_CSR_EWUP4 */
-#if defined (PWR_CSR_EWUP5)
+#if defined(PWR_CSR_EWUP5)
 #define LL_PWR_WAKEUP_PIN5                 (PWR_CSR_EWUP5)        /*!< WKUP pin 5 : LLG TBD */
 #endif /* PWR_CSR_EWUP5 */
-#if defined (PWR_CSR_EWUP6)
+#if defined(PWR_CSR_EWUP6)
 #define LL_PWR_WAKEUP_PIN6                 (PWR_CSR_EWUP6)        /*!< WKUP pin 6 : LLG TBD */
 #endif /* PWR_CSR_EWUP6 */
-#if defined (PWR_CSR_EWUP7)
+#if defined(PWR_CSR_EWUP7)
 #define LL_PWR_WAKEUP_PIN7                 (PWR_CSR_EWUP7)        /*!< WKUP pin 7 : LLG TBD */
 #endif /* PWR_CSR_EWUP7 */
-#if defined (PWR_CSR_EWUP8)
+#if defined(PWR_CSR_EWUP8)
 #define LL_PWR_WAKEUP_PIN8                 (PWR_CSR_EWUP8)        /*!< WKUP pin 8 : LLG TBD */
 #endif /* PWR_CSR_EWUP8 */
 /**
@@ -217,7 +211,6 @@
   * @}
   */
 
-
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
   * @{
@@ -227,7 +220,6 @@
   * @{
   */
 
-
 /**
   * @brief  Enable access to the backup domain
   * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
@@ -260,7 +252,7 @@
 
 #if defined(PWR_CR_LPDS)
 /**
-  * @brief  Set voltage regulator mode during deep sleep mode
+  * @brief  Set voltage Regulator mode during deep sleep mode
   * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
   * @param  RegulMode This parameter can be one of the following values:
   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
@@ -273,7 +265,7 @@
 }
 
 /**
-  * @brief  Get voltage regulator mode during deep sleep mode
+  * @brief  Get voltage Regulator mode during deep sleep mode
   * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
@@ -286,9 +278,9 @@
 #endif /* PWR_CR_LPDS */
 
 /**
-  * @brief  Set power down mode when CPU enters deepsleep
+  * @brief  Set Power Down mode when CPU enters deepsleep
   * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\n
-  *         CR    LPDS         LL_PWR_SetPowerMode
+  * @rmtoll CR    LPDS         LL_PWR_SetPowerMode
   * @param  PDMode This parameter can be one of the following values:
   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
@@ -301,9 +293,9 @@
 }
 
 /**
-  * @brief  Get power down mode when CPU enters deepsleep
-  * @rmtoll CR    PDDS         LL_PWR_GetPowerMode
-  *         CR    LPDS         LL_PWR_SetPowerMode
+  * @brief  Get Power Down mode when CPU enters deepsleep
+  * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\n
+  * @rmtoll CR    LPDS         LL_PWR_GetPowerMode
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
@@ -314,7 +306,7 @@
   return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
 }
 
-#if defined (PWR_PVD_SUPPORT)
+#if defined(PWR_PVD_SUPPORT)
 /**
   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
   * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
@@ -381,13 +373,18 @@
 {
   return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
 }
-#endif
+#endif /* PWR_PVD_SUPPORT */
 
 /**
   * @brief  Enable the WakeUp PINx functionality
   * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
-  *         CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
-  *         CSR   EWUP3       LL_PWR_EnableWakeUpPin
+  * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP4       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP5       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP6       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP7       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP8       LL_PWR_EnableWakeUpPin
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
@@ -409,8 +406,13 @@
 /**
   * @brief  Disable the WakeUp PINx functionality
   * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
-  *         CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
-  *         CSR   EWUP3       LL_PWR_DisableWakeUpPin
+  * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP4       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP5       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP6       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP7       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP8       LL_PWR_DisableWakeUpPin
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
@@ -432,8 +434,13 @@
 /**
   * @brief  Check if the WakeUp PINx functionality is enabled
   * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
-  *         CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
-  *         CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
+  * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP4       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP5       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP6       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP7       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP8       LL_PWR_IsEnabledWakeUpPin
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
@@ -452,6 +459,7 @@
   return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
 }
 
+
 /**
   * @}
   */
@@ -480,7 +488,7 @@
   return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
 }
 
-#if defined (PWR_PVD_SUPPORT)
+#if defined(PWR_PVD_SUPPORT)
 /**
   * @brief  Indicate whether VDD voltage is below the selected PVD threshold
   * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
@@ -490,9 +498,9 @@
 {
   return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
 }
-#endif
+#endif /* PWR_PVD_SUPPORT */
 
-#if defined (PWR_CSR_VREFINTRDYF)
+#if defined(PWR_CSR_VREFINTRDYF)
 /**
   * @brief  Get Internal Reference VrefInt Flag
   * @rmtoll CSR   VREFINTRDYF       LL_PWR_IsActiveFlag_VREFINTRDY
@@ -502,10 +510,7 @@
 {
   return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
 }
-#endif
-
-
-
+#endif /* PWR_CSR_VREFINTRDYF */
 /**
   * @brief  Clear Standby Flag
   * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
@@ -526,6 +531,9 @@
   SET_BIT(PWR->CR, PWR_CR_CWUF);
 }
 
+/**
+  * @}
+  */
 
 #if defined(USE_FULL_LL_DRIVER)
 /** @defgroup PWR_LL_EF_Init De-initialization function
@@ -545,10 +553,6 @@
   * @}
   */
 
-/**
-  * @}
-  */
-
 #endif /* defined(PWR) */
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_rcc.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   RCC LL module driver.
   ******************************************************************************
   * @attention
@@ -148,7 +146,7 @@
 
   /* Reset HSEBYP bit */
   LL_RCC_HSE_DisableBypass();
- 
+
   /* Reset CFGR register */
   LL_RCC_WriteReg(CFGR, 0x00000000U);
 
@@ -499,6 +497,12 @@
       frequency = RCC_PLL_GetFreqDomain_SYS();
       break;
 
+#if defined(RCC_HSI48_SUPPORT)
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock  source */
+      frequency = HSI48_VALUE;
+      break;
+#endif /* RCC_HSI48_SUPPORT */
+
     default:
       frequency = HSI_VALUE;
       break;
@@ -548,15 +552,15 @@
       pllinputfreq = HSI_VALUE;
 #else
     case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
-      pllinputfreq = HSI_VALUE / 2;
+      pllinputfreq = HSI_VALUE / 2U;
 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
       break;
 
-#if defined(RCC_CFGR_SW_HSI48)
+#if defined(RCC_HSI48_SUPPORT)
     case LL_RCC_PLLSOURCE_HSI48:     /* HSI48 used as PLL clock source */
       pllinputfreq = HSI48_VALUE;
       break;
-#endif /* RCC_CFGR_SW_HSI48 */
+#endif /* RCC_HSI48_SUPPORT */
 
     case LL_RCC_PLLSOURCE_HSE:       /* HSE used as PLL clock source */
       pllinputfreq = HSE_VALUE;
@@ -566,7 +570,7 @@
 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
       pllinputfreq = HSI_VALUE;
 #else
-      pllinputfreq = HSI_VALUE / 2;
+      pllinputfreq = HSI_VALUE / 2U;
 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
       break;
   }

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_rcc.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of RCC LL module.
   ******************************************************************************
   * @attention
@@ -58,14 +56,6 @@
 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Variables RCC Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
   * @{
@@ -139,24 +129,24 @@
   * @{
   */
 #if !defined  (HSE_VALUE)
-#define HSE_VALUE    ((uint32_t)8000000U)  /*!< Value of the HSE oscillator in Hz */
+#define HSE_VALUE    8000000U  /*!< Value of the HSE oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSI_VALUE)
-#define HSI_VALUE    ((uint32_t)8000000U) /*!< Value of the HSI oscillator in Hz */
+#define HSI_VALUE    8000000U  /*!< Value of the HSI oscillator in Hz */
 #endif /* HSI_VALUE */
 
 #if !defined  (LSE_VALUE)
-#define LSE_VALUE    ((uint32_t)32768U)    /*!< Value of the LSE oscillator in Hz */
+#define LSE_VALUE    32768U    /*!< Value of the LSE oscillator in Hz */
 #endif /* LSE_VALUE */
 
 #if !defined  (LSI_VALUE)
-#define LSI_VALUE    ((uint32_t)32000U)    /*!< Value of the LSI oscillator in Hz */
+#define LSI_VALUE    32000U    /*!< Value of the LSI oscillator in Hz */
 #endif /* LSI_VALUE */
 #if defined(RCC_HSI48_SUPPORT)
 
 #if !defined  (HSI48_VALUE)
-#define HSI48_VALUE  ((uint32_t)48000000U) /*!< Value of the HSI48 oscillator in Hz */
+#define HSI48_VALUE  48000000U /*!< Value of the HSI48 oscillator in Hz */
 #endif /* HSI48_VALUE */
 #endif /* RCC_HSI48_SUPPORT */
 /**
@@ -333,8 +323,8 @@
 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
   * @{
   */
-#define LL_RCC_PERIPH_FREQUENCY_NO         (uint32_t)0x00000000U      /*!< No clock enabled for the peripheral            */
-#define LL_RCC_PERIPH_FREQUENCY_NA         (uint32_t)0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U      /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
 /**
   * @}
   */
@@ -445,7 +435,7 @@
 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
   * @{
   */
-#define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)0x00000000U         /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
 #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
 #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
@@ -571,7 +561,7 @@
   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
   *             , @ref LL_RCC_PLL_GetPrediv());
   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48)
-  * @param  __PLLMUL__: This parameter can be one of the following values:
+  * @param  __PLLMUL__ This parameter can be one of the following values:
   *         @arg @ref LL_RCC_PLL_MUL_2
   *         @arg @ref LL_RCC_PLL_MUL_3
   *         @arg @ref LL_RCC_PLL_MUL_4
@@ -587,7 +577,7 @@
   *         @arg @ref LL_RCC_PLL_MUL_14
   *         @arg @ref LL_RCC_PLL_MUL_15
   *         @arg @ref LL_RCC_PLL_MUL_16
-  * @param  __PLLPREDIV__: This parameter can be one of the following values:
+  * @param  __PLLPREDIV__ This parameter can be one of the following values:
   *         @arg @ref LL_RCC_PREDIV_DIV_1
   *         @arg @ref LL_RCC_PREDIV_DIV_2
   *         @arg @ref LL_RCC_PREDIV_DIV_3
@@ -614,7 +604,7 @@
   * @brief  Helper macro to calculate the PLLCLK frequency
   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
-  * @param  __PLLMUL__: This parameter can be one of the following values:
+  * @param  __PLLMUL__ This parameter can be one of the following values:
   *         @arg @ref LL_RCC_PLL_MUL_2
   *         @arg @ref LL_RCC_PLL_MUL_3
   *         @arg @ref LL_RCC_PLL_MUL_4
@@ -640,7 +630,7 @@
   * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
   *        ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
-  * @param  __AHBPRESCALER__: This parameter can be one of the following values:
+  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
   *         @arg @ref LL_RCC_SYSCLK_DIV_1
   *         @arg @ref LL_RCC_SYSCLK_DIV_2
   *         @arg @ref LL_RCC_SYSCLK_DIV_4
@@ -652,14 +642,14 @@
   *         @arg @ref LL_RCC_SYSCLK_DIV_512
   * @retval HCLK clock frequency (in Hz)
   */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_POSITION_HPRE])
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
 
 /**
   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
   * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
   *        ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
   * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB1PRESCALER__: This parameter can be one of the following values:
+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
   *         @arg @ref LL_RCC_APB1_DIV_1
   *         @arg @ref LL_RCC_APB1_DIV_2
   *         @arg @ref LL_RCC_APB1_DIV_4
@@ -667,7 +657,7 @@
   *         @arg @ref LL_RCC_APB1_DIV_16
   * @retval PCLK1 clock frequency (in Hz)
   */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_POSITION_PPRE1])
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE_Pos])
 
 /**
   * @}
@@ -804,7 +794,7 @@
   */
 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
 {
-  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_POSITION_HSICAL);
+  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
 }
 
 /**
@@ -818,7 +808,7 @@
   */
 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
 {
-  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_POSITION_HSITRIM);
+  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
 }
 
 /**
@@ -828,7 +818,7 @@
   */
 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
 {
-  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_POSITION_HSITRIM);
+  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_rtc.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   RTC LL module driver.
   ******************************************************************************
   * @attention
@@ -62,12 +60,12 @@
   * @{
   */
 /* Default values used for prescaler */
-#define RTC_ASYNCH_PRESC_DEFAULT     ((uint32_t) 0x0000007FU)
-#define RTC_SYNCH_PRESC_DEFAULT      ((uint32_t) 0x000000FFU)
+#define RTC_ASYNCH_PRESC_DEFAULT     0x0000007FU
+#define RTC_SYNCH_PRESC_DEFAULT      0x000000FFU
 
 /* Values used for timeout */
-#define RTC_INITMODE_TIMEOUT         ((uint32_t) 1000U) /* 1s when tick set to 1ms */
-#define RTC_SYNCHRO_TIMEOUT          ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+#define RTC_INITMODE_TIMEOUT         1000U /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT          1000U /* 1s when tick set to 1ms */
 /**
   * @}
   */
@@ -80,9 +78,9 @@
 #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
                                       || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
 
-#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= (uint32_t)0x7FU)
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
 
-#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= (uint32_t)0x7FFFU)
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
 
 #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
                                   || ((__VALUE__) == LL_RTC_FORMAT_BCD))
@@ -103,7 +101,7 @@
                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
 
-#define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
+#define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
 
 #define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
                                  || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
@@ -369,7 +367,7 @@
   * @param  RTC_Format This parameter can be one of the following values:
   *         @arg @ref LL_RTC_FORMAT_BIN
   *         @arg @ref LL_RTC_FORMAT_BCD
-  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
+  * @param  RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
   *                         the date configuration information for the RTC.
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: RTC Day register is configured

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_rtc.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of RTC LL module.
   ******************************************************************************
   * @attention
@@ -63,49 +61,20 @@
   * @{
   */
 /* Masks Definition */
-#define RTC_INIT_MASK                 ((uint32_t)0xFFFFFFFFU)
-#define RTC_RSF_MASK                  ((uint32_t)0xFFFFFF5FU)
+#define RTC_INIT_MASK                 0xFFFFFFFFU
+#define RTC_RSF_MASK                  0xFFFFFF5FU
 
 /* Write protection defines */
 #define RTC_WRITE_PROTECTION_DISABLE  ((uint8_t)0xFFU)
 #define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
 #define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
 
-/* Defines used for the bit position in the register and perform offsets */
-#define RTC_POSITION_TR_HT            (uint32_t)20U
-#define RTC_POSITION_TR_HU            (uint32_t)16U
-#define RTC_POSITION_TR_MT            (uint32_t)12U
-#define RTC_POSITION_TR_MU            (uint32_t)8U
-#define RTC_POSITION_TR_ST            (uint32_t)4U
-#define RTC_POSITION_TR_SU            (uint32_t)0U
-#define RTC_POSITION_DR_YT            (uint32_t)20U
-#define RTC_POSITION_DR_YU            (uint32_t)16U
-#define RTC_POSITION_DR_MT            (uint32_t)12U
-#define RTC_POSITION_DR_MU            (uint32_t)8U
-#define RTC_POSITION_DR_DT            (uint32_t)4U
-#define RTC_POSITION_DR_DU            (uint32_t)0U
-#define RTC_POSITION_DR_WDU           (uint32_t)13U
-#define RTC_POSITION_ALMA_DT          (uint32_t)28U
-#define RTC_POSITION_ALMA_DU          (uint32_t)24U
-#define RTC_POSITION_ALMA_HT          (uint32_t)20U
-#define RTC_POSITION_ALMA_HU          (uint32_t)16U
-#define RTC_POSITION_ALMA_MT          (uint32_t)12U
-#define RTC_POSITION_ALMA_MU          (uint32_t)8U
-#define RTC_POSITION_ALMA_SU          (uint32_t)0U
-#define RTC_POSITION_ALMA_ST          (uint32_t)4U
-#define RTC_POSITION_PRER_PREDIV_A    (uint32_t)16U
-#define RTC_POSITION_ALMA_MASKSS      (uint32_t)24U
-#define RTC_POSITION_TS_HU            (uint32_t)16U
-#define RTC_POSITION_TS_MNU           (uint32_t)8U
-#define RTC_POSITION_TS_WDU           (uint32_t)13U
-#define RTC_POSITION_TS_MU            (uint32_t)8U
-
 /* Defines used to combine date & time */
-#define RTC_OFFSET_WEEKDAY            (uint32_t)24U
-#define RTC_OFFSET_DAY                (uint32_t)16U
-#define RTC_OFFSET_MONTH              (uint32_t)8U
-#define RTC_OFFSET_HOUR               (uint32_t)16U
-#define RTC_OFFSET_MINUTE             (uint32_t)8U
+#define RTC_OFFSET_WEEKDAY            24U
+#define RTC_OFFSET_DAY                16U
+#define RTC_OFFSET_MONTH              8U
+#define RTC_OFFSET_HOUR               16U
+#define RTC_OFFSET_MINUTE             8U
 
 /**
   * @}
@@ -248,8 +217,8 @@
 /** @defgroup RTC_LL_EC_FORMAT FORMAT
   * @{
   */
-#define LL_RTC_FORMAT_BIN                  ((uint32_t)0x000000000U) /*!< Binary data format */
-#define LL_RTC_FORMAT_BCD                  ((uint32_t)0x000000001U) /*!< BCD data format */
+#define LL_RTC_FORMAT_BIN                  0x000000000U /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD                  0x000000001U /*!< BCD data format */
 /**
   * @}
   */
@@ -257,7 +226,7 @@
 /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
   * @{
   */
-#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    ((uint32_t)0x00000000U) /*!< Alarm A Date is selected */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */
 #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
 /**
   * @}
@@ -335,7 +304,7 @@
 /** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
   * @{
   */
-#define LL_RTC_HOURFORMAT_24HOUR           (uint32_t)0x00000000U /*!< 24 hour/day format */
+#define LL_RTC_HOURFORMAT_24HOUR           0x00000000U           /*!< 24 hour/day format */
 #define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
 /**
   * @}
@@ -344,7 +313,7 @@
 /** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
   * @{
   */
-#define LL_RTC_ALARMOUT_DISABLE            ((uint32_t)0x00000000U) /*!< Output disabled */
+#define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */
 #define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
 #define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
 #define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
@@ -355,7 +324,7 @@
 /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
   * @{
   */
-#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  (uint32_t)0x00000000U  /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  0x00000000U                          /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
 /**
   * @}
@@ -374,7 +343,7 @@
 /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
   * @{
   */
-#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     (uint32_t)0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
+#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
 #define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
 /**
   * @}
@@ -383,7 +352,7 @@
 /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
   * @{
   */
-#define LL_RTC_TIME_FORMAT_AM_OR_24        (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */
 #define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
 /**
   * @}
@@ -392,7 +361,7 @@
 /** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
   * @{
   */
-#define LL_RTC_SHIFT_SECOND_DELAY          (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
+#define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
 #define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
 /**
   * @}
@@ -401,7 +370,7 @@
 /** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
   * @{
   */
-#define LL_RTC_ALMA_MASK_NONE              ((uint32_t)0x00000000U) /*!< No masks applied on Alarm A*/
+#define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/
 #define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
 #define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
 #define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
@@ -414,7 +383,7 @@
 /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
   * @{
   */
-#define LL_RTC_ALMA_TIME_FORMAT_AM         (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
 #define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
 /**
   * @}
@@ -423,7 +392,7 @@
 /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
   * @{
   */
-#define LL_RTC_TIMESTAMP_EDGE_RISING       (uint32_t)0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */
 #define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
 /**
   * @}
@@ -432,7 +401,7 @@
 /** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
   * @{
   */
-#define LL_RTC_TS_TIME_FORMAT_AM           (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */
 #define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
 /**
   * @}
@@ -490,7 +459,7 @@
 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
   * @{
   */
-#define LL_RTC_TAMPER_DURATION_1RTCCLK     ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
+#define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U                             /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
 #define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAFCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
 #define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAFCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
 #define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAFCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
@@ -503,7 +472,7 @@
 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
   * @{
   */
-#define LL_RTC_TAMPER_FILTER_DISABLE       ((uint32_t)0x00000000U)  /*!< Tamper filter is disabled */
+#define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U                              /*!< Tamper filter is disabled */
 #define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAFCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
 #define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAFCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
 #define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAFCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
@@ -516,7 +485,7 @@
 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
   * @{
   */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   ((uint32_t)0x00000000U)                          /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                                      /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
 #define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAFCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
 #define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAFCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
 #define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
@@ -548,7 +517,7 @@
 /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
   * @{
   */
-#define LL_RTC_WAKEUPCLOCK_DIV_16          ((uint32_t)0x00000000U)               /*!< RTC/16 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */
 #define LL_RTC_WAKEUPCLOCK_DIV_8           (RTC_CR_WUCKSEL_0)                    /*!< RTC/8 clock is selected */
 #define LL_RTC_WAKEUPCLOCK_DIV_4           (RTC_CR_WUCKSEL_1)                    /*!< RTC/4 clock is selected */
 #define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
@@ -562,11 +531,11 @@
 /** @defgroup RTC_LL_EC_BKP  BACKUP
   * @{
   */
-#define LL_RTC_BKP_DR0                     ((uint32_t)0x00000000U)
-#define LL_RTC_BKP_DR1                     ((uint32_t)0x00000001U)
-#define LL_RTC_BKP_DR2                     ((uint32_t)0x00000002U)
-#define LL_RTC_BKP_DR3                     ((uint32_t)0x00000003U)
-#define LL_RTC_BKP_DR4                     ((uint32_t)0x00000004U)
+#define LL_RTC_BKP_DR0                     0x00000000U
+#define LL_RTC_BKP_DR1                     0x00000001U
+#define LL_RTC_BKP_DR2                     0x00000002U
+#define LL_RTC_BKP_DR3                     0x00000003U
+#define LL_RTC_BKP_DR4                     0x00000004U
 /**
   * @}
   */
@@ -575,9 +544,9 @@
 /** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
   * @{
   */
-#define LL_RTC_CALIB_OUTPUT_NONE           (uint32_t)0x00000000U       /*!< Calibration output disabled */
-#define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */
-#define LL_RTC_CALIB_OUTPUT_512HZ          (RTC_CR_COE)                /*!< Calibration output is 1 Hz */
+#define LL_RTC_CALIB_OUTPUT_NONE           0x00000000U                 /*!< Calibration output disabled */
+#define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
+#define LL_RTC_CALIB_OUTPUT_512HZ          (RTC_CR_COE)                /*!< Calibration output is 512 Hz */
 /**
   * @}
   */
@@ -585,7 +554,7 @@
 /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion 
   * @{
   */
-#define LL_RTC_CALIB_INSERTPULSE_NONE      (uint32_t)0x00000000U /*!< No RTCCLK pulses are added */
+#define LL_RTC_CALIB_INSERTPULSE_NONE      0x00000000U           /*!< No RTCCLK pulses are added */
 #define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
 /**
   * @}
@@ -594,7 +563,7 @@
 /** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
   * @{
   */
-#define LL_RTC_CALIB_PERIOD_32SEC          (uint32_t)0x00000000U /*!< Use a 32-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_32SEC          0x00000000U           /*!< Use a 32-second calibration cycle period */
 #define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
 #define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
 /**
@@ -1041,7 +1010,7 @@
   */
 __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
 {
-  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_POSITION_PRER_PREDIV_A);
+  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
 }
 
 /**
@@ -1064,7 +1033,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_POSITION_PRER_PREDIV_A);
+  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
 }
 
 /**
@@ -1156,7 +1125,7 @@
 __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
 {
   MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
-             (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)));
+             (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
 }
 
 /**
@@ -1177,7 +1146,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
-  return (uint32_t)((((temp & RTC_TR_HT) >> RTC_POSITION_TR_HT) << 4U) | ((temp & RTC_TR_HU) >> RTC_POSITION_TR_HU));
+  return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
 }
 
 /**
@@ -1194,7 +1163,7 @@
 __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
 {
   MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
-             (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)));
+             (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
 }
 
 /**
@@ -1215,7 +1184,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
-  return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_POSITION_TR_MT) << 4U) | ((temp & RTC_TR_MNU) >> RTC_POSITION_TR_MU));
+  return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
 }
 
 /**
@@ -1232,7 +1201,7 @@
 __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
 {
   MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
-             (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU)));
+             (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
 }
 
 /**
@@ -1253,7 +1222,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
-  return (uint32_t)((((temp & RTC_TR_ST) >> RTC_POSITION_TR_ST) << 4U) | ((temp & RTC_TR_SU) >> RTC_POSITION_TR_SU));
+  return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
 }
 
 /**
@@ -1282,9 +1251,9 @@
   register uint32_t temp = 0U;
 
   temp = Format12_24                                                                                    | \
-         (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU))     | \
-         (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)) | \
-         (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU));
+         (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \
+         (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
   MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
 }
 
@@ -1307,42 +1276,47 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx));
+  register uint32_t temp = 0U;
+  
+  temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
+  return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) |  \
+                    (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
+                    ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
 }
 
 /**
   * @brief  Memorize whether the daylight saving time change has been performed
   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           BCK           LL_RTC_TIME_EnableDayLightStore
+  * @rmtoll CR           BKP           LL_RTC_TIME_EnableDayLightStore
   * @param  RTCx RTC Instance
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
 {
-  SET_BIT(RTCx->CR, RTC_CR_BCK);
+  SET_BIT(RTCx->CR, RTC_CR_BKP);
 }
 
 /**
   * @brief  Disable memorization whether the daylight saving time change has been performed.
   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           BCK           LL_RTC_TIME_DisableDayLightStore
+  * @rmtoll CR           BKP           LL_RTC_TIME_DisableDayLightStore
   * @param  RTCx RTC Instance
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
 {
-  CLEAR_BIT(RTCx->CR, RTC_CR_BCK);
+  CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
 }
 
 /**
   * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
-  * @rmtoll CR           BCK           LL_RTC_TIME_IsDayLightStoreEnabled
+  * @rmtoll CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
   * @param  RTCx RTC Instance
   * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
 {
-  return (READ_BIT(RTCx->CR, RTC_CR_BCK) == (RTC_CR_BCK));
+  return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
 }
 
 /**
@@ -1426,7 +1400,7 @@
 __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
 {
   MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
-             (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)));
+             (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
 }
 
 /**
@@ -1444,7 +1418,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
-  return (uint32_t)((((temp & RTC_DR_YT) >> RTC_POSITION_DR_YT) << 4U) | ((temp & RTC_DR_YU) >> RTC_POSITION_DR_YU));
+  return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
 }
 
 /**
@@ -1463,7 +1437,7 @@
   */
 __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
 {
-  MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_POSITION_DR_WDU);
+  MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
 }
 
 /**
@@ -1483,7 +1457,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_POSITION_DR_WDU);
+  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
 }
 
 /**
@@ -1510,7 +1484,7 @@
 __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
 {
   MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
-             (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)));
+             (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
 }
 
 /**
@@ -1540,7 +1514,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
-  return (uint32_t)((((temp & RTC_DR_MT) >> RTC_POSITION_DR_MT) << 4U) | ((temp & RTC_DR_MU) >> RTC_POSITION_DR_MU));
+  return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
 }
 
 /**
@@ -1555,7 +1529,7 @@
 __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
 {
   MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
-             (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)));
+             (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
 }
 
 /**
@@ -1573,7 +1547,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
-  return (uint32_t)((((temp & RTC_DR_DT) >> RTC_POSITION_DR_DT) << 4U) | ((temp & RTC_DR_DU) >> RTC_POSITION_DR_DU));
+  return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
 }
 
 /**
@@ -1615,10 +1589,10 @@
 {
   register uint32_t temp = 0U;
 
-  temp = (WeekDay << RTC_POSITION_DR_WDU)                                                        | \
-         (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU))   | \
-         (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) | \
-         (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU));
+  temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \
+         (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
+         (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
+         (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
 
   MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
 }
@@ -1641,7 +1615,13 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx));
+  register uint32_t temp = 0U;
+  
+  temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
+  return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
+                    (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
+                    (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
+                    ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
 }
 
 /**
@@ -1751,7 +1731,7 @@
 __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
 {
   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
-             (((Day & 0xF0U) << (RTC_POSITION_ALMA_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMA_DU)));
+             (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
 }
 
 /**
@@ -1767,7 +1747,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
-  return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_POSITION_ALMA_DT) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU));
+  return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
 }
 
 /**
@@ -1786,7 +1766,7 @@
   */
 __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
 {
-  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_POSITION_ALMA_DU);
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
 }
 
 /**
@@ -1804,7 +1784,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU);
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
 }
 
 /**
@@ -1846,7 +1826,7 @@
 __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
 {
   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
-             (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU)));
+             (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
 }
 
 /**
@@ -1862,7 +1842,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
-  return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_POSITION_ALMA_HT) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_POSITION_ALMA_HU));
+  return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
 }
 
 /**
@@ -1877,7 +1857,7 @@
 __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
 {
   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
-             (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)));
+             (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
 }
 
 /**
@@ -1893,7 +1873,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
-  return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_POSITION_ALMA_MT) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_POSITION_ALMA_MU));
+  return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
 }
 
 /**
@@ -1908,7 +1888,7 @@
 __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
 {
   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
-             (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU)));
+             (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
 }
 
 /**
@@ -1924,7 +1904,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
-  return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_POSITION_ALMA_ST) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_POSITION_ALMA_SU));
+  return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
 }
 
 /**
@@ -1949,9 +1929,9 @@
 {
   register uint32_t temp = 0U;
 
-  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU))    | \
-         (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)) | \
-         (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU));
+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
+         (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
 
   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
 }
@@ -1985,7 +1965,7 @@
   */
 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
 {
-  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_POSITION_ALMA_MASKSS);
+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
 }
 
 /**
@@ -1996,7 +1976,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_POSITION_ALMA_MASKSS);
+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
 }
 
 /**
@@ -2107,7 +2087,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_POSITION_TS_HU);
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
 }
 
 /**
@@ -2120,7 +2100,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_POSITION_TS_MNU);
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
 }
 
 /**
@@ -2170,7 +2150,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_POSITION_TS_WDU);
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
 }
 
 /**
@@ -2195,7 +2175,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_POSITION_TS_MU);
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_spi.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   SPI LL module driver.
   ******************************************************************************
   * @attention

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_spi.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of SPI LL module.
   ******************************************************************************
   * @attention
@@ -141,7 +139,6 @@
 #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
 #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
 #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
-#define LL_SPI_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
 #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
 #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
 #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
@@ -165,7 +162,7 @@
   * @{
   */
 #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
-#define LL_SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)         /*!< Slave configuration   */
+#define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
 /**
   * @}
   */
@@ -173,7 +170,7 @@
 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
   * @{
   */
-#define LL_SPI_PROTOCOL_MOTOROLA           ((uint32_t)0x00000000U)   /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
 #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
 /**
   * @}
@@ -182,7 +179,7 @@
 /** @defgroup SPI_LL_EC_PHASE Clock Phase
   * @{
   */
-#define LL_SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)   /*!< First clock transition is the first data capture edge  */
+#define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
 #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
 /**
   * @}
@@ -191,7 +188,7 @@
 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
   * @{
   */
-#define LL_SPI_POLARITY_LOW                ((uint32_t)0x00000000U)   /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
 #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
 /**
   * @}
@@ -200,7 +197,7 @@
 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
   * @{
   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV2      ((uint32_t)0x00000000U)                        /*!< BaudRate control equal to fPCLK/2   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
 #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
 #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
 #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
@@ -216,7 +213,7 @@
   * @{
   */
 #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST                   ((uint32_t)0x00000000U)   /*!< Data is transmitted/received with the MSB first */
+#define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
 /**
   * @}
   */
@@ -224,7 +221,7 @@
 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
   * @{
   */
-#define LL_SPI_FULL_DUPLEX                 ((uint32_t)0x00000000U)              /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
 #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
 #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
 #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
@@ -236,7 +233,7 @@
   * @{
   */
 #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
-#define LL_SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)           /*!< NSS pin used in Input. Only used in Master mode                */
+#define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
 #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
 /**
   * @}
@@ -266,7 +263,7 @@
 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
   * @{
   */
-#define LL_SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000U)   /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
 #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
 /**
   * @}
@@ -276,7 +273,7 @@
 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
   * @{
   */
-#define LL_SPI_CRC_8BIT                    ((uint32_t)0x00000000U)   /*!<  8-bit CRC length */
+#define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
 #define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
 /**
   * @}
@@ -285,7 +282,7 @@
 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
   * @{
   */
-#define LL_SPI_RX_FIFO_TH_HALF             ((uint32_t)0x00000000U)   /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
+#define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
 #define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit)  */
 /**
   * @}
@@ -294,7 +291,7 @@
 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
   * @{
   */
-#define LL_SPI_RX_FIFO_EMPTY               ((uint32_t)0x00000000U)           /*!< FIFO reception empty */
+#define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception empty */
 #define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
 #define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
 #define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
@@ -305,7 +302,7 @@
 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
   * @{
   */
-#define LL_SPI_TX_FIFO_EMPTY               ((uint32_t)0x00000000U)           /*!< FIFO transmission empty */
+#define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission empty */
 #define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
 #define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
 #define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
@@ -316,8 +313,8 @@
 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
   * @{
   */
-#define LL_SPI_DMA_PARITY_EVEN             ((uint32_t)0x00000000U)   /*!< Select DMA parity Even */
-#define LL_SPI_DMA_PARITY_ODD              ((uint32_t)0x00000001U)   /*!< Select DMA parity Odd  */
+#define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
+#define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
 
 /**
   * @}
@@ -1283,7 +1280,7 @@
   */
 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
 {
-  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << 13U));
+  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
 }
 
 /**
@@ -1296,7 +1293,7 @@
   */
 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
 {
-  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> 13U);
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
 }
 
 /**
@@ -1310,7 +1307,7 @@
   */
 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
 {
-  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << 14U));
+  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
 }
 
 /**
@@ -1323,7 +1320,7 @@
   */
 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
 {
-  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> 14U);
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
 }
 
 /**
@@ -1490,7 +1487,7 @@
 #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
 #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
 #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
-#define LL_I2S_SR_UDR                      LL_SPI_SR_UDR             /*!< Underrun flag                    */
+#define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
 #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
 #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
 /**
@@ -1511,7 +1508,7 @@
 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
   * @{
   */
-#define LL_I2S_DATAFORMAT_16B              ((uint32_t)0x00000000U)                       /*!< Data length 16 bits, Channel lenght 16bit */
+#define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel lenght 16bit */
 #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel lenght 32bit */
 #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel lenght 32bit */
 #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel lenght 32bit */
@@ -1522,7 +1519,7 @@
 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
   * @{
   */
-#define LL_I2S_POLARITY_LOW                ((uint32_t)0x00000000U)   /*!< Clock steady state is low level  */
+#define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
 #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
 /**
   * @}
@@ -1531,7 +1528,7 @@
 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
   * @{
   */
-#define LL_I2S_STANDARD_PHILIPS            ((uint32_t)0x00000000U)                                             /*!< I2S standard philips                      */
+#define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
 #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
 #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
 #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
@@ -1543,7 +1540,7 @@
 /** @defgroup I2S_LL_EC_MODE Operation Mode
   * @{
   */
-#define LL_I2S_MODE_SLAVE_TX               ((uint32_t)0x00000000U)                       /*!< Slave Tx configuration  */
+#define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
 #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
 #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
 #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
@@ -1554,7 +1551,7 @@
 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
   * @{
   */
-#define LL_I2S_PRESCALER_PARITY_EVEN       ((uint32_t)0x00000000U)   /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
+#define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
 #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
 /**
   * @}
@@ -1565,7 +1562,7 @@
 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
   * @{
   */
-#define LL_I2S_MCLK_OUTPUT_DISABLE         ((uint32_t)0x00000000U)   /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
 #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
 /**
   * @}
@@ -1575,16 +1572,16 @@
   * @{
   */
 
-#define LL_I2S_AUDIOFREQ_192K              ((uint32_t)192000)        /*!< Audio Frequency configuration 192000 Hz       */
-#define LL_I2S_AUDIOFREQ_96K               ((uint32_t) 96000)        /*!< Audio Frequency configuration  96000 Hz       */
-#define LL_I2S_AUDIOFREQ_48K               ((uint32_t) 48000)        /*!< Audio Frequency configuration  48000 Hz       */
-#define LL_I2S_AUDIOFREQ_44K               ((uint32_t) 44100)        /*!< Audio Frequency configuration  44100 Hz       */
-#define LL_I2S_AUDIOFREQ_32K               ((uint32_t) 32000)        /*!< Audio Frequency configuration  32000 Hz       */
-#define LL_I2S_AUDIOFREQ_22K               ((uint32_t) 22050)        /*!< Audio Frequency configuration  22050 Hz       */
-#define LL_I2S_AUDIOFREQ_16K               ((uint32_t) 16000)        /*!< Audio Frequency configuration  16000 Hz       */
-#define LL_I2S_AUDIOFREQ_11K               ((uint32_t) 11025)        /*!< Audio Frequency configuration  11025 Hz       */
-#define LL_I2S_AUDIOFREQ_8K                ((uint32_t)  8000)        /*!< Audio Frequency configuration   8000 Hz       */
-#define LL_I2S_AUDIOFREQ_DEFAULT           ((uint32_t)     2)        /*!< Audio Freq not specified. Register I2SDIV = 2 */
+#define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 Hz       */
+#define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 Hz       */
+#define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 Hz       */
+#define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 Hz       */
+#define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 Hz       */
+#define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 Hz       */
+#define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 Hz       */
+#define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 Hz       */
+#define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 Hz       */
+#define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2SDIV = 2 */
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_system.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of SYSTEM LL module.
   @verbatim
   ==============================================================================
@@ -76,9 +74,6 @@
   * @{
   */
 
-/* Defines used for position in the register */
-#define DBGMCU_REVID_POSITION         (uint32_t)16U
-
 /**
   * @}
   */
@@ -337,7 +332,7 @@
 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
   * @{
   */
-#define LL_FLASH_LATENCY_0                 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */
+#define LL_FLASH_LATENCY_0                 0x00000000U             /*!< FLASH Zero Latency cycle */
 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY       /*!< FLASH One Latency cycle */
 /**
   * @}
@@ -1635,7 +1630,7 @@
   */
 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
 {
-  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_tim.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   TIM LL module driver.
   ******************************************************************************
   * @attention
@@ -127,6 +125,26 @@
 
 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                                || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+                                     || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+                                      || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
+                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
+                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+                                       || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+                                          || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+                                                  || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
 /**
   * @}
   */
@@ -265,7 +283,7 @@
   /* Set the default configuration */
   TIM_InitStruct->Prescaler         = (uint16_t)0x0000U;
   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
-  TIM_InitStruct->Autoreload        = (uint32_t)0xFFFFFFFFU;
+  TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
 }
@@ -335,7 +353,7 @@
   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
-  TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U;
+  TIM_OC_InitStruct->CompareValue = 0x00000000U;
   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
@@ -528,7 +546,7 @@
   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
-  TIM_HallSensorInitStruct->CommutationDelay  = (uint32_t)0U;
+  TIM_HallSensorInitStruct->CommutationDelay  = 0U;
 }
 
 /**
@@ -624,6 +642,68 @@
 }
 
 /**
+  * @brief  Set the fields of the Break and Dead Time configuration data structure
+  *         to their default values.
+  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+  * @retval None
+  */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
+  TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
+  TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
+  TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00U;
+  TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
+  TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
+  TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+}
+
+/**
+  * @brief  Configure the Break and Dead Time feature of the timer instance.
+  * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
+  *  depending on the LOCK configuration, it can be necessary to configure all of
+  *  them during the first write access to the TIMx_BDTR register.
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @param  TIMx Timer Instance
+  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Break and Dead Time is initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+  uint32_t tmpbdtr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+  assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+  assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+  assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+  assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+  assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+  the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
+
+  /* Set TIMx_BDTR */
+  LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+
+  return SUCCESS;
+}
+/**
   * @}
   */
 

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_tim.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of TIM LL module.
   ******************************************************************************
   * @attention
@@ -126,9 +124,9 @@
   */
 
 
-#define TIMx_OR_RMP_SHIFT  ((uint32_t)16U)
-#define TIMx_OR_RMP_MASK   ((uint32_t)0x0000FFFFU)
-#define TIM14_OR_RMP_MASK  ((uint32_t)(TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT))
+#define TIMx_OR_RMP_SHIFT  16U
+#define TIMx_OR_RMP_MASK   0x0000FFFFU
+#define TIM14_OR_RMP_MASK  (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
 
 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
 #define DT_DELAY_1 ((uint8_t)0x7FU)
@@ -147,7 +145,6 @@
   * @}
   */
 
-
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
   * @{
@@ -209,7 +206,7 @@
 
                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
 
-  uint32_t Autoreload;       /*!< Specifies the auto reload value to be loaded into the active
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
                                    Auto-Reload Register at the next update event.
                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
                                    Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
@@ -267,6 +264,7 @@
 
                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
 
+
   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
 
@@ -391,6 +389,61 @@
 } LL_TIM_HALLSENSOR_InitTypeDef;
 
 /**
+  * @brief  BDTR (Break and Dead Time) structure definition
+  */
+typedef struct
+{
+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
+                                            has been written, their content is frozen until the next reset.*/
+
+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
+
+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
   * @}
   */
 #endif /* USE_FULL_LL_DRIVER */
@@ -420,6 +473,26 @@
   * @}
   */
 
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+  * @{
+  */
+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+  * @{
+  */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
 /** @defgroup TIM_LL_EC_IT IT Defines
   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
   * @{
@@ -439,8 +512,8 @@
 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
   * @{
   */
-#define LL_TIM_UPDATESOURCE_REGULAR            ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS            /*!< Only counter overflow/underflow generates an update request */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
 /**
   * @}
   */
@@ -448,8 +521,8 @@
 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
   * @{
   */
-#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM            /*!< Counter is not stopped at update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE         ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter is not stopped at update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter stops counting at the next update event */
 /**
   * @}
   */
@@ -457,11 +530,11 @@
 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
   * @{
   */
-#define LL_TIM_COUNTERMODE_UP                  ((uint32_t)0x00000000U) /*!<Counter used as upcounter */
-#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR             /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0           /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1           /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
-#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS             /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
 /**
   * @}
   */
@@ -469,9 +542,9 @@
 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
   * @{
   */
-#define LL_TIM_CLOCKDIVISION_DIV1              ((uint32_t)0x00000000U) /*!< tDTS=tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0           /*!< tDTS=2*tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1           /*!< tDTS=4*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
 /**
   * @}
   */
@@ -479,8 +552,8 @@
 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
   * @{
   */
-#define LL_TIM_COUNTERDIRECTION_UP             ((uint32_t)0x00000000U) /*!< Timer counter counts up */
-#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR             /*!< Timer counter counts down */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
 /**
   * @}
   */
@@ -488,8 +561,8 @@
 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
   * @{
   */
-#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        ((uint32_t)0x00000000U) /*!< Capture/compare control bits are updated by setting the COMG bit only */
-#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS            /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
 /**
   * @}
   */
@@ -497,8 +570,8 @@
 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
   * @{
   */
-#define LL_TIM_CCDMAREQUEST_CC                 ((uint32_t)0x00000000U) /*!< CCx DMA request sent when CCx event occurs */
-#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS            /*!< CCx DMA requests sent when update event occurs */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
 /**
   * @}
   */
@@ -506,10 +579,10 @@
 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
   * @{
   */
-#define LL_TIM_LOCKLEVEL_OFF                   ((uint32_t)0x00000000U) /*!< LOCK OFF - No bit is write protected */
-#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0         /*!< LOCK Level 1 */
-#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1         /*!< LOCK Level 2 */
-#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK           /*!< LOCK Level 3 */
+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
 /**
   * @}
   */
@@ -532,7 +605,7 @@
 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
   * @{
   */
-#define LL_TIM_OCSTATE_DISABLE                 ((uint32_t)0x00000000U) /*!< OCx is not active */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
 #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
 /**
   * @}
@@ -542,11 +615,11 @@
 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
   * @{
   */
-#define LL_TIM_OCMODE_FROZEN                   ((uint32_t)0x00000000U)                                  /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)                                       /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                       /*!<OCyREF is forced low*/
 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
@@ -557,7 +630,7 @@
 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
   * @{
   */
-#define LL_TIM_OCPOLARITY_HIGH                 ((uint32_t)0x00000000U)     /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
 /**
   * @}
@@ -566,7 +639,7 @@
 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
   * @{
   */
-#define LL_TIM_OCIDLESTATE_LOW                 ((uint32_t)0x00000000U) /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
 #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
 /**
   * @}
@@ -576,9 +649,9 @@
 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
   * @{
   */
-#define LL_TIM_ACTIVEINPUT_DIRECTTI            (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
-#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
-#define LL_TIM_ACTIVEINPUT_TRC                 (uint32_t)(TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
 /**
   * @}
   */
@@ -586,10 +659,10 @@
 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
   * @{
   */
-#define LL_TIM_ICPSC_DIV1                      ((uint32_t)0x00000000U) /*!< No prescaler, capture is done each time an edge is detected on the capture input */
-#define LL_TIM_ICPSC_DIV2                      (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
-#define LL_TIM_ICPSC_DIV4                      (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
-#define LL_TIM_ICPSC_DIV8                      (uint32_t)(TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                              /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
 /**
   * @}
   */
@@ -597,22 +670,22 @@
 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
   * @{
   */
-#define LL_TIM_IC_FILTER_FDIV1                 ((uint32_t)0x00000000U)                                         /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_IC_FILTER_FDIV1_N2              (uint32_t)(TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_IC_FILTER_FDIV1_N4              (uint32_t)(TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_IC_FILTER_FDIV1_N8              (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_IC_FILTER_FDIV2_N6              (uint32_t)(TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_IC_FILTER_FDIV2_N8              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_IC_FILTER_FDIV4_N6              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_IC_FILTER_FDIV4_N8              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_IC_FILTER_FDIV8_N6              (uint32_t)(TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_IC_FILTER_FDIV8_N8              (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_IC_FILTER_FDIV16_N5             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_IC_FILTER_FDIV16_N6             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_IC_FILTER_FDIV16_N8             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_IC_FILTER_FDIV32_N5             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_IC_FILTER_FDIV32_N6             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_IC_FILTER_FDIV32_N8             (uint32_t)(TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
 /**
   * @}
   */
@@ -620,7 +693,7 @@
 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
   * @{
   */
-#define LL_TIM_IC_POLARITY_RISING              ((uint32_t)0x00000000U)          /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
 #define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
 /**
@@ -630,9 +703,9 @@
 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
   * @{
   */
-#define LL_TIM_CLOCKSOURCE_INTERNAL            ((uint32_t)0x00000000U)                              /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
-#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                        /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
 /**
   * @}
   */
@@ -650,7 +723,7 @@
 /** @defgroup TIM_LL_EC_TRGO Trigger Output
   * @{
   */
-#define LL_TIM_TRGO_RESET                      ((uint32_t)0x00000000U)                         /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
@@ -666,7 +739,7 @@
 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
   * @{
   */
-#define LL_TIM_SLAVEMODE_DISABLED              ((uint32_t)0x00000000U)             /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
@@ -677,14 +750,14 @@
 /** @defgroup TIM_LL_EC_TS Trigger Selection
   * @{
   */
-#define LL_TIM_TS_ITR0                         ((uint32_t)0x00000000U)         /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF                         TIM_SMCR_TS                     /*!< Filtered external Trigger (ETRF) is used as trigger input */
+#define LL_TIM_TS_ITR0                         0x00000000U                                      /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                    /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                    /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                  /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                    /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                  /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                  /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)  /*!< Filtered external Trigger (ETRF) is used as trigger input */
 /**
   * @}
   */
@@ -692,7 +765,7 @@
 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
   * @{
   */
-#define LL_TIM_ETR_POLARITY_NONINVERTED        ((uint32_t)0x00000000U) /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
 /**
   * @}
@@ -701,7 +774,7 @@
 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
   * @{
   */
-#define LL_TIM_ETR_PRESCALER_DIV1              ((uint32_t)0x00000000U) /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
@@ -712,21 +785,21 @@
 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
   * @{
   */
-#define LL_TIM_ETR_FILTER_FDIV1                ((uint32_t)0x00000000U)                              /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 )                   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 )                   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 )                   /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2  | TIM_SMCR_ETF_0)  /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2  | TIM_SMCR_ETF_1)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
 /**
   * @}
@@ -736,7 +809,7 @@
 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
   * @{
   */
-#define LL_TIM_BREAK_POLARITY_LOW              ((uint32_t)0x00000000U)   /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
 #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
 /**
   * @}
@@ -748,7 +821,7 @@
 /** @defgroup TIM_LL_EC_OSSI OSSI
   * @{
   */
-#define LL_TIM_OSSI_DISABLE                    ((uint32_t)0x00000000U) /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
 #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
 /**
   * @}
@@ -757,7 +830,7 @@
 /** @defgroup TIM_LL_EC_OSSR OSSR
   * @{
   */
-#define LL_TIM_OSSR_DISABLE                    ((uint32_t)0x00000000U) /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
 #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
 /**
   * @}
@@ -767,7 +840,7 @@
 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
   * @{
   */
-#define LL_TIM_DMABURST_BASEADDR_CR1           ((uint32_t)0x00000000U)                                          /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
@@ -794,7 +867,7 @@
 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
   * @{
   */
-#define LL_TIM_DMABURST_LENGTH_1TRANSFER       ((uint32_t)0x00000000U)                                         /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
@@ -817,7 +890,7 @@
   */
 
 
-#define LL_TIM_TIM14_TI1_RMP_GPIO     ((uint32_t)0x00000000U | TIM14_OR_RMP_MASK)                              /*!< TIM14_TI1 is connected to Ored GPIO */
+#define LL_TIM_TIM14_TI1_RMP_GPIO     TIM14_OR_RMP_MASK                                                        /*!< TIM14_TI1 is connected to Ored GPIO */
 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK  (TIM14_OR_TI1_RMP_0  | TIM14_OR_RMP_MASK)                                /*!< TIM14_TI1 is connected to RTC clock */
 #define LL_TIM_TIM14_TI1_RMP_HSE      (TIM14_OR_TI1_RMP_1  | TIM14_OR_RMP_MASK)                                /*!< TIM14_TI1 is connected to HSE/32 clock */
 #define LL_TIM_TIM14_TI1_RMP_MCO      (TIM14_OR_TI1_RMP_0  | TIM14_OR_TI1_RMP_1  | TIM14_OR_RMP_MASK)          /*!< TIM14_TI1 is connected to MCO */
@@ -826,13 +899,12 @@
 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
   * @{
   */
-#define LL_TIM_OCREF_CLR_INT_OCREF_CLR     ((uint32_t)0x00000000U ) /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
-#define LL_TIM_OCREF_CLR_INT_ETR           TIM_SMCR_OCCS            /*!< OCREF_CLR_INT is connected to ETRF */
+#define LL_TIM_OCREF_CLR_INT_OCREF_CLR     0x00000000U         /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
+#define LL_TIM_OCREF_CLR_INT_ETR           TIM_SMCR_OCCS       /*!< OCREF_CLR_INT is connected to ETRF */
 /**
   * @}
   */
 
-
 /**
   * @}
   */
@@ -944,7 +1016,7 @@
   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
   */
 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
-   ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
 
 
 /**
@@ -1005,7 +1077,7 @@
   */
 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
 {
-  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
 }
 
 /**
@@ -1016,18 +1088,18 @@
   */
 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
 {
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
 }
 
 /**
   * @brief  Indicates whether update event generation is enabled.
   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
   * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
+  * @retval Inverted state of bit (0 or 1).
   */
 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
 {
-  return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
+  return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
 }
 
 /**
@@ -2709,7 +2781,13 @@
   */
 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
 {
+  __IO uint32_t tmpreg; 
+
   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
 }
 
 /**
@@ -2722,7 +2800,13 @@
   */
 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
 {
+  __IO uint32_t tmpreg;
+
   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
 }
 
 /**
@@ -2738,7 +2822,13 @@
   */
 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
 {
+  __IO uint32_t tmpreg;
+
   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
+
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
 }
 
 /**
@@ -2932,15 +3022,14 @@
   * @}
   */
 
-#if defined(TIM_SMCR_OCCS)
 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
   * @{
   */
 /**
-  * @brief  Set the OCREF clear source
+  * @brief  Set the OCREF clear input source
   * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
   * @note This function can only be used in Output compare and PWM modes.
-  * @rmtoll SMCR          OCCS           LL_TIM_SetOCRefClearInputSource
+  * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
   * @param  TIMx Timer instance
   * @param  OCRefClearInputSource This parameter can be one of the following values:
   *         @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
@@ -2955,7 +3044,6 @@
   * @}
   */
 
-#endif /* TIM_SMCR_OCCS */
 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
   * @{
   */
@@ -3847,6 +3935,8 @@
 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
 /**
   * @}
   */
@@ -3871,5 +3961,4 @@
 #endif
 
 #endif /* __STM32F0xx_LL_TIM_H */
-
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_usart.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   USART LL module driver.
   ******************************************************************************
   * @attention
@@ -77,6 +75,12 @@
  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U)
 
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
+#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
                                        || ((__VALUE__) == LL_USART_DIRECTION_RX) \
                                        || ((__VALUE__) == LL_USART_DIRECTION_TX) \
@@ -247,7 +251,7 @@
   *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
   * @param  USARTx USART Instance
-  * @param  USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
+  * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
   *         that contains the configuration information for the specified USART peripheral.
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
@@ -275,7 +279,7 @@
      CRx registers */
   if (LL_USART_IsEnabled(USARTx) == 0U)
   {
-    /*---------------------------- USART CR1 Configuration -----------------------
+    /*---------------------------- USART CR1 Configuration ---------------------
      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
@@ -288,20 +292,20 @@
                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
 
-    /*---------------------------- USART CR2 Configuration -----------------------
+    /*---------------------------- USART CR2 Configuration ---------------------
      * Configure USARTx CR2 (Stop bits) with parameters:
      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
      */
     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
 
-    /*---------------------------- USART CR3 Configuration -----------------------
+    /*---------------------------- USART CR3 Configuration ---------------------
      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
      */
     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
 
-    /*---------------------------- USART BRR Configuration -----------------------
+    /*---------------------------- USART BRR Configuration ---------------------
      * Retrieve Clock frequency used for USART Peripheral
      */
     if (USARTx == USART1)
@@ -389,6 +393,12 @@
                            periphclk,
                            USART_InitStruct->OverSampling,
                            USART_InitStruct->BaudRate);
+
+      /* Check BRR is greater than or equal to 16d */
+      assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+
+      /* Check BRR is greater than or equal to 16d */
+      assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
     }
   }
   /* Endif (=> USART not in Disabled state => return ERROR) */
@@ -398,7 +408,7 @@
 
 /**
   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
-  * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
+  * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
   *                          whose fields will be set to default values.
   * @retval None
   */
@@ -421,7 +431,7 @@
   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
   *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
   * @param  USARTx USART Instance
-  * @param  USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+  * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
   *         that contains the Clock configuration information for the specified USART peripheral.
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
@@ -482,7 +492,7 @@
 
 /**
   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
-  * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+  * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
   *                               whose fields will be set to default values.
   * @retval None
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_usart.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of USART LL module.
   ******************************************************************************
   * @attention
@@ -63,16 +61,6 @@
 /** @defgroup USART_LL_Private_Constants USART Private Constants
   * @{
   */
-
-/* Defines used for the bit position in the register and perform offsets*/
-#define USART_POSITION_CR1_DEDT                 (uint32_t)16
-#define USART_POSITION_CR1_DEAT                 (uint32_t)21
-#define USART_POSITION_CR2_ADD                  (uint32_t)24
-#if defined(USART_SMARTCARD_SUPPORT)
-#define USART_POSITION_CR3_SCARCNT              (uint32_t)17
-#define USART_POSITION_RTOR_BLEN                (uint32_t)24
-#define USART_POSITION_GTPR_GT                  (uint32_t)8
-#endif
 /**
   * @}
   */
@@ -268,7 +256,7 @@
 /** @defgroup USART_LL_EC_DIRECTION Communication Direction
   * @{
   */
-#define LL_USART_DIRECTION_NONE                 (uint32_t)0x00000000U              /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
 #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
 #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
 #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
@@ -279,7 +267,7 @@
 /** @defgroup USART_LL_EC_PARITY Parity Control
   * @{
   */
-#define LL_USART_PARITY_NONE                    (uint32_t)0x00000000U                /*!< Parity control disabled */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
 #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
 #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
 /**
@@ -289,7 +277,7 @@
 /** @defgroup USART_LL_EC_WAKEUP Wakeup
   * @{
   */
-#define LL_USART_WAKEUP_IDLELINE                (uint32_t)0x00000000U /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
 #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
 /**
   * @}
@@ -300,10 +288,10 @@
   */
 #if defined(USART_7BITS_SUPPORT)
 #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_8B                   (uint32_t)0x00000000U   /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
 #else
-#define LL_USART_DATAWIDTH_8B                   (uint32_t)0x00000000U   /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M             /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
 #endif
 /**
@@ -313,7 +301,7 @@
 /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
   * @{
   */
-#define LL_USART_OVERSAMPLING_16                (uint32_t)0x00000000U  /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
 #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
 /**
   * @}
@@ -324,7 +312,7 @@
   * @{
   */
 
-#define LL_USART_CLOCK_DISABLE                  (uint32_t)0x00000000U  /*!< Clock signal not provided */
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
 #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
 /**
   * @}
@@ -334,7 +322,7 @@
 /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
   * @{
   */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT         (uint32_t)0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
 #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
 /**
   * @}
@@ -343,7 +331,7 @@
 /** @defgroup USART_LL_EC_PHASE Clock Phase
   * @{
   */
-#define LL_USART_PHASE_1EDGE                    (uint32_t)0x00000000U /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
 #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
 /**
   * @}
@@ -352,7 +340,7 @@
 /** @defgroup USART_LL_EC_POLARITY Clock Polarity
   * @{
   */
-#define LL_USART_POLARITY_LOW                   (uint32_t)0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
 #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
 /**
   * @}
@@ -364,7 +352,7 @@
 #if defined(USART_SMARTCARD_SUPPORT)
 #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
 #endif
-#define LL_USART_STOPBITS_1                     (uint32_t)0x00000000U                      /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
 #if defined(USART_SMARTCARD_SUPPORT)
 #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
 #endif
@@ -376,7 +364,7 @@
 /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
   * @{
   */
-#define LL_USART_TXRX_STANDARD                  (uint32_t)0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
 #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
 /**
   * @}
@@ -385,7 +373,7 @@
 /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
   * @{
   */
-#define LL_USART_RXPIN_LEVEL_STANDARD           (uint32_t)0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
 #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
 /**
   * @}
@@ -394,7 +382,7 @@
 /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
   * @{
   */
-#define LL_USART_TXPIN_LEVEL_STANDARD           (uint32_t)0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
 #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
 /**
   * @}
@@ -403,7 +391,7 @@
 /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
   * @{
   */
-#define LL_USART_BINARY_LOGIC_POSITIVE          (uint32_t)0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
 #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
 /**
   * @}
@@ -412,7 +400,7 @@
 /** @defgroup USART_LL_EC_BITORDER Bit Order
   * @{
   */
-#define LL_USART_BITORDER_LSBFIRST              (uint32_t)0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
 #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
 /**
   * @}
@@ -421,7 +409,7 @@
 /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
   * @{
   */
-#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    (uint32_t)0x00000000U                       /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
 #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
 #if defined(USART_FABR_SUPPORT)
 #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
@@ -434,7 +422,7 @@
 /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
   * @{
   */
-#define LL_USART_ADDRESS_DETECT_4B              (uint32_t)0x00000000U /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
 #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
 /**
   * @}
@@ -443,7 +431,7 @@
 /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
   * @{
   */
-#define LL_USART_HWCONTROL_NONE                 (uint32_t)0x00000000U                /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
 #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
 #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
 #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
@@ -455,7 +443,7 @@
 /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
   * @{
   */
-#define LL_USART_WAKEUP_ON_ADDRESS              (uint32_t)0x00000000U                   /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
 #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
 #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
 /**
@@ -467,7 +455,7 @@
 /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
   * @{
   */
-#define LL_USART_IRDA_POWER_NORMAL              (uint32_t)0x00000000U /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
 #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
 /**
   * @}
@@ -478,7 +466,7 @@
 /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
   * @{
   */
-#define LL_USART_LINBREAK_DETECT_10B            (uint32_t)0x00000000U /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
 #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
 /**
   * @}
@@ -488,7 +476,7 @@
 /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
   * @{
   */
-#define LL_USART_DE_POLARITY_HIGH               (uint32_t)0x00000000U /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
 #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
 /**
   * @}
@@ -497,8 +485,8 @@
 /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
   * @{
   */
-#define LL_USART_DMA_REG_DATA_TRANSMIT          (uint32_t)0U          /*!< Get address of data register used for transmission */
-#define LL_USART_DMA_REG_DATA_RECEIVE           (uint32_t)1U          /*!< Get address of data register used for reception */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
 /**
   * @}
   */
@@ -1400,7 +1388,7 @@
 __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
 {
   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
-             (uint32_t)(AddressLen | (NodeAddress << USART_POSITION_CR2_ADD)));
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
 }
 
 /**
@@ -1415,7 +1403,7 @@
   */
 __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
 {
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_POSITION_CR2_ADD);
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
 }
 
 /**
@@ -1627,6 +1615,7 @@
   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
   *         (Baud rate value != 0)
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
   * @param  USARTx USART Instance
   * @param  PeriphClk Peripheral Clock
@@ -1659,6 +1648,7 @@
   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
   * @param  USARTx USART Instance
   * @param  PeriphClk Peripheral Clock
@@ -1725,7 +1715,7 @@
   */
 __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
 {
-  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_POSITION_RTOR_BLEN);
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
 }
 
 /**
@@ -1736,7 +1726,7 @@
   */
 __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
 {
-  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_POSITION_RTOR_BLEN);
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
 }
 #endif
 
@@ -1952,7 +1942,7 @@
   */
 __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
 {
-  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_POSITION_CR3_SCARCNT);
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
 }
 
 /**
@@ -1965,7 +1955,7 @@
   */
 __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
 {
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_POSITION_CR3_SCARCNT);
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
 }
 
 /**
@@ -2009,7 +1999,7 @@
   */
 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
 {
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);
 }
 
 /**
@@ -2023,7 +2013,7 @@
   */
 __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
 {
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
 }
 
 /**
@@ -2173,7 +2163,7 @@
   */
 __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
 {
-  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_POSITION_CR1_DEDT);
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
 }
 
 /**
@@ -2186,7 +2176,7 @@
   */
 __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
 {
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_POSITION_CR1_DEDT);
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
 }
 
 /**
@@ -2200,7 +2190,7 @@
   */
 __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
 {
-  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_POSITION_CR1_DEAT);
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
 }
 
 /**
@@ -2213,7 +2203,7 @@
   */
 __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
 {
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_POSITION_CR1_DEAT);
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_utils.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   UTILS LL module driver.
   ******************************************************************************
   * @attention
@@ -60,15 +58,15 @@
   */
 
 /* Defines used for PLL range */
-#define UTILS_PLL_OUTPUT_MIN        ((uint32_t)16000000U)        /*!< Frequency min for PLL output, in Hz  */
-#define UTILS_PLL_OUTPUT_MAX        ((uint32_t)48000000U)        /*!< Frequency max for PLL output, in Hz  */
+#define UTILS_PLL_OUTPUT_MIN        16000000U           /*!< Frequency min for PLL output, in Hz  */
+#define UTILS_PLL_OUTPUT_MAX        48000000U    /*!< Frequency max for PLL output, in Hz  */
 
 /* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN     ((uint32_t)4000000U)         /*!< Frequency min for HSE frequency, in Hz   */
-#define UTILS_HSE_FREQUENCY_MAX     ((uint32_t)32000000U)        /*!< Frequency max for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MIN      4000000U       /*!< Frequency min for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MAX     32000000U       /*!< Frequency max for HSE frequency, in Hz   */
 
 /* Defines used for FLASH latency according to SYSCLK Frequency */
-#define UTILS_LATENCY1_FREQ         ((uint32_t)24000000U)        /*!< SYSCLK frequency to set FLASH latency 1 */
+#define UTILS_LATENCY1_FREQ         24000000U        /*!< SYSCLK frequency to set FLASH latency 1 */
 /**
   * @}
   */
@@ -133,7 +131,9 @@
   */
 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+#if defined(FLASH_ACR_LATENCY)
 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
+#endif /* FLASH_ACR_LATENCY */
 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
 static ErrorStatus UTILS_PLL_IsBusy(void);
 /**
@@ -268,7 +268,6 @@
     /* Force PREDIV value to 2 */
     UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
-
     /* Calculate the new PLL output frequency */
     pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
 
@@ -426,7 +425,7 @@
 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
       LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
 #else
-      LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
+    LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
 
     /* Enable PLL and switch system clock to PLL */
@@ -460,6 +459,7 @@
   *          - SUCCESS: Latency has been modified
   *          - ERROR: Latency cannot be modified
   */
+#if defined(FLASH_ACR_LATENCY)
 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
 {
   ErrorStatus status = SUCCESS;
@@ -491,6 +491,7 @@
   }
   return status;
 }
+#endif /* FLASH_ACR_LATENCY */
 
 /**
   * @brief  Function to check that PLL can be modified
@@ -536,7 +537,6 @@
     status = ERROR;
   }
 
-
   return status;
 }
 
@@ -558,7 +558,7 @@
   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
 
   /* Calculate current SYSCLK frequency */
-  sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >>  RCC_POSITION_HPRE]);
+  sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]);
 
   /* Increasing the number of wait states because of higher CPU frequency */
   if (sysclk_frequency_current < SYSCLK_Frequency)

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_utils.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of UTILS LL module.
   @verbatim
   ==============================================================================
@@ -75,7 +73,7 @@
   */
 
 /* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY                  (uint32_t)0xFFFFFFFFU
+#define LL_MAX_DELAY                  0xFFFFFFFFU
 
 /**
  * @brief Unique device ID register base address
@@ -158,8 +156,8 @@
 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
   * @{
   */
-#define LL_UTILS_HSEBYPASS_OFF        (uint32_t)0x00000000U       /*!< HSE Bypass is not enabled                */
-#define LL_UTILS_HSEBYPASS_ON         (uint32_t)0x00000001U       /*!< HSE Bypass is enabled                    */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
 /**
   * @}
   */
@@ -217,6 +215,7 @@
   return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
 }
 
+
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f0xx_ll_wwdg.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    27-May-2016
   * @brief   Header file of WWDG LL module.
   ******************************************************************************
   * @attention
@@ -82,7 +80,7 @@
 /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
 * @{
 */
-#define LL_WWDG_PRESCALER_1                (uint32_t)0x00000000U                                   /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_1                0x00000000U                                             /*!< WWDG counter clock = (PCLK1/4096)/1 */
 #define LL_WWDG_PRESCALER_2                WWDG_CFR_WDGTB_0                                        /*!< WWDG counter clock = (PCLK1/4096)/2 */
 #define LL_WWDG_PRESCALER_4                WWDG_CFR_WDGTB_1                                        /*!< WWDG counter clock = (PCLK1/4096)/4 */
 #define LL_WWDG_PRESCALER_8                (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                   /*!< WWDG counter clock = (PCLK1/4096)/8 */

--- a/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c	Wed Jan 17 15:23:54 2018 +0000
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f0xx.c
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
   *
   * This file provides two functions and one global variable to be called from

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,175 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "mbed_critical.h"
+
+#if DEVICE_FLASH
+#include "mbed_assert.h"
+#include "cmsis.h"
+
+#ifndef FLASH_SIZE
+#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U)
+#endif
+
+// Minimum number of bytes to be programmed at a time
+#define MIN_PROG_SIZE (4U)
+
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Flash */
+    if (HAL_FLASH_Unlock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+static int32_t flash_lock(void)
+{
+    /* Disable the Flash option control register access (recommended to protect
+    the option Bytes against possible unwanted operations) */
+    if (HAL_FLASH_Lock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+int32_t flash_init(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    uint32_t PAGEError = 0;
+    FLASH_EraseInitTypeDef EraseInitStruct;
+    int32_t status = 0;
+
+    if (!(IS_FLASH_PROGRAM_ADDRESS(address))) {
+        return -1;
+    }
+
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
+    // Clear Flash status register's flags
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
+
+    /* MBED HAL erases 1 sector at a time */
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.PageAddress = address;
+    EraseInitStruct.NbPages     = 1;
+
+    /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
+     you have to make sure that these data are rewritten before they are accessed during code
+     execution. If this cannot be done safely, it is recommended to flush the caches by setting the
+     DCRST and ICRST bits in the FLASH_CR register. */
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
+        status = -1;
+    }
+
+    flash_lock();
+
+    return status;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+    uint32_t StartAddress = 0;
+    int32_t status = 0;
+
+    if (!(IS_FLASH_PROGRAM_ADDRESS(address))) {
+        return -1;
+    }
+
+    if ((size % MIN_PROG_SIZE) != 0) {
+        return -1;
+    }
+
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
+    /* Program the user Flash area word by word */
+    StartAddress = address;
+
+    /* HW needs an aligned address to program flash, which data parameter doesn't ensure */
+    if ((uint32_t) data % 4 != 0) {
+
+        volatile uint32_t data32;
+        while (address < (StartAddress + size) && (status == 0)) {
+            for (uint8_t i = 0; i < MIN_PROG_SIZE; i++) {
+                *(((uint8_t *) &data32) + i) = *(data + i);
+            }
+
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) {
+                address = address + MIN_PROG_SIZE;
+                data = data + MIN_PROG_SIZE;
+            } else {
+                status = -1;
+            }
+        }
+    } else { /*  case where data is aligned, so let's avoid any copy */
+        while ((address < (StartAddress + size)) && (status == 0)) {
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
+                address = address + MIN_PROG_SIZE;
+                data = data + MIN_PROG_SIZE;
+            } else {
+                status = -1;
+            }
+        }
+    }
+
+    flash_lock();
+
+    return status;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    if (!(IS_FLASH_PROGRAM_ADDRESS(address))) {
+        return MBED_FLASH_INVALID_SIZE;
+    } else {
+        return FLASH_PAGE_SIZE;
+    }
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return MIN_PROG_SIZE;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    return FLASH_BASE;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+    return FLASH_SIZE;
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,234 +27,26 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
-#include "mbed_assert.h"
-#include "serial_api.h"
-#include "serial_api_hal.h"
 
 #if DEVICE_SERIAL
 
-#include "cmsis.h"
-#include "pinmap.h"
-#include <string.h>
-#include "PeripheralPins.h"
-#include "mbed_error.h"
+#include "serial_api_hal.h"
 
-#if defined (TARGET_STM32F091RC)
-    #define UART_NUM (8)
+#if defined (TARGET_STM32F031K6)
+    #define UART_NUM (1)
 #elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) || defined (TARGET_STM32F042K6)
     #define UART_NUM (2)
-#elif defined (TARGET_STM32F031K6)
-    #define UART_NUM (1)
+#elif defined (TARGET_STM32F070RB) || defined (TARGET_STM32F072RB)
+    #define UART_NUM (4)
 #else
-    #define UART_NUM (4)
+    #define UART_NUM (8) // max value (TARGET_STM32F091RC)
 #endif
 
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+uint32_t serial_irq_ids[UART_NUM] = {0};
 UART_HandleTypeDef uart_handlers[UART_NUM];
 
 static uart_irq_handler irq_handler;
 
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-    
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj_s->uart != (UARTName)NC);
-
-    // Enable USART clock
-    if (obj_s->uart == UART_1) {
-        __HAL_RCC_USART1_FORCE_RESET();
-        __HAL_RCC_USART1_RELEASE_RESET();
-        __HAL_RCC_USART1_CLK_ENABLE();
-        obj_s->index = 0;
-    }
-
-#if defined USART2_BASE
-    if (obj_s->uart == UART_2) {
-        __HAL_RCC_USART2_FORCE_RESET();
-        __HAL_RCC_USART2_RELEASE_RESET();
-        __HAL_RCC_USART2_CLK_ENABLE();
-        obj_s->index = 1;
-    }
-#endif
-
-#if defined USART3_BASE
-    if (obj_s->uart == UART_3) {
-        __HAL_RCC_USART3_FORCE_RESET();
-        __HAL_RCC_USART3_RELEASE_RESET();
-        __HAL_RCC_USART3_CLK_ENABLE();
-        obj_s->index = 2;
-    }
-#endif
-
-#if defined USART4_BASE
-    if (obj_s->uart == UART_4) {
-        __HAL_RCC_USART4_FORCE_RESET();
-        __HAL_RCC_USART4_RELEASE_RESET();
-        __HAL_RCC_USART4_CLK_ENABLE();
-        obj_s->index = 3;
-    }
-#endif
-
-#if defined USART5_BASE
-    if (obj_s->uart == UART_5) {
-        __HAL_RCC_USART5_FORCE_RESET();
-        __HAL_RCC_USART5_RELEASE_RESET();
-        __HAL_RCC_USART5_CLK_ENABLE();
-        obj_s->index = 4;
-    }
-#endif
-
-#if defined USART6_BASE
-    if (obj_s->uart == UART_6) {
-        __HAL_RCC_USART6_FORCE_RESET();
-        __HAL_RCC_USART6_RELEASE_RESET();
-        __HAL_RCC_USART6_CLK_ENABLE();
-        obj_s->index = 5;
-    }
-#endif
-
-#if defined USART7_BASE
-    if (obj_s->uart == UART_7) {
-        __HAL_RCC_USART7_FORCE_RESET();
-        __HAL_RCC_USART7_RELEASE_RESET();
-        __HAL_RCC_USART7_CLK_ENABLE();
-        obj_s->index = 6;
-    }
-#endif
-
-#if defined USART8_BASE
-    if (obj_s->uart == UART_8) {
-        __HAL_RCC_USART8_FORCE_RESET();
-        __HAL_RCC_USART8_RELEASE_RESET();
-        __HAL_RCC_USART8_CLK_ENABLE();
-        obj_s->index = 7;
-    }
-#endif
-
-    // Configure the UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj_s->baudrate = 9600;
-    obj_s->databits = UART_WORDLENGTH_8B;
-    obj_s->stopbits = UART_STOPBITS_1;
-    obj_s->parity   = UART_PARITY_NONE;
-    
-#if DEVICE_SERIAL_FC
-    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
-#endif
-
-    obj_s->pin_tx = tx;
-    obj_s->pin_rx = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj_s->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-      
-    // Reset UART and disable clock
-    if (obj_s->uart == UART_1) {
-        __HAL_RCC_USART1_FORCE_RESET();
-        __HAL_RCC_USART1_RELEASE_RESET();
-        __HAL_RCC_USART1_CLK_DISABLE();
-    }
-
-#if defined(USART2_BASE)
-    if (obj_s->uart == UART_2) {
-         __HAL_RCC_USART2_FORCE_RESET();
-         __HAL_RCC_USART2_RELEASE_RESET();
-         __HAL_RCC_USART2_CLK_DISABLE();
-    }
-#endif
-
-#if defined USART3_BASE
-    if (obj_s->uart == UART_3) {
-        __HAL_RCC_USART3_FORCE_RESET();
-        __HAL_RCC_USART3_RELEASE_RESET();
-        __HAL_RCC_USART3_CLK_DISABLE();
-    }
-#endif
-
-#if defined USART4_BASE
-    if (obj_s->uart == UART_4) {
-        __HAL_RCC_USART4_FORCE_RESET();
-        __HAL_RCC_USART4_RELEASE_RESET();
-        __HAL_RCC_USART4_CLK_DISABLE();
-    }
-#endif
-
-#if defined USART5_BASE
-    if (obj_s->uart == UART_5) {
-        __HAL_RCC_USART5_FORCE_RESET();
-        __HAL_RCC_USART5_RELEASE_RESET();
-        __HAL_RCC_USART5_CLK_DISABLE();
-    }
-#endif
-
-#if defined USART6_BASE
-    if (obj_s->uart == UART_6) {
-        __HAL_RCC_USART6_FORCE_RESET();
-        __HAL_RCC_USART6_RELEASE_RESET();
-        __HAL_RCC_USART6_CLK_DISABLE();
-    }
-#endif
-
-#if defined USART7_BASE
-    if (obj_s->uart == UART_7) {
-        __HAL_RCC_USART7_FORCE_RESET();
-        __HAL_RCC_USART7_RELEASE_RESET();
-        __HAL_RCC_USART7_CLK_DISABLE();
-    }
-#endif
-
-#if defined USART8_BASE
-    if (obj_s->uart == UART_8) {
-        __HAL_RCC_USART8_FORCE_RESET();
-        __HAL_RCC_USART8_RELEASE_RESET();
-        __HAL_RCC_USART8_CLK_DISABLE();
-    }
-#endif
-
-    // Configure GPIOs
-    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj_s->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-
-    obj_s->baudrate = baudrate;
-    init_uart(obj);
-}
-
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
@@ -884,7 +676,7 @@
     }
 }
 
-#endif
+#endif /* DEVICE_SERIAL_ASYNCH */
 
 #if DEVICE_SERIAL_FC
 
@@ -943,6 +735,6 @@
     init_uart(obj);
 }
 
-#endif
+#endif /* DEVICE_SERIAL_FC */
 
-#endif
+#endif /* DEVICE_SERIAL */

--- a/targets/TARGET_STM/TARGET_STM32F1/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,193 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "mbed_wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-
-int adc_inited = 0;
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-    RCC_PeriphCLKInitTypeDef  PeriphClkInit;
-    uint32_t function = (uint32_t)NC;
-
-    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
-    //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be between 0xF0 and 0xFF
-    if ((pin < 0xF0) || (pin >= 0x100)) {
-        // Normal channels
-        // Get the peripheral name from the pin and assign it to the object
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
-        // Get the functions (adc channel) from the pin and assign it to the object
-        function = pinmap_function(pin, PinMap_ADC);
-        // Configure GPIO
-        pinmap_pinout(pin, PinMap_ADC);
-    } else {
-        // Internal channels
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
-        function = pinmap_function(pin, PinMap_ADC_Internal);
-        // No GPIO configuration for internal channels
-    }
-    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-    MBED_ASSERT(function != (uint32_t)NC);
-
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // The ADC initialization is done once
-    if (adc_inited == 0) {
-        adc_inited = 1;
-
-        // Enable ADC clock
-        __HAL_RCC_ADC1_CLK_ENABLE();
-
-        // Configure ADC clock prescaler
-        // Caution: On STM32F1, ADC clock frequency max is 14 MHz (refer to device datasheet).
-        // Therefore, ADC clock prescaler must be configured in function
-        // of ADC clock source frequency to remain below this maximum frequency.
-        // with 8 MHz external xtal: PCLK2 = 72 MHz --> ADC clock = 72/6 = 12 MHz
-        // with internal clock     : PCLK2 = 64 MHz --> ADC clock = 64/6 = 10.67 MHz
-        PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
-        PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
-        HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
-
-        // Configure ADC
-        obj->handle.State = HAL_ADC_STATE_RESET;
-        obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-        obj->handle.Init.ScanConvMode          = DISABLE;
-        obj->handle.Init.ContinuousConvMode    = DISABLE;
-        obj->handle.Init.NbrOfConversion       = 1;
-        obj->handle.Init.DiscontinuousConvMode = DISABLE;
-        obj->handle.Init.NbrOfDiscConversion   = 0;
-        obj->handle.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
-        HAL_ADC_Init(&obj->handle);
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj)
-{
-    ADC_ChannelConfTypeDef sConfig;
-
-    // Configure ADC channel
-    sConfig.Rank         = 1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5;
-
-    switch (obj->channel) {
-        case 0:
-            sConfig.Channel = ADC_CHANNEL_0;
-            break;
-        case 1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case 2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case 3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case 4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case 5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case 6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case 7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case 8:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case 9:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case 10:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case 11:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case 12:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case 13:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case 14:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case 15:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-        case 16:
-            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
-            break;
-        case 17:
-            sConfig.Channel = ADC_CHANNEL_VREFINT;
-            break;
-        default:
-            return 0;
-    }
-
-    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
-
-    HAL_ADC_Start(&obj->handle); // Start conversion
-
-    // Wait end of conversion and get value
-    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
-        return (HAL_ADC_GetValue(&obj->handle));
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/analogin_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,184 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include <stdbool.h>
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    static bool adc_calibrated = false;
+    RCC_PeriphCLKInitTypeDef  PeriphClkInit;
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
+    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // Enable ADC clock
+    __HAL_RCC_ADC1_CLK_ENABLE();
+
+    // Configure ADC object structures
+    obj->handle.State = HAL_ADC_STATE_RESET;
+    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+    obj->handle.Init.ScanConvMode          = DISABLE;
+    obj->handle.Init.ContinuousConvMode    = DISABLE;
+    obj->handle.Init.NbrOfConversion       = 1;
+    obj->handle.Init.DiscontinuousConvMode = DISABLE;
+    obj->handle.Init.NbrOfDiscConversion   = 0;
+    obj->handle.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
+
+    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+        error("Cannot initialize ADC");
+    }
+
+    // This section is done only once
+    if (!adc_calibrated) {
+        adc_calibrated = true;
+        // Configure ADC clock prescaler
+        // Caution: On STM32F1, ADC clock frequency max is 14 MHz (refer to device datasheet).
+        // Therefore, ADC clock prescaler must be configured in function
+        // of ADC clock source frequency to remain below this maximum frequency.
+        // with 8 MHz external xtal: PCLK2 = 72 MHz --> ADC clock = 72/6 = 12 MHz
+        // with internal clock     : PCLK2 = 64 MHz --> ADC clock = 64/6 = 10.67 MHz
+        PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+        PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
+        HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+        // Calibration
+        HAL_ADCEx_Calibration_Start(&obj->handle);
+    }
+}
+
+uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    // Configure ADC channel
+    sConfig.Rank         = 1;
+    sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5;
+
+    switch (obj->channel) {
+        case 0:
+            sConfig.Channel = ADC_CHANNEL_0;
+            break;
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+            break;
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_VREFINT;
+            break;
+        default:
+            return 0;
+    }
+
+    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+    HAL_ADC_Start(&obj->handle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+        return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+    } else {
+        return 0;
+    }
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h	Wed Jan 17 15:23:54 2018 +0000
@@ -124,6 +124,13 @@
 };
 #endif
 
+#if DEVICE_FLASH
+struct flash_s {
+    /*  nothing to be stored for now */
+    uint32_t dummy;
+};
+#endif
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,175 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "mbed_critical.h"
+
+#if DEVICE_FLASH
+#include "mbed_assert.h"
+#include "cmsis.h"
+
+#ifndef FLASH_SIZE
+#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U)
+#endif
+
+// Minimum number of bytes to be programmed at a time
+#define MIN_PROG_SIZE (4U)
+
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Flash */
+    if (HAL_FLASH_Unlock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+static int32_t flash_lock(void)
+{
+    /* Disable the Flash option control register access (recommended to protect
+    the option Bytes against possible unwanted operations) */
+    if (HAL_FLASH_Lock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+int32_t flash_init(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    uint32_t PAGEError = 0;
+    FLASH_EraseInitTypeDef EraseInitStruct;
+    int32_t status = 0;
+
+    if (!(IS_FLASH_PROGRAM_ADDRESS(address))) {
+        return -1;
+    }
+
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
+    // Clear Flash status register's flags
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_OPTVERR);
+
+    /* MBED HAL erases 1 sector at a time */
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.PageAddress = address;
+    EraseInitStruct.NbPages     = 1;
+
+    /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
+     you have to make sure that these data are rewritten before they are accessed during code
+     execution. If this cannot be done safely, it is recommended to flush the caches by setting the
+     DCRST and ICRST bits in the FLASH_CR register. */
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
+        status = -1;
+    }
+
+    flash_lock();
+
+    return status;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+    uint32_t StartAddress = 0;
+    int32_t status = 0;
+
+    if (!(IS_FLASH_PROGRAM_ADDRESS(address))) {
+        return -1;
+    }
+
+    if ((size % MIN_PROG_SIZE) != 0) {
+        return -1;
+    }
+
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
+    /* Program the user Flash area word by word */
+    StartAddress = address;
+
+    /* HW needs an aligned address to program flash, which data parameter doesn't ensure */
+    if ((uint32_t) data % 4 != 0) {
+
+        volatile uint32_t data32;
+        while (address < (StartAddress + size) && (status == 0)) {
+            for (uint8_t i = 0; i < MIN_PROG_SIZE; i++) {
+                *(((uint8_t *) &data32) + i) = *(data + i);
+            }
+
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) {
+                address = address + MIN_PROG_SIZE;
+                data = data + MIN_PROG_SIZE;
+            } else {
+                status = -1;
+            }
+        }
+    } else { /*  case where data is aligned, so let's avoid any copy */
+        while ((address < (StartAddress + size)) && (status == 0)) {
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
+                address = address + MIN_PROG_SIZE;
+                data = data + MIN_PROG_SIZE;
+            } else {
+                status = -1;
+            }
+        }
+    }
+
+    flash_lock();
+
+    return status;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    if (!(IS_FLASH_PROGRAM_ADDRESS(address))) {
+        return MBED_FLASH_INVALID_SIZE;
+    } else {
+        return FLASH_PAGE_SIZE;
+    }
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return MIN_PROG_SIZE;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    return FLASH_BASE;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+    return FLASH_SIZE;
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,129 +27,18 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
-#include "mbed_assert.h"
-#include "serial_api.h"
-#include "serial_api_hal.h"
 
 #if DEVICE_SERIAL
 
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include <string.h>
-#include "PeripheralPins.h"
+#include "serial_api_hal.h"
 
 #define UART_NUM (3)
 
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+uint32_t serial_irq_ids[UART_NUM] = {0};
 UART_HandleTypeDef uart_handlers[UART_NUM];
 
 static uart_irq_handler irq_handler;
 
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-    
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj_s->uart != (UARTName)NC);
-
-    // Enable USART clock
-    if (obj_s->uart == UART_1) {
-        __HAL_RCC_USART1_FORCE_RESET();
-        __HAL_RCC_USART1_RELEASE_RESET();
-        __HAL_RCC_USART1_CLK_ENABLE();
-        obj_s->index = 0;
-    }
-    if (obj_s->uart == UART_2) {
-        __HAL_RCC_USART2_FORCE_RESET();
-        __HAL_RCC_USART2_RELEASE_RESET();
-        __HAL_RCC_USART2_CLK_ENABLE();
-        obj_s->index = 1;
-    }
-    if (obj_s->uart == UART_3) {
-        __HAL_RCC_USART3_FORCE_RESET();
-        __HAL_RCC_USART3_RELEASE_RESET();
-        __HAL_RCC_USART3_CLK_ENABLE();
-        obj_s->index = 2;
-    }
-
-    // Configure UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj_s->baudrate = 9600;
-    obj_s->databits = UART_WORDLENGTH_8B;
-    obj_s->stopbits = UART_STOPBITS_1;
-    obj_s->parity   = UART_PARITY_NONE;
-    
-#if DEVICE_SERIAL_FC
-    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
-#endif
-
-    obj_s->pin_tx = tx;
-    obj_s->pin_rx = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj_s->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-      
-    // Reset UART and disable clock
-    if (obj_s->uart == UART_1) {
-        __HAL_RCC_USART1_FORCE_RESET();
-        __HAL_RCC_USART1_RELEASE_RESET();
-        __HAL_RCC_USART1_CLK_DISABLE();
-    }
-    if (obj_s->uart == UART_2) {
-        __HAL_RCC_USART2_FORCE_RESET();
-        __HAL_RCC_USART2_RELEASE_RESET();
-        __HAL_RCC_USART2_CLK_DISABLE();
-    }
-    if (obj_s->uart == UART_3) {
-        __HAL_RCC_USART3_FORCE_RESET();
-        __HAL_RCC_USART3_RELEASE_RESET();
-        __HAL_RCC_USART3_CLK_DISABLE();
-    }
-
-    // Configure GPIOs
-    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj_s->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-
-    obj_s->baudrate = baudrate;
-    init_uart(obj);
-}
-
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
@@ -687,7 +576,7 @@
     }
 }
 
-#endif
+#endif /* DEVICE_SERIAL_ASYNCH */
 
 #if DEVICE_SERIAL_FC
 
@@ -746,6 +635,6 @@
     init_uart(obj);
 }
 
-#endif
+#endif /* DEVICE_SERIAL_FC */
 
-#endif
+#endif /* DEVICE_SERIAL */

--- a/targets/TARGET_STM/TARGET_STM32F2/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,216 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "mbed_wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-    uint32_t function = (uint32_t)NC;
-
-#if defined(ADC1)
-    static int adc1_inited = 0;
-#endif
-#if defined(ADC2)
-    static int adc2_inited = 0;
-#endif
-#if defined(ADC3)
-    static int adc3_inited = 0;
-#endif
-    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
-    //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be between 0xF0 and 0xFF
-    if ((pin < 0xF0) || (pin >= 0x100)) {
-        // Normal channels
-        // Get the peripheral name from the pin and assign it to the object
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
-        // Get the functions (adc channel) from the pin and assign it to the object
-        function = pinmap_function(pin, PinMap_ADC);
-        // Configure GPIO
-        pinmap_pinout(pin, PinMap_ADC);
-    } else {
-        // Internal channels
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
-        function = pinmap_function(pin, PinMap_ADC_Internal);
-        // No GPIO configuration for internal channels
-    }
-    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-    MBED_ASSERT(function != (uint32_t)NC);
-
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // Check if ADC is already initialized
-    // Enable ADC clock
-#if defined(ADC1)
-    if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_1) {
-        __ADC1_CLK_ENABLE();
-        adc1_inited = 1;
-    }
-#endif
-#if defined(ADC2)
-    if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_2) {
-        __ADC2_CLK_ENABLE();
-        adc2_inited = 1;
-    }
-#endif
-#if defined(ADC3)
-    if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_3) {
-        __ADC3_CLK_ENABLE();
-        adc3_inited = 1;
-    }
-#endif
-    // Configure ADC
-    obj->handle.State = HAL_ADC_STATE_RESET;
-    obj->handle.Init.ClockPrescaler        = ADC_CLOCKPRESCALER_PCLK_DIV2;
-    obj->handle.Init.Resolution            = ADC_RESOLUTION12b;
-    obj->handle.Init.ScanConvMode          = DISABLE;
-    obj->handle.Init.ContinuousConvMode    = DISABLE;
-    obj->handle.Init.DiscontinuousConvMode = DISABLE;
-    obj->handle.Init.NbrOfDiscConversion   = 0;
-    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
-    obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIGCONV_T1_CC1;
-    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-    obj->handle.Init.NbrOfConversion       = 1;
-    obj->handle.Init.DMAContinuousRequests = DISABLE;
-    obj->handle.Init.EOCSelection          = DISABLE;
-    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
-        error("Cannot initialize ADC\n");
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj)
-{
-    ADC_ChannelConfTypeDef sConfig = {0};
-
-    // Configure ADC channel
-    sConfig.Rank         = 1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
-    sConfig.Offset       = 0;
-
-    switch (obj->channel) {
-        case 0:
-            sConfig.Channel = ADC_CHANNEL_0;
-            break;
-        case 1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case 2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case 3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case 4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case 5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case 6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case 7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case 8:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case 9:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case 10:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case 11:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case 12:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case 13:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case 14:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case 15:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-        case 16:
-            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
-            break;
-        case 17:
-            sConfig.Channel = ADC_CHANNEL_VREFINT;
-            break;
-        case 18:
-            sConfig.Channel = ADC_CHANNEL_VBAT;
-            break;
-        default:
-            return 0;
-    }
-
-    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
-
-    HAL_ADC_Start(&obj->handle); // Start conversion
-
-    // Wait end of conversion and get value
-    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
-        return (HAL_ADC_GetValue(&obj->handle));
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F2/analogin_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,187 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
+    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // Configure ADC object structures
+    obj->handle.State = HAL_ADC_STATE_RESET;
+    obj->handle.Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV2;
+    obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
+    obj->handle.Init.ScanConvMode          = DISABLE;
+    obj->handle.Init.ContinuousConvMode    = DISABLE;
+    obj->handle.Init.DiscontinuousConvMode = DISABLE;
+    obj->handle.Init.NbrOfDiscConversion   = 0;
+    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
+    obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIGCONV_T1_CC1;
+    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+    obj->handle.Init.NbrOfConversion       = 1;
+    obj->handle.Init.DMAContinuousRequests = DISABLE;
+    obj->handle.Init.EOCSelection          = DISABLE;
+
+#if defined(ADC1)
+    if ((ADCName)obj->handle.Instance == ADC_1) {
+        __HAL_RCC_ADC1_CLK_ENABLE();
+    }
+#endif
+#if defined(ADC2)
+    if ((ADCName)obj->handle.Instance == ADC_2) {
+        __HAL_RCC_ADC2_CLK_ENABLE();
+    }
+#endif
+#if defined(ADC3)
+    if ((ADCName)obj->handle.Instance == ADC_3) {
+        __HAL_RCC_ADC3_CLK_ENABLE();
+    }
+#endif
+
+    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+        error("Cannot initialize ADC");
+    }
+}
+
+uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    // Configure ADC channel
+    sConfig.Rank         = 1;
+    sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES;
+    sConfig.Offset       = 0;
+
+    switch (obj->channel) {
+        case 0:
+            sConfig.Channel = ADC_CHANNEL_0;
+            break;
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+            break;
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_VREFINT;
+            break;
+        case 18:
+            sConfig.Channel = ADC_CHANNEL_VBAT;
+            break;
+        default:
+            return 0;
+    }
+
+    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+    HAL_ADC_Start(&obj->handle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+        return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+    } else {
+        return 0;
+    }
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_def.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_def.h	Wed Jan 17 15:23:54 2018 +0000
@@ -130,9 +130,9 @@
 {
 	uint32_t newValue;
 	do {
-		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
+		newValue = (uint32_t)__LDREXW(ptr) | mask;
 
-	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+	} while (__STREXW(newValue, ptr));
 }
 
 
@@ -140,9 +140,9 @@
 {
 	uint32_t newValue;
 	do {
-		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
+		newValue = (uint32_t)__LDREXW(ptr) &~mask;
 
-	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+	} while (__STREXW(newValue, ptr));
 }
 
 #if  defined ( __GNUC__ ) && !defined ( __CC_ARM )

--- a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,216 +27,18 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
-#include "mbed_assert.h"
-#include "serial_api.h"
-#include "serial_api_hal.h"
 
 #if DEVICE_SERIAL
 
-#include "cmsis.h"
-#include "pinmap.h"
-#include <string.h>
-#include "PeripheralPins.h"
-#include "mbed_error.h"
+#include "serial_api_hal.h"
 
-#define UART_NUM (8)
+#define UART_NUM (6)
 
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+uint32_t serial_irq_ids[UART_NUM] = {0};
 UART_HandleTypeDef uart_handlers[UART_NUM];
 
 static uart_irq_handler irq_handler;
 
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-    
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj_s->uart != (UARTName)NC);
-
-    // Enable USART clock
-    switch (obj_s->uart) {
-        case UART_1:
-            __HAL_RCC_USART1_FORCE_RESET();
-            __HAL_RCC_USART1_RELEASE_RESET();
-            __HAL_RCC_USART1_CLK_ENABLE();
-            obj_s->index = 0;
-            break;
-
-        case UART_2:
-            __HAL_RCC_USART2_FORCE_RESET();
-            __HAL_RCC_USART2_RELEASE_RESET();
-            __HAL_RCC_USART2_CLK_ENABLE();
-            obj_s->index = 1;
-            break;
-
-#if defined(USART3_BASE)
-        case UART_3:
-            __HAL_RCC_USART3_FORCE_RESET();
-            __HAL_RCC_USART3_RELEASE_RESET();
-            __HAL_RCC_USART3_CLK_ENABLE();
-            obj_s->index = 2;
-            break;
-#endif
-#if defined(UART4_BASE)
-        case UART_4:
-            __HAL_RCC_UART4_FORCE_RESET();
-            __HAL_RCC_UART4_RELEASE_RESET();
-            __HAL_RCC_UART4_CLK_ENABLE();
-            obj_s->index = 3;
-            break;
-#endif
-#if defined(UART5_BASE)
-        case UART_5:
-            __HAL_RCC_UART5_FORCE_RESET();
-            __HAL_RCC_UART5_RELEASE_RESET();
-            __HAL_RCC_UART5_CLK_ENABLE();
-            obj_s->index = 4;
-            break;
-#endif
-#if defined(USART6_BASE)
-        case UART_6:
-            __HAL_RCC_USART6_FORCE_RESET();
-            __HAL_RCC_USART6_RELEASE_RESET();
-            __HAL_RCC_USART6_CLK_ENABLE();
-            obj_s->index = 5;
-            break;
-#endif
-#if defined(UART7_BASE)
-        case UART_7:
-            __HAL_RCC_UART7_FORCE_RESET();
-            __HAL_RCC_UART7_RELEASE_RESET();
-            __HAL_RCC_UART7_CLK_ENABLE();
-            obj_s->index = 6;
-            break;
-#endif
-#if defined(UART8_BASE)
-        case UART_8:
-            __HAL_RCC_UART8_FORCE_RESET();
-            __HAL_RCC_UART8_RELEASE_RESET();
-            __HAL_RCC_UART8_CLK_ENABLE();
-            obj_s->index = 7;
-            break;
-#endif
-    }
-
-    // Configure the UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj_s->baudrate = 9600;
-    obj_s->databits = UART_WORDLENGTH_8B;
-    obj_s->stopbits = UART_STOPBITS_1;
-    obj_s->parity   = UART_PARITY_NONE;
-    
-#if DEVICE_SERIAL_FC
-    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
-#endif
-
-    obj_s->pin_tx = tx;
-    obj_s->pin_rx = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj_s->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-      
-    // Reset UART and disable clock
-    switch (obj_s->index) {
-        case 0:
-            __USART1_FORCE_RESET();
-            __USART1_RELEASE_RESET();
-            __USART1_CLK_DISABLE();
-            break;
-
-        case 1:
-            __USART2_FORCE_RESET();
-            __USART2_RELEASE_RESET();
-            __USART2_CLK_DISABLE();
-            break;
-
-#if defined(USART3_BASE)
-        case 2:
-            __USART3_FORCE_RESET();
-            __USART3_RELEASE_RESET();
-            __USART3_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART4_BASE)
-        case 3:
-            __UART4_FORCE_RESET();
-            __UART4_RELEASE_RESET();
-            __UART4_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART5_BASE)
-        case 4:
-            __UART5_FORCE_RESET();
-            __UART5_RELEASE_RESET();
-            __UART5_CLK_DISABLE();
-            break;
-#endif
-#if defined(USART6_BASE)
-        case 5:
-            __USART6_FORCE_RESET();
-            __USART6_RELEASE_RESET();
-            __USART6_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART7_BASE)
-        case 6:
-            __UART7_FORCE_RESET();
-            __UART7_RELEASE_RESET();
-            __UART7_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART8_BASE)
-        case 7:
-            __UART8_FORCE_RESET();
-            __UART8_RELEASE_RESET();
-            __UART8_CLK_DISABLE();
-            break;
-#endif
-    }
-
-    // Configure GPIOs
-    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj_s->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-
-    obj_s->baudrate = baudrate;
-    init_uart(obj);
-}
-
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
@@ -865,7 +667,7 @@
     }
 }
 
-#endif
+#endif /* DEVICE_SERIAL_ASYNCH */
 
 #if DEVICE_SERIAL_FC
 
@@ -924,6 +726,6 @@
     init_uart(obj);
 }
 
-#endif
+#endif /* DEVICE_SERIAL_FC */
 
-#endif
+#endif /* DEVICE_SERIAL */

--- a/targets/TARGET_STM/TARGET_STM32F3/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,231 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "mbed_wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-#if defined(ADC1)
-    static int adc1_inited = 0;
-#endif
-#if defined(ADC2)
-    static int adc2_inited = 0;
-#endif
-#if defined(ADC3)
-    static int adc3_inited = 0;
-#endif
-#if defined(ADC4)
-    static int adc4_inited = 0;
-#endif
-
-    uint32_t function = (uint32_t)NC;
-
-    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
-    //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be between 0xF0 and 0xFF
-    if ((pin < 0xF0) || (pin >= 0x100)) {
-        // Normal channels
-        // Get the peripheral name from the pin and assign it to the object
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
-        // Get the functions (adc channel) from the pin and assign it to the object
-        function = pinmap_function(pin, PinMap_ADC);
-        // Configure GPIO
-        pinmap_pinout(pin, PinMap_ADC);
-    } else {
-        // Internal channels
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
-        function = pinmap_function(pin, PinMap_ADC_Internal);
-        // No GPIO configuration for internal channels
-    }
-    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-    MBED_ASSERT(function != (uint32_t)NC);
-
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // Check if ADC is already initialized
-    // Enable ADC clock
-#if defined(ADC1)
-    if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_1) {
-        __ADC1_CLK_ENABLE();
-        adc1_inited = 1;
-    }
-#endif
-#if defined(ADC2)
-    if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_2) {
-        __ADC2_CLK_ENABLE();
-        adc2_inited = 1;
-    }
-#endif
-#if defined(ADC3)
-    if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_3) {
-        __ADC34_CLK_ENABLE();
-        adc3_inited = 1;
-    }
-#endif
-#if defined(ADC4)
-    if (((ADCName)obj->handle.Instance == ADC_4) && adc4_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_4) {
-        __ADC34_CLK_ENABLE();
-        adc4_inited = 1;
-    }
-#endif
-
-    // Configure ADC
-    obj->handle.State = HAL_ADC_STATE_RESET;
-    obj->handle.Init.ClockPrescaler        = ADC_CLOCKPRESCALER_PCLK_DIV2;
-    obj->handle.Init.Resolution            = ADC_RESOLUTION12b;
-    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-    obj->handle.Init.ScanConvMode          = DISABLE;
-    obj->handle.Init.EOCSelection          = EOC_SINGLE_CONV;
-    obj->handle.Init.LowPowerAutoWait      = DISABLE;
-    obj->handle.Init.ContinuousConvMode    = DISABLE;
-    obj->handle.Init.NbrOfConversion       = 1;
-    obj->handle.Init.DiscontinuousConvMode = DISABLE;
-    obj->handle.Init.NbrOfDiscConversion   = 0;
-    obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIGCONV_T1_CC1;
-    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
-    obj->handle.Init.DMAContinuousRequests = DISABLE;
-    obj->handle.Init.Overrun               = OVR_DATA_OVERWRITTEN;
-
-    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
-        error("Cannot initialize ADC");
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj)
-{
-    ADC_ChannelConfTypeDef sConfig = {0};
-
-    // Configure ADC channel
-    sConfig.Rank         = ADC_REGULAR_RANK_1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_19CYCLES_5;
-    sConfig.SingleDiff   = ADC_SINGLE_ENDED;
-    sConfig.OffsetNumber = ADC_OFFSET_NONE;
-    sConfig.Offset       = 0;
-
-    switch (obj->channel) {
-        case 1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case 2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case 3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case 4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case 5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case 6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case 7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case 8:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case 9:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case 10:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case 11:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case 12:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case 13:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case 14:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case 15:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-        case 16:
-            sConfig.Channel = ADC_CHANNEL_16;
-            break;
-        case 17:
-            sConfig.Channel = ADC_CHANNEL_17;
-            break;
-        case 18:
-            sConfig.Channel = ADC_CHANNEL_18;
-            break;
-        default:
-            return 0;
-    }
-
-    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
-
-    HAL_ADC_Start(&obj->handle); // Start conversion
-
-    // Wait end of conversion and get value
-    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
-        return (HAL_ADC_GetValue(&obj->handle));
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/analogin_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,201 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include <stdbool.h>
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    static bool adc_calibrated = false;
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
+    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // Configure ADC object structures
+    obj->handle.State = HAL_ADC_STATE_RESET;
+    obj->handle.Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV2;
+    obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
+    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+    obj->handle.Init.ScanConvMode          = DISABLE;
+    obj->handle.Init.EOCSelection          = EOC_SINGLE_CONV;
+    obj->handle.Init.LowPowerAutoWait      = DISABLE;
+    obj->handle.Init.ContinuousConvMode    = DISABLE;
+    obj->handle.Init.NbrOfConversion       = 1;
+    obj->handle.Init.DiscontinuousConvMode = DISABLE;
+    obj->handle.Init.NbrOfDiscConversion   = 0;
+    obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIGCONV_T1_CC1;
+    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
+    obj->handle.Init.DMAContinuousRequests = DISABLE;
+    obj->handle.Init.Overrun               = OVR_DATA_OVERWRITTEN;
+
+#if defined(ADC1)
+    if ((ADCName)obj->handle.Instance == ADC_1) {
+        __HAL_RCC_ADC1_CLK_ENABLE();
+    }
+#endif
+#if defined(ADC2)
+    if ((ADCName)obj->handle.Instance == ADC_2) {
+        __HAL_RCC_ADC2_CLK_ENABLE();
+    }
+#endif
+#if defined(ADC3)
+    if ((ADCName)obj->handle.Instance == ADC_3) {
+        __HAL_RCC_ADC34_CLK_ENABLE();
+    }
+#endif
+#if defined(ADC4)
+    if ((ADCName)obj->handle.Instance == ADC_4) {
+        __HAL_RCC_ADC34_CLK_ENABLE();
+    }
+#endif
+
+    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+        error("Cannot initialize ADC");
+    }
+
+    // ADC calibration is done only once
+    if (!adc_calibrated) {
+        adc_calibrated = true;
+        HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED);
+    }
+}
+
+uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    // Configure ADC channel
+    sConfig.Rank         = ADC_REGULAR_RANK_1;
+    sConfig.SamplingTime = ADC_SAMPLETIME_19CYCLES_5;
+    sConfig.SingleDiff   = ADC_SINGLE_ENDED;
+    sConfig.OffsetNumber = ADC_OFFSET_NONE;
+    sConfig.Offset       = 0;
+
+    switch (obj->channel) {
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_16;
+            break;
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_17;
+            break;
+        case 18:
+            sConfig.Channel = ADC_CHANNEL_18;
+            break;
+        default:
+            return 0;
+    }
+
+    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+    HAL_ADC_Start(&obj->handle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+        return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+    } else {
+        return 0;
+    }
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h	Wed Jan 17 15:23:54 2018 +0000
@@ -132,6 +132,13 @@
 };
 #endif
 
+#if DEVICE_FLASH
+struct flash_s {
+    /*  nothing to be stored for now */
+    uint32_t dummy;
+};
+#endif
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus

--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h	Wed Jan 17 15:23:54 2018 +0000
@@ -447,16 +447,6 @@
 /**
   * @}
   */
-#elif  defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xE/STM32F303xE/STM32F398xx Product devices)
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLE           (0x00000000U)  /*!< Window mode disabled */
-#define COMP_WINDOWMODE_ENABLE            COMP_CSR_COMPxWNDWEN    /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U)
-                                                                       is connected to the non inverting input of comparator X-1U */
-/**
-  * @}
-  */
 #elif defined(STM32F373xC) || defined(STM32F378xx)
 /** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)
   * @{
@@ -2395,8 +2385,7 @@
     ||                                                         \
     (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
 
-#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
-                                        ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
+#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE))    /*!< Not available: check always true */ 
 
 #define IS_COMP_MODE(MODE)  ((MODE) == (MODE))  /*!< Not available: check always true */
 

--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_def.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_def.h	Wed Jan 17 15:23:54 2018 +0000
@@ -129,9 +129,9 @@
 {
 	uint32_t newValue;
 	do {
-		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
+		newValue = (uint32_t)__LDREXW(ptr) | mask;
 
-	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+	} while (__STREXW(newValue, ptr));
 }
 
 
@@ -139,9 +139,9 @@
 {
 	uint32_t newValue;
 	do {
-		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
+		newValue = (uint32_t)__LDREXW(ptr) &~mask;
 
-	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+	} while (__STREXW(newValue, ptr));
 }
 
 #if  defined ( __GNUC__ ) && !defined ( __CC_ARM )

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,175 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "mbed_critical.h"
+
+#if DEVICE_FLASH
+#include "mbed_assert.h"
+#include "cmsis.h"
+
+#ifndef FLASH_SIZE
+#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U)
+#endif
+
+// Minimum number of bytes to be programmed at a time
+#define MIN_PROG_SIZE (4U)
+
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Flash */
+    if (HAL_FLASH_Unlock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+static int32_t flash_lock(void)
+{
+    /* Disable the Flash option control register access (recommended to protect
+    the option Bytes against possible unwanted operations) */
+    if (HAL_FLASH_Lock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+int32_t flash_init(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    uint32_t PAGEError = 0;
+    FLASH_EraseInitTypeDef EraseInitStruct;
+    int32_t status = 0;
+
+    if (!(IS_FLASH_PROGRAM_ADDRESS(address))) {
+        return -1;
+    }
+
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
+    // Clear Flash status register's flags
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
+
+    /* MBED HAL erases 1 sector at a time */
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.PageAddress = address;
+    EraseInitStruct.NbPages     = 1;
+
+    /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
+     you have to make sure that these data are rewritten before they are accessed during code
+     execution. If this cannot be done safely, it is recommended to flush the caches by setting the
+     DCRST and ICRST bits in the FLASH_CR register. */
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
+        status = -1;
+    }
+
+    flash_lock();
+
+    return status;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+    uint32_t StartAddress = 0;
+    int32_t status = 0;
+
+    if (!(IS_FLASH_PROGRAM_ADDRESS(address))) {
+        return -1;
+    }
+
+    if ((size % MIN_PROG_SIZE) != 0) {
+        return -1;
+    }
+
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
+    /* Program the user Flash area word by word */
+    StartAddress = address;
+
+    /* HW needs an aligned address to program flash, which data parameter doesn't ensure */
+    if ((uint32_t) data % 4 != 0) {
+
+        volatile uint32_t data32;
+        while (address < (StartAddress + size) && (status == 0)) {
+            for (uint8_t i = 0; i < MIN_PROG_SIZE; i++) {
+                *(((uint8_t *) &data32) + i) = *(data + i);
+            }
+
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) {
+                address = address + MIN_PROG_SIZE;
+                data = data + MIN_PROG_SIZE;
+            } else {
+                status = -1;
+            }
+        }
+    } else { /*  case where data is aligned, so let's avoid any copy */
+        while ((address < (StartAddress + size)) && (status == 0)) {
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
+                address = address + MIN_PROG_SIZE;
+                data = data + MIN_PROG_SIZE;
+            } else {
+                status = -1;
+            }
+        }
+    }
+
+    flash_lock();
+
+    return status;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    if (!(IS_FLASH_PROGRAM_ADDRESS(address))) {
+        return MBED_FLASH_INVALID_SIZE;
+    } else {
+        return FLASH_PAGE_SIZE;
+    }
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return MIN_PROG_SIZE;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    return FLASH_BASE;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+    return FLASH_SIZE;
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,179 +27,21 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
-#include "mbed_assert.h"
-#include "serial_api.h"
-#include "serial_api_hal.h"
 
 #if DEVICE_SERIAL
 
-#include "cmsis.h"
-#include "pinmap.h"
-#include <string.h>
-#include "PeripheralPins.h"
-#include "mbed_error.h"
-
-#define UART_NUM (5)
-
-static uint32_t serial_irq_ids[UART_NUM] = {0};
-UART_HandleTypeDef uart_handlers[UART_NUM];
-
-uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-    
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj_s->uart != (UARTName)NC);
+#include "serial_api_hal.h"
 
-    // Enable USART clock + switch to SystemClock
-    if (obj_s->uart == UART_1) {
-        __USART1_FORCE_RESET();
-        __USART1_RELEASE_RESET();
-        __USART1_CLK_ENABLE();
-#if defined(RCC_USART1CLKSOURCE_SYSCLK) 
-        __HAL_RCC_USART1_CONFIG(RCC_USART1CLKSOURCE_SYSCLK);
-#endif
-        obj_s->index = 0;
-    }
-#if defined(USART2_BASE)
-    if (obj_s->uart == UART_2) {
-        __USART2_FORCE_RESET();
-        __USART2_RELEASE_RESET();
-        __USART2_CLK_ENABLE();
-#if defined(RCC_USART2CLKSOURCE_SYSCLK)
-        __HAL_RCC_USART2_CONFIG(RCC_USART2CLKSOURCE_SYSCLK);
-#endif
-        obj_s->index = 1;
-    }
-#endif
-#if defined(USART3_BASE)
-    if (obj_s->uart == UART_3) {
-        __USART3_FORCE_RESET();
-        __USART3_RELEASE_RESET();
-        __USART3_CLK_ENABLE();
-#if defined(RCC_USART3CLKSOURCE_SYSCLK)
-        __HAL_RCC_USART3_CONFIG(RCC_USART3CLKSOURCE_SYSCLK);
-#endif
-        obj_s->index = 2;
-    }
-#endif
-#if defined(UART4_BASE)
-    if (obj_s->uart == UART_4) {
-        __UART4_FORCE_RESET();
-        __UART4_RELEASE_RESET();
-        __UART4_CLK_ENABLE();
-#if defined(RCC_UART4CLKSOURCE_SYSCLK)
-        __HAL_RCC_UART4_CONFIG(RCC_UART4CLKSOURCE_SYSCLK);
-#endif
-        obj_s->index = 3;
-    }
-#endif
-#if defined(UART5_BASE)
-    if (obj_s->uart == UART_5) {
-        __HAL_RCC_UART5_FORCE_RESET();
-        __HAL_RCC_UART5_RELEASE_RESET();
-        __UART5_CLK_ENABLE();
-#if defined(RCC_UART5CLKSOURCE_SYSCLK)
-        __HAL_RCC_UART5_CONFIG(RCC_UART5CLKSOURCE_SYSCLK);
-#endif
-        obj_s->index = 4;
-    }
+#if defined (TARGET_STM32F302x8) || defined (TARGET_STM32F303x8) || defined (TARGET_STM32F334x8)
+    #define UART_NUM (3)
+#else
+    #define UART_NUM (5) // max value
 #endif
 
-    // Configure the UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj_s->baudrate = 9600;
-    obj_s->databits = UART_WORDLENGTH_8B;
-    obj_s->stopbits = UART_STOPBITS_1;
-    obj_s->parity   = UART_PARITY_NONE;
-
-#if DEVICE_SERIAL_FC
-    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
-#endif
-
-    obj_s->pin_tx = tx;
-    obj_s->pin_rx = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj_s->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
+uint32_t serial_irq_ids[UART_NUM] = {0};
+UART_HandleTypeDef uart_handlers[UART_NUM];
 
-void serial_free(serial_t *obj)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-      
-    // Reset UART and disable clock
-    if (obj_s->uart == UART_1) {
-        __USART1_FORCE_RESET();
-        __USART1_RELEASE_RESET();
-        __USART1_CLK_DISABLE();
-    }
-    if (obj_s->uart == UART_2) {
-        __USART2_FORCE_RESET();
-        __USART2_RELEASE_RESET();
-        __USART2_CLK_DISABLE();
-    }
-#if defined(USART3_BASE)
-    if (obj_s->uart == UART_3) {
-        __USART3_FORCE_RESET();
-        __USART3_RELEASE_RESET();
-        __USART3_CLK_DISABLE();
-    }
-#endif
-#if defined(UART4_BASE)
-    if (obj_s->uart == UART_4) {
-        __UART4_FORCE_RESET();
-        __UART4_RELEASE_RESET();
-        __UART4_CLK_DISABLE();
-    }
-#endif
-#if defined(UART5_BASE)
-    if (obj_s->uart == UART_5) {
-        __UART5_FORCE_RESET();
-        __UART5_RELEASE_RESET();
-        __UART5_CLK_DISABLE();
-    }
-#endif
-
-    // Configure GPIOs
-    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj_s->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-
-    obj_s->baudrate = baudrate;
-    init_uart(obj);
-}
+static uart_irq_handler irq_handler;
 
 /******************************************************************************
  * INTERRUPTS HANDLING
@@ -785,7 +627,7 @@
     }
 }
 
-#endif
+#endif /* DEVICE_SERIAL_ASYNCH */
 
 #if DEVICE_SERIAL_FC
 
@@ -844,6 +686,6 @@
     init_uart(obj);
 }
 
-#endif
+#endif /* DEVICE_SERIAL_FC */
 
-#endif
+#endif /* DEVICE_SERIAL */

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c	Wed Jan 17 15:23:54 2018 +0000
@@ -176,11 +176,13 @@
     }
 
     /* Select PLLSAI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
     PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
     PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
     PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
     PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+    PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
 
     HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
@@ -241,11 +243,13 @@
     }
 
     /* Select PLLSAI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
     PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
     PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
     PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
     PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+    PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
 
     HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c	Wed Jan 17 15:23:54 2018 +0000
@@ -177,11 +177,13 @@
     }
 
     /* Select PLLSAI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
     PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
     PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
     PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
     PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+    PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
 
     HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
@@ -242,11 +244,13 @@
     }
 
     /* Select PLLI2S output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
     PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
     PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
     PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
     PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+    PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
 
     HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License. 
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1  = (int)USART1_BASE,
+    UART_2  = (int)USART2_BASE,
+    UART_3  = (int)USART3_BASE,
+    UART_4  = (int)UART4_BASE,
+    UART_5  = (int)UART5_BASE,
+    UART_6  = (int)USART6_BASE,
+    UART_7  = (int)UART7_BASE,
+    UART_8  = (int)UART8_BASE,
+    UART_9  = (int)UART9_BASE,
+    UART_10 = (int)UART10_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PD_8
+#define STDIO_UART_RX  PD_9
+#define STDIO_UART     UART_3
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE,
+    SPI_4 = (int)SPI4_BASE,
+    SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1    = (int)I2C1_BASE,
+    I2C_2    = (int)I2C2_BASE,
+    I2C_3    = (int)I2C3_BASE,
+    FMPI2C_1 = (int)FMPI2C1_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_9  = (int)TIM9_BASE,
+    PWM_10 = (int)TIM10_BASE,
+    PWM_11 = (int)TIM11_BASE,
+    PWM_12 = (int)TIM12_BASE,
+    PWM_13 = (int)TIM13_BASE,
+    PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE,
+    CAN_2 = (int)CAN2_BASE,
+    CAN_3 = (int)CAN3_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,396 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+//==============================================================================
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
+    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)},
+    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)},
+    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)},
+    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)},
+    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)},
+    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)},
+    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)},
+    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // Connected to LED1
+    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)},
+    {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)},
+    {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)},
+    {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)},
+    {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)},
+    {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)},
+    {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)},
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+    {NC,       NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)},
+    {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)},
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_3,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+    {PB_3_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+    {PB_4,      I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+    {PB_7,      I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LED2
+    {PB_8,      I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+    {PB_9,      I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_9_ALT0, I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+    {PB_11,     I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_14,     FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to LED3
+    {PC_7,      FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+    {PC_9,      I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PD_13,     FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+    {PD_15,     FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+    {PF_0,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PF_15,     FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+    {NC,        NC,       0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PA_8,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PB_6,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_8,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_10_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)},
+    {PB_15,      FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+    {PC_6,       FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+    {PD_12,      FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+    {PD_14,      FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+    {PF_1,       I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PF_14,      FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+    {NC,         NC,       0}
+};
+
+//*** PWM ***
+
+// Pins using PWM_5 (TIM5) cannot be used as TIM5 is already used by ticker.
+const PinMap PinMap_PWM[] = {
+    {PA_0,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},
+//  {PA_0,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)},
+    {PA_1,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},
+//  {PA_1,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},
+    {PA_2,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},
+//  {PA_2,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},
+    {PA_2_ALT0,  PWM_9,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)},
+    {PA_3,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},
+//  {PA_3,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},
+    {PA_3,       PWM_9,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)},
+    {PA_5,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},
+    {PA_5_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},
+    {PA_6,       PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)},
+    {PA_6_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},
+    {PA_7,       PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)},
+    {PA_7_ALT0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},
+    {PA_7_ALT1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},
+    {PA_7_ALT2,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},
+    {PA_8,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},
+    {PA_9,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},
+    {PA_10,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},
+    {PA_11,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},
+    {PA_15,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},
+    {PB_0,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // Connected to LED1
+    {PB_0_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // Connected to LED1
+    {PB_0_ALT1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // Connected to LED1
+    {PB_1,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},
+    {PB_1_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},
+    {PB_1_ALT1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},
+    {PB_3,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},
+    {PB_4,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},
+    {PB_5,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},
+    {PB_6,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},
+    {PB_7,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // Connected to LED2
+    {PB_8,       PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)},
+    {PB_8_ALT0,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},
+    {PB_9,       PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)},
+    {PB_9_ALT0,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},
+    {PB_10,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},
+    {PB_11,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},
+    {PB_13,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},
+    {PB_14,      PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // Connected to LED3
+    {PB_14_ALT0, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // Connected to LED3
+    {PB_14_ALT1, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // Connected to LED3
+    {PB_15,      PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)},
+    {PB_15_ALT0, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},
+    {PB_15_ALT1, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},
+    {PC_6,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},
+    {PC_6_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)},
+    {PC_7,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},
+    {PC_7_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)},
+    {PC_8,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},
+    {PC_8_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)},
+    {PC_9,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},
+    {PC_9_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)},
+    {PD_12,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},
+    {PD_13,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},
+    {PD_14,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},
+    {PD_15,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},
+    {PE_5,       PWM_9,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)},
+    {PE_6,       PWM_9,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)},
+    {PE_8,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},
+    {PE_9,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},
+    {PE_10,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},
+    {PE_11,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},
+    {PE_12,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},
+    {PE_13,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},
+    {PE_14,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},
+//  {PF_3,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)},
+//  {PF_4,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},
+//  {PF_5,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},
+    {PF_6,       PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)},
+    {PF_7,       PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)},
+    {PF_8,       PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)},
+    {PF_9,       PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)},
+//  {PF_10,      PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},
+    {NC,         NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_0,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_2,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_9,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_12,      UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)},
+    {PA_11,      UART_6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PA_15,      UART_7,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PA_15_ALT0, UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,       UART_7,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PB_6,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6_ALT0,  UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+    {PB_9,       UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+    {PB_10,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_13,      UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+    {PC_6,       UART_6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PC_10,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_12,      UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PD_1,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)},
+    {PD_5,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_8,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX
+    {PD_10,      UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PD_15,      UART_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)},
+    {PE_1,       UART_8,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+    {PE_3,       UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)},
+    {PE_8,       UART_7,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PG_1,       UART_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)},
+    {PG_12,      UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)},
+    {PF_7,       UART_7,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PF_9,       UART_8,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+    {PG_14,      UART_6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {NC,         NC,      0} 
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_1,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_3,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_8,       UART_7,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PA_10,      UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_11,      UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)},
+    {PA_12,      UART_6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PB_3,       UART_7,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PB_3_ALT0,  UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_5,       UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+    {PB_7,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LED2
+    {PB_8,       UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+    {PB_11,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_12,      UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+    {PC_5,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_7,       UART_6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PC_11,      UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PC_11_ALT0, UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_0,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)},
+    {PD_2,       UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PD_6,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_9,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX
+    {PD_14,      UART_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)},
+    {PE_0,       UART_8,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+    {PE_2,       UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)},
+    {PE_7,       UART_7,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PF_6,       UART_7,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+    {PF_8,       UART_8,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+    {PG_0,       UART_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)},
+    {PG_9,       UART_6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PG_11,      UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)},
+    {NC,         NC,      0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED3
+    {PD_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PG_8,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)},
+    {PD_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_1,       SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PA_7,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_10,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PA_10_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {PB_5,       SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_5_ALT0,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_8,       SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {PB_15,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_3,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_12,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PD_6,       SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
+    {PE_6,       SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_6_ALT0,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {PE_14,      SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_14_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {NC,         NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_11,      SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+    {PA_12,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PA_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {PB_4,       SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_4_ALT0,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_14,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Connected to LED3
+    {PC_2,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_11,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PE_5,       SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_5_ALT0,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {PE_13,      SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_13_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {NC,         NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_9,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_0,       SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, // Connected to LED1
+    {PB_3,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_10,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)},
+    {PB_13,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+    {PC_7,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_10,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PD_3,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PE_2,       SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_2_ALT0,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {PE_12,      SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {NC,         NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_4_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_11,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PA_15,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_15_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_1,       SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {PB_9,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+    {PE_4,       SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_4_ALT0,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {PE_11,      SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {PE_11_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+    {NC,         NC,    0}
+};
+
+//*** CAN ***
+
+const PinMap PinMap_CAN_RD[] = {
+    {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_8,  CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)},
+    {PB_5,  CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+    {PB_3,  CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)},
+    {PB_8,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
+    {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+    {PD_0,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PG_0,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_15, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)},
+    {PB_4,  CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)},
+    {PB_6,  CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+    {PB_9,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
+    {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+    {PD_1,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PG_1,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+    {NC,    NC,    0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,261 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ALT0        = 0x100,
+    ALT1        = 0x200,
+    ALT2        = 0x300,
+    ALT3        = 0x400
+} ALTx;
+
+typedef enum {
+    PA_0        = 0x00,
+    PA_1        = 0x01,
+    PA_2        = 0x02,
+    PA_2_ALT0   = PA_2|ALT0,
+    PA_3        = 0x03,
+    PA_4        = 0x04,
+    PA_4_ALT0   = PA_4|ALT0,
+    PA_5        = 0x05,
+    PA_5_ALT0   = PA_5|ALT0,
+    PA_6        = 0x06,
+    PA_6_ALT0   = PA_6|ALT0,
+    PA_7        = 0x07,
+    PA_7_ALT0   = PA_7|ALT0,
+    PA_7_ALT1   = PA_7|ALT1,
+    PA_7_ALT2   = PA_7|ALT2,
+    PA_8        = 0x08,
+    PA_9        = 0x09,
+    PA_10       = 0x0A,
+    PA_10_ALT0  = PA_10|ALT0,
+    PA_11       = 0x0B,
+    PA_12       = 0x0C,
+    PA_12_ALT0  = PA_12|ALT0,
+    PA_13       = 0x0D,
+    PA_14       = 0x0E,
+    PA_15       = 0x0F,
+    PA_15_ALT0  = PA_15|ALT0,
+
+    PB_0        = 0x10,
+    PB_0_ALT0   = PB_0|ALT0,
+    PB_0_ALT1   = PB_0|ALT1,
+    PB_1        = 0x11,
+    PB_1_ALT0   = PB_1|ALT0,
+    PB_1_ALT1   = PB_1|ALT1,
+    PB_2        = 0x12,
+    PB_3        = 0x13,
+    PB_3_ALT0   = PB_3|ALT0,
+    PB_4        = 0x14,
+    PB_4_ALT0   = PA_4|ALT0,
+    PB_5        = 0x15,
+    PB_5_ALT0   = PB_5|ALT0,
+    PB_6        = 0x16,
+    PB_6_ALT0   = PB_6|ALT0,
+    PB_7        = 0x17,
+    PB_8        = 0x18,
+    PB_8_ALT0   = PB_8|ALT0,
+    PB_9        = 0x19,
+    PB_9_ALT0   = PB_9|ALT0,
+    PB_10       = 0x1A,
+    PB_10_ALT0   = PB_10|ALT0,
+    PB_11       = 0x1B,
+    PB_12       = 0x1C,
+    PB_12_ALT0  = PB_12|ALT0,
+    PB_13       = 0x1D,
+    PB_13_ALT0  = PB_13|ALT0,
+    PB_14       = 0x1E,
+    PB_14_ALT0  = PB_14|ALT0,
+    PB_14_ALT1  = PB_14|ALT1,
+    PB_15       = 0x1F,
+    PB_15_ALT0  = PB_15|ALT0,
+    PB_15_ALT1  = PB_15|ALT1,
+
+    PC_0        = 0x20,
+    PC_1        = 0x21,
+    PC_2        = 0x22,
+    PC_3        = 0x23,
+    PC_4        = 0x24,
+    PC_5        = 0x25,
+    PC_6        = 0x26,
+    PC_6_ALT0   = PC_6|ALT0,
+    PC_7        = 0x27,
+    PC_7_ALT0   = PC_7|ALT0,
+    PC_8        = 0x28,
+    PC_8_ALT0   = PC_8|ALT0,
+    PC_9        = 0x29,
+    PC_9_ALT0   = PC_9|ALT0,
+    PC_10       = 0x2A,
+    PC_11       = 0x2B,
+    PC_11_ALT0  = PC_11|ALT0,
+    PC_12       = 0x2C,
+    PC_13       = 0x2D,
+    PC_14       = 0x2E,
+    PC_15       = 0x2F,
+
+    PD_0        = 0x30,
+    PD_1        = 0x31,
+    PD_2        = 0x32,
+    PD_3        = 0x33,
+    PD_4        = 0x34,
+    PD_5        = 0x35,
+    PD_6        = 0x36,
+    PD_7        = 0x37,
+    PD_8        = 0x38,
+    PD_9        = 0x39,
+    PD_10       = 0x3A,
+    PD_11       = 0x3B,
+    PD_12       = 0x3C,
+    PD_13       = 0x3D,
+    PD_14       = 0x3E,
+    PD_15       = 0x3F,
+
+    PE_0        = 0x40,
+    PE_1        = 0x41,
+    PE_2        = 0x42,
+    PE_2_ALT0   = PE_2|ALT0,
+    PE_3        = 0x43,
+    PE_4        = 0x44,
+    PE_4_ALT0   = PE_4|ALT0,
+    PE_5        = 0x45,
+    PE_5_ALT0   = PE_5|ALT0,
+    PE_6        = 0x46,
+    PE_6_ALT0   = PE_6|ALT0,
+    PE_7        = 0x47,
+    PE_8        = 0x48,
+    PE_9        = 0x49,
+    PE_10       = 0x4A,
+    PE_11       = 0x4B,
+    PE_11_ALT0  = PE_11|ALT0,
+    PE_12       = 0x4C,
+    PE_12_ALT0  = PE_12|ALT0,
+    PE_13       = 0x4D,
+    PE_13_ALT0  = PE_13|ALT0,
+    PE_14       = 0x4E,
+    PE_14_ALT0  = PE_14|ALT0,
+    PE_15       = 0x4F,
+
+    PF_0        = 0x50,
+    PF_1        = 0x51,
+    PF_2        = 0x52,
+    PF_3        = 0x53,
+    PF_4        = 0x54,
+    PF_5        = 0x55,
+    PF_6        = 0x56,
+    PF_7        = 0x57,
+    PF_8        = 0x58,
+    PF_9        = 0x59,
+    PF_10       = 0x5A,
+    PF_11       = 0x5B,
+    PF_12       = 0x5C,
+    PF_13       = 0x5D,
+    PF_14       = 0x5E,
+    PF_15       = 0x5F,
+
+    PG_0        = 0x60,
+    PG_1        = 0x61,
+    PG_2        = 0x62,
+    PG_3        = 0x63,
+    PG_4        = 0x64,
+    PG_5        = 0x65,
+    PG_6        = 0x66,
+    PG_7        = 0x67,
+    PG_8        = 0x68,
+    PG_9        = 0x69,
+    PG_10       = 0x6A,
+    PG_11       = 0x6B,
+    PG_12       = 0x6C,
+    PG_13       = 0x6D,
+    PG_14       = 0x6E,
+    PG_15       = 0x6F,
+
+    PH_0        = 0x70,
+    PH_1        = 0x71,
+
+    // ADC internal channels
+    ADC_TEMP    = 0xF0,
+    ADC_VREF    = 0xF1,
+    ADC_VBAT    = 0xF2,
+
+    // Arduino connector namings
+    A0          = PA_3,
+    A1          = PC_0,
+    A2          = PC_3,
+    A3          = PC_1,
+    A4          = PC_4,
+    A5          = PC_5,
+    D0          = PG_9,
+    D1          = PG_14,
+    D2          = PF_15,
+    D3          = PE_13,
+    D4          = PF_14,
+    D5          = PE_11,
+    D6          = PE_9,
+    D7          = PF_13,
+    D8          = PF_12,
+    D9          = PD_15,
+    D10         = PD_14,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PB_0,  // Green
+    LED2        = PB_7,  // Blue
+    LED3        = PB_14, // Red
+    LED4        = LED1,
+    LED_RED     = LED3,
+    USER_BUTTON = PC_13,
+    // Standardized button names
+    BUTTON1 = USER_BUTTON,
+    SERIAL_TX   = PD_8,
+    SERIAL_RX   = PD_9,
+    USBTX       = SERIAL_TX,
+    USBRX       = SERIAL_RX,
+    I2C_SCL     = D15,
+    I2C_SDA     = D14,
+    SPI_MOSI    = D11,
+    SPI_MISO    = D12,
+    SPI_SCK     = D13,
+    SPI_CS      = D10,
+    PWM_OUT     = D9,
+
+    //USB pins
+    USB_OTG_FS_SOF = PA_8,
+    USB_OTG_FS_VBUS = PA_9,
+    USB_OTG_FS_ID = PA_10,
+    USB_OTG_FS_DM = PA_11,
+    USB_OTG_FS_DP = PA_12,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,269 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 100
+  * AHBCLK (MHz)        | 100
+  * APB1CLK (MHz)       |  50
+  * APB2CLK (MHz)       | 100
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_assert.h"
+
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x24003010;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO2 pin(PC9) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+    /* Enable Power Control clock */
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+
+    RCC_OscInitStruct.PLL.PLLM            = 8;             // VCO input clock = 1 MHz (8 MHz / 8)
+    RCC_OscInitStruct.PLL.PLLN            = 200;           // VCO output clock = 200 MHz (1 MHz * 200)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 7;
+    RCC_OscInitStruct.PLL.PLLR            = 2;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLLSAI output as USB clock source */
+    PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
+    PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+    PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+    /* Enable Power Control clock */
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLM            = 8;             // VCO input clock = 2 MHz (16 MHz / 8)
+    RCC_OscInitStruct.PLL.PLLN            = 100;           // VCO output clock = 200 MHz (2 MHz * 100)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 2;
+    RCC_OscInitStruct.PLL.PLLR            = 2;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLLI2S output as USB clock source */
+    PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
+    PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+    PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/battery_charger_i2c.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "battery_charger_i2c.h"
+
+BatteryChargerI2c::BatteryChargerI2c(PinName sda, PinName scl):_i2c(), _hz(100000)
+{
+    i2c_init(&_i2c, sda, scl);
+}
+
+bool BatteryChargerI2c::read_from_i2c(int i2c_address, char* data_read, int length)
+{
+    int bytes_read = i2c_read(&_i2c, i2c_address, data_read, length, 1);
+    return (length == bytes_read);
+}
+
+bool BatteryChargerI2c::write_to_i2c(int i2c_address, const char* data_write, int length)
+{
+    int bytes_written = i2c_write(&_i2c, i2c_address, data_write, length, 1);
+    return (length == bytes_written);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/battery_charger_i2c.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef BATTERY_CHARGER_I2C
+#define BATTERY_CHARGER_I2C
+
+#include "hal/i2c_api.h"
+
+#ifdef __cplusplus
+extern"C"{
+#endif
+
+class BatteryChargerI2c{
+
+public:
+    BatteryChargerI2c(PinName sda, PinName scl);
+    bool read_from_i2c(int i2c_address, char *data_read, int length);
+    bool write_to_i2c(int i2c_address, const char *data_write, int length);
+    virtual ~BatteryChargerI2c() {}
+
+private:
+    i2c_t _i2c;
+    int   _hz;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //BATTERY_CHARGER_I2C

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.cpp	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "min_battery_voltage.h"
+#include "battery_charger_i2c.h"
+
+/** Defining HAL_MspInit strong function
+ * in user defined file as described in documentation
+ */
+
+void HAL_MspInit(void)
+{
+	set_minimum_battery_voltage();
+}
+
+void set_minimum_battery_voltage()
+{
+    char data_write[2] = {0};
+    char data_read;
+    BatteryChargerI2c i2c_object(I2C_SDA_B, I2C_SCL_B);
+
+    if (i2c_object.write_to_i2c(BQ24295_I2C_ADDRESS,&data_write[0] , 1)){
+        i2c_object.read_from_i2c(BQ24295_I2C_ADDRESS, &data_read, 1);
+        data_read = data_read & MIN_BATTERY_VOLTAGE_MASK;
+        data_write[0] = 0x0;
+        data_write[1] = data_read;
+        if (i2c_object.write_to_i2c(BQ24295_I2C_ADDRESS,&data_write[0] , 2)){
+            //Battery Voltage is set to 3880mV
+            }
+        }
+    else{
+        // Minimum battery voltage could not be set.  This is not a critical error, no need to stop execution
+        // It simply means that longer cabling or USB ports with lower output voltages may cause problems.
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,37 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MIN_BATTERY_VOLTAGE_H
+#define MIN_BATTERY_VOLTAGE_H
+
+#ifdef __cplusplus
+extern"C"{
+#endif
+
+#define BQ24295_I2C_ADDRESS (0x6B << 1)
+#define MIN_BATTERY_VOLTAGE_MASK (0x87)
+
+/** Initializes an instance of class BatteryChargerI2c which is using the STM HAL I2C APIs
+ *  This allows longer USB cables or USB ports with lower output voltages to power the board correctly.
+ */
+
+void set_minimum_battery_voltage(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	// MIN_BATTERY_VOLTAGE_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,237 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+ 
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00, PA_1  = 0x01, PA_2  = 0x02, PA_3  = 0x03,
+    PA_4  = 0x04, PA_5  = 0x05, PA_6  = 0x06, PA_7  = 0x07,
+    PA_8  = 0x08, PA_9  = 0x09, PA_10 = 0x0A, PA_11 = 0x0B,
+    PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F,
+
+    PB_0  = 0x10, PB_1  = 0x11, PB_2  = 0x12, PB_3  = 0x13,
+    PB_4  = 0x14, PB_5  = 0x15, PB_6  = 0x16, PB_7  = 0x17,
+    PB_8  = 0x18, PB_9  = 0x19, PB_10 = 0x1A, PB_11 = 0x1B,
+    PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F,
+
+    PC_0  = 0x20, PC_1  = 0x21, PC_2  = 0x22, PC_3  = 0x23,
+    PC_4  = 0x24, PC_5  = 0x25, PC_6  = 0x26, PC_7  = 0x27,
+    PC_8  = 0x28, PC_9  = 0x29, PC_10 = 0x2A, PC_11 = 0x2B,
+    PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F,
+
+    PD_0  = 0x30, PD_1  = 0x31, PD_2  = 0x32, PD_3  = 0x33,
+    PD_4  = 0x34, PD_5  = 0x35, PD_6  = 0x36, PD_7  = 0x37,
+    PD_8  = 0x38, PD_9  = 0x39, PD_10 = 0x3A, PD_11 = 0x3B,
+    PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F,
+
+    PE_0  = 0x40, PE_1  = 0x41, PE_2  = 0x42, PE_3  = 0x43,
+    PE_4  = 0x44, PE_5  = 0x45, PE_6  = 0x46, PE_7  = 0x47,
+    PE_8  = 0x48, PE_9  = 0x49, PE_10 = 0x4A, PE_11 = 0x4B,
+    PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F,
+
+    PF_0  = 0x50, PF_1  = 0x51, PF_2  = 0x52, PF_3  = 0x53,
+    PF_4  = 0x54, PF_5  = 0x55, PF_6  = 0x56, PF_7  = 0x57,
+    PF_8  = 0x58, PF_9  = 0x59, PF_10 = 0x5A, PF_11 = 0x5B,
+    PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F,
+
+    PG_0  = 0x60, PG_1  = 0x61, PG_2  = 0x62, PG_3  = 0x63,
+    PG_4  = 0x64, PG_5  = 0x65, PG_6  = 0x66, PG_7  = 0x67,
+    PG_8  = 0x68, PG_9  = 0x69, PG_10 = 0x6A, PG_11 = 0x6B,
+    PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F,
+
+    PH_0  = 0x70, PH_1  = 0x71, PH_2  = 0x72, PH_3  = 0x73,
+    PH_4  = 0x74, PH_5  = 0x75, PH_6  = 0x76, PH_7  = 0x77,
+    PH_8  = 0x78, PH_9  = 0x79, PH_10 = 0x7A, PH_11 = 0x7B,
+    PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F,
+
+    // Not connected
+    NC    = (int)0xFFFFFFFF,
+
+    // Module Pins
+    // PortA
+    P_A1       = NC,
+    P_A2       = NC,
+    P_A3       = NC,
+    P_A4       = NC,
+    P_A5       = PC_2,   // UART-DTR
+    P_A6       = PF_2,   // Switch-0
+    P_A7       = PE_0,   // Red, Mode
+    P_A8       = PB_6,   // Green, Switch-1
+    P_A9       = PB_8,   // Blue
+    P_A10      = PA_11,  // UART-CTS
+    P_A11      = PA_9,   // UART-TXD
+    P_A12      = PA_12,  // UART-RTS
+    P_A13      = PA_10,  // UART-RXD
+    P_A14      = PD_9,   // GPIO-0
+    P_A15      = PD_8,   // GPIO-1
+    P_A16      = PD_11,  // GPIO-2
+    P_A17      = PD_12,  // GPIO-3
+    P_A18      = PA_3,   // UART-DSR
+    // PortB
+    P_B1       = NC,
+    P_B2       = NC,
+    P_B3       = NC,
+    P_B4       = NC,
+    P_B5       = NC,
+    P_B6       = NC,
+    P_B7       = NC,
+    P_B8       = NC,
+    // PortC
+    P_C1       = NC,
+    P_C2       = NC,
+    P_C3       = NC,
+    P_C4       = NC,
+    P_C5       = PG_4,   // SPI-IRQ
+    P_C6       = PE_13,  // SPI-MISO
+    P_C7       = NC,
+    P_C8       = PE_12,  // Res
+    P_C9       = NC,
+    P_C10      = PE_14,  // SPI-MOSI
+    P_C11      = PE_11,  // SPI-CS0
+    P_C12      = PE_9,   // Res
+    P_C13      = PF_6,   // GPIO-4
+    P_C14      = PC_1,   // RMII-MDC
+    P_C15      = PA_2,   // RMII-MDIO
+    P_C16      = PF_7,   // GPIO-7
+    P_C17      = PF_1,   // I2C-SCL
+    P_C18      = PF_0,   // I2C-SDA
+    // PortD
+    P_D1       = PB_12,  // RMII-TXD0
+    P_D2       = PB_13,  // RMII-TXD1
+    P_D3       = PB_11,  // RMII-TXEN
+    P_D4       = PA_7,   // RMII-CRSDV
+    P_D5       = PC_4,   // RMII-RXD0
+    P_D6       = PC_5,   // RMII-RXD1
+    P_D7       = NC,
+    P_D8       = PA_1,   // RMII-REFCLK
+    // TestPads
+    P_TP5      = PB_4,   // NTRST
+    P_TP7      = PA_13,  // TMS  SWDIO
+    P_TP8      = PA_15,  // TDI
+    P_TP9      = PA_14,  // TCK  SWCLK
+    P_TP10     = PB_3,   // TDO
+    //P_TP11,         // BOOT0
+
+    // Internal
+    LED1       = PD_9,
+    LED2       = PA_12,
+    LED3       = PD_8,
+    LED4       = PA_11,
+    LED5       = PC_2,
+    LED6       = PA_3,
+    LED7       = PF_6,
+    LED_RED    = PE_0,
+    LED_GREEN  = PB_6,
+    LED_BLUE   = PB_8,
+    SW1        = PF_2,
+    SW2        = PG_4,
+
+    // Standardized button names
+    BUTTON1    = SW1,
+    BUTTON2    = SW2,
+    
+    I2C_SDA    = PF_0,
+    I2C_SCL    = PF_1,
+    
+    SPI0_MOSI  = PE_14,
+    SPI0_MISO  = PE_13,
+    SPI0_SCK   = PE_12,
+    SPI0_CS    = PE_11,
+    SPI1_CS    = PE_9,
+ 
+    SPI_MOSI   = SPI0_MOSI,
+    SPI_MISO   = SPI0_MISO,
+    SPI_SCK    = SPI0_SCK,
+    SPI_CS     = SPI0_CS,
+
+    // DAPLink
+    USBRX      = MBED_CONF_TARGET_USB_RX,
+    USBTX      = MBED_CONF_TARGET_USB_TX,
+    SWDIO      = PA_15,
+    SWCLK      = PA_14,
+    NTRST      = PB_4,
+
+    // MTB Aliases
+    // Left  side (top view)
+    TGT_SWDIO      = SWDIO,
+    TGT_SWCLK      = SWCLK,
+    TGT_RESET      = NTRST,
+    TG_TX          = USBTX,
+    TG_RX          = USBRX,
+    TX1            = P_A15,
+    RX1            = P_A14,
+    SDA1           = P_C18,
+    SCL1           = P_C17,
+    MOSI1          = P_C10,
+    MISO1          = P_C6,
+    SCK1           = SPI_SCK,
+    GP0            = BUTTON1,
+    GP1            = SPI_CS,
+    AIN0           = P_C13,
+    AIN1           = P_A18,
+    AIN2           = P_A5,
+
+    //Right side (top view)
+    GND            = NC,
+    GP10           = NC,
+    RTS            = NC,
+    CTS            = NC,
+    GP7            = P_C12,
+    GP6            = P_A12,
+    GP5            = P_A10,
+    GP4            = P_A17,
+    TX2            = NC,
+    RX2            = NC,
+    SDA2           = NC,
+    SCL2           = NC,
+    MOSI2          = NC,
+    MISO2          = NC,
+    SCK2           = NC,
+    GP3            = P_A16,
+    GP2            = P_C5,
+    PWM2           = LED_GREEN,
+    PWM1           = LED_BLUE,
+    PWM0           = LED_RED,
+   
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,45 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2017, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : HAL
+ * File        : hal_overrides.c
+ *
+ * Description : Placeholder for HAL overrides.
+ *-------------------------------------------------------------------------*/
+
+#include "stm32f4xx_hal.h"
+#include "stm32f4xx_hal_rcc.h"
+#include "stm32f4xx_hal_gpio.h"
+
+void HAL_MspInit(void)
+{
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    
+    GPIO_InitTypeDef GPIO_InitDef;
+
+    GPIO_InitDef.Pin = GPIO_PIN_6 | GPIO_PIN_8;
+    GPIO_InitDef.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitDef.Pull = GPIO_NOPULL;
+    GPIO_InitDef.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitDef);
+    
+    GPIO_InitDef.Pin = GPIO_PIN_0;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitDef);
+    
+    HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(GPIOB, GPIO_PIN_8, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, GPIO_PIN_SET);
+}

Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar has changed

Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a has changed

Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a has changed

--- a/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,227 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "mbed_wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-    uint32_t function = (uint32_t)NC;
-
-#if defined(ADC1)
-    static int adc1_inited = 0;
-#endif
-#if defined(ADC2)
-    static int adc2_inited = 0;
-#endif
-#if defined(ADC3)
-    static int adc3_inited = 0;
-#endif
-    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
-    //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be between 0xF0 and 0xFF
-    if ((pin < 0xF0) || (pin >= 0x100)) {
-        // Normal channels
-        // Get the peripheral name from the pin and assign it to the object
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
-        // Get the functions (adc channel) from the pin and assign it to the object
-        function = pinmap_function(pin, PinMap_ADC);
-        // Configure GPIO
-        pinmap_pinout(pin, PinMap_ADC);
-    } else {
-        // Internal channels
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
-        function = pinmap_function(pin, PinMap_ADC_Internal);
-        // No GPIO configuration for internal channels
-    }
-    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-    MBED_ASSERT(function != (uint32_t)NC);
-
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // Check if ADC is already initialized
-    // Enable ADC clock
-#if defined(ADC1)
-    if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_1) {
-        __HAL_RCC_ADC1_CLK_ENABLE();
-        adc1_inited = 1;
-    }
-#endif
-#if defined(ADC2)
-    if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_2) {
-        __HAL_RCC_ADC2_CLK_ENABLE();
-        adc2_inited = 1;
-    }
-#endif
-#if defined(ADC3)
-    if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_3) {
-        __HAL_RCC_ADC3_CLK_ENABLE();
-        adc3_inited = 1;
-    }
-#endif
-    // Configure ADC
-    obj->handle.State = HAL_ADC_STATE_RESET;
-    obj->handle.Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV2;
-    obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
-    obj->handle.Init.ScanConvMode          = DISABLE;
-    obj->handle.Init.ContinuousConvMode    = DISABLE;
-    obj->handle.Init.DiscontinuousConvMode = DISABLE;
-    obj->handle.Init.NbrOfDiscConversion   = 0;
-    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
-    obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIGCONV_T1_CC1;
-    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-    obj->handle.Init.NbrOfConversion       = 1;
-    obj->handle.Init.DMAContinuousRequests = DISABLE;
-    obj->handle.Init.EOCSelection          = DISABLE;
-
-    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
-        error("Cannot initialize ADC\n");
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj)
-{
-    ADC_ChannelConfTypeDef sConfig = {0};
-
-    // Configure ADC channel
-    sConfig.Rank         = 1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES;
-    sConfig.Offset       = 0;
-
-    switch (obj->channel) {
-        case 0:
-            sConfig.Channel = ADC_CHANNEL_0;
-            break;
-        case 1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case 2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case 3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case 4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case 5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case 6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case 7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case 8:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case 9:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case 10:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case 11:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case 12:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case 13:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case 14:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case 15:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-        case 16:
-            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
-            break;
-        case 17:
-            sConfig.Channel = ADC_CHANNEL_VREFINT;
-            /*  From experiment, measurement needs max sampling time to be valid */
-            sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
-            break;
-        case 18:
-            sConfig.Channel = ADC_CHANNEL_VBAT;
-            /*  From experiment, measurement needs max sampling time to be valid */
-            sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
-            break;
-        default:
-            return 0;
-    }
-
-    // Measuring VBAT sets the ADC_CCR_VBATE bit in ADC->CCR, and there is not
-    // possibility with the ST HAL driver to clear it. If it isn't cleared,
-    // VBAT remains connected to the ADC channel in preference to temperature,
-    // so VBAT readings are returned in place of temperature.
-    ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
-
-    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
-
-    HAL_ADC_Start(&obj->handle); // Start conversion
-
-    // Wait end of conversion and get value
-    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
-        return (uint16_t)HAL_ADC_GetValue(&obj->handle);
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/analogin_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,197 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
+    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // Configure ADC object structures
+    obj->handle.State = HAL_ADC_STATE_RESET;
+    obj->handle.Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV2;
+    obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
+    obj->handle.Init.ScanConvMode          = DISABLE;
+    obj->handle.Init.ContinuousConvMode    = DISABLE;
+    obj->handle.Init.DiscontinuousConvMode = DISABLE;
+    obj->handle.Init.NbrOfDiscConversion   = 0;
+    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
+    obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIGCONV_T1_CC1;
+    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+    obj->handle.Init.NbrOfConversion       = 1;
+    obj->handle.Init.DMAContinuousRequests = DISABLE;
+    obj->handle.Init.EOCSelection          = DISABLE;
+
+#if defined(ADC1)
+    if ((ADCName)obj->handle.Instance == ADC_1) {
+        __HAL_RCC_ADC1_CLK_ENABLE();
+    }
+#endif
+#if defined(ADC2)
+    if ((ADCName)obj->handle.Instance == ADC_2) {
+        __HAL_RCC_ADC2_CLK_ENABLE();
+    }
+#endif
+#if defined(ADC3)
+    if ((ADCName)obj->handle.Instance == ADC_3) {
+        __HAL_RCC_ADC3_CLK_ENABLE();
+    }
+#endif
+
+    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+        error("Cannot initialize ADC");
+    }
+}
+
+uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    // Configure ADC channel
+    sConfig.Rank         = 1;
+    sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES;
+    sConfig.Offset       = 0;
+
+    switch (obj->channel) {
+        case 0:
+            sConfig.Channel = ADC_CHANNEL_0;
+            break;
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+            break;
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_VREFINT;
+            /*  From experiment, measurement needs max sampling time to be valid */
+            sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+            break;
+        case 18:
+            sConfig.Channel = ADC_CHANNEL_VBAT;
+            /*  From experiment, measurement needs max sampling time to be valid */
+            sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+            break;
+        default:
+            return 0;
+    }
+
+    // Measuring VBAT sets the ADC_CCR_VBATE bit in ADC->CCR, and there is not
+    // possibility with the ST HAL driver to clear it. If it isn't cleared,
+    // VBAT remains connected to the ADC channel in preference to temperature,
+    // so VBAT readings are returned in place of temperature.
+    ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
+
+    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+    HAL_ADC_Start(&obj->handle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+        return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+    } else {
+        return 0;
+    }
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32F4/can_device.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/can_device.h	Wed Jan 17 15:23:54 2018 +0000
@@ -25,7 +25,7 @@
 
 #ifdef DEVICE_CAN
 
-#if defined(CAN3_BASE) && defined(CAN_3)
+#if defined(CAN3_BASE)
 
 #define CAN_NUM 3 // Number of CAN peripherals present in the STM32 serie
 

--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h	Wed Jan 17 15:23:54 2018 +0000
@@ -129,9 +129,9 @@
 {
 	uint32_t newValue;
 	do {
-		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
+		newValue = (uint32_t)__LDREXW(ptr) | mask;
 
-	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+	} while (__STREXW(newValue, ptr));
 }
 
 
@@ -139,9 +139,9 @@
 {
 	uint32_t newValue;
 	do {
-		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
+		newValue = (uint32_t)__LDREXW(ptr) &~mask;
 
-	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+	} while (__STREXW(newValue, ptr));
 }
 
 #endif /* USE_RTOS */

--- a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,242 +28,27 @@
  *******************************************************************************
  */
 
-#include "mbed_assert.h"
-#include "serial_api.h"
-#include "serial_api_hal.h"
-
 #if DEVICE_SERIAL
 
-#include "cmsis.h"
-#include "pinmap.h"
-#include <string.h>
-#include "PeripheralPins.h"
-#include "mbed_error.h"
+#include "serial_api_hal.h"
 
-#define UART_NUM (10)
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+#if defined (TARGET_STM32F401xC) || defined (TARGET_STM32F401xE) || defined (TARGET_STM32F410xB) || defined (TARGET_STM32F411xE)
+    #define UART_NUM (3)
+#elif defined (TARGET_STM32F412xG)
+    #define UART_NUM (4)
+#elif defined (TARGET_STM32F407xG) || defined (TARGET_STM32F446xE)
+    #define UART_NUM (6)
+#elif defined (TARGET_STM32F429xI) || defined (TARGET_STM32F439xI) || defined (TARGET_STM32F437xG) || defined (TARGET_STM32F469xI)
+    #define UART_NUM (8)
+#else
+    #define UART_NUM (10) // max value // TARGET_STM32F413xH
+#endif
+
+uint32_t serial_irq_ids[UART_NUM] = {0};
 UART_HandleTypeDef uart_handlers[UART_NUM];
 
 static uart_irq_handler irq_handler;
 
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-  
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj_s->uart != (UARTName)NC);
-
-    // Enable USART clock
-    switch (obj_s->uart) {
-        case UART_1:
-            __HAL_RCC_USART1_FORCE_RESET();
-            __HAL_RCC_USART1_RELEASE_RESET();
-            __HAL_RCC_USART1_CLK_ENABLE();
-            obj_s->index = 0;
-            break;
-            
-        case UART_2:
-            __HAL_RCC_USART2_FORCE_RESET();
-            __HAL_RCC_USART2_RELEASE_RESET();
-            __HAL_RCC_USART2_CLK_ENABLE();
-            obj_s->index = 1;
-            break;
-#if defined(USART3_BASE)
-        case UART_3:
-            __HAL_RCC_USART3_FORCE_RESET();
-            __HAL_RCC_USART3_RELEASE_RESET();
-            __HAL_RCC_USART3_CLK_ENABLE();
-            obj_s->index = 2;
-            break;
-#endif
-#if defined(UART4_BASE)
-        case UART_4:
-            __HAL_RCC_UART4_FORCE_RESET();
-            __HAL_RCC_UART4_RELEASE_RESET();
-            __HAL_RCC_UART4_CLK_ENABLE();
-            obj_s->index = 3;
-            break;
-#endif
-#if defined(UART5_BASE)
-        case UART_5:
-            __HAL_RCC_UART5_FORCE_RESET();
-            __HAL_RCC_UART5_RELEASE_RESET();
-            __HAL_RCC_UART5_CLK_ENABLE();
-            obj_s->index = 4;
-            break;
-#endif
-#if defined(USART6_BASE)
-        case UART_6:
-            __HAL_RCC_USART6_FORCE_RESET();
-            __HAL_RCC_USART6_RELEASE_RESET();
-            __HAL_RCC_USART6_CLK_ENABLE();
-            obj_s->index = 5;
-            break;
-#endif
-#if defined(UART7_BASE)
-        case UART_7:
-            __HAL_RCC_UART7_FORCE_RESET();
-            __HAL_RCC_UART7_RELEASE_RESET();
-            __HAL_RCC_UART7_CLK_ENABLE();
-            obj_s->index = 6;
-            break;
-#endif
-#if defined(UART8_BASE)
-        case UART_8:
-            __HAL_RCC_UART8_FORCE_RESET();
-            __HAL_RCC_UART8_RELEASE_RESET();
-            __HAL_RCC_UART8_CLK_ENABLE();
-            obj_s->index = 7;
-            break;
-#endif
-#if defined(UART9_BASE)
-        case UART_9:
-            __HAL_RCC_UART9_FORCE_RESET();
-            __HAL_RCC_UART9_RELEASE_RESET();
-            __HAL_RCC_UART9_CLK_ENABLE();
-            obj_s->index = 8;
-            break;
-#endif
-#if defined(UART10_BASE)
-        case UART_10:
-            __HAL_RCC_UART10_FORCE_RESET();
-            __HAL_RCC_UART10_RELEASE_RESET();
-            __HAL_RCC_UART10_CLK_ENABLE();
-            obj_s->index = 9;
-            break;
-#endif
-    }
-
-    // Configure the UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj_s->baudrate = 9600;
-    obj_s->databits = UART_WORDLENGTH_8B;
-    obj_s->stopbits = UART_STOPBITS_1;
-    obj_s->parity   = UART_PARITY_NONE;
-    
-#if DEVICE_SERIAL_FC
-    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
-#endif
-
-    obj_s->pin_tx = tx;
-    obj_s->pin_rx = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj_s->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-    
-    // Reset UART and disable clock
-    switch (obj_s->index) {
-        case 0:
-            __HAL_RCC_USART1_FORCE_RESET();
-            __HAL_RCC_USART1_RELEASE_RESET();
-            __HAL_RCC_USART1_CLK_DISABLE();
-            break;
-        case 1:
-            __HAL_RCC_USART2_FORCE_RESET();
-            __HAL_RCC_USART2_RELEASE_RESET();
-            __HAL_RCC_USART2_CLK_DISABLE();
-            break;
-#if defined(USART3_BASE)
-        case 2:
-            __HAL_RCC_USART3_FORCE_RESET();
-            __HAL_RCC_USART3_RELEASE_RESET();
-            __HAL_RCC_USART3_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART4_BASE)
-        case 3:
-            __HAL_RCC_UART4_FORCE_RESET();
-            __HAL_RCC_UART4_RELEASE_RESET();
-            __HAL_RCC_UART4_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART5_BASE)
-        case 4:
-            __HAL_RCC_UART5_FORCE_RESET();
-            __HAL_RCC_UART5_RELEASE_RESET();
-            __HAL_RCC_UART5_CLK_DISABLE();
-            break;
-#endif
-#if defined(USART6_BASE)
-        case 5:
-            __HAL_RCC_USART6_FORCE_RESET();
-            __HAL_RCC_USART6_RELEASE_RESET();
-            __HAL_RCC_USART6_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART7_BASE)
-        case 6:
-            __HAL_RCC_UART7_FORCE_RESET();
-            __HAL_RCC_UART7_RELEASE_RESET();
-            __HAL_RCC_UART7_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART8_BASE)
-        case 7:
-            __HAL_RCC_UART8_FORCE_RESET();
-            __HAL_RCC_UART8_RELEASE_RESET();
-            __HAL_RCC_UART8_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART9_BASE)
-        case 8:
-            __HAL_RCC_UART9_FORCE_RESET();
-            __HAL_RCC_UART9_RELEASE_RESET();
-            __HAL_RCC_UART9_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART10_BASE)
-        case 9:
-            __HAL_RCC_UART10_FORCE_RESET();
-            __HAL_RCC_UART10_RELEASE_RESET();
-            __HAL_RCC_UART10_CLK_DISABLE();
-            break;
-#endif
-    }
-    
-    // Configure GPIOs
-    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj_s->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-  
-    obj_s->baudrate = baudrate;
-    init_uart(obj);
-}
-
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
@@ -927,7 +712,7 @@
     }
 }
 
-#endif
+#endif /* DEVICE_SERIAL_ASYNCH */
 
 #if DEVICE_SERIAL_FC
 
@@ -986,6 +771,6 @@
     init_uart(obj);
 }
 
-#endif
+#endif /* DEVICE_SERIAL_FC */
 
-#endif
+#endif /* DEVICE_SERIAL */

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h	Wed Jan 17 15:23:54 2018 +0000
@@ -94,7 +94,8 @@
 
 typedef enum {
     CAN_1 = (int)CAN1_BASE,
-    CAN_2 = (int)CAN2_BASE
+    CAN_2 = (int)CAN2_BASE,
+    CAN_3 = (int)CAN3_BASE
 } CANName;
 
 #ifdef __cplusplus

--- a/targets/TARGET_STM/TARGET_STM32F7/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,220 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "mbed_wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "mbed_error.h"
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-    uint32_t function = (uint32_t)NC;
-
-#if defined(ADC1)
-    static int adc1_inited = 0;
-#endif
-#if defined(ADC2)
-    static int adc2_inited = 0;
-#endif
-#if defined(ADC3)
-    static int adc3_inited = 0;
-#endif
-    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
-    //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be between 0xF0 and 0xFF
-    if ((pin < 0xF0) || (pin >= 0x100)) {
-        // Normal channels
-        // Get the peripheral name from the pin and assign it to the object
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
-        function = pinmap_function(pin, PinMap_ADC);
-        // Configure GPIO
-        pinmap_pinout(pin, PinMap_ADC);
-    } else {
-        // Internal channels
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
-        function = pinmap_function(pin, PinMap_ADC_Internal);
-        // No GPIO configuration for internal channels
-    }
-    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-    MBED_ASSERT(function != (uint32_t)NC);
-
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // Check if ADC is already initialized
-    // Enable ADC clock
-#if defined(ADC1)
-    if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_1) {
-        __HAL_RCC_ADC1_CLK_ENABLE();
-        adc1_inited = 1;
-    }
-#endif
-#if defined(ADC2)
-    if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_2) {
-        __HAL_RCC_ADC2_CLK_ENABLE();
-        adc2_inited = 1;
-    }
-#endif
-#if defined(ADC3)
-    if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return;
-    if ((ADCName)obj->handle.Instance == ADC_3) {
-        __HAL_RCC_ADC3_CLK_ENABLE();
-        adc3_inited = 1;
-    }
-#endif
-
-    // Configure ADC
-    obj->handle.State = HAL_ADC_STATE_RESET;
-    obj->handle.Init.ClockPrescaler        = ADC_CLOCKPRESCALER_PCLK_DIV4;
-    obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
-    obj->handle.Init.ScanConvMode          = DISABLE;
-    obj->handle.Init.ContinuousConvMode    = DISABLE;
-    obj->handle.Init.DiscontinuousConvMode = DISABLE;
-    obj->handle.Init.NbrOfDiscConversion   = 0;
-    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
-    obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIGCONV_T1_CC1;
-    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-    obj->handle.Init.NbrOfConversion       = 1;
-    obj->handle.Init.DMAContinuousRequests = DISABLE;
-    obj->handle.Init.EOCSelection          = DISABLE;
-
-    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
-        error("Cannot initialize ADC");
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj)
-{
-    ADC_ChannelConfTypeDef sConfig = {0};
-
-    // Configure ADC channel
-    sConfig.Rank         = 1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES;
-    sConfig.Offset       = 0;
-
-    switch (obj->channel) {
-        case 0:
-            sConfig.Channel = ADC_CHANNEL_0;
-            break;
-        case 1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case 2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case 3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case 4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case 5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case 6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case 7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case 8:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case 9:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case 10:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case 11:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case 12:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case 13:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case 14:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case 15:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-        case 16:
-            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
-            break;
-        case 17:
-            sConfig.Channel = ADC_CHANNEL_VREFINT;
-            break;
-        case 18:
-            sConfig.Channel = ADC_CHANNEL_VBAT;
-            break;
-        default:
-            return 0;
-    }
-
-    if (HAL_ADC_ConfigChannel(&obj->handle, &sConfig) != HAL_OK) {
-        error("Cannot configure ADC channel");
-    }
-
-    HAL_ADC_Start(&obj->handle); // Start conversion
-
-    // Wait end of conversion and get value
-    HAL_ADC_PollForConversion(&obj->handle, 10);
-    if (HAL_ADC_GetState(&obj->handle) & HAL_ADC_STATE_EOC_REG) {
-        return (HAL_ADC_GetValue(&obj->handle));
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/analogin_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,187 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
+    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // Configure ADC object structures
+    obj->handle.State = HAL_ADC_STATE_RESET;
+    obj->handle.Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4;
+    obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
+    obj->handle.Init.ScanConvMode          = DISABLE;
+    obj->handle.Init.ContinuousConvMode    = DISABLE;
+    obj->handle.Init.DiscontinuousConvMode = DISABLE;
+    obj->handle.Init.NbrOfDiscConversion   = 0;
+    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
+    obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIGCONV_T1_CC1;
+    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+    obj->handle.Init.NbrOfConversion       = 1;
+    obj->handle.Init.DMAContinuousRequests = DISABLE;
+    obj->handle.Init.EOCSelection          = DISABLE;
+
+#if defined(ADC1)
+    if ((ADCName)obj->handle.Instance == ADC_1) {
+        __HAL_RCC_ADC1_CLK_ENABLE();
+    }
+#endif
+#if defined(ADC2)
+    if ((ADCName)obj->handle.Instance == ADC_2) {
+        __HAL_RCC_ADC2_CLK_ENABLE();
+    }
+#endif
+#if defined(ADC3)
+    if ((ADCName)obj->handle.Instance == ADC_3) {
+        __HAL_RCC_ADC3_CLK_ENABLE();
+    }
+#endif
+
+    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+        error("Cannot initialize ADC");
+    }
+}
+
+uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    // Configure ADC channel
+    sConfig.Rank         = 1;
+    sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES;
+    sConfig.Offset       = 0;
+
+    switch (obj->channel) {
+        case 0:
+            sConfig.Channel = ADC_CHANNEL_0;
+            break;
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+            break;
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_VREFINT;
+            break;
+        case 18:
+            sConfig.Channel = ADC_CHANNEL_VBAT;
+            break;
+        default:
+            return 0;
+    }
+
+    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+    HAL_ADC_Start(&obj->handle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+        return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+    } else {
+        return 0;
+    }
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32F7/can_device.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/can_device.h	Wed Jan 17 15:23:54 2018 +0000
@@ -25,7 +25,7 @@
 
 #ifdef DEVICE_CAN
 
-#if defined(CAN3_BASE) && defined(CAN_3)
+#if defined(CAN3_BASE)
 
 #define CAN_NUM 3 // Number of CAN peripherals present in the STM32 serie
 

--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h	Wed Jan 17 15:23:54 2018 +0000
@@ -130,9 +130,9 @@
 {
 	uint32_t newValue;
 	do {
-		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
+		newValue = (uint32_t)__LDREXW(ptr) | mask;
 
-	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+	} while (__STREXW(newValue, ptr));
 }
 
 
@@ -140,9 +140,9 @@
 {
 	uint32_t newValue;
 	do {
-		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
+		newValue = (uint32_t)__LDREXW(ptr) &~mask;
 
-	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+	} while (__STREXW(newValue, ptr));
 }
 
 #if  defined ( __GNUC__ ) && !defined ( __CC_ARM )

--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c	Wed Jan 17 15:23:54 2018 +0000
@@ -717,6 +717,8 @@
     heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
     /* Set frame size */
     heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
+    /* Ensure rest of descriptor is written to RAM before the OWN bit */
+    __DMB();
     /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
     heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
     /* Point to next descriptor */
@@ -746,6 +748,8 @@
         heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
       }
       
+      /* Ensure rest of descriptor is written to RAM before the OWN bit */
+      __DMB();
       /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
       heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
       /* point to next descriptor */
@@ -753,6 +757,9 @@
     }
   }
   
+  /* Ensure all descriptors are written to RAM before checking transmitter status */
+  __DMB();
+
   /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
   if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
   {

--- a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,208 +27,17 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
-#include "mbed_assert.h"
-#include "serial_api.h"
-#include "serial_api_hal.h"
 
 #if DEVICE_SERIAL
 
-#include "cmsis.h"
-#include "pinmap.h"
-#include <string.h>
-#include "PeripheralPins.h"
-#include "mbed_error.h"
+#include "serial_api_hal.h"
 
 #define UART_NUM (8)
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+uint32_t serial_irq_ids[UART_NUM] = {0};
 UART_HandleTypeDef uart_handlers[UART_NUM];
 
 static uart_irq_handler irq_handler;
 
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-  
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj_s->uart != (UARTName)NC);
-
-    // Enable USART clock
-    switch (obj_s->uart) {
-        case UART_1:
-            __HAL_RCC_USART1_FORCE_RESET();
-            __HAL_RCC_USART1_RELEASE_RESET();
-            __HAL_RCC_USART1_CLK_ENABLE();
-            obj_s->index = 0;
-            break;
-            
-        case UART_2:
-            __HAL_RCC_USART2_FORCE_RESET();
-            __HAL_RCC_USART2_RELEASE_RESET();
-            __HAL_RCC_USART2_CLK_ENABLE();
-            obj_s->index = 1;
-            break;
-#if defined(USART3_BASE)
-        case UART_3:
-            __HAL_RCC_USART3_FORCE_RESET();
-            __HAL_RCC_USART3_RELEASE_RESET();
-            __HAL_RCC_USART3_CLK_ENABLE();
-            obj_s->index = 2;
-            break;
-#endif
-#if defined(UART4_BASE)
-        case UART_4:
-            __HAL_RCC_UART4_FORCE_RESET();
-            __HAL_RCC_UART4_RELEASE_RESET();
-            __HAL_RCC_UART4_CLK_ENABLE();
-            obj_s->index = 3;
-            break;
-#endif
-#if defined(UART5_BASE)
-        case UART_5:
-            __HAL_RCC_UART5_FORCE_RESET();
-            __HAL_RCC_UART5_RELEASE_RESET();
-            __HAL_RCC_UART5_CLK_ENABLE();
-            obj_s->index = 4;
-            break;
-#endif
-        case UART_6:
-            __HAL_RCC_USART6_FORCE_RESET();
-            __HAL_RCC_USART6_RELEASE_RESET();
-            __HAL_RCC_USART6_CLK_ENABLE();
-            obj_s->index = 5;
-            break;
-#if defined(UART7_BASE)
-        case UART_7:
-            __HAL_RCC_UART7_FORCE_RESET();
-            __HAL_RCC_UART7_RELEASE_RESET();
-            __HAL_RCC_UART7_CLK_ENABLE();
-            obj_s->index = 6;
-            break;
-#endif
-#if defined(UART8_BASE)
-        case UART_8:
-            __HAL_RCC_UART8_FORCE_RESET();
-            __HAL_RCC_UART8_RELEASE_RESET();
-            __HAL_RCC_UART8_CLK_ENABLE();
-            obj_s->index = 7;
-            break;
-#endif
-    }
-
-    // Configure the UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj_s->baudrate = 9600;
-    obj_s->databits = UART_WORDLENGTH_8B;
-    obj_s->stopbits = UART_STOPBITS_1;
-    obj_s->parity   = UART_PARITY_NONE;
-    
-#if DEVICE_SERIAL_FC
-    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
-#endif
-
-    obj_s->pin_tx = tx;
-    obj_s->pin_rx = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj_s->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-    
-    // Reset UART and disable clock
-    switch (obj_s->uart) {
-        case UART_1:
-            __USART1_FORCE_RESET();
-            __USART1_RELEASE_RESET();
-            __USART1_CLK_DISABLE();
-            break;
-        case UART_2:
-            __USART2_FORCE_RESET();
-            __USART2_RELEASE_RESET();
-            __USART2_CLK_DISABLE();
-            break;
-#if defined(USART3_BASE)
-        case UART_3:
-            __USART3_FORCE_RESET();
-            __USART3_RELEASE_RESET();
-            __USART3_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART4_BASE)
-        case UART_4:
-            __UART4_FORCE_RESET();
-            __UART4_RELEASE_RESET();
-            __UART4_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART5_BASE)
-        case UART_5:
-            __UART5_FORCE_RESET();
-            __UART5_RELEASE_RESET();
-            __UART5_CLK_DISABLE();
-            break;
-#endif
-        case UART_6:
-            __USART6_FORCE_RESET();
-            __USART6_RELEASE_RESET();
-            __USART6_CLK_DISABLE();
-            break;
-#if defined(UART7_BASE)
-        case UART_7:
-            __UART7_FORCE_RESET();
-            __UART7_RELEASE_RESET();
-            __UART7_CLK_DISABLE();
-            break;
-#endif
-#if defined(UART8_BASE)
-        case UART_8:
-            __UART8_FORCE_RESET();
-            __UART8_RELEASE_RESET();
-            __UART8_CLK_DISABLE();
-            break;
-#endif
-    }
-    
-    // Configure GPIOs
-    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj_s->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-  
-    obj_s->baudrate = baudrate;
-    init_uart(obj);
-}
-
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
@@ -854,7 +663,7 @@
     }
 }
 
-#endif
+#endif /* DEVICE_SERIAL_ASYNCH */
 
 #if DEVICE_SERIAL_FC
 
@@ -913,6 +722,6 @@
     init_uart(obj);
 }
 
-#endif
+#endif /* DEVICE_SERIAL_FC */
 
-#endif
+#endif /* DEVICE_SERIAL */

--- a/targets/TARGET_STM/TARGET_STM32L0/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,205 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "mbed_wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-int adc_inited = 0;
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-    uint32_t function = (uint32_t)NC;
-    obj->handle.Instance = (ADC_TypeDef *)NC;
-
-    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
-    //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be between 0xF0 and 0xFF
-    if ((pin < 0xF0) || (pin >= 0x100)) {
-        // Normal channels
-        // Get the peripheral name from the pin and assign it to the object
-        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
-        // Get the functions (adc channel) from the pin and assign it to the object
-        function = pinmap_function(pin, PinMap_ADC);
-        // Configure GPIO
-        pinmap_pinout(pin, PinMap_ADC);
-    } else {
-        // Internal channels
-        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
-        function = pinmap_function(pin, PinMap_ADC_Internal);
-        // No GPIO configuration for internal channels
-    }
-    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-    MBED_ASSERT(function != (uint32_t)NC);
-
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // The ADC initialization is done once
-    if (adc_inited == 0) {
-        adc_inited = 1;
-
-        obj->handle.State = HAL_ADC_STATE_RESET;
-        // Enable ADC clock
-        __ADC1_CLK_ENABLE();
-
-        // Configure ADC
-        obj->handle.Init.OversamplingMode      = DISABLE;
-        obj->handle.Init.ClockPrescaler        = ADC_CLOCKPRESCALER_PCLK_DIV1;
-        obj->handle.Init.Resolution            = ADC_RESOLUTION12b;
-        obj->handle.Init.SamplingTime          = ADC_SAMPLETIME_239CYCLES_5;
-        obj->handle.Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD;
-        obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-        obj->handle.Init.ContinuousConvMode    = DISABLE;
-        obj->handle.Init.DiscontinuousConvMode = DISABLE;
-        obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIG_EDGE_NONE;
-        obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIG0_T6_TRGO; // Not used here
-        obj->handle.Init.DMAContinuousRequests = DISABLE;
-        obj->handle.Init.EOCSelection          = EOC_SINGLE_CONV;
-        obj->handle.Init.Overrun               = OVR_DATA_OVERWRITTEN;
-        obj->handle.Init.LowPowerAutoWait      = ENABLE;
-        obj->handle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz
-        obj->handle.Init.LowPowerAutoPowerOff  = DISABLE;
-
-        if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
-            error("Cannot initialize ADC");
-        }
-
-        // Calibration
-        HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED);
-
-        __HAL_ADC_ENABLE(&obj->handle);
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj)
-{
-    ADC_ChannelConfTypeDef sConfig = {0};
-
-    // Configure ADC channel
-    sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
-    switch (obj->channel) {
-        case 0:
-            sConfig.Channel = ADC_CHANNEL_0;
-            break;
-        case 1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case 2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case 3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case 4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case 5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case 6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case 7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case 8:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case 9:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case 10:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case 11:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case 12:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case 13:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case 14:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case 15:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-#ifdef ADC_CHANNEL_VLCD
-        case 16:
-            sConfig.Channel = ADC_CHANNEL_VLCD;
-            break;
-#endif
-        case 17:
-            sConfig.Channel = ADC_CHANNEL_VREFINT;
-            break;
-        case 18:
-            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
-            break;
-        default:
-            return 0;
-    }
-
-    ADC1->CHSELR = 0; // [TODO] Workaround. To be removed after Cube driver is corrected.
-    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
-
-    HAL_ADC_Start(&obj->handle); // Start conversion
-
-    // Wait end of conversion and get value
-    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
-        return (HAL_ADC_GetValue(&obj->handle));
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/analogin_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,187 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include <stdbool.h>
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    static bool adc_calibrated = false;
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
+    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // Configure ADC object structures
+    obj->handle.State = HAL_ADC_STATE_RESET;
+    obj->handle.Init.OversamplingMode      = DISABLE;
+    obj->handle.Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV1;
+    obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
+    obj->handle.Init.SamplingTime          = ADC_SAMPLETIME_239CYCLES_5;
+    obj->handle.Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD;
+    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+    obj->handle.Init.ContinuousConvMode    = DISABLE;
+    obj->handle.Init.DiscontinuousConvMode = DISABLE;
+    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIG_EDGE_NONE;
+    obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIG0_T6_TRGO; // Not used here
+    obj->handle.Init.DMAContinuousRequests = DISABLE;
+    obj->handle.Init.EOCSelection          = EOC_SINGLE_CONV;
+    obj->handle.Init.Overrun               = OVR_DATA_OVERWRITTEN;
+    obj->handle.Init.LowPowerAutoWait      = ENABLE;
+    obj->handle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz
+    obj->handle.Init.LowPowerAutoPowerOff  = DISABLE;
+
+    __HAL_RCC_ADC1_CLK_ENABLE();
+
+    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+        error("Cannot initialize ADC");
+    }
+
+    // ADC calibration is done only once
+    if (!adc_calibrated) {
+        adc_calibrated = true;
+        HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED);
+    }
+
+    __HAL_ADC_ENABLE(&obj->handle);
+}
+
+uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    // Configure ADC channel
+    sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
+    switch (obj->channel) {
+        case 0:
+            sConfig.Channel = ADC_CHANNEL_0;
+            break;
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+#ifdef ADC_CHANNEL_VLCD
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_VLCD;
+            break;
+#endif
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_VREFINT;
+            break;
+        case 18:
+            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+            break;
+        default:
+            return 0;
+    }
+
+    ADC1->CHSELR = 0; // [TODO] Workaround. To be removed after Cube driver is corrected.
+    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+    HAL_ADC_Start(&obj->handle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+        return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+    } else {
+        return 0;
+    }
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,171 +27,24 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
-#include "mbed_assert.h"
-#include "serial_api.h"
-#include "serial_api_hal.h"
 
 #if DEVICE_SERIAL
 
-#include "cmsis.h"
-#include "pinmap.h"
-#include <string.h>
-#include "PeripheralPins.h"
-#include "mbed_error.h"
+#include "serial_api_hal.h"
 
-#define UART_NUM (5)
+#if defined (TARGET_STM32L011K4) || defined (TARGET_STM32L031K6)
+    #define UART_NUM (2)
+#elif defined (TARGET_STM32L053x8)
+    #define UART_NUM (3)
+#else
+    #define UART_NUM (5)
+#endif
 
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+uint32_t serial_irq_ids[UART_NUM] = {0};
 UART_HandleTypeDef uart_handlers[UART_NUM];
 
 static uart_irq_handler irq_handler;
 
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-    
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj_s->uart != (UARTName)NC);
-
-    // Enable UART clock
-#if defined(USART1_BASE)
-    if (obj_s->uart == UART_1) {
-        __HAL_RCC_USART1_FORCE_RESET();
-        __HAL_RCC_USART1_RELEASE_RESET();
-        __HAL_RCC_USART1_CLK_ENABLE();
-        obj_s->index = 0;
-    }
-#endif
-
-    if (obj_s->uart == UART_2) {
-        __HAL_RCC_USART2_FORCE_RESET();
-        __HAL_RCC_USART2_RELEASE_RESET();
-        __HAL_RCC_USART2_CLK_ENABLE();
-        obj_s->index = 1;
-    }
-
-    if (obj_s->uart == LPUART_1) {
-        __HAL_RCC_LPUART1_FORCE_RESET();
-        __HAL_RCC_LPUART1_RELEASE_RESET();
-        __HAL_RCC_LPUART1_CLK_ENABLE();
-        obj_s->index = 2;
-    }
-
-#if defined(USART4_BASE)
-    if (obj_s->uart == UART_4) {
-        __HAL_RCC_USART4_FORCE_RESET();
-        __HAL_RCC_USART4_RELEASE_RESET();
-        __HAL_RCC_USART4_CLK_ENABLE();
-        obj_s->index = 3;
-    }
-#endif
-
-#if defined(USART5_BASE)
-    if (obj_s->uart == UART_5) {
-        __HAL_RCC_USART5_FORCE_RESET();
-        __HAL_RCC_USART5_RELEASE_RESET();
-        __HAL_RCC_USART5_CLK_ENABLE();
-        obj_s->index = 4;
-    }
-#endif
-
-    // Configure the UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj_s->baudrate = 9600;
-    obj_s->databits = UART_WORDLENGTH_8B;
-    obj_s->stopbits = UART_STOPBITS_1;
-    obj_s->parity   = UART_PARITY_NONE;
-    
-#if DEVICE_SERIAL_FC
-    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
-#endif
-
-    obj_s->pin_tx = tx;
-    obj_s->pin_rx = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj_s->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-      
-    // Reset UART and disable clock
-#if defined(USART1_BASE)
-    if (obj_s->uart == UART_1) {
-        __HAL_RCC_USART1_FORCE_RESET();
-        __HAL_RCC_USART1_RELEASE_RESET();
-        __HAL_RCC_USART1_CLK_DISABLE();
-    }
-#endif
-
-    if (obj_s->uart == UART_2) {
-        __HAL_RCC_USART2_FORCE_RESET();
-        __HAL_RCC_USART2_RELEASE_RESET();
-        __HAL_RCC_USART2_CLK_DISABLE();
-    }
-
-    if (obj_s->uart == LPUART_1) {
-        __HAL_RCC_LPUART1_FORCE_RESET();
-        __HAL_RCC_LPUART1_RELEASE_RESET();
-        __HAL_RCC_LPUART1_CLK_DISABLE();
-    }
-
-#if defined(USART4_BASE)
-    if (obj_s->uart == UART_4) {
-        __HAL_RCC_USART4_FORCE_RESET();
-        __HAL_RCC_USART4_RELEASE_RESET();
-        __HAL_RCC_USART4_CLK_DISABLE();
-    }
-#endif
-
-#if defined(USART5_BASE)
-    if (obj_s->uart == UART_5) {
-        __HAL_RCC_USART5_FORCE_RESET();
-        __HAL_RCC_USART5_RELEASE_RESET();
-        __HAL_RCC_USART5_CLK_DISABLE();
-    }
-#endif
-
-    // Configure GPIOs
-    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj_s->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-
-    obj_s->baudrate = baudrate;
-    init_uart(obj);
-}
-
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
@@ -761,7 +614,7 @@
     }
 }
 
-#endif
+#endif /* DEVICE_SERIAL_ASYNCH */
 
 #if DEVICE_SERIAL_FC
 
@@ -820,6 +673,6 @@
     init_uart(obj);
 }
 
-#endif
+#endif /* DEVICE_SERIAL_FC */
 
-#endif
+#endif /* DEVICE_SERIAL */

--- a/targets/TARGET_STM/TARGET_STM32L1/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,254 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "mbed_wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-int adc_inited = 0;
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    uint32_t function = (uint32_t)NC;
-
-    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
-    //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be between 0xF0 and 0xFF
-    if ((pin < 0xF0) || (pin >= 0x100)) {
-        // Normal channels
-        // Get the peripheral name from the pin and assign it to the object
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
-        // Get the functions (adc channel) from the pin and assign it to the object
-        function = pinmap_function(pin, PinMap_ADC);
-        // Configure GPIO
-        pinmap_pinout(pin, PinMap_ADC);
-    } else {
-        // Internal channels
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
-        function = pinmap_function(pin, PinMap_ADC_Internal);
-        // No GPIO configuration for internal channels
-    }
-    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-    MBED_ASSERT(function != (uint32_t)NC);
-
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // The ADC initialization is done once
-    if (adc_inited == 0) {
-        adc_inited = 1;
-
-        // Enable the HSI (to clock the ADC)
-        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-        RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
-        RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
-        RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-        HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-        obj->handle.State = HAL_ADC_STATE_RESET;
-        // Enable ADC clock
-        __ADC1_CLK_ENABLE();
-
-        // Configure ADC
-        obj->handle.Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV4;
-        obj->handle.Init.Resolution            = ADC_RESOLUTION12b;
-        obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-        obj->handle.Init.ScanConvMode          = DISABLE;                       // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
-        obj->handle.Init.EOCSelection          = EOC_SINGLE_CONV;               // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
-        obj->handle.Init.LowPowerAutoWait      = ADC_AUTOWAIT_UNTIL_DATA_READ;  // Enable the dynamic low power Auto Delay: new conversion start only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
-        obj->handle.Init.LowPowerAutoPowerOff  = ADC_AUTOPOWEROFF_IDLE_PHASE;   // Enable the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
-        obj->handle.Init.ChannelsBank          = ADC_CHANNELS_BANK_A;
-        obj->handle.Init.ContinuousConvMode    = DISABLE;                       // Continuous mode disabled to have only 1 conversion at each conversion trig
-        obj->handle.Init.NbrOfConversion       = 1;                             // Parameter discarded because sequencer is disabled
-        obj->handle.Init.DiscontinuousConvMode = DISABLE;                       // Parameter discarded because sequencer is disabled
-        obj->handle.Init.NbrOfDiscConversion   = 1;                             // Parameter discarded because sequencer is disabled
-        obj->handle.Init.ExternalTrigConv      = 0;                             // Not used
-        obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
-        obj->handle.Init.DMAContinuousRequests = DISABLE;
-
-        if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
-            error("Cannot initialize ADC");
-        }
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj)
-{
-    ADC_ChannelConfTypeDef sConfig = {0};
-
-    // Configure ADC channel
-    switch (obj->channel) {
-        case 0:
-            sConfig.Channel = ADC_CHANNEL_0;
-            break;
-        case 1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case 2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case 3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case 4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case 5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case 6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case 7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case 8:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case 9:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case 10:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case 11:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case 12:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case 13:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case 14:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case 15:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-        case 16:
-            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
-            break;
-        case 17:
-            sConfig.Channel = ADC_CHANNEL_VREFINT;
-            break;
-        case 18:
-            sConfig.Channel = ADC_CHANNEL_18;
-            break;
-        case 19:
-            sConfig.Channel = ADC_CHANNEL_19;
-            break;
-        case 20:
-            sConfig.Channel = ADC_CHANNEL_20;
-            break;
-        case 21:
-            sConfig.Channel = ADC_CHANNEL_21;
-            break;
-        case 22:
-            sConfig.Channel = ADC_CHANNEL_22;
-            break;
-        case 23:
-            sConfig.Channel = ADC_CHANNEL_23;
-            break;
-        case 24:
-            sConfig.Channel = ADC_CHANNEL_24;
-            break;
-        case 25:
-            sConfig.Channel = ADC_CHANNEL_25;
-            break;
-        case 26:
-            sConfig.Channel = ADC_CHANNEL_26;
-            break;
-#ifdef ADC_CHANNEL_27
-        case 27:
-            sConfig.Channel = ADC_CHANNEL_27;
-            break;
-#endif
-#ifdef ADC_CHANNEL_28
-        case 28:
-            sConfig.Channel = ADC_CHANNEL_28;
-            break;
-#endif
-#ifdef ADC_CHANNEL_29
-        case 29:
-            sConfig.Channel = ADC_CHANNEL_29;
-            break;
-#endif
-#ifdef ADC_CHANNEL_30
-        case 30:
-            sConfig.Channel = ADC_CHANNEL_30;
-            break;
-#endif
-#ifdef ADC_CHANNEL_31
-        case 31:
-            sConfig.Channel = ADC_CHANNEL_31;
-            break;
-#endif
-        default:
-            return 0;
-    }
-
-    sConfig.Rank         = ADC_REGULAR_RANK_1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES;
-
-    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
-
-    HAL_ADC_Start(&obj->handle); // Start conversion
-
-    // Wait end of conversion and get value
-    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
-        return (HAL_ADC_GetValue(&obj->handle));
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/analogin_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,238 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include <stdbool.h>
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    static bool adc_hsi_inited = false;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
+    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // Configure ADC object structures
+    obj->handle.State = HAL_ADC_STATE_RESET;
+    obj->handle.Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV4;
+    obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
+    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+    obj->handle.Init.ScanConvMode          = DISABLE;                       // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
+    obj->handle.Init.EOCSelection          = EOC_SINGLE_CONV;               // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
+    obj->handle.Init.LowPowerAutoWait      = ADC_AUTOWAIT_UNTIL_DATA_READ;  // Enable the dynamic low power Auto Delay: new conversion start only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
+    obj->handle.Init.LowPowerAutoPowerOff  = ADC_AUTOPOWEROFF_IDLE_PHASE;   // Enable the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
+    obj->handle.Init.ChannelsBank          = ADC_CHANNELS_BANK_A;
+    obj->handle.Init.ContinuousConvMode    = DISABLE;                       // Continuous mode disabled to have only 1 conversion at each conversion trig
+    obj->handle.Init.NbrOfConversion       = 1;                             // Parameter discarded because sequencer is disabled
+    obj->handle.Init.DiscontinuousConvMode = DISABLE;                       // Parameter discarded because sequencer is disabled
+    obj->handle.Init.NbrOfDiscConversion   = 1;                             // Parameter discarded because sequencer is disabled
+    obj->handle.Init.ExternalTrigConv      = 0;                             // Not used
+    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
+    obj->handle.Init.DMAContinuousRequests = DISABLE;
+
+    __HAL_RCC_ADC1_CLK_ENABLE();
+
+    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+        error("Cannot initialize ADC");
+    }
+
+    // This section is done only once
+    if (!adc_hsi_inited) {
+        adc_hsi_inited = true;
+        // Enable the HSI (to clock the ADC)
+        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+        RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
+        RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
+        RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+        HAL_RCC_OscConfig(&RCC_OscInitStruct);
+    }
+}
+
+uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    // Configure ADC channel
+    switch (obj->channel) {
+        case 0:
+            sConfig.Channel = ADC_CHANNEL_0;
+            break;
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+            break;
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_VREFINT;
+            break;
+        case 18:
+            sConfig.Channel = ADC_CHANNEL_18;
+            break;
+        case 19:
+            sConfig.Channel = ADC_CHANNEL_19;
+            break;
+        case 20:
+            sConfig.Channel = ADC_CHANNEL_20;
+            break;
+        case 21:
+            sConfig.Channel = ADC_CHANNEL_21;
+            break;
+        case 22:
+            sConfig.Channel = ADC_CHANNEL_22;
+            break;
+        case 23:
+            sConfig.Channel = ADC_CHANNEL_23;
+            break;
+        case 24:
+            sConfig.Channel = ADC_CHANNEL_24;
+            break;
+        case 25:
+            sConfig.Channel = ADC_CHANNEL_25;
+            break;
+        case 26:
+            sConfig.Channel = ADC_CHANNEL_26;
+            break;
+#ifdef ADC_CHANNEL_27
+        case 27:
+            sConfig.Channel = ADC_CHANNEL_27;
+            break;
+#endif
+#ifdef ADC_CHANNEL_28
+        case 28:
+            sConfig.Channel = ADC_CHANNEL_28;
+            break;
+#endif
+#ifdef ADC_CHANNEL_29
+        case 29:
+            sConfig.Channel = ADC_CHANNEL_29;
+            break;
+#endif
+#ifdef ADC_CHANNEL_30
+        case 30:
+            sConfig.Channel = ADC_CHANNEL_30;
+            break;
+#endif
+#ifdef ADC_CHANNEL_31
+        case 31:
+            sConfig.Channel = ADC_CHANNEL_31;
+            break;
+#endif
+        default:
+            return 0;
+    }
+
+    sConfig.Rank         = ADC_REGULAR_RANK_1;
+    sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES;
+
+    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+    HAL_ADC_Start(&obj->handle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+        return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+    } else {
+        return 0;
+    }
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,160 +27,18 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
-#include "mbed_assert.h"
-#include "serial_api.h"
-#include "serial_api_hal.h"
 
 #if DEVICE_SERIAL
 
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include <string.h>
-#include "PeripheralPins.h"
+#include "serial_api_hal.h"
 
 #define UART_NUM (5)
 
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+uint32_t serial_irq_ids[UART_NUM] = {0};
 UART_HandleTypeDef uart_handlers[UART_NUM];
 
 static uart_irq_handler irq_handler;
 
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-    
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj_s->uart != (UARTName)NC);
-
-    // Enable USART clock
-    if (obj_s->uart == UART_1) {
-        __HAL_RCC_USART1_FORCE_RESET();
-        __HAL_RCC_USART1_RELEASE_RESET();
-        __HAL_RCC_USART1_CLK_ENABLE();
-        obj_s->index = 0;
-    }
-    if (obj_s->uart == UART_2) {
-        __HAL_RCC_USART2_FORCE_RESET();
-        __HAL_RCC_USART2_RELEASE_RESET();
-        __HAL_RCC_USART2_CLK_ENABLE();
-        obj_s->index = 1;
-    }
-    if (obj_s->uart == UART_3) {
-        __HAL_RCC_USART3_FORCE_RESET();
-        __HAL_RCC_USART3_RELEASE_RESET();
-        __HAL_RCC_USART3_CLK_ENABLE();
-        obj_s->index = 2;
-    }
-#if defined(UART4_BASE)
-    if (obj_s->uart == UART_4) {
-        __HAL_RCC_UART4_FORCE_RESET();
-        __HAL_RCC_UART4_RELEASE_RESET();
-        __HAL_RCC_UART4_CLK_ENABLE();
-        obj_s->index = 3;
-    }
-#endif
-#if defined(UART5_BASE)
-    if (obj_s->uart == UART_5) {
-        __HAL_RCC_UART5_FORCE_RESET();
-        __HAL_RCC_UART5_RELEASE_RESET();
-        __HAL_RCC_UART5_CLK_ENABLE();
-        obj_s->index = 4;
-    }
-#endif
-
-    // Configure UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj_s->baudrate = 9600;
-    obj_s->databits = UART_WORDLENGTH_8B;
-    obj_s->stopbits = UART_STOPBITS_1;
-    obj_s->parity   = UART_PARITY_NONE;
-    
-#if DEVICE_SERIAL_FC
-    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
-#endif
-
-    obj_s->pin_tx = tx;
-    obj_s->pin_rx = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj_s->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-      
-    // Reset UART and disable clock
-    if (obj_s->uart == UART_1) {
-        __USART1_FORCE_RESET();
-        __USART1_RELEASE_RESET();
-        __USART1_CLK_DISABLE();
-    }
-    if (obj_s->uart == UART_2) {
-        __USART2_FORCE_RESET();
-        __USART2_RELEASE_RESET();
-        __USART2_CLK_DISABLE();
-    }
-    if (obj_s->uart == UART_3) {
-        __USART3_FORCE_RESET();
-        __USART3_RELEASE_RESET();
-        __USART3_CLK_DISABLE();
-    }
-
-#if defined(UART4_BASE)
-    if (obj_s->uart == UART_4) {
-        __UART4_FORCE_RESET();
-        __UART4_RELEASE_RESET();
-        __UART4_CLK_DISABLE();
-    }
-#endif
-#if defined(UART5_BASE)
-    if (obj_s->uart == UART_5) {
-        __UART5_FORCE_RESET();
-        __UART5_RELEASE_RESET();
-        __UART5_CLK_DISABLE();
-    }
-#endif
-
-    // Configure GPIOs
-    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj_s->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-
-    obj_s->baudrate = baudrate;
-    init_uart(obj);
-}
-
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
@@ -752,7 +610,7 @@
     }
 }
 
-#endif
+#endif /* DEVICE_SERIAL_ASYNCH */
 
 #if DEVICE_SERIAL_FC
 
@@ -811,6 +669,6 @@
     init_uart(obj);
 }
 
-#endif
+#endif /* DEVICE_SERIAL_FC */
 
-#endif
+#endif /* DEVICE_SERIAL */

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c	Wed Jan 17 15:23:54 2018 +0000
@@ -110,7 +110,7 @@
 #ifdef VECT_TAB_SRAM
     SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 #else
-    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
 #endif
 
 }

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct	Wed Jan 17 15:23:54 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
 ; Scatter-Loading Description File
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ; Copyright (c) 2015, STMicroelectronics
@@ -27,10 +28,18 @@
 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x40000
+#endif
+
 ; 256KB FLASH (0x40000) + 64KB SRAM (0x10000)
-LR_IROM1 0x08000000 0x40000  {    ; load region size_region
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
 
-  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct	Wed Jan 17 15:23:54 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
 ; Scatter-Loading Description File
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ; Copyright (c) 2015, STMicroelectronics
@@ -27,10 +28,18 @@
 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x40000
+#endif
+
 ; 256KB FLASH (0x40000) + 64KB SRAM (0x10000)
-LR_IROM1 0x08000000 0x40000  {    ; load region size_region
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
 
-  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld	Wed Jan 17 15:23:54 2018 +0000
@@ -1,7 +1,15 @@
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 256k
+#endif
+
 /* Linker script to configure memory regions. */
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
   SRAM1 (rwx)  : ORIGIN = 0x20000188, LENGTH = 64k - 0x188
 }
 

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf	Wed Jan 17 15:23:54 2018 +0000
@@ -1,9 +1,12 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x40000; }
+
 /* [ROM = 256kb = 0x40000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x0803FFFF;
+define symbol __intvec_start__     = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
 
-/* [RAM = 48kb + 16kb = 0xC000] */
+/* [RAM = 48kb + 16kb = 0x10000] */
 /* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
 define symbol __NVIC_start__          = 0x20000000;
 define symbol __NVIC_end__            = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralNames.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,87 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_2
+#define STDIO_UART_RX  PA_3
+#define STDIO_UART     UART_2
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_6  = (int)TIM6_BASE,
+    PWM_7  = (int)TIM7_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralPins.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,264 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+// - All mapping tables are declared as weak to allow custom overwrites for similar MCU models.
+//
+//==============================================================================
+
+//*** ADC ***
+
+__weak const PinMap PinMap_ADC[] = {
+    {PA_0,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+    {PA_1,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+    {PA_2,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+    {PA_3,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+    {PA_4,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+    {PA_5,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+    {PA_6,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+    {PA_7,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+    {PB_0,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {PB_1,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
+    {PC_0,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+    {PC_1,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+    {PC_2,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+    {PC_3,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+    {PC_4,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+	{PC_5,		 ADC_1,	   STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+    {NC,         NC,       0}
+};
+
+__weak const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
+    {NC,   NC,    0}
+};
+
+//*** DAC ***
+
+__weak const PinMap PinMap_DAC[] = {
+    {PA_4,       DAC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
+    {PA_5,       DAC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2
+    {NC,         NC,       0}
+};
+
+//*** I2C ***
+
+__weak const PinMap PinMap_I2C_SDA[] = {
+    {PA_10,      I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_4,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PB_7,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_9,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_14,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_1,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,         NC,       0}
+};
+
+__weak const PinMap PinMap_I2C_SCL[] = {
+    {PA_7,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PA_9,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_6,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_8,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_13,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_0,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,         NC,       0}
+};
+
+
+//*** PWM ***
+
+__weak const PinMap PinMap_PWM[] = {
+    {PA_0,       PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+    {PA_1,       PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+    {PA_1_ALT0,  PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+    {PA_2,       PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+    {PA_2_ALT0,  PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+    {PA_3,       PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+    {PA_3_ALT0,  PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+    {PA_5,       PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+    {PA_6,       PWM_16,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+    {PA_7,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+    {PA_8,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+    {PA_9,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+    {PA_10,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+    {PA_11,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+    {PA_15,      PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+    {PB_0,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+    {PB_1,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+    {PB_3,       PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+    {PB_6,       PWM_16,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N
+    {PB_8,       PWM_16,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+    {PB_10,      PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+    {PB_11,      PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+    {PB_13,      PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+    {PB_13_ALT0, PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+    {PB_14,      PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+    {PB_14_ALT0, PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+    {PB_15,      PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+    {PB_15_ALT0, PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+    {NC,         NC,       0}
+};
+
+//*** SERIAL ***
+
+__weak const PinMap PinMap_UART_TX[] = {
+    {PA_2_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},// connected to STDIO_UART_TX
+    {PA_2,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // connected to STDIO_UART_TX
+    {PA_9,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_11,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_1,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_4,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_5, 		 UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_10,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC,         NC,       0}
+};
+
+__weak const PinMap PinMap_UART_RX[] = {
+    {PA_3_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},// connected to STDIO_UART_RX
+    {PA_3,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},   // connected to STDIO_UART_RX
+    {PA_10,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)},
+    {PB_7,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_11,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_0,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ 	{PC_5,		 UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_11,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC,         NC,       0}
+};
+
+__weak const PinMap PinMap_UART_RTS[] = {
+    {PA_1,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_12,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_1_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_1,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_3,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_12,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_14,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ 	{PD_2,		 UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC,         NC,       0}
+};
+
+__weak const PinMap PinMap_UART_CTS[] = {
+    {PA_0,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_6_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PA_6,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_11,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_13_ALT0, LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_13,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC,         NC,       0}
+};
+
+//*** SPI ***
+
+__weak const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_12,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5_ALT0,  SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_15,      SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_3,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_12,      SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,         NC,       0}
+};
+
+__weak const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_11,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4_ALT0,  SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_14,      SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_2,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_11,      SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,         NC,       0}
+};
+
+__weak const PinMap PinMap_SPI_SCLK[] = {
+    {PA_1,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_5,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3_ALT0,  SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_10,      SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13,      SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_10,      SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,         NC,       0}
+};
+
+__weak const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_4_ALT0,  SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_15,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_15_ALT0, SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_0,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_9,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12,      SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC,         NC,       0}
+};
+
+//*** CAN ***
+
+__weak const PinMap PinMap_CAN_RD[] = {
+    {PA_11,      CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PB_8,       CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,         NC,       0}
+};
+
+__weak const PinMap PinMap_CAN_TD[] = {
+    {PA_12,      CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PB_9,       CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,         NC,       0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,219 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+  ALT0 = 0x100,
+  ALT1 = 0x200,
+  ALT2 = 0x300,
+  ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+  PA_0  = 0x00,
+  PA_1  = 0x01,
+  PA_1_ALT0 = PA_1|ALT0,
+  PA_2  = 0x02,
+  PA_2_ALT0 = PA_2|ALT0,
+  PA_3  = 0x03,
+  PA_3_ALT0 = PA_3|ALT0,
+  PA_4  = 0x04,
+  PA_4_ALT0 = PA_4|ALT0,
+  PA_5  = 0x05,
+  PA_6  = 0x06,
+  PA_6_ALT0 = PA_6|ALT0,
+  PA_7  = 0x07,
+  PA_8  = 0x08,
+  PA_9  = 0x09,
+  PA_10 = 0x0A,
+  PA_11 = 0x0B,
+  PA_12 = 0x0C,
+  PA_13 = 0x0D,
+  PA_14 = 0x0E,
+  PA_15 = 0x0F,
+  PA_15_ALT0 = PA_15|ALT0,
+
+  PB_0  = 0x10,
+  PB_1  = 0x11,
+  PB_1_ALT0 = PB_1|ALT0,
+  PB_2  = 0x12,
+  PB_3  = 0x13,
+  PB_3_ALT0 = PB_3|ALT0,
+  PB_4  = 0x14,
+  PB_4_ALT0 = PB_4|ALT0,
+  PB_5  = 0x15,
+  PB_5_ALT0 = PB_5|ALT0,
+  PB_6  = 0x16,
+  PB_7  = 0x17,
+  PB_8  = 0x18,
+  PB_9  = 0x19,
+  PB_10 = 0x1A,
+  PB_11 = 0x1B,
+  PB_12 = 0x1C,
+  PB_13 = 0x1D,
+  PB_13_ALT0 = PB_13|ALT0,
+  PB_14 = 0x1E,
+  PB_14_ALT0 = PB_14|ALT0,
+  PB_15 = 0x1F,
+  PB_15_ALT0 = PB_15|ALT0,
+
+#ifndef STM32L433_48PINS // 48 pin versions don't have PC0-PC15 pins
+  PC_0  = 0x20,
+  PC_1  = 0x21,
+  PC_2  = 0x22,
+  PC_3  = 0x23,
+  PC_4  = 0x24,
+  PC_5  = 0x25,
+  PC_6  = 0x26,
+  PC_7  = 0x27,
+  PC_8  = 0x28,
+  PC_9  = 0x29,
+  PC_10 = 0x2A,
+  PC_11 = 0x2B,
+  PC_12 = 0x2C,
+#endif
+  PC_13 = 0x2D,
+  PC_14 = 0x2E,
+  PC_15 = 0x2F,
+
+    
+  PD_2  = 0x32,
+#ifdef STM32L433_100PINS // LQFP100 or UFBGA100 versions
+  PD_0  = 0x30,
+  PD_1  = 0x31,
+  PD_3  = 0x33,
+  PD_4  = 0x34,
+  PD_5  = 0x35,
+  PD_6  = 0x36,
+  PD_7  = 0x37,
+  PD_8  = 0x38,
+  PD_9  = 0x39,
+  PD_10 = 0x3A,
+  PD_11 = 0x3B,
+  PD_12 = 0x3C,
+  PD_13 = 0x3D,
+  PD_14 = 0x3E,
+  PD_15 = 0x3F,
+    
+  PE_0  = 0x40,
+  PE_1  = 0x41,
+  PE_2  = 0x42,
+  PE_3  = 0x43,
+  PE_4  = 0x44,
+  PE_5  = 0x45,
+  PE_6  = 0x46,
+  PE_7  = 0x47,
+  PE_8  = 0x48,
+  PE_9  = 0x49,
+  PE_10 = 0x4A,
+  PE_11 = 0x4B,
+  PE_12 = 0x4C,
+  PE_13 = 0x4D,
+  PE_14 = 0x4E,
+  PE_15 = 0x4F,
+#endif
+
+  PH_0  = 0x70,
+  PH_1  = 0x71,
+
+  PH_3  = 0x73,
+
+  // ADC internal channels
+  ADC_TEMP = 0xF0,
+  ADC_VREF = 0xF1,
+  ADC_VBAT = 0xF2,
+
+  // Arduino connector namings
+  A0          = PA_0,
+  A1          = PA_1,
+  A2          = PC_3,
+  A3          = PC_2,
+  A4          = PC_1,
+  A5          = PC_0,
+    
+  A6          = PA_7,
+  A7          = PA_2,
+    
+  D0          = PA_2,
+  D1          = PA_3,
+  D2          = PA_12,
+  D3          = PB_3,
+  D4          = PB_5,
+  D5          = PA_15,
+  D6          = PB_10,
+  D7          = PC_7,
+  D8          = PB_6,
+  D9          = PA_8,
+  D10         = PA_11,
+  D11         = PB_15,
+  D12         = PB_14,
+  D13         = PB_13,
+
+  // Generic signals namings
+  LED1        = PA_5,
+  LED2        = PA_5,
+  LED3        = PA_5,
+  LED4        = PA_5,
+  USER_BUTTON = PC_13,
+  BUTTON1 = USER_BUTTON,
+  SERIAL_TX   = PA_2,
+  SERIAL_RX   = PA_3,
+  USBTX       = SERIAL_TX,
+  USBRX       = SERIAL_RX,
+  I2C_SCL     = PB_8,
+  I2C_SDA     = PB_7,
+  SPI_MOSI    = D11,
+  SPI_MISO    = D12,
+  SPI_SCK     = D13,
+  SPI_CS      = D10,
+  PWM_OUT     = D9,
+
+  //USB pins
+  USB_DM = PA_11,
+  USB_DP = PA_12,
+  USB_NOE = PA_13,
+
+  // Not connected
+  NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,374 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.c
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL        | or PLL_MSI
+  *                                    | (external 8 MHz xtal)  | (internal 4 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | NO
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,378 @@
+;********************** COPYRIGHT(c) 2016  STMicroelectronics ******************
+;* File Name          : startup_stm32l432xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 29-April-2016
+;* Description        : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+__initial_sp    EQU     0x20010000 ; Top of RAM
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x0F800 ; 62KB (64KB, -2*1KB for main thread and scheduler)
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     0                                 ; Reserved
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     USB_IRQHandler                    ; USB FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     0                                 ; Reserved
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     LCD_IRQHandler                    ; LCD global interrupt
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     USB_IRQHandler                    [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     LCD_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+SDMMC1_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+USB_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+LCD_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/stm32l433xx.sct	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,53 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x40000
+#endif
+
+; 256KB FLASH (0x40000) + 64KB SRAM (0x10000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188)  {
+  .ANY (+RW +ZI)
+  }
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,361 @@
+;********************** COPYRIGHT(c) 2016  STMicroelectronics ******************
+;* File Name          : startup_stm32l432xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 29-April-2016
+;* Description        : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+
+__initial_sp    EQU     0x20010000 ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     0                                 ; Reserved
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     USB_IRQHandler                    ; USB FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     0                                 ; Reserved
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     LCD_IRQHandler                    ; LCD global interrupt
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     USB_IRQHandler                    [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     LCD_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+SDMMC1_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+USB_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+LCD_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/stm32l433xx.sct	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,53 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x40000
+#endif
+
+; 256KB FLASH (0x40000) + 64KB SRAM (0x10000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188)  {
+  .ANY (+RW +ZI)
+  }
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/STM32L433XX.ld	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,161 @@
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 256k
+#endif
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+  SRAM1 (rwx)  : ORIGIN = 0x20000188, LENGTH = 64k - 0x188
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > SRAM1
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > SRAM1
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > SRAM1
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM1
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,472 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l432xx.s
+  * @author    MCD Application Team
+  * @version   V1.1.1
+  * @date      29-April-2016
+  * @brief     STM32L432xx devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  //bl  main
+  // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+  // and when existing hardware_init_hook() and software_init_hook() before
+  // starting main(). software_init_hook() is available and has to be called due
+  // to initializsation when using rtos.
+  bl _start
+  bx  lr
+
+LoopForever:
+    b LoopForever
+
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_PVM_IRQHandler
+	.word	TAMP_STAMP_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_IRQHandler
+	.word	CAN1_TX_IRQHandler
+	.word	CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	0
+	.word	0
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SDMMC1_IRQHandler
+	.word	0
+	.word	SPI3_IRQHandler
+	.word	0
+	.word	0
+	.word	TIM6_DAC_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	COMP_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	USB_IRQHandler
+	.word	DMA2_Channel6_IRQHandler
+	.word	DMA2_Channel7_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	QUADSPI_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	0
+	.word	SWPMI1_IRQHandler
+	.word	TSC_IRQHandler
+	.word	LCD_IRQHandler
+	.word	0
+	.word	RNG_IRQHandler
+	.word	FPU_IRQHandler
+	.word	CRS_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	TAMP_STAMP_IRQHandler
+	.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_IRQHandler
+	.thumb_set ADC1_IRQHandler,Default_Handler
+
+	.weak	CAN1_TX_IRQHandler
+	.thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX0_IRQHandler
+	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_TIM15_IRQHandler
+	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_TIM16_IRQHandler
+	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC_IRQHandler
+	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	COMP_IRQHandler
+	.thumb_set COMP_IRQHandler,Default_Handler
+	
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+	
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler	
+	
+	.weak	USB_IRQHandler
+	.thumb_set USB_IRQHandler,Default_Handler	
+	
+	.weak	DMA2_Channel6_IRQHandler
+	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler	
+	
+	.weak	DMA2_Channel7_IRQHandler
+	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler	
+	
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler	
+	
+	.weak	QUADSPI_IRQHandler
+	.thumb_set QUADSPI_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler	
+	
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+	
+	.weak	SWPMI1_IRQHandler
+	.thumb_set SWPMI1_IRQHandler,Default_Handler
+	
+	.weak	TSC_IRQHandler
+	.thumb_set TSC_IRQHandler,Default_Handler
+	
+	.weak	LCD_IRQHandler
+	.thumb_set LCD_IRQHandler,Default_Handler
+	
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+	
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+	
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,563 @@
+;/********************* COPYRIGHT(c) 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l432xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 29-April-2016
+;* Description        : STM32L432xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler                   ; ADC1
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     0                                 ; Reserved
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     USB_IRQHandler                    ; USB FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     0                                 ; Reserved
+        DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     LCD_IRQHandler                    ; LCD global interrupt
+        DCD     0                                 ; Reserved
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+       PUBWEAK LCD_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+LCD_IRQHandler
+       B LCD_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/stm32l433xx.icf	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,33 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x40000; }
+
+/* [ROM = 256kb = 0x40000] */
+define symbol __intvec_start__     = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
+
+/* [RAM = 48kb + 16kb = 0x10000] */
+/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */
+define symbol __region_SRAM1_start__  = 0x20000188;
+define symbol __region_SRAM1_end__    = 0x2000FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
+
+define symbol __size_cstack__ = 0x2000;
+define symbol __size_heap__   = 0x4000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in SRAM1_region   { readwrite, block STACKHEAP };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32l4xx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis_nvic.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187
+// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+#define NVIC_NUM_VECTORS        98
+#define NVIC_RAM_VECTOR_ADDRESS SRAM1_BASE    // Vectors positioned at start of SRAM1
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/hal_tick.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,66 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32l4xx.h"
+#include "stm32l4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST      TIM2
+#define TIM_MST_IRQ  TIM2_IRQn
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
+
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
+
+#define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
+
+#define TIM_MST_PCLK  1 // Select the peripheral clock number (1 or 2)
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,15973 @@
+/**
+  ******************************************************************************
+  * @file    stm32l433xx.h
+  * @author  MCD Application Team
+  * @version V1.3.2
+  * @date    16-June-2017
+  * @brief   CMSIS STM32L433xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32l433xx
+  * @{
+  */
+
+#ifndef __STM32L433xx_H
+#define __STM32L433xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+   */
+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */
+  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
+  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
+  USB_IRQn                    = 67,     /*!< USB event Interrupt                                               */
+  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
+  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
+  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
+  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */
+  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */
+  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
+  LCD_IRQn                    = 78,     /*!< LCD global interrupt                                              */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  CRS_IRQn                    = 82      /*!< CRS global interrupt                                              */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32l4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
+  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
+  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
+  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
+  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
+       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
+  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
+  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
+  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
+       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
+  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
+  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
+       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
+       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
+  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
+       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
+  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
+  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
+  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
+  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
+       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
+  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
+  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
+  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
+  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
+       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
+  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
+       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
+       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
+  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
+  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+  uint32_t      RESERVED1;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x300 */
+  uint32_t      RESERVED2;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
+  uint32_t      RESERVED3;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+  * @brief Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct 
+{
+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
+  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
+  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
+  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
+  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
+  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSELR;       /*!< DMA channel selection register              */
+} DMA_Request_TypeDef;
+
+/* Legacy define */
+#define DMA_request_TypeDef  DMA_Request_TypeDef
+
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
+  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
+  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
+  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
+  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
+  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
+  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
+  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
+  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
+  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
+  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
+  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
+  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
+} EXTI_TypeDef;
+
+
+/**
+  * @brief Firewall
+  */
+
+typedef struct
+{
+  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
+  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
+  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
+  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
+  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
+  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
+  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
+  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
+} FIREWALL_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
+  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
+  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
+  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
+  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
+  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
+  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
+  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
+  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
+  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
+  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
+  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
+} FLASH_TypeDef;
+
+
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
+  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
+
+} GPIO_TypeDef;
+
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief LCD
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< LCD control register,              Address offset: 0x00 */
+  __IO uint32_t FCR;         /*!< LCD frame control register,        Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< LCD status register,               Address offset: 0x08 */
+  __IO uint32_t CLR;         /*!< LCD clear register,                Address offset: 0x0C */
+  uint32_t RESERVED;         /*!< Reserved,                          Address offset: 0x10 */
+  __IO uint32_t RAM[16];     /*!< LCD display memory,           Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
+  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
+  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
+  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
+  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
+  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
+  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
+  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
+  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
+  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
+  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
+  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
+  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
+  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
+  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
+  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
+  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
+  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
+  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
+  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
+  uint32_t RESERVED1;  /*!< Reserved,                            Address offset: 0x48 */
+  uint32_t RESERVED2;  /*!< Reserved,                            Address offset: 0x4C */
+  uint32_t RESERVED3;  /*!< Reserved,                            Address offset: 0x50 */
+  uint32_t RESERVED4;  /*!< Reserved,                            Address offset: 0x54 */ 
+  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
+  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
+} PWR_TypeDef;
+
+
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
+  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
+  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
+  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
+  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
+  uint32_t      RESERVED;    /*!< Reserved,                                                                Address offset: 0x14 */
+  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
+  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
+  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
+  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
+  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
+  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
+  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
+  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
+  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
+  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
+  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
+  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
+  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
+  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
+  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
+  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
+  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
+  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
+  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
+  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
+  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
+  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
+  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
+  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
+  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
+  uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
+  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
+  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
+  __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;    /*!< Reserved  */
+  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
+  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
+  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
+  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
+  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */
+  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
+  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
+  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
+} SYSCFG_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
+  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Touch Sensing Controller (TSC)
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[7];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-4C */
+} TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+/** 
+  * @brief Universal Serial Bus Full Speed Device
+  */
+  
+typedef struct
+{
+  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
+  __IO uint16_t RESERVED0;       /*!< Reserved */     
+  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
+  __IO uint16_t RESERVED1;       /*!< Reserved */       
+  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
+  __IO uint16_t RESERVED2;       /*!< Reserved */       
+  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
+  __IO uint16_t RESERVED3;       /*!< Reserved */       
+  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
+  __IO uint16_t RESERVED4;       /*!< Reserved */       
+  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
+  __IO uint16_t RESERVED5;       /*!< Reserved */       
+  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
+  __IO uint16_t RESERVED6;       /*!< Reserved */       
+  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
+  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
+  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
+  __IO uint16_t RESERVED8;       /*!< Reserved */       
+  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
+  __IO uint16_t RESERVED9;       /*!< Reserved */       
+  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
+  __IO uint16_t RESERVEDA;       /*!< Reserved */       
+  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
+  __IO uint16_t RESERVEDB;       /*!< Reserved */       
+  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
+  __IO uint16_t RESERVEDC;       /*!< Reserved */       
+  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
+  __IO uint16_t RESERVEDD;       /*!< Reserved */       
+  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
+  __IO uint16_t RESERVEDE;       /*!< Reserved */       
+} USB_TypeDef;
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
+#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
+#define SRAM2_BASE            ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
+#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address */
+#define QSPI_BASE             ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
+
+#define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
+#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX        ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */
+#define SRAM2_SIZE            ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)
+
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define LCD_BASE              (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CRS_BASE              (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define USB_BASE              (APB1PERIPH_BASE + 0x6800U)  /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x6C00U)  /*!< USB_IP Packet Memory Area base address */
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400U)
+#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800U)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00U)
+#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000U)
+#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800U)
+#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400U)
+
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000U)
+#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030U)
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200U)
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00U)
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800U)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000U)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000U)
+
+
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008U)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CU)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030U)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044U)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058U)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CU)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080U)
+#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8U)
+
+
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008U)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CU)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030U)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044U)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058U)
+#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CU)
+#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080U)
+#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8U)
+
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000U)
+#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00U)
+
+
+#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000U)
+#define ADC1_COMMON_BASE      (AHB2PERIPH_BASE + 0x08040300U)
+
+
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800U)
+
+
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t)0xE0042000U)
+
+
+#define PACKAGE_BASE          ((uint32_t)0x1FFF7500U)        /*!< Package data register base address     */
+#define UID_BASE              ((uint32_t)0x1FFF7590U)        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0U)        /*!< Flash size data register base address  */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define LCD                 ((LCD_TypeDef *) LCD_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+// #define CAN                 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define USB                 ((USB_TypeDef *) USB_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC1_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP1_COMMON       ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+
+
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
+
+
+
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+/* Note: No specific macro feature on this device */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)                                    
+#define ADC_ISR_ADRDY_Msk              (0x1U << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)                                    
+#define ADC_ISR_EOSMP_Msk              (0x1U << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)                                    
+#define ADC_ISR_EOC_Msk                (0x1U << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)                                    
+#define ADC_ISR_EOS_Msk                (0x1U << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)                                    
+#define ADC_ISR_OVR_Msk                (0x1U << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)                                    
+#define ADC_ISR_JEOC_Msk               (0x1U << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)                                    
+#define ADC_ISR_JEOS_Msk               (0x1U << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)                                    
+#define ADC_ISR_AWD1_Msk               (0x1U << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)                                    
+#define ADC_ISR_AWD2_Msk               (0x1U << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)                                    
+#define ADC_ISR_AWD3_Msk               (0x1U << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos              (10U)                                   
+#define ADC_ISR_JQOVF_Msk              (0x1U << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)                                    
+#define ADC_IER_ADRDYIE_Msk            (0x1U << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)                                    
+#define ADC_IER_EOSMPIE_Msk            (0x1U << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)                                    
+#define ADC_IER_EOCIE_Msk              (0x1U << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)                                    
+#define ADC_IER_EOSIE_Msk              (0x1U << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)                                    
+#define ADC_IER_OVRIE_Msk              (0x1U << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)                                    
+#define ADC_IER_JEOCIE_Msk             (0x1U << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)                                    
+#define ADC_IER_JEOSIE_Msk             (0x1U << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)                                    
+#define ADC_IER_AWD1IE_Msk             (0x1U << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)                                    
+#define ADC_IER_AWD2IE_Msk             (0x1U << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)                                    
+#define ADC_IER_AWD3IE_Msk             (0x1U << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos            (10U)                                   
+#define ADC_IER_JQOVFIE_Msk            (0x1U << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC             (ADC_IER_EOCIE)
+#define ADC_IER_EOS             (ADC_IER_EOSIE)
+#define ADC_IER_OVR             (ADC_IER_OVRIE)
+#define ADC_IER_JEOC            (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS            (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1            (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2            (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3            (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)                                    
+#define ADC_CR_ADEN_Msk                (0x1U << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)                                    
+#define ADC_CR_ADDIS_Msk               (0x1U << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)                                    
+#define ADC_CR_ADSTART_Msk             (0x1U << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)                                    
+#define ADC_CR_JADSTART_Msk            (0x1U << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)                                    
+#define ADC_CR_ADSTP_Msk               (0x1U << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)                                    
+#define ADC_CR_JADSTP_Msk              (0x1U << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos            (28U)                                   
+#define ADC_CR_ADVREGEN_Msk            (0x1U << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos             (29U)                                   
+#define ADC_CR_DEEPPWD_Msk             (0x1U << ADC_CR_DEEPPWD_Pos)            /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)                                   
+#define ADC_CR_ADCALDIF_Msk            (0x1U << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)                                   
+#define ADC_CR_ADCAL_Msk               (0x1U << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR register  ******************/
+#define ADC_CFGR_DMAEN_Pos             (0U)                                    
+#define ADC_CFGR_DMAEN_Msk             (0x1U << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos            (1U)                                    
+#define ADC_CFGR_DMACFG_Msk            (0x1U << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_RES_Pos               (3U)                                    
+#define ADC_CFGR_RES_Msk               (0x3U << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */
+#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
+#define ADC_CFGR_RES_0                 (0x1U << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */
+#define ADC_CFGR_RES_1                 (0x2U << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos             (5U)                                    
+#define ADC_CFGR_ALIGN_Msk             (0x1U << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos            (6U)                                    
+#define ADC_CFGR_EXTSEL_Msk            (0xFU << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0              (0x1U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1              (0x2U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2              (0x4U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3              (0x8U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos             (10U)                                   
+#define ADC_CFGR_EXTEN_Msk             (0x3U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0               (0x1U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1               (0x2U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos            (12U)                                   
+#define ADC_CFGR_OVRMOD_Msk            (0x1U << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos              (13U)                                   
+#define ADC_CFGR_CONT_Msk              (0x1U << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */
+#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos            (14U)                                   
+#define ADC_CFGR_AUTDLY_Msk            (0x1U << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos            (16U)                                   
+#define ADC_CFGR_DISCEN_Msk            (0x1U << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos           (17U)                                   
+#define ADC_CFGR_DISCNUM_Msk           (0x7U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0             (0x1U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1             (0x2U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2             (0x4U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos           (20U)                                   
+#define ADC_CFGR_JDISCEN_Msk           (0x1U << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos               (21U)                                   
+#define ADC_CFGR_JQM_Msk               (0x1U << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */
+#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos           (22U)                                   
+#define ADC_CFGR_AWD1SGL_Msk           (0x1U << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos            (23U)                                   
+#define ADC_CFGR_AWD1EN_Msk            (0x1U << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos           (24U)                                   
+#define ADC_CFGR_JAWD1EN_Msk           (0x1U << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos             (25U)                                   
+#define ADC_CFGR_JAUTO_Msk             (0x1U << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos            (26U)                                   
+#define ADC_CFGR_AWD1CH_Msk            (0x1FU << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0              (0x01U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1              (0x02U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2              (0x04U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3              (0x08U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4              (0x10U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos             (31U)                                   
+#define ADC_CFGR_JQDIS_Msk             (0x1U << ADC_CFGR_JQDIS_Pos)            /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)                                    
+#define ADC_CFGR2_ROVSE_Msk            (0x1U << ADC_CFGR2_ROVSE_Pos)           /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)                                    
+#define ADC_CFGR2_JOVSE_Msk            (0x1U << ADC_CFGR2_JOVSE_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos             (2U)                                    
+#define ADC_CFGR2_OVSR_Msk             (0x7U << ADC_CFGR2_OVSR_Pos)            /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x1U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1               (0x2U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2               (0x4U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)                                    
+#define ADC_CFGR2_OVSS_Msk             (0xFU << ADC_CFGR2_OVSS_Pos)            /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)                                    
+#define ADC_CFGR2_TROVS_Msk            (0x1U << ADC_CFGR2_TROVS_Pos)           /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)                                   
+#define ADC_CFGR2_ROVSM_Msk            (0x1U << ADC_CFGR2_ROVSM_Pos)           /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)                                    
+#define ADC_SMPR1_SMP0_Msk             (0x7U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)                                    
+#define ADC_SMPR1_SMP1_Msk             (0x7U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)                                    
+#define ADC_SMPR1_SMP2_Msk             (0x7U << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)                                    
+#define ADC_SMPR1_SMP3_Msk             (0x7U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)                                   
+#define ADC_SMPR1_SMP4_Msk             (0x7U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)                                   
+#define ADC_SMPR1_SMP5_Msk             (0x7U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)                                   
+#define ADC_SMPR1_SMP6_Msk             (0x7U << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)                                   
+#define ADC_SMPR1_SMP7_Msk             (0x7U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)                                   
+#define ADC_SMPR1_SMP8_Msk             (0x7U << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1U << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2U << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4U << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)                                   
+#define ADC_SMPR1_SMP9_Msk             (0x7U << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1U << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2U << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4U << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)                                    
+#define ADC_SMPR2_SMP10_Msk            (0x7U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)                                    
+#define ADC_SMPR2_SMP11_Msk            (0x7U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)                                    
+#define ADC_SMPR2_SMP12_Msk            (0x7U << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)                                    
+#define ADC_SMPR2_SMP13_Msk            (0x7U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)                                   
+#define ADC_SMPR2_SMP14_Msk            (0x7U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)                                   
+#define ADC_SMPR2_SMP15_Msk            (0x7U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)                                   
+#define ADC_SMPR2_SMP16_Msk            (0x7U << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)                                   
+#define ADC_SMPR2_SMP17_Msk            (0x7U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)                                   
+#define ADC_SMPR2_SMP18_Msk            (0x7U << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1U << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2U << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4U << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_TR1 register  *******************/
+#define ADC_TR1_LT1_Pos                (0U)                                    
+#define ADC_TR1_LT1_Msk                (0xFFFU << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */
+#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0                  (0x001U << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */
+#define ADC_TR1_LT1_1                  (0x002U << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */
+#define ADC_TR1_LT1_2                  (0x004U << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */
+#define ADC_TR1_LT1_3                  (0x008U << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */
+#define ADC_TR1_LT1_4                  (0x010U << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */
+#define ADC_TR1_LT1_5                  (0x020U << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */
+#define ADC_TR1_LT1_6                  (0x040U << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */
+#define ADC_TR1_LT1_7                  (0x080U << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */
+#define ADC_TR1_LT1_8                  (0x100U << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */
+#define ADC_TR1_LT1_9                  (0x200U << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */
+#define ADC_TR1_LT1_10                 (0x400U << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */
+#define ADC_TR1_LT1_11                 (0x800U << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos                (16U)                                   
+#define ADC_TR1_HT1_Msk                (0xFFFU << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0                  (0x001U << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */
+#define ADC_TR1_HT1_1                  (0x002U << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */
+#define ADC_TR1_HT1_2                  (0x004U << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */
+#define ADC_TR1_HT1_3                  (0x008U << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */
+#define ADC_TR1_HT1_4                  (0x010U << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */
+#define ADC_TR1_HT1_5                  (0x020U << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */
+#define ADC_TR1_HT1_6                  (0x040U << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */
+#define ADC_TR1_HT1_7                  (0x080U << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */
+#define ADC_TR1_HT1_8                  (0x100U << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */
+#define ADC_TR1_HT1_9                  (0x200U << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */
+#define ADC_TR1_HT1_10                 (0x400U << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */
+#define ADC_TR1_HT1_11                 (0x800U << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */
+
+/********************  Bit definition for ADC_TR2 register  *******************/
+#define ADC_TR2_LT2_Pos                (0U)                                    
+#define ADC_TR2_LT2_Msk                (0xFFU << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */
+#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0                  (0x01U << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */
+#define ADC_TR2_LT2_1                  (0x02U << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */
+#define ADC_TR2_LT2_2                  (0x04U << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */
+#define ADC_TR2_LT2_3                  (0x08U << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */
+#define ADC_TR2_LT2_4                  (0x10U << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */
+#define ADC_TR2_LT2_5                  (0x20U << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */
+#define ADC_TR2_LT2_6                  (0x40U << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */
+#define ADC_TR2_LT2_7                  (0x80U << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos                (16U)                                   
+#define ADC_TR2_HT2_Msk                (0xFFU << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0                  (0x01U << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */
+#define ADC_TR2_HT2_1                  (0x02U << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */
+#define ADC_TR2_HT2_2                  (0x04U << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */
+#define ADC_TR2_HT2_3                  (0x08U << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */
+#define ADC_TR2_HT2_4                  (0x10U << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */
+#define ADC_TR2_HT2_5                  (0x20U << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */
+#define ADC_TR2_HT2_6                  (0x40U << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */
+#define ADC_TR2_HT2_7                  (0x80U << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_TR3 register  *******************/
+#define ADC_TR3_LT3_Pos                (0U)                                    
+#define ADC_TR3_LT3_Msk                (0xFFU << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */
+#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0                  (0x01U << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */
+#define ADC_TR3_LT3_1                  (0x02U << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */
+#define ADC_TR3_LT3_2                  (0x04U << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */
+#define ADC_TR3_LT3_3                  (0x08U << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */
+#define ADC_TR3_LT3_4                  (0x10U << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */
+#define ADC_TR3_LT3_5                  (0x20U << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */
+#define ADC_TR3_LT3_6                  (0x40U << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */
+#define ADC_TR3_LT3_7                  (0x80U << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos                (16U)                                   
+#define ADC_TR3_HT3_Msk                (0xFFU << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0                  (0x01U << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */
+#define ADC_TR3_HT3_1                  (0x02U << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */
+#define ADC_TR3_HT3_2                  (0x04U << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */
+#define ADC_TR3_HT3_3                  (0x08U << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */
+#define ADC_TR3_HT3_4                  (0x10U << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */
+#define ADC_TR3_HT3_5                  (0x20U << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */
+#define ADC_TR3_HT3_6                  (0x40U << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */
+#define ADC_TR3_HT3_7                  (0x80U << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)                                    
+#define ADC_SQR1_L_Msk                 (0xFU << ADC_SQR1_L_Pos)                /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1U << ADC_SQR1_L_Pos)                /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2U << ADC_SQR1_L_Pos)                /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4U << ADC_SQR1_L_Pos)                /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8U << ADC_SQR1_L_Pos)                /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)                                    
+#define ADC_SQR1_SQ1_Msk               (0x1FU << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)                                   
+#define ADC_SQR1_SQ2_Msk               (0x1FU << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01U << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02U << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04U << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08U << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10U << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)                                   
+#define ADC_SQR1_SQ3_Msk               (0x1FU << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01U << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02U << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04U << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08U << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10U << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)                                   
+#define ADC_SQR1_SQ4_Msk               (0x1FU << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01U << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02U << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04U << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08U << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10U << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)                                    
+#define ADC_SQR2_SQ5_Msk               (0x1FU << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)                                    
+#define ADC_SQR2_SQ6_Msk               (0x1FU << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)                                   
+#define ADC_SQR2_SQ7_Msk               (0x1FU << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01U << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02U << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04U << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08U << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10U << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)                                   
+#define ADC_SQR2_SQ8_Msk               (0x1FU << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01U << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02U << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04U << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08U << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10U << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)                                   
+#define ADC_SQR2_SQ9_Msk               (0x1FU << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01U << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02U << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04U << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08U << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10U << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)                                    
+#define ADC_SQR3_SQ10_Msk              (0x1FU << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)                                    
+#define ADC_SQR3_SQ11_Msk              (0x1FU << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)                                   
+#define ADC_SQR3_SQ12_Msk              (0x1FU << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01U << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02U << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04U << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08U << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10U << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)                                   
+#define ADC_SQR3_SQ13_Msk              (0x1FU << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01U << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02U << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04U << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08U << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10U << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)                                   
+#define ADC_SQR3_SQ14_Msk              (0x1FU << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01U << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02U << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04U << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08U << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10U << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)                                    
+#define ADC_SQR4_SQ15_Msk              (0x1FU << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)                                    
+#define ADC_SQR4_SQ16_Msk              (0x1FU << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)                                    
+#define ADC_DR_RDATA_Msk               (0xFFFFU << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x0001U << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x0002U << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x0004U << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x0008U << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x0010U << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x0020U << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x0040U << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x0080U << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x0100U << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x0200U << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x0400U << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x0800U << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x1000U << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x2000U << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x4000U << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x8000U << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)                                    
+#define ADC_JSQR_JL_Msk                (0x3U << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1U << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2U << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)                                    
+#define ADC_JSQR_JEXTSEL_Msk           (0xFU << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x1U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x2U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x4U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x8U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos            (6U)                                    
+#define ADC_JSQR_JEXTEN_Msk            (0x3U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1              (0x2U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos              (8U)                                    
+#define ADC_JSQR_JSQ1_Msk              (0x1FU << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1                (0x02U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2                (0x04U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3                (0x08U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4                (0x10U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos              (14U)                                   
+#define ADC_JSQR_JSQ2_Msk              (0x1FU << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1                (0x02U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2                (0x04U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3                (0x08U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4                (0x10U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos              (20U)                                   
+#define ADC_JSQR_JSQ3_Msk              (0x1FU << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1                (0x02U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2                (0x04U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3                (0x08U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4                (0x10U << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (26U)                                   
+#define ADC_JSQR_JSQ4_Msk              (0x1FU << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01U << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1                (0x02U << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2                (0x04U << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3                (0x08U << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4                (0x10U << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET1_Pos           (0U)                                    
+#define ADC_OFR1_OFFSET1_Msk           (0xFFFU << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0             (0x001U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1             (0x002U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2             (0x004U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3             (0x008U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4             (0x010U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5             (0x020U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6             (0x040U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7             (0x080U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8             (0x100U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9             (0x200U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10            (0x400U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11            (0x800U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos        (26U)                                   
+#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0          (0x01U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1          (0x02U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2          (0x04U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3          (0x08U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4          (0x10U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos        (31U)                                   
+#define ADC_OFR1_OFFSET1_EN_Msk        (0x1U << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET2_Pos           (0U)                                    
+#define ADC_OFR2_OFFSET2_Msk           (0xFFFU << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0             (0x001U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1             (0x002U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2             (0x004U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3             (0x008U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4             (0x010U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5             (0x020U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6             (0x040U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7             (0x080U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8             (0x100U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9             (0x200U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10            (0x400U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11            (0x800U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos        (26U)                                   
+#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0          (0x01U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1          (0x02U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2          (0x04U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3          (0x08U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4          (0x10U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos        (31U)                                   
+#define ADC_OFR2_OFFSET2_EN_Msk        (0x1U << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET3_Pos           (0U)                                    
+#define ADC_OFR3_OFFSET3_Msk           (0xFFFU << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0             (0x001U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1             (0x002U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2             (0x004U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3             (0x008U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4             (0x010U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5             (0x020U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6             (0x040U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7             (0x080U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8             (0x100U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9             (0x200U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10            (0x400U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11            (0x800U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos        (26U)                                   
+#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0          (0x01U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1          (0x02U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2          (0x04U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3          (0x08U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4          (0x10U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos        (31U)                                   
+#define ADC_OFR3_OFFSET3_EN_Msk        (0x1U << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET4_Pos           (0U)                                    
+#define ADC_OFR4_OFFSET4_Msk           (0xFFFU << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0             (0x001U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1             (0x002U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2             (0x004U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3             (0x008U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4             (0x010U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5             (0x020U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6             (0x040U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7             (0x080U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8             (0x100U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9             (0x200U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10            (0x400U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11            (0x800U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos        (26U)                                   
+#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0          (0x01U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1          (0x02U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2          (0x04U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3          (0x08U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4          (0x10U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos        (31U)                                   
+#define ADC_OFR4_OFFSET4_EN_Msk        (0x1U << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)                                    
+#define ADC_JDR1_JDATA_Msk             (0xFFFFU << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x0001U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x0002U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x0004U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x0008U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x0010U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x0020U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x0040U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x0080U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x0100U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x0200U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x0400U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x0800U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x1000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x2000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x4000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x8000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR2 register  ******************/
+#define ADC_JDR2_JDATA_Pos             (0U)                                    
+#define ADC_JDR2_JDATA_Msk             (0xFFFFU << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x0001U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x0002U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x0004U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x0008U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x0010U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x0020U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x0040U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x0080U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x0100U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x0200U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x0400U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x0800U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x1000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x2000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x4000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x8000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR3 register  ******************/
+#define ADC_JDR3_JDATA_Pos             (0U)                                    
+#define ADC_JDR3_JDATA_Msk             (0xFFFFU << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x0001U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x0002U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x0004U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x0008U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x0010U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x0020U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x0040U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x0080U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x0100U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x0200U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x0400U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x0800U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x1000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x2000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x4000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x8000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR4 register  ******************/
+#define ADC_JDR4_JDATA_Pos             (0U)                                    
+#define ADC_JDR4_JDATA_Msk             (0xFFFFU << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x0001U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x0002U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x0004U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x0008U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x0010U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x0020U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x0040U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x0080U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x0100U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x0200U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x0400U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x0800U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x1000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x2000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x4000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x8000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)                                    
+#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)                                    
+#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)                                    
+#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)                                    
+#define ADC_CALFACT_CALFACT_S_Msk      (0x7FU << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)                                   
+#define ADC_CALFACT_CALFACT_D_Msk      (0x7FU << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_CKMODE_Pos             (16U)                                   
+#define ADC_CCR_CKMODE_Msk             (0x3U << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0               (0x1U << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1               (0x2U << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos              (18U)                                   
+#define ADC_CCR_PRESC_Msk              (0xFU << ADC_CCR_PRESC_Pos)             /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0                (0x1U << ADC_CCR_PRESC_Pos)             /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                (0x2U << ADC_CCR_PRESC_Pos)             /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                (0x4U << ADC_CCR_PRESC_Pos)             /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                (0x8U << ADC_CCR_PRESC_Pos)             /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)                                   
+#define ADC_CCR_VREFEN_Msk             (0x1U << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos               (23U)                                   
+#define ADC_CCR_TSEN_Msk               (0x1U << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */
+#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos             (24U)                                   
+#define ADC_CCR_VBATEN_Msk             (0x1U << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)                                          
+#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)                                          
+#define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)                                          
+#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)                                          
+#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)                                          
+#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)                                          
+#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)                                          
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)                                          
+#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)                                         
+#define CRS_CR_SYNCOKIE_Msk       (0x1U << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)                                         
+#define CRS_CR_SYNCWARNIE_Msk     (0x1U << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos          (2U)                                         
+#define CRS_CR_ERRIE_Msk          (0x1U << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos        (3U)                                         
+#define CRS_CR_ESYNCIE_Msk        (0x1U << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos            (5U)                                         
+#define CRS_CR_CEN_Msk            (0x1U << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)                                         
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1U << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos         (7U)                                         
+#define CRS_CR_SWSYNC_Msk         (0x1U << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos           (8U)                                         
+#define CRS_CR_TRIM_Msk           (0x3FU << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)                                         
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFU << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos        (16U)                                        
+#define CRS_CFGR_FELIM_Msk        (0xFFU << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)                                        
+#define CRS_CFGR_SYNCDIV_Msk      (0x7U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0        (0x1U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)                                        
+#define CRS_CFGR_SYNCSRC_Msk      (0x3U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0        (0x1U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)                                        
+#define CRS_CFGR_SYNCPOL_Msk      (0x1U << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
+  
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)                                         
+#define CRS_ISR_SYNCOKF_Msk       (0x1U << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)                                         
+#define CRS_ISR_SYNCWARNF_Msk     (0x1U << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos          (2U)                                         
+#define CRS_ISR_ERRF_Msk          (0x1U << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos        (3U)                                         
+#define CRS_ISR_ESYNCF_Msk        (0x1U << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos       (8U)                                         
+#define CRS_ISR_SYNCERR_Msk       (0x1U << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos      (9U)                                         
+#define CRS_ISR_SYNCMISS_Msk      (0x1U << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos       (10U)                                        
+#define CRS_ISR_TRIMOVF_Msk       (0x1U << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)                                        
+#define CRS_ISR_FEDIR_Msk         (0x1U << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos         (16U)                                        
+#define CRS_ISR_FECAP_Msk         (0xFFFFU << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)                                         
+#define CRS_ICR_SYNCOKC_Msk       (0x1U << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)                                         
+#define CRS_ICR_SYNCWARNC_Msk     (0x1U << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos          (2U)                                         
+#define CRS_ICR_ERRC_Msk          (0x1U << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos        (3U)                                         
+#define CRS_ICR_ESYNCC_Msk        (0x1U << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)                                      
+#define DAC_CR_CEN1_Msk             (0x1U << DAC_CR_CEN1_Pos)                  /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)                                      
+#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (18U)                                      
+#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)                                      
+#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)                                      
+#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)                                      
+#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)                                      
+#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
+#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)                                      
+#define DAC_CR_CEN2_Msk             (0x1U << DAC_CR_CEN2_Pos)                  /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)                                      
+#define DAC_SR_CAL_FLAG1_Msk        (0x1U << DAC_SR_CAL_FLAG1_Pos)             /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)                                      
+#define DAC_SR_BWST1_Msk            (0x1U << DAC_SR_BWST1_Pos)                 /*!< 0x00008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)                                      
+#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)                                      
+#define DAC_SR_CAL_FLAG2_Msk        (0x1U << DAC_SR_CAL_FLAG2_Pos)             /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)                                      
+#define DAC_SR_BWST2_Msk            (0x1U << DAC_SR_BWST2_Pos)                 /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)                                       
+#define DAC_CCR_OTRIM1_Msk          (0x1FU << DAC_CCR_OTRIM1_Pos)              /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)                                      
+#define DAC_CCR_OTRIM2_Msk          (0x1FU << DAC_CCR_OTRIM2_Pos)              /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)                                       
+#define DAC_MCR_MODE1_Msk           (0x7U << DAC_MCR_MODE1_Pos)                /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1U << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2U << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4U << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)                                      
+#define DAC_MCR_MODE2_Msk           (0x7U << DAC_MCR_MODE2_Pos)                /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1U << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2U << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4U << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)                                       
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)                                       
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)                                       
+#define DAC_SHHR_THOLD1_Msk         (0x3FFU << DAC_SHHR_THOLD1_Pos)            /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)                                      
+#define DAC_SHHR_THOLD2_Msk         (0x3FFU << DAC_SHHR_THOLD2_Pos)            /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)                                       
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFU << DAC_SHRR_TREFRESH1_Pos)          /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)                                      
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFU << DAC_SHRR_TREFRESH2_Pos)          /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos       (0U)                                            
+#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
+#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos      (1U)                                            
+#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
+#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos      (2U)                                            
+#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
+#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos      (3U)                                            
+#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
+#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos       (4U)                                            
+#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
+#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos      (5U)                                            
+#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
+#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos      (6U)                                            
+#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
+#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos      (7U)                                            
+#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
+#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos       (8U)                                            
+#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
+#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos      (9U)                                            
+#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
+#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos      (10U)                                           
+#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
+#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos      (11U)                                           
+#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
+#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos       (12U)                                           
+#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
+#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos      (13U)                                           
+#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
+#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos      (14U)                                           
+#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
+#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos      (15U)                                           
+#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
+#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos       (16U)                                           
+#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
+#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos      (17U)                                           
+#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
+#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos      (18U)                                           
+#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
+#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos      (19U)                                           
+#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
+#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos       (20U)                                           
+#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
+#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos      (21U)                                           
+#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
+#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos      (22U)                                           
+#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
+#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos      (23U)                                           
+#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
+#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos       (24U)                                           
+#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
+#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos      (25U)                                           
+#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
+#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos      (26U)                                           
+#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
+#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos      (27U)                                           
+#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
+#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos     (0U)                                            
+#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos    (1U)                                            
+#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos    (2U)                                            
+#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos    (3U)                                            
+#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos     (4U)                                            
+#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos    (5U)                                            
+#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos    (6U)                                            
+#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos    (7U)                                            
+#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos     (8U)                                            
+#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos    (9U)                                            
+#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos    (10U)                                           
+#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos    (11U)                                           
+#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos     (12U)                                           
+#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos    (13U)                                           
+#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos    (14U)                                           
+#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos    (15U)                                           
+#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos     (16U)                                           
+#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos    (17U)                                           
+#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos    (18U)                                           
+#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos    (19U)                                           
+#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos     (20U)                                           
+#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos    (21U)                                           
+#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos    (22U)                                           
+#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos    (23U)                                           
+#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos     (24U)                                           
+#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos    (25U)                                           
+#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos    (26U)                                           
+#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos    (27U)                                           
+#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos         (0U)                                            
+#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
+#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
+#define DMA_CCR_TCIE_Pos       (1U)                                            
+#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
+#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
+#define DMA_CCR_HTIE_Pos       (2U)                                            
+#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
+#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
+#define DMA_CCR_TEIE_Pos       (3U)                                            
+#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
+#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
+#define DMA_CCR_DIR_Pos        (4U)                                            
+#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
+#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
+#define DMA_CCR_CIRC_Pos       (5U)                                            
+#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
+#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
+#define DMA_CCR_PINC_Pos       (6U)                                            
+#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
+#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
+#define DMA_CCR_MINC_Pos       (7U)                                            
+#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
+#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
+
+#define DMA_CCR_PSIZE_Pos      (8U)                                            
+#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
+#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos      (10U)                                           
+#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
+#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos         (12U)                                           
+#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
+#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
+#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos    (14U)                                           
+#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos      (0U)                                            
+#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos        (0U)                                            
+#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos        (0U)                                            
+#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
+
+
+/*******************  Bit definition for DMA_CSELR register  *******************/
+#define DMA_CSELR_C1S_Pos      (0U)                                            
+#define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
+#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos      (4U)                                            
+#define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
+#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos      (8U)                                            
+#define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
+#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos      (12U)                                           
+#define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
+#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos      (16U)                                           
+#define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
+#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos      (20U)                                           
+#define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
+#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos      (24U)                                           
+#define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
+#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos        (0U)                                          
+#define EXTI_IMR1_IM0_Msk        (0x1U << EXTI_IMR1_IM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos        (1U)                                          
+#define EXTI_IMR1_IM1_Msk        (0x1U << EXTI_IMR1_IM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos        (2U)                                          
+#define EXTI_IMR1_IM2_Msk        (0x1U << EXTI_IMR1_IM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos        (3U)                                          
+#define EXTI_IMR1_IM3_Msk        (0x1U << EXTI_IMR1_IM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos        (4U)                                          
+#define EXTI_IMR1_IM4_Msk        (0x1U << EXTI_IMR1_IM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos        (5U)                                          
+#define EXTI_IMR1_IM5_Msk        (0x1U << EXTI_IMR1_IM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos        (6U)                                          
+#define EXTI_IMR1_IM6_Msk        (0x1U << EXTI_IMR1_IM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos        (7U)                                          
+#define EXTI_IMR1_IM7_Msk        (0x1U << EXTI_IMR1_IM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos        (8U)                                          
+#define EXTI_IMR1_IM8_Msk        (0x1U << EXTI_IMR1_IM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos        (9U)                                          
+#define EXTI_IMR1_IM9_Msk        (0x1U << EXTI_IMR1_IM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos       (10U)                                         
+#define EXTI_IMR1_IM10_Msk       (0x1U << EXTI_IMR1_IM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos       (11U)                                         
+#define EXTI_IMR1_IM11_Msk       (0x1U << EXTI_IMR1_IM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos       (12U)                                         
+#define EXTI_IMR1_IM12_Msk       (0x1U << EXTI_IMR1_IM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos       (13U)                                         
+#define EXTI_IMR1_IM13_Msk       (0x1U << EXTI_IMR1_IM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos       (14U)                                         
+#define EXTI_IMR1_IM14_Msk       (0x1U << EXTI_IMR1_IM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos       (15U)                                         
+#define EXTI_IMR1_IM15_Msk       (0x1U << EXTI_IMR1_IM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos       (16U)                                         
+#define EXTI_IMR1_IM16_Msk       (0x1U << EXTI_IMR1_IM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos       (17U)                                         
+#define EXTI_IMR1_IM17_Msk       (0x1U << EXTI_IMR1_IM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos       (18U)                                         
+#define EXTI_IMR1_IM18_Msk       (0x1U << EXTI_IMR1_IM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos       (19U)                                         
+#define EXTI_IMR1_IM19_Msk       (0x1U << EXTI_IMR1_IM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos       (20U)                                         
+#define EXTI_IMR1_IM20_Msk       (0x1U << EXTI_IMR1_IM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos       (21U)                                         
+#define EXTI_IMR1_IM21_Msk       (0x1U << EXTI_IMR1_IM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos       (22U)                                         
+#define EXTI_IMR1_IM22_Msk       (0x1U << EXTI_IMR1_IM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos       (23U)                                         
+#define EXTI_IMR1_IM23_Msk       (0x1U << EXTI_IMR1_IM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos       (24U)                                         
+#define EXTI_IMR1_IM24_Msk       (0x1U << EXTI_IMR1_IM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos       (25U)                                         
+#define EXTI_IMR1_IM25_Msk       (0x1U << EXTI_IMR1_IM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos       (26U)                                         
+#define EXTI_IMR1_IM26_Msk       (0x1U << EXTI_IMR1_IM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos       (27U)                                         
+#define EXTI_IMR1_IM27_Msk       (0x1U << EXTI_IMR1_IM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos       (28U)                                         
+#define EXTI_IMR1_IM28_Msk       (0x1U << EXTI_IMR1_IM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM31_Pos       (31U)                                         
+#define EXTI_IMR1_IM31_Msk       (0x1U << EXTI_IMR1_IM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos         (0U)                                          
+#define EXTI_IMR1_IM_Msk         (0x9FFFFFFFU << EXTI_IMR1_IM_Pos)             /*!< 0x9FFFFFFF */
+#define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos        (0U)                                          
+#define EXTI_EMR1_EM0_Msk        (0x1U << EXTI_EMR1_EM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos        (1U)                                          
+#define EXTI_EMR1_EM1_Msk        (0x1U << EXTI_EMR1_EM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos        (2U)                                          
+#define EXTI_EMR1_EM2_Msk        (0x1U << EXTI_EMR1_EM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos        (3U)                                          
+#define EXTI_EMR1_EM3_Msk        (0x1U << EXTI_EMR1_EM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos        (4U)                                          
+#define EXTI_EMR1_EM4_Msk        (0x1U << EXTI_EMR1_EM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos        (5U)                                          
+#define EXTI_EMR1_EM5_Msk        (0x1U << EXTI_EMR1_EM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos        (6U)                                          
+#define EXTI_EMR1_EM6_Msk        (0x1U << EXTI_EMR1_EM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos        (7U)                                          
+#define EXTI_EMR1_EM7_Msk        (0x1U << EXTI_EMR1_EM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos        (8U)                                          
+#define EXTI_EMR1_EM8_Msk        (0x1U << EXTI_EMR1_EM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos        (9U)                                          
+#define EXTI_EMR1_EM9_Msk        (0x1U << EXTI_EMR1_EM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos       (10U)                                         
+#define EXTI_EMR1_EM10_Msk       (0x1U << EXTI_EMR1_EM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos       (11U)                                         
+#define EXTI_EMR1_EM11_Msk       (0x1U << EXTI_EMR1_EM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos       (12U)                                         
+#define EXTI_EMR1_EM12_Msk       (0x1U << EXTI_EMR1_EM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos       (13U)                                         
+#define EXTI_EMR1_EM13_Msk       (0x1U << EXTI_EMR1_EM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos       (14U)                                         
+#define EXTI_EMR1_EM14_Msk       (0x1U << EXTI_EMR1_EM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos       (15U)                                         
+#define EXTI_EMR1_EM15_Msk       (0x1U << EXTI_EMR1_EM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos       (16U)                                         
+#define EXTI_EMR1_EM16_Msk       (0x1U << EXTI_EMR1_EM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos       (17U)                                         
+#define EXTI_EMR1_EM17_Msk       (0x1U << EXTI_EMR1_EM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos       (18U)                                         
+#define EXTI_EMR1_EM18_Msk       (0x1U << EXTI_EMR1_EM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos       (19U)                                         
+#define EXTI_EMR1_EM19_Msk       (0x1U << EXTI_EMR1_EM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos       (20U)                                         
+#define EXTI_EMR1_EM20_Msk       (0x1U << EXTI_EMR1_EM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos       (21U)                                         
+#define EXTI_EMR1_EM21_Msk       (0x1U << EXTI_EMR1_EM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos       (22U)                                         
+#define EXTI_EMR1_EM22_Msk       (0x1U << EXTI_EMR1_EM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos       (23U)                                         
+#define EXTI_EMR1_EM23_Msk       (0x1U << EXTI_EMR1_EM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos       (24U)                                         
+#define EXTI_EMR1_EM24_Msk       (0x1U << EXTI_EMR1_EM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos       (25U)                                         
+#define EXTI_EMR1_EM25_Msk       (0x1U << EXTI_EMR1_EM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos       (26U)                                         
+#define EXTI_EMR1_EM26_Msk       (0x1U << EXTI_EMR1_EM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos       (27U)                                         
+#define EXTI_EMR1_EM27_Msk       (0x1U << EXTI_EMR1_EM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos       (28U)                                         
+#define EXTI_EMR1_EM28_Msk       (0x1U << EXTI_EMR1_EM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM31_Pos       (31U)                                         
+#define EXTI_EMR1_EM31_Msk       (0x1U << EXTI_EMR1_EM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
+
+/******************  Bit definition for EXTI_RTSR1 register  ******************/
+#define EXTI_RTSR1_RT0_Pos       (0U)                                          
+#define EXTI_RTSR1_RT0_Msk       (0x1U << EXTI_RTSR1_RT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_RT1_Pos       (1U)                                          
+#define EXTI_RTSR1_RT1_Msk       (0x1U << EXTI_RTSR1_RT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_RT2_Pos       (2U)                                          
+#define EXTI_RTSR1_RT2_Msk       (0x1U << EXTI_RTSR1_RT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_RT3_Pos       (3U)                                          
+#define EXTI_RTSR1_RT3_Msk       (0x1U << EXTI_RTSR1_RT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_RT4_Pos       (4U)                                          
+#define EXTI_RTSR1_RT4_Msk       (0x1U << EXTI_RTSR1_RT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_RT5_Pos       (5U)                                          
+#define EXTI_RTSR1_RT5_Msk       (0x1U << EXTI_RTSR1_RT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_RT6_Pos       (6U)                                          
+#define EXTI_RTSR1_RT6_Msk       (0x1U << EXTI_RTSR1_RT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_RT7_Pos       (7U)                                          
+#define EXTI_RTSR1_RT7_Msk       (0x1U << EXTI_RTSR1_RT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_RT8_Pos       (8U)                                          
+#define EXTI_RTSR1_RT8_Msk       (0x1U << EXTI_RTSR1_RT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_RT9_Pos       (9U)                                          
+#define EXTI_RTSR1_RT9_Msk       (0x1U << EXTI_RTSR1_RT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_RT10_Pos      (10U)                                         
+#define EXTI_RTSR1_RT10_Msk      (0x1U << EXTI_RTSR1_RT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_RT11_Pos      (11U)                                         
+#define EXTI_RTSR1_RT11_Msk      (0x1U << EXTI_RTSR1_RT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_RT12_Pos      (12U)                                         
+#define EXTI_RTSR1_RT12_Msk      (0x1U << EXTI_RTSR1_RT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_RT13_Pos      (13U)                                         
+#define EXTI_RTSR1_RT13_Msk      (0x1U << EXTI_RTSR1_RT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_RT14_Pos      (14U)                                         
+#define EXTI_RTSR1_RT14_Msk      (0x1U << EXTI_RTSR1_RT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_RT15_Pos      (15U)                                         
+#define EXTI_RTSR1_RT15_Msk      (0x1U << EXTI_RTSR1_RT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_RT16_Pos      (16U)                                         
+#define EXTI_RTSR1_RT16_Msk      (0x1U << EXTI_RTSR1_RT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_RT18_Pos      (18U)                                         
+#define EXTI_RTSR1_RT18_Msk      (0x1U << EXTI_RTSR1_RT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_RT19_Pos      (19U)                                         
+#define EXTI_RTSR1_RT19_Msk      (0x1U << EXTI_RTSR1_RT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_RT20_Pos      (20U)                                         
+#define EXTI_RTSR1_RT20_Msk      (0x1U << EXTI_RTSR1_RT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_RT21_Pos      (21U)                                         
+#define EXTI_RTSR1_RT21_Msk      (0x1U << EXTI_RTSR1_RT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR1_RT22_Pos      (22U)                                         
+#define EXTI_RTSR1_RT22_Msk      (0x1U << EXTI_RTSR1_RT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR1 register  ******************/
+#define EXTI_FTSR1_FT0_Pos       (0U)                                          
+#define EXTI_FTSR1_FT0_Msk       (0x1U << EXTI_FTSR1_FT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_FT1_Pos       (1U)                                          
+#define EXTI_FTSR1_FT1_Msk       (0x1U << EXTI_FTSR1_FT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_FT2_Pos       (2U)                                          
+#define EXTI_FTSR1_FT2_Msk       (0x1U << EXTI_FTSR1_FT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_FT3_Pos       (3U)                                          
+#define EXTI_FTSR1_FT3_Msk       (0x1U << EXTI_FTSR1_FT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_FT4_Pos       (4U)                                          
+#define EXTI_FTSR1_FT4_Msk       (0x1U << EXTI_FTSR1_FT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_FT5_Pos       (5U)                                          
+#define EXTI_FTSR1_FT5_Msk       (0x1U << EXTI_FTSR1_FT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_FT6_Pos       (6U)                                          
+#define EXTI_FTSR1_FT6_Msk       (0x1U << EXTI_FTSR1_FT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_FT7_Pos       (7U)                                          
+#define EXTI_FTSR1_FT7_Msk       (0x1U << EXTI_FTSR1_FT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_FT8_Pos       (8U)                                          
+#define EXTI_FTSR1_FT8_Msk       (0x1U << EXTI_FTSR1_FT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_FT9_Pos       (9U)                                          
+#define EXTI_FTSR1_FT9_Msk       (0x1U << EXTI_FTSR1_FT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_FT10_Pos      (10U)                                         
+#define EXTI_FTSR1_FT10_Msk      (0x1U << EXTI_FTSR1_FT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_FT11_Pos      (11U)                                         
+#define EXTI_FTSR1_FT11_Msk      (0x1U << EXTI_FTSR1_FT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_FT12_Pos      (12U)                                         
+#define EXTI_FTSR1_FT12_Msk      (0x1U << EXTI_FTSR1_FT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_FT13_Pos      (13U)                                         
+#define EXTI_FTSR1_FT13_Msk      (0x1U << EXTI_FTSR1_FT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_FT14_Pos      (14U)                                         
+#define EXTI_FTSR1_FT14_Msk      (0x1U << EXTI_FTSR1_FT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_FT15_Pos      (15U)                                         
+#define EXTI_FTSR1_FT15_Msk      (0x1U << EXTI_FTSR1_FT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_FT16_Pos      (16U)                                         
+#define EXTI_FTSR1_FT16_Msk      (0x1U << EXTI_FTSR1_FT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_FT18_Pos      (18U)                                         
+#define EXTI_FTSR1_FT18_Msk      (0x1U << EXTI_FTSR1_FT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_FT19_Pos      (19U)                                         
+#define EXTI_FTSR1_FT19_Msk      (0x1U << EXTI_FTSR1_FT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_FT20_Pos      (20U)                                         
+#define EXTI_FTSR1_FT20_Msk      (0x1U << EXTI_FTSR1_FT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_FT21_Pos      (21U)                                         
+#define EXTI_FTSR1_FT21_Msk      (0x1U << EXTI_FTSR1_FT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR1_FT22_Pos      (22U)                                         
+#define EXTI_FTSR1_FT22_Msk      (0x1U << EXTI_FTSR1_FT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER1 register  *****************/
+#define EXTI_SWIER1_SWI0_Pos     (0U)                                          
+#define EXTI_SWIER1_SWI0_Msk     (0x1U << EXTI_SWIER1_SWI0_Pos)                /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos     (1U)                                          
+#define EXTI_SWIER1_SWI1_Msk     (0x1U << EXTI_SWIER1_SWI1_Pos)                /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos     (2U)                                          
+#define EXTI_SWIER1_SWI2_Msk     (0x1U << EXTI_SWIER1_SWI2_Pos)                /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos     (3U)                                          
+#define EXTI_SWIER1_SWI3_Msk     (0x1U << EXTI_SWIER1_SWI3_Pos)                /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos     (4U)                                          
+#define EXTI_SWIER1_SWI4_Msk     (0x1U << EXTI_SWIER1_SWI4_Pos)                /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos     (5U)                                          
+#define EXTI_SWIER1_SWI5_Msk     (0x1U << EXTI_SWIER1_SWI5_Pos)                /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos     (6U)                                          
+#define EXTI_SWIER1_SWI6_Msk     (0x1U << EXTI_SWIER1_SWI6_Pos)                /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos     (7U)                                          
+#define EXTI_SWIER1_SWI7_Msk     (0x1U << EXTI_SWIER1_SWI7_Pos)                /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos     (8U)                                          
+#define EXTI_SWIER1_SWI8_Msk     (0x1U << EXTI_SWIER1_SWI8_Pos)                /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos     (9U)                                          
+#define EXTI_SWIER1_SWI9_Msk     (0x1U << EXTI_SWIER1_SWI9_Pos)                /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos    (10U)                                         
+#define EXTI_SWIER1_SWI10_Msk    (0x1U << EXTI_SWIER1_SWI10_Pos)               /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos    (11U)                                         
+#define EXTI_SWIER1_SWI11_Msk    (0x1U << EXTI_SWIER1_SWI11_Pos)               /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos    (12U)                                         
+#define EXTI_SWIER1_SWI12_Msk    (0x1U << EXTI_SWIER1_SWI12_Pos)               /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos    (13U)                                         
+#define EXTI_SWIER1_SWI13_Msk    (0x1U << EXTI_SWIER1_SWI13_Pos)               /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos    (14U)                                         
+#define EXTI_SWIER1_SWI14_Msk    (0x1U << EXTI_SWIER1_SWI14_Pos)               /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos    (15U)                                         
+#define EXTI_SWIER1_SWI15_Msk    (0x1U << EXTI_SWIER1_SWI15_Pos)               /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI16_Pos    (16U)                                         
+#define EXTI_SWIER1_SWI16_Msk    (0x1U << EXTI_SWIER1_SWI16_Pos)               /*!< 0x00010000 */
+#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWI18_Pos    (18U)                                         
+#define EXTI_SWIER1_SWI18_Msk    (0x1U << EXTI_SWIER1_SWI18_Pos)               /*!< 0x00040000 */
+#define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWI19_Pos    (19U)                                         
+#define EXTI_SWIER1_SWI19_Msk    (0x1U << EXTI_SWIER1_SWI19_Pos)               /*!< 0x00080000 */
+#define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWI20_Pos    (20U)                                         
+#define EXTI_SWIER1_SWI20_Msk    (0x1U << EXTI_SWIER1_SWI20_Pos)               /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos    (21U)                                         
+#define EXTI_SWIER1_SWI21_Msk    (0x1U << EXTI_SWIER1_SWI21_Pos)               /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER1_SWI22_Pos    (22U)                                         
+#define EXTI_SWIER1_SWI22_Msk    (0x1U << EXTI_SWIER1_SWI22_Pos)               /*!< 0x00400000 */
+#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR1 register  *******************/
+#define EXTI_PR1_PIF0_Pos        (0U)                                          
+#define EXTI_PR1_PIF0_Msk        (0x1U << EXTI_PR1_PIF0_Pos)                   /*!< 0x00000001 */
+#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
+#define EXTI_PR1_PIF1_Pos        (1U)                                          
+#define EXTI_PR1_PIF1_Msk        (0x1U << EXTI_PR1_PIF1_Pos)                   /*!< 0x00000002 */
+#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
+#define EXTI_PR1_PIF2_Pos        (2U)                                          
+#define EXTI_PR1_PIF2_Msk        (0x1U << EXTI_PR1_PIF2_Pos)                   /*!< 0x00000004 */
+#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
+#define EXTI_PR1_PIF3_Pos        (3U)                                          
+#define EXTI_PR1_PIF3_Msk        (0x1U << EXTI_PR1_PIF3_Pos)                   /*!< 0x00000008 */
+#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
+#define EXTI_PR1_PIF4_Pos        (4U)                                          
+#define EXTI_PR1_PIF4_Msk        (0x1U << EXTI_PR1_PIF4_Pos)                   /*!< 0x00000010 */
+#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
+#define EXTI_PR1_PIF5_Pos        (5U)                                          
+#define EXTI_PR1_PIF5_Msk        (0x1U << EXTI_PR1_PIF5_Pos)                   /*!< 0x00000020 */
+#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
+#define EXTI_PR1_PIF6_Pos        (6U)                                          
+#define EXTI_PR1_PIF6_Msk        (0x1U << EXTI_PR1_PIF6_Pos)                   /*!< 0x00000040 */
+#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
+#define EXTI_PR1_PIF7_Pos        (7U)                                          
+#define EXTI_PR1_PIF7_Msk        (0x1U << EXTI_PR1_PIF7_Pos)                   /*!< 0x00000080 */
+#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
+#define EXTI_PR1_PIF8_Pos        (8U)                                          
+#define EXTI_PR1_PIF8_Msk        (0x1U << EXTI_PR1_PIF8_Pos)                   /*!< 0x00000100 */
+#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
+#define EXTI_PR1_PIF9_Pos        (9U)                                          
+#define EXTI_PR1_PIF9_Msk        (0x1U << EXTI_PR1_PIF9_Pos)                   /*!< 0x00000200 */
+#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
+#define EXTI_PR1_PIF10_Pos       (10U)                                         
+#define EXTI_PR1_PIF10_Msk       (0x1U << EXTI_PR1_PIF10_Pos)                  /*!< 0x00000400 */
+#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
+#define EXTI_PR1_PIF11_Pos       (11U)                                         
+#define EXTI_PR1_PIF11_Msk       (0x1U << EXTI_PR1_PIF11_Pos)                  /*!< 0x00000800 */
+#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
+#define EXTI_PR1_PIF12_Pos       (12U)                                         
+#define EXTI_PR1_PIF12_Msk       (0x1U << EXTI_PR1_PIF12_Pos)                  /*!< 0x00001000 */
+#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
+#define EXTI_PR1_PIF13_Pos       (13U)                                         
+#define EXTI_PR1_PIF13_Msk       (0x1U << EXTI_PR1_PIF13_Pos)                  /*!< 0x00002000 */
+#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
+#define EXTI_PR1_PIF14_Pos       (14U)                                         
+#define EXTI_PR1_PIF14_Msk       (0x1U << EXTI_PR1_PIF14_Pos)                  /*!< 0x00004000 */
+#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
+#define EXTI_PR1_PIF15_Pos       (15U)                                         
+#define EXTI_PR1_PIF15_Msk       (0x1U << EXTI_PR1_PIF15_Pos)                  /*!< 0x00008000 */
+#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
+#define EXTI_PR1_PIF16_Pos       (16U)                                         
+#define EXTI_PR1_PIF16_Msk       (0x1U << EXTI_PR1_PIF16_Pos)                  /*!< 0x00010000 */
+#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
+#define EXTI_PR1_PIF18_Pos       (18U)                                         
+#define EXTI_PR1_PIF18_Msk       (0x1U << EXTI_PR1_PIF18_Pos)                  /*!< 0x00040000 */
+#define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
+#define EXTI_PR1_PIF19_Pos       (19U)                                         
+#define EXTI_PR1_PIF19_Msk       (0x1U << EXTI_PR1_PIF19_Pos)                  /*!< 0x00080000 */
+#define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
+#define EXTI_PR1_PIF20_Pos       (20U)                                         
+#define EXTI_PR1_PIF20_Msk       (0x1U << EXTI_PR1_PIF20_Pos)                  /*!< 0x00100000 */
+#define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
+#define EXTI_PR1_PIF21_Pos       (21U)                                         
+#define EXTI_PR1_PIF21_Msk       (0x1U << EXTI_PR1_PIF21_Pos)                  /*!< 0x00200000 */
+#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
+#define EXTI_PR1_PIF22_Pos       (22U)                                         
+#define EXTI_PR1_PIF22_Msk       (0x1U << EXTI_PR1_PIF22_Pos)                  /*!< 0x00400000 */
+#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos       (0U)                                          
+#define EXTI_IMR2_IM32_Msk       (0x1U << EXTI_IMR2_IM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos       (1U)                                          
+#define EXTI_IMR2_IM33_Msk       (0x1U << EXTI_IMR2_IM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos       (2U)                                          
+#define EXTI_IMR2_IM34_Msk       (0x1U << EXTI_IMR2_IM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos       (3U)                                          
+#define EXTI_IMR2_IM35_Msk       (0x1U << EXTI_IMR2_IM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos       (4U)                                          
+#define EXTI_IMR2_IM36_Msk       (0x1U << EXTI_IMR2_IM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos       (5U)                                          
+#define EXTI_IMR2_IM37_Msk       (0x1U << EXTI_IMR2_IM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos       (6U)                                          
+#define EXTI_IMR2_IM38_Msk       (0x1U << EXTI_IMR2_IM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos       (7U)                                          
+#define EXTI_IMR2_IM39_Msk       (0x1U << EXTI_IMR2_IM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM_Pos         (0U)                                          
+#define EXTI_IMR2_IM_Msk         (0xFFU << EXTI_IMR2_IM_Pos)                   /*!< 0x000000FF */
+#define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos       (0U)                                          
+#define EXTI_EMR2_EM32_Msk       (0x1U << EXTI_EMR2_EM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos       (1U)                                          
+#define EXTI_EMR2_EM33_Msk       (0x1U << EXTI_EMR2_EM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos       (2U)                                          
+#define EXTI_EMR2_EM34_Msk       (0x1U << EXTI_EMR2_EM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos       (3U)                                          
+#define EXTI_EMR2_EM35_Msk       (0x1U << EXTI_EMR2_EM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos       (4U)                                          
+#define EXTI_EMR2_EM36_Msk       (0x1U << EXTI_EMR2_EM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos       (5U)                                          
+#define EXTI_EMR2_EM37_Msk       (0x1U << EXTI_EMR2_EM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos       (6U)                                          
+#define EXTI_EMR2_EM38_Msk       (0x1U << EXTI_EMR2_EM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos       (7U)                                          
+#define EXTI_EMR2_EM39_Msk       (0x1U << EXTI_EMR2_EM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
+#define EXTI_EMR2_EM_Pos         (0U)                                          
+#define EXTI_EMR2_EM_Msk         (0xFFU << EXTI_EMR2_EM_Pos)                   /*!< 0x000000FF */
+#define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
+
+/******************  Bit definition for EXTI_RTSR2 register  ******************/
+#define EXTI_RTSR2_RT35_Pos      (3U)                                          
+#define EXTI_RTSR2_RT35_Msk      (0x1U << EXTI_RTSR2_RT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */
+#define EXTI_RTSR2_RT36_Pos      (4U)                                          
+#define EXTI_RTSR2_RT36_Msk      (0x1U << EXTI_RTSR2_RT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_RTSR2_RT36          EXTI_RTSR2_RT36_Msk                           /*!< Rising trigger event configuration bit of line 36 */
+#define EXTI_RTSR2_RT37_Pos      (5U)                                          
+#define EXTI_RTSR2_RT37_Msk      (0x1U << EXTI_RTSR2_RT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */
+#define EXTI_RTSR2_RT38_Pos      (6U)                                          
+#define EXTI_RTSR2_RT38_Msk      (0x1U << EXTI_RTSR2_RT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_FTSR2 register  ******************/
+#define EXTI_FTSR2_FT35_Pos      (3U)                                          
+#define EXTI_FTSR2_FT35_Msk      (0x1U << EXTI_FTSR2_FT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */
+#define EXTI_FTSR2_FT36_Pos      (4U)                                          
+#define EXTI_FTSR2_FT36_Msk      (0x1U << EXTI_FTSR2_FT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_FTSR2_FT36          EXTI_FTSR2_FT36_Msk                           /*!< Falling trigger event configuration bit of line 36 */
+#define EXTI_FTSR2_FT37_Pos      (5U)                                          
+#define EXTI_FTSR2_FT37_Msk      (0x1U << EXTI_FTSR2_FT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */
+#define EXTI_FTSR2_FT38_Pos      (6U)                                          
+#define EXTI_FTSR2_FT38_Msk      (0x1U << EXTI_FTSR2_FT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_SWIER2 register  *****************/
+#define EXTI_SWIER2_SWI35_Pos    (3U)                                          
+#define EXTI_SWIER2_SWI35_Msk    (0x1U << EXTI_SWIER2_SWI35_Pos)               /*!< 0x00000008 */
+#define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */
+#define EXTI_SWIER2_SWI36_Pos    (4U)                                          
+#define EXTI_SWIER2_SWI36_Msk    (0x1U << EXTI_SWIER2_SWI36_Pos)               /*!< 0x00000010 */
+#define EXTI_SWIER2_SWI36        EXTI_SWIER2_SWI36_Msk                         /*!< Software Interrupt on line 36 */
+#define EXTI_SWIER2_SWI37_Pos    (5U)                                          
+#define EXTI_SWIER2_SWI37_Msk    (0x1U << EXTI_SWIER2_SWI37_Pos)               /*!< 0x00000020 */
+#define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */
+#define EXTI_SWIER2_SWI38_Pos    (6U)                                          
+#define EXTI_SWIER2_SWI38_Msk    (0x1U << EXTI_SWIER2_SWI38_Pos)               /*!< 0x00000040 */
+#define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
+
+/*******************  Bit definition for EXTI_PR2 register  *******************/
+#define EXTI_PR2_PIF35_Pos       (3U)                                          
+#define EXTI_PR2_PIF35_Msk       (0x1U << EXTI_PR2_PIF35_Pos)                  /*!< 0x00000008 */
+#define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */
+#define EXTI_PR2_PIF36_Pos       (4U)                                          
+#define EXTI_PR2_PIF36_Msk       (0x1U << EXTI_PR2_PIF36_Pos)                  /*!< 0x00000010 */
+#define EXTI_PR2_PIF36           EXTI_PR2_PIF36_Msk                            /*!< Pending bit for line 36 */
+#define EXTI_PR2_PIF37_Pos       (5U)                                          
+#define EXTI_PR2_PIF37_Msk       (0x1U << EXTI_PR2_PIF37_Pos)                  /*!< 0x00000020 */
+#define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */
+#define EXTI_PR2_PIF38_Pos       (6U)                                          
+#define EXTI_PR2_PIF38_Msk       (0x1U << EXTI_PR2_PIF38_Pos)                  /*!< 0x00000040 */
+#define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos             (0U)                                 
+#define FLASH_ACR_LATENCY_Msk             (0x7U << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk                
+#define FLASH_ACR_LATENCY_0WS             (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS             (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS             (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS             (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS             (0x00000004U)
+#define FLASH_ACR_PRFTEN_Pos              (8U)                                 
+#define FLASH_ACR_PRFTEN_Msk              (0x1U << FLASH_ACR_PRFTEN_Pos)       /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk                 
+#define FLASH_ACR_ICEN_Pos                (9U)                                 
+#define FLASH_ACR_ICEN_Msk                (0x1U << FLASH_ACR_ICEN_Pos)         /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk                   
+#define FLASH_ACR_DCEN_Pos                (10U)                                
+#define FLASH_ACR_DCEN_Msk                (0x1U << FLASH_ACR_DCEN_Pos)         /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk                   
+#define FLASH_ACR_ICRST_Pos               (11U)                                
+#define FLASH_ACR_ICRST_Msk               (0x1U << FLASH_ACR_ICRST_Pos)        /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk                  
+#define FLASH_ACR_DCRST_Pos               (12U)                                
+#define FLASH_ACR_DCRST_Msk               (0x1U << FLASH_ACR_DCRST_Pos)        /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk                  
+#define FLASH_ACR_RUN_PD_Pos              (13U)                                
+#define FLASH_ACR_RUN_PD_Msk              (0x1U << FLASH_ACR_RUN_PD_Pos)       /*!< 0x00002000 */
+#define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
+#define FLASH_ACR_SLEEP_PD_Pos            (14U)                                
+#define FLASH_ACR_SLEEP_PD_Msk            (0x1U << FLASH_ACR_SLEEP_PD_Pos)     /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos                  (0U)                                 
+#define FLASH_SR_EOP_Msk                  (0x1U << FLASH_SR_EOP_Pos)           /*!< 0x00000001 */
+#define FLASH_SR_EOP                      FLASH_SR_EOP_Msk                     
+#define FLASH_SR_OPERR_Pos                (1U)                                 
+#define FLASH_SR_OPERR_Msk                (0x1U << FLASH_SR_OPERR_Pos)         /*!< 0x00000002 */
+#define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk                   
+#define FLASH_SR_PROGERR_Pos              (3U)                                 
+#define FLASH_SR_PROGERR_Msk              (0x1U << FLASH_SR_PROGERR_Pos)       /*!< 0x00000008 */
+#define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk                 
+#define FLASH_SR_WRPERR_Pos               (4U)                                 
+#define FLASH_SR_WRPERR_Msk               (0x1U << FLASH_SR_WRPERR_Pos)        /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk                  
+#define FLASH_SR_PGAERR_Pos               (5U)                                 
+#define FLASH_SR_PGAERR_Msk               (0x1U << FLASH_SR_PGAERR_Pos)        /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk                  
+#define FLASH_SR_SIZERR_Pos               (6U)                                 
+#define FLASH_SR_SIZERR_Msk               (0x1U << FLASH_SR_SIZERR_Pos)        /*!< 0x00000040 */
+#define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk                  
+#define FLASH_SR_PGSERR_Pos               (7U)                                 
+#define FLASH_SR_PGSERR_Msk               (0x1U << FLASH_SR_PGSERR_Pos)        /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk                  
+#define FLASH_SR_MISERR_Pos               (8U)                                 
+#define FLASH_SR_MISERR_Msk               (0x1U << FLASH_SR_MISERR_Pos)        /*!< 0x00000100 */
+#define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk                  
+#define FLASH_SR_FASTERR_Pos              (9U)                                 
+#define FLASH_SR_FASTERR_Msk              (0x1U << FLASH_SR_FASTERR_Pos)       /*!< 0x00000200 */
+#define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk                 
+#define FLASH_SR_RDERR_Pos                (14U)                                
+#define FLASH_SR_RDERR_Msk                (0x1U << FLASH_SR_RDERR_Pos)         /*!< 0x00004000 */
+#define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk                   
+#define FLASH_SR_OPTVERR_Pos              (15U)                                
+#define FLASH_SR_OPTVERR_Msk              (0x1U << FLASH_SR_OPTVERR_Pos)       /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk                 
+#define FLASH_SR_BSY_Pos                  (16U)                                
+#define FLASH_SR_BSY_Msk                  (0x1U << FLASH_SR_BSY_Pos)           /*!< 0x00010000 */
+#define FLASH_SR_BSY                      FLASH_SR_BSY_Msk                     
+#define FLASH_SR_PEMPTY_Pos               (17U)                                
+#define FLASH_SR_PEMPTY_Msk               (0x1U << FLASH_SR_PEMPTY_Pos)        /*!< 0x00020000 */
+#define FLASH_SR_PEMPTY                   FLASH_SR_PEMPTY_Msk                  
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                   (0U)                                 
+#define FLASH_CR_PG_Msk                   (0x1U << FLASH_CR_PG_Pos)            /*!< 0x00000001 */
+#define FLASH_CR_PG                       FLASH_CR_PG_Msk                      
+#define FLASH_CR_PER_Pos                  (1U)                                 
+#define FLASH_CR_PER_Msk                  (0x1U << FLASH_CR_PER_Pos)           /*!< 0x00000002 */
+#define FLASH_CR_PER                      FLASH_CR_PER_Msk                     
+#define FLASH_CR_MER1_Pos                 (2U)                                 
+#define FLASH_CR_MER1_Msk                 (0x1U << FLASH_CR_MER1_Pos)          /*!< 0x00000004 */
+#define FLASH_CR_MER1                     FLASH_CR_MER1_Msk                    
+#define FLASH_CR_PNB_Pos                  (3U)                                 
+#define FLASH_CR_PNB_Msk                  (0xFFU << FLASH_CR_PNB_Pos)          /*!< 0x000007F8 */
+#define FLASH_CR_PNB                      FLASH_CR_PNB_Msk                     
+#define FLASH_CR_STRT_Pos                 (16U)                                
+#define FLASH_CR_STRT_Msk                 (0x1U << FLASH_CR_STRT_Pos)          /*!< 0x00010000 */
+#define FLASH_CR_STRT                     FLASH_CR_STRT_Msk                    
+#define FLASH_CR_OPTSTRT_Pos              (17U)                                
+#define FLASH_CR_OPTSTRT_Msk              (0x1U << FLASH_CR_OPTSTRT_Pos)       /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk                 
+#define FLASH_CR_FSTPG_Pos                (18U)                                
+#define FLASH_CR_FSTPG_Msk                (0x1U << FLASH_CR_FSTPG_Pos)         /*!< 0x00040000 */
+#define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk                   
+#define FLASH_CR_EOPIE_Pos                (24U)                                
+#define FLASH_CR_EOPIE_Msk                (0x1U << FLASH_CR_EOPIE_Pos)         /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk                   
+#define FLASH_CR_ERRIE_Pos                (25U)                                
+#define FLASH_CR_ERRIE_Msk                (0x1U << FLASH_CR_ERRIE_Pos)         /*!< 0x02000000 */
+#define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk                   
+#define FLASH_CR_RDERRIE_Pos              (26U)                                
+#define FLASH_CR_RDERRIE_Msk              (0x1U << FLASH_CR_RDERRIE_Pos)       /*!< 0x04000000 */
+#define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk                 
+#define FLASH_CR_OBL_LAUNCH_Pos           (27U)                                
+#define FLASH_CR_OBL_LAUNCH_Msk           (0x1U << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk              
+#define FLASH_CR_OPTLOCK_Pos              (30U)                                
+#define FLASH_CR_OPTLOCK_Msk              (0x1U << FLASH_CR_OPTLOCK_Pos)       /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk                 
+#define FLASH_CR_LOCK_Pos                 (31U)                                
+#define FLASH_CR_LOCK_Msk                 (0x1U << FLASH_CR_LOCK_Pos)          /*!< 0x80000000 */
+#define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk                    
+
+/*******************  Bits definition for FLASH_ECCR register  ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos           (0U)                                 
+#define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
+#define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk              
+#define FLASH_ECCR_SYSF_ECC_Pos           (20U)                                
+#define FLASH_ECCR_SYSF_ECC_Msk           (0x1U << FLASH_ECCR_SYSF_ECC_Pos)    /*!< 0x00100000 */
+#define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk              
+#define FLASH_ECCR_ECCIE_Pos              (24U)                                
+#define FLASH_ECCR_ECCIE_Msk              (0x1U << FLASH_ECCR_ECCIE_Pos)       /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk                 
+#define FLASH_ECCR_ECCC_Pos               (30U)                                
+#define FLASH_ECCR_ECCC_Msk               (0x1U << FLASH_ECCR_ECCC_Pos)        /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk                  
+#define FLASH_ECCR_ECCD_Pos               (31U)                                
+#define FLASH_ECCR_ECCD_Msk               (0x1U << FLASH_ECCR_ECCD_Pos)        /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk                  
+
+/*******************  Bits definition for FLASH_OPTR register  ***************/
+#define FLASH_OPTR_RDP_Pos                (0U)                                 
+#define FLASH_OPTR_RDP_Msk                (0xFFU << FLASH_OPTR_RDP_Pos)        /*!< 0x000000FF */
+#define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk                   
+#define FLASH_OPTR_BOR_LEV_Pos            (8U)                                 
+#define FLASH_OPTR_BOR_LEV_Msk            (0x7U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk               
+#define FLASH_OPTR_BOR_LEV_0              (0x0U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000000 */
+#define FLASH_OPTR_BOR_LEV_1              (0x1U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_2              (0x2U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_3              (0x3U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000300 */
+#define FLASH_OPTR_BOR_LEV_4              (0x4U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos          (12U)                                
+#define FLASH_OPTR_nRST_STOP_Msk          (0x1U << FLASH_OPTR_nRST_STOP_Pos)   /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk             
+#define FLASH_OPTR_nRST_STDBY_Pos         (13U)                                
+#define FLASH_OPTR_nRST_STDBY_Msk         (0x1U << FLASH_OPTR_nRST_STDBY_Pos)  /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk            
+#define FLASH_OPTR_nRST_SHDW_Pos          (14U)                                
+#define FLASH_OPTR_nRST_SHDW_Msk          (0x1U << FLASH_OPTR_nRST_SHDW_Pos)   /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk             
+#define FLASH_OPTR_IWDG_SW_Pos            (16U)                                
+#define FLASH_OPTR_IWDG_SW_Msk            (0x1U << FLASH_OPTR_IWDG_SW_Pos)     /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk               
+#define FLASH_OPTR_IWDG_STOP_Pos          (17U)                                
+#define FLASH_OPTR_IWDG_STOP_Msk          (0x1U << FLASH_OPTR_IWDG_STOP_Pos)   /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk             
+#define FLASH_OPTR_IWDG_STDBY_Pos         (18U)                                
+#define FLASH_OPTR_IWDG_STDBY_Msk         (0x1U << FLASH_OPTR_IWDG_STDBY_Pos)  /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk            
+#define FLASH_OPTR_WWDG_SW_Pos            (19U)                                
+#define FLASH_OPTR_WWDG_SW_Msk            (0x1U << FLASH_OPTR_WWDG_SW_Pos)     /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk               
+#define FLASH_OPTR_nBOOT1_Pos             (23U)                                
+#define FLASH_OPTR_nBOOT1_Msk             (0x1U << FLASH_OPTR_nBOOT1_Pos)      /*!< 0x00800000 */
+#define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk                
+#define FLASH_OPTR_SRAM2_PE_Pos           (24U)                                
+#define FLASH_OPTR_SRAM2_PE_Msk           (0x1U << FLASH_OPTR_SRAM2_PE_Pos)    /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk              
+#define FLASH_OPTR_SRAM2_RST_Pos          (25U)                                
+#define FLASH_OPTR_SRAM2_RST_Msk          (0x1U << FLASH_OPTR_SRAM2_RST_Pos)   /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk             
+#define FLASH_OPTR_nSWBOOT0_Pos           (26U)                                
+#define FLASH_OPTR_nSWBOOT0_Msk           (0x1U << FLASH_OPTR_nSWBOOT0_Pos)    /*!< 0x04000000 */
+#define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk              
+#define FLASH_OPTR_nBOOT0_Pos             (27U)                                
+#define FLASH_OPTR_nBOOT0_Msk             (0x1U << FLASH_OPTR_nBOOT0_Pos)      /*!< 0x08000000 */
+#define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk                
+
+/******************  Bits definition for FLASH_PCROP1SR register  **********/
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)                                 
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk       
+
+/******************  Bits definition for FLASH_PCROP1ER register  ***********/
+#define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)                                 
+#define FLASH_PCROP1ER_PCROP1_END_Msk     (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk        
+#define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)                                
+#define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
+#define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk         
+
+/******************  Bits definition for FLASH_WRP1AR register  ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)                                 
+#define FLASH_WRP1AR_WRP1A_STRT_Msk       (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk          
+#define FLASH_WRP1AR_WRP1A_END_Pos        (16U)                                
+#define FLASH_WRP1AR_WRP1A_END_Msk        (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk           
+
+/******************  Bits definition for FLASH_WRPB1R register  ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)                                 
+#define FLASH_WRP1BR_WRP1B_STRT_Msk       (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk          
+#define FLASH_WRP1BR_WRP1B_END_Pos        (16U)                                
+#define FLASH_WRP1BR_WRP1B_END_Msk        (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk           
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)                                    
+#define GPIO_MODER_MODE0_Msk           (0x3U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk                    
+#define GPIO_MODER_MODE0_0             (0x1U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)                                    
+#define GPIO_MODER_MODE1_Msk           (0x3U << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk                    
+#define GPIO_MODER_MODE1_0             (0x1U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)                                    
+#define GPIO_MODER_MODE2_Msk           (0x3U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk                    
+#define GPIO_MODER_MODE2_0             (0x1U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)                                    
+#define GPIO_MODER_MODE3_Msk           (0x3U << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk                    
+#define GPIO_MODER_MODE3_0             (0x1U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)                                    
+#define GPIO_MODER_MODE4_Msk           (0x3U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk                    
+#define GPIO_MODER_MODE4_0             (0x1U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)                                   
+#define GPIO_MODER_MODE5_Msk           (0x3U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk                    
+#define GPIO_MODER_MODE5_0             (0x1U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)                                   
+#define GPIO_MODER_MODE6_Msk           (0x3U << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk                    
+#define GPIO_MODER_MODE6_0             (0x1U << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2U << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)                                   
+#define GPIO_MODER_MODE7_Msk           (0x3U << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk                    
+#define GPIO_MODER_MODE7_0             (0x1U << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2U << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)                                   
+#define GPIO_MODER_MODE8_Msk           (0x3U << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk                    
+#define GPIO_MODER_MODE8_0             (0x1U << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2U << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)                                   
+#define GPIO_MODER_MODE9_Msk           (0x3U << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk                    
+#define GPIO_MODER_MODE9_0             (0x1U << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2U << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)                                   
+#define GPIO_MODER_MODE10_Msk          (0x3U << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk                   
+#define GPIO_MODER_MODE10_0            (0x1U << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2U << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)                                   
+#define GPIO_MODER_MODE11_Msk          (0x3U << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk                   
+#define GPIO_MODER_MODE11_0            (0x1U << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2U << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)                                   
+#define GPIO_MODER_MODE12_Msk          (0x3U << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk                   
+#define GPIO_MODER_MODE12_0            (0x1U << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2U << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)                                   
+#define GPIO_MODER_MODE13_Msk          (0x3U << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk                   
+#define GPIO_MODER_MODE13_0            (0x1U << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2U << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)                                   
+#define GPIO_MODER_MODE14_Msk          (0x3U << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk                   
+#define GPIO_MODER_MODE14_0            (0x1U << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2U << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)                                   
+#define GPIO_MODER_MODE15_Msk          (0x3U << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk                   
+#define GPIO_MODER_MODE15_0            (0x1U << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2U << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
+#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
+#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
+#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
+#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
+#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
+#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
+#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
+#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
+#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
+#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
+#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
+#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
+#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
+#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
+#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
+#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
+#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
+#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
+#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
+#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
+#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
+#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
+#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
+#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
+#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
+#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
+#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
+#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
+#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
+#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
+#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
+#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
+#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
+#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
+#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
+#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
+#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
+#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
+#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
+#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
+#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
+#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
+#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
+#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
+#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
+#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
+#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)                                    
+#define GPIO_OTYPER_OT0_Msk            (0x1U << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk                     
+#define GPIO_OTYPER_OT1_Pos            (1U)                                    
+#define GPIO_OTYPER_OT1_Msk            (0x1U << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk                     
+#define GPIO_OTYPER_OT2_Pos            (2U)                                    
+#define GPIO_OTYPER_OT2_Msk            (0x1U << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk                     
+#define GPIO_OTYPER_OT3_Pos            (3U)                                    
+#define GPIO_OTYPER_OT3_Msk            (0x1U << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk                     
+#define GPIO_OTYPER_OT4_Pos            (4U)                                    
+#define GPIO_OTYPER_OT4_Msk            (0x1U << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk                     
+#define GPIO_OTYPER_OT5_Pos            (5U)                                    
+#define GPIO_OTYPER_OT5_Msk            (0x1U << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk                     
+#define GPIO_OTYPER_OT6_Pos            (6U)                                    
+#define GPIO_OTYPER_OT6_Msk            (0x1U << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk                     
+#define GPIO_OTYPER_OT7_Pos            (7U)                                    
+#define GPIO_OTYPER_OT7_Msk            (0x1U << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk                     
+#define GPIO_OTYPER_OT8_Pos            (8U)                                    
+#define GPIO_OTYPER_OT8_Msk            (0x1U << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk                     
+#define GPIO_OTYPER_OT9_Pos            (9U)                                    
+#define GPIO_OTYPER_OT9_Msk            (0x1U << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk                     
+#define GPIO_OTYPER_OT10_Pos           (10U)                                   
+#define GPIO_OTYPER_OT10_Msk           (0x1U << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk                    
+#define GPIO_OTYPER_OT11_Pos           (11U)                                   
+#define GPIO_OTYPER_OT11_Msk           (0x1U << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk                    
+#define GPIO_OTYPER_OT12_Pos           (12U)                                   
+#define GPIO_OTYPER_OT12_Msk           (0x1U << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk                    
+#define GPIO_OTYPER_OT13_Pos           (13U)                                   
+#define GPIO_OTYPER_OT13_Msk           (0x1U << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk                    
+#define GPIO_OTYPER_OT14_Pos           (14U)                                   
+#define GPIO_OTYPER_OT14_Msk           (0x1U << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk                    
+#define GPIO_OTYPER_OT15_Pos           (15U)                                   
+#define GPIO_OTYPER_OT15_Msk           (0x1U << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk                    
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)                                    
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk                
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)                                    
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk                
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)                                    
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk                
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)                                    
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk                
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)                                    
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk                
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)                                   
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk                
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)                                   
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk                
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)                                   
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk                
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)                                   
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk                
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)                                   
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk                
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)                                   
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk               
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)                                   
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk               
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)                                   
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk               
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)                                   
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk               
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)                                   
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk               
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)                                   
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk               
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)                                    
+#define GPIO_PUPDR_PUPD0_Msk           (0x3U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk                    
+#define GPIO_PUPDR_PUPD0_0             (0x1U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)                                    
+#define GPIO_PUPDR_PUPD1_Msk           (0x3U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk                    
+#define GPIO_PUPDR_PUPD1_0             (0x1U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)                                    
+#define GPIO_PUPDR_PUPD2_Msk           (0x3U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk                    
+#define GPIO_PUPDR_PUPD2_0             (0x1U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)                                    
+#define GPIO_PUPDR_PUPD3_Msk           (0x3U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk                    
+#define GPIO_PUPDR_PUPD3_0             (0x1U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)                                    
+#define GPIO_PUPDR_PUPD4_Msk           (0x3U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk                    
+#define GPIO_PUPDR_PUPD4_0             (0x1U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)                                   
+#define GPIO_PUPDR_PUPD5_Msk           (0x3U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk                    
+#define GPIO_PUPDR_PUPD5_0             (0x1U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)                                   
+#define GPIO_PUPDR_PUPD6_Msk           (0x3U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk                    
+#define GPIO_PUPDR_PUPD6_0             (0x1U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)                                   
+#define GPIO_PUPDR_PUPD7_Msk           (0x3U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk                    
+#define GPIO_PUPDR_PUPD7_0             (0x1U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)                                   
+#define GPIO_PUPDR_PUPD8_Msk           (0x3U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk                    
+#define GPIO_PUPDR_PUPD8_0             (0x1U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)                                   
+#define GPIO_PUPDR_PUPD9_Msk           (0x3U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk                    
+#define GPIO_PUPDR_PUPD9_0             (0x1U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)                                   
+#define GPIO_PUPDR_PUPD10_Msk          (0x3U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk                   
+#define GPIO_PUPDR_PUPD10_0            (0x1U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)                                   
+#define GPIO_PUPDR_PUPD11_Msk          (0x3U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk                   
+#define GPIO_PUPDR_PUPD11_0            (0x1U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)                                   
+#define GPIO_PUPDR_PUPD12_Msk          (0x3U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk                   
+#define GPIO_PUPDR_PUPD12_0            (0x1U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)                                   
+#define GPIO_PUPDR_PUPD13_Msk          (0x3U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk                   
+#define GPIO_PUPDR_PUPD13_0            (0x1U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)                                   
+#define GPIO_PUPDR_PUPD14_Msk          (0x3U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk                   
+#define GPIO_PUPDR_PUPD14_0            (0x1U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)                                   
+#define GPIO_PUPDR_PUPD15_Msk          (0x3U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk                   
+#define GPIO_PUPDR_PUPD15_0            (0x1U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)                                    
+#define GPIO_IDR_ID0_Msk               (0x1U << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk                        
+#define GPIO_IDR_ID1_Pos               (1U)                                    
+#define GPIO_IDR_ID1_Msk               (0x1U << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk                        
+#define GPIO_IDR_ID2_Pos               (2U)                                    
+#define GPIO_IDR_ID2_Msk               (0x1U << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk                        
+#define GPIO_IDR_ID3_Pos               (3U)                                    
+#define GPIO_IDR_ID3_Msk               (0x1U << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk                        
+#define GPIO_IDR_ID4_Pos               (4U)                                    
+#define GPIO_IDR_ID4_Msk               (0x1U << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk                        
+#define GPIO_IDR_ID5_Pos               (5U)                                    
+#define GPIO_IDR_ID5_Msk               (0x1U << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk                        
+#define GPIO_IDR_ID6_Pos               (6U)                                    
+#define GPIO_IDR_ID6_Msk               (0x1U << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk                        
+#define GPIO_IDR_ID7_Pos               (7U)                                    
+#define GPIO_IDR_ID7_Msk               (0x1U << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk                        
+#define GPIO_IDR_ID8_Pos               (8U)                                    
+#define GPIO_IDR_ID8_Msk               (0x1U << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk                        
+#define GPIO_IDR_ID9_Pos               (9U)                                    
+#define GPIO_IDR_ID9_Msk               (0x1U << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk                        
+#define GPIO_IDR_ID10_Pos              (10U)                                   
+#define GPIO_IDR_ID10_Msk              (0x1U << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk                       
+#define GPIO_IDR_ID11_Pos              (11U)                                   
+#define GPIO_IDR_ID11_Msk              (0x1U << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk                       
+#define GPIO_IDR_ID12_Pos              (12U)                                   
+#define GPIO_IDR_ID12_Msk              (0x1U << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk                       
+#define GPIO_IDR_ID13_Pos              (13U)                                   
+#define GPIO_IDR_ID13_Msk              (0x1U << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk                       
+#define GPIO_IDR_ID14_Pos              (14U)                                   
+#define GPIO_IDR_ID14_Msk              (0x1U << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk                       
+#define GPIO_IDR_ID15_Pos              (15U)                                   
+#define GPIO_IDR_ID15_Msk              (0x1U << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk                       
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
+
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
+#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
+#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
+#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
+#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
+#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
+#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
+#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
+#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
+#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
+#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
+#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
+#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
+#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
+#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
+#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)                                    
+#define GPIO_ODR_OD0_Msk               (0x1U << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk                        
+#define GPIO_ODR_OD1_Pos               (1U)                                    
+#define GPIO_ODR_OD1_Msk               (0x1U << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk                        
+#define GPIO_ODR_OD2_Pos               (2U)                                    
+#define GPIO_ODR_OD2_Msk               (0x1U << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk                        
+#define GPIO_ODR_OD3_Pos               (3U)                                    
+#define GPIO_ODR_OD3_Msk               (0x1U << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk                        
+#define GPIO_ODR_OD4_Pos               (4U)                                    
+#define GPIO_ODR_OD4_Msk               (0x1U << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk                        
+#define GPIO_ODR_OD5_Pos               (5U)                                    
+#define GPIO_ODR_OD5_Msk               (0x1U << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk                        
+#define GPIO_ODR_OD6_Pos               (6U)                                    
+#define GPIO_ODR_OD6_Msk               (0x1U << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk                        
+#define GPIO_ODR_OD7_Pos               (7U)                                    
+#define GPIO_ODR_OD7_Msk               (0x1U << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk                        
+#define GPIO_ODR_OD8_Pos               (8U)                                    
+#define GPIO_ODR_OD8_Msk               (0x1U << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk                        
+#define GPIO_ODR_OD9_Pos               (9U)                                    
+#define GPIO_ODR_OD9_Msk               (0x1U << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk                        
+#define GPIO_ODR_OD10_Pos              (10U)                                   
+#define GPIO_ODR_OD10_Msk              (0x1U << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk                       
+#define GPIO_ODR_OD11_Pos              (11U)                                   
+#define GPIO_ODR_OD11_Msk              (0x1U << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk                       
+#define GPIO_ODR_OD12_Pos              (12U)                                   
+#define GPIO_ODR_OD12_Msk              (0x1U << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk                       
+#define GPIO_ODR_OD13_Pos              (13U)                                   
+#define GPIO_ODR_OD13_Msk              (0x1U << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk                       
+#define GPIO_ODR_OD14_Pos              (14U)                                   
+#define GPIO_ODR_OD14_Msk              (0x1U << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk                       
+#define GPIO_ODR_OD15_Pos              (15U)                                   
+#define GPIO_ODR_OD15_Msk              (0x1U << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk                       
+
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
+
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
+#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
+#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
+#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
+#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
+#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
+#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
+#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
+#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
+#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
+#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
+#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
+#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
+#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
+#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
+#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)                                    
+#define GPIO_BSRR_BS0_Msk              (0x1U << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk                       
+#define GPIO_BSRR_BS1_Pos              (1U)                                    
+#define GPIO_BSRR_BS1_Msk              (0x1U << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk                       
+#define GPIO_BSRR_BS2_Pos              (2U)                                    
+#define GPIO_BSRR_BS2_Msk              (0x1U << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk                       
+#define GPIO_BSRR_BS3_Pos              (3U)                                    
+#define GPIO_BSRR_BS3_Msk              (0x1U << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk                       
+#define GPIO_BSRR_BS4_Pos              (4U)                                    
+#define GPIO_BSRR_BS4_Msk              (0x1U << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk                       
+#define GPIO_BSRR_BS5_Pos              (5U)                                    
+#define GPIO_BSRR_BS5_Msk              (0x1U << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk                       
+#define GPIO_BSRR_BS6_Pos              (6U)                                    
+#define GPIO_BSRR_BS6_Msk              (0x1U << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk                       
+#define GPIO_BSRR_BS7_Pos              (7U)                                    
+#define GPIO_BSRR_BS7_Msk              (0x1U << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk                       
+#define GPIO_BSRR_BS8_Pos              (8U)                                    
+#define GPIO_BSRR_BS8_Msk              (0x1U << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk                       
+#define GPIO_BSRR_BS9_Pos              (9U)                                    
+#define GPIO_BSRR_BS9_Msk              (0x1U << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk                       
+#define GPIO_BSRR_BS10_Pos             (10U)                                   
+#define GPIO_BSRR_BS10_Msk             (0x1U << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk                      
+#define GPIO_BSRR_BS11_Pos             (11U)                                   
+#define GPIO_BSRR_BS11_Msk             (0x1U << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk                      
+#define GPIO_BSRR_BS12_Pos             (12U)                                   
+#define GPIO_BSRR_BS12_Msk             (0x1U << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk                      
+#define GPIO_BSRR_BS13_Pos             (13U)                                   
+#define GPIO_BSRR_BS13_Msk             (0x1U << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk                      
+#define GPIO_BSRR_BS14_Pos             (14U)                                   
+#define GPIO_BSRR_BS14_Msk             (0x1U << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk                      
+#define GPIO_BSRR_BS15_Pos             (15U)                                   
+#define GPIO_BSRR_BS15_Msk             (0x1U << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk                      
+#define GPIO_BSRR_BR0_Pos              (16U)                                   
+#define GPIO_BSRR_BR0_Msk              (0x1U << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk                       
+#define GPIO_BSRR_BR1_Pos              (17U)                                   
+#define GPIO_BSRR_BR1_Msk              (0x1U << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk                       
+#define GPIO_BSRR_BR2_Pos              (18U)                                   
+#define GPIO_BSRR_BR2_Msk              (0x1U << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk                       
+#define GPIO_BSRR_BR3_Pos              (19U)                                   
+#define GPIO_BSRR_BR3_Msk              (0x1U << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk                       
+#define GPIO_BSRR_BR4_Pos              (20U)                                   
+#define GPIO_BSRR_BR4_Msk              (0x1U << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk                       
+#define GPIO_BSRR_BR5_Pos              (21U)                                   
+#define GPIO_BSRR_BR5_Msk              (0x1U << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk                       
+#define GPIO_BSRR_BR6_Pos              (22U)                                   
+#define GPIO_BSRR_BR6_Msk              (0x1U << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk                       
+#define GPIO_BSRR_BR7_Pos              (23U)                                   
+#define GPIO_BSRR_BR7_Msk              (0x1U << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk                       
+#define GPIO_BSRR_BR8_Pos              (24U)                                   
+#define GPIO_BSRR_BR8_Msk              (0x1U << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk                       
+#define GPIO_BSRR_BR9_Pos              (25U)                                   
+#define GPIO_BSRR_BR9_Msk              (0x1U << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk                       
+#define GPIO_BSRR_BR10_Pos             (26U)                                   
+#define GPIO_BSRR_BR10_Msk             (0x1U << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk                      
+#define GPIO_BSRR_BR11_Pos             (27U)                                   
+#define GPIO_BSRR_BR11_Msk             (0x1U << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk                      
+#define GPIO_BSRR_BR12_Pos             (28U)                                   
+#define GPIO_BSRR_BR12_Msk             (0x1U << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk                      
+#define GPIO_BSRR_BR13_Pos             (29U)                                   
+#define GPIO_BSRR_BR13_Msk             (0x1U << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk                      
+#define GPIO_BSRR_BR14_Pos             (30U)                                   
+#define GPIO_BSRR_BR14_Msk             (0x1U << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk                      
+#define GPIO_BSRR_BR15_Pos             (31U)                                   
+#define GPIO_BSRR_BR15_Msk             (0x1U << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk                      
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)                                    
+#define GPIO_LCKR_LCK0_Msk             (0x1U << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk                      
+#define GPIO_LCKR_LCK1_Pos             (1U)                                    
+#define GPIO_LCKR_LCK1_Msk             (0x1U << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk                      
+#define GPIO_LCKR_LCK2_Pos             (2U)                                    
+#define GPIO_LCKR_LCK2_Msk             (0x1U << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk                      
+#define GPIO_LCKR_LCK3_Pos             (3U)                                    
+#define GPIO_LCKR_LCK3_Msk             (0x1U << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk                      
+#define GPIO_LCKR_LCK4_Pos             (4U)                                    
+#define GPIO_LCKR_LCK4_Msk             (0x1U << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk                      
+#define GPIO_LCKR_LCK5_Pos             (5U)                                    
+#define GPIO_LCKR_LCK5_Msk             (0x1U << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk                      
+#define GPIO_LCKR_LCK6_Pos             (6U)                                    
+#define GPIO_LCKR_LCK6_Msk             (0x1U << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk                      
+#define GPIO_LCKR_LCK7_Pos             (7U)                                    
+#define GPIO_LCKR_LCK7_Msk             (0x1U << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk                      
+#define GPIO_LCKR_LCK8_Pos             (8U)                                    
+#define GPIO_LCKR_LCK8_Msk             (0x1U << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk                      
+#define GPIO_LCKR_LCK9_Pos             (9U)                                    
+#define GPIO_LCKR_LCK9_Msk             (0x1U << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk                      
+#define GPIO_LCKR_LCK10_Pos            (10U)                                   
+#define GPIO_LCKR_LCK10_Msk            (0x1U << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk                     
+#define GPIO_LCKR_LCK11_Pos            (11U)                                   
+#define GPIO_LCKR_LCK11_Msk            (0x1U << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk                     
+#define GPIO_LCKR_LCK12_Pos            (12U)                                   
+#define GPIO_LCKR_LCK12_Msk            (0x1U << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk                     
+#define GPIO_LCKR_LCK13_Pos            (13U)                                   
+#define GPIO_LCKR_LCK13_Msk            (0x1U << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk                     
+#define GPIO_LCKR_LCK14_Pos            (14U)                                   
+#define GPIO_LCKR_LCK14_Msk            (0x1U << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk                     
+#define GPIO_LCKR_LCK15_Pos            (15U)                                   
+#define GPIO_LCKR_LCK15_Msk            (0x1U << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk                     
+#define GPIO_LCKR_LCKK_Pos             (16U)                                   
+#define GPIO_LCKR_LCKK_Msk             (0x1U << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk                      
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)                                    
+#define GPIO_AFRL_AFSEL0_Msk           (0xFU << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL0_0             (0x1U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)                                    
+#define GPIO_AFRL_AFSEL1_Msk           (0xFU << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL1_0             (0x1U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)                                    
+#define GPIO_AFRL_AFSEL2_Msk           (0xFU << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL2_0             (0x1U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)                                   
+#define GPIO_AFRL_AFSEL3_Msk           (0xFU << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL3_0             (0x1U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)                                   
+#define GPIO_AFRL_AFSEL4_Msk           (0xFU << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL4_0             (0x1U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)                                   
+#define GPIO_AFRL_AFSEL5_Msk           (0xFU << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL5_0             (0x1U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)                                   
+#define GPIO_AFRL_AFSEL6_Msk           (0xFU << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL6_0             (0x1U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)                                   
+#define GPIO_AFRL_AFSEL7_Msk           (0xFU << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk                    
+#define GPIO_AFRL_AFSEL7_0             (0x1U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)                                    
+#define GPIO_AFRH_AFSEL8_Msk           (0xFU << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL8_0             (0x1U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)                                    
+#define GPIO_AFRH_AFSEL9_Msk           (0xFU << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL9_0             (0x1U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)                                    
+#define GPIO_AFRH_AFSEL10_Msk          (0xFU << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk                   
+#define GPIO_AFRH_AFSEL10_0            (0x1U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)                                   
+#define GPIO_AFRH_AFSEL11_Msk          (0xFU << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk                   
+#define GPIO_AFRH_AFSEL11_0            (0x1U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)                                   
+#define GPIO_AFRH_AFSEL12_Msk          (0xFU << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk                   
+#define GPIO_AFRH_AFSEL12_0            (0x1U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)                                   
+#define GPIO_AFRH_AFSEL13_Msk          (0xFU << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk                   
+#define GPIO_AFRH_AFSEL13_0            (0x1U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)                                   
+#define GPIO_AFRH_AFSEL14_Msk          (0xFU << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk                   
+#define GPIO_AFRH_AFSEL14_0            (0x1U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)                                   
+#define GPIO_AFRH_AFSEL15_Msk          (0xFU << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk                   
+#define GPIO_AFRH_AFSEL15_0            (0x1U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)                                    
+#define GPIO_BRR_BR0_Msk               (0x1U << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk                        
+#define GPIO_BRR_BR1_Pos               (1U)                                    
+#define GPIO_BRR_BR1_Msk               (0x1U << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk                        
+#define GPIO_BRR_BR2_Pos               (2U)                                    
+#define GPIO_BRR_BR2_Msk               (0x1U << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk                        
+#define GPIO_BRR_BR3_Pos               (3U)                                    
+#define GPIO_BRR_BR3_Msk               (0x1U << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk                        
+#define GPIO_BRR_BR4_Pos               (4U)                                    
+#define GPIO_BRR_BR4_Msk               (0x1U << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk                        
+#define GPIO_BRR_BR5_Pos               (5U)                                    
+#define GPIO_BRR_BR5_Msk               (0x1U << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk                        
+#define GPIO_BRR_BR6_Pos               (6U)                                    
+#define GPIO_BRR_BR6_Msk               (0x1U << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk                        
+#define GPIO_BRR_BR7_Pos               (7U)                                    
+#define GPIO_BRR_BR7_Msk               (0x1U << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk                        
+#define GPIO_BRR_BR8_Pos               (8U)                                    
+#define GPIO_BRR_BR8_Msk               (0x1U << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk                        
+#define GPIO_BRR_BR9_Pos               (9U)                                    
+#define GPIO_BRR_BR9_Msk               (0x1U << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk                        
+#define GPIO_BRR_BR10_Pos              (10U)                                   
+#define GPIO_BRR_BR10_Msk              (0x1U << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk                       
+#define GPIO_BRR_BR11_Pos              (11U)                                   
+#define GPIO_BRR_BR11_Msk              (0x1U << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk                       
+#define GPIO_BRR_BR12_Pos              (12U)                                   
+#define GPIO_BRR_BR12_Msk              (0x1U << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk                       
+#define GPIO_BRR_BR13_Pos              (13U)                                   
+#define GPIO_BRR_BR13_Msk              (0x1U << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk                       
+#define GPIO_BRR_BR14_Pos              (14U)                                   
+#define GPIO_BRR_BR14_Msk              (0x1U << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk                       
+#define GPIO_BRR_BR15_Pos              (15U)                                   
+#define GPIO_BRR_BR15_Msk              (0x1U << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk                       
+
+/* Legacy defines */
+#define GPIO_BRR_BR_0                       GPIO_BRR_BR0
+#define GPIO_BRR_BR_1                       GPIO_BRR_BR1
+#define GPIO_BRR_BR_2                       GPIO_BRR_BR2
+#define GPIO_BRR_BR_3                       GPIO_BRR_BR3
+#define GPIO_BRR_BR_4                       GPIO_BRR_BR4
+#define GPIO_BRR_BR_5                       GPIO_BRR_BR5
+#define GPIO_BRR_BR_6                       GPIO_BRR_BR6
+#define GPIO_BRR_BR_7                       GPIO_BRR_BR7
+#define GPIO_BRR_BR_8                       GPIO_BRR_BR8
+#define GPIO_BRR_BR_9                       GPIO_BRR_BR9
+#define GPIO_BRR_BR_10                      GPIO_BRR_BR10
+#define GPIO_BRR_BR_11                      GPIO_BRR_BR11
+#define GPIO_BRR_BR_12                      GPIO_BRR_BR12
+#define GPIO_BRR_BR_13                      GPIO_BRR_BR13
+#define GPIO_BRR_BR_14                      GPIO_BRR_BR14
+#define GPIO_BRR_BR_15                      GPIO_BRR_BR15
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)                                      
+#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
+#define I2C_CR1_TXIE_Pos             (1U)                                      
+#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
+#define I2C_CR1_RXIE_Pos             (2U)                                      
+#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
+#define I2C_CR1_ADDRIE_Pos           (3U)                                      
+#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
+#define I2C_CR1_NACKIE_Pos           (4U)                                      
+#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
+#define I2C_CR1_STOPIE_Pos           (5U)                                      
+#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
+#define I2C_CR1_TCIE_Pos             (6U)                                      
+#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
+#define I2C_CR1_ERRIE_Pos            (7U)                                      
+#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
+#define I2C_CR1_DNF_Pos              (8U)                                      
+#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
+#define I2C_CR1_ANFOFF_Pos           (12U)                                     
+#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
+#define I2C_CR1_SWRST_Pos            (13U)                                     
+#define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
+#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
+#define I2C_CR1_TXDMAEN_Pos          (14U)                                     
+#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
+#define I2C_CR1_RXDMAEN_Pos          (15U)                                     
+#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
+#define I2C_CR1_SBC_Pos              (16U)                                     
+#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
+#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
+#define I2C_CR1_WUPEN_Pos            (18U)                                     
+#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
+#define I2C_CR1_GCEN_Pos             (19U)                                     
+#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
+#define I2C_CR1_SMBHEN_Pos           (20U)                                     
+#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
+#define I2C_CR1_SMBDEN_Pos           (21U)                                     
+#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)                                     
+#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
+#define I2C_CR1_PECEN_Pos            (23U)                                     
+#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)                                      
+#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
+#define I2C_CR2_RD_WRN_Pos           (10U)                                     
+#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
+#define I2C_CR2_ADD10_Pos            (11U)                                     
+#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
+#define I2C_CR2_HEAD10R_Pos          (12U)                                     
+#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)                                     
+#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
+#define I2C_CR2_STOP_Pos             (14U)                                     
+#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
+#define I2C_CR2_NACK_Pos             (15U)                                     
+#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
+#define I2C_CR2_NBYTES_Pos           (16U)                                     
+#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
+#define I2C_CR2_RELOAD_Pos           (24U)                                     
+#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
+#define I2C_CR2_AUTOEND_Pos          (25U)                                     
+#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
+#define I2C_CR2_PECBYTE_Pos          (26U)                                     
+#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)                                      
+#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
+#define I2C_OAR1_OA1MODE_Pos         (10U)                                     
+#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)                                     
+#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)                                      
+#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
+#define I2C_OAR2_OA2MSK_Pos          (8U)                                      
+#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
+#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
+#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos           (15U)                                     
+#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)                                      
+#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
+#define I2C_TIMINGR_SCLH_Pos         (8U)                                      
+#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
+#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
+#define I2C_TIMINGR_PRESC_Pos        (28U)                                     
+#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)                                      
+#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
+#define I2C_ISR_TXIS_Pos             (1U)                                      
+#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
+#define I2C_ISR_RXNE_Pos             (2U)                                      
+#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)                                      
+#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
+#define I2C_ISR_NACKF_Pos            (4U)                                      
+#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
+#define I2C_ISR_STOPF_Pos            (5U)                                      
+#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
+#define I2C_ISR_TC_Pos               (6U)                                      
+#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)                                      
+#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
+#define I2C_ISR_BERR_Pos             (8U)                                      
+#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
+#define I2C_ISR_ARLO_Pos             (9U)                                      
+#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
+#define I2C_ISR_OVR_Pos              (10U)                                     
+#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
+#define I2C_ISR_PECERR_Pos           (11U)                                     
+#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
+#define I2C_ISR_TIMEOUT_Pos          (12U)                                     
+#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
+#define I2C_ISR_ALERT_Pos            (13U)                                     
+#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
+#define I2C_ISR_BUSY_Pos             (15U)                                     
+#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
+#define I2C_ISR_DIR_Pos              (16U)                                     
+#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)                                     
+#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)                                      
+#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
+#define I2C_ICR_NACKCF_Pos           (4U)                                      
+#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
+#define I2C_ICR_STOPCF_Pos           (5U)                                      
+#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
+#define I2C_ICR_BERRCF_Pos           (8U)                                      
+#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
+#define I2C_ICR_ARLOCF_Pos           (9U)                                      
+#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)                                     
+#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)                                     
+#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
+#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
+#define I2C_ICR_ALERTCF_Pos          (13U)                                     
+#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)                                      
+#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)                                      
+#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)                                      
+#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)                                              
+#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)                                              
+#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)                                              
+#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)                                              
+#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)                                              
+#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)                                              
+#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)                                              
+#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     Firewall                               */
+/*                                                                            */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */
+#define FW_CSSA_ADD_Pos      (8U)                                              
+#define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos      (8U)                                              
+#define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
+#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
+#define FW_NVDSSA_ADD_Pos    (8U)                                              
+#define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos    (8U)                                              
+#define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos     (6U)                                              
+#define FW_VDSSA_ADD_Msk     (0x7FFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos     (6U)                                              
+#define FW_VDSL_LENG_Msk     (0x7FFU << FW_VDSL_LENG_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos        (0U)                                              
+#define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
+#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos        (1U)                                              
+#define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
+#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos        (2U)                                              
+#define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
+#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR1 register  ********************/
+
+#define PWR_CR1_LPR_Pos              (14U)                                     
+#define PWR_CR1_LPR_Msk              (0x1U << PWR_CR1_LPR_Pos)                 /*!< 0x00004000 */
+#define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
+#define PWR_CR1_VOS_Pos              (9U)                                      
+#define PWR_CR1_VOS_Msk              (0x3U << PWR_CR1_VOS_Pos)                 /*!< 0x00000600 */
+#define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR1_VOS_0                (0x1U << PWR_CR1_VOS_Pos)                 /*!< 0x00000200 */
+#define PWR_CR1_VOS_1                (0x2U << PWR_CR1_VOS_Pos)                 /*!< 0x00000400 */
+#define PWR_CR1_DBP_Pos              (8U)                                      
+#define PWR_CR1_DBP_Msk              (0x1U << PWR_CR1_DBP_Pos)                 /*!< 0x00000100 */
+#define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
+#define PWR_CR1_LPMS_Pos             (0U)                                      
+#define PWR_CR1_LPMS_Msk             (0x7U << PWR_CR1_LPMS_Pos)                /*!< 0x00000007 */
+#define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
+#define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
+#define PWR_CR1_LPMS_STOP1_Pos       (0U)                                      
+#define PWR_CR1_LPMS_STOP1_Msk       (0x1U << PWR_CR1_LPMS_STOP1_Pos)          /*!< 0x00000001 */
+#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
+#define PWR_CR1_LPMS_STOP2_Pos       (1U)                                      
+#define PWR_CR1_LPMS_STOP2_Msk       (0x1U << PWR_CR1_LPMS_STOP2_Pos)          /*!< 0x00000002 */
+#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */
+#define PWR_CR1_LPMS_STANDBY_Pos     (0U)                                      
+#define PWR_CR1_LPMS_STANDBY_Msk     (0x3U << PWR_CR1_LPMS_STANDBY_Pos)        /*!< 0x00000003 */
+#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
+#define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)                                      
+#define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos)       /*!< 0x00000004 */
+#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
+
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_USV_Pos              (10U)                                     
+#define PWR_CR2_USV_Msk              (0x1U << PWR_CR2_USV_Pos)                 /*!< 0x00000400 */
+#define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */
+/*!< PVME  Peripheral Voltage Monitor Enable */
+#define PWR_CR2_PVME_Pos             (4U)                                      
+#define PWR_CR2_PVME_Msk             (0xDU << PWR_CR2_PVME_Pos)                /*!< 0x000000D0 */
+#define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
+#define PWR_CR2_PVME4_Pos            (7U)                                      
+#define PWR_CR2_PVME4_Msk            (0x1U << PWR_CR2_PVME4_Pos)               /*!< 0x00000080 */
+#define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
+#define PWR_CR2_PVME3_Pos            (6U)                                      
+#define PWR_CR2_PVME3_Msk            (0x1U << PWR_CR2_PVME3_Pos)               /*!< 0x00000040 */
+#define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
+#define PWR_CR2_PVME1_Pos            (4U)                                      
+#define PWR_CR2_PVME1_Msk            (0x1U << PWR_CR2_PVME1_Pos)               /*!< 0x00000010 */
+#define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
+/*!< PVD level configuration */
+#define PWR_CR2_PLS_Pos              (1U)                                      
+#define PWR_CR2_PLS_Msk              (0x7U << PWR_CR2_PLS_Pos)                 /*!< 0x0000000E */
+#define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
+#define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
+#define PWR_CR2_PLS_LEV1_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV1_Msk         (0x1U << PWR_CR2_PLS_LEV1_Pos)            /*!< 0x00000002 */
+#define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
+#define PWR_CR2_PLS_LEV2_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV2_Msk         (0x1U << PWR_CR2_PLS_LEV2_Pos)            /*!< 0x00000004 */
+#define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
+#define PWR_CR2_PLS_LEV3_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV3_Msk         (0x3U << PWR_CR2_PLS_LEV3_Pos)            /*!< 0x00000006 */
+#define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
+#define PWR_CR2_PLS_LEV4_Pos         (3U)                                      
+#define PWR_CR2_PLS_LEV4_Msk         (0x1U << PWR_CR2_PLS_LEV4_Pos)            /*!< 0x00000008 */
+#define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
+#define PWR_CR2_PLS_LEV5_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV5_Msk         (0x5U << PWR_CR2_PLS_LEV5_Pos)            /*!< 0x0000000A */
+#define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
+#define PWR_CR2_PLS_LEV6_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV6_Msk         (0x3U << PWR_CR2_PLS_LEV6_Pos)            /*!< 0x0000000C */
+#define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
+#define PWR_CR2_PLS_LEV7_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV7_Msk         (0x7U << PWR_CR2_PLS_LEV7_Pos)            /*!< 0x0000000E */
+#define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
+#define PWR_CR2_PVDE_Pos             (0U)                                      
+#define PWR_CR2_PVDE_Msk             (0x1U << PWR_CR2_PVDE_Pos)                /*!< 0x00000001 */
+#define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
+
+/********************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_EIWF_Pos             (15U)                                     
+#define PWR_CR3_EIWF_Msk             (0x1U << PWR_CR3_EIWF_Pos)                /*!< 0x00008000 */
+#define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
+#define PWR_CR3_APC_Pos              (10U)                                     
+#define PWR_CR3_APC_Msk              (0x1U << PWR_CR3_APC_Pos)                 /*!< 0x00000400 */
+#define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
+#define PWR_CR3_RRS_Pos              (8U)                                      
+#define PWR_CR3_RRS_Msk              (0x1U << PWR_CR3_RRS_Pos)                 /*!< 0x00000100 */
+#define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
+#define PWR_CR3_EWUP5_Pos            (4U)                                      
+#define PWR_CR3_EWUP5_Msk            (0x1U << PWR_CR3_EWUP5_Pos)               /*!< 0x00000010 */
+#define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
+#define PWR_CR3_EWUP4_Pos            (3U)                                      
+#define PWR_CR3_EWUP4_Msk            (0x1U << PWR_CR3_EWUP4_Pos)               /*!< 0x00000008 */
+#define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
+#define PWR_CR3_EWUP3_Pos            (2U)                                      
+#define PWR_CR3_EWUP3_Msk            (0x1U << PWR_CR3_EWUP3_Pos)               /*!< 0x00000004 */
+#define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
+#define PWR_CR3_EWUP2_Pos            (1U)                                      
+#define PWR_CR3_EWUP2_Msk            (0x1U << PWR_CR3_EWUP2_Pos)               /*!< 0x00000002 */
+#define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
+#define PWR_CR3_EWUP1_Pos            (0U)                                      
+#define PWR_CR3_EWUP1_Msk            (0x1U << PWR_CR3_EWUP1_Pos)               /*!< 0x00000001 */
+#define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
+#define PWR_CR3_EWUP_Pos             (0U)                                      
+#define PWR_CR3_EWUP_Msk             (0x1FU << PWR_CR3_EWUP_Pos)               /*!< 0x0000001F */
+#define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
+
+/********************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_VBRS_Pos             (9U)                                      
+#define PWR_CR4_VBRS_Msk             (0x1U << PWR_CR4_VBRS_Pos)                /*!< 0x00000200 */
+#define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBE_Pos              (8U)                                      
+#define PWR_CR4_VBE_Msk              (0x1U << PWR_CR4_VBE_Pos)                 /*!< 0x00000100 */
+#define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
+#define PWR_CR4_WP5_Pos              (4U)                                      
+#define PWR_CR4_WP5_Msk              (0x1U << PWR_CR4_WP5_Pos)                 /*!< 0x00000010 */
+#define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
+#define PWR_CR4_WP4_Pos              (3U)                                      
+#define PWR_CR4_WP4_Msk              (0x1U << PWR_CR4_WP4_Pos)                 /*!< 0x00000008 */
+#define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
+#define PWR_CR4_WP3_Pos              (2U)                                      
+#define PWR_CR4_WP3_Msk              (0x1U << PWR_CR4_WP3_Pos)                 /*!< 0x00000004 */
+#define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
+#define PWR_CR4_WP2_Pos              (1U)                                      
+#define PWR_CR4_WP2_Msk              (0x1U << PWR_CR4_WP2_Pos)                 /*!< 0x00000002 */
+#define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
+#define PWR_CR4_WP1_Pos              (0U)                                      
+#define PWR_CR4_WP1_Msk              (0x1U << PWR_CR4_WP1_Pos)                 /*!< 0x00000001 */
+#define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
+
+/********************  Bit definition for PWR_SR1 register  ********************/
+#define PWR_SR1_WUFI_Pos             (15U)                                     
+#define PWR_SR1_WUFI_Msk             (0x1U << PWR_SR1_WUFI_Pos)                /*!< 0x00008000 */
+#define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
+#define PWR_SR1_SBF_Pos              (8U)                                      
+#define PWR_SR1_SBF_Msk              (0x1U << PWR_SR1_SBF_Pos)                 /*!< 0x00000100 */
+#define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
+#define PWR_SR1_WUF_Pos              (0U)                                      
+#define PWR_SR1_WUF_Msk              (0x1FU << PWR_SR1_WUF_Pos)                /*!< 0x0000001F */
+#define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
+#define PWR_SR1_WUF5_Pos             (4U)                                      
+#define PWR_SR1_WUF5_Msk             (0x1U << PWR_SR1_WUF5_Pos)                /*!< 0x00000010 */
+#define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
+#define PWR_SR1_WUF4_Pos             (3U)                                      
+#define PWR_SR1_WUF4_Msk             (0x1U << PWR_SR1_WUF4_Pos)                /*!< 0x00000008 */
+#define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
+#define PWR_SR1_WUF3_Pos             (2U)                                      
+#define PWR_SR1_WUF3_Msk             (0x1U << PWR_SR1_WUF3_Pos)                /*!< 0x00000004 */
+#define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
+#define PWR_SR1_WUF2_Pos             (1U)                                      
+#define PWR_SR1_WUF2_Msk             (0x1U << PWR_SR1_WUF2_Pos)                /*!< 0x00000002 */
+#define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
+#define PWR_SR1_WUF1_Pos             (0U)                                      
+#define PWR_SR1_WUF1_Msk             (0x1U << PWR_SR1_WUF1_Pos)                /*!< 0x00000001 */
+#define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_SR2 register  ********************/
+#define PWR_SR2_PVMO4_Pos            (15U)                                     
+#define PWR_SR2_PVMO4_Msk            (0x1U << PWR_SR2_PVMO4_Pos)               /*!< 0x00008000 */
+#define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO3_Pos            (14U)                                     
+#define PWR_SR2_PVMO3_Msk            (0x1U << PWR_SR2_PVMO3_Pos)               /*!< 0x00004000 */
+#define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO1_Pos            (12U)                                     
+#define PWR_SR2_PVMO1_Msk            (0x1U << PWR_SR2_PVMO1_Pos)               /*!< 0x00001000 */
+#define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVDO_Pos             (11U)                                     
+#define PWR_SR2_PVDO_Msk             (0x1U << PWR_SR2_PVDO_Pos)                /*!< 0x00000800 */
+#define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
+#define PWR_SR2_VOSF_Pos             (10U)                                     
+#define PWR_SR2_VOSF_Msk             (0x1U << PWR_SR2_VOSF_Pos)                /*!< 0x00000400 */
+#define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
+#define PWR_SR2_REGLPF_Pos           (9U)                                      
+#define PWR_SR2_REGLPF_Msk           (0x1U << PWR_SR2_REGLPF_Pos)              /*!< 0x00000200 */
+#define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
+#define PWR_SR2_REGLPS_Pos           (8U)                                      
+#define PWR_SR2_REGLPS_Msk           (0x1U << PWR_SR2_REGLPS_Pos)              /*!< 0x00000100 */
+#define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
+
+/********************  Bit definition for PWR_SCR register  ********************/
+#define PWR_SCR_CSBF_Pos             (8U)                                      
+#define PWR_SCR_CSBF_Msk             (0x1U << PWR_SCR_CSBF_Pos)                /*!< 0x00000100 */
+#define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
+#define PWR_SCR_CWUF_Pos             (0U)                                      
+#define PWR_SCR_CWUF_Msk             (0x1FU << PWR_SCR_CWUF_Pos)               /*!< 0x0000001F */
+#define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
+#define PWR_SCR_CWUF5_Pos            (4U)                                      
+#define PWR_SCR_CWUF5_Msk            (0x1U << PWR_SCR_CWUF5_Pos)               /*!< 0x00000010 */
+#define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
+#define PWR_SCR_CWUF4_Pos            (3U)                                      
+#define PWR_SCR_CWUF4_Msk            (0x1U << PWR_SCR_CWUF4_Pos)               /*!< 0x00000008 */
+#define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
+#define PWR_SCR_CWUF3_Pos            (2U)                                      
+#define PWR_SCR_CWUF3_Msk            (0x1U << PWR_SCR_CWUF3_Pos)               /*!< 0x00000004 */
+#define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
+#define PWR_SCR_CWUF2_Pos            (1U)                                      
+#define PWR_SCR_CWUF2_Msk            (0x1U << PWR_SCR_CWUF2_Pos)               /*!< 0x00000002 */
+#define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
+#define PWR_SCR_CWUF1_Pos            (0U)                                      
+#define PWR_SCR_CWUF1_Msk            (0x1U << PWR_SCR_CWUF1_Pos)               /*!< 0x00000001 */
+#define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_PUCRA register  ********************/
+#define PWR_PUCRA_PA15_Pos           (15U)                                     
+#define PWR_PUCRA_PA15_Msk           (0x1U << PWR_PUCRA_PA15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
+#define PWR_PUCRA_PA13_Pos           (13U)                                     
+#define PWR_PUCRA_PA13_Msk           (0x1U << PWR_PUCRA_PA13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
+#define PWR_PUCRA_PA12_Pos           (12U)                                     
+#define PWR_PUCRA_PA12_Msk           (0x1U << PWR_PUCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
+#define PWR_PUCRA_PA11_Pos           (11U)                                     
+#define PWR_PUCRA_PA11_Msk           (0x1U << PWR_PUCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
+#define PWR_PUCRA_PA10_Pos           (10U)                                     
+#define PWR_PUCRA_PA10_Msk           (0x1U << PWR_PUCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
+#define PWR_PUCRA_PA9_Pos            (9U)                                      
+#define PWR_PUCRA_PA9_Msk            (0x1U << PWR_PUCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
+#define PWR_PUCRA_PA8_Pos            (8U)                                      
+#define PWR_PUCRA_PA8_Msk            (0x1U << PWR_PUCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
+#define PWR_PUCRA_PA7_Pos            (7U)                                      
+#define PWR_PUCRA_PA7_Msk            (0x1U << PWR_PUCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
+#define PWR_PUCRA_PA6_Pos            (6U)                                      
+#define PWR_PUCRA_PA6_Msk            (0x1U << PWR_PUCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
+#define PWR_PUCRA_PA5_Pos            (5U)                                      
+#define PWR_PUCRA_PA5_Msk            (0x1U << PWR_PUCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
+#define PWR_PUCRA_PA4_Pos            (4U)                                      
+#define PWR_PUCRA_PA4_Msk            (0x1U << PWR_PUCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
+#define PWR_PUCRA_PA3_Pos            (3U)                                      
+#define PWR_PUCRA_PA3_Msk            (0x1U << PWR_PUCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
+#define PWR_PUCRA_PA2_Pos            (2U)                                      
+#define PWR_PUCRA_PA2_Msk            (0x1U << PWR_PUCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
+#define PWR_PUCRA_PA1_Pos            (1U)                                      
+#define PWR_PUCRA_PA1_Msk            (0x1U << PWR_PUCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
+#define PWR_PUCRA_PA0_Pos            (0U)                                      
+#define PWR_PUCRA_PA0_Msk            (0x1U << PWR_PUCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRA register  ********************/
+#define PWR_PDCRA_PA14_Pos           (14U)                                     
+#define PWR_PDCRA_PA14_Msk           (0x1U << PWR_PDCRA_PA14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
+#define PWR_PDCRA_PA12_Pos           (12U)                                     
+#define PWR_PDCRA_PA12_Msk           (0x1U << PWR_PDCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
+#define PWR_PDCRA_PA11_Pos           (11U)                                     
+#define PWR_PDCRA_PA11_Msk           (0x1U << PWR_PDCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
+#define PWR_PDCRA_PA10_Pos           (10U)                                     
+#define PWR_PDCRA_PA10_Msk           (0x1U << PWR_PDCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
+#define PWR_PDCRA_PA9_Pos            (9U)                                      
+#define PWR_PDCRA_PA9_Msk            (0x1U << PWR_PDCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
+#define PWR_PDCRA_PA8_Pos            (8U)                                      
+#define PWR_PDCRA_PA8_Msk            (0x1U << PWR_PDCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
+#define PWR_PDCRA_PA7_Pos            (7U)                                      
+#define PWR_PDCRA_PA7_Msk            (0x1U << PWR_PDCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
+#define PWR_PDCRA_PA6_Pos            (6U)                                      
+#define PWR_PDCRA_PA6_Msk            (0x1U << PWR_PDCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
+#define PWR_PDCRA_PA5_Pos            (5U)                                      
+#define PWR_PDCRA_PA5_Msk            (0x1U << PWR_PDCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
+#define PWR_PDCRA_PA4_Pos            (4U)                                      
+#define PWR_PDCRA_PA4_Msk            (0x1U << PWR_PDCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
+#define PWR_PDCRA_PA3_Pos            (3U)                                      
+#define PWR_PDCRA_PA3_Msk            (0x1U << PWR_PDCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
+#define PWR_PDCRA_PA2_Pos            (2U)                                      
+#define PWR_PDCRA_PA2_Msk            (0x1U << PWR_PDCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
+#define PWR_PDCRA_PA1_Pos            (1U)                                      
+#define PWR_PDCRA_PA1_Msk            (0x1U << PWR_PDCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
+#define PWR_PDCRA_PA0_Pos            (0U)                                      
+#define PWR_PDCRA_PA0_Msk            (0x1U << PWR_PDCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRB register  ********************/
+#define PWR_PUCRB_PB15_Pos           (15U)                                     
+#define PWR_PUCRB_PB15_Msk           (0x1U << PWR_PUCRB_PB15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
+#define PWR_PUCRB_PB14_Pos           (14U)                                     
+#define PWR_PUCRB_PB14_Msk           (0x1U << PWR_PUCRB_PB14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
+#define PWR_PUCRB_PB13_Pos           (13U)                                     
+#define PWR_PUCRB_PB13_Msk           (0x1U << PWR_PUCRB_PB13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
+#define PWR_PUCRB_PB12_Pos           (12U)                                     
+#define PWR_PUCRB_PB12_Msk           (0x1U << PWR_PUCRB_PB12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
+#define PWR_PUCRB_PB11_Pos           (11U)                                     
+#define PWR_PUCRB_PB11_Msk           (0x1U << PWR_PUCRB_PB11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
+#define PWR_PUCRB_PB10_Pos           (10U)                                     
+#define PWR_PUCRB_PB10_Msk           (0x1U << PWR_PUCRB_PB10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
+#define PWR_PUCRB_PB9_Pos            (9U)                                      
+#define PWR_PUCRB_PB9_Msk            (0x1U << PWR_PUCRB_PB9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
+#define PWR_PUCRB_PB8_Pos            (8U)                                      
+#define PWR_PUCRB_PB8_Msk            (0x1U << PWR_PUCRB_PB8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
+#define PWR_PUCRB_PB7_Pos            (7U)                                      
+#define PWR_PUCRB_PB7_Msk            (0x1U << PWR_PUCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
+#define PWR_PUCRB_PB6_Pos            (6U)                                      
+#define PWR_PUCRB_PB6_Msk            (0x1U << PWR_PUCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
+#define PWR_PUCRB_PB5_Pos            (5U)                                      
+#define PWR_PUCRB_PB5_Msk            (0x1U << PWR_PUCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
+#define PWR_PUCRB_PB4_Pos            (4U)                                      
+#define PWR_PUCRB_PB4_Msk            (0x1U << PWR_PUCRB_PB4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
+#define PWR_PUCRB_PB3_Pos            (3U)                                      
+#define PWR_PUCRB_PB3_Msk            (0x1U << PWR_PUCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
+#define PWR_PUCRB_PB2_Pos            (2U)                                      
+#define PWR_PUCRB_PB2_Msk            (0x1U << PWR_PUCRB_PB2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
+#define PWR_PUCRB_PB1_Pos            (1U)                                      
+#define PWR_PUCRB_PB1_Msk            (0x1U << PWR_PUCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
+#define PWR_PUCRB_PB0_Pos            (0U)                                      
+#define PWR_PUCRB_PB0_Msk            (0x1U << PWR_PUCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRB register  ********************/
+#define PWR_PDCRB_PB15_Pos           (15U)                                     
+#define PWR_PDCRB_PB15_Msk           (0x1U << PWR_PDCRB_PB15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
+#define PWR_PDCRB_PB14_Pos           (14U)                                     
+#define PWR_PDCRB_PB14_Msk           (0x1U << PWR_PDCRB_PB14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
+#define PWR_PDCRB_PB13_Pos           (13U)                                     
+#define PWR_PDCRB_PB13_Msk           (0x1U << PWR_PDCRB_PB13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
+#define PWR_PDCRB_PB12_Pos           (12U)                                     
+#define PWR_PDCRB_PB12_Msk           (0x1U << PWR_PDCRB_PB12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
+#define PWR_PDCRB_PB11_Pos           (11U)                                     
+#define PWR_PDCRB_PB11_Msk           (0x1U << PWR_PDCRB_PB11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
+#define PWR_PDCRB_PB10_Pos           (10U)                                     
+#define PWR_PDCRB_PB10_Msk           (0x1U << PWR_PDCRB_PB10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
+#define PWR_PDCRB_PB9_Pos            (9U)                                      
+#define PWR_PDCRB_PB9_Msk            (0x1U << PWR_PDCRB_PB9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
+#define PWR_PDCRB_PB8_Pos            (8U)                                      
+#define PWR_PDCRB_PB8_Msk            (0x1U << PWR_PDCRB_PB8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
+#define PWR_PDCRB_PB7_Pos            (7U)                                      
+#define PWR_PDCRB_PB7_Msk            (0x1U << PWR_PDCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
+#define PWR_PDCRB_PB6_Pos            (6U)                                      
+#define PWR_PDCRB_PB6_Msk            (0x1U << PWR_PDCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
+#define PWR_PDCRB_PB5_Pos            (5U)                                      
+#define PWR_PDCRB_PB5_Msk            (0x1U << PWR_PDCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
+#define PWR_PDCRB_PB3_Pos            (3U)                                      
+#define PWR_PDCRB_PB3_Msk            (0x1U << PWR_PDCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
+#define PWR_PDCRB_PB2_Pos            (2U)                                      
+#define PWR_PDCRB_PB2_Msk            (0x1U << PWR_PDCRB_PB2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
+#define PWR_PDCRB_PB1_Pos            (1U)                                      
+#define PWR_PDCRB_PB1_Msk            (0x1U << PWR_PDCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
+#define PWR_PDCRB_PB0_Pos            (0U)                                      
+#define PWR_PDCRB_PB0_Msk            (0x1U << PWR_PDCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRC register  ********************/
+#define PWR_PUCRC_PC15_Pos           (15U)                                     
+#define PWR_PUCRC_PC15_Msk           (0x1U << PWR_PUCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
+#define PWR_PUCRC_PC14_Pos           (14U)                                     
+#define PWR_PUCRC_PC14_Msk           (0x1U << PWR_PUCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
+#define PWR_PUCRC_PC13_Pos           (13U)                                     
+#define PWR_PUCRC_PC13_Msk           (0x1U << PWR_PUCRC_PC13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
+#define PWR_PUCRC_PC12_Pos           (12U)                                     
+#define PWR_PUCRC_PC12_Msk           (0x1U << PWR_PUCRC_PC12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
+#define PWR_PUCRC_PC11_Pos           (11U)                                     
+#define PWR_PUCRC_PC11_Msk           (0x1U << PWR_PUCRC_PC11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
+#define PWR_PUCRC_PC10_Pos           (10U)                                     
+#define PWR_PUCRC_PC10_Msk           (0x1U << PWR_PUCRC_PC10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
+#define PWR_PUCRC_PC9_Pos            (9U)                                      
+#define PWR_PUCRC_PC9_Msk            (0x1U << PWR_PUCRC_PC9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
+#define PWR_PUCRC_PC8_Pos            (8U)                                      
+#define PWR_PUCRC_PC8_Msk            (0x1U << PWR_PUCRC_PC8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
+#define PWR_PUCRC_PC7_Pos            (7U)                                      
+#define PWR_PUCRC_PC7_Msk            (0x1U << PWR_PUCRC_PC7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
+#define PWR_PUCRC_PC6_Pos            (6U)                                      
+#define PWR_PUCRC_PC6_Msk            (0x1U << PWR_PUCRC_PC6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
+#define PWR_PUCRC_PC5_Pos            (5U)                                      
+#define PWR_PUCRC_PC5_Msk            (0x1U << PWR_PUCRC_PC5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
+#define PWR_PUCRC_PC4_Pos            (4U)                                      
+#define PWR_PUCRC_PC4_Msk            (0x1U << PWR_PUCRC_PC4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
+#define PWR_PUCRC_PC3_Pos            (3U)                                      
+#define PWR_PUCRC_PC3_Msk            (0x1U << PWR_PUCRC_PC3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
+#define PWR_PUCRC_PC2_Pos            (2U)                                      
+#define PWR_PUCRC_PC2_Msk            (0x1U << PWR_PUCRC_PC2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
+#define PWR_PUCRC_PC1_Pos            (1U)                                      
+#define PWR_PUCRC_PC1_Msk            (0x1U << PWR_PUCRC_PC1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
+#define PWR_PUCRC_PC0_Pos            (0U)                                      
+#define PWR_PUCRC_PC0_Msk            (0x1U << PWR_PUCRC_PC0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRC register  ********************/
+#define PWR_PDCRC_PC15_Pos           (15U)                                     
+#define PWR_PDCRC_PC15_Msk           (0x1U << PWR_PDCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
+#define PWR_PDCRC_PC14_Pos           (14U)                                     
+#define PWR_PDCRC_PC14_Msk           (0x1U << PWR_PDCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
+#define PWR_PDCRC_PC13_Pos           (13U)                                     
+#define PWR_PDCRC_PC13_Msk           (0x1U << PWR_PDCRC_PC13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
+#define PWR_PDCRC_PC12_Pos           (12U)                                     
+#define PWR_PDCRC_PC12_Msk           (0x1U << PWR_PDCRC_PC12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
+#define PWR_PDCRC_PC11_Pos           (11U)                                     
+#define PWR_PDCRC_PC11_Msk           (0x1U << PWR_PDCRC_PC11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
+#define PWR_PDCRC_PC10_Pos           (10U)                                     
+#define PWR_PDCRC_PC10_Msk           (0x1U << PWR_PDCRC_PC10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
+#define PWR_PDCRC_PC9_Pos            (9U)                                      
+#define PWR_PDCRC_PC9_Msk            (0x1U << PWR_PDCRC_PC9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
+#define PWR_PDCRC_PC8_Pos            (8U)                                      
+#define PWR_PDCRC_PC8_Msk            (0x1U << PWR_PDCRC_PC8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
+#define PWR_PDCRC_PC7_Pos            (7U)                                      
+#define PWR_PDCRC_PC7_Msk            (0x1U << PWR_PDCRC_PC7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
+#define PWR_PDCRC_PC6_Pos            (6U)                                      
+#define PWR_PDCRC_PC6_Msk            (0x1U << PWR_PDCRC_PC6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
+#define PWR_PDCRC_PC5_Pos            (5U)                                      
+#define PWR_PDCRC_PC5_Msk            (0x1U << PWR_PDCRC_PC5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
+#define PWR_PDCRC_PC4_Pos            (4U)                                      
+#define PWR_PDCRC_PC4_Msk            (0x1U << PWR_PDCRC_PC4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
+#define PWR_PDCRC_PC3_Pos            (3U)                                      
+#define PWR_PDCRC_PC3_Msk            (0x1U << PWR_PDCRC_PC3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
+#define PWR_PDCRC_PC2_Pos            (2U)                                      
+#define PWR_PDCRC_PC2_Msk            (0x1U << PWR_PDCRC_PC2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
+#define PWR_PDCRC_PC1_Pos            (1U)                                      
+#define PWR_PDCRC_PC1_Msk            (0x1U << PWR_PDCRC_PC1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
+#define PWR_PDCRC_PC0_Pos            (0U)                                      
+#define PWR_PDCRC_PC0_Msk            (0x1U << PWR_PDCRC_PC0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRD register  ********************/
+#define PWR_PUCRD_PD15_Pos           (15U)                                     
+#define PWR_PUCRD_PD15_Msk           (0x1U << PWR_PUCRD_PD15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
+#define PWR_PUCRD_PD14_Pos           (14U)                                     
+#define PWR_PUCRD_PD14_Msk           (0x1U << PWR_PUCRD_PD14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
+#define PWR_PUCRD_PD13_Pos           (13U)                                     
+#define PWR_PUCRD_PD13_Msk           (0x1U << PWR_PUCRD_PD13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
+#define PWR_PUCRD_PD12_Pos           (12U)                                     
+#define PWR_PUCRD_PD12_Msk           (0x1U << PWR_PUCRD_PD12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
+#define PWR_PUCRD_PD11_Pos           (11U)                                     
+#define PWR_PUCRD_PD11_Msk           (0x1U << PWR_PUCRD_PD11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
+#define PWR_PUCRD_PD10_Pos           (10U)                                     
+#define PWR_PUCRD_PD10_Msk           (0x1U << PWR_PUCRD_PD10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
+#define PWR_PUCRD_PD9_Pos            (9U)                                      
+#define PWR_PUCRD_PD9_Msk            (0x1U << PWR_PUCRD_PD9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
+#define PWR_PUCRD_PD8_Pos            (8U)                                      
+#define PWR_PUCRD_PD8_Msk            (0x1U << PWR_PUCRD_PD8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
+#define PWR_PUCRD_PD7_Pos            (7U)                                      
+#define PWR_PUCRD_PD7_Msk            (0x1U << PWR_PUCRD_PD7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
+#define PWR_PUCRD_PD6_Pos            (6U)                                      
+#define PWR_PUCRD_PD6_Msk            (0x1U << PWR_PUCRD_PD6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
+#define PWR_PUCRD_PD5_Pos            (5U)                                      
+#define PWR_PUCRD_PD5_Msk            (0x1U << PWR_PUCRD_PD5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
+#define PWR_PUCRD_PD4_Pos            (4U)                                      
+#define PWR_PUCRD_PD4_Msk            (0x1U << PWR_PUCRD_PD4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
+#define PWR_PUCRD_PD3_Pos            (3U)                                      
+#define PWR_PUCRD_PD3_Msk            (0x1U << PWR_PUCRD_PD3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
+#define PWR_PUCRD_PD2_Pos            (2U)                                      
+#define PWR_PUCRD_PD2_Msk            (0x1U << PWR_PUCRD_PD2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
+#define PWR_PUCRD_PD1_Pos            (1U)                                      
+#define PWR_PUCRD_PD1_Msk            (0x1U << PWR_PUCRD_PD1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
+#define PWR_PUCRD_PD0_Pos            (0U)                                      
+#define PWR_PUCRD_PD0_Msk            (0x1U << PWR_PUCRD_PD0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRD register  ********************/
+#define PWR_PDCRD_PD15_Pos           (15U)                                     
+#define PWR_PDCRD_PD15_Msk           (0x1U << PWR_PDCRD_PD15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
+#define PWR_PDCRD_PD14_Pos           (14U)                                     
+#define PWR_PDCRD_PD14_Msk           (0x1U << PWR_PDCRD_PD14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
+#define PWR_PDCRD_PD13_Pos           (13U)                                     
+#define PWR_PDCRD_PD13_Msk           (0x1U << PWR_PDCRD_PD13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
+#define PWR_PDCRD_PD12_Pos           (12U)                                     
+#define PWR_PDCRD_PD12_Msk           (0x1U << PWR_PDCRD_PD12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
+#define PWR_PDCRD_PD11_Pos           (11U)                                     
+#define PWR_PDCRD_PD11_Msk           (0x1U << PWR_PDCRD_PD11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
+#define PWR_PDCRD_PD10_Pos           (10U)                                     
+#define PWR_PDCRD_PD10_Msk           (0x1U << PWR_PDCRD_PD10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
+#define PWR_PDCRD_PD9_Pos            (9U)                                      
+#define PWR_PDCRD_PD9_Msk            (0x1U << PWR_PDCRD_PD9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
+#define PWR_PDCRD_PD8_Pos            (8U)                                      
+#define PWR_PDCRD_PD8_Msk            (0x1U << PWR_PDCRD_PD8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
+#define PWR_PDCRD_PD7_Pos            (7U)                                      
+#define PWR_PDCRD_PD7_Msk            (0x1U << PWR_PDCRD_PD7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
+#define PWR_PDCRD_PD6_Pos            (6U)                                      
+#define PWR_PDCRD_PD6_Msk            (0x1U << PWR_PDCRD_PD6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
+#define PWR_PDCRD_PD5_Pos            (5U)                                      
+#define PWR_PDCRD_PD5_Msk            (0x1U << PWR_PDCRD_PD5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
+#define PWR_PDCRD_PD4_Pos            (4U)                                      
+#define PWR_PDCRD_PD4_Msk            (0x1U << PWR_PDCRD_PD4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
+#define PWR_PDCRD_PD3_Pos            (3U)                                      
+#define PWR_PDCRD_PD3_Msk            (0x1U << PWR_PDCRD_PD3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
+#define PWR_PDCRD_PD2_Pos            (2U)                                      
+#define PWR_PDCRD_PD2_Msk            (0x1U << PWR_PDCRD_PD2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
+#define PWR_PDCRD_PD1_Pos            (1U)                                      
+#define PWR_PDCRD_PD1_Msk            (0x1U << PWR_PDCRD_PD1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
+#define PWR_PDCRD_PD0_Pos            (0U)                                      
+#define PWR_PDCRD_PD0_Msk            (0x1U << PWR_PDCRD_PD0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRE register  ********************/
+#define PWR_PUCRE_PE15_Pos           (15U)                                     
+#define PWR_PUCRE_PE15_Msk           (0x1U << PWR_PUCRE_PE15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
+#define PWR_PUCRE_PE14_Pos           (14U)                                     
+#define PWR_PUCRE_PE14_Msk           (0x1U << PWR_PUCRE_PE14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
+#define PWR_PUCRE_PE13_Pos           (13U)                                     
+#define PWR_PUCRE_PE13_Msk           (0x1U << PWR_PUCRE_PE13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
+#define PWR_PUCRE_PE12_Pos           (12U)                                     
+#define PWR_PUCRE_PE12_Msk           (0x1U << PWR_PUCRE_PE12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
+#define PWR_PUCRE_PE11_Pos           (11U)                                     
+#define PWR_PUCRE_PE11_Msk           (0x1U << PWR_PUCRE_PE11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
+#define PWR_PUCRE_PE10_Pos           (10U)                                     
+#define PWR_PUCRE_PE10_Msk           (0x1U << PWR_PUCRE_PE10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
+#define PWR_PUCRE_PE9_Pos            (9U)                                      
+#define PWR_PUCRE_PE9_Msk            (0x1U << PWR_PUCRE_PE9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
+#define PWR_PUCRE_PE8_Pos            (8U)                                      
+#define PWR_PUCRE_PE8_Msk            (0x1U << PWR_PUCRE_PE8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
+#define PWR_PUCRE_PE7_Pos            (7U)                                      
+#define PWR_PUCRE_PE7_Msk            (0x1U << PWR_PUCRE_PE7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
+#define PWR_PUCRE_PE6_Pos            (6U)                                      
+#define PWR_PUCRE_PE6_Msk            (0x1U << PWR_PUCRE_PE6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
+#define PWR_PUCRE_PE5_Pos            (5U)                                      
+#define PWR_PUCRE_PE5_Msk            (0x1U << PWR_PUCRE_PE5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
+#define PWR_PUCRE_PE4_Pos            (4U)                                      
+#define PWR_PUCRE_PE4_Msk            (0x1U << PWR_PUCRE_PE4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
+#define PWR_PUCRE_PE3_Pos            (3U)                                      
+#define PWR_PUCRE_PE3_Msk            (0x1U << PWR_PUCRE_PE3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
+#define PWR_PUCRE_PE2_Pos            (2U)                                      
+#define PWR_PUCRE_PE2_Msk            (0x1U << PWR_PUCRE_PE2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
+#define PWR_PUCRE_PE1_Pos            (1U)                                      
+#define PWR_PUCRE_PE1_Msk            (0x1U << PWR_PUCRE_PE1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
+#define PWR_PUCRE_PE0_Pos            (0U)                                      
+#define PWR_PUCRE_PE0_Msk            (0x1U << PWR_PUCRE_PE0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRE register  ********************/
+#define PWR_PDCRE_PE15_Pos           (15U)                                     
+#define PWR_PDCRE_PE15_Msk           (0x1U << PWR_PDCRE_PE15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
+#define PWR_PDCRE_PE14_Pos           (14U)                                     
+#define PWR_PDCRE_PE14_Msk           (0x1U << PWR_PDCRE_PE14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
+#define PWR_PDCRE_PE13_Pos           (13U)                                     
+#define PWR_PDCRE_PE13_Msk           (0x1U << PWR_PDCRE_PE13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
+#define PWR_PDCRE_PE12_Pos           (12U)                                     
+#define PWR_PDCRE_PE12_Msk           (0x1U << PWR_PDCRE_PE12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
+#define PWR_PDCRE_PE11_Pos           (11U)                                     
+#define PWR_PDCRE_PE11_Msk           (0x1U << PWR_PDCRE_PE11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
+#define PWR_PDCRE_PE10_Pos           (10U)                                     
+#define PWR_PDCRE_PE10_Msk           (0x1U << PWR_PDCRE_PE10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
+#define PWR_PDCRE_PE9_Pos            (9U)                                      
+#define PWR_PDCRE_PE9_Msk            (0x1U << PWR_PDCRE_PE9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
+#define PWR_PDCRE_PE8_Pos            (8U)                                      
+#define PWR_PDCRE_PE8_Msk            (0x1U << PWR_PDCRE_PE8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
+#define PWR_PDCRE_PE7_Pos            (7U)                                      
+#define PWR_PDCRE_PE7_Msk            (0x1U << PWR_PDCRE_PE7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
+#define PWR_PDCRE_PE6_Pos            (6U)                                      
+#define PWR_PDCRE_PE6_Msk            (0x1U << PWR_PDCRE_PE6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
+#define PWR_PDCRE_PE5_Pos            (5U)                                      
+#define PWR_PDCRE_PE5_Msk            (0x1U << PWR_PDCRE_PE5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
+#define PWR_PDCRE_PE4_Pos            (4U)                                      
+#define PWR_PDCRE_PE4_Msk            (0x1U << PWR_PDCRE_PE4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
+#define PWR_PDCRE_PE3_Pos            (3U)                                      
+#define PWR_PDCRE_PE3_Msk            (0x1U << PWR_PDCRE_PE3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
+#define PWR_PDCRE_PE2_Pos            (2U)                                      
+#define PWR_PDCRE_PE2_Msk            (0x1U << PWR_PDCRE_PE2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
+#define PWR_PDCRE_PE1_Pos            (1U)                                      
+#define PWR_PDCRE_PE1_Msk            (0x1U << PWR_PDCRE_PE1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
+#define PWR_PDCRE_PE0_Pos            (0U)                                      
+#define PWR_PDCRE_PE0_Msk            (0x1U << PWR_PDCRE_PE0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
+
+
+/********************  Bit definition for PWR_PUCRH register  ********************/
+#define PWR_PUCRH_PH3_Pos            (3U)                                      
+#define PWR_PUCRH_PH3_Msk            (0x1U << PWR_PUCRH_PH3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRH_PH3                PWR_PUCRH_PH3_Msk                         /*!< Port PH3 Pull-Up set  */
+#define PWR_PUCRH_PH1_Pos            (1U)                                      
+#define PWR_PUCRH_PH1_Msk            (0x1U << PWR_PUCRH_PH1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */
+#define PWR_PUCRH_PH0_Pos            (0U)                                      
+#define PWR_PUCRH_PH0_Msk            (0x1U << PWR_PUCRH_PH0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRH register  ********************/
+#define PWR_PDCRH_PH3_Pos            (3U)                                      
+#define PWR_PDCRH_PH3_Msk            (0x1U << PWR_PDCRH_PH3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRH_PH3                PWR_PDCRH_PH3_Msk                         /*!< Port PH3 Pull-Down set  */
+#define PWR_PDCRH_PH1_Pos            (1U)                                      
+#define PWR_PDCRH_PH1_Msk            (0x1U << PWR_PDCRH_PH1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */
+#define PWR_PDCRH_PH0_Pos            (0U)                                      
+#define PWR_PDCRH_PH0_Msk            (0x1U << PWR_PDCRH_PH0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)
+*/
+#define RCC_HSI48_SUPPORT
+#define RCC_PLLP_DIV_2_31_SUPPORT
+#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_MSION_Pos                     (0U)                              
+#define RCC_CR_MSION_Msk                     (0x1U << RCC_CR_MSION_Pos)        /*!< 0x00000001 */
+#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
+#define RCC_CR_MSIRDY_Pos                    (1U)                              
+#define RCC_CR_MSIRDY_Msk                    (0x1U << RCC_CR_MSIRDY_Pos)       /*!< 0x00000002 */
+#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
+#define RCC_CR_MSIPLLEN_Pos                  (2U)                              
+#define RCC_CR_MSIPLLEN_Msk                  (0x1U << RCC_CR_MSIPLLEN_Pos)     /*!< 0x00000004 */
+#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
+#define RCC_CR_MSIRGSEL_Pos                  (3U)                              
+#define RCC_CR_MSIRGSEL_Msk                  (0x1U << RCC_CR_MSIRGSEL_Pos)     /*!< 0x00000008 */
+#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
+
+/*!< MSIRANGE configuration : 12 frequency ranges available */
+#define RCC_CR_MSIRANGE_Pos                  (4U)                              
+#define RCC_CR_MSIRANGE_Msk                  (0xFU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000F0 */
+#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
+#define RCC_CR_MSIRANGE_0                    (0x0U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000000 */
+#define RCC_CR_MSIRANGE_1                    (0x1U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_2                    (0x2U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_3                    (0x3U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000030 */
+#define RCC_CR_MSIRANGE_4                    (0x4U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_5                    (0x5U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000050 */
+#define RCC_CR_MSIRANGE_6                    (0x6U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000060 */
+#define RCC_CR_MSIRANGE_7                    (0x7U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000070 */
+#define RCC_CR_MSIRANGE_8                    (0x8U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000080 */
+#define RCC_CR_MSIRANGE_9                    (0x9U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000090 */
+#define RCC_CR_MSIRANGE_10                   (0xAU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000A0 */
+#define RCC_CR_MSIRANGE_11                   (0xBU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000B0 */
+
+#define RCC_CR_HSION_Pos                     (8U)                              
+#define RCC_CR_HSION_Msk                     (0x1U << RCC_CR_HSION_Pos)        /*!< 0x00000100 */
+#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
+#define RCC_CR_HSIKERON_Pos                  (9U)                              
+#define RCC_CR_HSIKERON_Msk                  (0x1U << RCC_CR_HSIKERON_Pos)     /*!< 0x00000200 */
+#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                    (10U)                             
+#define RCC_CR_HSIRDY_Msk                    (0x1U << RCC_CR_HSIRDY_Pos)       /*!< 0x00000400 */
+#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
+#define RCC_CR_HSIASFS_Pos                   (11U)                             
+#define RCC_CR_HSIASFS_Msk                   (0x1U << RCC_CR_HSIASFS_Pos)      /*!< 0x00000800 */
+#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
+
+#define RCC_CR_HSEON_Pos                     (16U)                             
+#define RCC_CR_HSEON_Msk                     (0x1U << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
+#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
+#define RCC_CR_HSERDY_Pos                    (17U)                             
+#define RCC_CR_HSERDY_Msk                    (0x1U << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
+#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
+#define RCC_CR_HSEBYP_Pos                    (18U)                             
+#define RCC_CR_HSEBYP_Msk                    (0x1U << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
+#define RCC_CR_CSSON_Pos                     (19U)                             
+#define RCC_CR_CSSON_Msk                     (0x1U << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
+#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
+
+#define RCC_CR_PLLON_Pos                     (24U)                             
+#define RCC_CR_PLLON_Msk                     (0x1U << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
+#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                    (25U)                             
+#define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
+#define RCC_CR_PLLSAI1ON_Pos                 (26U)                             
+#define RCC_CR_PLLSAI1ON_Msk                 (0x1U << RCC_CR_PLLSAI1ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */
+#define RCC_CR_PLLSAI1RDY_Pos                (27U)                             
+#define RCC_CR_PLLSAI1RDY_Msk                (0x1U << RCC_CR_PLLSAI1RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */
+
+/********************  Bit definition for RCC_ICSCR register  ***************/
+/*!< MSICAL configuration */
+#define RCC_ICSCR_MSICAL_Pos                 (0U)                              
+#define RCC_ICSCR_MSICAL_Msk                 (0xFFU << RCC_ICSCR_MSICAL_Pos)   /*!< 0x000000FF */
+#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
+#define RCC_ICSCR_MSICAL_0                   (0x01U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000001 */
+#define RCC_ICSCR_MSICAL_1                   (0x02U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000002 */
+#define RCC_ICSCR_MSICAL_2                   (0x04U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000004 */
+#define RCC_ICSCR_MSICAL_3                   (0x08U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000008 */
+#define RCC_ICSCR_MSICAL_4                   (0x10U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000010 */
+#define RCC_ICSCR_MSICAL_5                   (0x20U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000020 */
+#define RCC_ICSCR_MSICAL_6                   (0x40U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000040 */
+#define RCC_ICSCR_MSICAL_7                   (0x80U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000080 */
+
+/*!< MSITRIM configuration */
+#define RCC_ICSCR_MSITRIM_Pos                (8U)                              
+#define RCC_ICSCR_MSITRIM_Msk                (0xFFU << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x0000FF00 */
+#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
+#define RCC_ICSCR_MSITRIM_0                  (0x01U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000100 */
+#define RCC_ICSCR_MSITRIM_1                  (0x02U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000200 */
+#define RCC_ICSCR_MSITRIM_2                  (0x04U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000400 */
+#define RCC_ICSCR_MSITRIM_3                  (0x08U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000800 */
+#define RCC_ICSCR_MSITRIM_4                  (0x10U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00001000 */
+#define RCC_ICSCR_MSITRIM_5                  (0x20U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00002000 */
+#define RCC_ICSCR_MSITRIM_6                  (0x40U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00004000 */
+#define RCC_ICSCR_MSITRIM_7                  (0x80U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00008000 */
+
+/*!< HSICAL configuration */
+#define RCC_ICSCR_HSICAL_Pos                 (16U)                             
+#define RCC_ICSCR_HSICAL_Msk                 (0xFFU << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00FF0000 */
+#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
+#define RCC_ICSCR_HSICAL_0                   (0x01U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00010000 */
+#define RCC_ICSCR_HSICAL_1                   (0x02U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00020000 */
+#define RCC_ICSCR_HSICAL_2                   (0x04U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00040000 */
+#define RCC_ICSCR_HSICAL_3                   (0x08U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00080000 */
+#define RCC_ICSCR_HSICAL_4                   (0x10U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00100000 */
+#define RCC_ICSCR_HSICAL_5                   (0x20U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00200000 */
+#define RCC_ICSCR_HSICAL_6                   (0x40U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00400000 */
+#define RCC_ICSCR_HSICAL_7                   (0x80U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00800000 */
+
+/*!< HSITRIM configuration */
+#define RCC_ICSCR_HSITRIM_Pos                (24U)                             
+#define RCC_ICSCR_HSITRIM_Msk                (0x1FU << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x1F000000 */
+#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[4:0] bits */
+#define RCC_ICSCR_HSITRIM_0                  (0x01U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x01000000 */
+#define RCC_ICSCR_HSITRIM_1                  (0x02U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x02000000 */
+#define RCC_ICSCR_HSITRIM_2                  (0x04U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x04000000 */
+#define RCC_ICSCR_HSITRIM_3                  (0x08U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x08000000 */
+#define RCC_ICSCR_HSITRIM_4                  (0x10U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x10000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                      (0U)                              
+#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
+#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI oscillator selection as system clock */
+#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
+#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
+#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                     (2U)                              
+#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
+#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                    (4U)                              
+#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                   (8U)                              
+#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                   (11U)                             
+#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
+#define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
+
+/*!< MCOSEL configuration */
+#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
+#define RCC_CFGR_MCOSEL_Msk                  (0xFU << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3                    (0x8U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
+#define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
+ 
+#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
+ 
+/* Legacy aliases */
+#define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
+#define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
+#define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
+#define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
+#define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
+#define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLSRC_Pos               (0U)                              
+#define RCC_PLLCFGR_PLLSRC_Msk               (0x3U << RCC_PLLCFGR_PLLSRC_Pos)  /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk            
+
+#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)                              
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
+
+#define RCC_PLLCFGR_PLLM_Pos                 (4U)                              
+#define RCC_PLLCFGR_PLLM_Msk                 (0x7U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000070 */
+#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk              
+#define RCC_PLLCFGR_PLLM_0                   (0x1U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_1                   (0x2U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLLM_2                   (0x4U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000040 */
+
+#define RCC_PLLCFGR_PLLN_Pos                 (8U)                              
+#define RCC_PLLCFGR_PLLN_Msk                 (0x7FU << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00007F00 */
+#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk              
+#define RCC_PLLCFGR_PLLN_0                   (0x01U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_1                   (0x02U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_2                   (0x04U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_3                   (0x08U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_4                   (0x10U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_5                   (0x20U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_6                   (0x40U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLPEN_Pos               (16U)                             
+#define RCC_PLLCFGR_PLLPEN_Msk               (0x1U << RCC_PLLCFGR_PLLPEN_Pos)  /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk            
+#define RCC_PLLCFGR_PLLP_Pos                 (17U)                             
+#define RCC_PLLCFGR_PLLP_Msk                 (0x1U << RCC_PLLCFGR_PLLP_Pos)    /*!< 0x00020000 */
+#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk              
+#define RCC_PLLCFGR_PLLQEN_Pos               (20U)                             
+#define RCC_PLLCFGR_PLLQEN_Msk               (0x1U << RCC_PLLCFGR_PLLQEN_Pos)  /*!< 0x00100000 */
+#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk            
+
+#define RCC_PLLCFGR_PLLQ_Pos                 (21U)                             
+#define RCC_PLLCFGR_PLLQ_Msk                 (0x3U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00600000 */
+#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk              
+#define RCC_PLLCFGR_PLLQ_0                   (0x1U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00200000 */
+#define RCC_PLLCFGR_PLLQ_1                   (0x2U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00400000 */
+
+#define RCC_PLLCFGR_PLLREN_Pos               (24U)                             
+#define RCC_PLLCFGR_PLLREN_Msk               (0x1U << RCC_PLLCFGR_PLLREN_Pos)  /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk            
+#define RCC_PLLCFGR_PLLR_Pos                 (25U)                             
+#define RCC_PLLCFGR_PLLR_Msk                 (0x3U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x06000000 */
+#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk              
+#define RCC_PLLCFGR_PLLR_0                   (0x1U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLR_1                   (0x2U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x04000000 */
+
+#define RCC_PLLCFGR_PLLPDIV_Pos              (27U)                             
+#define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
+#define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk           
+#define RCC_PLLCFGR_PLLPDIV_0                (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
+#define RCC_PLLCFGR_PLLPDIV_1                (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLPDIV_2                (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLPDIV_3                (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
+#define RCC_PLLCFGR_PLLPDIV_4                (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk      
+
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos      (27U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk      (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV          RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk   
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0        (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1        (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2        (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3        (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4        (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                (0U)                              
+#define RCC_CIER_LSIRDYIE_Msk                (0x1U << RCC_CIER_LSIRDYIE_Pos)   /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk             
+#define RCC_CIER_LSERDYIE_Pos                (1U)                              
+#define RCC_CIER_LSERDYIE_Msk                (0x1U << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk             
+#define RCC_CIER_MSIRDYIE_Pos                (2U)                              
+#define RCC_CIER_MSIRDYIE_Msk                (0x1U << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk             
+#define RCC_CIER_HSIRDYIE_Pos                (3U)                              
+#define RCC_CIER_HSIRDYIE_Msk                (0x1U << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk             
+#define RCC_CIER_HSERDYIE_Pos                (4U)                              
+#define RCC_CIER_HSERDYIE_Msk                (0x1U << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk             
+#define RCC_CIER_PLLRDYIE_Pos                (5U)                              
+#define RCC_CIER_PLLRDYIE_Msk                (0x1U << RCC_CIER_PLLRDYIE_Pos)   /*!< 0x00000020 */
+#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk             
+#define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)                              
+#define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk         
+#define RCC_CIER_LSECSSIE_Pos                (9U)                              
+#define RCC_CIER_LSECSSIE_Msk                (0x1U << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk             
+#define RCC_CIER_HSI48RDYIE_Pos              (10U)                             
+#define RCC_CIER_HSI48RDYIE_Msk              (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk           
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                 (0U)                              
+#define RCC_CIFR_LSIRDYF_Msk                 (0x1U << RCC_CIFR_LSIRDYF_Pos)    /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk              
+#define RCC_CIFR_LSERDYF_Pos                 (1U)                              
+#define RCC_CIFR_LSERDYF_Msk                 (0x1U << RCC_CIFR_LSERDYF_Pos)    /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk              
+#define RCC_CIFR_MSIRDYF_Pos                 (2U)                              
+#define RCC_CIFR_MSIRDYF_Msk                 (0x1U << RCC_CIFR_MSIRDYF_Pos)    /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk              
+#define RCC_CIFR_HSIRDYF_Pos                 (3U)                              
+#define RCC_CIFR_HSIRDYF_Msk                 (0x1U << RCC_CIFR_HSIRDYF_Pos)    /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk              
+#define RCC_CIFR_HSERDYF_Pos                 (4U)                              
+#define RCC_CIFR_HSERDYF_Msk                 (0x1U << RCC_CIFR_HSERDYF_Pos)    /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk              
+#define RCC_CIFR_PLLRDYF_Pos                 (5U)                              
+#define RCC_CIFR_PLLRDYF_Msk                 (0x1U << RCC_CIFR_PLLRDYF_Pos)    /*!< 0x00000020 */
+#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk              
+#define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)                              
+#define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk          
+#define RCC_CIFR_CSSF_Pos                    (8U)                              
+#define RCC_CIFR_CSSF_Msk                    (0x1U << RCC_CIFR_CSSF_Pos)       /*!< 0x00000100 */
+#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk                 
+#define RCC_CIFR_LSECSSF_Pos                 (9U)                              
+#define RCC_CIFR_LSECSSF_Msk                 (0x1U << RCC_CIFR_LSECSSF_Pos)    /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk              
+#define RCC_CIFR_HSI48RDYF_Pos               (10U)                             
+#define RCC_CIFR_HSI48RDYF_Msk               (0x1U << RCC_CIFR_HSI48RDYF_Pos)  /*!< 0x00000400 */
+#define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk            
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                 (0U)                              
+#define RCC_CICR_LSIRDYC_Msk                 (0x1U << RCC_CICR_LSIRDYC_Pos)    /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk              
+#define RCC_CICR_LSERDYC_Pos                 (1U)                              
+#define RCC_CICR_LSERDYC_Msk                 (0x1U << RCC_CICR_LSERDYC_Pos)    /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk              
+#define RCC_CICR_MSIRDYC_Pos                 (2U)                              
+#define RCC_CICR_MSIRDYC_Msk                 (0x1U << RCC_CICR_MSIRDYC_Pos)    /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk              
+#define RCC_CICR_HSIRDYC_Pos                 (3U)                              
+#define RCC_CICR_HSIRDYC_Msk                 (0x1U << RCC_CICR_HSIRDYC_Pos)    /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk              
+#define RCC_CICR_HSERDYC_Pos                 (4U)                              
+#define RCC_CICR_HSERDYC_Msk                 (0x1U << RCC_CICR_HSERDYC_Pos)    /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk              
+#define RCC_CICR_PLLRDYC_Pos                 (5U)                              
+#define RCC_CICR_PLLRDYC_Msk                 (0x1U << RCC_CICR_PLLRDYC_Pos)    /*!< 0x00000020 */
+#define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk              
+#define RCC_CICR_PLLSAI1RDYC_Pos             (6U)                              
+#define RCC_CICR_PLLSAI1RDYC_Msk             (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk          
+#define RCC_CICR_CSSC_Pos                    (8U)                              
+#define RCC_CICR_CSSC_Msk                    (0x1U << RCC_CICR_CSSC_Pos)       /*!< 0x00000100 */
+#define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk                 
+#define RCC_CICR_LSECSSC_Pos                 (9U)                              
+#define RCC_CICR_LSECSSC_Msk                 (0x1U << RCC_CICR_LSECSSC_Pos)    /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk              
+#define RCC_CICR_HSI48RDYC_Pos               (10U)                             
+#define RCC_CICR_HSI48RDYC_Msk               (0x1U << RCC_CICR_HSI48RDYC_Pos)  /*!< 0x00000400 */
+#define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk            
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)                              
+#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk          
+#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)                              
+#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk          
+#define RCC_AHB1RSTR_FLASHRST_Pos            (8U)                              
+#define RCC_AHB1RSTR_FLASHRST_Msk            (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk         
+#define RCC_AHB1RSTR_CRCRST_Pos              (12U)                             
+#define RCC_AHB1RSTR_CRCRST_Msk              (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk           
+#define RCC_AHB1RSTR_TSCRST_Pos              (16U)                             
+#define RCC_AHB1RSTR_TSCRST_Msk              (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk           
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_GPIOARST_Pos            (0U)                              
+#define RCC_AHB2RSTR_GPIOARST_Msk            (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk         
+#define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)                              
+#define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk         
+#define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)                              
+#define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk         
+#define RCC_AHB2RSTR_GPIODRST_Pos            (3U)                              
+#define RCC_AHB2RSTR_GPIODRST_Msk            (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk         
+#define RCC_AHB2RSTR_GPIOERST_Pos            (4U)                              
+#define RCC_AHB2RSTR_GPIOERST_Msk            (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk         
+#define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)                              
+#define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk         
+#define RCC_AHB2RSTR_ADCRST_Pos              (13U)                             
+#define RCC_AHB2RSTR_ADCRST_Msk              (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
+#define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk           
+#define RCC_AHB2RSTR_RNGRST_Pos              (18U)                             
+#define RCC_AHB2RSTR_RNGRST_Msk              (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
+#define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk           
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define RCC_AHB3RSTR_QSPIRST_Pos             (8U)                              
+#define RCC_AHB3RSTR_QSPIRST_Msk             (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk          
+
+/********************  Bit definition for RCC_APB1RSTR1 register  **************/
+#define RCC_APB1RSTR1_TIM2RST_Pos            (0U)                              
+#define RCC_APB1RSTR1_TIM2RST_Msk            (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk         
+#define RCC_APB1RSTR1_TIM6RST_Pos            (4U)                              
+#define RCC_APB1RSTR1_TIM6RST_Msk            (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk         
+#define RCC_APB1RSTR1_TIM7RST_Pos            (5U)                              
+#define RCC_APB1RSTR1_TIM7RST_Msk            (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk         
+#define RCC_APB1RSTR1_LCDRST_Pos             (9U)                              
+#define RCC_APB1RSTR1_LCDRST_Msk             (0x1U << RCC_APB1RSTR1_LCDRST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTR1_LCDRST                 RCC_APB1RSTR1_LCDRST_Msk          
+#define RCC_APB1RSTR1_SPI2RST_Pos            (14U)                             
+#define RCC_APB1RSTR1_SPI2RST_Msk            (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk         
+#define RCC_APB1RSTR1_SPI3RST_Pos            (15U)                             
+#define RCC_APB1RSTR1_SPI3RST_Msk            (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk         
+#define RCC_APB1RSTR1_USART2RST_Pos          (17U)                             
+#define RCC_APB1RSTR1_USART2RST_Msk          (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk       
+#define RCC_APB1RSTR1_USART3RST_Pos          (18U)                             
+#define RCC_APB1RSTR1_USART3RST_Msk          (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk       
+#define RCC_APB1RSTR1_I2C1RST_Pos            (21U)                             
+#define RCC_APB1RSTR1_I2C1RST_Msk            (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk         
+#define RCC_APB1RSTR1_I2C2RST_Pos            (22U)                             
+#define RCC_APB1RSTR1_I2C2RST_Msk            (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk         
+#define RCC_APB1RSTR1_I2C3RST_Pos            (23U)                             
+#define RCC_APB1RSTR1_I2C3RST_Msk            (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk         
+#define RCC_APB1RSTR1_CRSRST_Pos             (24U)                             
+#define RCC_APB1RSTR1_CRSRST_Msk             (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
+#define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk          
+#define RCC_APB1RSTR1_CAN1RST_Pos            (25U)                             
+#define RCC_APB1RSTR1_CAN1RST_Msk            (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk         
+#define RCC_APB1RSTR1_USBFSRST_Pos           (26U)                             
+#define RCC_APB1RSTR1_USBFSRST_Msk           (0x1U << RCC_APB1RSTR1_USBFSRST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR1_USBFSRST               RCC_APB1RSTR1_USBFSRST_Msk        
+#define RCC_APB1RSTR1_PWRRST_Pos             (28U)                             
+#define RCC_APB1RSTR1_PWRRST_Msk             (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk          
+#define RCC_APB1RSTR1_DAC1RST_Pos            (29U)                             
+#define RCC_APB1RSTR1_DAC1RST_Msk            (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk         
+#define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)                             
+#define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk        
+#define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)                             
+#define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk       
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)                              
+#define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk      
+#define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)                              
+#define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk       
+#define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)                              
+#define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk       
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)                              
+#define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk        
+#define RCC_APB2RSTR_SDMMC1RST_Pos           (10U)                             
+#define RCC_APB2RSTR_SDMMC1RST_Msk           (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_SDMMC1RST               RCC_APB2RSTR_SDMMC1RST_Msk        
+#define RCC_APB2RSTR_TIM1RST_Pos             (11U)                             
+#define RCC_APB2RSTR_TIM1RST_Msk             (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          
+#define RCC_APB2RSTR_SPI1RST_Pos             (12U)                             
+#define RCC_APB2RSTR_SPI1RST_Msk             (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          
+#define RCC_APB2RSTR_USART1RST_Pos           (14U)                             
+#define RCC_APB2RSTR_USART1RST_Msk           (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        
+#define RCC_APB2RSTR_TIM15RST_Pos            (16U)                             
+#define RCC_APB2RSTR_TIM15RST_Msk            (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk         
+#define RCC_APB2RSTR_TIM16RST_Pos            (17U)                             
+#define RCC_APB2RSTR_TIM16RST_Msk            (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk         
+#define RCC_APB2RSTR_SAI1RST_Pos             (21U)                             
+#define RCC_APB2RSTR_SAI1RST_Msk             (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk          
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos               (0U)                              
+#define RCC_AHB1ENR_DMA1EN_Msk               (0x1U << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk            
+#define RCC_AHB1ENR_DMA2EN_Pos               (1U)                              
+#define RCC_AHB1ENR_DMA2EN_Msk               (0x1U << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk            
+#define RCC_AHB1ENR_FLASHEN_Pos              (8U)                              
+#define RCC_AHB1ENR_FLASHEN_Msk              (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk           
+#define RCC_AHB1ENR_CRCEN_Pos                (12U)                             
+#define RCC_AHB1ENR_CRCEN_Msk                (0x1U << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk             
+#define RCC_AHB1ENR_TSCEN_Pos                (16U)                             
+#define RCC_AHB1ENR_TSCEN_Msk                (0x1U << RCC_AHB1ENR_TSCEN_Pos)   /*!< 0x00010000 */
+#define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk             
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_GPIOAEN_Pos              (0U)                              
+#define RCC_AHB2ENR_GPIOAEN_Msk              (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk           
+#define RCC_AHB2ENR_GPIOBEN_Pos              (1U)                              
+#define RCC_AHB2ENR_GPIOBEN_Msk              (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk           
+#define RCC_AHB2ENR_GPIOCEN_Pos              (2U)                              
+#define RCC_AHB2ENR_GPIOCEN_Msk              (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk           
+#define RCC_AHB2ENR_GPIODEN_Pos              (3U)                              
+#define RCC_AHB2ENR_GPIODEN_Msk              (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk           
+#define RCC_AHB2ENR_GPIOEEN_Pos              (4U)                              
+#define RCC_AHB2ENR_GPIOEEN_Msk              (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk           
+#define RCC_AHB2ENR_GPIOHEN_Pos              (7U)                              
+#define RCC_AHB2ENR_GPIOHEN_Msk              (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk           
+#define RCC_AHB2ENR_ADCEN_Pos                (13U)                             
+#define RCC_AHB2ENR_ADCEN_Msk                (0x1U << RCC_AHB2ENR_ADCEN_Pos)   /*!< 0x00002000 */
+#define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk             
+#define RCC_AHB2ENR_RNGEN_Pos                (18U)                             
+#define RCC_AHB2ENR_RNGEN_Msk                (0x1U << RCC_AHB2ENR_RNGEN_Pos)   /*!< 0x00040000 */
+#define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk             
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define RCC_AHB3ENR_QSPIEN_Pos               (8U)                              
+#define RCC_AHB3ENR_QSPIEN_Msk               (0x1U << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk            
+
+/********************  Bit definition for RCC_APB1ENR1 register  ***************/
+#define RCC_APB1ENR1_TIM2EN_Pos              (0U)                              
+#define RCC_APB1ENR1_TIM2EN_Msk              (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk           
+#define RCC_APB1ENR1_TIM6EN_Pos              (4U)                              
+#define RCC_APB1ENR1_TIM6EN_Msk              (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk           
+#define RCC_APB1ENR1_TIM7EN_Pos              (5U)                              
+#define RCC_APB1ENR1_TIM7EN_Msk              (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk           
+#define RCC_APB1ENR1_LCDEN_Pos               (9U)                              
+#define RCC_APB1ENR1_LCDEN_Msk               (0x1U << RCC_APB1ENR1_LCDEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1ENR1_LCDEN                   RCC_APB1ENR1_LCDEN_Msk            
+#define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)                             
+#define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk         
+#define RCC_APB1ENR1_WWDGEN_Pos              (11U)                             
+#define RCC_APB1ENR1_WWDGEN_Msk              (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk           
+#define RCC_APB1ENR1_SPI2EN_Pos              (14U)                             
+#define RCC_APB1ENR1_SPI2EN_Msk              (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk           
+#define RCC_APB1ENR1_SPI3EN_Pos              (15U)                             
+#define RCC_APB1ENR1_SPI3EN_Msk              (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk           
+#define RCC_APB1ENR1_USART2EN_Pos            (17U)                             
+#define RCC_APB1ENR1_USART2EN_Msk            (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk         
+#define RCC_APB1ENR1_USART3EN_Pos            (18U)                             
+#define RCC_APB1ENR1_USART3EN_Msk            (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk         
+#define RCC_APB1ENR1_I2C1EN_Pos              (21U)                             
+#define RCC_APB1ENR1_I2C1EN_Msk              (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk           
+#define RCC_APB1ENR1_I2C2EN_Pos              (22U)                             
+#define RCC_APB1ENR1_I2C2EN_Msk              (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk           
+#define RCC_APB1ENR1_I2C3EN_Pos              (23U)                             
+#define RCC_APB1ENR1_I2C3EN_Msk              (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk           
+#define RCC_APB1ENR1_CRSEN_Pos               (24U)                             
+#define RCC_APB1ENR1_CRSEN_Msk               (0x1U << RCC_APB1ENR1_CRSEN_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk            
+#define RCC_APB1ENR1_CAN1EN_Pos              (25U)                             
+#define RCC_APB1ENR1_CAN1EN_Msk              (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk           
+#define RCC_APB1ENR1_USBFSEN_Pos             (26U)                             
+#define RCC_APB1ENR1_USBFSEN_Msk             (0x1U << RCC_APB1ENR1_USBFSEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR1_USBFSEN                 RCC_APB1ENR1_USBFSEN_Msk          
+#define RCC_APB1ENR1_PWREN_Pos               (28U)                             
+#define RCC_APB1ENR1_PWREN_Msk               (0x1U << RCC_APB1ENR1_PWREN_Pos)  /*!< 0x10000000 */
+#define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk            
+#define RCC_APB1ENR1_DAC1EN_Pos              (29U)                             
+#define RCC_APB1ENR1_DAC1EN_Msk              (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk           
+#define RCC_APB1ENR1_OPAMPEN_Pos             (30U)                             
+#define RCC_APB1ENR1_OPAMPEN_Msk             (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk          
+#define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)                             
+#define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk         
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1ENR2_LPUART1EN_Pos           (0U)                              
+#define RCC_APB1ENR2_LPUART1EN_Msk           (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk        
+#define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)                              
+#define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk         
+#define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)                              
+#define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk         
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_SYSCFGEN_Pos             (0U)                              
+#define RCC_APB2ENR_SYSCFGEN_Msk             (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk          
+#define RCC_APB2ENR_FWEN_Pos                 (7U)                              
+#define RCC_APB2ENR_FWEN_Msk                 (0x1U << RCC_APB2ENR_FWEN_Pos)    /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk              
+#define RCC_APB2ENR_SDMMC1EN_Pos             (10U)                             
+#define RCC_APB2ENR_SDMMC1EN_Msk             (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_SDMMC1EN                 RCC_APB2ENR_SDMMC1EN_Msk          
+#define RCC_APB2ENR_TIM1EN_Pos               (11U)                             
+#define RCC_APB2ENR_TIM1EN_Msk               (0x1U << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            
+#define RCC_APB2ENR_SPI1EN_Pos               (12U)                             
+#define RCC_APB2ENR_SPI1EN_Msk               (0x1U << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            
+#define RCC_APB2ENR_USART1EN_Pos             (14U)                             
+#define RCC_APB2ENR_USART1EN_Msk             (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          
+#define RCC_APB2ENR_TIM15EN_Pos              (16U)                             
+#define RCC_APB2ENR_TIM15EN_Msk              (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk           
+#define RCC_APB2ENR_TIM16EN_Pos              (17U)                             
+#define RCC_APB2ENR_TIM16EN_Msk              (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk           
+#define RCC_APB2ENR_SAI1EN_Pos               (21U)                             
+#define RCC_APB2ENR_SAI1EN_Msk               (0x1U << RCC_APB2ENR_SAI1EN_Pos)  /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk            
+
+/********************  Bit definition for RCC_AHB1SMENR register  ***************/
+#define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)                              
+#define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk        
+#define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)                              
+#define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk        
+#define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)                              
+#define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk       
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)                              
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk       
+#define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)                             
+#define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk         
+#define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)                             
+#define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB2SMENR register  *************/
+#define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)                              
+#define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk       
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)                              
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)                              
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk       
+#define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)                              
+#define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)                              
+#define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk       
+#define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)                              
+#define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk       
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)                              
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk       
+#define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)                             
+#define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk         
+#define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)                             
+#define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB3SMENR register  *************/
+#define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)                              
+#define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk        
+
+/********************  Bit definition for RCC_APB1SMENR1 register  *************/
+#define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)                              
+#define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk       
+#define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)                              
+#define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk       
+#define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)                              
+#define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk       
+#define RCC_APB1SMENR1_LCDSMEN_Pos           (9U)                              
+#define RCC_APB1SMENR1_LCDSMEN_Msk           (0x1U << RCC_APB1SMENR1_LCDSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1SMENR1_LCDSMEN               RCC_APB1SMENR1_LCDSMEN_Msk        
+#define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)                             
+#define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk     
+#define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)                             
+#define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk       
+#define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)                             
+#define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk       
+#define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)                             
+#define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk       
+#define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)                             
+#define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk     
+#define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)                             
+#define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk     
+#define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)                             
+#define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk       
+#define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)                             
+#define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk       
+#define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)                             
+#define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk       
+#define RCC_APB1SMENR1_CRSSMEN_Pos           (24U)                             
+#define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk        
+#define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)                             
+#define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk       
+#define RCC_APB1SMENR1_USBFSSMEN_Pos         (26U)                             
+#define RCC_APB1SMENR1_USBFSSMEN_Msk         (0x1U << RCC_APB1SMENR1_USBFSSMEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1SMENR1_USBFSSMEN             RCC_APB1SMENR1_USBFSSMEN_Msk      
+#define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)                             
+#define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk        
+#define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)                             
+#define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk       
+#define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)                             
+#define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk      
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)                             
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk     
+
+/********************  Bit definition for RCC_APB1SMENR2 register  *************/
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)                              
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk    
+#define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)                              
+#define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk     
+#define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)                              
+#define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk     
+
+/********************  Bit definition for RCC_APB2SMENR register  *************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)                              
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk      
+#define RCC_APB2SMENR_SDMMC1SMEN_Pos         (10U)                             
+#define RCC_APB2SMENR_SDMMC1SMEN_Msk         (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2SMENR_SDMMC1SMEN             RCC_APB2SMENR_SDMMC1SMEN_Msk      
+#define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)                             
+#define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk        
+#define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)                             
+#define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk        
+#define RCC_APB2SMENR_USART1SMEN_Pos         (14U)                             
+#define RCC_APB2SMENR_USART1SMEN_Msk         (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk      
+#define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)                             
+#define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk       
+#define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)                             
+#define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk       
+#define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)                             
+#define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk        
+
+/********************  Bit definition for RCC_CCIPR register  ******************/
+#define RCC_CCIPR_USART1SEL_Pos              (0U)                              
+#define RCC_CCIPR_USART1SEL_Msk              (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk           
+#define RCC_CCIPR_USART1SEL_0                (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1                (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+#define RCC_CCIPR_USART2SEL_Pos              (2U)                              
+#define RCC_CCIPR_USART2SEL_Msk              (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk           
+#define RCC_CCIPR_USART2SEL_0                (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1                (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+#define RCC_CCIPR_USART3SEL_Pos              (4U)                              
+#define RCC_CCIPR_USART3SEL_Msk              (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
+#define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk           
+#define RCC_CCIPR_USART3SEL_0                (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
+#define RCC_CCIPR_USART3SEL_1                (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_CCIPR_LPUART1SEL_Pos             (10U)                             
+#define RCC_CCIPR_LPUART1SEL_Msk             (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk          
+#define RCC_CCIPR_LPUART1SEL_0               (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR_LPUART1SEL_1               (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
+
+#define RCC_CCIPR_I2C1SEL_Pos                (12U)                             
+#define RCC_CCIPR_I2C1SEL_Msk                (0x3U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk             
+#define RCC_CCIPR_I2C1SEL_0                  (0x1U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1                  (0x2U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
+
+#define RCC_CCIPR_I2C2SEL_Pos                (14U)                             
+#define RCC_CCIPR_I2C2SEL_Msk                (0x3U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */
+#define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk             
+#define RCC_CCIPR_I2C2SEL_0                  (0x1U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */
+#define RCC_CCIPR_I2C2SEL_1                  (0x2U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */
+
+#define RCC_CCIPR_I2C3SEL_Pos                (16U)                             
+#define RCC_CCIPR_I2C3SEL_Msk                (0x3U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk             
+#define RCC_CCIPR_I2C3SEL_0                  (0x1U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1                  (0x2U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
+
+#define RCC_CCIPR_LPTIM1SEL_Pos              (18U)                             
+#define RCC_CCIPR_LPTIM1SEL_Msk              (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk           
+#define RCC_CCIPR_LPTIM1SEL_0                (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1                (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+#define RCC_CCIPR_LPTIM2SEL_Pos              (20U)                             
+#define RCC_CCIPR_LPTIM2SEL_Msk              (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk           
+#define RCC_CCIPR_LPTIM2SEL_0                (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR_LPTIM2SEL_1                (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
+
+#define RCC_CCIPR_SAI1SEL_Pos                (22U)                             
+#define RCC_CCIPR_SAI1SEL_Msk                (0x3U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00C00000 */
+#define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk             
+#define RCC_CCIPR_SAI1SEL_0                  (0x1U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00400000 */
+#define RCC_CCIPR_SAI1SEL_1                  (0x2U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00800000 */
+
+#define RCC_CCIPR_CLK48SEL_Pos               (26U)                             
+#define RCC_CCIPR_CLK48SEL_Msk               (0x3U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x0C000000 */
+#define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk            
+#define RCC_CCIPR_CLK48SEL_0                 (0x1U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x04000000 */
+#define RCC_CCIPR_CLK48SEL_1                 (0x2U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x08000000 */
+
+#define RCC_CCIPR_ADCSEL_Pos                 (28U)                             
+#define RCC_CCIPR_ADCSEL_Msk                 (0x3U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
+#define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk              
+#define RCC_CCIPR_ADCSEL_0                   (0x1U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
+#define RCC_CCIPR_ADCSEL_1                   (0x2U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
+
+#define RCC_CCIPR_SWPMI1SEL_Pos              (30U)                             
+#define RCC_CCIPR_SWPMI1SEL_Msk              (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
+#define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk           
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                   (0U)                              
+#define RCC_BDCR_LSEON_Msk                   (0x1U << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                
+#define RCC_BDCR_LSERDY_Pos                  (1U)                              
+#define RCC_BDCR_LSERDY_Msk                  (0x1U << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               
+#define RCC_BDCR_LSEBYP_Pos                  (2U)                              
+#define RCC_BDCR_LSEBYP_Msk                  (0x1U << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               
+
+#define RCC_BDCR_LSEDRV_Pos                  (3U)                              
+#define RCC_BDCR_LSEDRV_Msk                  (0x3U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk               
+#define RCC_BDCR_LSEDRV_0                    (0x1U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                    (0x2U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                (5U)                              
+#define RCC_BDCR_LSECSSON_Msk                (0x1U << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk             
+#define RCC_BDCR_LSECSSD_Pos                 (6U)                              
+#define RCC_BDCR_LSECSSD_Msk                 (0x1U << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk              
+
+#define RCC_BDCR_RTCSEL_Pos                  (8U)                              
+#define RCC_BDCR_RTCSEL_Msk                  (0x3U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               
+#define RCC_BDCR_RTCSEL_0                    (0x1U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                   (15U)                             
+#define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                
+#define RCC_BDCR_BDRST_Pos                   (16U)                             
+#define RCC_BDCR_BDRST_Msk                   (0x1U << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                
+#define RCC_BDCR_LSCOEN_Pos                  (24U)                             
+#define RCC_BDCR_LSCOEN_Msk                  (0x1U << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
+#define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk               
+#define RCC_BDCR_LSCOSEL_Pos                 (25U)                             
+#define RCC_BDCR_LSCOSEL_Msk                 (0x1U << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
+#define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk              
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                    (0U)                              
+#define RCC_CSR_LSION_Msk                    (0x1U << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
+#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 
+#define RCC_CSR_LSIRDY_Pos                   (1U)                              
+#define RCC_CSR_LSIRDY_Msk                   (0x1U << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                
+
+#define RCC_CSR_MSISRANGE_Pos                (8U)                              
+#define RCC_CSR_MSISRANGE_Msk                (0xFU << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000F00 */
+#define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk             
+#define RCC_CSR_MSISRANGE_1                  (0x4U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_2                  (0x5U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000500 */
+#define RCC_CSR_MSISRANGE_4                  (0x6U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000600 */
+#define RCC_CSR_MSISRANGE_8                  (0x7U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000700 */
+
+#define RCC_CSR_RMVF_Pos                     (23U)                             
+#define RCC_CSR_RMVF_Msk                     (0x1U << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
+#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  
+#define RCC_CSR_FWRSTF_Pos                   (24U)                             
+#define RCC_CSR_FWRSTF_Msk                   (0x1U << RCC_CSR_FWRSTF_Pos)      /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk                
+#define RCC_CSR_OBLRSTF_Pos                  (25U)                             
+#define RCC_CSR_OBLRSTF_Msk                  (0x1U << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk               
+#define RCC_CSR_PINRSTF_Pos                  (26U)                             
+#define RCC_CSR_PINRSTF_Msk                  (0x1U << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               
+#define RCC_CSR_BORRSTF_Pos                  (27U)                             
+#define RCC_CSR_BORRSTF_Msk                  (0x1U << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
+#define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk               
+#define RCC_CSR_SFTRSTF_Pos                  (28U)                             
+#define RCC_CSR_SFTRSTF_Msk                  (0x1U << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               
+#define RCC_CSR_IWDGRSTF_Pos                 (29U)                             
+#define RCC_CSR_IWDGRSTF_Msk                 (0x1U << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              
+#define RCC_CSR_WWDGRSTF_Pos                 (30U)                             
+#define RCC_CSR_WWDGRSTF_Msk                 (0x1U << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              
+#define RCC_CSR_LPWRRSTF_Pos                 (31U)                             
+#define RCC_CSR_LPWRRSTF_Msk                 (0x1U << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+#define RCC_CRRCR_HSI48ON_Pos                (0U)                              
+#define RCC_CRRCR_HSI48ON_Msk                (0x1U << RCC_CRRCR_HSI48ON_Pos)   /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk             
+#define RCC_CRRCR_HSI48RDY_Pos               (1U)                              
+#define RCC_CRRCR_HSI48RDY_Msk               (0x1U << RCC_CRRCR_HSI48RDY_Pos)  /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk            
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos               (7U)                             
+#define RCC_CRRCR_HSI48CAL_Msk               (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
+#define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
+#define RCC_CRRCR_HSI48CAL_0                 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_1                 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_2                 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
+#define RCC_CRRCR_HSI48CAL_3                 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
+#define RCC_CRRCR_HSI48CAL_4                 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
+#define RCC_CRRCR_HSI48CAL_5                 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
+#define RCC_CRRCR_HSI48CAL_6                 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
+#define RCC_CRRCR_HSI48CAL_7                 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
+#define RCC_CRRCR_HSI48CAL_8                 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)                                               
+#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
+#define RNG_CR_IE_Pos       (3U)                                               
+#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk                                      
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)                                               
+#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
+#define RNG_SR_CECS_Pos     (1U)                                               
+#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
+#define RNG_SR_SECS_Pos     (2U)                                               
+#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
+#define RNG_SR_CEIS_Pos     (5U)                                               
+#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
+#define RNG_SR_SEIS_Pos     (6U)                                               
+#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)                                   
+#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk                           
+#define RTC_TR_HT_Pos                  (20U)                                   
+#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk                           
+#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)                                   
+#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk                           
+#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)                                   
+#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          
+#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)                                    
+#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          
+#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)                                    
+#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk                           
+#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)                                    
+#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk                           
+#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)                                   
+#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk                           
+#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)                                   
+#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk                           
+#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)                                   
+#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          
+#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)                                   
+#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk                           
+#define RTC_DR_MU_Pos                  (8U)                                    
+#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk                           
+#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)                                    
+#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk                           
+#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)                                    
+#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk                           
+#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)                                   
+#define RTC_CR_ITSE_Msk                (0x1U << RTC_CR_ITSE_Pos)               /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk                         
+#define RTC_CR_COE_Pos                 (23U)                                   
+#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk                          
+#define RTC_CR_OSEL_Pos                (21U)                                   
+#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         
+#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)                                   
+#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk                          
+#define RTC_CR_COSEL_Pos               (19U)                                   
+#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        
+#define RTC_CR_BKP_Pos                 (18U)                                   
+#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          
+#define RTC_CR_SUB1H_Pos               (17U)                                   
+#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        
+#define RTC_CR_ADD1H_Pos               (16U)                                   
+#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        
+#define RTC_CR_TSIE_Pos                (15U)                                   
+#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         
+#define RTC_CR_WUTIE_Pos               (14U)                                   
+#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        
+#define RTC_CR_ALRBIE_Pos              (13U)                                   
+#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       
+#define RTC_CR_ALRAIE_Pos              (12U)                                   
+#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       
+#define RTC_CR_TSE_Pos                 (11U)                                   
+#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          
+#define RTC_CR_WUTE_Pos                (10U)                                   
+#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         
+#define RTC_CR_ALRBE_Pos               (9U)                                    
+#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        
+#define RTC_CR_ALRAE_Pos               (8U)                                    
+#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        
+#define RTC_CR_FMT_Pos                 (6U)                                    
+#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          
+#define RTC_CR_BYPSHAD_Pos             (5U)                                    
+#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      
+#define RTC_CR_REFCKON_Pos             (4U)                                    
+#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      
+#define RTC_CR_TSEDGE_Pos              (3U)                                    
+#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       
+#define RTC_CR_WUCKSEL_Pos             (0U)                                    
+#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      
+#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk
+#define RTC_CR_BCK                     RTC_CR_BKP
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)                                   
+#define RTC_ISR_ITSF_Msk               (0x1U << RTC_ISR_ITSF_Pos)              /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk                        
+#define RTC_ISR_RECALPF_Pos            (16U)                                   
+#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     
+#define RTC_ISR_TAMP3F_Pos             (15U)                                   
+#define RTC_ISR_TAMP3F_Msk             (0x1U << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      
+#define RTC_ISR_TAMP2F_Pos             (14U)                                   
+#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      
+#define RTC_ISR_TAMP1F_Pos             (13U)                                   
+#define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      
+#define RTC_ISR_TSOVF_Pos              (12U)                                   
+#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       
+#define RTC_ISR_TSF_Pos                (11U)                                   
+#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         
+#define RTC_ISR_WUTF_Pos               (10U)                                   
+#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        
+#define RTC_ISR_ALRBF_Pos              (9U)                                    
+#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       
+#define RTC_ISR_ALRAF_Pos              (8U)                                    
+#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       
+#define RTC_ISR_INIT_Pos               (7U)                                    
+#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        
+#define RTC_ISR_INITF_Pos              (6U)                                    
+#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       
+#define RTC_ISR_RSF_Pos                (5U)                                    
+#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         
+#define RTC_ISR_INITS_Pos              (4U)                                    
+#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       
+#define RTC_ISR_SHPF_Pos               (3U)                                    
+#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        
+#define RTC_ISR_WUTWF_Pos              (2U)                                    
+#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       
+#define RTC_ISR_ALRBWF_Pos             (1U)                                    
+#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      
+#define RTC_ISR_ALRAWF_Pos             (0U)                                    
+#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)                                   
+#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   
+#define RTC_PRER_PREDIV_S_Pos          (0U)                                    
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)                                    
+#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     
+#define RTC_ALRMAR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    
+#define RTC_ALRMAR_DT_Pos              (28U)                                   
+#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       
+#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)                                   
+#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       
+#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     
+#define RTC_ALRMAR_PM_Pos              (22U)                                   
+#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       
+#define RTC_ALRMAR_HT_Pos              (20U)                                   
+#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       
+#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)                                   
+#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       
+#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     
+#define RTC_ALRMAR_MNT_Pos             (12U)                                   
+#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      
+#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)                                    
+#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      
+#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     
+#define RTC_ALRMAR_ST_Pos              (4U)                                    
+#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       
+#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)                                    
+#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       
+#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     
+#define RTC_ALRMBR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    
+#define RTC_ALRMBR_DT_Pos              (28U)                                   
+#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       
+#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)                                   
+#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       
+#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     
+#define RTC_ALRMBR_PM_Pos              (22U)                                   
+#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       
+#define RTC_ALRMBR_HT_Pos              (20U)                                   
+#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       
+#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)                                   
+#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       
+#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     
+#define RTC_ALRMBR_MNT_Pos             (12U)                                   
+#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      
+#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)                                    
+#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      
+#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     
+#define RTC_ALRMBR_ST_Pos              (4U)                                    
+#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       
+#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)                                    
+#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       
+#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)                                    
+#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)                                    
+#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)                                    
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    
+#define RTC_SHIFTR_ADD1S_Pos           (31U)                                   
+#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)                                   
+#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         
+#define RTC_TSTR_HT_Pos                (20U)                                   
+#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         
+#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)                                   
+#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         
+#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)                                   
+#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        
+#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)                                    
+#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        
+#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)                                    
+#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         
+#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)                                    
+#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         
+#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)                                   
+#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        
+#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)                                   
+#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         
+#define RTC_TSDR_MU_Pos                (8U)                                    
+#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         
+#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)                                    
+#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         
+#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)                                    
+#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         
+#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)                                    
+#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)                                   
+#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       
+#define RTC_CALR_CALW8_Pos             (14U)                                   
+#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      
+#define RTC_CALR_CALW16_Pos            (13U)                                   
+#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     
+#define RTC_CALR_CALM_Pos              (0U)                                    
+#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       
+#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)                                   
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1U << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)                                   
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)                                   
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1U << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)                                   
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)                                   
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)                                   
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)                                   
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)                                   
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)                                   
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)                                   
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)                                   
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)                                   
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  
+#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)                                    
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)                                    
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)                                    
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1U << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)                                    
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1U << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)                                    
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)                                    
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)                                    
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)                                    
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)                                    
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
+#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)                                    
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
+#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)                                    
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
+
+/********************  Bits definition for RTC_0R register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)                                    
+#define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)                                    
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 
+
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)                                    
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk                           
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)                                    
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk                           
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)                                    
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk                           
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)                                    
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk                           
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)                                    
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk                           
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)                                    
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFU << RTC_BKP5R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk                           
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)                                    
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFU << RTC_BKP6R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk                           
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)                                    
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFU << RTC_BKP7R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk                           
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)                                    
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFU << RTC_BKP8R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk                           
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)                                    
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFU << RTC_BKP9R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk                           
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)                                    
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFU << RTC_BKP10R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk                          
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)                                    
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFU << RTC_BKP11R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk                          
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)                                    
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFU << RTC_BKP12R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk                          
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)                                    
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFU << RTC_BKP13R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk                          
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)                                    
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFU << RTC_BKP14R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk                          
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)                                    
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFU << RTC_BKP15R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk                          
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)                                    
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFU << RTC_BKP16R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk                          
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)                                    
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFU << RTC_BKP17R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk                          
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)                                    
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFU << RTC_BKP18R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk                          
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)                                    
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFU << RTC_BKP19R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk                          
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)                                    
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFU << RTC_BKP20R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk                          
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)                                    
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFU << RTC_BKP21R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk                          
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)                                    
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFU << RTC_BKP22R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk                          
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)                                    
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFU << RTC_BKP23R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk                          
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)                                    
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFU << RTC_BKP24R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk                          
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)                                    
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFU << RTC_BKP25R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk                          
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)                                    
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFU << RTC_BKP26R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk                          
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)                                    
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFU << RTC_BKP27R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk                          
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)                                    
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFU << RTC_BKP28R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk                          
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)                                    
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFU << RTC_BKP29R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk                          
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)                                    
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFU << RTC_BKP30R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk                          
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)                                    
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFU << RTC_BKP31R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk                          
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       32U
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)                                        
+#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)                                        
+#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)                                        
+#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)                                        
+#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)                                        
+#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)                                        
+#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)                                        
+#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)                                       
+#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)                                       
+#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)                                       
+#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)                                       
+#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)                                       
+#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)                                       
+#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)                                       
+#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)                                        
+#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)                                        
+#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)                                        
+#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)                                        
+#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)                                        
+#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)                                        
+#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)                                       
+#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos          (14U)                                       
+#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)                                        
+#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)                                        
+#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)                                       
+#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos        (17U)                                       
+#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)                                       
+#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)                                        
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)                                        
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)                                        
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)                                       
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)                                        
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)                                        
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)                                        
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)                                        
+#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)                                        
+#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)                                        
+#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)                                        
+#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)                                        
+#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)                                        
+#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)                                        
+#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)                                        
+#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)                                        
+#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)                                        
+#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)                                        
+#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)                                       
+#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)                                        
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)                                        
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)                                        
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)                                        
+#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)                                        
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)                                        
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)                                        
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos           (0U)                                        
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk                            
+
+/******************************************************************************/
+/*                                                                            */
+/*                          LCD Controller (LCD)                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for LCD_CR register  *********************/
+#define LCD_CR_LCDEN_Pos            (0U)                                       
+#define LCD_CR_LCDEN_Msk            (0x1U << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
+#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
+#define LCD_CR_VSEL_Pos             (1U)                                       
+#define LCD_CR_VSEL_Msk             (0x1U << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
+#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY_Pos             (2U)                                       
+#define LCD_CR_DUTY_Msk             (0x7U << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
+#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0               (0x1U << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
+#define LCD_CR_DUTY_1               (0x2U << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
+#define LCD_CR_DUTY_2               (0x4U << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
+
+#define LCD_CR_BIAS_Pos             (5U)                                       
+#define LCD_CR_BIAS_Msk             (0x3U << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
+#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0               (0x1U << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
+#define LCD_CR_BIAS_1               (0x2U << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
+
+#define LCD_CR_MUX_SEG_Pos          (7U)                                       
+#define LCD_CR_MUX_SEG_Msk          (0x1U << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
+#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
+#define LCD_CR_BUFEN_Pos            (8U)                                       
+#define LCD_CR_BUFEN_Msk            (0x1U << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
+#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable */
+
+/*******************  Bit definition for LCD_FCR register  ********************/
+#define LCD_FCR_HD_Pos              (0U)                                       
+#define LCD_FCR_HD_Msk              (0x1U << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
+#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE_Pos           (1U)                                       
+#define LCD_FCR_SOFIE_Msk           (0x1U << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
+#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE_Pos           (3U)                                       
+#define LCD_FCR_UDDIE_Msk           (0x1U << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
+#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON_Pos             (4U)                                       
+#define LCD_FCR_PON_Msk             (0x7U << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
+#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Pulse ON Duration) */
+#define LCD_FCR_PON_0               (0x1U << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
+#define LCD_FCR_PON_1               (0x2U << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
+#define LCD_FCR_PON_2               (0x4U << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
+
+#define LCD_FCR_DEAD_Pos            (7U)                                       
+#define LCD_FCR_DEAD_Msk            (0x7U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
+#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0              (0x1U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
+#define LCD_FCR_DEAD_1              (0x2U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
+#define LCD_FCR_DEAD_2              (0x4U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
+
+#define LCD_FCR_CC_Pos              (10U)                                      
+#define LCD_FCR_CC_Msk              (0x7U << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
+#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0                (0x1U << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
+#define LCD_FCR_CC_1                (0x2U << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
+#define LCD_FCR_CC_2                (0x4U << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
+
+#define LCD_FCR_BLINKF_Pos          (13U)                                      
+#define LCD_FCR_BLINKF_Msk          (0x7U << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
+#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0            (0x1U << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
+#define LCD_FCR_BLINKF_1            (0x2U << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
+#define LCD_FCR_BLINKF_2            (0x4U << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
+
+#define LCD_FCR_BLINK_Pos           (16U)                                      
+#define LCD_FCR_BLINK_Msk           (0x3U << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
+#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0             (0x1U << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
+#define LCD_FCR_BLINK_1             (0x2U << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
+
+#define LCD_FCR_DIV_Pos             (18U)                                      
+#define LCD_FCR_DIV_Msk             (0xFU << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
+#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS_Pos              (22U)                                      
+#define LCD_FCR_PS_Msk              (0xFU << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
+#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
+
+/*******************  Bit definition for LCD_SR register  *********************/
+#define LCD_SR_ENS_Pos              (0U)                                       
+#define LCD_SR_ENS_Msk              (0x1U << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
+#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
+#define LCD_SR_SOF_Pos              (1U)                                       
+#define LCD_SR_SOF_Msk              (0x1U << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
+#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR_Pos              (2U)                                       
+#define LCD_SR_UDR_Msk              (0x1U << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
+#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
+#define LCD_SR_UDD_Pos              (3U)                                       
+#define LCD_SR_UDD_Msk              (0x1U << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
+#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY_Pos              (4U)                                       
+#define LCD_SR_RDY_Msk              (0x1U << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
+#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR_Pos            (5U)                                       
+#define LCD_SR_FCRSR_Msk            (0x1U << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
+#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
+
+/*******************  Bit definition for LCD_CLR register  ********************/
+#define LCD_CLR_SOFC_Pos            (1U)                                       
+#define LCD_CLR_SOFC_Msk            (0x1U << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
+#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC_Pos            (3U)                                       
+#define LCD_CLR_UDDC_Msk            (0x1U << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
+#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
+
+/*******************  Bit definition for LCD_RAM register  ********************/
+#define LCD_RAM_SEGMENT_DATA_Pos    (0U)                                       
+#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
+#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos         (0U)                                   
+#define SDMMC_POWER_PWRCTRL_Msk         (0x3U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0           (0x1U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1           (0x2U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos          (0U)                                   
+#define SDMMC_CLKCR_CLKDIV_Msk          (0xFFU << SDMMC_CLKCR_CLKDIV_Pos)      /*!< 0x000000FF */
+#define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */
+#define SDMMC_CLKCR_CLKEN_Pos           (8U)                                   
+#define SDMMC_CLKCR_CLKEN_Msk           (0x1U << SDMMC_CLKCR_CLKEN_Pos)        /*!< 0x00000100 */
+#define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */
+#define SDMMC_CLKCR_PWRSAV_Pos          (9U)                                   
+#define SDMMC_CLKCR_PWRSAV_Msk          (0x1U << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00000200 */
+#define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */
+#define SDMMC_CLKCR_BYPASS_Pos          (10U)                                  
+#define SDMMC_CLKCR_BYPASS_Msk          (0x1U << SDMMC_CLKCR_BYPASS_Pos)       /*!< 0x00000400 */
+#define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */
+
+#define SDMMC_CLKCR_WIDBUS_Pos          (11U)                                  
+#define SDMMC_CLKCR_WIDBUS_Msk          (0x3U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001800 */
+#define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0            (0x1U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00000800 */
+#define SDMMC_CLKCR_WIDBUS_1            (0x2U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos         (13U)                                  
+#define SDMMC_CLKCR_NEGEDGE_Msk         (0x1U << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00002000 */
+#define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos         (14U)                                  
+#define SDMMC_CLKCR_HWFC_EN_Msk         (0x1U << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos            (0U)                                   
+#define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos          (0U)                                   
+#define SDMMC_CMD_CMDINDEX_Msk          (0x3FU << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */
+
+#define SDMMC_CMD_WAITRESP_Pos          (6U)                                   
+#define SDMMC_CMD_WAITRESP_Msk          (0x3U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x000000C0 */
+#define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0            (0x1U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000040 */
+#define SDMMC_CMD_WAITRESP_1            (0x2U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000080 */
+
+#define SDMMC_CMD_WAITINT_Pos           (8U)                                   
+#define SDMMC_CMD_WAITINT_Msk           (0x1U << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000100 */
+#define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos          (9U)                                   
+#define SDMMC_CMD_WAITPEND_Msk          (0x1U << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000200 */
+#define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos            (10U)                                  
+#define SDMMC_CMD_CPSMEN_Msk            (0x1U << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00000400 */
+#define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)                                  
+#define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos)    /*!< 0x00000800 */
+#define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos       (0U)                                   
+#define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)                                   
+#define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)                                   
+#define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)                                   
+#define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)                                   
+#define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos       (0U)                                   
+#define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos       (0U)                                   
+#define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos            (0U)                                   
+#define SDMMC_DCTRL_DTEN_Msk            (0x1U << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */
+#define SDMMC_DCTRL_DTDIR_Pos           (1U)                                   
+#define SDMMC_DCTRL_DTDIR_Msk           (0x1U << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */
+#define SDMMC_DCTRL_DTMODE_Pos          (2U)                                   
+#define SDMMC_DCTRL_DTMODE_Msk          (0x1U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */
+#define SDMMC_DCTRL_DMAEN_Pos           (3U)                                   
+#define SDMMC_DCTRL_DMAEN_Msk           (0x1U << SDMMC_DCTRL_DMAEN_Pos)        /*!< 0x00000008 */
+#define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)                                   
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos         (8U)                                   
+#define SDMMC_DCTRL_RWSTART_Msk         (0x1U << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */
+#define SDMMC_DCTRL_RWSTOP_Pos          (9U)                                   
+#define SDMMC_DCTRL_RWSTOP_Msk          (0x1U << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */
+#define SDMMC_DCTRL_RWMOD_Pos           (10U)                                  
+#define SDMMC_DCTRL_RWMOD_Msk           (0x1U << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */
+#define SDMMC_DCTRL_SDIOEN_Pos          (11U)                                  
+#define SDMMC_DCTRL_SDIOEN_Msk          (0x1U << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)                                   
+#define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos          (0U)                                   
+#define SDMMC_STA_CCRCFAIL_Msk          (0x1U << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos          (1U)                                   
+#define SDMMC_STA_DCRCFAIL_Msk          (0x1U << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos          (2U)                                   
+#define SDMMC_STA_CTIMEOUT_Msk          (0x1U << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos          (3U)                                   
+#define SDMMC_STA_DTIMEOUT_Msk          (0x1U << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos          (4U)                                   
+#define SDMMC_STA_TXUNDERR_Msk          (0x1U << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos           (5U)                                   
+#define SDMMC_STA_RXOVERR_Msk           (0x1U << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos           (6U)                                   
+#define SDMMC_STA_CMDREND_Msk           (0x1U << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos           (7U)                                   
+#define SDMMC_STA_CMDSENT_Msk           (0x1U << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos           (8U)                                   
+#define SDMMC_STA_DATAEND_Msk           (0x1U << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_STBITERR_Pos          (9U)                                   
+#define SDMMC_STA_STBITERR_Msk          (0x1U << SDMMC_STA_STBITERR_Pos)       /*!< 0x00000200 */
+#define SDMMC_STA_STBITERR              SDMMC_STA_STBITERR_Msk                 /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDMMC_STA_DBCKEND_Pos           (10U)                                  
+#define SDMMC_STA_DBCKEND_Msk           (0x1U << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_CMDACT_Pos            (11U)                                  
+#define SDMMC_STA_CMDACT_Msk            (0x1U << SDMMC_STA_CMDACT_Pos)         /*!< 0x00000800 */
+#define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */
+#define SDMMC_STA_TXACT_Pos             (12U)                                  
+#define SDMMC_STA_TXACT_Msk             (0x1U << SDMMC_STA_TXACT_Pos)          /*!< 0x00001000 */
+#define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */
+#define SDMMC_STA_RXACT_Pos             (13U)                                  
+#define SDMMC_STA_RXACT_Msk             (0x1U << SDMMC_STA_RXACT_Pos)          /*!< 0x00002000 */
+#define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */
+#define SDMMC_STA_TXFIFOHE_Pos          (14U)                                  
+#define SDMMC_STA_TXFIFOHE_Msk          (0x1U << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos          (15U)                                  
+#define SDMMC_STA_RXFIFOHF_Msk          (0x1U << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos           (16U)                                  
+#define SDMMC_STA_TXFIFOF_Msk           (0x1U << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos           (17U)                                  
+#define SDMMC_STA_RXFIFOF_Msk           (0x1U << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos           (18U)                                  
+#define SDMMC_STA_TXFIFOE_Msk           (0x1U << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos           (19U)                                  
+#define SDMMC_STA_RXFIFOE_Msk           (0x1U << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */
+#define SDMMC_STA_TXDAVL_Pos            (20U)                                  
+#define SDMMC_STA_TXDAVL_Msk            (0x1U << SDMMC_STA_TXDAVL_Pos)         /*!< 0x00100000 */
+#define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */
+#define SDMMC_STA_RXDAVL_Pos            (21U)                                  
+#define SDMMC_STA_RXDAVL_Msk            (0x1U << SDMMC_STA_RXDAVL_Pos)         /*!< 0x00200000 */
+#define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */
+#define SDMMC_STA_SDIOIT_Pos            (22U)                                  
+#define SDMMC_STA_SDIOIT_Msk            (0x1U << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDIO interrupt received                       */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos         (0U)                                   
+#define SDMMC_ICR_CCRCFAILC_Msk         (0x1U << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos         (1U)                                   
+#define SDMMC_ICR_DCRCFAILC_Msk         (0x1U << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos         (2U)                                   
+#define SDMMC_ICR_CTIMEOUTC_Msk         (0x1U << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos         (3U)                                   
+#define SDMMC_ICR_DTIMEOUTC_Msk         (0x1U << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos         (4U)                                   
+#define SDMMC_ICR_TXUNDERRC_Msk         (0x1U << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos          (5U)                                   
+#define SDMMC_ICR_RXOVERRC_Msk          (0x1U << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos          (6U)                                   
+#define SDMMC_ICR_CMDRENDC_Msk          (0x1U << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos          (7U)                                   
+#define SDMMC_ICR_CMDSENTC_Msk          (0x1U << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos          (8U)                                   
+#define SDMMC_ICR_DATAENDC_Msk          (0x1U << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_STBITERRC_Pos         (9U)                                   
+#define SDMMC_ICR_STBITERRC_Msk         (0x1U << SDMMC_ICR_STBITERRC_Pos)      /*!< 0x00000200 */
+#define SDMMC_ICR_STBITERRC             SDMMC_ICR_STBITERRC_Msk                /*!<STBITERR flag clear bit */
+#define SDMMC_ICR_DBCKENDC_Pos          (10U)                                  
+#define SDMMC_ICR_DBCKENDC_Msk          (0x1U << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos           (22U)                                  
+#define SDMMC_ICR_SDIOITC_Msk           (0x1U << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDIOIT flag clear bit   */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos       (0U)                                   
+#define SDMMC_MASK_CCRCFAILIE_Msk       (0x1U << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos       (1U)                                   
+#define SDMMC_MASK_DCRCFAILIE_Msk       (0x1U << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)                                   
+#define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)                                   
+#define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos       (4U)                                   
+#define SDMMC_MASK_TXUNDERRIE_Msk       (0x1U << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos        (5U)                                   
+#define SDMMC_MASK_RXOVERRIE_Msk        (0x1U << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos        (6U)                                   
+#define SDMMC_MASK_CMDRENDIE_Msk        (0x1U << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos        (7U)                                   
+#define SDMMC_MASK_CMDSENTIE_Msk        (0x1U << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos        (8U)                                   
+#define SDMMC_MASK_DATAENDIE_Msk        (0x1U << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DBCKENDIE_Pos        (10U)                                  
+#define SDMMC_MASK_DBCKENDIE_Msk        (0x1U << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_CMDACTIE_Pos         (11U)                                  
+#define SDMMC_MASK_CMDACTIE_Msk         (0x1U << SDMMC_MASK_CMDACTIE_Pos)      /*!< 0x00000800 */
+#define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */
+#define SDMMC_MASK_TXACTIE_Pos          (12U)                                  
+#define SDMMC_MASK_TXACTIE_Msk          (0x1U << SDMMC_MASK_TXACTIE_Pos)       /*!< 0x00001000 */
+#define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */
+#define SDMMC_MASK_RXACTIE_Pos          (13U)                                  
+#define SDMMC_MASK_RXACTIE_Msk          (0x1U << SDMMC_MASK_RXACTIE_Pos)       /*!< 0x00002000 */
+#define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */
+#define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)                                  
+#define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)                                  
+#define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDMMC_MASK_TXFIFOFIE_Pos        (16U)                                  
+#define SDMMC_MASK_TXFIFOFIE_Msk        (0x1U << SDMMC_MASK_TXFIFOFIE_Pos)     /*!< 0x00010000 */
+#define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_RXFIFOFIE_Pos        (17U)                                  
+#define SDMMC_MASK_RXFIFOFIE_Msk        (0x1U << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos        (18U)                                  
+#define SDMMC_MASK_TXFIFOEIE_Msk        (0x1U << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_RXFIFOEIE_Pos        (19U)                                  
+#define SDMMC_MASK_RXFIFOEIE_Msk        (0x1U << SDMMC_MASK_RXFIFOEIE_Pos)     /*!< 0x00080000 */
+#define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_TXDAVLIE_Pos         (20U)                                  
+#define SDMMC_MASK_TXDAVLIE_Msk         (0x1U << SDMMC_MASK_TXDAVLIE_Pos)      /*!< 0x00100000 */
+#define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */
+#define SDMMC_MASK_RXDAVLIE_Pos         (21U)                                  
+#define SDMMC_MASK_RXDAVLIE_Msk         (0x1U << SDMMC_MASK_RXDAVLIE_Pos)      /*!< 0x00200000 */
+#define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos         (22U)                                  
+#define SDMMC_MASK_SDIOITIE_Msk         (0x1U << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)                                   
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos         (0U)                                   
+#define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos         (0U)                                          
+#define SPI_CR1_CPHA_Msk         (0x1U << SPI_CR1_CPHA_Pos)                    /*!< 0x00000001 */
+#define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos         (1U)                                          
+#define SPI_CR1_CPOL_Msk         (0x1U << SPI_CR1_CPOL_Pos)                    /*!< 0x00000002 */
+#define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos         (2U)                                          
+#define SPI_CR1_MSTR_Msk         (0x1U << SPI_CR1_MSTR_Pos)                    /*!< 0x00000004 */
+#define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos           (3U)                                          
+#define SPI_CR1_BR_Msk           (0x7U << SPI_CR1_BR_Pos)                      /*!< 0x00000038 */
+#define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0             (0x1U << SPI_CR1_BR_Pos)                      /*!< 0x00000008 */
+#define SPI_CR1_BR_1             (0x2U << SPI_CR1_BR_Pos)                      /*!< 0x00000010 */
+#define SPI_CR1_BR_2             (0x4U << SPI_CR1_BR_Pos)                      /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos          (6U)                                          
+#define SPI_CR1_SPE_Msk          (0x1U << SPI_CR1_SPE_Pos)                     /*!< 0x00000040 */
+#define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos     (7U)                                          
+#define SPI_CR1_LSBFIRST_Msk     (0x1U << SPI_CR1_LSBFIRST_Pos)                /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos          (8U)                                          
+#define SPI_CR1_SSI_Msk          (0x1U << SPI_CR1_SSI_Pos)                     /*!< 0x00000100 */
+#define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos          (9U)                                          
+#define SPI_CR1_SSM_Msk          (0x1U << SPI_CR1_SSM_Pos)                     /*!< 0x00000200 */
+#define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos       (10U)                                         
+#define SPI_CR1_RXONLY_Msk       (0x1U << SPI_CR1_RXONLY_Pos)                  /*!< 0x00000400 */
+#define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */
+#define SPI_CR1_CRCL_Pos         (11U)                                         
+#define SPI_CR1_CRCL_Msk         (0x1U << SPI_CR1_CRCL_Pos)                    /*!< 0x00000800 */
+#define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos      (12U)                                         
+#define SPI_CR1_CRCNEXT_Msk      (0x1U << SPI_CR1_CRCNEXT_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos        (13U)                                         
+#define SPI_CR1_CRCEN_Msk        (0x1U << SPI_CR1_CRCEN_Pos)                   /*!< 0x00002000 */
+#define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos       (14U)                                         
+#define SPI_CR1_BIDIOE_Msk       (0x1U << SPI_CR1_BIDIOE_Pos)                  /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos     (15U)                                         
+#define SPI_CR1_BIDIMODE_Msk     (0x1U << SPI_CR1_BIDIMODE_Pos)                /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos      (0U)                                          
+#define SPI_CR2_RXDMAEN_Msk      (0x1U << SPI_CR2_RXDMAEN_Pos)                 /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos      (1U)                                          
+#define SPI_CR2_TXDMAEN_Msk      (0x1U << SPI_CR2_TXDMAEN_Pos)                 /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos         (2U)                                          
+#define SPI_CR2_SSOE_Msk         (0x1U << SPI_CR2_SSOE_Pos)                    /*!< 0x00000004 */
+#define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos         (3U)                                          
+#define SPI_CR2_NSSP_Msk         (0x1U << SPI_CR2_NSSP_Pos)                    /*!< 0x00000008 */
+#define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos          (4U)                                          
+#define SPI_CR2_FRF_Msk          (0x1U << SPI_CR2_FRF_Pos)                     /*!< 0x00000010 */
+#define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos        (5U)                                          
+#define SPI_CR2_ERRIE_Msk        (0x1U << SPI_CR2_ERRIE_Pos)                   /*!< 0x00000020 */
+#define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos       (6U)                                          
+#define SPI_CR2_RXNEIE_Msk       (0x1U << SPI_CR2_RXNEIE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos        (7U)                                          
+#define SPI_CR2_TXEIE_Msk        (0x1U << SPI_CR2_TXEIE_Pos)                   /*!< 0x00000080 */
+#define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos           (8U)                                          
+#define SPI_CR2_DS_Msk           (0xFU << SPI_CR2_DS_Pos)                      /*!< 0x00000F00 */
+#define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0             (0x1U << SPI_CR2_DS_Pos)                      /*!< 0x00000100 */
+#define SPI_CR2_DS_1             (0x2U << SPI_CR2_DS_Pos)                      /*!< 0x00000200 */
+#define SPI_CR2_DS_2             (0x4U << SPI_CR2_DS_Pos)                      /*!< 0x00000400 */
+#define SPI_CR2_DS_3             (0x8U << SPI_CR2_DS_Pos)                      /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos        (12U)                                         
+#define SPI_CR2_FRXTH_Msk        (0x1U << SPI_CR2_FRXTH_Pos)                   /*!< 0x00001000 */
+#define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos       (13U)                                         
+#define SPI_CR2_LDMARX_Msk       (0x1U << SPI_CR2_LDMARX_Pos)                  /*!< 0x00002000 */
+#define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos       (14U)                                         
+#define SPI_CR2_LDMATX_Msk       (0x1U << SPI_CR2_LDMATX_Pos)                  /*!< 0x00004000 */
+#define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos          (0U)                                          
+#define SPI_SR_RXNE_Msk          (0x1U << SPI_SR_RXNE_Pos)                     /*!< 0x00000001 */
+#define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos           (1U)                                          
+#define SPI_SR_TXE_Msk           (0x1U << SPI_SR_TXE_Pos)                      /*!< 0x00000002 */
+#define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos        (2U)                                          
+#define SPI_SR_CHSIDE_Msk        (0x1U << SPI_SR_CHSIDE_Pos)                   /*!< 0x00000004 */
+#define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */
+#define SPI_SR_UDR_Pos           (3U)                                          
+#define SPI_SR_UDR_Msk           (0x1U << SPI_SR_UDR_Pos)                      /*!< 0x00000008 */
+#define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos        (4U)                                          
+#define SPI_SR_CRCERR_Msk        (0x1U << SPI_SR_CRCERR_Pos)                   /*!< 0x00000010 */
+#define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos          (5U)                                          
+#define SPI_SR_MODF_Msk          (0x1U << SPI_SR_MODF_Pos)                     /*!< 0x00000020 */
+#define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */
+#define SPI_SR_OVR_Pos           (6U)                                          
+#define SPI_SR_OVR_Msk           (0x1U << SPI_SR_OVR_Pos)                      /*!< 0x00000040 */
+#define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */
+#define SPI_SR_BSY_Pos           (7U)                                          
+#define SPI_SR_BSY_Msk           (0x1U << SPI_SR_BSY_Pos)                      /*!< 0x00000080 */
+#define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */
+#define SPI_SR_FRE_Pos           (8U)                                          
+#define SPI_SR_FRE_Msk           (0x1U << SPI_SR_FRE_Pos)                      /*!< 0x00000100 */
+#define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos         (9U)                                          
+#define SPI_SR_FRLVL_Msk         (0x3U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000600 */
+#define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0           (0x1U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1           (0x2U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos         (11U)                                         
+#define SPI_SR_FTLVL_Msk         (0x3U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001800 */
+#define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0           (0x1U << SPI_SR_FTLVL_Pos)                    /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1           (0x2U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001000 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos            (0U)                                          
+#define SPI_DR_DR_Msk            (0xFFFFU << SPI_DR_DR_Pos)                    /*!< 0x0000FFFF */
+#define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos    (0U)                                          
+#define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)            /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos     (0U)                                          
+#define SPI_RXCRCR_RXCRC_Msk     (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos     (0U)                                          
+#define SPI_TXCRCR_TXCRC_Msk     (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos              (0U)                                    
+#define QUADSPI_CR_EN_Msk              (0x1U << QUADSPI_CR_EN_Pos)             /*!< 0x00000001 */
+#define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos           (1U)                                    
+#define QUADSPI_CR_ABORT_Msk           (0x1U << QUADSPI_CR_ABORT_Pos)          /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos           (2U)                                    
+#define QUADSPI_CR_DMAEN_Msk           (0x1U << QUADSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos            (3U)                                    
+#define QUADSPI_CR_TCEN_Msk            (0x1U << QUADSPI_CR_TCEN_Pos)           /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos          (4U)                                    
+#define QUADSPI_CR_SSHIFT_Msk          (0x1U << QUADSPI_CR_SSHIFT_Pos)         /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
+#define QUADSPI_CR_DFM_Pos             (6U)                                    
+#define QUADSPI_CR_DFM_Msk             (0x1U << QUADSPI_CR_DFM_Pos)            /*!< 0x00000040 */
+#define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */
+#define QUADSPI_CR_FSEL_Pos            (7U)                                    
+#define QUADSPI_CR_FSEL_Msk            (0x1U << QUADSPI_CR_FSEL_Pos)           /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */
+#define QUADSPI_CR_FTHRES_Pos          (8U)                                    
+#define QUADSPI_CR_FTHRES_Msk          (0xFU << QUADSPI_CR_FTHRES_Pos)         /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_TEIE_Pos            (16U)                                   
+#define QUADSPI_CR_TEIE_Msk            (0x1U << QUADSPI_CR_TEIE_Pos)           /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos            (17U)                                   
+#define QUADSPI_CR_TCIE_Msk            (0x1U << QUADSPI_CR_TCIE_Pos)           /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos            (18U)                                   
+#define QUADSPI_CR_FTIE_Msk            (0x1U << QUADSPI_CR_FTIE_Pos)           /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos            (19U)                                   
+#define QUADSPI_CR_SMIE_Msk            (0x1U << QUADSPI_CR_SMIE_Pos)           /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos            (20U)                                   
+#define QUADSPI_CR_TOIE_Msk            (0x1U << QUADSPI_CR_TOIE_Pos)           /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos            (22U)                                   
+#define QUADSPI_CR_APMS_Msk            (0x1U << QUADSPI_CR_APMS_Pos)           /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
+#define QUADSPI_CR_PMM_Pos             (23U)                                   
+#define QUADSPI_CR_PMM_Msk             (0x1U << QUADSPI_CR_PMM_Pos)            /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos       (24U)                                   
+#define QUADSPI_CR_PRESCALER_Msk       (0xFFU << QUADSPI_CR_PRESCALER_Pos)     /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos         (0U)                                    
+#define QUADSPI_DCR_CKMODE_Msk         (0x1U << QUADSPI_DCR_CKMODE_Pos)        /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos           (8U)                                    
+#define QUADSPI_DCR_CSHT_Msk           (0x7U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0             (0x1U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1             (0x2U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2             (0x4U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos          (16U)                                   
+#define QUADSPI_DCR_FSIZE_Msk          (0x1FU << QUADSPI_DCR_FSIZE_Pos)        /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos             (0U)                                    
+#define QUADSPI_SR_TEF_Msk             (0x1U << QUADSPI_SR_TEF_Pos)            /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos             (1U)                                    
+#define QUADSPI_SR_TCF_Msk             (0x1U << QUADSPI_SR_TCF_Pos)            /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos             (2U)                                    
+#define QUADSPI_SR_FTF_Msk             (0x1U << QUADSPI_SR_FTF_Pos)            /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos             (3U)                                    
+#define QUADSPI_SR_SMF_Msk             (0x1U << QUADSPI_SR_SMF_Pos)            /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos             (4U)                                    
+#define QUADSPI_SR_TOF_Msk             (0x1U << QUADSPI_SR_TOF_Pos)            /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos            (5U)                                    
+#define QUADSPI_SR_BUSY_Msk            (0x1U << QUADSPI_SR_BUSY_Pos)           /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos          (8U)                                    
+#define QUADSPI_SR_FLEVEL_Msk          (0x1FU << QUADSPI_SR_FLEVEL_Pos)        /*!< 0x00001F00 */
+#define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos           (0U)                                    
+#define QUADSPI_FCR_CTEF_Msk           (0x1U << QUADSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos           (1U)                                    
+#define QUADSPI_FCR_CTCF_Msk           (0x1U << QUADSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos           (3U)                                    
+#define QUADSPI_FCR_CSMF_Msk           (0x1U << QUADSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos           (4U)                                    
+#define QUADSPI_FCR_CTOF_Msk           (0x1U << QUADSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos             (0U)                                    
+#define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos    (0U)                                    
+#define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos)  /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_IMODE_Pos          (8U)                                    
+#define QUADSPI_CCR_IMODE_Msk          (0x3U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0            (0x1U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1            (0x2U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos         (10U)                                   
+#define QUADSPI_CCR_ADMODE_Msk         (0x3U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0           (0x1U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1           (0x2U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos         (12U)                                   
+#define QUADSPI_CCR_ADSIZE_Msk         (0x3U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0           (0x1U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1           (0x2U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos         (14U)                                   
+#define QUADSPI_CCR_ABMODE_Msk         (0x3U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0           (0x1U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1           (0x2U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos         (16U)                                   
+#define QUADSPI_CCR_ABSIZE_Msk         (0x3U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0           (0x1U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1           (0x2U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos           (18U)                                   
+#define QUADSPI_CCR_DCYC_Msk           (0x1FU << QUADSPI_CCR_DCYC_Pos)         /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DMODE_Pos          (24U)                                   
+#define QUADSPI_CCR_DMODE_Msk          (0x3U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0            (0x1U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1            (0x2U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos          (26U)                                   
+#define QUADSPI_CCR_FMODE_Msk          (0x3U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0            (0x1U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1            (0x2U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos           (28U)                                   
+#define QUADSPI_CCR_SIOO_Msk           (0x1U << QUADSPI_CCR_SIOO_Pos)          /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos           (30U)                                   
+#define QUADSPI_CCR_DHHC_Msk           (0x1U << QUADSPI_CCR_DHHC_Pos)          /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */
+#define QUADSPI_CCR_DDRM_Pos           (31U)                                   
+#define QUADSPI_CCR_DDRM_Msk           (0x1U << QUADSPI_CCR_DDRM_Pos)          /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos         (0U)                                    
+#define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos      (0U)                                    
+#define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos            (0U)                                    
+#define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos         (0U)                                    
+#define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos        (0U)                                    
+#define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos       (0U)                                    
+#define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos       (0U)                                    
+#define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
+#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2        (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000004 */
+
+/******************  Bit definition for SYSCFG_CFGR1 register  ******************/
+#define SYSCFG_CFGR1_FWDIS_Pos          (0U)                                   
+#define SYSCFG_CFGR1_FWDIS_Msk          (0x1U << SYSCFG_CFGR1_FWDIS_Pos)       /*!< 0x00000001 */
+#define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/
+#define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)                                   
+#define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)                                  
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)                                  
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)                                  
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)                                  
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)                                  
+#define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos)    /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)                                  
+#define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos)    /*!< 0x00200000 */
+#define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)                                  
+#define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos)    /*!< 0x00400000 */
+#define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0x7U << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0x7U << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0x7U << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000700 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0x7U << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x00007000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007U)                      /*!<PH[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070U)                      /*!<PH[1] pin */
+
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0x7U << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0x7U << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0x7U << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000700 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0x7U << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x00007000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
+
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
+
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0x7U << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0x7U << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0x7U << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0x7U << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0x7U << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x00000007 */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0x7U << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x00000070 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0x7U << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0x7U << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
+
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
+
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
+
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
+
+/******************  Bit definition for SYSCFG_SCSR register  ****************/
+#define SYSCFG_SCSR_SRAM2ER_Pos         (0U)                                   
+#define SYSCFG_SCSR_SRAM2ER_Msk         (0x1U << SYSCFG_SCSR_SRAM2ER_Pos)      /*!< 0x00000001 */
+#define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */
+#define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)                                   
+#define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */
+
+/******************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_CLL_Pos            (0U)                                   
+#define SYSCFG_CFGR2_CLL_Msk            (0x1U << SYSCFG_CFGR2_CLL_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
+#define SYSCFG_CFGR2_SPL_Pos            (1U)                                   
+#define SYSCFG_CFGR2_SPL_Msk            (0x1U << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
+#define SYSCFG_CFGR2_PVDL_Pos           (2U)                                   
+#define SYSCFG_CFGR2_PVDL_Msk           (0x1U << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
+#define SYSCFG_CFGR2_ECCL_Pos           (3U)                                   
+#define SYSCFG_CFGR2_ECCL_Msk           (0x1U << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
+#define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
+#define SYSCFG_CFGR2_SPF_Pos            (8U)                                   
+#define SYSCFG_CFGR2_SPF_Msk            (0x1U << SYSCFG_CFGR2_SPF_Pos)         /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
+
+/******************  Bit definition for SYSCFG_SWPR register  ****************/
+#define SYSCFG_SWPR_PAGE0_Pos           (0U)                                   
+#define SYSCFG_SWPR_PAGE0_Msk           (0x1U << SYSCFG_SWPR_PAGE0_Pos)        /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SWPR_PAGE1_Pos           (1U)                                   
+#define SYSCFG_SWPR_PAGE1_Msk           (0x1U << SYSCFG_SWPR_PAGE1_Pos)        /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SWPR_PAGE2_Pos           (2U)                                   
+#define SYSCFG_SWPR_PAGE2_Msk           (0x1U << SYSCFG_SWPR_PAGE2_Pos)        /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SWPR_PAGE3_Pos           (3U)                                   
+#define SYSCFG_SWPR_PAGE3_Msk           (0x1U << SYSCFG_SWPR_PAGE3_Pos)        /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SWPR_PAGE4_Pos           (4U)                                   
+#define SYSCFG_SWPR_PAGE4_Msk           (0x1U << SYSCFG_SWPR_PAGE4_Pos)        /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SWPR_PAGE5_Pos           (5U)                                   
+#define SYSCFG_SWPR_PAGE5_Msk           (0x1U << SYSCFG_SWPR_PAGE5_Pos)        /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SWPR_PAGE6_Pos           (6U)                                   
+#define SYSCFG_SWPR_PAGE6_Msk           (0x1U << SYSCFG_SWPR_PAGE6_Pos)        /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SWPR_PAGE7_Pos           (7U)                                   
+#define SYSCFG_SWPR_PAGE7_Msk           (0x1U << SYSCFG_SWPR_PAGE7_Pos)        /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SWPR_PAGE8_Pos           (8U)                                   
+#define SYSCFG_SWPR_PAGE8_Msk           (0x1U << SYSCFG_SWPR_PAGE8_Pos)        /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SWPR_PAGE9_Pos           (9U)                                   
+#define SYSCFG_SWPR_PAGE9_Msk           (0x1U << SYSCFG_SWPR_PAGE9_Pos)        /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SWPR_PAGE10_Pos          (10U)                                  
+#define SYSCFG_SWPR_PAGE10_Msk          (0x1U << SYSCFG_SWPR_PAGE10_Pos)       /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/
+#define SYSCFG_SWPR_PAGE11_Pos          (11U)                                  
+#define SYSCFG_SWPR_PAGE11_Msk          (0x1U << SYSCFG_SWPR_PAGE11_Pos)       /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/
+#define SYSCFG_SWPR_PAGE12_Pos          (12U)                                  
+#define SYSCFG_SWPR_PAGE12_Msk          (0x1U << SYSCFG_SWPR_PAGE12_Pos)       /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/
+#define SYSCFG_SWPR_PAGE13_Pos          (13U)                                  
+#define SYSCFG_SWPR_PAGE13_Msk          (0x1U << SYSCFG_SWPR_PAGE13_Pos)       /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/
+#define SYSCFG_SWPR_PAGE14_Pos          (14U)                                  
+#define SYSCFG_SWPR_PAGE14_Msk          (0x1U << SYSCFG_SWPR_PAGE14_Pos)       /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/
+#define SYSCFG_SWPR_PAGE15_Pos          (15U)                                  
+#define SYSCFG_SWPR_PAGE15_Msk          (0x1U << SYSCFG_SWPR_PAGE15_Pos)       /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/
+
+/******************  Bit definition for SYSCFG_SKR register  ****************/
+#define SYSCFG_SKR_KEY_Pos              (0U)                                   
+#define SYSCFG_SKR_KEY_Msk              (0xFFU << SYSCFG_SKR_KEY_Pos)          /*!< 0x000000FF */
+#define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)                                        
+#define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)                                        
+#define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)                                        
+#define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)                                        
+#define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_OCCS_Pos         (3U)                                         
+#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)                                         
+#define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)                                        
+#define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)                                        
+#define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)                                        
+#define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)                                         
+#define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)                                         
+#define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)                                         
+#define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)                                         
+#define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)                                         
+#define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)                                        
+#define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)                                        
+#define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)                                        
+#define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)                                        
+#define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)                                        
+#define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)                                        
+#define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)                                        
+#define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)                                        
+#define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                         
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)                                        
+#define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)                                         
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)                                        
+#define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)                                        
+#define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)                                        
+#define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)                                         
+#define TIM_CCR6_CCR6_Msk         (0xFFFFU << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)                                        
+#define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)                                        
+#define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)                                        
+#define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)                                        
+#define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM1_OR1 register  *******************/
+#define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)                                    
+#define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000003 */
+#define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
+#define TIM1_OR1_ETR_ADC1_RMP_0        (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000001 */
+#define TIM1_OR1_ETR_ADC1_RMP_1        (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM1_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM1_OR1_TI1_RMP_Msk           (0x1U << TIM1_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM1_OR2 register  *******************/
+#define TIM1_OR2_BKINE_Pos             (0U)                                    
+#define TIM1_OR2_BKINE_Msk             (0x1U << TIM1_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM1_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM1_OR2_BKCMP1E_Msk           (0x1U << TIM1_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM1_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM1_OR2_BKCMP2E_Msk           (0x1U << TIM1_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM1_OR2_BKINP_Pos             (9U)                                    
+#define TIM1_OR2_BKINP_Msk             (0x1U << TIM1_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM1_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM1_OR2_BKCMP1P_Msk           (0x1U << TIM1_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM1_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM1_OR2_BKCMP2P_Msk           (0x1U << TIM1_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM1_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM1_OR2_ETRSEL_Msk            (0x7U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
+#define TIM1_OR2_ETRSEL_0              (0x1U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM1_OR2_ETRSEL_1              (0x2U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM1_OR2_ETRSEL_2              (0x4U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM1_OR3 register  *******************/
+#define TIM1_OR3_BK2INE_Pos            (0U)                                    
+#define TIM1_OR3_BK2INE_Msk            (0x1U << TIM1_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM1_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM1_OR3_BK2CMP1E_Msk          (0x1U << TIM1_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM1_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM1_OR3_BK2CMP2E_Msk          (0x1U << TIM1_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM1_OR3_BK2INP_Pos            (9U)                                    
+#define TIM1_OR3_BK2INP_Msk            (0x1U << TIM1_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM1_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM1_OR3_BK2CMP1P_Msk          (0x1U << TIM1_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM1_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM1_OR3_BK2CMP2P_Msk          (0x1U << TIM1_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+
+/*******************  Bit definition for TIM2_OR1 register  *******************/
+#define TIM2_OR1_ITR1_RMP_Pos     (0U)                                         
+#define TIM2_OR1_ITR1_RMP_Msk     (0x1U << TIM2_OR1_ITR1_RMP_Pos)              /*!< 0x00000001 */
+#define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */
+#define TIM2_OR1_ETR1_RMP_Pos     (1U)                                         
+#define TIM2_OR1_ETR1_RMP_Msk     (0x1U << TIM2_OR1_ETR1_RMP_Pos)              /*!< 0x00000002 */
+#define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */
+
+#define TIM2_OR1_TI4_RMP_Pos      (2U)                                         
+#define TIM2_OR1_TI4_RMP_Msk      (0x3U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x0000000C */
+#define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
+#define TIM2_OR1_TI4_RMP_0        (0x1U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000004 */
+#define TIM2_OR1_TI4_RMP_1        (0x2U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000008 */
+
+/*******************  Bit definition for TIM2_OR2 register  *******************/
+#define TIM2_OR2_ETRSEL_Pos       (14U)                                        
+#define TIM2_OR2_ETRSEL_Msk       (0x7U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
+#define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
+#define TIM2_OR2_ETRSEL_0         (0x1U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM2_OR2_ETRSEL_1         (0x2U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM2_OR2_ETRSEL_2         (0x4U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
+
+
+/*******************  Bit definition for TIM15_OR1 register  ******************/
+#define TIM15_OR1_TI1_RMP_Pos           (0U)                                   
+#define TIM15_OR1_TI1_RMP_Msk           (0x1U << TIM15_OR1_TI1_RMP_Pos)        /*!< 0x00000001 */
+#define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */
+
+#define TIM15_OR1_ENCODER_MODE_Pos      (1U)                                   
+#define TIM15_OR1_ENCODER_MODE_Msk      (0x3U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000006 */
+#define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
+#define TIM15_OR1_ENCODER_MODE_0        (0x1U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000002 */
+#define TIM15_OR1_ENCODER_MODE_1        (0x2U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000004 */
+
+/*******************  Bit definition for TIM15_OR2 register  ******************/
+#define TIM15_OR2_BKINE_Pos             (0U)                                   
+#define TIM15_OR2_BKINE_Msk             (0x1U << TIM15_OR2_BKINE_Pos)          /*!< 0x00000001 */
+#define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */
+#define TIM15_OR2_BKCMP1E_Pos           (1U)                                   
+#define TIM15_OR2_BKCMP1E_Msk           (0x1U << TIM15_OR2_BKCMP1E_Pos)        /*!< 0x00000002 */
+#define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */
+#define TIM15_OR2_BKCMP2E_Pos           (2U)                                   
+#define TIM15_OR2_BKCMP2E_Msk           (0x1U << TIM15_OR2_BKCMP2E_Pos)        /*!< 0x00000004 */
+#define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */
+#define TIM15_OR2_BKINP_Pos             (9U)                                   
+#define TIM15_OR2_BKINP_Msk             (0x1U << TIM15_OR2_BKINP_Pos)          /*!< 0x00000200 */
+#define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */
+#define TIM15_OR2_BKCMP1P_Pos           (10U)                                  
+#define TIM15_OR2_BKCMP1P_Msk           (0x1U << TIM15_OR2_BKCMP1P_Pos)        /*!< 0x00000400 */
+#define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */
+#define TIM15_OR2_BKCMP2P_Pos           (11U)                                  
+#define TIM15_OR2_BKCMP2P_Msk           (0x1U << TIM15_OR2_BKCMP2P_Pos)        /*!< 0x00000800 */
+#define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_OR1 register  ******************/
+#define TIM16_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM16_OR1_TI1_RMP_Msk      (0x7U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000007 */
+#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
+#define TIM16_OR1_TI1_RMP_0        (0x1U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM16_OR1_TI1_RMP_1        (0x2U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+#define TIM16_OR1_TI1_RMP_2        (0x4U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000004 */
+
+/*******************  Bit definition for TIM16_OR2 register  ******************/
+#define TIM16_OR2_BKINE_Pos        (0U)                                        
+#define TIM16_OR2_BKINE_Msk        (0x1U << TIM16_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM16_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM16_OR2_BKCMP1E_Msk      (0x1U << TIM16_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM16_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM16_OR2_BKCMP2E_Msk      (0x1U << TIM16_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM16_OR2_BKINP_Pos        (9U)                                        
+#define TIM16_OR2_BKINP_Msk        (0x1U << TIM16_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM16_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM16_OR2_BKCMP1P_Msk      (0x1U << TIM16_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM16_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM16_OR2_BKCMP2P_Msk      (0x1U << TIM16_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)                                       
+#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)                                       
+#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)                                       
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)                                       
+#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)                                       
+#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)                                       
+#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)                                       
+#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)                                       
+#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)                                       
+#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)                                       
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)                                       
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)                                       
+#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)                                       
+#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)                                       
+#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)                                       
+#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)                                       
+#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)                                       
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)                                       
+#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)                                       
+#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)                                       
+#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)                                       
+#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)                                       
+#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)                                       
+#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)                                       
+#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)                                       
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)                                       
+#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)                                      
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)                                      
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)                                      
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)                                      
+#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)                                      
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)                                      
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)                                      
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)                                      
+#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)                                       
+#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)                                       
+#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)                                       
+#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)                                       
+#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)                                       
+#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)                                       
+#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_OR register  ********************/
+#define LPTIM_OR_OR_Pos             (0U)                                       
+#define LPTIM_OR_OR_Msk             (0x3U << LPTIM_OR_OR_Pos)                  /*!< 0x00000003 */
+#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0               (0x1U << LPTIM_OR_OR_Pos)                  /*!< 0x00000001 */
+#define LPTIM_OR_OR_1               (0x2U << LPTIM_OR_OR_Pos)                  /*!< 0x00000002 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/**********************  Bit definition for COMP_CSR register  ****************/
+#define COMP_CSR_EN_Pos            (0U)                                        
+#define COMP_CSR_EN_Msk            (0x1U << COMP_CSR_EN_Pos)                   /*!< 0x00000001 */
+#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
+
+#define COMP_CSR_PWRMODE_Pos       (2U)                                        
+#define COMP_CSR_PWRMODE_Msk       (0x3U << COMP_CSR_PWRMODE_Pos)              /*!< 0x0000000C */
+#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
+#define COMP_CSR_PWRMODE_0         (0x1U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000004 */
+#define COMP_CSR_PWRMODE_1         (0x2U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000008 */
+
+#define COMP_CSR_INMSEL_Pos        (4U)                                        
+#define COMP_CSR_INMSEL_Msk        (0x7U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000070 */
+#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0          (0x1U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1          (0x2U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2          (0x4U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000040 */
+
+#define COMP_CSR_INPSEL_Pos        (7U)                                        
+#define COMP_CSR_INPSEL_Msk        (0x3U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000180 */
+#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
+#define COMP_CSR_INPSEL_0          (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
+#define COMP_CSR_INPSEL_1          (0x2U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000100 */
+
+#define COMP_CSR_WINMODE_Pos       (9U)                                        
+#define COMP_CSR_WINMODE_Msk       (0x1U << COMP_CSR_WINMODE_Pos)              /*!< 0x00000200 */
+#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
+
+#define COMP_CSR_POLARITY_Pos      (15U)                                       
+#define COMP_CSR_POLARITY_Msk      (0x1U << COMP_CSR_POLARITY_Pos)             /*!< 0x00008000 */
+#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
+
+#define COMP_CSR_HYST_Pos          (16U)                                       
+#define COMP_CSR_HYST_Msk          (0x3U << COMP_CSR_HYST_Pos)                 /*!< 0x00030000 */
+#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
+#define COMP_CSR_HYST_0            (0x1U << COMP_CSR_HYST_Pos)                 /*!< 0x00010000 */
+#define COMP_CSR_HYST_1            (0x2U << COMP_CSR_HYST_Pos)                 /*!< 0x00020000 */
+
+#define COMP_CSR_BLANKING_Pos      (18U)                                       
+#define COMP_CSR_BLANKING_Msk      (0x7U << COMP_CSR_BLANKING_Pos)             /*!< 0x001C0000 */
+#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
+#define COMP_CSR_BLANKING_0        (0x1U << COMP_CSR_BLANKING_Pos)             /*!< 0x00040000 */
+#define COMP_CSR_BLANKING_1        (0x2U << COMP_CSR_BLANKING_Pos)             /*!< 0x00080000 */
+#define COMP_CSR_BLANKING_2        (0x4U << COMP_CSR_BLANKING_Pos)             /*!< 0x00100000 */
+
+#define COMP_CSR_BRGEN_Pos         (22U)                                       
+#define COMP_CSR_BRGEN_Msk         (0x1U << COMP_CSR_BRGEN_Pos)                /*!< 0x00400000 */
+#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
+#define COMP_CSR_SCALEN_Pos        (23U)                                       
+#define COMP_CSR_SCALEN_Msk        (0x1U << COMP_CSR_SCALEN_Pos)               /*!< 0x00800000 */
+#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
+
+#define COMP_CSR_INMESEL_Pos       (25U)                                       
+#define COMP_CSR_INMESEL_Msk       (0x3U << COMP_CSR_INMESEL_Pos)              /*!< 0x06000000 */
+#define COMP_CSR_INMESEL           COMP_CSR_INMESEL_Msk                        /*!< Comparator input minus extended selection */
+#define COMP_CSR_INMESEL_0         (0x1U << COMP_CSR_INMESEL_Pos)              /*!< 0x02000000 */
+#define COMP_CSR_INMESEL_1         (0x2U << COMP_CSR_INMESEL_Pos)              /*!< 0x04000000 */
+
+#define COMP_CSR_VALUE_Pos         (30U)                                       
+#define COMP_CSR_VALUE_Msk         (0x1U << COMP_CSR_VALUE_Pos)                /*!< 0x40000000 */
+#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
+
+#define COMP_CSR_LOCK_Pos          (31U)                                       
+#define COMP_CSR_LOCK_Msk          (0x1U << COMP_CSR_LOCK_Pos)                 /*!< 0x80000000 */
+#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)                                  
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1U << OPAMP_CSR_OPAMPxEN_Pos)      /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_OPALPM_Pos             (1U)                                  
+#define OPAMP_CSR_OPALPM_Msk             (0x1U << OPAMP_CSR_OPALPM_Pos)        /*!< 0x00000002 */
+#define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
+
+#define OPAMP_CSR_OPAMODE_Pos            (2U)                                  
+#define OPAMP_CSR_OPAMODE_Msk            (0x3U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x0000000C */
+#define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
+#define OPAMP_CSR_OPAMODE_0              (0x1U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000004 */
+#define OPAMP_CSR_OPAMODE_1              (0x2U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000008 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (4U)                                  
+#define OPAMP_CSR_PGGAIN_Msk             (0x3U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000030 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000010 */
+#define OPAMP_CSR_PGGAIN_1               (0x2U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000020 */
+
+#define OPAMP_CSR_VMSEL_Pos              (8U)                                  
+#define OPAMP_CSR_VMSEL_Msk              (0x3U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000300 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000100 */
+#define OPAMP_CSR_VMSEL_1                (0x2U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000200 */
+
+#define OPAMP_CSR_VPSEL_Pos              (10U)                                 
+#define OPAMP_CSR_VPSEL_Msk              (0x1U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000400 */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_CALON_Pos              (12U)                                 
+#define OPAMP_CSR_CALON_Msk              (0x1U << OPAMP_CSR_CALON_Pos)         /*!< 0x00001000 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos             (13U)                                 
+#define OPAMP_CSR_CALSEL_Msk             (0x1U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_USERTRIM_Pos           (14U)                                 
+#define OPAMP_CSR_USERTRIM_Msk           (0x1U << OPAMP_CSR_USERTRIM_Pos)      /*!< 0x00004000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_CALOUT_Pos             (15U)                                 
+#define OPAMP_CSR_CALOUT_Msk             (0x1U << OPAMP_CSR_CALOUT_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP1_CSR_OPAEN_Msk              (0x1U << OPAMP1_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP1_CSR_OPALPM_Msk             (0x1U << OPAMP1_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
+
+#define OPAMP1_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP1_CSR_OPAMODE_Msk            (0x3U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
+#define OPAMP1_CSR_OPAMODE_0              (0x1U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP1_CSR_OPAMODE_1              (0x2U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP1_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP1_CSR_PGAGAIN_Msk            (0x3U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGAGAIN_0              (0x1U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP1_CSR_PGAGAIN_1              (0x2U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP1_CSR_VMSEL_Msk              (0x3U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP1_CSR_VMSEL_1                (0x2U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP1_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP1_CSR_VPSEL_Msk              (0x1U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_CALON_Pos              (12U)                                
+#define OPAMP1_CSR_CALON_Msk              (0x1U << OPAMP1_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP1_CSR_CALSEL_Msk             (0x1U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1U << OPAMP1_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP1_CSR_CALOUT_Msk             (0x1U << OPAMP1_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+#define OPAMP1_CSR_OPARANGE_Pos           (31U)                                
+#define OPAMP1_CSR_OPARANGE_Msk           (0x1U << OPAMP1_CSR_OPARANGE_Pos)    /*!< 0x80000000 */
+#define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)                                  
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos)  /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)                                  
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos)  /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_LPOTR register  ****************/
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_LPOTR register  ****************/
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Touch Sensing Controller (TSC)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TSC_CR register  *********************/
+#define TSC_CR_TSCE_Pos          (0U)                                          
+#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
+#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos         (1U)                                          
+#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
+#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
+#define TSC_CR_AM_Pos            (2U)                                          
+#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
+#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos       (3U)                                          
+#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos         (4U)                                          
+#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
+#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos           (5U)                                          
+#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
+#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
+#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
+#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos         (12U)                                         
+#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
+#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos         (15U)                                         
+#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
+#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos           (16U)                                         
+#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
+#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos           (17U)                                         
+#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
+#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
+#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
+#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
+#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
+#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
+#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
+#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos          (24U)                                         
+#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
+#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
+#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
+#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
+#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos          (28U)                                         
+#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
+#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
+#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
+#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
+#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
+
+/*******************  Bit definition for TSC_IER register  ********************/
+#define TSC_IER_EOAIE_Pos        (0U)                                          
+#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
+#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos        (1U)                                          
+#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
+#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
+
+/*******************  Bit definition for TSC_ICR register  ********************/
+#define TSC_ICR_EOAIC_Pos        (0U)                                          
+#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
+#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos        (1U)                                          
+#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
+#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
+
+/*******************  Bit definition for TSC_ISR register  ********************/
+#define TSC_ISR_EOAF_Pos         (0U)                                          
+#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
+#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos         (1U)                                          
+#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
+#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
+
+/*******************  Bit definition for TSC_IOHCR register  ******************/
+#define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+
+/*******************  Bit definition for TSC_IOASCR register  *****************/
+#define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
+#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
+#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
+#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
+#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
+#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
+#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
+#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
+#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
+#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
+#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
+#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
+#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
+#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
+#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
+#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
+#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
+#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
+#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
+#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
+#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
+#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
+#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
+#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
+#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
+#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
+#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
+#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
+#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
+
+/*******************  Bit definition for TSC_IOSCR register  ******************/
+#define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
+
+/*******************  Bit definition for TSC_IOCCR register  ******************/
+#define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
+
+/*******************  Bit definition for TSC_IOGCSR register  *****************/
+#define TSC_IOGCSR_G1E_Pos       (0U)                                          
+#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos       (1U)                                          
+#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos       (2U)                                          
+#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos       (3U)                                          
+#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos       (4U)                                          
+#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos       (5U)                                          
+#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos       (6U)                                          
+#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G1S_Pos       (16U)                                         
+#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos       (17U)                                         
+#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos       (18U)                                         
+#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos       (19U)                                         
+#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos       (20U)                                         
+#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos       (21U)                                         
+#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos       (22U)                                         
+#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
+
+/*******************  Bit definition for TSC_IOGXCR register  *****************/
+#define TSC_IOGXCR_CNT_Pos       (0U)                                          
+#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+*/
+#define USART_TCBGT_SUPPORT
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos              (0U)                                     
+#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
+#define USART_CR1_UESM_Pos            (1U)                                     
+#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
+#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
+#define USART_CR1_M0_Pos              (12U)                                    
+#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
+#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos             (13U)                                    
+#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
+#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos            (14U)                                    
+#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
+#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos            (16U)                                    
+#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
+#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
+#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
+#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
+#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
+#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos            (21U)                                    
+#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
+#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
+#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
+#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
+#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
+#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos           (26U)                                    
+#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
+#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos           (27U)                                    
+#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
+#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos              (28U)                                    
+#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
+#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADDM7_Pos           (4U)                                     
+#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
+#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
+#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos            (15U)                                    
+#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
+#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos           (16U)                                    
+#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
+#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos           (17U)                                    
+#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
+#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos         (18U)                                    
+#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
+#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos        (19U)                                    
+#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos           (20U)                                    
+#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
+#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos         (21U)                                    
+#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
+#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos           (23U)                                    
+#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
+#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos             (24U)                                    
+#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos          (12U)                                    
+#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
+#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos            (13U)                                    
+#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
+#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos             (14U)                                    
+#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
+#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos             (15U)                                    
+#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
+#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos         (17U)                                    
+#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos             (20U)                                    
+#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
+#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
+#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos           (22U)                                    
+#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
+#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TCBGTIE_Pos         (24U)                                    
+#define USART_CR3_TCBGTIE_Msk         (0x1U << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE             USART_CR3_TCBGTIE_Msk                    /*!< Transmission Complete Before Guard Time Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
+#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
+#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos            (0U)                                     
+#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos           (24U)                                    
+#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
+#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos           (0U)                                     
+#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
+#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos           (1U)                                     
+#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
+#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos            (2U)                                     
+#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
+#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos           (3U)                                     
+#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
+#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos           (4U)                                     
+#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
+#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos              (0U)                                     
+#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
+#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
+#define USART_ISR_FE_Pos              (1U)                                     
+#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
+#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
+#define USART_ISR_NE_Pos              (2U)                                     
+#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
+#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos             (3U)                                     
+#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
+#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos            (4U)                                     
+#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
+#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos            (5U)                                     
+#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
+#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos              (6U)                                     
+#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
+#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos             (7U)                                     
+#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
+#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos            (8U)                                     
+#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
+#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos           (9U)                                     
+#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
+#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos             (10U)                                    
+#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
+#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
+#define USART_ISR_RTOF_Pos            (11U)                                    
+#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
+#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos            (12U)                                    
+#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
+#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos            (14U)                                    
+#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
+#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos            (15U)                                    
+#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
+#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos            (16U)                                    
+#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
+#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
+#define USART_ISR_CMF_Pos             (17U)                                    
+#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
+#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos            (18U)                                    
+#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
+#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos             (19U)                                    
+#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
+#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos             (20U)                                    
+#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
+#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos           (21U)                                    
+#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
+#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos           (22U)                                    
+#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
+#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TCBGT_Pos           (25U)                                    
+#define USART_ISR_TCBGT_Msk           (0x1U << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
+#define USART_ISR_TCBGT               USART_ISR_TCBGT_Msk                      /*!< Transmission Complete Before Guard Time Completion Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos            (0U)                                     
+#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
+#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos            (1U)                                     
+#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
+#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos             (2U)                                     
+#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
+#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos           (3U)                                     
+#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
+#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos          (4U)                                     
+#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
+#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos            (6U)                                     
+#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
+#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos         (7U)                                     
+#define USART_ICR_TCBGTCF_Msk         (0x1U << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF             USART_ICR_TCBGTCF_Msk                    /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos           (8U)                                     
+#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
+#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos           (9U)                                     
+#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
+#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos           (11U)                                    
+#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
+#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos           (12U)                                    
+#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
+#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos            (17U)                                    
+#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
+#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos            (20U)                                    
+#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
+#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos             (0U)                                     
+#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
+#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos             (0U)                                     
+#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
+#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)                                          
+#define SWPMI_CR_RXDMA_Msk       (0x1U << SWPMI_CR_RXDMA_Pos)                  /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)                                          
+#define SWPMI_CR_TXDMA_Msk       (0x1U << SWPMI_CR_TXDMA_Pos)                  /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)                                          
+#define SWPMI_CR_RXMODE_Msk      (0x1U << SWPMI_CR_RXMODE_Pos)                 /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)                                          
+#define SWPMI_CR_TXMODE_Msk      (0x1U << SWPMI_CR_TXMODE_Pos)                 /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)                                          
+#define SWPMI_CR_LPBK_Msk        (0x1U << SWPMI_CR_LPBK_Pos)                   /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)                                          
+#define SWPMI_CR_SWPACT_Msk      (0x1U << SWPMI_CR_SWPACT_Pos)                 /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)                                         
+#define SWPMI_CR_DEACT_Msk       (0x1U << SWPMI_CR_DEACT_Pos)                  /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)                                          
+#define SWPMI_BRR_BR_Msk         (0x3FU << SWPMI_BRR_BR_Pos)                   /*!< 0x0000003F */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)                                          
+#define SWPMI_ISR_RXBFF_Msk      (0x1U << SWPMI_ISR_RXBFF_Pos)                 /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)                                          
+#define SWPMI_ISR_TXBEF_Msk      (0x1U << SWPMI_ISR_TXBEF_Pos)                 /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)                                          
+#define SWPMI_ISR_RXBERF_Msk     (0x1U << SWPMI_ISR_RXBERF_Pos)                /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)                                          
+#define SWPMI_ISR_RXOVRF_Msk     (0x1U << SWPMI_ISR_RXOVRF_Pos)                /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)                                          
+#define SWPMI_ISR_TXUNRF_Msk     (0x1U << SWPMI_ISR_TXUNRF_Pos)                /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)                                          
+#define SWPMI_ISR_RXNE_Msk       (0x1U << SWPMI_ISR_RXNE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)                                          
+#define SWPMI_ISR_TXE_Msk        (0x1U << SWPMI_ISR_TXE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)                                          
+#define SWPMI_ISR_TCF_Msk        (0x1U << SWPMI_ISR_TCF_Pos)                   /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)                                          
+#define SWPMI_ISR_SRF_Msk        (0x1U << SWPMI_ISR_SRF_Pos)                   /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)                                          
+#define SWPMI_ISR_SUSP_Msk       (0x1U << SWPMI_ISR_SUSP_Pos)                  /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)                                         
+#define SWPMI_ISR_DEACTF_Msk     (0x1U << SWPMI_ISR_DEACTF_Pos)                /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)                                          
+#define SWPMI_ICR_CRXBFF_Msk     (0x1U << SWPMI_ICR_CRXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)                                          
+#define SWPMI_ICR_CTXBEF_Msk     (0x1U << SWPMI_ICR_CTXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)                                          
+#define SWPMI_ICR_CRXBERF_Msk    (0x1U << SWPMI_ICR_CRXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)                                          
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1U << SWPMI_ICR_CRXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)                                          
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1U << SWPMI_ICR_CTXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)                                          
+#define SWPMI_ICR_CTCF_Msk       (0x1U << SWPMI_ICR_CTCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)                                          
+#define SWPMI_ICR_CSRF_Msk       (0x1U << SWPMI_ICR_CSRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_SRIE_Pos       (8U)                                          
+#define SWPMI_IER_SRIE_Msk       (0x1U << SWPMI_IER_SRIE_Pos)                  /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_TCIE_Pos       (7U)                                          
+#define SWPMI_IER_TCIE_Msk       (0x1U << SWPMI_IER_TCIE_Pos)                  /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_TIE_Pos        (6U)                                          
+#define SWPMI_IER_TIE_Msk        (0x1U << SWPMI_IER_TIE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_RIE_Pos        (5U)                                          
+#define SWPMI_IER_RIE_Msk        (0x1U << SWPMI_IER_RIE_Pos)                   /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)                                          
+#define SWPMI_IER_TXUNRIE_Msk    (0x1U << SWPMI_IER_TXUNRIE_Pos)               /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)                                          
+#define SWPMI_IER_RXOVRIE_Msk    (0x1U << SWPMI_IER_RXOVRIE_Pos)               /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)                                          
+#define SWPMI_IER_RXBERIE_Msk    (0x1U << SWPMI_IER_RXBERIE_Pos)               /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_TXBEIE_Pos     (1U)                                          
+#define SWPMI_IER_TXBEIE_Msk     (0x1U << SWPMI_IER_TXBEIE_Pos)                /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBFIE_Pos     (0U)                                          
+#define SWPMI_IER_RXBFIE_Msk     (0x1U << SWPMI_IER_RXBFIE_Pos)                /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)                                          
+#define SWPMI_RFL_RFL_Msk        (0x1FU << SWPMI_RFL_RFL_Pos)                  /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1_Pos    (0U)                                          
+#define SWPMI_RFL_RFL_0_1_Msk    (0x3U << SWPMI_RFL_RFL_0_1_Pos)               /*!< 0x00000003 */
+#define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)                                          
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFU << SWPMI_TDR_TD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)                                          
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFU << SWPMI_RDR_RD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)                                          
+#define SWPMI_OR_TBYP_Msk        (0x1U << SWPMI_OR_TBYP_Pos)                   /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)                                          
+#define SWPMI_OR_CLASS_Msk       (0x1U << SWPMI_OR_CLASS_Pos)                  /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos    (0U)                                           
+#define VREFBUF_CSR_ENVR_Msk    (0x1U << VREFBUF_CSR_ENVR_Pos)                 /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos     (1U)                                           
+#define VREFBUF_CSR_HIZ_Msk     (0x1U << VREFBUF_CSR_HIZ_Pos)                  /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
+#define VREFBUF_CSR_VRS_Pos     (2U)                                           
+#define VREFBUF_CSR_VRS_Msk     (0x1U << VREFBUF_CSR_VRS_Pos)                  /*!< 0x00000004 */
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */
+#define VREFBUF_CSR_VRR_Pos     (3U)                                           
+#define VREFBUF_CSR_VRR_Msk     (0x1U << VREFBUF_CSR_VRR_Pos)                  /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos    (0U)                                           
+#define VREFBUF_CCR_TRIM_Msk    (0x3FU << VREFBUF_CCR_TRIM_Pos)                /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
+#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        
+#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
+#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
+#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         
+#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
+#define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          
+#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
+#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       
+#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)                            
+#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk        
+
+#define DBGMCU_CR_TRACE_MODE_Pos               (6U)                            
+#define DBGMCU_CR_TRACE_MODE_Msk               (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk        
+#define DBGMCU_CR_TRACE_MODE_0                 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)                           
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)                           
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)                           
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)                           
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)                           
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)                            
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB2FZ register  ************/
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)                           
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)                           
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)                           
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk 
+
+/******************************************************************************/
+/*                                                                            */
+/*                         USB Device FS Endpoint registers                   */
+/*                                                                            */
+/******************************************************************************/
+#define USB_EP0R                             USB_BASE                    /*!< endpoint 0 register address */
+#define USB_EP1R                             (USB_BASE + 0x0x00000004)   /*!< endpoint 1 register address */
+#define USB_EP2R                             (USB_BASE + 0x0x00000008)   /*!< endpoint 2 register address */
+#define USB_EP3R                             (USB_BASE + 0x0x0000000C)   /*!< endpoint 3 register address */
+#define USB_EP4R                             (USB_BASE + 0x0x00000010)   /*!< endpoint 4 register address */
+#define USB_EP5R                             (USB_BASE + 0x0x00000014)   /*!< endpoint 5 register address */
+#define USB_EP6R                             (USB_BASE + 0x0x00000018)   /*!< endpoint 6 register address */
+#define USB_EP7R                             (USB_BASE + 0x0x0000001C)   /*!< endpoint 7 register address */
+
+/* bit positions */ 
+#define USB_EP_CTR_RX                            ((uint16_t)0x8000U)           /*!<  EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX                           ((uint16_t)0x4000U)           /*!<  EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT                            ((uint16_t)0x3000U)           /*!<  EndPoint RX STATus bit field */
+#define USB_EP_SETUP                             ((uint16_t)0x0800U)           /*!<  EndPoint SETUP */
+#define USB_EP_T_FIELD                           ((uint16_t)0x0600U)           /*!<  EndPoint TYPE */
+#define USB_EP_KIND                              ((uint16_t)0x0100U)           /*!<  EndPoint KIND */
+#define USB_EP_CTR_TX                            ((uint16_t)0x0080U)           /*!<  EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX                           ((uint16_t)0x0040U)           /*!<  EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT                            ((uint16_t)0x0030U)           /*!<  EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD                         ((uint16_t)0x000FU)           /*!<  EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK                         ((uint16_t)0x0600U)           /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK                              ((uint16_t)0x0000U)           /*!< EndPoint BULK */
+#define USB_EP_CONTROL                           ((uint16_t)0x0200U)           /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS                       ((uint16_t)0x0400U)           /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT                         ((uint16_t)0x0600U)           /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+                                                                 
+#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL                          ((uint16_t)0x0010U)           /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK                            ((uint16_t)0x0020U)           /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID                          ((uint16_t)0x0030U)           /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1                           ((uint16_t)0x0010U)           /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2                           ((uint16_t)0x0020U)           /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
+                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL                          ((uint16_t)0x1000U)           /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK                            ((uint16_t)0x2000U)           /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID                          ((uint16_t)0x3000U)           /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1                           ((uint16_t)0x1000U)           /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2                           ((uint16_t)0x2000U)           /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/*                                                                            */
+/*                         USB Device FS General registers                    */
+/*                                                                            */
+/******************************************************************************/
+#define USB_CNTR                             (USB_BASE + 0x00000040U)     /*!< Control register */
+#define USB_ISTR                             (USB_BASE + 0x00000044U)     /*!< Interrupt status register */
+#define USB_FNR                              (USB_BASE + 0x00000048U)     /*!< Frame number register */
+#define USB_DADDR                            (USB_BASE + 0x0000004CU)     /*!< Device address register */
+#define USB_BTABLE                           (USB_BASE + 0x00000050U)     /*!< Buffer Table address register */
+#define USB_LPMCSR                           (USB_BASE + 0x00000054U)     /*!< LPM Control and Status register */
+#define USB_BCDR                             (USB_BASE + 0x00000058U)     /*!< Battery Charging detector register*/
+
+/******************  Bits definition for USB_CNTR register  *******************/
+#define USB_CNTR_CTRM                            ((uint16_t)0x8000U)           /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM                         ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM                            ((uint16_t)0x2000U)           /*!< ERRor Mask */
+#define USB_CNTR_WKUPM                           ((uint16_t)0x1000U)           /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM                           ((uint16_t)0x0800U)           /*!< SUSPend Mask */
+#define USB_CNTR_RESETM                          ((uint16_t)0x0400U)           /*!< RESET Mask   */
+#define USB_CNTR_SOFM                            ((uint16_t)0x0200U)           /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM                           ((uint16_t)0x0100U)           /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM                          ((uint16_t)0x0080U)           /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME                        ((uint16_t)0x0020U)           /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME                          ((uint16_t)0x0010U)           /*!< RESUME request */
+#define USB_CNTR_FSUSP                           ((uint16_t)0x0008U)           /*!< Force SUSPend */
+#define USB_CNTR_LPMODE                          ((uint16_t)0x0004U)           /*!< Low-power MODE */
+#define USB_CNTR_PDWN                            ((uint16_t)0x0002U)           /*!< Power DoWN */
+#define USB_CNTR_FRES                            ((uint16_t)0x0001U)           /*!< Force USB RESet */
+
+/******************  Bits definition for USB_ISTR register  *******************/
+#define USB_ISTR_EP_ID                           ((uint16_t)0x000FU)           /*!< EndPoint IDentifier (read-only bit)  */
+#define USB_ISTR_DIR                             ((uint16_t)0x0010U)           /*!< DIRection of transaction (read-only bit)  */
+#define USB_ISTR_L1REQ                           ((uint16_t)0x0080U)           /*!< LPM L1 state request  */
+#define USB_ISTR_ESOF                            ((uint16_t)0x0100U)           /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_SOF                             ((uint16_t)0x0200U)           /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_RESET                           ((uint16_t)0x0400U)           /*!< RESET (clear-only bit) */
+#define USB_ISTR_SUSP                            ((uint16_t)0x0800U)           /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_WKUP                            ((uint16_t)0x1000U)           /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_ERR                             ((uint16_t)0x2000U)           /*!< ERRor (clear-only bit) */
+#define USB_ISTR_PMAOVR                          ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_CTR                             ((uint16_t)0x8000U)           /*!< Correct TRansfer (clear-only bit) */
+
+#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
+#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
+#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
+#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
+#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
+#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
+#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
+
+/******************  Bits definition for USB_FNR register  ********************/
+#define USB_FNR_FN                               ((uint16_t)0x07FFU)           /*!< Frame Number */
+#define USB_FNR_LSOF                             ((uint16_t)0x1800U)           /*!< Lost SOF */
+#define USB_FNR_LCK                              ((uint16_t)0x2000U)           /*!< LoCKed */
+#define USB_FNR_RXDM                             ((uint16_t)0x4000U)           /*!< status of D- data line */
+#define USB_FNR_RXDP                             ((uint16_t)0x8000U)           /*!< status of D+ data line */
+
+/******************  Bits definition for USB_DADDR register    ****************/
+#define USB_DADDR_ADD                            ((uint8_t)0x7FU)              /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0                           ((uint8_t)0x01U)              /*!< Bit 0 */
+#define USB_DADDR_ADD1                           ((uint8_t)0x02U)              /*!< Bit 1 */
+#define USB_DADDR_ADD2                           ((uint8_t)0x04U)              /*!< Bit 2 */
+#define USB_DADDR_ADD3                           ((uint8_t)0x08U)              /*!< Bit 3 */
+#define USB_DADDR_ADD4                           ((uint8_t)0x10U)              /*!< Bit 4 */
+#define USB_DADDR_ADD5                           ((uint8_t)0x20U)              /*!< Bit 5 */
+#define USB_DADDR_ADD6                           ((uint8_t)0x40U)              /*!< Bit 6 */
+
+#define USB_DADDR_EF                             ((uint8_t)0x80U)              /*!< Enable Function */
+
+/******************  Bit definition for USB_BTABLE register  ******************/
+#define USB_BTABLE_BTABLE                        ((uint16_t)0xFFF8U)           /*!< Buffer Table */
+
+/******************  Bits definition for USB_BCDR register  *******************/
+#define USB_BCDR_BCDEN                           ((uint16_t)0x0001U)           /*!< Battery charging detector (BCD) enable */
+#define USB_BCDR_DCDEN                           ((uint16_t)0x0002U)           /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_PDEN                            ((uint16_t)0x0004U)           /*!< Primary detection (PD) mode enable */  
+#define USB_BCDR_SDEN                            ((uint16_t)0x0008U)           /*!< Secondary detection (SD) mode enable */ 
+#define USB_BCDR_DCDET                           ((uint16_t)0x0010U)           /*!< Data contact detection (DCD) status */ 
+#define USB_BCDR_PDET                            ((uint16_t)0x0020U)           /*!< Primary detection (PD) status */ 
+#define USB_BCDR_SDET                            ((uint16_t)0x0040U)           /*!< Secondary detection (SD) status */  
+#define USB_BCDR_PS2DET                          ((uint16_t)0x0080U)           /*!< PS2 port or proprietary charger detected */  
+#define USB_BCDR_DPPU                            ((uint16_t)0x8000U)           /*!< DP Pull-up Enable */  
+
+/*******************  Bit definition for LPMCSR register  *********************/
+#define USB_LPMCSR_LMPEN                         ((uint16_t)0x0001U)           /*!< LPM support enable  */
+#define USB_LPMCSR_LPMACK                        ((uint16_t)0x0002U)           /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_REMWAKE                       ((uint16_t)0x0008U)           /*!< bRemoteWake value received with last ACKed LPM Token */ 
+#define USB_LPMCSR_BESL                          ((uint16_t)0x00F0U)           /*!< BESL value received with last ACKed LPM Token  */ 
+
+/*!< Buffer descriptor table */
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos                (1U)                          
+#define USB_ADDR0_TX_ADDR0_TX_Msk                (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX                    USB_ADDR0_TX_ADDR0_TX_Msk     /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos                (1U)                          
+#define USB_ADDR1_TX_ADDR1_TX_Msk                (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX                    USB_ADDR1_TX_ADDR1_TX_Msk     /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos                (1U)                          
+#define USB_ADDR2_TX_ADDR2_TX_Msk                (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX                    USB_ADDR2_TX_ADDR2_TX_Msk     /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos                (1U)                          
+#define USB_ADDR3_TX_ADDR3_TX_Msk                (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX                    USB_ADDR3_TX_ADDR3_TX_Msk     /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos                (1U)                          
+#define USB_ADDR4_TX_ADDR4_TX_Msk                (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX                    USB_ADDR4_TX_ADDR4_TX_Msk     /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos                (1U)                          
+#define USB_ADDR5_TX_ADDR5_TX_Msk                (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX                    USB_ADDR5_TX_ADDR5_TX_Msk     /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos                (1U)                          
+#define USB_ADDR6_TX_ADDR6_TX_Msk                (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX                    USB_ADDR6_TX_ADDR6_TX_Msk     /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos                (1U)                          
+#define USB_ADDR7_TX_ADDR7_TX_Msk                (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX                    USB_ADDR7_TX_ADDR7_TX_Msk     /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos              (0U)                          
+#define USB_COUNT0_TX_COUNT0_TX_Msk              (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX                  USB_COUNT0_TX_COUNT0_TX_Msk   /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos              (0U)                          
+#define USB_COUNT1_TX_COUNT1_TX_Msk              (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX                  USB_COUNT1_TX_COUNT1_TX_Msk   /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos              (0U)                          
+#define USB_COUNT2_TX_COUNT2_TX_Msk              (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX                  USB_COUNT2_TX_COUNT2_TX_Msk   /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos              (0U)                          
+#define USB_COUNT3_TX_COUNT3_TX_Msk              (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX                  USB_COUNT3_TX_COUNT3_TX_Msk   /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos              (0U)                          
+#define USB_COUNT4_TX_COUNT4_TX_Msk              (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX                  USB_COUNT4_TX_COUNT4_TX_Msk   /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos              (0U)                          
+#define USB_COUNT5_TX_COUNT5_TX_Msk              (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX                  USB_COUNT5_TX_COUNT5_TX_Msk   /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos              (0U)                          
+#define USB_COUNT6_TX_COUNT6_TX_Msk              (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX                  USB_COUNT6_TX_COUNT6_TX_Msk   /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos              (0U)                          
+#define USB_COUNT7_TX_COUNT7_TX_Msk              (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX                  USB_COUNT7_TX_COUNT7_TX_Msk   /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos                (1U)                          
+#define USB_ADDR0_RX_ADDR0_RX_Msk                (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX                    USB_ADDR0_RX_ADDR0_RX_Msk     /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos                (1U)                          
+#define USB_ADDR1_RX_ADDR1_RX_Msk                (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX                    USB_ADDR1_RX_ADDR1_RX_Msk     /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos                (1U)                          
+#define USB_ADDR2_RX_ADDR2_RX_Msk                (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX                    USB_ADDR2_RX_ADDR2_RX_Msk     /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos                (1U)                          
+#define USB_ADDR3_RX_ADDR3_RX_Msk                (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX                    USB_ADDR3_RX_ADDR3_RX_Msk     /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos                (1U)                          
+#define USB_ADDR4_RX_ADDR4_RX_Msk                (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX                    USB_ADDR4_RX_ADDR4_RX_Msk     /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos                (1U)                          
+#define USB_ADDR5_RX_ADDR5_RX_Msk                (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX                    USB_ADDR5_RX_ADDR5_RX_Msk     /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos                (1U)                          
+#define USB_ADDR6_RX_ADDR6_RX_Msk                (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX                    USB_ADDR6_RX_ADDR6_RX_Msk     /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos                (1U)                          
+#define USB_ADDR7_RX_ADDR7_RX_Msk                (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX                    USB_ADDR7_RX_ADDR7_RX_Msk     /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos              (0U)                          
+#define USB_COUNT0_RX_COUNT0_RX_Msk              (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX                  USB_COUNT0_RX_COUNT0_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT0_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK                  USB_COUNT0_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0                (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1                (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2                (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3                (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4                (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT0_RX_BLSIZE_Msk                 (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE                     USB_COUNT0_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos              (0U)                          
+#define USB_COUNT1_RX_COUNT1_RX_Msk              (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX                  USB_COUNT1_RX_COUNT1_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT1_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK                  USB_COUNT1_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0                (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1                (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2                (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3                (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4                (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT1_RX_BLSIZE_Msk                 (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE                     USB_COUNT1_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos              (0U)                          
+#define USB_COUNT2_RX_COUNT2_RX_Msk              (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX                  USB_COUNT2_RX_COUNT2_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT2_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK                  USB_COUNT2_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0                (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1                (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2                (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3                (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4                (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT2_RX_BLSIZE_Msk                 (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE                     USB_COUNT2_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos              (0U)                          
+#define USB_COUNT3_RX_COUNT3_RX_Msk              (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX                  USB_COUNT3_RX_COUNT3_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT3_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK                  USB_COUNT3_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0                (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1                (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2                (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3                (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4                (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT3_RX_BLSIZE_Msk                 (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE                     USB_COUNT3_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos              (0U)                          
+#define USB_COUNT4_RX_COUNT4_RX_Msk              (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX                  USB_COUNT4_RX_COUNT4_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT4_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK                  USB_COUNT4_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0                (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1                (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2                (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3                (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4                (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT4_RX_BLSIZE_Msk                 (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE                     USB_COUNT4_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos              (0U)                          
+#define USB_COUNT5_RX_COUNT5_RX_Msk              (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX                  USB_COUNT5_RX_COUNT5_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT5_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK                  USB_COUNT5_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0                (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1                (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2                (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3                (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4                (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT5_RX_BLSIZE_Msk                 (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE                     USB_COUNT5_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos              (0U)                          
+#define USB_COUNT6_RX_COUNT6_RX_Msk              (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX                  USB_COUNT6_RX_COUNT6_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT6_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK                  USB_COUNT6_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0                (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1                (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2                (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3                (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4                (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT6_RX_BLSIZE_Msk                 (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE                     USB_COUNT6_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos              (0U)                          
+#define USB_COUNT7_RX_COUNT7_RX_Msk              (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX                  USB_COUNT7_RX_COUNT7_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT7_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK                  USB_COUNT7_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0                (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1                (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2                (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3                (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4                (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT7_RX_BLSIZE_Msk                 (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE                     USB_COUNT7_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************** CAN Instances ******************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                        ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA1_Channel7) || \
+                                       ((INSTANCE) == DMA2_Channel1) || \
+                                       ((INSTANCE) == DMA2_Channel2) || \
+                                       ((INSTANCE) == DMA2_Channel3) || \
+                                       ((INSTANCE) == DMA2_Channel4) || \
+                                       ((INSTANCE) == DMA2_Channel5) || \
+                                       ((INSTANCE) == DMA2_Channel6) || \
+                                       ((INSTANCE) == DMA2_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOH))
+
+/******************************* GPIO AF Instances ****************************/
+/* On L4, all GPIO Bank support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L4, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************* LCD Instances ********************************/
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON)
+
+/******************************* QSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                                       ((INSTANCE) == SAI1_Block_B))
+
+/****************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM15)   || \
+                                            ((INSTANCE) == TIM16))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM15)  || \
+                                               ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
+                                                    ((INSTANCE) == TIM2)    || \
+                                                    ((INSTANCE) == TIM15)   || \
+                                                    ((INSTANCE) == TIM16))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM15)  || \
+                                                     ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                      ((INSTANCE) == TIM2))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                          ((INSTANCE) == TIM2))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                             ((INSTANCE) == TIM2))
+      
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM6)  || \
+                                            ((INSTANCE) == TIM7)  || \
+                                            ((INSTANCE) == TIM15))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM2))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM15) || \
+                                            ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                 ((INSTANCE) == USART2) || \
+                                                 ((INSTANCE) == USART3) || \
+                                                 ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                          ((INSTANCE) == USART2) || \
+                                          ((INSTANCE) == USART3))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/******************************* USB Instances *******************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/**
+  * @}
+  */
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32L4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */ 
+/*  product lines within the same STM32L4 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn                    ADC1_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn        TIM1_TRG_COM_IRQn
+#define HASH_RNG_IRQn                  RNG_IRQn
+#define HASH_CRS_IRQn                  CRS_IRQn
+#define USB_FS_IRQn                    USB_IRQn
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler              ADC1_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler  TIM1_TRG_COM_IRQHandler
+#define HASH_RNG_IRQHandler            RNG_IRQHandler
+#define HASH_CRS_IRQHandler            CRS_IRQHandler
+#define USB_FS_IRQHandler              USB_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L433xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l4xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,240 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32L4xx device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral�s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx
+  * @{
+  */
+
+#ifndef __STM32L4xx_H
+#define __STM32L4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L4)
+#define STM32L4
+#endif /* STM32L4 */
+
+/* Uncomment the line below according to the target STM32L4 device used in your
+   application
+  */
+
+#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+    !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
+    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
+    !defined (STM32L496xx) && !defined (STM32L4A6xx)
+  /* #define STM32L431xx */   /*!< STM32L431xx Devices */
+  /* #define STM32L432xx */   /*!< STM32L432xx Devices */
+#define STM32L433xx   /*!< STM32L433xx Devices */
+  /* #define STM32L442xx */   /*!< STM32L442xx Devices */
+  /* #define STM32L443xx */   /*!< STM32L443xx Devices */
+  /* #define STM32L451xx */   /*!< STM32L451xx Devices */
+  /* #define STM32L452xx */   /*!< STM32L452xx Devices */
+  /* #define STM32L462xx */   /*!< STM32L462xx Devices */
+  /* #define STM32L471xx */   /*!< STM32L471xx Devices */
+  /* #define STM32L475xx */   /*!< STM32L475xx Devices */
+  /* #define STM32L476xx */   /*!< STM32L476xx Devices */
+  /* #define STM32L485xx */   /*!< STM32L485xx Devices */
+  /* #define STM32L486xx */   /*!< STM32L486xx Devices */
+  /* #define STM32L496xx */   /*!< STM32L496xx Devices */
+  /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.3.1
+  */
+#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32L4_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L431xx)
+  #include "stm32l431xx.h"
+#elif defined(STM32L432xx)
+  #include "stm32l432xx.h"
+#elif defined(STM32L433xx)
+  #include "stm32l433xx.h"
+#elif defined(STM32L442xx)
+  #include "stm32l442xx.h"
+#elif defined(STM32L443xx)
+  #include "stm32l443xx.h"
+#elif defined(STM32L451xx)
+  #include "stm32l451xx.h"
+#elif defined(STM32L452xx)
+  #include "stm32l452xx.h"
+#elif defined(STM32L462xx)
+  #include "stm32l462xx.h"
+#elif defined(STM32L471xx)
+  #include "stm32l471xx.h"
+#elif defined(STM32L475xx)
+  #include "stm32l475xx.h"
+#elif defined(STM32L476xx)
+  #include "stm32l476xx.h"
+#elif defined(STM32L485xx)
+  #include "stm32l485xx.h"
+#elif defined(STM32L486xx)
+  #include "stm32l486xx.h"
+#elif defined(STM32L496xx)
+  #include "stm32l496xx.h"
+#elif defined(STM32L4A6xx)
+  #include "stm32l4a6xx.h"
+#else
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/system_stm32l4xx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,127 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L4XX_H
+#define __SYSTEM_STM32L4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32L4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L4xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16];     /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L4XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/objects.h	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,201 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "mbed_wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-int adc_inited = 0;
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-    uint32_t function = (uint32_t)NC;
-
-    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
-    //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be between 0xF0 and 0xFF
-    if ((pin < 0xF0) || (pin >= 0x100)) {
-        // Normal channels
-        // Get the peripheral name from the pin and assign it to the object
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
-        // Get the functions (adc channel) from the pin and assign it to the object
-        function = pinmap_function(pin, PinMap_ADC);
-        // Configure GPIO
-        pinmap_pinout(pin, PinMap_ADC);
-    } else {
-        // Internal channels
-        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
-        function = pinmap_function(pin, PinMap_ADC_Internal);
-        // No GPIO configuration for internal channels
-    }
-    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-    MBED_ASSERT(function != (uint32_t)NC);
-
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // The ADC initialization is done once
-    if (adc_inited == 0) {
-        adc_inited = 1;
-
-        // Enable ADC clock
-        __HAL_RCC_ADC_CLK_ENABLE();
-        __HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_SYSCLK);
-
-        obj->handle.State = HAL_ADC_STATE_RESET;
-        // Configure ADC
-        obj->handle.Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV2;          // Asynchronous clock mode, input ADC clock
-        obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
-        obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-        obj->handle.Init.ScanConvMode          = DISABLE;                       // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
-        obj->handle.Init.EOCSelection          = ADC_EOC_SINGLE_CONV;           // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
-        obj->handle.Init.LowPowerAutoWait      = DISABLE;
-        obj->handle.Init.ContinuousConvMode    = DISABLE;                       // Continuous mode disabled to have only 1 conversion at each conversion trig
-        obj->handle.Init.NbrOfConversion       = 1;                             // Parameter discarded because sequencer is disabled
-        obj->handle.Init.DiscontinuousConvMode = DISABLE;                       // Parameter discarded because sequencer is disabled
-        obj->handle.Init.NbrOfDiscConversion   = 1;                             // Parameter discarded because sequencer is disabled
-        obj->handle.Init.ExternalTrigConv      = ADC_SOFTWARE_START;            // Software start to trig the 1st conversion manually, without external event
-        obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
-        obj->handle.Init.DMAContinuousRequests = DISABLE;
-        obj->handle.Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN;      // DR register is overwritten with the last conversion result in case of overrun
-        obj->handle.Init.OversamplingMode      = DISABLE;                       // No oversampling
-
-        if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
-            error("Cannot initialize ADC\n");
-        }
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj)
-{
-    ADC_ChannelConfTypeDef sConfig = {0};
-
-    // Configure ADC channel
-    switch (obj->channel) {
-        case 0:
-            sConfig.Channel = ADC_CHANNEL_VREFINT;
-            break;
-        case 1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case 2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case 3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case 4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case 5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case 6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case 7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case 8:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case 9:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case 10:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case 11:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case 12:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case 13:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case 14:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case 15:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-        case 16:
-            sConfig.Channel = ADC_CHANNEL_16;
-            break;
-        case 17:
-            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
-            break;
-        case 18:
-            sConfig.Channel = ADC_CHANNEL_VBAT;
-            break;
-        default:
-            return 0;
-    }
-
-    sConfig.Rank         = ADC_REGULAR_RANK_1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5;
-    sConfig.SingleDiff   = ADC_SINGLE_ENDED;
-    sConfig.OffsetNumber = ADC_OFFSET_NONE;
-    sConfig.Offset       = 0;
-
-    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
-
-    HAL_ADC_Start(&obj->handle); // Start conversion
-
-    // Wait end of conversion and get value
-    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
-        return (HAL_ADC_GetValue(&obj->handle));
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,188 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include <stdbool.h>
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    static bool adc_calibrated = false;
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
+    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // Configure ADC object structures
+    obj->handle.State = HAL_ADC_STATE_RESET;
+    obj->handle.Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV2;          // Asynchronous clock mode, input ADC clock
+    obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
+    obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+    obj->handle.Init.ScanConvMode          = DISABLE;                       // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
+    obj->handle.Init.EOCSelection          = ADC_EOC_SINGLE_CONV;           // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
+    obj->handle.Init.LowPowerAutoWait      = DISABLE;
+    obj->handle.Init.ContinuousConvMode    = DISABLE;                       // Continuous mode disabled to have only 1 conversion at each conversion trig
+    obj->handle.Init.NbrOfConversion       = 1;                             // Parameter discarded because sequencer is disabled
+    obj->handle.Init.DiscontinuousConvMode = DISABLE;                       // Parameter discarded because sequencer is disabled
+    obj->handle.Init.NbrOfDiscConversion   = 1;                             // Parameter discarded because sequencer is disabled
+    obj->handle.Init.ExternalTrigConv      = ADC_SOFTWARE_START;            // Software start to trig the 1st conversion manually, without external event
+    obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
+    obj->handle.Init.DMAContinuousRequests = DISABLE;
+    obj->handle.Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN;      // DR register is overwritten with the last conversion result in case of overrun
+    obj->handle.Init.OversamplingMode      = DISABLE;                       // No oversampling
+
+    // Enable ADC clock
+    __HAL_RCC_ADC_CLK_ENABLE();
+    __HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_SYSCLK);
+
+    if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+        error("Cannot initialize ADC");
+    }
+
+    // ADC calibration is done only once
+    if (!adc_calibrated) {
+        adc_calibrated = true;
+        HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED);
+    }
+}
+
+uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    // Configure ADC channel
+    switch (obj->channel) {
+        case 0:
+            sConfig.Channel = ADC_CHANNEL_VREFINT;
+            break;
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_16;
+            break;
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+            break;
+        case 18:
+            sConfig.Channel = ADC_CHANNEL_VBAT;
+            break;
+        default:
+            return 0;
+    }
+
+    sConfig.Rank         = ADC_REGULAR_RANK_1;
+    sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5;
+    sConfig.SingleDiff   = ADC_SINGLE_ENDED;
+    sConfig.OffsetNumber = ADC_OFFSET_NONE;
+    sConfig.Offset       = 0;
+
+    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+    HAL_ADC_Start(&obj->handle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+        return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+    } else {
+        return 0;
+    }
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h	Wed Jan 17 15:23:54 2018 +0000
@@ -132,9 +132,9 @@
 {
 	uint32_t newValue;
 	do {
-		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
+		newValue = (uint32_t)__LDREXW(ptr) | mask;
 
-	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+	} while (__STREXW(newValue, ptr));
 }
 
 
@@ -142,9 +142,9 @@
 {
 	uint32_t newValue;
 	do {
-		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
+		newValue = (uint32_t)__LDREXW(ptr) &~mask;
 
-	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+	} while (__STREXW(newValue, ptr));
 }
 
 #if  defined ( __GNUC__ ) && !defined ( __CC_ARM )

--- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h	Wed Jan 17 15:23:54 2018 +0000
@@ -611,6 +611,8 @@
 
 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
 
+#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
+
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,187 +27,22 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
-#include "mbed_assert.h"
-#include "serial_api.h"
-#include "serial_api_hal.h"
 
 #if DEVICE_SERIAL
 
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include <string.h>
-#include "PeripheralPins.h"
+#include "serial_api_hal.h"
 
-#define UART_NUM (6)
+#if defined (TARGET_STM32L432xC)
+    #define UART_NUM (3)
+#else
+    #define UART_NUM (6) // max value
+#endif
 
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+uint32_t serial_irq_ids[UART_NUM] = {0};
 UART_HandleTypeDef uart_handlers[UART_NUM];
 
 static uart_irq_handler irq_handler;
 
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-    
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj_s->uart != (UARTName)NC);
-
-    // Enable USART clock
-    if (obj_s->uart == UART_1) {
-        __HAL_RCC_USART1_FORCE_RESET();
-        __HAL_RCC_USART1_RELEASE_RESET();
-        __HAL_RCC_USART1_CLK_ENABLE();
-        obj_s->index = 0;
-    }
-    if (obj_s->uart == UART_2) {
-        __HAL_RCC_USART2_FORCE_RESET();
-        __HAL_RCC_USART2_RELEASE_RESET();
-        __HAL_RCC_USART2_CLK_ENABLE();
-        obj_s->index = 1;
-    }
-
-#if defined(USART3_BASE)
-    if (obj_s->uart == UART_3) {
-        __HAL_RCC_USART3_FORCE_RESET();
-        __HAL_RCC_USART3_RELEASE_RESET();
-        __HAL_RCC_USART3_CLK_ENABLE();
-        obj_s->index = 2;
-    }
-#endif
-
-#if defined(UART4_BASE)
-    if (obj_s->uart == UART_4) {
-        __HAL_RCC_UART4_FORCE_RESET();
-        __HAL_RCC_UART4_RELEASE_RESET();
-        __HAL_RCC_UART4_CLK_ENABLE();
-        obj_s->index = 3;
-    }
-#endif
-
-#if defined(UART5_BASE)
-    if (obj_s->uart == UART_5) {
-        __HAL_RCC_UART5_FORCE_RESET();
-        __HAL_RCC_UART5_RELEASE_RESET();
-        __HAL_RCC_UART5_CLK_ENABLE();
-        obj_s->index = 4;
-    }
-#endif
-
-#if defined(LPUART1_BASE)
-    if (obj_s->uart == LPUART_1) {
-        __HAL_RCC_LPUART1_FORCE_RESET();
-        __HAL_RCC_LPUART1_RELEASE_RESET();
-        __HAL_RCC_LPUART1_CLK_ENABLE();
-        obj_s->index = 5;
-    }
-#endif
-
-    // Configure UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj_s->baudrate = 9600;
-    obj_s->databits = UART_WORDLENGTH_8B;
-    obj_s->stopbits = UART_STOPBITS_1;
-    obj_s->parity   = UART_PARITY_NONE;
-    
-#if DEVICE_SERIAL_FC
-    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
-#endif
-
-    obj_s->pin_tx = tx;
-    obj_s->pin_rx = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj_s->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-      
-    // Reset UART and disable clock
-    if (obj_s->uart == UART_1) {
-        __HAL_RCC_USART1_FORCE_RESET();
-        __HAL_RCC_USART1_RELEASE_RESET();
-        __HAL_RCC_USART1_CLK_DISABLE();
-    }
-
-    if (obj_s->uart == UART_2) {
-        __HAL_RCC_USART2_FORCE_RESET();
-        __HAL_RCC_USART2_RELEASE_RESET();
-        __HAL_RCC_USART2_CLK_DISABLE();
-    }
-
-#if defined(USART3_BASE)
-    if (obj_s->uart == UART_3) {
-        __HAL_RCC_USART3_FORCE_RESET();
-        __HAL_RCC_USART3_RELEASE_RESET();
-        __HAL_RCC_USART3_CLK_DISABLE();
-    }
-#endif
-
-#if defined(UART4_BASE)
-    if (obj_s->uart == UART_4) {
-        __HAL_RCC_UART4_FORCE_RESET();
-        __HAL_RCC_UART4_RELEASE_RESET();
-        __HAL_RCC_UART4_CLK_DISABLE();
-    }
-#endif
-
-#if defined(UART5_BASE)
-    if (obj_s->uart == UART_5) {
-        __HAL_RCC_UART5_FORCE_RESET();
-        __HAL_RCC_UART5_RELEASE_RESET();
-        __HAL_RCC_UART5_CLK_DISABLE();
-    }
-#endif
-
-#if defined(LPUART1_BASE)
-    if (obj_s->uart == LPUART_1) {
-        __HAL_RCC_LPUART1_FORCE_RESET();
-        __HAL_RCC_LPUART1_RELEASE_RESET();
-        __HAL_RCC_LPUART1_CLK_DISABLE();
-    }
-#endif
-
-    // Configure GPIOs
-    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj_s->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    struct serial_s *obj_s = SERIAL_S(obj);
-
-    obj_s->baudrate = baudrate;
-    init_uart(obj);
-}
-
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
@@ -491,7 +326,7 @@
             irq_n = USART2_IRQn;
             break;
 
-#if defined(UART3_BASE)
+#if defined(USART3_BASE)
         case 2:
             irq_n = USART3_IRQn;
             break;
@@ -806,7 +641,7 @@
     }
 }
 
-#endif
+#endif /* DEVICE_SERIAL_ASYNCH */
 
 #if DEVICE_SERIAL_FC
 
@@ -865,6 +700,6 @@
     init_uart(obj);
 }
 
-#endif
+#endif /* DEVICE_SERIAL_FC */
 
-#endif
+#endif /* DEVICE_SERIAL */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/analogin_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+uint16_t adc_read(analogin_t *obj);
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    uint16_t value = adc_read(obj);
+    // 12-bit to 16-bit conversion
+    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
+    return value;
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = adc_read(obj);
+    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
+}
+
+#endif

--- a/targets/TARGET_STM/can_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/can_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -57,14 +57,14 @@
         __HAL_RCC_CAN1_CLK_ENABLE();
         obj->index = 0;
     }
-#if defined(CAN2_BASE) && defined(CAN_2)
+#if defined(CAN2_BASE) && (CAN_NUM > 1)
     else if (can == CAN_2) {
         __HAL_RCC_CAN1_CLK_ENABLE(); // needed to set filters
         __HAL_RCC_CAN2_CLK_ENABLE();
         obj->index = 1;
     }
 #endif
-#if defined(CAN3_BASE) && defined(CAN_3)
+#if defined(CAN3_BASE) && (CAN_NUM > 2)
     else if (can == CAN_3) {
         __HAL_RCC_CAN3_CLK_ENABLE();
         obj->index = 2;
@@ -103,7 +103,13 @@
 
     can_registers_init(obj);
 
+    /* Bits 27:14 are available for dual CAN configuration and are reserved for
+       single CAN configuration: */
+#if defined(CAN3_BASE) && (CAN_NUM > 2)
+    uint32_t filter_number = (can == CAN_1 || can == CAN_3) ? 0 : 14;
+#else
     uint32_t filter_number = (can == CAN_1) ? 0 : 14;
+#endif
     can_filter(obj, 0, 0, CANStandard, filter_number);
 }
 
@@ -132,14 +138,14 @@
         __HAL_RCC_CAN1_RELEASE_RESET();
         __HAL_RCC_CAN1_CLK_DISABLE();
     }
-#if defined(CAN2_BASE) && defined(CAN_2)
+#if defined(CAN2_BASE) && (CAN_NUM > 1)
     if (can == CAN_2) {
         __HAL_RCC_CAN2_FORCE_RESET();
         __HAL_RCC_CAN2_RELEASE_RESET();
         __HAL_RCC_CAN2_CLK_DISABLE();
     }
 #endif
-#if defined(CAN3_BASE) && defined(CAN_3)
+#if defined(CAN3_BASE) && (CAN_NUM > 2)
     if (can == CAN_3) {
         __HAL_RCC_CAN3_FORCE_RESET();
         __HAL_RCC_CAN3_RELEASE_RESET();
@@ -277,9 +283,9 @@
 
     can->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
     if (!(msg.format)) {
-      can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | msg.type);
+      can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | (msg.type << 1));
     } else {
-      can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | msg.type);
+      can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | (msg.type << 1));
     }
 
     /* Set up the DLC */
@@ -562,7 +568,7 @@
 {
     can_irq(CAN_1, 0);
 }
-#if defined(CAN2_BASE) && defined(CAN_2)
+#if defined(CAN2_BASE) && (CAN_NUM > 1)
 void CAN2_RX0_IRQHandler(void)
 {
     can_irq(CAN_2, 1);
@@ -576,18 +582,18 @@
     can_irq(CAN_2, 1);
 }
 #endif
-#if defined(CAN3_BASE) && defined(CAN_3)
+#if defined(CAN3_BASE) && (CAN_NUM > 2)
 void CAN3_RX0_IRQHandler(void)
 {
-    can_irq(CAN_3, 1);
+    can_irq(CAN_3, 2);
 }
 void CAN3_TX_IRQHandler(void)
 {
-    can_irq(CAN_3, 1);
+    can_irq(CAN_3, 2);
 }
 void CAN3_SCE_IRQHandler(void)
 {
-    can_irq(CAN_3, 1);
+    can_irq(CAN_3, 2);
 }
 #endif
 #endif // else
@@ -630,7 +636,7 @@
                 return;
         }
     }
-#if defined(CAN2_BASE) && defined(CAN_2)
+#if defined(CAN2_BASE) && (CAN_NUM > 1)
     else if ((CANName) can == CAN_2) {
         switch (type) {
             case IRQ_RX:
@@ -663,7 +669,7 @@
         }
     }
 #endif
-#if defined(CAN3_BASE) && defined(CAN_3)
+#if defined(CAN3_BASE) && (CAN_NUM > 2)
     else if ((CANName) can == CAN_3) {
         switch (type) {
             case IRQ_RX:
@@ -711,4 +717,3 @@
 }
 
 #endif // DEVICE_CAN
-

--- a/targets/TARGET_STM/hal_tick_32b.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/hal_tick_32b.c	Wed Jan 17 15:23:54 2018 +0000
@@ -42,7 +42,7 @@
     if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
         if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC2) == SET) {
             __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
-            uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+            uint32_t val = __HAL_TIM_GET_COUNTER(&TimMasterHandle);
             if ((val - PreviousVal) >= HAL_TICK_DELAY) {
                 // Increment HAL variable
                 HAL_IncTick();
@@ -114,7 +114,7 @@
 
     // Channel 2 for HAL tick
     HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
-    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+    PreviousVal = __HAL_TIM_GET_COUNTER(&TimMasterHandle);
     __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
     __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
 

--- a/targets/TARGET_STM/i2c_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/i2c_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -274,10 +274,6 @@
         obj_s->index = 0;
         __HAL_RCC_I2C1_CLK_ENABLE();
         // Configure I2C pins
-        pinmap_pinout(sda, PinMap_I2C_SDA);
-        pinmap_pinout(scl, PinMap_I2C_SCL);
-        pin_mode(sda, OpenDrainPullUp);
-        pin_mode(scl, OpenDrainPullUp);
         obj_s->event_i2cIRQ = I2C1_EV_IRQn;
         obj_s->error_i2cIRQ = I2C1_ER_IRQn;
     }
@@ -287,11 +283,6 @@
     if (obj_s->i2c == I2C_2) {
         obj_s->index = 1;
         __HAL_RCC_I2C2_CLK_ENABLE();
-        // Configure I2C pins
-        pinmap_pinout(sda, PinMap_I2C_SDA);
-        pinmap_pinout(scl, PinMap_I2C_SCL);
-        pin_mode(sda, OpenDrainPullUp);
-        pin_mode(scl, OpenDrainPullUp);
         obj_s->event_i2cIRQ = I2C2_EV_IRQn;
         obj_s->error_i2cIRQ = I2C2_ER_IRQn;
     }
@@ -301,11 +292,6 @@
     if (obj_s->i2c == I2C_3) {
         obj_s->index = 2;
         __HAL_RCC_I2C3_CLK_ENABLE();
-        // Configure I2C pins
-        pinmap_pinout(sda, PinMap_I2C_SDA);
-        pinmap_pinout(scl, PinMap_I2C_SCL);
-        pin_mode(sda, OpenDrainPullUp);
-        pin_mode(scl, OpenDrainPullUp);
         obj_s->event_i2cIRQ = I2C3_EV_IRQn;
         obj_s->error_i2cIRQ = I2C3_ER_IRQn;
     }
@@ -315,11 +301,6 @@
     if (obj_s->i2c == I2C_4) {
         obj_s->index = 3;
         __HAL_RCC_I2C4_CLK_ENABLE();
-        // Configure I2C pins
-        pinmap_pinout(sda, PinMap_I2C_SDA);
-        pinmap_pinout(scl, PinMap_I2C_SCL);
-        pin_mode(sda, OpenDrainPullUp);
-        pin_mode(scl, OpenDrainPullUp);
         obj_s->event_i2cIRQ = I2C4_EV_IRQn;
         obj_s->error_i2cIRQ = I2C4_ER_IRQn;
     }
@@ -329,16 +310,17 @@
     if (obj_s->i2c == FMPI2C_1) {
         obj_s->index = 4;
         __HAL_RCC_FMPI2C1_CLK_ENABLE();
-        // Configure I2C pins
-        pinmap_pinout(sda, PinMap_I2C_SDA);
-        pinmap_pinout(scl, PinMap_I2C_SCL);
-        pin_mode(sda, OpenDrainPullUp);
-        pin_mode(scl, OpenDrainPullUp);
         obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
         obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
     }
 #endif
 
+    // Configure I2C pins
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    pin_mode(sda, OpenDrainNoPull);
+    pin_mode(scl, OpenDrainNoPull);
+
     // I2C configuration
     // Default hz value used for timeout computation
     if(!obj_s->hz)
@@ -431,7 +413,7 @@
 
 #ifdef I2C_ANALOGFILTER_ENABLE
     /* Enable the Analog I2C Filter */
-    HAL_I2CEx_AnalogFilter_Config(handle,I2C_ANALOGFILTER_ENABLE);
+    HAL_I2CEx_ConfigAnalogFilter(handle,I2C_ANALOGFILTER_ENABLE);
 #endif
 
     // I2C configuration

--- a/targets/TARGET_STM/lp_ticker.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/lp_ticker.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -31,20 +31,11 @@
 
 #if DEVICE_LOWPOWERTIMER
 
-#include "ticker_api.h"
-#include "lp_ticker_api.h"
-#include "rtc_api.h"
 #include "rtc_api_hal.h"
 
-static uint8_t lp_ticker_inited = 0;
-
 void lp_ticker_init(void)
 {
-    if (lp_ticker_inited) return;
-    lp_ticker_inited = 1;
-
     rtc_init();
-    rtc_set_irq_handler((uint32_t) lp_ticker_irq_handler);
 }
 
 uint32_t lp_ticker_read(void)
@@ -52,8 +43,6 @@
     uint32_t usecs = 0;
     time_t time = 0;
 
-    lp_ticker_init();
-
     do {
         time = rtc_read();
         usecs = rtc_read_subseconds();
@@ -82,7 +71,7 @@
 
 void lp_ticker_clear_interrupt(void)
 {
-
+    NVIC_ClearPendingIRQ(RTC_WKUP_IRQn);
 }
 
-#endif
+#endif /* DEVICE_LOWPOWERTIMER */

--- a/targets/TARGET_STM/mbed_rtx.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/mbed_rtx.h	Wed Jan 17 15:23:54 2018 +0000
@@ -52,7 +52,8 @@
 #elif defined(TARGET_STM32F303VC)
 #define INITIAL_SP              (0x2000A000UL)
 
-#elif defined(TARGET_STM32L432KC)
+#elif defined(TARGET_STM32L432KC) ||\
+      defined (TARGET_STM32L433RC)
 #define INITIAL_SP              (0x20010000UL)
 
 #elif (defined(TARGET_STM32F303RE) ||\

--- a/targets/TARGET_STM/rtc_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/rtc_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,29 +27,15 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
+
 #if DEVICE_RTC
 
-#include "rtc_api.h"
 #include "rtc_api_hal.h"
 #include "mbed_error.h"
 #include "mbed_mktime.h"
 
 static RTC_HandleTypeDef RtcHandle;
 
-#if RTC_LSI
-#define RTC_CLOCK LSI_VALUE
-#else
-#define RTC_CLOCK LSE_VALUE
-#endif
-
-#if DEVICE_LOWPOWERTIMER
-#define RTC_ASYNCH_PREDIV ((RTC_CLOCK - 1) / 0x8000)
-#define RTC_SYNCH_PREDIV  (RTC_CLOCK / (RTC_ASYNCH_PREDIV + 1) - 1)
-#else
-#define RTC_ASYNCH_PREDIV (0x007F)
-#define RTC_SYNCH_PREDIV  (RTC_CLOCK / (RTC_ASYNCH_PREDIV + 1) - 1)
-#endif
-
 #if DEVICE_LOWPOWERTIMER
 static void (*irq_handler)(void);
 static void RTC_IRQHandler(void);
@@ -61,38 +47,38 @@
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
     // Enable access to Backup domain
+    __HAL_RCC_PWR_CLK_ENABLE();
     HAL_PWR_EnableBkUpAccess();
 
-    RtcHandle.Instance = RTC;
-    RtcHandle.State = HAL_RTC_STATE_RESET;
+    if (rtc_isenabled()) {
+        return;
+    }
 
-#if !RTC_LSI
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+#if MBED_CONF_TARGET_LSE_AVAILABLE
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE;
     RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
     RCC_OscInitStruct.LSEState       = RCC_LSE_ON;
     RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
 
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
-    } else {
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         error("Cannot initialize RTC with LSE\n");
     }
 
+    __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
+    __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+
     PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
     PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
         error("PeriphClkInitStruct RTC failed with LSE\n");
     }
-#else /* !RTC_LSI */
-    __HAL_RCC_PWR_CLK_ENABLE();
-
+#else /*  MBED_CONF_TARGET_LSE_AVAILABLE */
     // Reset Backup domain
     __HAL_RCC_BACKUPRESET_FORCE();
     __HAL_RCC_BACKUPRESET_RELEASE();
 
     // Enable LSI clock
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE;
     RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
     RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
     RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
@@ -108,46 +94,50 @@
     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
         error("PeriphClkInitStruct RTC failed with LSI\n");
     }
-#endif /* !RTC_LSI */
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
 
     // Enable RTC
     __HAL_RCC_RTC_ENABLE();
 
+    RtcHandle.Instance = RTC;
+    RtcHandle.State = HAL_RTC_STATE_RESET;
+
 #if TARGET_STM32F1
     RtcHandle.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
 #else /* TARGET_STM32F1 */
     RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
-    RtcHandle.Init.AsynchPrediv   = RTC_ASYNCH_PREDIV;
-    RtcHandle.Init.SynchPrediv    = RTC_SYNCH_PREDIV;
+
+    /* PREDIV_A : 7-bit asynchronous prescaler */
+#if DEVICE_LOWPOWERTIMER
+    /* PREDIV_A is set to a small value to improve the SubSeconds resolution */
+    /* with a 32768Hz clock, PREDIV_A=7 gives a precision of 244us */
+    RtcHandle.Init.AsynchPrediv = 7;
+#else
+    /* PREDIV_A is set to the maximum value to improve the consumption */
+    RtcHandle.Init.AsynchPrediv   = 0x007F;
+#endif
+    /* PREDIV_S : 15-bit synchronous prescaler */
+    /* PREDIV_S is set in order to get a 1 Hz clock */
+    RtcHandle.Init.SynchPrediv    = RTC_CLOCK / (RtcHandle.Init.AsynchPrediv + 1) - 1;
     RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
     RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
     RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
 #endif /* TARGET_STM32F1 */
 
     if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
-        error("RTC error: RTC initialization failed.");
+        error("RTC initialization failed");
     }
 
-#if DEVICE_LOWPOWERTIMER
+    rtc_synchronize(); // Wait for RSF
 
-#if !RTC_LSI
-    if (!rtc_isenabled())
-#endif /* !RTC_LSI */
-    {
+    if (!rtc_isenabled()) {
         rtc_write(0);
     }
-
-    NVIC_ClearPendingIRQ(RTC_WKUP_IRQn);
-    NVIC_DisableIRQ(RTC_WKUP_IRQn);
-    NVIC_SetVector(RTC_WKUP_IRQn, (uint32_t)RTC_IRQHandler);
-    NVIC_EnableIRQ(RTC_WKUP_IRQn);
-
-#endif /* DEVICE_LOWPOWERTIMER */
 }
 
 void rtc_free(void)
 {
-#if RTC_LSI
+#if !MBED_CONF_TARGET_LSE_AVAILABLE
     // Enable Power clock
     __HAL_RCC_PWR_CLK_ENABLE();
 
@@ -279,8 +269,12 @@
 #endif /* TARGET_STM32F1 */
 
     // Change the RTC current date/time
-    HAL_RTC_SetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN);
-    HAL_RTC_SetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN);
+    if (HAL_RTC_SetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN) != HAL_OK) {
+        error("HAL_RTC_SetDate error\n");
+    }
+    if (HAL_RTC_SetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN) != HAL_OK) {
+        error("HAL_RTC_SetTime error\n");
+    }
 }
 
 int rtc_isenabled(void)
@@ -292,11 +286,20 @@
 #endif /* TARGET_STM32F1 */
 }
 
+void rtc_synchronize(void)
+{
+    RtcHandle.Instance = RTC;
+    if (HAL_RTC_WaitForSynchro(&RtcHandle) != HAL_OK) {
+        error("rtc_synchronize error\n");
+    }
+}
+
 #if DEVICE_LOWPOWERTIMER
 
 static void RTC_IRQHandler(void)
 {
     /*  Update HAL state */
+    RtcHandle.Instance = RTC;
     HAL_RTCEx_WakeUpTimerIRQHandler(&RtcHandle);
     /* In case of registered handler, call it. */
     if (irq_handler) {
@@ -304,35 +307,52 @@
     }
 }
 
-void rtc_set_irq_handler(uint32_t handler)
-{
-    irq_handler = (void (*)(void))handler;
-}
-
 uint32_t rtc_read_subseconds(void)
 {
-    return 1000000.f * ((double)(RTC_SYNCH_PREDIV - RTC->SSR) / (RTC_SYNCH_PREDIV + 1));
+    return 1000000.f * ((double)((RTC->PRER & RTC_PRER_PREDIV_S) - RTC->SSR) / ((RTC->PRER & RTC_PRER_PREDIV_S) + 1));
 }
 
 void rtc_set_wake_up_timer(uint32_t delta)
 {
-    uint32_t wake_up_counter = delta / (2000000 / RTC_CLOCK);
+    /* Ex for Wakeup period resolution with RTCCLK=32768 Hz :
+    *    RTCCLK_DIV2: ~122us < wakeup period < ~4s
+    *    RTCCLK_DIV4: ~244us < wakeup period < ~8s
+    *    RTCCLK_DIV8: ~488us < wakeup period < ~16s
+    *    RTCCLK_DIV16: ~976us < wakeup period < ~32s
+    *    CK_SPRE_16BITS: 1s < wakeup period < (0xFFFF+ 1) x 1 s = 65536 s (18 hours)
+    *    CK_SPRE_17BITS: 18h+1s < wakeup period < (0x1FFFF+ 1) x 1 s = 131072 s (36 hours)
+    */
+    uint32_t WakeUpClock[6] = {RTC_WAKEUPCLOCK_RTCCLK_DIV2, RTC_WAKEUPCLOCK_RTCCLK_DIV4, RTC_WAKEUPCLOCK_RTCCLK_DIV8, RTC_WAKEUPCLOCK_RTCCLK_DIV16, RTC_WAKEUPCLOCK_CK_SPRE_16BITS, RTC_WAKEUPCLOCK_CK_SPRE_17BITS};
+    uint8_t ClockDiv[4] = {2, 4, 8, 16};
+    uint32_t WakeUpCounter;
+    uint8_t DivIndex = 0;
 
-    if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, wake_up_counter,
-                                    RTC_WAKEUPCLOCK_RTCCLK_DIV2) != HAL_OK) {
-        error("Set wake up timer failed\n");
+    do {
+        WakeUpCounter = delta / (ClockDiv[DivIndex] * 1000000 / RTC_CLOCK);
+        DivIndex++;
+    } while ( (WakeUpCounter > 0xFFFF) && (DivIndex < 4) );
+
+    if (WakeUpCounter > 0xFFFF) {
+        WakeUpCounter = delta / 1000000;
+        DivIndex++;
+    }
+
+    irq_handler = (void (*)(void))lp_ticker_irq_handler;
+    NVIC_SetVector(RTC_WKUP_IRQn, (uint32_t)RTC_IRQHandler);
+    NVIC_EnableIRQ(RTC_WKUP_IRQn);
+
+    RtcHandle.Instance = RTC;
+    if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, 0xFFFF & WakeUpCounter, WakeUpClock[DivIndex-1]) != HAL_OK) {
+        error("rtc_set_wake_up_timer init error (%d)\n", DivIndex);
     }
 }
 
 void rtc_deactivate_wake_up_timer(void)
 {
+    RtcHandle.Instance = RTC;
     HAL_RTCEx_DeactivateWakeUpTimer(&RtcHandle);
 }
 
-void rtc_synchronize(void)
-{
-    HAL_RTC_WaitForSynchro(&RtcHandle);
-}
 #endif /* DEVICE_LOWPOWERTIMER */
 
 #endif /* DEVICE_RTC */

--- a/targets/TARGET_STM/rtc_api_hal.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/rtc_api_hal.h	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
 *******************************************************************************
-* Copyright (c) 2016, STMicroelectronics
+* Copyright (c) 2017, STMicroelectronics
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -33,19 +33,18 @@
 
 #include <stdint.h>
 #include "rtc_api.h"
+#include "ticker_api.h"
+#include "lp_ticker_api.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-/*
- * Extend rtc_api.h
- */
 
-/** Set the given function as handler of wakeup timer event.
- *
- * @param handler    The function to set as handler
- */
-void rtc_set_irq_handler(uint32_t handler);
+#if MBED_CONF_TARGET_LSE_AVAILABLE
+#define RTC_CLOCK LSE_VALUE
+#else
+#define RTC_CLOCK LSI_VALUE
+#endif
 
 /** Read the subsecond register.
  *

--- a/targets/TARGET_STM/serial_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/serial_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,15 +27,393 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
  */
-#include "mbed_assert.h"
-#include "mbed_error.h"
-#include "serial_api.h"
-#include "serial_api_hal.h"
-#include "PeripheralPins.h"
 
 #if DEVICE_SERIAL
 
-void init_uart(serial_t *obj)
+#include "serial_api_hal.h"
+
+int stdio_uart_inited = 0; // used in platform/mbed_board.c and platform/mbed_retarget.cpp
+serial_t stdio_uart;
+
+extern UART_HandleTypeDef uart_handlers[];
+extern uint32_t serial_irq_ids[];
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    int IndexNumber = 0;
+
+    // Determine the UART to use (UART_1, UART_2, ...)
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+
+    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
+    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT(obj_s->uart != (UARTName)NC);
+
+    // Enable USART clock
+#if defined(USART1_BASE)
+    if (obj_s->uart == UART_1) {
+        __HAL_RCC_USART1_FORCE_RESET();
+        __HAL_RCC_USART1_RELEASE_RESET();
+        __HAL_RCC_USART1_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined (USART2_BASE)
+    if (obj_s->uart == UART_2) {
+        __HAL_RCC_USART2_FORCE_RESET();
+        __HAL_RCC_USART2_RELEASE_RESET();
+        __HAL_RCC_USART2_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(USART3_BASE)
+    if (obj_s->uart == UART_3) {
+        __HAL_RCC_USART3_FORCE_RESET();
+        __HAL_RCC_USART3_RELEASE_RESET();
+        __HAL_RCC_USART3_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(UART4_BASE)
+    if (obj_s->uart == UART_4) {
+        __HAL_RCC_UART4_FORCE_RESET();
+        __HAL_RCC_UART4_RELEASE_RESET();
+        __HAL_RCC_UART4_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(USART4_BASE)
+    if (obj_s->uart == UART_4) {
+        __HAL_RCC_USART4_FORCE_RESET();
+        __HAL_RCC_USART4_RELEASE_RESET();
+        __HAL_RCC_USART4_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(UART5_BASE)
+    if (obj_s->uart == UART_5) {
+        __HAL_RCC_UART5_FORCE_RESET();
+        __HAL_RCC_UART5_RELEASE_RESET();
+        __HAL_RCC_UART5_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(USART5_BASE)
+    if (obj_s->uart == UART_5) {
+        __HAL_RCC_USART5_FORCE_RESET();
+        __HAL_RCC_USART5_RELEASE_RESET();
+        __HAL_RCC_USART5_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(USART6_BASE)
+    if (obj_s->uart == UART_6) {
+        __HAL_RCC_USART6_FORCE_RESET();
+        __HAL_RCC_USART6_RELEASE_RESET();
+        __HAL_RCC_USART6_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(UART7_BASE)
+    if (obj_s->uart == UART_7) {
+        __HAL_RCC_UART7_FORCE_RESET();
+        __HAL_RCC_UART7_RELEASE_RESET();
+        __HAL_RCC_UART7_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(USART7_BASE)
+    if (obj_s->uart == UART_7) {
+        __HAL_RCC_USART7_FORCE_RESET();
+        __HAL_RCC_USART7_RELEASE_RESET();
+        __HAL_RCC_USART7_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(UART8_BASE)
+    if (obj_s->uart == UART_8) {
+        __HAL_RCC_UART8_FORCE_RESET();
+        __HAL_RCC_UART8_RELEASE_RESET();
+        __HAL_RCC_UART8_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(USART8_BASE)
+    if (obj_s->uart == UART_8) {
+        __HAL_RCC_USART8_FORCE_RESET();
+        __HAL_RCC_USART8_RELEASE_RESET();
+        __HAL_RCC_USART8_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(UART9_BASE)
+    if (obj_s->uart == UART_9) {
+        __HAL_RCC_UART9_FORCE_RESET();
+        __HAL_RCC_UART9_RELEASE_RESET();
+        __HAL_RCC_UART9_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+#if defined(UART10_BASE)
+    if (obj_s->uart == UART_10) {
+        __HAL_RCC_UART10_FORCE_RESET();
+        __HAL_RCC_UART10_RELEASE_RESET();
+        __HAL_RCC_UART10_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+
+#if defined(LPUART1_BASE)
+    if (obj_s->uart == LPUART_1) {
+        __HAL_RCC_LPUART1_FORCE_RESET();
+        __HAL_RCC_LPUART1_RELEASE_RESET();
+        __HAL_RCC_LPUART1_CLK_ENABLE();
+        obj_s->index = IndexNumber;
+    }
+    IndexNumber++;
+#endif
+
+    // Configure UART pins
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+
+    if (tx != NC) {
+        pin_mode(tx, PullUp);
+    }
+    if (rx != NC) {
+        pin_mode(rx, PullUp);
+    }
+
+    // Configure UART
+    obj_s->baudrate = 9600; // baudrate default value
+    if (obj_s->uart == STDIO_UART) {
+#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE
+        obj_s->baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json
+#endif /* MBED_CONF_PLATFORM_STDIO_BAUD_RATE */
+    }
+    else {
+#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE
+        obj_s->baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json
+#endif /* MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE */
+    }
+    obj_s->databits = UART_WORDLENGTH_8B;
+    obj_s->stopbits = UART_STOPBITS_1;
+    obj_s->parity   = UART_PARITY_NONE;
+
+#if DEVICE_SERIAL_FC
+    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
+#endif
+
+    obj_s->pin_tx = tx;
+    obj_s->pin_rx = rx;
+
+    init_uart(obj); /* init_uart will be called again in serial_baud function, so don't worry if init_uart returns HAL_ERROR */
+
+    // For stdio management
+    if (obj_s->uart == STDIO_UART) { // STDIO_UART defined in PeripheralNames.h
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+
+    // Reset UART and disable clock
+#if defined(USART1_BASE)
+    if (obj_s->uart == UART_1) {
+        __HAL_RCC_USART1_FORCE_RESET();
+        __HAL_RCC_USART1_RELEASE_RESET();
+        __HAL_RCC_USART1_CLK_DISABLE();
+    }
+#endif
+
+#if defined(USART2_BASE)
+    if (obj_s->uart == UART_2) {
+        __HAL_RCC_USART2_FORCE_RESET();
+        __HAL_RCC_USART2_RELEASE_RESET();
+        __HAL_RCC_USART2_CLK_DISABLE();
+    }
+#endif
+
+#if defined(USART3_BASE)
+    if (obj_s->uart == UART_3) {
+        __HAL_RCC_USART3_FORCE_RESET();
+        __HAL_RCC_USART3_RELEASE_RESET();
+        __HAL_RCC_USART3_CLK_DISABLE();
+    }
+#endif
+
+#if defined(UART4_BASE)
+    if (obj_s->uart == UART_4) {
+        __HAL_RCC_UART4_FORCE_RESET();
+        __HAL_RCC_UART4_RELEASE_RESET();
+        __HAL_RCC_UART4_CLK_DISABLE();
+    }
+#endif
+
+#if defined(USART4_BASE)
+    if (obj_s->uart == UART_4) {
+        __HAL_RCC_USART4_FORCE_RESET();
+        __HAL_RCC_USART4_RELEASE_RESET();
+        __HAL_RCC_USART4_CLK_DISABLE();
+    }
+#endif
+
+#if defined(UART5_BASE)
+    if (obj_s->uart == UART_5) {
+        __HAL_RCC_UART5_FORCE_RESET();
+        __HAL_RCC_UART5_RELEASE_RESET();
+        __HAL_RCC_UART5_CLK_DISABLE();
+    }
+#endif
+
+#if defined(USART5_BASE)
+    if (obj_s->uart == UART_5) {
+        __HAL_RCC_USART5_FORCE_RESET();
+        __HAL_RCC_USART5_RELEASE_RESET();
+        __HAL_RCC_USART5_CLK_DISABLE();
+    }
+#endif
+
+#if defined(USART6_BASE)
+    if (obj_s->uart == UART_6) {
+        __HAL_RCC_USART6_FORCE_RESET();
+        __HAL_RCC_USART6_RELEASE_RESET();
+        __HAL_RCC_USART6_CLK_DISABLE();
+    }
+#endif
+
+#if defined(UART7_BASE)
+    if (obj_s->uart == UART_7) {
+        __HAL_RCC_UART7_FORCE_RESET();
+        __HAL_RCC_UART7_RELEASE_RESET();
+        __HAL_RCC_UART7_CLK_DISABLE();
+    }
+#endif
+
+#if defined(USART7_BASE)
+    if (obj_s->uart == UART_7) {
+        __HAL_RCC_USART7_FORCE_RESET();
+        __HAL_RCC_USART7_RELEASE_RESET();
+        __HAL_RCC_USART7_CLK_DISABLE();
+    }
+#endif
+
+#if defined(UART8_BASE)
+    if (obj_s->uart == UART_8) {
+        __HAL_RCC_UART8_FORCE_RESET();
+        __HAL_RCC_UART8_RELEASE_RESET();
+        __HAL_RCC_UART8_CLK_DISABLE();
+    }
+#endif
+
+#if defined(USART8_BASE)
+    if (obj_s->uart == UART_8) {
+        __HAL_RCC_USART8_FORCE_RESET();
+        __HAL_RCC_USART8_RELEASE_RESET();
+        __HAL_RCC_USART8_CLK_DISABLE();
+    }
+#endif
+
+#if defined(UART9_BASE)
+    if (obj_s->uart == UART_9) {
+        __HAL_RCC_UART9_FORCE_RESET();
+        __HAL_RCC_UART9_RELEASE_RESET();
+        __HAL_RCC_UART9_CLK_DISABLE();
+    }
+#endif
+
+#if defined(UART10_BASE)
+    if (obj_s->uart == UART_10) {
+        __HAL_RCC_UART10_FORCE_RESET();
+        __HAL_RCC_UART10_RELEASE_RESET();
+        __HAL_RCC_UART10_CLK_DISABLE();
+    }
+#endif
+
+#if defined(LPUART1_BASE)
+    if (obj_s->uart == LPUART_1) {
+        __HAL_RCC_LPUART1_FORCE_RESET();
+        __HAL_RCC_LPUART1_RELEASE_RESET();
+        __HAL_RCC_LPUART1_CLK_DISABLE();
+    }
+#endif
+
+    // Configure GPIOs
+    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+    serial_irq_ids[obj_s->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+
+    obj_s->baudrate = baudrate;
+    if (init_uart(obj) != HAL_OK) {
+
+#if defined(LPUART1_BASE)
+        /* Note that LPUART clock source must be in the range [3 x baud rate, 4096 x baud rate], check Ref Manual */
+        if (obj_s->uart == LPUART_1) {
+            /* Try to change LPUART clock source */
+            RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+            if (baudrate == 9600) {
+                PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+                PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
+                HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+                if (init_uart(obj) == HAL_OK){
+                    return;
+                }
+            }
+            else {
+                PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+                PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK;
+                HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+                if (init_uart(obj) == HAL_OK){
+                    return;
+                }
+            }
+        }
+#endif /* LPUART1_BASE */
+
+        debug("Cannot initialize UART with baud rate %u\n", baudrate);
+    }
+}
+
+HAL_StatusTypeDef init_uart(serial_t *obj)
 {
     struct serial_s *obj_s = SERIAL_S(obj);
     UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
@@ -64,9 +442,7 @@
         huart->Init.Mode = UART_MODE_TX_RX;
     }
 
-    if (HAL_UART_Init(huart) != HAL_OK) {
-        error("Cannot initialize UART\n");
-    }
+    return HAL_UART_Init(huart);
 }
 
 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)

--- a/targets/TARGET_STM/serial_api_hal.h	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/serial_api_hal.h	Wed Jan 17 15:23:54 2018 +0000
@@ -32,7 +32,12 @@
 #define MBED_SERIAL_API_HAL_H
 
 #include "serial_api.h"
+#include <string.h>
+#include "mbed_assert.h"
+#include "mbed_debug.h"
+#include "mbed_error.h"
 
+#include "PeripheralPins.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -47,14 +52,12 @@
     #define SERIAL_S(obj) (obj)
 #endif
 
-extern UART_HandleTypeDef uart_handlers[];
-
 
 /** Initialize and configure the UART peripheral
  *
  * @param obj       The serial object containing the configuration
  */
-void init_uart(serial_t *obj);
+HAL_StatusTypeDef init_uart(serial_t *obj);
 
 #ifdef __cplusplus
 }

--- a/targets/TARGET_STM/sleep.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_STM/sleep.c	Wed Jan 17 15:23:54 2018 +0000
@@ -68,16 +68,16 @@
 #if TARGET_STM32L4
     int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED();
     int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR;
-    
+
     if (!pwrClockEnabled) {
         __HAL_RCC_PWR_CLK_ENABLE();
     }
     if (lowPowerModeEnabled) {
         HAL_PWREx_DisableLowPowerRunMode();
     }
-    
+
     HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
-    
+
     if (lowPowerModeEnabled) {
         HAL_PWREx_EnableLowPowerRunMode();
     }
@@ -101,8 +101,15 @@
     TimMasterHandle.Instance = TIM_MST;
     __HAL_TIM_SET_COUNTER(&TimMasterHandle, EnterTimeUS);
 
-#if DEVICE_LOWPOWERTIMER
-    rtc_synchronize();
+#if DEVICE_RTC
+    /* Wait for RTC RSF bit synchro if RTC is configured */
+#if (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7)
+    if (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) {
+#else /* (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) */
+    if (__HAL_RCC_GET_RTC_SOURCE()) {
+#endif  /* (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) */
+        rtc_synchronize();
+    }
 #endif
 }
 

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -25,7 +25,6 @@
 #include "pinmap.h"
 #include "em_cmu.h"
 #include "mbed_assert.h"
-#include "sleepmodes.h"
 
 
 void gpio_write(gpio_t *obj, int value)

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -31,10 +31,8 @@
 #include "em_gpio.h"
 #include "em_cmu.h"
 #include "sleep_api.h"
-#include "sleepmodes.h"
 
 #define NUM_GPIO_CHANNELS (16)
-#define GPIO_LEAST_ACTIVE_SLEEPMODE EM3
 
 /* Macro return index of the LSB flag which is set. */
 #if ((__CORTEX_M == 3) || (__CORTEX_M == 4))
@@ -142,21 +140,16 @@
     if(GPIO->IEN == 0) was_disabled = true;
 
     GPIO_IntConfig((GPIO_Port_TypeDef)((obj->pin >> 4) & 0xF), obj->pin &0xF, obj->risingEdge, obj->fallingEdge, obj->risingEdge || obj->fallingEdge);
-    if ((GPIO->IEN != 0) && (obj->risingEdge || obj->fallingEdge) && was_disabled) {
-        blockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE);
-    }
 }
 
 inline void gpio_irq_enable(gpio_irq_t *obj)
 {
-    if(GPIO->IEN == 0) blockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE);
     GPIO_IntEnable(1 << (obj->pin & 0xF)); // pin mask for pins to enable
 }
 
 inline void gpio_irq_disable(gpio_irq_t *obj)
 {
     GPIO_IntDisable(1 << (obj->pin & 0xF)); // pin mask for pins to disable
-    if(GPIO->IEN == 0) unblockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE);
 }
 
 /***************************************************************************//**

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -28,10 +28,10 @@
 #if DEVICE_I2C
 
 #include "mbed_assert.h"
+#include "mbed_sleep.h"
 #include "i2c_api.h"
 #include "PeripheralPins.h"
 #include "pinmap_function.h"
-#include "sleepmodes.h"
 
 #include "em_i2c.h"
 #include "em_cmu.h"
@@ -508,7 +508,7 @@
     retval = I2C_TransferInit(obj->i2c.i2c, &(obj->i2c.xfer));
 
     if(retval == i2cTransferInProgress) {
-        blockSleepMode(EM1);
+        sleep_manager_lock_deep_sleep();
     } else {
         // something happened, and the transfer did not go through
         // So, we need to clean up
@@ -541,7 +541,7 @@
             // Disable interrupt
             i2c_enable_interrupt(obj, 0, false);
 
-            unblockSleepMode(EM1);
+            sleep_manager_unlock_deep_sleep();
 
             return I2C_EVENT_TRANSFER_COMPLETE & obj->i2c.events;
         case i2cTransferNack:
@@ -549,7 +549,7 @@
             // Disable interrupt
             i2c_enable_interrupt(obj, 0, false);
 
-            unblockSleepMode(EM1);
+            sleep_manager_unlock_deep_sleep();
 
             return I2C_EVENT_ERROR_NO_SLAVE & obj->i2c.events;
         default:
@@ -557,7 +557,7 @@
             // Disable interrupt
             i2c_enable_interrupt(obj, 0, false);
 
-            unblockSleepMode(EM1);
+            sleep_manager_unlock_deep_sleep();
 
             // return error
             return I2C_EVENT_ERROR & obj->i2c.events;
@@ -578,19 +578,19 @@
  */
 void i2c_abort_asynch(i2c_t *obj)
 {
+    // Disable interrupt
+    i2c_enable_interrupt(obj, 0, false);
+
     // Do not deactivate I2C twice
     if (!i2c_active(obj)) return;
 
-    // Disable interrupt
-    i2c_enable_interrupt(obj, 0, false);
-
     // Abort
     obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
 
     // Block until free
     while(i2c_active(obj));
 
-    unblockSleepMode(EM1);
+    sleep_manager_unlock_deep_sleep();
 }
 
 #endif //DEVICE_I2C ASYNCH

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -26,11 +26,11 @@
 #if DEVICE_PWMOUT
 
 #include "mbed_assert.h"
+#include "mbed_sleep.h"
 #include "pwmout_api.h"
 #include "pinmap.h"
 #include "PeripheralPins.h"
 #include "device_peripherals.h"
-#include "sleepmodes.h"
 
 #include "em_cmu.h"
 #include "em_gpio.h"
@@ -180,7 +180,7 @@
         return;
     } else {
         pwmout_set_channel_route(pwmout_get_channel_route(obj->channel));
-        blockSleepMode(EM1);
+        sleep_manager_lock_deep_sleep();
         pwmout_enable(obj, true);
         pwmout_enable_pins(obj, true);
     }
@@ -226,7 +226,7 @@
 {
     if(pwmout_disable_channel_route(pwmout_get_channel_route(obj->channel))) {
         //Channel was previously enabled, so do housekeeping
-        unblockSleepMode(EM1);
+        sleep_manager_unlock_deep_sleep();
     } else {
         //This channel was disabled already
     }

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -28,7 +28,6 @@
 #include "rtc_api_HAL.h"
 #include "em_cmu.h"
 #include "sleep_api.h"
-#include "sleepmodes.h"
 
 #if (defined RTC_COUNT) && (RTC_COUNT > 0)
 #include "em_rtc.h"
@@ -48,8 +47,6 @@
 #ifndef RTCC_COUNT
 
 /* Using RTC API */
-
-#define RTC_LEAST_ACTIVE_SLEEPMODE  EM2
 #define RTC_NUM_BITS                (24)
 
 void RTC_IRQHandler(void)
@@ -111,7 +108,6 @@
         /* Initialize */
         RTC_Init(&init);
 
-        blockSleepMode(RTC_LEAST_ACTIVE_SLEEPMODE);
         rtc_inited = true;
     }
 }
@@ -131,7 +127,6 @@
         NVIC_DisableIRQ(RTC_IRQn);
         RTC_Reset();
         CMU_ClockEnable(cmuClock_RTC, false);
-        unblockSleepMode(RTC_LEAST_ACTIVE_SLEEPMODE);
         rtc_inited = false;
     }
 }
@@ -139,8 +134,6 @@
 #else
 
 /* Using RTCC API */
-
-#define RTCC_LEAST_ACTIVE_SLEEPMODE  EM2
 #define RTCC_NUM_BITS                (32)
 
 void RTCC_IRQHandler(void)
@@ -204,8 +197,6 @@
 
         /* Initialize */
         RTCC_Init(&init);
-
-        blockSleepMode(RTCC_LEAST_ACTIVE_SLEEPMODE);
         rtc_inited = true;
     }
 }
@@ -225,7 +216,6 @@
         NVIC_DisableIRQ(RTCC_IRQn);
         RTCC_Reset();
         CMU_ClockEnable(cmuClock_RTCC, false);
-        unblockSleepMode(RTCC_LEAST_ACTIVE_SLEEPMODE);
         rtc_inited = false;
     }
 }

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -26,6 +26,7 @@
 #if DEVICE_SERIAL
 
 #include "mbed_assert.h"
+#include "mbed_sleep.h"
 #include "serial_api.h"
 #include "serial_api_HAL.h"
 #include <string.h>
@@ -44,10 +45,6 @@
 #include "dma_api.h"
 #include "sleep_api.h"
 #include "buffer.h"
-#include "sleepmodes.h"
-
-#define SERIAL_LEAST_ACTIVE_SLEEPMODE EM1
-#define SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART EM2
 
 /** Validation of LEUART register block pointer reference
  *  for assert statements. */
@@ -2239,13 +2236,11 @@
 {
     if( obj->serial.sleep_blocked > 0 ) {
 #ifdef LEUART_USING_LFXO
-        if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){
-            unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART);
-        }else{
-            unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
+        if(!LEUART_REF_VALID(obj->serial.periph.leuart) || (LEUART_BaudrateGet(obj->serial.periph.leuart) > (LEUART_LF_REF_FREQ/2))){
+            sleep_manager_unlock_deep_sleep();
         }
 #else
-        unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
+        sleep_manager_unlock_deep_sleep();
 #endif
         obj->serial.sleep_blocked--;
     }
@@ -2255,13 +2250,13 @@
 {
     obj->serial.sleep_blocked++;
 #ifdef LEUART_USING_LFXO
-    if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){
-        blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART);
-    }else{
-        blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
+    if(!LEUART_REF_VALID(obj->serial.periph.leuart) || (LEUART_BaudrateGet(obj->serial.periph.leuart) > (LEUART_LF_REF_FREQ/2))){
+        /* LEUART configured to a baudrate triggering the use of HFCLK, so prevent HFCLK from getting turned off */
+        sleep_manager_lock_deep_sleep();
     }
 #else
-    blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE);
+    /* HFCLK unavailable in deepsleep */
+    sleep_manager_lock_deep_sleep();
 #endif
 }
 

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c	Wed Jan 17 15:23:54 2018 +0000
@@ -25,32 +25,15 @@
 #if DEVICE_SLEEP
 
 #include "sleep_api.h"
-#include "sleepmodes.h"
 #include "em_emu.h"
-#include "mbed_critical.h"
-
-uint32_t sleep_block_counter[NUM_SLEEP_MODES] = {0};
 
 /**
  * Sleep mode.
- * Enter the lowest possible sleep mode that is not blocked by ongoing activity.
+ * Stop the core clock using a WFI.
  */
 void hal_sleep(void)
 {
-    if (sleep_block_counter[0] > 0) {
-        /* Blocked everything below EM0, so just return */
-        return;
-    } else if (sleep_block_counter[1] > 0) {
-        /* Blocked everything below EM1, enter EM1 */
-        EMU_EnterEM1();
-    } else if (sleep_block_counter[2] > 0) {
-        /* Blocked everything below EM2, enter EM2 */
-        EMU_EnterEM2(true);
-    } else {
-        /* Blocked everything below EM3, enter EM3 */
-        EMU_EnterEM3(true);
-    } /* Never enter EM4, as mbed has no way of configuring EM4 wakeup */
-    return;
+    EMU_EnterEM1();
 }
 
 /**
@@ -69,35 +52,4 @@
     EMU_EnterEM2(true);
 }
 
-/** Block the microcontroller from sleeping below a certain mode
- *
- * This will block sleep() from entering an energy mode below the one given.
- * -- To be called by peripheral HAL's --
- *
- * After the peripheral is finished with the operation, it should call unblock with the same state
- *
- */
-void blockSleepMode(sleepstate_enum minimumMode)
-{
-    core_util_critical_section_enter();
-    sleep_block_counter[minimumMode]++;
-    core_util_critical_section_exit();
-}
-
-/** Unblock the microcontroller from sleeping below a certain mode
- *
- * This will unblock sleep() from entering an energy mode below the one given.
- * -- To be called by peripheral HAL's --
- *
- * This should be called after all transactions on a peripheral are done.
- */
-void unblockSleepMode(sleepstate_enum minimumMode)
-{
-    core_util_critical_section_enter();
-    if(sleep_block_counter[minimumMode] > 0) {
-        sleep_block_counter[minimumMode]--;
-    }
-    core_util_critical_section_exit();
-}
-
 #endif

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h	Thu Dec 07 14:01:42 2017 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-/***************************************************************************//**
- * @file sleepmodes.h
- *******************************************************************************
- * @section License
- * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
- *******************************************************************************
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************/
-
-#ifndef MBED_SLEEPMODES_H
-#define MBED_SLEEPMODES_H
-
-#include "em_gpio.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-* Blocks all sleepmodes below the one passed as argument
-*
-* @param minimumMode The lowest-power sleep mode which must remain active
-*/
-void blockSleepMode(sleepstate_enum minimumMode);
-
-/*
-* Unblocks a previously-blocked sleep mode
-* 
-*@param minimumMode The same sleepmode that was previously passed to blockSleepMode
-*/
-void unblockSleepMode(sleepstate_enum minimumMode);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c	Wed Jan 17 15:23:54 2018 +0000
@@ -26,6 +26,7 @@
 #if DEVICE_SPI
 
 #include "mbed_assert.h"
+#include "mbed_sleep.h"
 #include "PeripheralPins.h"
 #include "pinmap.h"
 #include "pinmap_function.h"
@@ -39,12 +40,9 @@
 #include "em_cmu.h"
 #include "em_dma.h"
 #include "sleep_api.h"
-#include "sleepmodes.h"
 
 static uint16_t fill_word = SPI_FILL_WORD;
 
-#define SPI_LEAST_ACTIVE_SLEEPMODE EM1
-
 static inline CMU_Clock_TypeDef spi_get_clock_tree(spi_t *obj)
 {
     switch ((int)obj->spi.spi) {
@@ -1188,7 +1186,7 @@
     spi_enable_event(obj, event, true);
 
     // Set the sleep mode
-    blockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
+    sleep_manager_lock_deep_sleep();
 
     /* And kick off the transfer */
     spi_master_transfer_dma(obj, tx, rx, tx_length, rx_length, (void*)handler, hint);
@@ -1244,7 +1242,7 @@
 
         /* Wait transmit to complete, before user code is indicated*/
         while(!(obj->spi.spi->STATUS & USART_STATUS_TXC));
-        unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
+        sleep_manager_unlock_deep_sleep();
         /* return to CPP land to say we're finished */
         return SPI_EVENT_COMPLETE;
     } else {
@@ -1262,7 +1260,7 @@
             /* disable interrupts */
             spi_enable_interrupt(obj, (uint32_t)NULL, false);
 
-            unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
+            sleep_manager_unlock_deep_sleep();
             /* Return the event back to userland */
             return event;
         }
@@ -1370,7 +1368,7 @@
 
         /* Wait for transmit to complete, before user code is indicated */
         while(!(obj->spi.spi->STATUS & USART_STATUS_TXC));
-        unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
+        sleep_manager_unlock_deep_sleep();
 
         /* return to CPP land to say we're finished */
         return SPI_EVENT_COMPLETE;
@@ -1391,7 +1389,7 @@
 
             /* Wait for transmit to complete, before user code is indicated */
             while(!(obj->spi.spi->STATUS & USART_STATUS_TXC));
-            unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
+            sleep_manager_unlock_deep_sleep();
 
             /* Return the event back to userland */
             return event;
@@ -1433,7 +1431,7 @@
     }
 
     // Release sleep mode block
-    unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
+    sleep_manager_unlock_deep_sleep();
 }
 
 #endif

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c	Wed Jan 17 15:23:54 2018 +0000
@@ -25,13 +25,12 @@
 #include "us_ticker_api.h"
 #include "device.h"
 #include "mbed_assert.h"
+#include "mbed_sleep.h"
 #include "em_cmu.h"
 #include "em_timer.h"
 #include "clocking.h"
 #include "sleep_api.h"
-#include "sleepmodes.h"
 
-#define TIMER_LEAST_ACTIVE_SLEEPMODE EM1
 /**
  * Timer functions for microsecond ticker.
  * mbed expects a 32-bit timer. Since the EFM32 only has 16-bit timers,
@@ -161,7 +160,7 @@
 
     if((US_TICKER_TIMER->IEN & TIMER_IEN_CC0) == 0) {
         //Timer was disabled, but is going to be enabled. Set sleep mode.
-        blockSleepMode(TIMER_LEAST_ACTIVE_SLEEPMODE);
+        sleep_manager_lock_deep_sleep();
     }
     TIMER_IntDisable(US_TICKER_TIMER, TIMER_IEN_CC0);
 
@@ -218,7 +217,7 @@
 {
     if((US_TICKER_TIMER->IEN & TIMER_IEN_CC0) != 0) {
         //Timer was enabled, but is going to get disabled. Clear sleepmode.
-        unblockSleepMode(TIMER_LEAST_ACTIVE_SLEEPMODE);
+        sleep_manager_unlock_deep_sleep();
     }
     /* Disable compare channel interrupts */
     TIMER_IntDisable(US_TICKER_TIMER, TIMER_IEN_CC0);

--- a/targets/targets.json	Thu Dec 07 14:01:42 2017 +0000
+++ b/targets/targets.json	Wed Jan 17 15:23:54 2018 +0000
@@ -622,7 +622,7 @@
     },
     "EV_COG_AD4050LZ": {
         "inherits": ["Target"],
-        "core": "Cortex-M4",
+        "core": "Cortex-M4F",
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"],
         "extra_labels": ["Analog_Devices", "ADUCM4X50", "ADUCM4050", "EV_COG_AD4050LZ", "FLASH_CMSIS_ALGO"],
@@ -706,6 +706,12 @@
         "extra_labels": ["STM"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "config": {
+            "lse_available": {
+                "help": "Define if a Low Speed External xtal (LSE) is available on the board (0 = No, 1 = Yes). If Yes, the LSE will be used to clock the RTC, LPUART, ... otherwise the Low Speed Internal clock (LSI) will be used",
+                "value": "1"
+            }
+        },
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"]
     },
     "LPC54114": {
@@ -738,7 +744,6 @@
     "FF_LPC546XX": {
         "inherits": ["LPC546XX"],
         "extra_labels_remove" : ["LPCXpresso"],
-        "features_remove": ["LWIP"],
         "supported_form_factors": [""],
         "detect_code": ["8081"]
     },
@@ -775,7 +780,8 @@
             }
         },
         "detect_code": ["0791"],
-        "macros_add": ["RTC_LSI=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "overrides": {"lse_available": 0},
+        "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "device_has_add": ["SERIAL_FC"],
         "default_lib": "small",
         "release_versions": ["2"],
@@ -795,7 +801,8 @@
             }
         },
         "detect_code": ["0785"],
-        "macros_add": ["RTC_LSI=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "overrides": {"lse_available": 0},
+        "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "device_has_add": ["CAN", "SERIAL_FC"],
         "default_lib": "small",
         "release_versions": ["2"],
@@ -815,7 +822,7 @@
         },
         "detect_code": ["0755"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F070RB"
     },
@@ -833,7 +840,7 @@
         },
         "detect_code": ["0730"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F072RB"
     },
@@ -851,7 +858,7 @@
         },
         "detect_code": ["0750"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F091RC"
     },
@@ -873,7 +880,7 @@
             }
         },
         "detect_code": ["0700"],
-        "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F103RB"
     },
@@ -924,7 +931,6 @@
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F303x8", "STM32F303K8"],
-        "macros_add": ["RTC_LSI=1"],
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
@@ -932,6 +938,7 @@
                 "macro_name": "CLOCK_SOURCE"
             }
         },
+        "overrides": {"lse_available": 0},
         "detect_code": ["0775"],
         "default_lib": "small",
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC"],
@@ -951,7 +958,7 @@
             }
         },
         "detect_code": ["0745"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F303RE"
     },
@@ -968,7 +975,7 @@
             }
         },
         "detect_code": ["0747"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F303ZE"
     },
@@ -1004,7 +1011,7 @@
         },
         "detect_code": ["0720"],
         "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
-        "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH", "LOWPOWERTIMER"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F401RE"
     },
@@ -1085,6 +1092,24 @@
         "release_versions": ["2", "5"],
         "device_name": "STM32F413ZH"
     },
+    "NUCLEO_F413ZH": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F413xx", "STM32F413ZH", "STM32F413xH"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0743"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F413ZH"
+    },
     "ELMO_F411RE": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO"],
@@ -1383,7 +1408,26 @@
         "detect_code": ["0770"],
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32L432KC"
+        "device_name": "STM32L432KC",
+        "bootloader_supported": true
+    },
+    "NUCLEO_L433RC_P": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L433xC", "STM32L433RC"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0770"],
+        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L433RC",
+        "bootloader_supported": true
     },
     "NUCLEO_L476RG": {
         "inherits": ["FAMILY_STM32"],
@@ -1479,7 +1523,7 @@
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F303", "STM32F303xC", "STM32F303VC"],
-        "macros_add": ["RTC_LSI=1"],
+        "overrides": {"lse_available": 0},
         "supported_toolchains": ["GCC_ARM"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC"],
         "device_name": "STM32F303VC"
@@ -1488,7 +1532,6 @@
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F334x8","STM32F334C8"],
-        "macros_add": ["RTC_LSI=1"],
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
@@ -1496,6 +1539,7 @@
                 "macro_name": "CLOCK_SOURCE"
             }
         },
+        "overrides": {"lse_available": 0},
         "detect_code": ["0810"],
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
         "default_lib": "small",
@@ -1507,7 +1551,8 @@
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
-        "macros_add": ["RTC_LSI=1", "USB_STM_HAL"],
+        "macros_add": ["USB_STM_HAL"],
+        "overrides": {"lse_available": 0},
         "device_has_add": ["ANALOGOUT"],
         "device_name": "STM32F407VG"
     },
@@ -1527,7 +1572,8 @@
                 "macro_name": "CLOCK_SOURCE_USB"
             }
         },
-        "macros_add": ["RTC_LSI=1", "USB_STM_HAL", "USBHOST_OTHER"],
+        "overrides": {"lse_available": 0},
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
         "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F429ZI",
@@ -1546,7 +1592,7 @@
             }
         },
         "detect_code": ["0788"],
-        "macros_add": ["USB_STM_HAL"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F469NI"
@@ -1555,7 +1601,6 @@
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M0+",
         "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053C8"],
-        "macros": ["RTC_LSI=1"],
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
@@ -1563,6 +1608,7 @@
                 "macro_name": "CLOCK_SOURCE"
             }
         },
+        "overrides": {"lse_available": 0},
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "FLASH"],
         "default_lib": "small",
         "release_versions": ["2"],
@@ -1602,6 +1648,7 @@
             }
         },
         "detect_code": ["0815"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
         "features": ["LWIP"],
         "release_versions": ["2", "5"],
@@ -1620,6 +1667,7 @@
             }
         },
         "detect_code": ["0817"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
         "features": ["LWIP"],
         "release_versions": ["2", "5"],
@@ -1701,7 +1749,8 @@
                 "macro_name": "MODEM_ON_BOARD_UART"
             }
         },
-        "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000", "RTC_LSI=1"],
+        "overrides": {"lse_available": 0},
+        "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"],
         "post_binary_hook": {
             "function": "MTSCode.combine_bins_mts_dragonfly",
             "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
@@ -1737,7 +1786,7 @@
         "core": "Cortex-M3",
         "default_toolchain": "uARM",
         "extra_labels_add": ["STM32L1", "STM32L152RC"],
-        "macros": ["RTC_LSI=1"],
+        "overrides": {"lse_available": 0},
         "detect_code": ["4100"],
         "device_has_add": ["ANALOGOUT"],
         "default_lib": "small",
@@ -1803,6 +1852,25 @@
             }
         }
     },
+    "MTB_UBLOX_ODIN_W2": {
+        "inherits": ["MODULE_UBLOX_ODIN_W2"],
+        "release_versions": ["5"],
+        "config": {
+            "usb_tx": {
+                "help": "Value PA_11",
+                "value": "PA_11"
+            },
+            "usb_rx": {
+                "help": "Value PA_13",
+                "value": "PA_13"
+            },
+            "stdio_uart": {
+                "help": "Value: UART_1",
+                "value": "UART_1",
+                "macro_name": "STDIO_UART"
+             }
+        }
+     },
     "UBLOX_C030": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO"],
@@ -1821,7 +1889,8 @@
                 "macro_name": "MODEM_ON_BOARD_UART"
             }
         },
-        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "RTC_LSI=1", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
+        "overrides": {"lse_available": 0},
         "device_has_add": ["ANALOGOUT", "SERIAL_FC", "TRNG", "FLASH"],
         "features": ["LWIP"],
         "public": false,
@@ -1842,7 +1911,7 @@
         "default_toolchain": "uARM",
         "program_cycle_s": 1.5,
         "extra_labels_add": ["STM32L1", "STM32L151RC"],
-        "macros": ["RTC_LSI=1"],
+        "overrides": {"lse_available": 0},
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
         "device_has_add": ["ANALOGOUT"],
         "default_lib": "small",
@@ -2366,7 +2435,7 @@
         "inherits": ["Target"],
         "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "features": ["LWIP"],
-        "release_versions": ["2"]
+        "release_versions": ["2", "5"]
     },
     "VK_RZ_A1H": {
         "inherits": ["Target"],
@@ -2378,7 +2447,7 @@
         "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "features": ["LWIP"],
         "default_lib": "std",
-        "release_versions": ["2"]
+        "release_versions": []
     },
     "MAXWSNENV": {
         "inherits": ["Target"],
@@ -2873,6 +2942,7 @@
         "macros_add": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
+        "device_name": "EFM32PG12B500F1024GL125",
         "public": false,
         "bootloader_supported": true
     },
@@ -2925,11 +2995,13 @@
         "macros_add": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
+        "device_name": "EFR32MG12P332F1024GL125",
         "public": false,
         "bootloader_supported": true
     },
     "TB_SENSE_12": {
         "inherits": ["EFR32MG12P332F1024GL125"],
+        "device_name": "EFR32MG12P332F1024GL125",
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"],
         "forced_reset_timeout": 5,
         "config": {
@@ -3197,7 +3269,7 @@
     "MCU_NRF52840": {
         "inherits": ["Target"],
         "core": "Cortex-M4F",
-        "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"],
         "device_has": ["STCLK_OFF_DURING_SLEEP"],
         "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"],
         "OUTPUT_EXT": "hex",
@@ -3239,7 +3311,8 @@
         "macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"],
         "device_has_add": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"],
         "release_versions": ["2", "5"],
-        "device_name": "nRF52840_xxAA"
+        "device_name": "nRF52840_xxAA",
+        "bootloader_supported": true
     },
     "BLUEPILL_F103C8": {
         "inherits": ["FAMILY_STM32"],