mbed official
NXP LPC1768 Ethernet driver for lwip and CMSIS-RTOS
Dependents: EthernetInterface EthernetInterface EthernetInterface_RSF EthernetInterface ... more
Legacy Networking Libraries
This is an mbed 2 networking library. For mbed 5, the networking libraries have been revised to better support additional network stacks and thread safety here.
This library is based on the code of the NXP LPC port of the Lightweight TCP/IP Stack
Copyright(C) 2011, NXP Semiconductor All rights reserved. Software that is described herein is for illustrative purposes only which provides customers with programming information regarding the products. This software is supplied "AS IS" without any warranties. NXP Semiconductors assumes no responsibility or liability for the use of the software, conveys no license or title under any patent, copyright, or mask work right to the product. NXP Semiconductors reserves the right to make changes in the software without notification. NXP Semiconductors also make no representation or warranty that such application will be suitable for the specified use without further testing or modification.
Revision 1:0c9d93e2f51c, committed 2012-06-22
- Comitter:
- emilmont
- Date:
- Fri Jun 22 11:17:21 2012 +0000
- Parent:
- 0:f4db29eb9e47
- Child:
- 2:5208926bd863
- Commit message:
- Adapt NXP lwip Ethernet driver to CMSIS-RTOS and LPC1768
Changed in this revision
--- a/arch/lpc17_emac.c Fri Jun 22 09:32:29 2012 +0000
+++ b/arch/lpc17_emac.c Fri Jun 22 11:17:21 2012 +0000
@@ -1,44 +1,47 @@
-/**********************************************************************
-* $Id$ lpc17_emac.c 2011-11-20
-*//**
-* @file lpc17_emac.c
-* @brief LPC17 ethernet driver for LWIP
-* @version 1.0
-* @date 20. Nov. 2011
-* @author NXP MCU SW Application Team
-*
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
+/**********************************************************************
+* $Id$ lpc17_emac.c 2011-11-20
+*//**
+* @file lpc17_emac.c
+* @brief LPC17 ethernet driver for LWIP
+* @version 1.0
+* @date 20. Nov. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
**********************************************************************/
-#include "lwip/opt.h"
-#include "lwip/sys.h"
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/pbuf.h"
-#include "lwip/stats.h"
-#include "lwip/snmp.h"
-#include "netif/etharp.h"
+#include "lwip/opt.h"
+#include "lwip/sys.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "netif/etharp.h"
#include "netif/ppp_oe.h"
-#include "lpc177x_8x_emac.h"
-#include "lpc177x_8x_clkpwr.h"
+#include "lpc17xx_emac.h"
#include "lpc17_emac.h"
#include "lpc_emac_config.h"
#include "lpc_phy.h"
-
+#include "sys_arch.h"
+
+#include "mbed_interface.h"
+#include <string.h>
+
#ifndef LPC_EMAC_RMII
#error LPC_EMAC_RMII is not defined!
#endif
@@ -50,92 +53,92 @@
#if LPC_NUM_BUFF_RXDESCS < 3
#error LPC_NUM_BUFF_RXDESCS must be at least 3
#endif
-
-/** @defgroup lwip17xx_emac_DRIVER lpc17 EMAC driver for LWIP
- * @ingroup lwip_emac
- *
- * @{
+
+/** @defgroup lwip17xx_emac_DRIVER lpc17 EMAC driver for LWIP
+ * @ingroup lwip_emac
+ *
+ * @{
*/
-
-#if NO_SYS == 0
-/** \brief Driver transmit and receive thread priorities
- *
+
+#if NO_SYS == 0
+/** \brief Driver transmit and receive thread priorities
+ *
* Thread priorities for receive thread and TX cleanup thread. Alter
* to prioritize receive or transmit bandwidth. In a heavily loaded
* system or with LEIP_DEBUG enabled, the priorities might be better
* the same. */
-#define tskRECPKT_PRIORITY (DEFAULT_THREAD_PRIO + 4)
-#define tskTXCLEAN_PRIORITY (DEFAULT_THREAD_PRIO + 5)
-
-/** \brief Debug output formatter lock define
- *
+#define RX_PRIORITY (osPriorityNormal)
+#define TX_PRIORITY (osPriorityNormal)
+
+/** \brief Debug output formatter lock define
+ *
* When using FreeRTOS and with LWIP_DEBUG enabled, enabling this
* define will allow RX debug messages to not interleave with the
- * TX messages (so they are actually readable). Not enabling this
- * define when the system is under load will cause the output to
- * be unreadable. There is a small tradeoff in performance for this
+ * TX messages (so they are actually readable). Not enabling this
+ * define when the system is under load will cause the output to
+ * be unreadable. There is a small tradeoff in performance for this
* so use it only for debug. */
//#define LOCK_RX_THREAD
-
-/** \brief Receive group interrupts
- */
-#define RXINTGROUP (EMAC_INT_RX_OVERRUN | EMAC_INT_RX_ERR | EMAC_INT_RX_DONE)
-
-/** \brief Transmit group interrupts
- */
-#define TXINTGROUP (EMAC_INT_TX_UNDERRUN | EMAC_INT_TX_ERR | EMAC_INT_TX_DONE)
-#else
-#define RXINTGROUP 0
-#define TXINTGROUP 0
-#endif
-
- /** \brief Structure of a TX/RX descriptor
- */
-typedef struct
-{
- volatile u32_t packet; /**< Pointer to buffer */
- volatile u32_t control; /**< Control word */
-} LPC_TXRX_DESC_T;
-
-/** \brief Structure of a RX status entry
- */
-typedef struct
-{
- volatile u32_t statusinfo; /**< RX status word */
- volatile u32_t statushashcrc; /**< RX hash CRC */
+
+/** \brief Receive group interrupts
+ */
+#define RXINTGROUP (EMAC_INT_RX_OVERRUN | EMAC_INT_RX_ERR | EMAC_INT_RX_DONE)
+
+/** \brief Transmit group interrupts
+ */
+#define TXINTGROUP (EMAC_INT_TX_UNDERRUN | EMAC_INT_TX_ERR | EMAC_INT_TX_DONE)
+#else
+#define RXINTGROUP 0
+#define TXINTGROUP 0
+#endif
+
+ /** \brief Structure of a TX/RX descriptor
+ */
+typedef struct
+{
+ volatile u32_t packet; /**< Pointer to buffer */
+ volatile u32_t control; /**< Control word */
+} LPC_TXRX_DESC_T;
+
+/** \brief Structure of a RX status entry
+ */
+typedef struct
+{
+ volatile u32_t statusinfo; /**< RX status word */
+ volatile u32_t statushashcrc; /**< RX hash CRC */
} LPC_TXRX_STATUS_T;
-
-/* LPC EMAC driver data structure */
-struct lpc_enetdata {
- /* prxs must be 8 byte aligned! */
- LPC_TXRX_STATUS_T prxs[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX statuses */
- struct netif *netif; /**< Reference back to LWIP parent netif */
- LPC_TXRX_DESC_T ptxd[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX descriptor list */
- LPC_TXRX_STATUS_T ptxs[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX statuses */
- LPC_TXRX_DESC_T prxd[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX descriptor list */
- struct pbuf *rxb[LPC_NUM_BUFF_RXDESCS]; /**< RX pbuf pointer list, zero-copy mode */
- u32_t rx_fill_desc_index; /**< RX descriptor next available index */
- volatile u32_t rx_free_descs; /**< Count of free RX descriptors */
- struct pbuf *txb[LPC_NUM_BUFF_TXDESCS]; /**< TX pbuf pointer list, zero-copy mode */
- u32_t lpc_last_tx_idx; /**< TX last descriptor index, zero-copy mode */
-#if NO_SYS == 0
+
+/* LPC EMAC driver data structure */
+struct lpc_enetdata {
+ /* prxs must be 8 byte aligned! */
+ LPC_TXRX_STATUS_T prxs[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX statuses */
+ struct netif *netif; /**< Reference back to LWIP parent netif */
+ LPC_TXRX_DESC_T ptxd[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX descriptor list */
+ LPC_TXRX_STATUS_T ptxs[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX statuses */
+ LPC_TXRX_DESC_T prxd[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX descriptor list */
+ struct pbuf *rxb[LPC_NUM_BUFF_RXDESCS]; /**< RX pbuf pointer list, zero-copy mode */
+ u32_t rx_fill_desc_index; /**< RX descriptor next available index */
+ volatile u32_t rx_free_descs; /**< Count of free RX descriptors */
+ struct pbuf *txb[LPC_NUM_BUFF_TXDESCS]; /**< TX pbuf pointer list, zero-copy mode */
+ u32_t lpc_last_tx_idx; /**< TX last descriptor index, zero-copy mode */
+#if NO_SYS == 0
sys_sem_t RxSem; /**< RX receive thread wakeup semaphore */
sys_sem_t TxCleanSem; /**< TX cleanup thread wakeup semaphore */
sys_mutex_t TXLockMutex; /**< TX critical section mutex */
- xSemaphoreHandle xTXDCountSem; /**< TX free buffer counting semaphore */
-#endif
-};
-
-/** \brief LPC EMAC driver work data
- */
+ sys_sem_t xTXDCountSem; /**< TX free buffer counting semaphore */
+#endif
+};
+
+/** \brief LPC EMAC driver work data
+ */
ALIGNED(8) struct lpc_enetdata lpc_enetdata;
-
+
/* Write a value via the MII link (non-blocking) */
void lpc_mii_write_noblock(u32_t PhyReg, u32_t Value)
{
/* Write value at PHY address and register */
- LPC_EMAC->MADR = (LPC_PHYDEF_PHYADDR << 8) | PhyReg;
- LPC_EMAC->MWTD = Value;
+ LPC_EMAC->MADR = (LPC_PHYDEF_PHYADDR << 8) | PhyReg;
+ LPC_EMAC->MWTD = Value;
}
/* Write a value via the MII link (blocking) */
@@ -145,16 +148,16 @@
err_t sts = ERR_OK;
/* Write value at PHY address and register */
- lpc_mii_write_noblock(PhyReg, Value);
-
+ lpc_mii_write_noblock(PhyReg, Value);
+
/* Wait for unbusy status */
while (mst > 0) {
sts = LPC_EMAC->MIND;
- if ((sts & EMAC_MIND_BUSY) == 0)
+ if ((sts & EMAC_MIND_BUSY) == 0)
mst = 0;
else {
mst--;
- msDelay(1);
+ osDelay(1);
}
}
@@ -175,7 +178,7 @@
{
u32_t data = LPC_EMAC->MRDD;
LPC_EMAC->MCMD = 0;
-
+
return data;
}
@@ -183,8 +186,8 @@
void lpc_mii_read_noblock(u32_t PhyReg)
{
/* Read value at PHY address and register */
- LPC_EMAC->MADR = (LPC_PHYDEF_PHYADDR << 8) | PhyReg;
- LPC_EMAC->MCMD = EMAC_MCMD_READ;
+ LPC_EMAC->MADR = (LPC_PHYDEF_PHYADDR << 8) | PhyReg;
+ LPC_EMAC->MCMD = EMAC_MCMD_READ;
}
/* Read a value via the MII link (blocking) */
@@ -199,17 +202,17 @@
/* Wait for unbusy status */
while (mst > 0) {
sts = LPC_EMAC->MIND & ~EMAC_MIND_MII_LINK_FAIL;
- if ((sts & EMAC_MIND_BUSY) == 0) {
+ if ((sts & EMAC_MIND_BUSY) == 0) {
mst = 0;
*data = LPC_EMAC->MRDD;
} else {
mst--;
- msDelay(1);
+ osDelay(1);
}
}
LPC_EMAC->MCMD = 0;
-
+
if (sts != 0)
sts = ERR_TIMEOUT;
@@ -218,10 +221,10 @@
/** \brief Queues a pbuf into the RX descriptor list
*
- * \param[in] lpc_enetif Pointer to the drvier data structure
- * \param[in] p Pointer to pbuf to queue
+ * \param[in] lpc_enetif Pointer to the drvier data structure
+ * \param[in] p Pointer to pbuf to queue
*/
-static void lpc_rxqueue_pbuf(struct lpc_enetdata *lpc_enetif, struct pbuf *p)
+static void lpc_rxqueue_pbuf(struct lpc_enetdata *lpc_enetif, struct pbuf *p)
{
u32_t idx;
@@ -254,8 +257,8 @@
/** \brief Attempt to allocate and requeue a new pbuf for RX
*
- * \param[in] netif Pointer to the netif structure
- * \returns 1 if a packet was allocated and requeued, otherwise 0
+ * \param[in] netif Pointer to the netif structure
+ * \returns 1 if a packet was allocated and requeued, otherwise 0
*/
s32_t lpc_rx_queue(struct netif *netif)
{
@@ -279,7 +282,7 @@
/* pbufs allocated from the RAM pool should be non-chained. */
LWIP_ASSERT("lpc_rx_queue: pbuf is not contiguous (chained)",
pbuf_clen(p) <= 1);
-
+
/* Queue packet */
lpc_rxqueue_pbuf(lpc_enetif, p);
@@ -299,8 +302,6 @@
*/
static err_t lpc_rx_setup(struct lpc_enetdata *lpc_enetif)
{
- s32_t idx;
-
/* Setup pointers to RX structures */
LPC_EMAC->RxDescriptor = (u32_t) &lpc_enetif->prxd[0];
LPC_EMAC->RxStatus = (u32_t) &lpc_enetif->prxs[0];
@@ -317,31 +318,30 @@
/** \brief Allocates a pbuf and returns the data from the incoming packet.
*
- * \param[in] netif the lwip network interface structure for this lpc_enetif
- * \return a pbuf filled with the received packet (including MAC header)
- * NULL on memory error
+ * \param[in] netif the lwip network interface structure for this lpc_enetif
+ * \return a pbuf filled with the received packet (including MAC header)
+ * NULL on memory error
*/
-static struct pbuf *lpc_low_level_input(struct netif *netif)
-{
- struct lpc_enetdata *lpc_enetif = netif->state;
- struct pbuf *p = NULL, *q;
+static struct pbuf *lpc_low_level_input(struct netif *netif)
+{
+ struct lpc_enetdata *lpc_enetif = netif->state;
+ struct pbuf *p = NULL;
u32_t idx, length;
- u8_t *src;
-
+
#ifdef LOCK_RX_THREAD
#if NO_SYS == 0
/* Get exclusive access */
sys_mutex_lock(&lpc_enetif->TXLockMutex);
#endif
#endif
-
+
/* Monitor RX overrun status. This should never happen unless
(possibly) the internal bus is behing held up by something.
Unless your system is running at a very low clock speed or
there are possibilities that the internal buses may be held
up for a long time, this can probably safely be removed. */
if (LPC_EMAC->IntStatus & EMAC_INT_RX_OVERRUN) {
- LINK_STATS_INC(link.err);
+ LINK_STATS_INC(link.err);
LINK_STATS_INC(link.drop);
/* Temporarily disable RX */
@@ -379,9 +379,9 @@
idx = LPC_EMAC->RxConsumeIndex;
if (LPC_EMAC->RxProduceIndex != idx) {
/* Handle errors */
- if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
+ if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
EMAC_RINFO_SYM_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_LEN_ERR)) {
-#if LINK_STATS
+#if LINK_STATS
if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
EMAC_RINFO_SYM_ERR | EMAC_RINFO_ALIGN_ERR))
LINK_STATS_INC(link.chkerr);
@@ -399,7 +399,7 @@
lpc_rxqueue_pbuf(lpc_enetif, p);
LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
- ("lpc_low_level_input: Packet dropped with errors (0x%x)\n",
+ ("lpc_low_level_input: Packet dropped with errors (0x%x)\n",
lpc_enetif->prxs[idx].statusinfo));
} else {
/* A packet is waiting, get length */
@@ -432,53 +432,53 @@
#endif
#endif
- return p;
+ return p;
}
/** \brief Attempt to read a packet from the EMAC interface.
*
- * \param[in] netif the lwip network interface structure for this lpc_enetif
+ * \param[in] netif the lwip network interface structure for this lpc_enetif
*/
-void lpc_enetif_input(struct netif *netif)
-{
- struct eth_hdr *ethhdr;
+void lpc_enetif_input(struct netif *netif)
+{
+ struct eth_hdr *ethhdr;
struct pbuf *p;
-
- /* move received packet into a new pbuf */
+
+ /* move received packet into a new pbuf */
p = lpc_low_level_input(netif);
if (p == NULL)
return;
-
- /* points to packet payload, which starts with an Ethernet header */
+
+ /* points to packet payload, which starts with an Ethernet header */
ethhdr = p->payload;
-
- switch (htons(ethhdr->type)) {
- case ETHTYPE_IP:
- case ETHTYPE_ARP:
-#if PPPOE_SUPPORT
- case ETHTYPE_PPPOEDISC:
- case ETHTYPE_PPPOE:
-#endif /* PPPOE_SUPPORT */
- /* full packet send to tcpip_thread to process */
- if (netif->input(p, netif) != ERR_OK) {
- LWIP_DEBUGF(NETIF_DEBUG, ("lpc_enetif_input: IP input error\n"));
+
+ switch (htons(ethhdr->type)) {
+ case ETHTYPE_IP:
+ case ETHTYPE_ARP:
+#if PPPOE_SUPPORT
+ case ETHTYPE_PPPOEDISC:
+ case ETHTYPE_PPPOE:
+#endif /* PPPOE_SUPPORT */
+ /* full packet send to tcpip_thread to process */
+ if (netif->input(p, netif) != ERR_OK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("lpc_enetif_input: IP input error\n"));
/* Free buffer */
pbuf_free(p);
- }
- break;
-
- default:
+ }
+ break;
+
+ default:
/* Return buffer */
- pbuf_free(p);
- break;
- }
+ pbuf_free(p);
+ break;
+ }
}
/** \brief Determine if the passed address is usable for the ethernet
* DMA controller.
*
- * \param[in] addr Address of packet to check for DMA safe operation
- * \return 1 if the packet address is not safe, otherwise 0
+ * \param[in] addr Address of packet to check for DMA safe operation
+ * \return 1 if the packet address is not safe, otherwise 0
*/
static s32_t lpc_packet_addr_notsafe(void *addr) {
/* Check for legal address ranges */
@@ -518,7 +518,7 @@
/** \brief Free TX buffers that are complete
*
* \param[in] lpc_enetif Pointer to driver data structure
- * \param[in] cidx EMAC current descriptor comsumer index
+ * \param[in] cidx EMAC current descriptor comsumer index
*/
static void lpc_tx_reclaim_st(struct lpc_enetdata *lpc_enetif, u32_t cidx)
{
@@ -538,7 +538,7 @@
}
#if NO_SYS == 0
- xSemaphoreGive(lpc_enetif->xTXDCountSem);
+ osSemaphoreRelease(lpc_enetif->xTXDCountSem.id);
#endif
lpc_enetif->lpc_last_tx_idx++;
if (lpc_enetif->lpc_last_tx_idx >= LPC_NUM_BUFF_TXDESCS)
@@ -553,7 +553,7 @@
/** \brief User call for freeingTX buffers that are complete
*
- * \param[in] netif the lwip network interface structure for this lpc_enetif
+ * \param[in] netif the lwip network interface structure for this lpc_enetif
*/
void lpc_tx_reclaim(struct netif *netif)
{
@@ -564,14 +564,14 @@
/** \brief Polls if an available TX descriptor is ready. Can be used to
* determine if the low level transmit function will block.
*
- * \param[in] netif the lwip network interface structure for this lpc_enetif
- * \return 0 if no descriptors are read, or >0
+ * \param[in] netif the lwip network interface structure for this lpc_enetif
+ * \return 0 if no descriptors are read, or >0
*/
s32_t lpc_tx_ready(struct netif *netif)
{
s32_t fb;
u32_t idx, cidx;
-
+
cidx = LPC_EMAC->TxConsumeIndex;
idx = LPC_EMAC->TxProduceIndex;
@@ -591,17 +591,16 @@
* interrupt context, as it may block until TX descriptors
* become available.
*
- * \param[in] netif the lwip network interface structure for this lpc_enetif
- * \param[in] p the MAC packet to send (e.g. IP packet including MAC addresses and type)
- * \return ERR_OK if the packet could be sent or an err_t value if the packet couldn't be sent
+ * \param[in] netif the lwip network interface structure for this lpc_enetif
+ * \param[in] p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * \return ERR_OK if the packet could be sent or an err_t value if the packet couldn't be sent
*/
-static err_t lpc_low_level_output(struct netif *netif, struct pbuf *p)
+static err_t lpc_low_level_output(struct netif *netif, struct pbuf *p)
{
struct lpc_enetdata *lpc_enetif = netif->state;
struct pbuf *q;
u8_t *dst;
- u32_t idx, sz = 0;
- err_t err = ERR_OK;
+ u32_t idx;
struct pbuf *np;
u32_t dn, notdmasafe = 0;
@@ -629,10 +628,10 @@
/* This buffer better be contiguous! */
LWIP_ASSERT("lpc_low_level_output: New transmit pbuf is chained",
(pbuf_clen(np) == 1));
-
+
/* Copy to DMA safe pbuf */
dst = (u8_t *) np->payload;
- for(q = p; q != NULL; q = q->next) {
+ for(q = p; q != NULL; q = q->next) {
/* Copy the buffer to the descriptor's buffer */
MEMCPY(dst, (u8_t *) q->payload, q->len);
dst += q->len;
@@ -651,16 +650,16 @@
#else
if (notdmasafe)
LWIP_ASSERT("lpc_low_level_output: Not a DMA safe pbuf",
- (notdmasafe == 0));
+ (notdmasafe == 0));
#endif
/* Wait until enough descriptors are available for the transfer. */
/* THIS WILL BLOCK UNTIL THERE ARE ENOUGH DESCRIPTORS AVAILABLE */
while (dn > lpc_tx_ready(netif))
#if NO_SYS == 0
- xSemaphoreTake(lpc_enetif->xTXDCountSem, 0);
+ osSemaphoreWait(lpc_enetif->xTXDCountSem.id, osWaitForever);
#else
- msDelay(1);
+ osDelay(1);
#endif
/* Get free TX buffer index */
@@ -715,8 +714,8 @@
/* Restore access */
sys_mutex_unlock(&lpc_enetif->TXLockMutex);
#endif
-
- return ERR_OK;
+
+ return ERR_OK;
}
/** \brief LPC EMAC interrupt handler.
@@ -730,7 +729,6 @@
/* Interrupts are not used without an RTOS */
NVIC_DisableIRQ(ENET_IRQn);
#else
- signed portBASE_TYPE xRecTaskWoken = pdFALSE, XTXTaskWoken = pdFALSE;
uint32_t ints;
/* Interrupts are of 2 groups - transmit or receive. Based on the
@@ -740,24 +738,17 @@
ints = LPC_EMAC->IntStatus;
if (ints & RXINTGROUP) {
- /* RX group interrupt(s) */
- /* Give semaphore to wakeup RX receive task. Note the FreeRTOS
- method is used instead of the LWIP arch method. */
- xSemaphoreGiveFromISR(lpc_enetdata.RxSem, &xRecTaskWoken);
+ /* RX group interrupt(s): Give semaphore to wakeup RX receive task.*/
+ sys_sem_signal(&lpc_enetdata.RxSem);
}
if (ints & TXINTGROUP) {
- /* TX group interrupt(s) */
- /* Give semaphore to wakeup TX cleanup task. Note the FreeRTOS
- method is used instead of the LWIP arch method. */
- xSemaphoreGiveFromISR(lpc_enetdata.TxCleanSem, &XTXTaskWoken);
+ /* TX group interrupt(s): Give semaphore to wakeup TX cleanup task. */
+ sys_sem_signal(&lpc_enetdata.TxCleanSem);
}
/* Clear pending interrupts */
LPC_EMAC->IntClear = ints;
-
- /* Context switch needed? */
- portEND_SWITCHING_ISR( xRecTaskWoken || XTXTaskWoken );
#endif
}
@@ -766,11 +757,10 @@
*
* This task is called when a packet is received. It will
* pass the packet to the LWIP core.
- *
- * \param[in] pvParameters Not used yet
+ *
+ * \param[in] pvParameters Not used yet
*/
-static portTASK_FUNCTION( vPacketReceiveTask, pvParameters )
-{
+static void packet_rx(void* pvParameters) {
struct lpc_enetdata *lpc_enetif = pvParameters;
while (1) {
@@ -788,11 +778,10 @@
* This task is called when a transmit interrupt occurs and
* reclaims the pbuf and descriptor used for the packet once
* the packet has been transferred.
- *
- * \param[in] pvParameters Not used yet
+ *
+ * \param[in] pvParameters Not used yet
*/
-static portTASK_FUNCTION( vTransmitCleanupTask, pvParameters )
-{
+static void packet_tx(void* pvParameters) {
struct lpc_enetdata *lpc_enetif = pvParameters;
s32_t idx;
@@ -804,7 +793,7 @@
something is holding the bus or the clocks are going too slow. It
can probably be safely removed. */
if (LPC_EMAC->IntStatus & EMAC_INT_TX_UNDERRUN) {
- LINK_STATS_INC(link.err);
+ LINK_STATS_INC(link.err);
LINK_STATS_INC(link.drop);
#if NO_SYS == 0
@@ -841,13 +830,16 @@
*
* \param[in] netif Pointer to LWIP netif structure
*/
-static err_t low_level_init(struct netif *netif)
-{
+static err_t low_level_init(struct netif *netif)
+{
struct lpc_enetdata *lpc_enetif = netif->state;
- err_t err = ERR_OK;
-
+ err_t err = ERR_OK;
+
/* Enable MII clocking */
- CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCENET, ENABLE);
+ LPC_SC->PCONP |= CLKPWR_PCONP_PCENET;
+
+ LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */
+ LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
/* Reset all MAC logic */
LPC_EMAC->MAC1 = EMAC_MAC1_RES_TX | EMAC_MAC1_RES_MCS_TX |
@@ -855,7 +847,7 @@
EMAC_MAC1_SOFT_RES;
LPC_EMAC->Command = EMAC_CR_REG_RES | EMAC_CR_TX_RES | EMAC_CR_RX_RES |
EMAC_CR_PASS_RUNT_FRM;
- msDelay(10);
+ osDelay(10);
/* Initial MAC initialization */
LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL;
@@ -915,41 +907,41 @@
return err;
}
-
-/* This function provides a method for the PHY to setup the EMAC
- for the PHY negotiated duplex mode */
-void lpc_emac_set_duplex(int full_duplex)
-{
- if (full_duplex) {
- LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
- LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
- LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
- } else {
- LPC_EMAC->MAC2 &= ~EMAC_MAC2_FULL_DUP;
- LPC_EMAC->Command &= ~EMAC_CR_FULL_DUP;
- LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
- }
-}
-
-/* This function provides a method for the PHY to setup the EMAC
- for the PHY negotiated bit rate */
-void lpc_emac_set_speed(int mbs_100)
-{
- if (mbs_100)
- LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
- else
- LPC_EMAC->SUPP = 0;
+
+/* This function provides a method for the PHY to setup the EMAC
+ for the PHY negotiated duplex mode */
+void lpc_emac_set_duplex(int full_duplex)
+{
+ if (full_duplex) {
+ LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
+ LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
+ LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
+ } else {
+ LPC_EMAC->MAC2 &= ~EMAC_MAC2_FULL_DUP;
+ LPC_EMAC->Command &= ~EMAC_CR_FULL_DUP;
+ LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
+ }
}
-
-/**
+
+/* This function provides a method for the PHY to setup the EMAC
+ for the PHY negotiated bit rate */
+void lpc_emac_set_speed(int mbs_100)
+{
+ if (mbs_100)
+ LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
+ else
+ LPC_EMAC->SUPP = 0;
+}
+
+/**
* This function is the ethernet packet send function. It calls
- * etharp_output after checking link status.
- *
- * \param[in] netif the lwip network interface structure for this lpc_enetif
- * \param[in] q Pointer to pbug to send
- * \param[in] ipaddr IP address
+ * etharp_output after checking link status.
+ *
+ * \param[in] netif the lwip network interface structure for this lpc_enetif
+ * \param[in] q Pointer to pbug to send
+ * \param[in] ipaddr IP address
* \return ERR_OK or error code
- */
+ */
err_t lpc_etharp_output(struct netif *netif, struct pbuf *q,
ip_addr_t *ipaddr)
{
@@ -958,83 +950,92 @@
return etharp_output(netif, q, ipaddr);
return ERR_CONN;
-}
-
-/**
- * Should be called at the beginning of the program to set up the
- * network interface.
- *
- * This function should be passed as a parameter to netif_add().
- *
- * @param[in] netif the lwip network interface structure for this lpc_enetif
- * @return ERR_OK if the loopif is initialized
- * ERR_MEM if private data couldn't be allocated
- * any other err_t on error
- */
-err_t lpc_enetif_init(struct netif *netif)
-{
- err_t err;
-
- LWIP_ASSERT("netif != NULL", (netif != NULL));
-
+}
+
+#if NO_SYS == 0
+/* periodic PHY status update */
+void phy_update(void const *nif) {
+ lpc_phy_sts_sm((struct netif*)nif);
+}
+osTimerDef(phy_update, phy_update);
+#endif
+
+/**
+ * Should be called at the beginning of the program to set up the
+ * network interface.
+ *
+ * This function should be passed as a parameter to netif_add().
+ *
+ * @param[in] netif the lwip network interface structure for this lpc_enetif
+ * @return ERR_OK if the loopif is initialized
+ * ERR_MEM if private data couldn't be allocated
+ * any other err_t on error
+ */
+err_t lpc_enetif_init(struct netif *netif)
+{
+ err_t err;
+
+ LWIP_ASSERT("netif != NULL", (netif != NULL));
+
lpc_enetdata.netif = netif;
/* set MAC hardware address */
- board_get_macaddr(netif->hwaddr);
- netif->hwaddr_len = ETHARP_HWADDR_LEN;
-
- /* maximum transfer unit */
- netif->mtu = 1500;
-
- /* device capabilities */
- netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_UP |
- NETIF_FLAG_ETHERNET;
-
+ mbed_mac_address((char *)netif->hwaddr);
+ netif->hwaddr_len = ETHARP_HWADDR_LEN;
+
+ /* maximum transfer unit */
+ netif->mtu = 1500;
+
+ /* device capabilities */
+ netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET;
+
/* Initialize the hardware */
netif->state = &lpc_enetdata;
- err = low_level_init(netif);
+ err = low_level_init(netif);
if (err != ERR_OK)
return err;
-#if LWIP_NETIF_HOSTNAME
- /* Initialize interface hostname */
- netif->hostname = "lwiplpc";
+#if LWIP_NETIF_HOSTNAME
+ /* Initialize interface hostname */
+ netif->hostname = "lwiplpc";
#endif /* LWIP_NETIF_HOSTNAME */
- netif->name[0] = 'e';
+ netif->name[0] = 'e';
netif->name[1] = 'n';
- netif->output = lpc_etharp_output;
+ netif->output = lpc_etharp_output;
netif->linkoutput = lpc_low_level_output;
- /* For FreeRTOS, start tasks */
+ /* CMSIS-RTOS, start tasks */
#if NO_SYS == 0
- lpc_enetdata.xTXDCountSem = xSemaphoreCreateCounting(LPC_NUM_BUFF_TXDESCS,
- LPC_NUM_BUFF_TXDESCS);
- LWIP_ASSERT("xTXDCountSem creation error",
- (lpc_enetdata.xTXDCountSem != NULL));
-
- err = sys_mutex_new(&lpc_enetdata.TXLockMutex);
+ #ifdef CMSIS_OS_RTX
+ memset(lpc_enetdata.xTXDCountSem.data, 0, sizeof(lpc_enetdata.xTXDCountSem.data));
+ lpc_enetdata.xTXDCountSem.def.semaphore = lpc_enetdata.xTXDCountSem.data;
+ #endif
+ lpc_enetdata.xTXDCountSem.id = osSemaphoreCreate(&lpc_enetdata.xTXDCountSem.def, LPC_NUM_BUFF_TXDESCS);
+ LWIP_ASSERT("xTXDCountSem creation error", (lpc_enetdata.xTXDCountSem.id != NULL));
+
+ err = sys_mutex_new(&lpc_enetdata.TXLockMutex);
LWIP_ASSERT("TXLockMutex creation error", (err == ERR_OK));
-
+
/* Packet receive task */
err = sys_sem_new(&lpc_enetdata.RxSem, 0);
- LWIP_ASSERT("RxSem creation error", (err == ERR_OK));
- sys_thread_new("receive_thread", vPacketReceiveTask, netif->state,
- DEFAULT_THREAD_STACKSIZE, tskRECPKT_PRIORITY);
-
+ LWIP_ASSERT("RxSem creation error", (err == ERR_OK));
+ sys_thread_new("receive_thread", packet_rx, netif->state, DEFAULT_THREAD_STACKSIZE, RX_PRIORITY);
+
/* Transmit cleanup task */
- err = sys_sem_new(&lpc_enetdata.TxCleanSem, 0);
- LWIP_ASSERT("TxCleanSem creation error", (err == ERR_OK));
- sys_thread_new("txclean_thread", vTransmitCleanupTask, netif->state,
- DEFAULT_THREAD_STACKSIZE, tskTXCLEAN_PRIORITY);
+ sys_thread_new("txclean_thread", packet_tx, netif->state, DEFAULT_THREAD_STACKSIZE, TX_PRIORITY);
+
+ /* periodic PHY status update */
+ osTimerId phy_timer = osTimerCreate(osTimer(phy_update), osTimerPeriodic, (void *)netif);
+ osTimerStart(phy_timer, 250);
#endif
-
- return ERR_OK;
+
+ return ERR_OK;
}
-/**
- * @}
+/**
+ * @}
*/
-/* --------------------------------- End Of File ------------------------------ */
+/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/lpc17xx_emac.h Fri Jun 22 11:17:21 2012 +0000
@@ -0,0 +1,661 @@
+/**********************************************************************
+* $Id$ lpc17xx_emac.h 2010-05-21
+*//**
+* @file lpc17xx_emac.h
+* @brief Contains all macro definitions and function prototypes
+* support for Ethernet MAC firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup EMAC EMAC (Ethernet Media Access Controller)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_EMAC_H_
+#define LPC17XX_EMAC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define MCB_LPC_1768
+//#define IAR_LPC_1768
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup EMAC_Public_Macros EMAC Public Macros
+ * @{
+ */
+
+
+/* EMAC PHY status type definitions */
+#define EMAC_PHY_STAT_LINK (0) /**< Link Status */
+#define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
+#define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
+
+/* EMAC PHY device Speed definitions */
+#define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
+#define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
+#define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
+#define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
+#define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
+
+/**
+ * @}
+ */
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup EMAC_Private_Macros EMAC Private Macros
+ * @{
+ */
+
+
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
+#define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
+#define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
+#define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
+#define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for MAC Configuration Register 1
+ **********************************************************************/
+#define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
+#define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
+#define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
+#define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
+#define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
+#define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
+#define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
+#define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
+#define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
+#define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
+#define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
+
+/*********************************************************************//**
+ * Macro defines for MAC Configuration Register 2
+ **********************************************************************/
+#define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
+#define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
+#define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
+#define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
+#define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
+#define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
+#define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
+#define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
+#define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
+#define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
+#define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
+#define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
+#define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
+
+/*********************************************************************//**
+ * Macro defines for Back-to-Back Inter-Packet-Gap Register
+ **********************************************************************/
+/** Programmable field representing the nibble time offset of the minimum possible period
+ * between the end of any transmitted packet to the beginning of the next */
+#define EMAC_IPGT_BBIPG(n) (n&0x7F)
+/** Recommended value for Full Duplex of Programmable field representing the nibble time
+ * offset of the minimum possible period between the end of any transmitted packet to the
+ * beginning of the next */
+#define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
+/** Recommended value for Half Duplex of Programmable field representing the nibble time
+ * offset of the minimum possible period between the end of any transmitted packet to the
+ * beginning of the next */
+#define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
+
+/*********************************************************************//**
+ * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
+ **********************************************************************/
+/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
+#define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
+/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
+#define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
+/** Programmable field representing the optional carrierSense window referenced in
+ * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
+#define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
+/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
+#define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
+
+/*********************************************************************//**
+ * Macro defines for Collision Window/Retry Register
+ **********************************************************************/
+/** Programmable field specifying the number of retransmission attempts following a collision before
+ * aborting the packet due to excessive collisions */
+#define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
+/** Programmable field representing the slot time or collision window during which collisions occur
+ * in properly configured networks */
+#define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
+/** Default value for Collision Window / Retry register */
+#define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
+
+/*********************************************************************//**
+ * Macro defines for Maximum Frame Register
+ **********************************************************************/
+/** Represents a maximum receive frame of 1536 octets */
+#define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
+
+/*********************************************************************//**
+ * Macro defines for PHY Support Register
+ **********************************************************************/
+#define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
+#define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
+
+/*********************************************************************//**
+ * Macro defines for Test Register
+ **********************************************************************/
+#define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
+#define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
+#define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Configuration Register
+ **********************************************************************/
+#define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
+#define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
+#define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
+#define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
+#define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Command Register
+ **********************************************************************/
+#define EMAC_MCMD_READ 0x00000001 /**< MII Read */
+#define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
+
+#define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
+#define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Address Register
+ **********************************************************************/
+#define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
+#define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Write Data Register
+ **********************************************************************/
+#define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Read Data Register
+ **********************************************************************/
+#define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Indicators Register
+ **********************************************************************/
+#define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
+#define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
+#define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
+#define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
+
+/* Station Address 0 Register */
+/* Station Address 1 Register */
+/* Station Address 2 Register */
+
+
+/* Control register definitions --------------------------------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Command Register
+ **********************************************************************/
+#define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
+#define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
+#define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
+#define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
+#define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
+#define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
+#define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
+#define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
+#define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
+#define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
+
+/*********************************************************************//**
+ * Macro defines for Status Register
+ **********************************************************************/
+#define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
+#define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
+
+/*********************************************************************//**
+ * Macro defines for Transmit Status Vector 0 Register
+ **********************************************************************/
+#define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
+#define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
+#define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
+#define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
+#define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
+#define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
+#define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
+#define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
+#define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
+#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
+#define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
+#define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
+#define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
+#define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
+#define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
+#define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
+#define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
+
+/*********************************************************************//**
+ * Macro defines for Transmit Status Vector 1 Register
+ **********************************************************************/
+#define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
+#define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
+
+/*********************************************************************//**
+ * Macro defines for Receive Status Vector Register
+ **********************************************************************/
+#define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
+#define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
+#define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
+#define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
+#define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
+#define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
+#define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
+#define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
+#define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
+#define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
+#define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
+#define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
+#define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
+#define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
+#define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
+#define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
+
+/*********************************************************************//**
+ * Macro defines for Flow Control Counter Register
+ **********************************************************************/
+#define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
+#define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
+
+/*********************************************************************//**
+ * Macro defines for Flow Control Status Register
+ **********************************************************************/
+#define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
+
+
+/* Receive filter register definitions -------------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Receive Filter Control Register
+ **********************************************************************/
+#define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
+#define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
+#define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
+#define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
+#define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
+#define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
+#define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
+#define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
+
+/*********************************************************************//**
+ * Macro defines for Receive Filter WoL Status/Clear Registers
+ **********************************************************************/
+#define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
+#define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
+#define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
+#define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
+#define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
+#define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
+#define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
+#define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
+#define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
+
+
+/* Module control register definitions ---------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Interrupt Status/Enable/Clear/Set Registers
+ **********************************************************************/
+#define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
+#define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
+#define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
+#define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
+#define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
+#define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
+#define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
+#define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
+#define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
+#define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
+
+/*********************************************************************//**
+ * Macro defines for Power Down Register
+ **********************************************************************/
+#define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
+
+/* Descriptor and status formats ---------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for RX Descriptor Control Word
+ **********************************************************************/
+#define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
+#define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
+
+/*********************************************************************//**
+ * Macro defines for RX Status Hash CRC Word
+ **********************************************************************/
+#define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
+#define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
+
+/*********************************************************************//**
+ * Macro defines for RX Status Information Word
+ **********************************************************************/
+#define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
+#define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
+#define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
+#define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
+#define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
+#define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
+#define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
+#define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
+#define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
+#define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
+#define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
+#define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
+#define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
+#define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
+#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
+#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
+EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
+
+/*********************************************************************//**
+ * Macro defines for TX Descriptor Control Word
+ **********************************************************************/
+#define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
+#define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
+#define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
+#define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
+#define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
+#define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
+#define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
+
+/*********************************************************************//**
+ * Macro defines for TX Status Information Word
+ **********************************************************************/
+#define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
+#define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
+#define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
+#define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
+#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
+#define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
+#define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
+#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
+
+#ifdef MCB_LPC_1768
+/* DP83848C PHY definition ------------------------------------------------------------ */
+
+/** PHY device reset time out definition */
+#define EMAC_PHY_RESP_TOUT 0x100000UL
+
+/* ENET Device Revision ID */
+#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
+
+/*********************************************************************//**
+ * Macro defines for DP83848C PHY Registers
+ **********************************************************************/
+#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
+#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
+#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
+#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
+#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
+#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
+#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
+#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
+#define EMAC_PHY_REG_LPNPA 0x08
+
+/*********************************************************************//**
+ * Macro defines for PHY Extended Registers
+ **********************************************************************/
+#define EMAC_PHY_REG_STS 0x10 /**< Status Register */
+#define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
+#define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
+#define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
+#define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
+#define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
+#define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
+#define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
+#define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
+#define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
+#define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
+#define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Control Register
+ **********************************************************************/
+#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
+#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
+#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
+#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
+#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
+#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
+#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
+#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Status Status Register
+ **********************************************************************/
+#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
+#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
+#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
+#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
+#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
+#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
+#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
+#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
+#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
+#define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
+
+/*********************************************************************//**
+ * Macro defines for PHY Status Register
+ **********************************************************************/
+#define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
+#define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
+#define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
+#define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
+#define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
+#define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
+#define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
+
+#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
+#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
+#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
+#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
+#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
+
+#define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
+#define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
+
+#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
+#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
+#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
+
+#elif defined(IAR_LPC_1768)
+/* KSZ8721BL PHY definition ------------------------------------------------------------ */
+/** PHY device reset time out definition */
+#define EMAC_PHY_RESP_TOUT 0x100000UL
+
+/* ENET Device Revision ID */
+#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
+
+/*********************************************************************//**
+ * Macro defines for KSZ8721BL PHY Registers
+ **********************************************************************/
+#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
+#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
+#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
+#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
+#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
+#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
+#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
+#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
+#define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
+#define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
+#define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
+#define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Control Register
+ **********************************************************************/
+#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
+#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
+#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
+#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
+#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
+#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
+#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
+#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
+#define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
+#define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Status Register
+ **********************************************************************/
+#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
+#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
+#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
+#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
+#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
+#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
+#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
+#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
+#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
+#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
+#define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
+#define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
+
+/*********************************************************************//**
+ * Macro defines for PHY Identifier
+ **********************************************************************/
+/* PHY Identifier 1 bitmap definitions */
+#define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
+
+/* PHY Identifier 2 bitmap definitions */
+#define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
+
+/*********************************************************************//**
+ * Macro defines for Auto-Negotiation Advertisement
+ **********************************************************************/
+#define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
+#define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
+#define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
+#define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
+#define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
+#define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
+#define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
+#define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
+#define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
+
+#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
+#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
+#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
+#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
+#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
+
+#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
+#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
+
+#define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
+#define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup EMAC_Public_Types EMAC Public Types
+ * @{
+ */
+
+/* Descriptor and status formats ---------------------------------------------- */
+
+/**
+ * @brief RX Descriptor structure type definition
+ */
+typedef struct {
+ uint32_t Packet; /**< Receive Packet Descriptor */
+ uint32_t Ctrl; /**< Receive Control Descriptor */
+} RX_Desc;
+
+/**
+ * @brief RX Status structure type definition
+ */
+typedef struct {
+ uint32_t Info; /**< Receive Information Status */
+ uint32_t HashCRC; /**< Receive Hash CRC Status */
+} RX_Stat;
+
+/**
+ * @brief TX Descriptor structure type definition
+ */
+typedef struct {
+ uint32_t Packet; /**< Transmit Packet Descriptor */
+ uint32_t Ctrl; /**< Transmit Control Descriptor */
+} TX_Desc;
+
+/**
+ * @brief TX Status structure type definition
+ */
+typedef struct {
+ uint32_t Info; /**< Transmit Information Status */
+} TX_Stat;
+
+
+/**
+ * @brief TX Data Buffer structure definition
+ */
+typedef struct {
+ uint32_t ulDataLen; /**< Data length */
+ uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
+} EMAC_PACKETBUF_Type;
+
+/**
+ * @brief EMAC configuration structure definition
+ */
+typedef struct {
+ uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
+ - EMAC_MODE_AUTO
+ - EMAC_MODE_10M_FULL
+ - EMAC_MODE_10M_HALF
+ - EMAC_MODE_100M_FULL
+ - EMAC_MODE_100M_HALF
+ */
+ uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
+ of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
+ */
+} EMAC_CFG_Type;
+
+/** Ethernet block power/clock control bit*/
+#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_EMAC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
--- a/arch/lpc_emac_config.h Fri Jun 22 09:32:29 2012 +0000
+++ b/arch/lpc_emac_config.h Fri Jun 22 11:17:21 2012 +0000
@@ -1,45 +1,45 @@
-/**********************************************************************
-* $Id$ lpc_emac_config.h 2011-11-20
-*//**
-* @file lpc_emac_config.h
-* @brief PHY and EMAC configuration file
-* @version 1.0
-* @date 20 Nov. 2011
-* @author NXP MCU SW Application Team
-*
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
+/**********************************************************************
+* $Id$ lpc_emac_config.h 2011-11-20
+*//**
+* @file lpc_emac_config.h
+* @brief PHY and EMAC configuration file
+* @version 1.0
+* @date 20 Nov. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
**********************************************************************/
#ifndef __LPC_EMAC_CONFIG_H
#define __LPC_EMAC_CONFIG_H
#include "lwip/opt.h"
-
+
#ifdef __cplusplus
extern "C"
{
#endif
-
-/** @defgroup lwip_phy_config LWIP PHY configuration
- * @ingroup lwip_phy
- *
- * Configuration options for the PHY connected to the LPC EMAC.
- * @{
- */
-
+
+/** @defgroup lwip_phy_config LWIP PHY configuration
+ * @ingroup lwip_phy
+ *
+ * Configuration options for the PHY connected to the LPC EMAC.
+ * @{
+ */
+
/** \brief The PHY address connected the to MII/RMII
*/
#define LPC_PHYDEF_PHYADDR 1 /**< The PHY address on the PHY device. */
@@ -62,18 +62,18 @@
* operation if PHY_USE_AUTONEG is not enabled.
*/
#define PHY_USE_100MBS 1 /**< Sets data rate to 100Mbps. */
-
-/**
- * @}
+
+/**
+ * @}
*/
-
-/** @defgroup lwip_emac_config LWIP EMAC configuration
- * @ingroup lwip_emac
- *
- * Configuration options for the LPC EMAC.
- * @{
+
+/** @defgroup lwip_emac_config LWIP EMAC configuration
+ * @ingroup lwip_emac
+ *
+ * Configuration options for the LPC EMAC.
+ * @{
*/
-
+
/** \brief Selects RMII or MII connection type in the EMAC peripheral
*/
#define LPC_EMAC_RMII 1 /**< Use the RMII or MII driver variant .*/
@@ -87,21 +87,21 @@
* be a minimum value of 2.
*/
#define LPC_NUM_BUFF_TXDESCS 3
-
-/** \brief Set this define to 1 to enable bounce buffers for transmit pbufs
- * that cannot be sent via the zero-copy method. Some chained pbufs
- * may have a payload address that links to an area of memory that
- * cannot be used for transmit DMA operations. If this define is
- * set to 1, an extra check will be made with the pbufs. If a buffer
- * is determined to be non-usable for zero-copy, a temporary bounce
- * buffer will be created and used instead.
- */
-#define LPC_TX_PBUF_BOUNCE_EN 0
-
-/**
- * @}
+
+/** \brief Set this define to 1 to enable bounce buffers for transmit pbufs
+ * that cannot be sent via the zero-copy method. Some chained pbufs
+ * may have a payload address that links to an area of memory that
+ * cannot be used for transmit DMA operations. If this define is
+ * set to 1, an extra check will be made with the pbufs. If a buffer
+ * is determined to be non-usable for zero-copy, a temporary bounce
+ * buffer will be created and used instead.
*/
-
+#define LPC_TX_PBUF_BOUNCE_EN 1
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
--- a/arch/lpc_phy_dp83848.c Fri Jun 22 09:32:29 2012 +0000
+++ b/arch/lpc_phy_dp83848.c Fri Jun 22 11:17:21 2012 +0000
@@ -90,8 +90,8 @@
#define DP8_PHYID1_OUI 0x2000 /**< Expected PHY ID1 */
#define DP8_PHYID2_OUI 0x5c90 /**< Expected PHY ID2 */
-/** \brief PHY status structure used to indicate current status of PHY.
- */
+/** \brief PHY status structure used to indicate current status of PHY.
+ */
typedef struct {
u32_t phy_speed_100mbs:1; /**< 10/100 MBS connection speed flag. */
u32_t phy_full_duplex:1; /**< Half/full duplex connection speed flag. */
@@ -129,28 +129,28 @@
/* Full or half duplex */
if (linksts & DP8_FULLDUPLEX)
- physts.phy_full_duplex = 1;
+ physts.phy_full_duplex = 1;
else
physts.phy_full_duplex = 0;
-
- /* Configure 100MBit/10MBit mode. */
+
+ /* Configure 100MBit/10MBit mode. */
if (linksts & DP8_SPEED10MBPS)
physts.phy_speed_100mbs = 0;
- else
+ else
physts.phy_speed_100mbs = 1;
if (physts.phy_speed_100mbs != olddphysts.phy_speed_100mbs) {
changed = 1;
if (physts.phy_speed_100mbs) {
- /* 100MBit mode. */
+ /* 100MBit mode. */
lpc_emac_set_speed(1);
NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100000000);
}
else {
- /* 10MBit mode. */
+ /* 10MBit mode. */
lpc_emac_set_speed(0);
-
+
NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
}
@@ -197,7 +197,7 @@
* controlled by setting up configuration defines in lpc_phy.h.
*
* \param[in] netif NETIF structure
- * \param[in] rmii If set, configures the PHY for RMII mode
+ * \param[in] rmii If set, configures the PHY for RMII mode
* \return ERR_OK if the setup was successful, otherwise ERR_TIMEOUT
*/
err_t lpc_phy_init(struct netif *netif, int rmii)
@@ -211,19 +211,19 @@
phyustate = 0;
/* Only first read and write are checked for failure */
- /* Put the DP83848C in reset mode and wait for completion */
+ /* Put the DP83848C in reset mode and wait for completion */
if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != 0)
- return ERR_TIMEOUT;
+ return ERR_TIMEOUT;
i = 400;
while (i > 0) {
- msDelay(1); /* 1 ms */
+ osDelay(1); /* 1 ms */
if (lpc_mii_read(DP8_BMCR_REG, &tmp) != 0)
return ERR_TIMEOUT;
-
- if (!(tmp & (DP8_RESET | DP8_POWER_DOWN)))
+
+ if (!(tmp & (DP8_RESET | DP8_POWER_DOWN)))
i = -1;
else
- i--;
+ i--;
}
/* Timeout? */
if (i == 0)
@@ -280,8 +280,8 @@
return changed;
}
-/**
- * @}
+/**
+ * @}
*/
/* --------------------------------- End Of File ------------------------------ */
