Revision 437:0b72c0f86db6, committed 2014-12-15

Comitter:

mbed_official

Date:

Mon Dec 15 09:00:08 2014 +0000

Parent:

436:cef2a8a56f9e

Child:

438:5de36ba1188c

Commit message:

Synchronized with git revision f3acd0e7aa3cbba2a6b264dc2e9f596891dea133

Full URL: https://github.com/mbedmicro/mbed/commit/f3acd0e7aa3cbba2a6b264dc2e9f596891dea133/

Tools: changed device name from nRF51822_xxAA -> nRF51xxx on all Nordic boards

Changed in this revision

--- a/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c	Thu Dec 11 14:15:07 2014 +0000
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c	Mon Dec 15 09:00:08 2014 +0000
@@ -64,7 +64,7 @@
         assoc =  8;
 
     PL310->INV_WAY = (1 << assoc) - 1;
-    while(PL310->INV_WAY && ((1 << assoc) - 1)); //poll invalidate
+    while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
 
     PL310_Sync();
 }
@@ -89,7 +89,7 @@
 void PL310_Enable(void)
 {
     PL310->CONTROL = 0;
-    PL310->INTERRUPT_CLEAR = 0;
+    PL310->INTERRUPT_CLEAR = 0x000001FFuL;
     PL310->DEBUG_CONTROL = 0;
     PL310->DATA_LOCK_0_WAY = 0;
     PL310->CACHE_SYNC = 0;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TOOLCHAIN_IAR/cmain.s	Mon Dec 15 09:00:08 2014 +0000
@@ -0,0 +1,81 @@
+/**************************************************
+ *
+ * Part two of the system initialization code, contains C-level
+ * initialization, thumb-2 only variant.
+ *
+ * Copyright 2006 IAR Systems. All rights reserved.
+ *
+ * $Revision: 59783 $
+ *
+ **************************************************/
+
+
+; --------------------------------------------------
+; Module ?cmain, C-level initialization.
+;
+
+
+        SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
+        SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
+
+        SECTION .text:CODE:NOROOT(2)
+
+        PUBLIC  __cmain
+        ;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
+        PUBLIC  ?main
+        EXTWEAK __iar_data_init3
+        EXTWEAK __iar_argc_argv
+        EXTERN  __low_level_init
+        EXTERN  __call_ctors
+        EXTERN  main
+        EXTERN  exit
+        EXTERN  __iar_dynamic_initialization
+        EXTERN mbed_sdk_init
+        EXTERN SystemInit
+        
+        THUMB
+__cmain:
+?main:
+
+; Initialize segments.
+; __segment_init and __low_level_init are assumed to use the same
+; instruction set and to be reachable by BL from the ICODE segment
+; (it is safest to link them in segment ICODE).
+
+          FUNCALL __cmain, __low_level_init
+        bl      __low_level_init
+        cmp     r0,#0
+        beq     ?l1
+          FUNCALL __cmain, __iar_data_init3
+        bl      __iar_data_init3
+        MOVS    r0,#0             ;  No parameters
+        FUNCALL __cmain, mbed_sdk_init
+        BL      mbed_sdk_init
+        MOVS    r0,#0             ;  No parameters        
+          FUNCALL __cmain, __iar_dynamic_initialization
+        BL      __iar_dynamic_initialization   ; C++ dynamic initialization  
+
+?l1:
+        REQUIRE ?l3
+
+        SECTION .text:CODE:NOROOT(2)
+
+        PUBLIC  _main
+        PUBLIC _call_main
+        THUMB
+
+__iar_init$$done:                 ; Copy initialization is done
+
+?l3:
+_call_main:
+        MOVS    r0,#0             ;  No parameters  
+          FUNCALL __cmain, __iar_argc_argv
+        BL      __iar_argc_argv   ; Maybe setup command line
+
+          FUNCALL __cmain, main
+        BL      main
+_main:
+          FUNCALL __cmain, exit
+        BL      exit
+
+        END

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h	Thu Dec 11 14:15:07 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h	Mon Dec 15 09:00:08 2014 +0000
@@ -50,16 +50,20 @@
     PWM2H,
 } PWMType;
 
-#define PTM_SHIFT 8
 typedef enum {
-    PWM0_PIN = (1 << PTM_SHIFT) | PWM2E,  // LED_R (through MTU2) TIOC4A [T.B.D]
-    PWM1_PIN = (0 << PTM_SHIFT) | PWM2F,  // LED_G
-    PWM2_PIN = (0 << PTM_SHIFT) | PWM2G,  // LED_B
-    PWM3_PIN = (0 << PTM_SHIFT) | PWM2H,  // LED_USER (not explicitly supported)
-    PWM4_PIN = (0 << PTM_SHIFT) | PWM1G,  // D9    
-    PWM5_PIN = (0 << PTM_SHIFT) | PWM1H,  // D8  not explicitly supported
-    PWM6_PIN = (0 << PTM_SHIFT) | PWM1F,  // D7  not explicitly supported
-    PWM7_PIN = (0 << PTM_SHIFT) | PWM1D,  // D6
+    PWM0_PIN,
+    PWM1_PIN,
+    PWM2_PIN,
+    PWM3_PIN,
+    PWM4_PIN,
+    PWM5_PIN,
+    PWM6_PIN,
+    PWM7_PIN,
+    PWM8_PIN,
+    PWM9_PIN,
+    PWM10_PIN,
+    PWM11_PIN,
+    PWM12_PIN,
 } PWMName;
 
 typedef enum {

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c	Thu Dec 11 14:15:07 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c	Mon Dec 15 09:00:08 2014 +0000
@@ -116,42 +116,34 @@
 
 static void gpio_irq0(void) {
     handle_interrupt_in(0);
-    GIC_EndInterrupt((IRQn_Type)(nIRQn_h + 0));
 }
 
 static void gpio_irq1(void) {
     handle_interrupt_in(1);
-    GIC_EndInterrupt((IRQn_Type)(nIRQn_h + 1));
 }
 
 static void gpio_irq2(void) {
     handle_interrupt_in(2);
-    GIC_EndInterrupt((IRQn_Type)(nIRQn_h + 2));
 }
 
 static void gpio_irq3(void) {
     handle_interrupt_in(3);
-    GIC_EndInterrupt((IRQn_Type)(nIRQn_h + 3));
 }
 
 static void gpio_irq4(void) {
     handle_interrupt_in(4);
-    GIC_EndInterrupt((IRQn_Type)(nIRQn_h + 4));
 }
 
 static void gpio_irq5(void) {
     handle_interrupt_in(5);
-    GIC_EndInterrupt((IRQn_Type)(nIRQn_h + 5));
 }
 
 static void gpio_irq6(void) {
     handle_interrupt_in(6);
-    GIC_EndInterrupt((IRQn_Type)(nIRQn_h + 6));
 }
 
 static void gpio_irq7(void) {
     handle_interrupt_in(7);
-    GIC_EndInterrupt((IRQn_Type)(nIRQn_h + 7));
 }
 
 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h	Thu Dec 11 14:15:07 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h	Mon Dec 15 09:00:08 2014 +0000
@@ -58,9 +58,8 @@
 };
 
 struct pwmout_s {
-    __IO uint16_t *MR;
-    __IO uint16_t *CY;
-    uint16_t flag;
+    uint32_t ch;
+    int32_t  period;
     PWMName pwm;
 };
 

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c	Thu Dec 11 14:15:07 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c	Mon Dec 15 09:00:08 2014 +0000
@@ -17,114 +17,134 @@
 #include "pwmout_api.h"
 #include "cmsis.h"
 #include "pinmap.h"
-
+#include "RZ_A1_Init.h"
 #include "cpg_iodefine.h"
 #include "pwm_iodefine.h"
 
-#define TCR_CNT_EN       0x00000001
-#define TCR_RESET        0x00000002
-
 //  PORT ID, PWM ID, Pin function
 static const PinMap PinMap_PWM[] = {
-    {LED_RED  , 0, 4},
-    {LED_GREEN, 1, 7},
-    {LED_BLUE , 2, 4},
-    {P4_7     , 3, 4},
-    {P8_14    , 4, 6},
-    {P8_15    , 5, 6},
-    {P8_13    , 6, 6},
-    {P8_11    , 7, 6},
+    {P4_4     , PWM0_PIN , 4},
+    {P3_2     , PWM1_PIN , 7},
+    {P4_6     , PWM2_PIN , 4},
+    {P4_7     , PWM3_PIN , 4},
+    {P8_14    , PWM4_PIN , 6},
+    {P8_15    , PWM5_PIN , 6},
+    {P8_13    , PWM6_PIN , 6},
+    {P8_11    , PWM7_PIN , 6},
+    {P8_8     , PWM8_PIN , 6},
+    {P10_0    , PWM9_PIN , 3},
+    {P8_12    , PWM10_PIN, 6},
+    {P8_9     , PWM11_PIN, 6},
+    {P8_10    , PWM12_PIN, 6},
     {NC, NC, 0}
 };
 
-static __IO uint16_t PORT[] = {
-     PWM2E,
-     PWM2C,
-     PWM2G,
-     PWM2H,
-     PWM1G,
-     PWM1H,
-     PWM1F,
-     PWM1D,
-};
-static __IO uint16_t *PWM_MATCH[] = {
-    &PWMPWBFR_2E,
-    &PWMPWBFR_2C,
-    &PWMPWBFR_2G,
-    &PWMPWBFR_2G,
-    &PWMPWBFR_1G,
-    &PWMPWBFR_1G,
-    &PWMPWBFR_1E,
-    &PWMPWBFR_1C,
+static PWMType PORT[] = {
+     PWM2E,          // PWM0_PIN
+     PWM2C,          // PWM1_PIN
+     PWM2G,          // PWM2_PIN
+     PWM2H,          // PWM3_PIN
+     PWM1G,          // PWM4_PIN
+     PWM1H,          // PWM5_PIN
+     PWM1F,          // PWM6_PIN
+     PWM1D,          // PWM7_PIN
+     PWM1A,          // PWM8_PIN
+     PWM2A,          // PWM9_PIN
+     PWM1E,          // PWM10_PIN
+     PWM1B,          // PWM11_PIN
+     PWM1C,          // PWM12_PIN
 };
 
-#define TCR_PWM_EN       0x00000008
+static __IO uint16_t *PWM_MATCH[] = {
+    &PWMPWBFR_2E,    // PWM0_PIN
+    &PWMPWBFR_2C,    // PWM1_PIN
+    &PWMPWBFR_2G,    // PWM2_PIN
+    &PWMPWBFR_2G,    // PWM3_PIN
+    &PWMPWBFR_1G,    // PWM4_PIN
+    &PWMPWBFR_1G,    // PWM5_PIN
+    &PWMPWBFR_1E,    // PWM6_PIN
+    &PWMPWBFR_1C,    // PWM7_PIN
+    &PWMPWBFR_1A,    // PWM8_PIN
+    &PWMPWBFR_2A,    // PWM9_PIN
+    &PWMPWBFR_1E,    // PWM10_PIN
+    &PWMPWBFR_1A,    // PWM11_PIN
+    &PWMPWBFR_1C,    // PWM12_PIN
+};
 
-static unsigned int pwm_clock_mhz;
+static uint16_t init_period_ch1 = 0;
+static uint16_t init_period_ch2 = 0;
 
 void pwmout_init(pwmout_t* obj, PinName pin) {
     // determine the channel
     PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
     MBED_ASSERT(pwm != (PWMName)NC);
 
-    obj->pwm = pwm;
-    obj->MR = PWM_MATCH[pwm];
-    obj->flag = (PORT[pwm]&1)<<12;
-    
     // power on
     CPGSTBCR3 &= ~(1<<0);
-    
-    // clk mode settings PWM mode
-    PWMPWCR_1_BYTE_L = 0xc4;
-    PWMPWCR_2_BYTE_L = 0xc4;
-    
-    // output settings
-    PWMPWPR_1_BYTE_L = 0x00;
-    PWMPWPR_2_BYTE_L = 0x00;
 
-    // cycle reg.
-    PWMPWCYR_1 = 0x3ff;
-    PWMPWCYR_2 = 0x3ff;
-    
-    //pwm_clock_mhz = SystemCoreClock / 4000000;
-    
-    PWMPWCR_1_BYTE_L = 0xcc;
-    PWMPWCR_2_BYTE_L = 0xcc;
-    // default to 20ms: standard for servos, and fine for e.g. brightness control
-    //pwmout_period_ms(obj, 20);
-    //pwmout_write    (obj, 0);
-    
+    obj->pwm = pwm;
+    if (((uint32_t)PORT[obj->pwm] & 0x00000010) != 0) {
+        obj->ch  = 2;
+        PWMPWPR_2_BYTE_L = 0x00;
+    } else {
+        obj->ch  = 1;
+        PWMPWPR_1_BYTE_L = 0x00;
+    }
+
     // Wire pinout
     pinmap_pinout(pin, PinMap_PWM);
-    
+
+    // default to 491us: standard for servos, and fine for e.g. brightness control
+    pwmout_write(obj, 0);
+    if ((obj->ch == 2) && (init_period_ch2 == 0)) {
+        pwmout_period_us(obj, 491);
+        init_period_ch2 = 1;
+    }
+    if ((obj->ch == 1) && (init_period_ch1 == 0)) {
+        pwmout_period_us(obj, 491);
+        init_period_ch1 = 1;
+    }
 }
 
 void pwmout_free(pwmout_t* obj) {
-    // [TODO]
+    pwmout_write(obj, 0);
 }
 
 void pwmout_write(pwmout_t* obj, float value) {
+    uint32_t wk_cycle;
+    uint16_t v;
+
     if (value < 0.0f) {
-        value = 0.0;
+        value = 0.0f;
     } else if (value > 1.0f) {
-        value = 1.0;
+        value = 1.0f;
+    } else {
+        // Do Nothing
     }
-    
+
+    if (obj->ch == 2) {
+        wk_cycle = PWMPWCYR_2 & 0x03ff;
+    } else {
+        wk_cycle = PWMPWCYR_1 & 0x03ff;
+    }
+
     // set channel match to percentage
-    uint16_t v = (uint32_t)((float)0x3ff* value);
-
-    v |= (obj->flag);
-    
-    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
-    *obj->MR = v;
-    
-    // accept on next period start
-    //LPC_PWM1->LER |= 1 << obj->pwm;
+    v = (uint16_t)((float)wk_cycle * value);
+    *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12));
 }
 
 float pwmout_read(pwmout_t* obj) {
-    float v = (float)((*obj->MR&0x3ff)) / 0x3ff;
-    return (v > 1.0f) ? (1.0f) : (v);
+    uint32_t wk_cycle;
+    float value;
+
+    if (obj->ch == 2) {
+        wk_cycle = PWMPWCYR_2 & 0x03ff;
+    } else {
+        wk_cycle = PWMPWCYR_1 & 0x03ff;
+    }
+    value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle);
+
+    return (value > 1.0f) ? (1.0f) : (value);
 }
 
 void pwmout_period(pwmout_t* obj, float seconds) {
@@ -135,21 +155,75 @@
     pwmout_period_us(obj, ms * 1000);
 }
 
+static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
+    uint16_t wk_pwmpbfr;
+    float    value;
+    uint16_t v;
+
+    wk_pwmpbfr = *p_pwmpbfr;
+    value      = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle);
+    v          = (uint16_t)((float)new_cycle * value);
+    *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000));
+}
+
 // Set the PWM period, keeping the duty cycle the same.
 void pwmout_period_us(pwmout_t* obj, int us) {
-    // calculate number of ticks
-    uint16_t ticks = 0x3ff * us;
+    uint32_t pclk_base;
+    uint32_t wk_cycle;
+    uint16_t wk_last_cycle;
+    uint32_t wk_cks = 0;
+
+    if (us > 491) {
+        us = 491;
+    } else if (us < 1) {
+        us = 1;
+    } else {
+        // Do Nothing
+    }
 
-    // stop timer
-    *obj->MR = ticks;
+    if (RZ_A1_IsClockMode0() == false) {
+        pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000;
+    } else {
+        pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000;
+    }
+
+    wk_cycle = pclk_base * us;
+    while (wk_cycle >= 102350) {
+        wk_cycle >>= 1;
+        wk_cks++;
+    }
+    wk_cycle = (wk_cycle + 50) / 100;
 
-    // Scale the pulse width to preserve the duty ratio
+    if (obj->ch == 2) {
+        wk_last_cycle    = PWMPWCYR_2 & 0x03ff;
+        PWMPWCR_2_BYTE_L = 0xc0 | wk_cks;
+        PWMPWCYR_2       = (uint16_t)wk_cycle;
+
+        // Set duty again
+        set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle);
+        set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle);
+        set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle);
+        set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle);
 
-    // set the channel latch to update value at next period start
-//    LPC_PWM1->LER |= 1 << 0;
+        // Counter Start
+        PWMPWCR_2_BYTE_L |= 0x08;
+    } else {
+        wk_last_cycle    = PWMPWCYR_1 & 0x03ff;
+        PWMPWCR_1_BYTE_L = 0xc0 | wk_cks;
+        PWMPWCYR_1       = (uint16_t)wk_cycle;
 
-    // enable counter and pwm, clear reset
- //   LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN;
+        // Set duty again
+        set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle);
+        set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle);
+        set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle);
+        set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle);
+
+        // Counter Start
+        PWMPWCR_1_BYTE_L |= 0x08;
+    }
+
+    // Save for future use
+    obj->period = us;
 }
 
 void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
@@ -161,14 +235,6 @@
 }
 
 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
-    // calculate number of ticks
-    uint32_t v = pwm_clock_mhz * us;
-    
-    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
-    
-    // set the match register value
-    *obj->MR = v;
-    
-    // set the channel latch to update value at next period start
-    //LPC_PWM1->LER |= 1 << obj->pwm;
+    float value = (float)us / (float)obj->period;
+    pwmout_write(obj, value);
 }

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c	Thu Dec 11 14:15:07 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c	Mon Dec 15 09:00:08 2014 +0000
@@ -31,32 +31,55 @@
 /******************************************************************************
  * INITIALIZATION
  ******************************************************************************/
-#define UART_NUM    6
+#define UART_NUM    8
+#define IRQ_NUM     2
+
+static void uart0_tx_irq(void);
+static void uart1_tx_irq(void);
+static void uart2_tx_irq(void);
+static void uart3_tx_irq(void);
+static void uart4_tx_irq(void);
+static void uart5_tx_irq(void);
+static void uart6_tx_irq(void);
+static void uart7_tx_irq(void);
+static void uart0_rx_irq(void);
+static void uart1_rx_irq(void);
+static void uart2_rx_irq(void);
+static void uart3_rx_irq(void);
+static void uart4_rx_irq(void);
+static void uart5_rx_irq(void);
+static void uart6_rx_irq(void);
+static void uart7_rx_irq(void);
+
 
 static const PinMap PinMap_UART_TX[] = {
-    {P6_3 , P_SCIF2, 7},
-    {P2_14, P_SCIF0, 6},
-    {P5_0 , P_SCIF4, 5},
-    {P5_3 , P_SCIF3, 5},
-    {P5_6 , P_SCIF6, 5},
-    {P2_5 , P_SCIF1, 6},
-    {P8_14, P_SCIF4, 7},
-    {P8_13, P_SCIF5, 5},
-    {P7_5 , P_SCIF7, 4},
-    {NC   , NC    , 0}
+    {P6_3  , P_SCIF2, 7},
+    {P2_14 , P_SCIF0, 6},
+    {P5_0  , P_SCIF4, 5},
+    {P5_3  , P_SCIF3, 5},
+    {P5_6  , P_SCIF6, 5},
+    {P2_5  , P_SCIF1, 6},
+    {P8_14 , P_SCIF4, 7},
+    {P8_13 , P_SCIF5, 5},
+    {P7_4  , P_SCIF7, 4},
+    {P11_10, P_SCIF5, 3},
+    {P6_6  , P_SCIF5, 5},
+    {NC    , NC     , 0}
 };
 
 static const PinMap PinMap_UART_RX[] = {
-    {P6_2 , P_SCIF2, 7},
-    {P2_15, P_SCIF0, 6},
-    {P5_1 , P_SCIF4, 5},
-    {P5_4 , P_SCIF3, 5},
-    {P5_7 , P_SCIF6, 5},
-    {P2_6 , P_SCIF1, 6},
-    {P8_15, P_SCIF4, 7},
-    {P8_11, P_SCIF5, 5},
-    {P7_4 , P_SCIF7, 4},
-    {NC   , NC    , 0}
+    {P6_2  , P_SCIF2, 7},
+    {P2_15 , P_SCIF0, 6},
+    {P5_1  , P_SCIF4, 5},
+    {P5_4  , P_SCIF3, 5},
+    {P5_7  , P_SCIF6, 5},
+    {P2_6  , P_SCIF1, 6},
+    {P8_15 , P_SCIF4, 7},
+    {P8_11 , P_SCIF5, 5},
+    {P7_5  , P_SCIF7, 4},
+    {P11_11, P_SCIF5, 3},
+    {P6_7  , P_SCIF5, 5},
+    {NC    , NC     , 0}
 };
 
 /* [TODO] impliment hardware Flow Control, interrupt
@@ -85,6 +108,51 @@
 
 static struct serial_global_data_s uart_data[UART_NUM];
 
+static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
+    {SCIFRXI0_IRQn, SCIFTXI0_IRQn},
+    {SCIFRXI1_IRQn, SCIFTXI1_IRQn},
+    {SCIFRXI2_IRQn, SCIFTXI2_IRQn},
+    {SCIFRXI3_IRQn, SCIFTXI3_IRQn},
+    {SCIFRXI4_IRQn, SCIFTXI4_IRQn},
+    {SCIFRXI5_IRQn, SCIFTXI5_IRQn},
+    {SCIFRXI6_IRQn, SCIFTXI6_IRQn},
+    {SCIFRXI7_IRQn, SCIFTXI7_IRQn}
+};
+
+static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
+    {uart0_rx_irq, uart0_tx_irq},
+    {uart1_rx_irq, uart1_tx_irq},
+    {uart2_rx_irq, uart2_tx_irq},
+    {uart3_rx_irq, uart3_tx_irq},
+    {uart4_rx_irq, uart4_tx_irq},
+    {uart5_rx_irq, uart5_tx_irq},
+    {uart6_rx_irq, uart6_tx_irq},
+    {uart7_rx_irq, uart7_tx_irq}
+};
+
+static __IO uint16_t *SCSCR_MATCH[] = {
+    &SCSCR_0,
+    &SCSCR_1,
+    &SCSCR_2,
+    &SCSCR_3,
+    &SCSCR_4,
+    &SCSCR_5,
+    &SCSCR_6,
+    &SCSCR_7,
+};
+
+static __IO uint16_t *SCFSR_MATCH[] = {
+    &SCFSR_0,
+    &SCFSR_1,
+    &SCFSR_2,
+    &SCFSR_3,
+    &SCFSR_4,
+    &SCFSR_5,
+    &SCFSR_6,
+    &SCFSR_7,
+};
+
+
 void serial_init(serial_t *obj, PinName tx, PinName rx) {
     int is_stdio_uart = 0;
 
@@ -119,7 +187,8 @@
     obj->uart->SCFCR = 0x0006;
 
     /* ---- Serial status register (SCFSR) setting ---- */
-    obj->uart->SCFSR &= 0xFF6Cu;         /* ER,BRK,DR bit clear */
+    dummy = obj->uart->SCFSR;
+    obj->uart->SCFSR = (dummy & 0xFF6Cu);         /* ER,BRK,DR bit clear */
 
     /* ---- Line status register (SCLSR) setting ---- */
     /* ORER bit clear */
@@ -221,104 +290,47 @@
  ******************************************************************************/
 
 static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
-    uint16_t dummy_read;
-    /* Clear TDFE */
-    switch (index) {
-        case 0:
-            dummy_read = SCFSR_0;
-            SCFSR_0 = (dummy_read & ~0x0060);
-            break;
-        case 1:
-            dummy_read = SCFSR_1;
-            SCFSR_1 = (dummy_read & ~0x0060);
-            break;
-        case 2:
-            dummy_read = SCFSR_2;
-            SCFSR_2 = (dummy_read & ~0x0060);
-            break;
-        case 3:
-            dummy_read = SCFSR_3;
-            SCFSR_3 = (dummy_read & ~0x0060);
-            break;
-        case 4:
-            dummy_read = SCFSR_4;
-            SCFSR_4 = (dummy_read & ~0x0060);
-            break;
-        case 5:
-            dummy_read = SCFSR_5;
-            SCFSR_5 = (dummy_read & ~0x0060);
-            break;
-        case 6:
-            dummy_read = SCFSR_6;
-            SCFSR_6 = (dummy_read & ~0x0060);
-            break;
-        case 7:
-            dummy_read = SCFSR_7;
-            SCFSR_7 = (dummy_read & ~0x0060);
-            break;
-    }
+    __IO uint16_t *dmy_rd_scscr;
+    __IO uint16_t *dmy_rd_scfsr;
+    
+    dmy_rd_scscr = SCSCR_MATCH[index];
+    *dmy_rd_scscr &= 0x007B;                    // Clear TIE and Write to bit15~8,2 is always 0
+    dmy_rd_scfsr = SCFSR_MATCH[index];
+    *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020);  // Clear TDFE
+    
     irq_handler(uart_data[index].serial_irq_id, TxIrq);
-    GIC_EndInterrupt(irq_num);
 }
 
 static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
-    uint16_t dummy_read;
-    /* Clear RDF */
-    switch (index) {
-        case 0:
-            dummy_read = SCFSR_0;
-            SCFSR_0 = (dummy_read & ~0x0003);
-            break;
-        case 1:
-            dummy_read = SCFSR_1;
-            SCFSR_1 = (dummy_read & ~0x0003);
-            break;
-        case 2:
-            dummy_read = SCFSR_2;
-            SCFSR_2 = (dummy_read & ~0x0003);
-            break;
-        case 3:
-            dummy_read = SCFSR_3;
-            SCFSR_3 = (dummy_read & ~0x0003);
-            break;
-        case 4:
-            dummy_read = SCFSR_4;
-            SCFSR_4 = (dummy_read & ~0x0003);
-            break;
-        case 5:
-            dummy_read = SCFSR_5;
-            SCFSR_5 = (dummy_read & ~0x0003);
-            break;
-        case 6:
-            dummy_read = SCFSR_6;
-            SCFSR_6 = (dummy_read & ~0x0003);
-            break;
-        case 7:
-            dummy_read = SCFSR_7;
-            SCFSR_7 = (dummy_read & ~0x0003);
-            break;
-    }
+    __IO uint16_t *dmy_rd_scscr;
+    __IO uint16_t *dmy_rd_scfsr;
+    
+    dmy_rd_scscr = SCSCR_MATCH[index];
+    *dmy_rd_scscr &= 0x00B3;                    // Clear RIE,REIE and Write to bit15~8,2 is always 0
+    dmy_rd_scfsr = SCFSR_MATCH[index];
+    *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003);  // Clear RDF,DR
+
     irq_handler(uart_data[index].serial_irq_id, RxIrq);
-    GIC_EndInterrupt(irq_num);
 }
+
 /* TX handler */
-void uart0_tx_irq()  {uart_tx_irq(SCIFTXI0_IRQn, 0);}
-void uart1_tx_irq()  {uart_tx_irq(SCIFTXI1_IRQn, 1);}
-void uart2_tx_irq()  {uart_tx_irq(SCIFTXI2_IRQn, 2);}
-void uart3_tx_irq()  {uart_tx_irq(SCIFTXI3_IRQn, 3);}
-void uart4_tx_irq()  {uart_tx_irq(SCIFTXI4_IRQn, 4);}
-void uart5_tx_irq()  {uart_tx_irq(SCIFTXI5_IRQn, 5);}
-void uart6_tx_irq()  {uart_tx_irq(SCIFTXI6_IRQn, 6);}
-void uart7_tx_irq()  {uart_tx_irq(SCIFTXI7_IRQn, 7);}
+static void uart0_tx_irq(void)  {uart_tx_irq(SCIFTXI0_IRQn, 0);}
+static void uart1_tx_irq(void)  {uart_tx_irq(SCIFTXI1_IRQn, 1);}
+static void uart2_tx_irq(void)  {uart_tx_irq(SCIFTXI2_IRQn, 2);}
+static void uart3_tx_irq(void)  {uart_tx_irq(SCIFTXI3_IRQn, 3);}
+static void uart4_tx_irq(void)  {uart_tx_irq(SCIFTXI4_IRQn, 4);}
+static void uart5_tx_irq(void)  {uart_tx_irq(SCIFTXI5_IRQn, 5);}
+static void uart6_tx_irq(void)  {uart_tx_irq(SCIFTXI6_IRQn, 6);}
+static void uart7_tx_irq(void)  {uart_tx_irq(SCIFTXI7_IRQn, 7);}
 /* RX handler */
-void uart0_rx_irq()  {uart_rx_irq(SCIFRXI0_IRQn, 0);}
-void uart1_rx_irq()  {uart_rx_irq(SCIFRXI1_IRQn, 1);}
-void uart2_rx_irq()  {uart_rx_irq(SCIFRXI2_IRQn, 2);}
-void uart3_rx_irq()  {uart_rx_irq(SCIFRXI3_IRQn, 3);}
-void uart4_rx_irq()  {uart_rx_irq(SCIFRXI4_IRQn, 4);}
-void uart5_rx_irq()  {uart_rx_irq(SCIFRXI5_IRQn, 5);}
-void uart6_rx_irq()  {uart_rx_irq(SCIFRXI6_IRQn, 6);}
-void uart7_rx_irq()  {uart_rx_irq(SCIFRXI7_IRQn, 7);}
+static void uart0_rx_irq(void)  {uart_rx_irq(SCIFRXI0_IRQn, 0);}
+static void uart1_rx_irq(void)  {uart_rx_irq(SCIFRXI1_IRQn, 1);}
+static void uart2_rx_irq(void)  {uart_rx_irq(SCIFRXI2_IRQn, 2);}
+static void uart3_rx_irq(void)  {uart_rx_irq(SCIFRXI3_IRQn, 3);}
+static void uart4_rx_irq(void)  {uart_rx_irq(SCIFRXI4_IRQn, 4);}
+static void uart5_rx_irq(void)  {uart_rx_irq(SCIFRXI5_IRQn, 5);}
+static void uart6_rx_irq(void)  {uart_rx_irq(SCIFRXI6_IRQn, 6);}
+static void uart7_rx_irq(void)  {uart_rx_irq(SCIFRXI7_IRQn, 7);}
 
 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
     irq_handler = handler;
@@ -326,71 +338,20 @@
 }
 
 static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
-    switch (obj->index){
-        case 0:
-            InterruptHandlerRegister(SCIFTXI0_IRQn, (void (*)(uint32_t))uart0_tx_irq);
-            InterruptHandlerRegister(SCIFRXI0_IRQn, (void (*)(uint32_t))uart0_rx_irq);
-            GIC_SetPriority(SCIFTXI0_IRQn, 5);
-            GIC_SetPriority(SCIFRXI0_IRQn, 5);
-            GIC_EnableIRQ(SCIFTXI0_IRQn);
-            GIC_EnableIRQ(SCIFRXI0_IRQn);
-            break;
-        case 1:
-            InterruptHandlerRegister(SCIFTXI1_IRQn, (void (*)(uint32_t))uart1_tx_irq);
-            InterruptHandlerRegister(SCIFRXI1_IRQn, (void (*)(uint32_t))uart1_rx_irq);
-            GIC_SetPriority(SCIFTXI1_IRQn, 5);
-            GIC_SetPriority(SCIFRXI1_IRQn, 5);
-            GIC_EnableIRQ(SCIFTXI1_IRQn);
-            GIC_EnableIRQ(SCIFRXI1_IRQn);
-            break;
-        case 2:
-            InterruptHandlerRegister(SCIFTXI2_IRQn, (void (*)(uint32_t))uart2_tx_irq);
-            InterruptHandlerRegister(SCIFRXI2_IRQn, (void (*)(uint32_t))uart2_rx_irq);
-            GIC_SetPriority(SCIFTXI2_IRQn, 5);
-            GIC_SetPriority(SCIFRXI2_IRQn, 5);
-            GIC_EnableIRQ(SCIFTXI2_IRQn);
-            GIC_EnableIRQ(SCIFRXI2_IRQn);
-            break;
-        case 3:
-            InterruptHandlerRegister(SCIFTXI3_IRQn, (void (*)(uint32_t))uart3_tx_irq);
-            InterruptHandlerRegister(SCIFRXI3_IRQn, (void (*)(uint32_t))uart3_rx_irq);
-            GIC_SetPriority(SCIFTXI3_IRQn, 5);
-            GIC_SetPriority(SCIFRXI3_IRQn, 5);
-            GIC_EnableIRQ(SCIFTXI3_IRQn);
-            GIC_EnableIRQ(SCIFRXI3_IRQn);
-            break;
-        case 4:
-            InterruptHandlerRegister(SCIFTXI4_IRQn, (void (*)(uint32_t))uart4_tx_irq);
-            InterruptHandlerRegister(SCIFRXI4_IRQn, (void (*)(uint32_t))uart4_rx_irq);
-            GIC_SetPriority(SCIFTXI4_IRQn, 5);
-            GIC_SetPriority(SCIFRXI4_IRQn, 5);
-            GIC_EnableIRQ(SCIFTXI4_IRQn);
-            GIC_EnableIRQ(SCIFRXI4_IRQn);
-            break;
-        case 5:
-            InterruptHandlerRegister(SCIFTXI5_IRQn, (void (*)(uint32_t))uart5_tx_irq);
-            InterruptHandlerRegister(SCIFRXI5_IRQn, (void (*)(uint32_t))uart5_rx_irq);
-            GIC_SetPriority(SCIFTXI5_IRQn, 5);
-            GIC_SetPriority(SCIFRXI5_IRQn, 5);
-            GIC_EnableIRQ(SCIFTXI5_IRQn);
-            GIC_EnableIRQ(SCIFRXI5_IRQn);
-            break;
-        case 6:
-            InterruptHandlerRegister(SCIFTXI6_IRQn, (void (*)(uint32_t))uart6_tx_irq);
-            InterruptHandlerRegister(SCIFRXI6_IRQn, (void (*)(uint32_t))uart6_rx_irq);
-            GIC_SetPriority(SCIFTXI6_IRQn, 5);
-            GIC_SetPriority(SCIFRXI6_IRQn, 5);
-            GIC_EnableIRQ(SCIFTXI6_IRQn);
-            GIC_EnableIRQ(SCIFRXI6_IRQn);
-            break;
-        case 7:
-            InterruptHandlerRegister(SCIFTXI7_IRQn, (void (*)(uint32_t))uart7_tx_irq);
-            InterruptHandlerRegister(SCIFRXI7_IRQn, (void (*)(uint32_t))uart7_rx_irq);
-            GIC_SetPriority(SCIFTXI7_IRQn, 5);
-            GIC_SetPriority(SCIFRXI7_IRQn, 5);
-            GIC_EnableIRQ(SCIFTXI7_IRQn);
-            GIC_EnableIRQ(SCIFRXI7_IRQn);
-            break;
+    IRQn_Type IRQn;
+    IRQHandler handler;
+
+    IRQn = irq_set_tbl[obj->index][irq];
+    handler = hander_set_tbl[obj->index][irq];
+
+    if ((obj->index >= 0) && (obj->index <= 7)) {
+        if (enable) {
+            InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
+            GIC_SetPriority(IRQn, 5);
+            GIC_EnableIRQ(IRQn);
+        } else {
+            GIC_DisableIRQ(IRQn);
+        }
     }
 }
 
@@ -409,7 +370,13 @@
  * READ/WRITE
  ******************************************************************************/
 int serial_getc(serial_t *obj) {
-    if (obj->uart->SCFSR & 0x93) { obj->uart->SCFSR = ~0x93;}
+    uint16_t dummy_read;
+    
+    if (obj->uart->SCFSR & 0x93) {
+        dummy_read = obj->uart->SCFSR;
+        obj->uart->SCFSR = (dummy_read & ~0x93);
+    }
+    obj->uart->SCSCR |= 0x0040;     // Set RIE
     while (!serial_readable(obj));
     int data = obj->uart->SCFRDR & 0xff;
                 /* Clear DR,RDF */
@@ -418,9 +385,13 @@
 }
 
 void serial_putc(serial_t *obj, int c) {
+    uint16_t dummy_read;
+    
+    obj->uart->SCSCR |= 0x0080;     // Set TIE
     while (!serial_writable(obj));
     obj->uart->SCFTDR = c;
-    obj->uart->SCFSR &= 0xff9f;  // Clear TEND/TDFE
+    dummy_read = obj->uart->SCFSR;
+    obj->uart->SCFSR = (dummy_read & 0xff9f);  // Clear TEND/TDFE
     uart_data[obj->index].count++;
 }
 
@@ -451,47 +422,5 @@
 
 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
     serial_flow_irq_set(obj, 0);
-    // Only UART1 has hardware flow control on LPC176x
-    /*LPC_UART1_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)LPC_UART1 ? LPC_UART1 : NULL;
-    int index = obj->index;
-
-    // First, disable flow control completely
-    if (uart1)
-        uart1->MCR = uart1->MCR & ~UART_MCR_FLOWCTRL_MASK;
-    uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC;
-    serial_flow_irq_set(obj, 0);
-    if (FlowControlNone == type)
-        return;
-    // Check type(s) of flow control to use
-    UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS);
-    UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS);
-    if (((FlowControlCTS == type) || (FlowControlRTSCTS == type)) && (NC != txflow)) {
-        // Can this be enabled in hardware?
-        if ((UART_1 == uart_cts) && (NULL != uart1)) {
-            // Enable auto-CTS mode
-            uart1->MCR |= UART_MCR_CTSEN_MASK;
-            pinmap_pinout(txflow, PinMap_UART_CTS);
-        } else {
-            // Can't enable in hardware, use software emulation
-            gpio_init_in(&uart_data[index].sw_cts, txflow);
-        }
-    }
-    if (((FlowControlRTS == type) || (FlowControlRTSCTS == type)) && (NC != rxflow)) {
-        // Enable FIFOs, trigger level of 1 char on RX FIFO
-        obj->uart->FCR = 1 << 0  // FIFO Enable - 0 = Disables, 1 = Enabled
-                       | 1 << 1  // Rx Fifo Reset
-                       | 1 << 2  // Tx Fifo Reset
-                       | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
-         // Can this be enabled in hardware?
-        if ((UART_1 == uart_rts) && (NULL != uart1)) {
-            // Enable auto-RTS mode
-            uart1->MCR |= UART_MCR_RTSEN_MASK;
-            pinmap_pinout(rxflow, PinMap_UART_RTS);
-        } else { // can't enable in hardware, use software emulation
-            gpio_init_out_ex(&uart_data[index].sw_rts, rxflow, 0);
-            // Enable RX interrupt
-            serial_flow_irq_set(obj, 1);
-        }
-    }*/
 }
 

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c	Thu Dec 11 14:15:07 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c	Mon Dec 15 09:00:08 2014 +0000
@@ -28,6 +28,8 @@
 
 int us_ticker_inited = 0;
 static double count_clock = 0;
+static uint32_t last_read = 0;
+static uint32_t wrap_arround = 0;
 
 void us_ticker_interrupt(void) {
     us_ticker_irq_handler();
@@ -36,12 +38,12 @@
 void us_ticker_init(void) {
     if (us_ticker_inited) return;
     us_ticker_inited = 1;
-    
+
     /* set Counter Clock(us) */
     if (false == RZ_A1_IsClockMode0()) {
-        count_clock = (double)(CM1_RENESAS_RZ_A1_P0_CLK / US_TICKER_CLOCK_US_DEV);
+        count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
     } else {
-        count_clock = (double)(CM0_RENESAS_RZ_A1_P0_CLK / US_TICKER_CLOCK_US_DEV);
+        count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
     }
 
     /* Power Control for Peripherals      */
@@ -61,14 +63,21 @@
 
 uint32_t us_ticker_read() {
     uint32_t val;
+    uint64_t val64;
+
     if (!us_ticker_inited)
         us_ticker_init();
-    
+
     /* read counter */
     val = OSTM1CNT;
-    
+    if ( last_read > val ) {
+        wrap_arround++;
+    }
+    last_read = val;
+    val64 = ((uint64_t)wrap_arround << 32) + val;
+
     /* clock to us */
-    val = (uint32_t)(val / count_clock);
+    val = (uint32_t)(val64 / count_clock);
     return val;
 }