Adam Kucybala
mbed library sources
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mbed official
Revision 174:8bb9f3a33240, committed 2014-04-29
- Comitter:
- mbed_official
- Date:
- Tue Apr 29 11:15:07 2014 +0100
- Parent:
- 173:033f1c328f6e
- Child:
- 175:906e2386ace8
- Commit message:
- Synchronized with git revision 5bf985ebc651a2c31cefabd9d62c51dc465ef60a
Full URL: https://github.com/mbedmicro/mbed/commit/5bf985ebc651a2c31cefabd9d62c51dc465ef60a/
[NUCLEO_L152RE/F103RB] Add LSE configuration for RTC
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,1247 @@
+
+/****************************************************************************************************//**
+ * @file LPC11U6x.h
+ *
+ * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
+ * LPC11U6x from .
+ *
+ * @version V0.4
+ * @date 22. October 2013
+ *
+ * @note Generated with SVDConv V2.81a
+ * from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
+ *
+ * modified by Keil
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+ * @{
+ */
+
+/** @addtogroup LPC11U6x
+ * @{
+ */
+
+#ifndef LPC11U6X_H
+#define LPC11U6X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+
+
+
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+
+
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
+ PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
+ PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
+ PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
+ PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
+ PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
+ PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
+ PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
+ PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
+ GINT0_IRQn = 8, /*!< 8 GINT0 */
+ GINT1_IRQn = 9, /*!< 9 GINT1 */
+ I2C1_IRQn = 10, /*!< 10 I2C1 */
+ USART1_4_IRQn = 11, /*!< 11 USART1_4 */
+ USART2_3_IRQn = 12, /*!< 12 USART2_3 */
+ SCT0_1_IRQn = 13, /*!< 13 SCT0_1 */
+ SSP1_IRQn = 14, /*!< 14 SSP1 */
+ I2C0_IRQn = 15, /*!< 15 I2C0 */
+ CT16B0_IRQn = 16, /*!< 16 CT16B0 */
+ CT16B1_IRQn = 17, /*!< 17 CT16B1 */
+ CT32B0_IRQn = 18, /*!< 18 CT32B0 */
+ CT32B1_IRQn = 19, /*!< 19 CT32B1 */
+ SSP0_IRQn = 20, /*!< 20 SSP0 */
+ USART0_IRQn = 21, /*!< 21 USART0 */
+ USB_IRQn = 22, /*!< 22 USB */
+ USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
+ ADC_A_IRQn = 24, /*!< 24 ADC_A */
+ RTC_IRQn = 25, /*!< 25 RTC */
+ BOD_WDT_IRQn = 26, /*!< 26 BOD_WDT */
+ FLASH_IRQn = 27, /*!< 27 FLASH */
+ DMA_IRQn = 28, /*!< 28 DMA */
+ ADC_B_IRQn = 29, /*!< 29 ADC_B */
+ USBWAKEUP_IRQn = 30 /*!< 30 USBWAKEUP */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
+#define __CM0PLUS_REV 0x0000 /*!< Cortex-M0PLUS Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
+#include "system_LPC11U6x.h" /*!< LPC11U6x System */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ I2C0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I2C-bus controller (I2C0)
+ */
+
+typedef struct { /*!< I2C0 Structure */
+ __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
+ this register, the corresponding bit in the I2C control register
+ is set. Writing a zero has no effect on the corresponding bit
+ in the I2C control register. */
+ __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
+ detailed status codes that allow software to determine the next
+ action needed. */
+ __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
+ to be transmitted is written to this register. During master
+ or slave receive mode, data that has been received may be read
+ from this register. */
+ __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
+ for operation of the I2C interface in slave mode, and is not
+ used in master mode. The least significant bit determines whether
+ a slave responds to the General Call address. */
+ __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
+ time of the I2C clock. */
+ __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
+ of the I2C clock. I2nSCLL and I2nSCLH together determine the
+ clock frequency generated by an I2C master and certain times
+ used in slave mode. */
+ __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
+ this register, the corresponding bit in the I2C control register
+ is cleared. Writing a zero has no effect on the corresponding
+ bit in the I2C control register. */
+ __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
+ __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
+ for operation of the I2C interface in slave mode, and is not
+ used in master mode. The least significant bit determines whether
+ a slave responds to the General Call address. */
+ __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
+ for operation of the I2C interface in slave mode, and is not
+ used in master mode. The least significant bit determines whether
+ a slave responds to the General Call address. */
+ __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
+ for operation of the I2C interface in slave mode, and is not
+ used in master mode. The least significant bit determines whether
+ a slave responds to the General Call address. */
+ __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
+ shift register will be transferred to the DATA_BUFFER automatically
+ after every nine bits (8 bits of data plus ACK or NACK) has
+ been received on the bus. */
+ __IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
+ with I2ADR0 to determine an address match. The mask register
+ has no effect when comparing to the General Call address (0000000). */
+ __IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
+ with I2ADR0 to determine an address match. The mask register
+ has no effect when comparing to the General Call address (0000000). */
+ __IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
+ with I2ADR0 to determine an address match. The mask register
+ has no effect when comparing to the General Call address (0000000). */
+ __IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
+ with I2ADR0 to determine an address match. The mask register
+ has no effect when comparing to the General Call address (0000000). */
+} LPC_I2C0_Type;
+
+
+/* ================================================================================ */
+/* ================ WWDT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Windowed Watchdog Timer (WWDT) (WWDT)
+ */
+
+typedef struct { /*!< WWDT Structure */
+ __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
+ and status of the Watchdog Timer. */
+ __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
+ the time-out value. */
+ __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
+ to this register reloads the Watchdog timer with the value contained
+ in WDTC. */
+ __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
+ the current value of the Watchdog timer. */
+ __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
+ __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+/* ================================================================================ */
+/* ================ USART0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USART0 (USART0)
+ */
+
+typedef struct { /*!< USART0 Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
+ value. The full divisor is used to generate a baud rate from
+ the fractional rate divider. (DLAB=1) */
+ __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
+ is written here. (DLAB=0) */
+ __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
+ to be read. (DLAB=0) */
+ };
+
+ union {
+ __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
+ bits for the 7 potential USART interrupts. (DLAB=0) */
+ __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
+ value. The full divisor is used to generate a baud rate from
+ the fractional rate divider. (DLAB=1) */
+ };
+
+ union {
+ __O uint32_t FCR; /*!< FIFO Control Register. Controls USART FIFO usage and modes. */
+ __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+ __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
+ and break generation. */
+ __IO uint32_t MCR; /*!< Modem Control Register. */
+ __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
+ status, including line errors. */
+ __I uint32_t MSR; /*!< Modem Status Register. */
+ __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
+ feature. */
+ __IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
+ control) mode. */
+ __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
+ baud rate divider. */
+ __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
+ each bit time. */
+ __IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
+ with software flow control. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /*!< Half duplex enable register. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
+ the Smart Card Interface feature. */
+ __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
+ aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
+ for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
+ __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. */
+} LPC_USART0_Type;
+
+
+/* ================================================================================ */
+/* ================ CT16B0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief 16-bit counter/timers CT16B0 (CT16B0)
+ */
+
+typedef struct { /*!< CT16B0 Structure */
+ __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
+ The IR can be read to identify which of eight possible interrupt
+ sources are pending. */
+ __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
+ Counter functions. The Timer Counter can be disabled or reset
+ through the TCR. */
+ __IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
+ of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
+ to this value, the next clock increments the TC and clears the
+ PC. */
+ __IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
+ to the value stored in PR. When the value in PR is reached,
+ the TC is incremented and the PC is cleared. The PC is observable
+ and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
+ is generated and if the TC is reset when a Match occurs. */
+ __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
+ capture inputs are used to load the Capture Registers and whether
+ or not an interrupt is generated when a capture takes place. */
+ __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
+ and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+ __I uint32_t RESERVED1[12];
+ __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
+ mode, and in Counter mode selects the signal and edge(s) for
+ counting. */
+ __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
+ match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CT16B0_Type;
+
+
+/* ================================================================================ */
+/* ================ CT32B0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief 32-bit counter/timers CT32B0 (CT32B0)
+ */
+
+typedef struct { /*!< CT32B0 Structure */
+ __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
+ The IR can be read to identify which of eight possible interrupt
+ sources are pending. */
+ __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
+ Counter functions. The Timer Counter can be disabled or reset
+ through the TCR. */
+ __IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
+ of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
+ to this value, the next clock increments the TC and clears the
+ PC. */
+ __IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
+ to the value stored in PR. When the value in PR is reached,
+ the TC is incremented and the PC is cleared. The PC is observable
+ and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
+ is generated and if the TC is reset when a Match occurs. */
+ __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
+ capture inputs are used to load the Capture Registers and whether
+ or not an interrupt is generated when a capture takes place. */
+ __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
+ and the external match pins CT32Bn_MAT[3:0]. */
+ __I uint32_t RESERVED1[12];
+ __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
+ mode, and in Counter mode selects the signal and edge(s) for
+ counting. */
+ __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
+ match pins CT32Bn_MAT[3:0]. */
+} LPC_CT32B0_Type;
+
+
+/* ================================================================================ */
+/* ================ ADC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
+ */
+
+typedef struct { /*!< ADC Structure */
+ __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
+ bits for each sequence and the A/D power-down bit. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
+ and channel selection for conversion sequence-A. Also specifies
+ interrupt mode for sequence-A. */
+ __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
+ and channel selection for conversion sequence-B. Also specifies
+ interrupt mode for sequence-B. */
+ __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
+ the result of the most recent A/D conversion performed under
+ sequence-A */
+ __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
+ the result of the most recent A/D conversion performed under
+ sequence-B */
+ __I uint32_t RESERVED1[2];
+ __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
+ of the most recent conversion completed on channel 0. */
+ __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 0. */
+ __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 1. */
+ __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 0. */
+ __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 1. */
+ __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
+ threshold compare registers are to be used for each channel */
+ __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
+ bits that enable the sequence-A, sequence-B, threshold compare
+ and data overrun interrupts to be generated. */
+ __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
+ and the individual component overrun and threshold-compare flags.
+ (The overrun bits replicate information stored in the result
+ registers). */
+ __IO uint32_t TRM; /*!< ADC trim register. */
+} LPC_ADC_Type;
+
+
+/* ================================================================================ */
+/* ================ RTC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Real-Time Clock (RTC) (RTC)
+ */
+
+typedef struct { /*!< RTC Structure */
+ __IO uint32_t CTRL; /*!< RTC control register */
+ __IO uint32_t MATCH; /*!< RTC match register */
+ __IO uint32_t COUNT; /*!< RTC counter register */
+ __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
+} LPC_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================ DMATRIGMUX ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
+ */
+
+typedef struct { /*!< DMATRIGMUX Structure */
+ __IO uint32_t DMA_ITRIG_PINMUX[16]; /*!< Trigger input select register for DMA channel 0. */
+} LPC_DMATRIGMUX_Type;
+
+
+/* ================================================================================ */
+/* ================ PMU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
+ */
+
+typedef struct { /*!< PMU Structure */
+ __IO uint32_t PCON; /*!< Power control register */
+ __IO uint32_t GPREG0; /*!< General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< General purpose register 0 */
+ __IO uint32_t GPREG2; /*!< General purpose register 0 */
+ __IO uint32_t GPREG3; /*!< General purpose register 0 */
+ __IO uint32_t DPDCTRL; /*!< Deep power down control register */
+} LPC_PMU_Type;
+
+
+/* ================================================================================ */
+/* ================ FLASHCTRL ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Flash controller (FLASHCTRL)
+ */
+
+typedef struct { /*!< FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< Flash configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
+ __I uint32_t RESERVED2;
+ __I uint32_t FMSW0; /*!< Signature Word */
+} LPC_FLASHCTRL_Type;
+
+
+/* ================================================================================ */
+/* ================ SSP0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SSP/SPI (SSP0)
+ */
+
+typedef struct { /*!< SSP0 Structure */
+ __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
+ and data size. */
+ __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
+ the receive FIFO. */
+ __I uint32_t SR; /*!< Status Register */
+ __IO uint32_t CPSR; /*!< Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< Masked Interrupt Status Register */
+ __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
+} LPC_SSP0_Type;
+
+
+/* ================================================================================ */
+/* ================ IOCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
+ */
+
+typedef struct { /*!< IOCON Structure */
+ __IO uint32_t PIO0_0; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_1; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_2; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_3; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_4; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_5; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_6; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_7; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_8; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_9; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_10; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_11; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_12; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_13; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_14; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_15; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_16; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_17; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_18; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_19; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_20; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_21; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_22; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_23; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO1_0; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_1; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_2; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_3; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_4; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_5; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_6; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_7; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_8; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_9; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_10; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_11; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_12; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_13; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_14; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_15; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_16; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_17; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_18; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_19; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_20; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_21; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_22; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_23; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_24; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_25; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_26; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_27; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_28; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_29; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_30; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_31; /*!< I/O configuration for port PIO1 */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t PIO2_0; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_1; /*!< I/O configuration for port PIO2 */
+ __I uint32_t RESERVED1;
+ __IO uint32_t PIO2_2; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_3; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_4; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_5; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_6; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_7; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_8; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_9; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_10; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_11; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_12; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_13; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_14; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_15; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_16; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_17; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_18; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_19; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_20; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_21; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_22; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_23; /*!< I/O configuration for port PIO2 */
+} LPC_IOCON_Type;
+
+
+/* ================================================================================ */
+/* ================ SYSCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
+ */
+
+typedef struct { /*!< SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< System PLL status */
+ __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
+ __I uint32_t USBPLLSTAT; /*!< USB PLL status */
+ __I uint32_t RESERVED0;
+ __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator 32 kHz output control */
+ __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< Watchdog oscillator control */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
+ __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable */
+ __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
+ __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable */
+ __I uint32_t RESERVED3[8];
+ __IO uint32_t MAINCLKSEL; /*!< Main clock source select */
+ __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable */
+ __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
+ __I uint32_t RESERVED4;
+ __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider */
+ __IO uint32_t USART0CLKDIV; /*!< USART0 clock divider */
+ __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider */
+ __IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
+ of USART1 to USART4 */
+ __I uint32_t RESERVED6[7];
+ __IO uint32_t USBCLKSEL; /*!< USB clock source select */
+ __IO uint32_t USBCLKUEN; /*!< USB clock source update enable */
+ __IO uint32_t USBCLKDIV; /*!< USB clock source divider */
+ __I uint32_t RESERVED7[5];
+ __IO uint32_t CLKOUTSEL; /*!< CLKOUT clock source select */
+ __IO uint32_t CLKOUTUEN; /*!< CLKOUT clock source update enable */
+ __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
+ __I uint32_t RESERVED8;
+ __IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider value */
+ __IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier value */
+ __I uint32_t RESERVED9;
+ __IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
+ __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
+ __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
+ __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 1 */
+ __I uint32_t RESERVED10[10];
+ __IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
+ __IO uint32_t AHBMATRIXPRIO; /*!< AHB matrix priority configuration */
+ __I uint32_t RESERVED11[5];
+ __IO uint32_t IRQLATENCY; /*!< IRQ delay. Allows trade-off between interrupt latency and determinism. */
+ __IO uint32_t NMISRC; /*!< NMI Source Control */
+ union {
+ __IO uint32_t PINTSEL[8];
+ struct {
+ __IO uint32_t PINTSEL0; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL1; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL2; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL3; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL4; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL5; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL6; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL7; /*!< GPIO Pin Interrupt Select register 0 */
+ };
+ };
+ __IO uint32_t USBCLKCTRL; /*!< USB clock control */
+ __I uint32_t USBCLKST; /*!< USB clock status */
+ __I uint32_t RESERVED12[25];
+ __IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register 0 */
+ __I uint32_t RESERVED13[3];
+ __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register 1 */
+ __I uint32_t RESERVED14[6];
+ __IO uint32_t PDSLEEPCFG; /*!< Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< Power configuration register */
+ __I uint32_t RESERVED15[110];
+ __I uint32_t DEVICE_ID; /*!< Device ID */
+} LPC_SYSCON_Type;
+
+
+/* ================================================================================ */
+/* ================ USART4 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USART4 (USART4)
+ */
+
+typedef struct { /*!< USART4 Structure */
+ __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
+ that typically are not changed during operation. */
+ __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
+ likely to change during operation. */
+ __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
+ here. Writing ones clears some bits in the register. Some bits
+ can be cleared by writing a 1 to them. */
+ __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
+ interrupt enable bit for each potential USART interrupt. A complete
+ value may be read from this register. Writing a 1 to any implemented
+ bit position causes that bit to be set. */
+ __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
+ of bits in the INTENSET register. Writing a 1 to any implemented
+ bit position causes the corresponding bit to be cleared. */
+ __I uint32_t RXDAT; /*!< Receiver Data register. Contains the last character received. */
+ __I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
+ received with the current USART receive status. Allows DMA or
+ software to recover incoming data and status together. */
+ __IO uint32_t TXDAT; /*!< Transmit Data register. Data to be transmitted is written here. */
+ __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
+ value. */
+ __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
+ enabled. */
+ __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
+ __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
+} LPC_USART4_Type;
+
+
+/* ================================================================================ */
+/* ================ GINT0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief GPIO group interrupt 0 (GINT0)
+ */
+
+typedef struct { /*!< GINT0 Structure */
+ __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[5];
+ __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port enable register */
+} LPC_GINT0_Type;
+
+
+/* ================================================================================ */
+/* ================ USB ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USB device controller (USB)
+ */
+
+typedef struct { /*!< USB Structure */
+ __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
+ __IO uint32_t INFO; /*!< USB Info register */
+ __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
+ __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
+ __IO uint32_t LPM; /*!< Link Power Management register */
+ __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
+ __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
+ __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
+ __IO uint32_t INTSTAT; /*!< USB interrupt status register */
+ __IO uint32_t INTEN; /*!< USB interrupt enable register */
+ __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
+ __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
+ __I uint32_t RESERVED0;
+ __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+/* ================================================================================ */
+/* ================ CRC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Cyclic Redundancy Check (CRC) engine (CRC)
+ */
+
+typedef struct { /*!< CRC Structure */
+ __IO uint32_t MODE; /*!< CRC mode register */
+ __IO uint32_t SEED; /*!< CRC seed register */
+
+ union {
+ __O uint32_t WR_DATA; /*!< CRC data register */
+ __I uint32_t SUM; /*!< CRC checksum register */
+ };
+} LPC_CRC_Type;
+
+
+/* ================================================================================ */
+/* ================ DMA ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
+ */
+
+typedef struct { /*!< DMA Structure */
+ __IO uint32_t CTRL; /*!< DMA control. */
+ __I uint32_t INTSTAT; /*!< Interrupt status. */
+ __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED1;
+ __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED2;
+ __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
+ __I uint32_t RESERVED3;
+ __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
+ __I uint32_t RESERVED4;
+ __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED6;
+ __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED7;
+ __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
+ __I uint32_t RESERVED8;
+ __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
+ __I uint32_t RESERVED9;
+ __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
+ __I uint32_t RESERVED10;
+ __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
+ __I uint32_t RESERVED11;
+ __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
+ __I uint32_t RESERVED12[225];
+ __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED13;
+ __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED14;
+ __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED15;
+ __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED16;
+ __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED17;
+ __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED18;
+ __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED19;
+ __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED20;
+ __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED21;
+ __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED22;
+ __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED23;
+ __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED24;
+ __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED25;
+ __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED26;
+ __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED27;
+ __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
+} LPC_DMA_Type;
+
+
+/* ================================================================================ */
+/* ================ SCT0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
+ */
+
+typedef struct { /*!< SCT0 Structure */
+ __IO uint32_t CONFIG; /*!< SCT configuration register */
+ __IO uint32_t CTRL; /*!< SCT control register */
+ __IO uint32_t LIMIT; /*!< SCT limit register */
+ __IO uint32_t HALT; /*!< SCT halt condition register */
+ __IO uint32_t STOP; /*!< SCT stop condition register */
+ __IO uint32_t START; /*!< SCT start condition register */
+ __I uint32_t RESERVED0[10];
+ __IO uint32_t COUNT; /*!< SCT counter register */
+ __IO uint32_t STATE; /*!< SCT state register */
+ __I uint32_t INPUT; /*!< SCT input register */
+ __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
+ __IO uint32_t OUTPUT; /*!< SCT output register */
+ __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
+ __IO uint32_t RES; /*!< SCT conflict resolution register */
+ __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
+ __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
+ __I uint32_t RESERVED1[35];
+ __IO uint32_t EVEN; /*!< SCT event enable register */
+ __IO uint32_t EVFLAG; /*!< SCT event flag register */
+ __IO uint32_t CONEN; /*!< SCT conflict enable register */
+ __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
+
+ union {
+ __IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
+ REGMODE4 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
+ REGMODE4 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
+ REGMODE4 = 0 */
+ __IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
+ REGMODE4 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
+ REGMODE4 = 0 */
+ };
+ __I uint32_t RESERVED2[59];
+
+ union {
+ __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
+ = 0 */
+ __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
+ = 0 */
+ __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
+ = 0 */
+ };
+ __I uint32_t RESERVED3[59];
+ __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
+ __I uint32_t RESERVED4[116];
+ __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
+} LPC_SCT0_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIO_PORT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief General Purpose I/O (GPIO) (GPIO_PORT)
+ */
+
+typedef struct { /*!< GPIO_PORT Structure */
+ __IO uint8_t B[88]; /*!< Byte pin registers */
+ __I uint32_t RESERVED0[42];
+ __IO uint32_t W[88]; /*!< Word pin registers */
+ __I uint32_t RESERVED1[1896];
+ __IO uint32_t DIR[3]; /*!< Port Direction registers */
+ __I uint32_t RESERVED2[29];
+ __IO uint32_t MASK[3]; /*!< Port Mask register */
+ __I uint32_t RESERVED3[29];
+ __IO uint32_t PIN[3]; /*!< Port pin register */
+ __I uint32_t RESERVED4[29];
+ __IO uint32_t MPIN[3]; /*!< Masked port register */
+ __I uint32_t RESERVED5[29];
+ __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
+ __I uint32_t RESERVED6[29];
+ __O uint32_t CLR[3]; /*!< Clear port */
+ __I uint32_t RESERVED7[29];
+ __O uint32_t NOT[3]; /*!< Toggle port */
+} LPC_GPIO_PORT_Type;
+
+
+/* ================================================================================ */
+/* ================ PINT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Pin interruptand pattern match (PINT) (PINT)
+ */
+
+typedef struct { /*!< PINT Structure */
+ __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
+ __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
+ __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
+ __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
+ register */
+ __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
+ __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
+ __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
+ __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
+ __IO uint32_t IST; /*!< Pin interrupt status register */
+ __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
+ __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
+ __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
+} LPC_PINT_Type;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+#define LPC_I2C0_BASE 0x40000000UL
+#define LPC_WWDT_BASE 0x40004000UL
+#define LPC_USART0_BASE 0x40008000UL
+#define LPC_CT16B0_BASE 0x4000C000UL
+#define LPC_CT16B1_BASE 0x40010000UL
+#define LPC_CT32B0_BASE 0x40014000UL
+#define LPC_CT32B1_BASE 0x40018000UL
+#define LPC_ADC_BASE 0x4001C000UL
+#define LPC_I2C1_BASE 0x40020000UL
+#define LPC_RTC_BASE 0x40024000UL
+#define LPC_DMATRIGMUX_BASE 0x40028000UL
+#define LPC_PMU_BASE 0x40038000UL
+#define LPC_FLASHCTRL_BASE 0x4003C000UL
+#define LPC_SSP0_BASE 0x40040000UL
+#define LPC_IOCON_BASE 0x40044000UL
+#define LPC_SYSCON_BASE 0x40048000UL
+#define LPC_USART4_BASE 0x4004C000UL
+#define LPC_SSP1_BASE 0x40058000UL
+#define LPC_GINT0_BASE 0x4005C000UL
+#define LPC_GINT1_BASE 0x40060000UL
+#define LPC_USART1_BASE 0x4006C000UL
+#define LPC_USART2_BASE 0x40070000UL
+#define LPC_USART3_BASE 0x40074000UL
+#define LPC_USB_BASE 0x40080000UL
+#define LPC_CRC_BASE 0x50000000UL
+#define LPC_DMA_BASE 0x50004000UL
+#define LPC_SCT0_BASE 0x5000C000UL
+#define LPC_SCT1_BASE 0x5000E000UL
+#define LPC_GPIO_PORT_BASE 0xA0000000UL
+#define LPC_PINT_BASE 0xA0004000UL
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
+#define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
+#define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
+#define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
+#define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
+#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
+#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
+#define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
+#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
+#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
+#define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
+#define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
+#define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
+#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
+#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
+#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
+#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
+#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
+#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group LPC11U6x */
+/** @} */ /* End of group (null) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC11U6x_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/LPC11U68.sct Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,13 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
+ ; 32kB (0x8000) - 0x100 = 0x7F00
+ RW_IRAM1 (0x10000000+0x100) (0x8000-0x100) {
+ .ANY (+RW +ZI)
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/startup_LPC11U6x.s Tue Apr 29 11:15:07 2014 +0100 @@ -0,0 +1,244 @@ +;/**************************************************************************//** +; * @file startup_LPC11U6x.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * NXP LPC11U6x Device Series +; * @version V1.00 +; * @date 22. October 2013 +; * +; * @note +; * Copyright (C) 2013 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +__initial_sp EQU 0x10008000 ; Top of RAM from LPC1U68 + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0 + DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1 + DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2 + DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3 + DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4 + DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5 + DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6 + DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7 + DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt + DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt + DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt + DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts + DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts + DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts + DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt + DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt + DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt + DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt + DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt + DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt + DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt + DCD USART0_IRQHandler ; 16+21 USART0 interrupt + DCD USB_IRQHandler ; 16+22 USB interrupt + DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt + DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts + DCD RTC_IRQHandler ; 16+25 RTC interrupt + DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt + DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts + DCD DMA_IRQHandler ; 16+28 DMA interrupt + DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts + DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt + DCD 0 ; 16+31 Reserved + +; <h> Code Read Protection +; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled +; <0x12345678=>CRP Level 1 +; <0x87654321=>CRP Level 2 +; <0x43218765=>CRP Level 3 (ARE YOU SURE?) +; <0x4E697370=>NO ISP (ARE YOU SURE?) +; </h> + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY + DCD 0xFFFFFFFF + ENDIF + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PIN_INT0_IRQHandler [WEAK] + EXPORT PIN_INT1_IRQHandler [WEAK] + EXPORT PIN_INT2_IRQHandler [WEAK] + EXPORT PIN_INT3_IRQHandler [WEAK] + EXPORT PIN_INT4_IRQHandler [WEAK] + EXPORT PIN_INT5_IRQHandler [WEAK] + EXPORT PIN_INT6_IRQHandler [WEAK] + EXPORT PIN_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT USART1_4_IRQHandler [WEAK] + EXPORT USART2_3_IRQHandler [WEAK] + EXPORT SCT0_1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT CT16B0_IRQHandler [WEAK] + EXPORT CT16B1_IRQHandler [WEAK] + EXPORT CT32B0_IRQHandler [WEAK] + EXPORT CT32B1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQ_IRQHandler [WEAK] + EXPORT ADC_A_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT BOD_WDT_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT ADC_B_IRQHandler [WEAK] + EXPORT USBWAKEUP_IRQHandler [WEAK] + +PIN_INT0_IRQHandler +PIN_INT1_IRQHandler +PIN_INT2_IRQHandler +PIN_INT3_IRQHandler +PIN_INT4_IRQHandler +PIN_INT5_IRQHandler +PIN_INT6_IRQHandler +PIN_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +I2C1_IRQHandler +USART1_4_IRQHandler +USART2_3_IRQHandler +SCT0_1_IRQHandler +SSP1_IRQHandler +I2C0_IRQHandler +CT16B0_IRQHandler +CT16B1_IRQHandler +CT32B0_IRQHandler +CT32B1_IRQHandler +SSP0_IRQHandler +USART0_IRQHandler +USB_IRQHandler +USB_FIQ_IRQHandler +ADC_A_IRQHandler +RTC_IRQHandler +BOD_WDT_IRQHandler +FLASH_IRQHandler +DMA_IRQHandler +ADC_B_IRQHandler +USBWAKEUP_IRQHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/sys.cpp Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis.h Tue Apr 29 11:15:07 2014 +0100 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC8xx specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC11U6x.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.c Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.h Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.c Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,555 @@
+/**************************************************************************//**
+ * @file system_LPC11U6x.c
+ * @brief CMSIS Cortex-M3 Device System Source File for
+ * NXP LPC11U6x Device Series
+ * @version V1.00
+ * @date 19. July 2013
+ *
+ * @note
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC11U6x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*- SystemCoreClock Configuration -------------------------------------------*/
+// <e0> SystemCoreClock Configuration
+#define CLOCK_SETUP 1
+//
+// <h> System Oscillator Control (SYSOSCCTRL)
+// <o.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o.1> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+#define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
+//
+// <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
+// <0=> IRC Oscillator
+// <1=> Crystal Oscillator (SYSOSC)
+// <3=> RTC Oscillator (32 kHz)
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
+//
+// <e> Clock Configuration (Manual)
+#define CLOCK_SETUP_REG 1
+//
+// <h> WD Oscillator Setting (WDTOSCCTRL)
+// <o.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wd_osc_clk = Fclkana / (2 × (1 + DIVSEL))
+// <0-31>
+// <o.5..8> FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana)
+// <1=> 0.5 MHz
+// <2=> 0.8 MHz
+// <3=> 1.1 MHz
+// <4=> 1.4 MHz
+// <5=> 1.6 MHz
+// <6=> 1.8 MHz
+// <7=> 2.0 MHz
+// <8=> 2.2 MHz
+// <9=> 2.4 MHz
+// <10=> 2.6 MHz
+// <11=> 2.7 MHz
+// <12=> 2.9 MHz
+// <13=> 3.1 MHz
+// <14=> 3.2 MHz
+// <15=> 3.4 MHz
+// </h>
+#define WDTOSCCTRL_Val 0x000000A0 // Reset value: 0x0A0
+//
+// <h> System PLL Setting (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.5..6> PSEL: Post Divider Selection
+// <i> Post divider ratio P. Division ratio is 2 * P
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define SYSPLLCTRL_Val 0x00000003 // Reset value: 0x000
+//
+// <o.0..1> Main Clock Source Select (MAINCLKSEL)
+// <0=> IRC Oscillator
+// <1=> PLL Input
+// <2=> WD Oscillator
+// <3=> PLL Output
+#define MAINCLKSEL_Val 0x00000003 // Reset value: 0x000
+//
+// <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
+// </e>
+//
+// <e> Clock Configuration (via ROM PLL API)
+#define CLOCK_SETUP_API 0
+//
+// <o> PLL API Mode Select
+// <0=> Exact
+// <1=> Less than or equal
+// <2=> Greater than or equal
+// <3=> As close as possible
+#define PLL_API_MODE_Val 0
+//
+// <o> CPU Frequency [Hz] <1000000-50000000:1000>
+#define PLL_API_FREQ_Val 48000000
+// </e>
+//
+// <e> USB Clock Configuration
+#define USB_CLOCK_SETUP 1
+// <h> USB PLL Control (USBPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.5..6> PSEL: Post Divider Selection
+// <i> Post divider ratio P. Division ratio is 2 * P
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
+//
+// <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
+// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+#define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
+//
+// <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
+// <0=> USB PLL out
+// <1=> Main clock
+#define USBCLKSEL_Val 0x00000000 // Reset value: 0x000
+//
+// <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
+// <i> Divides USB clock to 48 MHz.
+// <i> 0 = is disabled
+// <0-255>
+#define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
+// </e>
+//
+// </e>
+//
+// <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
+// <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
+//
+#define XTAL_CLK_Val 12000000
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
+#define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
+#define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
+#define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (SYSPLLCLKSEL_Val == 3) // RTC Oscillator used as PLL input
+ #if (CLOCK_SETUP_API == 1)
+ #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
+ #endif
+ #if (CLOCK_SETUP_REG == 1) && (MAINCLKSEL_Val == 3) // RTC Oscillator used as PLL input
+ #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
+ #endif
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x0000007F))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+#if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
+ #error "You must select either manual or API based Clock Configuration!"
+#endif
+
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
+ #error "USBPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000007F))
+ #error "USBPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
+ #error "USBCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
+ #error "USBCLKDIV: Value out of range!"
+#endif
+
+#if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
+ #error "XTAL frequency is out of bounds"
+#endif
+
+#if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
+ #error "PLL API Mode Select not valid"
+#endif
+
+#if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 50000000))
+ #error "CPU Frequency (API mode) not valid"
+#endif
+
+
+
+/*----------------------------------------------------------------------------
+ Calculate system core clock
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP) /* Clock Setup */
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ #define __SYS_PLLCLKIN (__RTC_OSC_CLK)
+ #else
+ #error "Oops"
+ #endif
+
+ #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
+
+ #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+ #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+ #if (__FREQSEL == 0)
+ #error "WDTOSCCTRL.FREQSEL undefined!"
+ #elif (__FREQSEL == 1)
+ #define __OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #define __MAIN_CLOCK (__OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #error "Oops"
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+ #endif /* Clock Setup via Register */
+
+ #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
+ #define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
+ #endif /* Clock Setup via PLL API */
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif /* CLOCK_SETUP */
+
+
+
+#if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
+#include "power_api.h"
+
+typedef struct _ROM {
+ const unsigned p_dev0;
+ const unsigned p_dev1;
+ const unsigned p_dev2;
+ const PWRD * pPWRD; /* ROM Power Management API */
+ const unsigned p_dev4;
+ const unsigned p_dev5;
+ const unsigned p_dev6;
+ const unsigned p_dev7;
+} ROM;
+
+/*----------------------------------------------------------------------------
+ PLL API Function
+ *----------------------------------------------------------------------------*/
+static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
+{
+ uint32_t cmd[5], res[5];
+ ROM ** rom = (ROM **) 0x1FFF1FF8; /* pointer to power API calls */
+
+ cmd[0] = pllInFreq; /* PLL's input freq in KHz */
+ cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
+ cmd[2] = pllMode;
+ cmd[3] = 0; /* no timeout for PLL to lock */
+
+ /* Execute API call */
+ (*rom)->pPWRD->set_pll(cmd, res); /* call API function */
+ if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
+ while(1); /* ... stay here */
+ }
+}
+#endif
+
+
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t oscClk = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: oscClk = 0; break;
+ case 1: oscClk = 500000; break;
+ case 2: oscClk = 800000; break;
+ case 3: oscClk = 1100000; break;
+ case 4: oscClk = 1400000; break;
+ case 5: oscClk = 1600000; break;
+ case 6: oscClk = 1800000; break;
+ case 7: oscClk = 2000000; break;
+ case 8: oscClk = 2200000; break;
+ case 9: oscClk = 2400000; break;
+ case 10: oscClk = 2600000; break;
+ case 11: oscClk = 2700000; break;
+ case 12: oscClk = 2900000; break;
+ case 13: oscClk = 3100000; break;
+ case 14: oscClk = 3200000; break;
+ case 15: oscClk = 3400000; break;
+ }
+ oscClk /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = oscClk;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ */
+void SystemInit (void) {
+#if (CLOCK_SETUP)
+ volatile uint32_t i;
+#endif
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+
+#warning "should not return here, need to fix an issue with PLL lock"
+ return;
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up sysosc */
+ for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
+#endif
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
+ for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ //LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 2000; i++) __NOP(); /* Wait for osc to stabilize */
+#endif
+
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->PDRUNCFG |= (1 << 7); /* Power-down SYSPLL */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->MAINCLKUEN = 0x01;
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif /* Clock Setup via Register */
+
+#if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
+// LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
+// LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+// LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
+// LPC_SYSCON->SYSPLLCLKUEN = 0x01;
+// while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->MAINCLKSEL = SYSPLLCLKSEL_Val; /* Select same as SYSPLL */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->MAINCLKUEN = 0x01;
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = 1;
+
+ setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
+#endif /* Clock Setup via PLL API */
+
+#if (USB_CLOCK_SETUP == 1) /* USB clock is used */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
+
+#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
+ LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->USBPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
+ while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+
+ LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
+#endif
+
+ LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
+ LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
+
+#else /* USB clock is not used */
+ LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
+ LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
+#endif
+
+#endif /* Clock Setup */
+
+ /* System clock to the IOCON needs to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.h Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_LPC11U6x.h
+ * @brief CMSIS Cortex-M3 Device System Header File for
+ * NXP LPC11U6x Device Series
+ * @version V1.00
+ * @date 19. July 2013
+ *
+ * @note
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC11U6x_H
+#define __SYSTEM_LPC11U6x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC11U6x_H */
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x.h Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x.h Tue Apr 29 11:15:07 2014 +0100
@@ -147,6 +147,10 @@
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif
+
/**
* @brief STM32F10x Standard Peripheral Library version number
*/
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.h Mon Apr 28 18:15:06 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.h Tue Apr 29 11:15:07 2014 +0100 @@ -94,6 +94,8 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + /** * @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/PeripheralNames.h Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_USART0_BASE,
+ UART_1 = (int)LPC_USART1_BASE,
+ UART_2 = (int)LPC_USART2_BASE,
+ UART_3 = (int)LPC_USART3_BASE,
+ UART_4 = (int)LPC_USART4_BASE,
+} UARTName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7,
+ ADC0_8,
+ ADC0_9,
+ ADC0_10,
+ ADC0_11,
+ ADC1_0,
+ ADC1_1,
+ ADC1_2,
+ ADC1_3,
+ ADC1_4,
+ ADC1_5,
+ ADC1_6,
+ ADC1_7,
+ ADC1_8,
+ ADC1_9,
+ ADC1_10,
+ ADC1_11,
+} ADCName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C0_BASE,
+ I2C_1 = (int)LPC_I2C1_BASE
+} I2CName;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/PinNames.h Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,181 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2014 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 16
+#define PIN_SHIFT 9
+
+typedef enum {
+ // LPC11U68 Pin Names (PORT[19:16] + PIN[15:9] + IOCON offset[8:0])
+
+ P0_0 = (0 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x000,
+ P0_1 = (0 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x004,
+ P0_2 = (0 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x008,
+ P0_3 = (0 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x00C,
+ P0_4 = (0 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x010,
+ P0_5 = (0 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x014,
+ P0_6 = (0 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x018,
+ P0_7 = (0 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x01C,
+ P0_8 = (0 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x020,
+ P0_9 = (0 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x024,
+ P0_10= (0 << PORT_SHIFT) | (10<< PIN_SHIFT) | 0x028,
+ P0_11= (0 << PORT_SHIFT) | (11<< PIN_SHIFT) | 0x02C,
+ P0_12= (0 << PORT_SHIFT) | (12<< PIN_SHIFT) | 0x030,
+ P0_13= (0 << PORT_SHIFT) | (13<< PIN_SHIFT) | 0x034,
+ P0_14= (0 << PORT_SHIFT) | (14<< PIN_SHIFT) | 0x038,
+ P0_15= (0 << PORT_SHIFT) | (15<< PIN_SHIFT) | 0x03C,
+ P0_16= (0 << PORT_SHIFT) | (16<< PIN_SHIFT) | 0x040,
+ P0_17= (0 << PORT_SHIFT) | (17<< PIN_SHIFT) | 0x044,
+ P0_18= (0 << PORT_SHIFT) | (18<< PIN_SHIFT) | 0x048,
+ P0_19= (0 << PORT_SHIFT) | (19<< PIN_SHIFT) | 0x04C,
+ P0_20= (0 << PORT_SHIFT) | (20<< PIN_SHIFT) | 0x050,
+ P0_21= (0 << PORT_SHIFT) | (21<< PIN_SHIFT) | 0x054,
+ P0_22= (0 << PORT_SHIFT) | (22<< PIN_SHIFT) | 0x058,
+ P0_23= (0 << PORT_SHIFT) | (23<< PIN_SHIFT) | 0x05C,
+
+ P1_0 = (1 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x060,
+ P1_1 = (1 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x064,
+ P1_2 = (1 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x068,
+ P1_3 = (1 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x06C,
+ P1_4 = (1 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x070,
+ P1_5 = (1 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x074,
+ P1_6 = (1 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x078,
+ P1_7 = (1 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x07C,
+ P1_8 = (1 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x080,
+ P1_9 = (1 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x084,
+ P1_10= (1 << PORT_SHIFT) | (10<< PIN_SHIFT) | 0x088,
+ P1_11= (1 << PORT_SHIFT) | (11<< PIN_SHIFT) | 0x08C,
+ P1_12= (1 << PORT_SHIFT) | (12<< PIN_SHIFT) | 0x090,
+ P1_13= (1 << PORT_SHIFT) | (13<< PIN_SHIFT) | 0x094,
+ P1_14= (1 << PORT_SHIFT) | (14<< PIN_SHIFT) | 0x098,
+ P1_15= (1 << PORT_SHIFT) | (15<< PIN_SHIFT) | 0x09C,
+ P1_16= (1 << PORT_SHIFT) | (16<< PIN_SHIFT) | 0x0A0,
+ P1_17= (1 << PORT_SHIFT) | (17<< PIN_SHIFT) | 0x0A4,
+ P1_18= (1 << PORT_SHIFT) | (18<< PIN_SHIFT) | 0x0A8,
+ P1_19= (1 << PORT_SHIFT) | (19<< PIN_SHIFT) | 0x0AC,
+ P1_20= (1 << PORT_SHIFT) | (20<< PIN_SHIFT) | 0x0B0,
+ P1_21= (1 << PORT_SHIFT) | (21<< PIN_SHIFT) | 0x0B4,
+ P1_22= (1 << PORT_SHIFT) | (22<< PIN_SHIFT) | 0x0B8,
+ P1_23= (1 << PORT_SHIFT) | (23<< PIN_SHIFT) | 0x0BC,
+ P1_24= (1 << PORT_SHIFT) | (24<< PIN_SHIFT) | 0x0C0,
+ P1_25= (1 << PORT_SHIFT) | (25<< PIN_SHIFT) | 0x0C4,
+ P1_26= (1 << PORT_SHIFT) | (26<< PIN_SHIFT) | 0x0C8,
+ P1_27= (1 << PORT_SHIFT) | (27<< PIN_SHIFT) | 0x0CC,
+ P1_28= (1 << PORT_SHIFT) | (28<< PIN_SHIFT) | 0x0D0,
+ P1_29= (1 << PORT_SHIFT) | (29<< PIN_SHIFT) | 0x0D4,
+ P1_30= (1 << PORT_SHIFT) | (30<< PIN_SHIFT) | 0x0D8,
+ P1_31= (1 << PORT_SHIFT) | (31<< PIN_SHIFT) | 0x0DC,
+
+ P2_0 = (2 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x0F0,
+ P2_1 = (2 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x0F4,
+ P2_2 = (2 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x0FC,
+ P2_3 = (2 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x100,
+ P2_4 = (2 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x104,
+ P2_5 = (2 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x108,
+ P2_6 = (2 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x10C,
+ P2_7 = (2 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x110,
+ P2_8 = (2 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x114,
+ P2_9 = (2 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x118,
+ P2_10= (2 << PORT_SHIFT) | (10<< PIN_SHIFT) | 0x11C,
+ P2_11= (2 << PORT_SHIFT) | (11<< PIN_SHIFT) | 0x120,
+ P2_12= (2 << PORT_SHIFT) | (12<< PIN_SHIFT) | 0x124,
+ P2_13= (2 << PORT_SHIFT) | (13<< PIN_SHIFT) | 0x128,
+ P2_14= (2 << PORT_SHIFT) | (14<< PIN_SHIFT) | 0x12C,
+ P2_15= (2 << PORT_SHIFT) | (15<< PIN_SHIFT) | 0x130,
+ P2_16= (2 << PORT_SHIFT) | (16<< PIN_SHIFT) | 0x134,
+ P2_17= (2 << PORT_SHIFT) | (17<< PIN_SHIFT) | 0x138,
+ P2_18= (2 << PORT_SHIFT) | (18<< PIN_SHIFT) | 0x13C,
+ P2_19= (2 << PORT_SHIFT) | (19<< PIN_SHIFT) | 0x140,
+ P2_20= (2 << PORT_SHIFT) | (20<< PIN_SHIFT) | 0x144,
+ P2_21= (2 << PORT_SHIFT) | (21<< PIN_SHIFT) | 0x148,
+ P2_22= (2 << PORT_SHIFT) | (22<< PIN_SHIFT) | 0x14C,
+ P2_23= (2 << PORT_SHIFT) | (23<< PIN_SHIFT) | 0x150,
+
+ LED_RED = P2_17,
+ LED_GREEN = P2_16,
+ LED_BLUE = P2_18,
+
+ // mbed original LED naming
+ LED1 = LED_BLUE,
+ LED2 = LED_GREEN,
+ LED3 = LED_RED,
+ LED4 = LED_RED,
+
+ // Serial to USB pins
+ USBTX = P0_19,
+ USBRX = P0_18,
+
+ // Arduino Shield Receptacles Names
+ D0 = P0_18,
+ D1 = P0_19,
+ D2 = P1_18,
+ D3 = P1_24,
+ D4 = P1_19,
+ D5 = P1_26,
+ D6 = P1_27,
+ D7 = P1_25,
+ D8 = P1_28,
+ D9 = P2_3,
+ D10= P0_2,
+ D11= P0_9,
+ D12= P0_8,
+ D13= P1_29,
+ D14= P0_5,
+ D15= P0_4,
+
+ A0 = P1_9,
+ A1 = P0_14,
+ A2 = P0_13,
+ A3 = P0_12,
+ A4 = P0_5, // same port as SDA
+ A5 = P0_4, // same port as SCL
+ SDA= P0_5, // same port as A4
+ SCL= P0_4, // same port as A5
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/PortNames.h Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2014 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1,
+ Port2 = 2
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/device.h Tue Apr 29 11:15:07 2014 +0100 @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2014 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 0 +#define DEVICE_PORTOUT 0 +#define DEVICE_PORTINOUT 0 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 0 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 0 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 0 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2014 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+static int gpio_enabled = 0;
+
+static void gpio_enable(void) {
+ gpio_enabled = 1;
+
+ /* Enable AHB clock to the GPIO and IOCON domain. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 16) | (1 << 6));
+}
+
+uint32_t gpio_set(PinName pin) {
+
+ if (!gpio_enabled)
+ gpio_enable();
+
+ return (1UL << ((int)pin >> PIN_SHIFT & 0x1F));
+}
+
+void gpio_init(gpio_t *obj, PinName pin) {
+ if(pin == NC) return;
+
+ obj->pin = pin;
+ obj->mask = gpio_set(pin);
+
+ unsigned int port = (unsigned int)(pin >> PORT_SHIFT);
+
+ obj->reg_set = &LPC_GPIO_PORT->SET[port];
+ obj->reg_clr = &LPC_GPIO_PORT->CLR[port];
+ obj->reg_in = &LPC_GPIO_PORT->PIN[port];
+ obj->reg_dir = &LPC_GPIO_PORT->DIR[port];
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+ switch (direction) {
+ case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+ case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,143 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "error.h"
+
+#if DEVICE_INTERRUPTIN
+
+#define CHANNEL_NUM 8
+#define LPC_GPIO_X LPC_PINT
+#define PININT_IRQ PIN_INT0_IRQn
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static inline void handle_interrupt_in(uint32_t channel) {
+ uint32_t ch_bit = (1 << channel);
+ // Return immediately if:
+ // * The interrupt was already served
+ // * There is no user handler
+ // * It is a level interrupt, not an edge interrupt
+ if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
+ (channel_ids[channel] == 0 ) ||
+ (LPC_GPIO_X->ISEL & ch_bit ) ) return;
+
+ if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
+ irq_handler(channel_ids[channel], IRQ_RISE);
+ LPC_GPIO_X->RISE = ch_bit;
+ }
+ if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
+ irq_handler(channel_ids[channel], IRQ_FALL);
+ LPC_GPIO_X->FALL = ch_bit;
+ }
+ LPC_GPIO_X->IST = ch_bit;
+}
+
+void gpio_irq0(void) {handle_interrupt_in(0);}
+void gpio_irq1(void) {handle_interrupt_in(1);}
+void gpio_irq2(void) {handle_interrupt_in(2);}
+void gpio_irq3(void) {handle_interrupt_in(3);}
+void gpio_irq4(void) {handle_interrupt_in(4);}
+void gpio_irq5(void) {handle_interrupt_in(5);}
+void gpio_irq6(void) {handle_interrupt_in(6);}
+void gpio_irq7(void) {handle_interrupt_in(7);}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+ // PINT only supprt PIO0_*, PIO1_* and from PIO2_0 to PIO0_7 interrupt
+ if (pin >= P2_8) return -1;
+
+ irq_handler = handler;
+
+ int found_free_channel = 0;
+ int i = 0;
+ for (i=0; i<CHANNEL_NUM; i++) {
+ if (channel_ids[i] == 0) {
+ channel_ids[i] = id;
+ obj->ch = i;
+ found_free_channel = 1;
+ break;
+ }
+ }
+ if (!found_free_channel) return -1;
+
+ /* Enable AHB clock to the PIN, GPIO and IOCON domain. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 19) | (1 << 16) | (1 << 7));
+
+ LPC_SYSCON->PINTSEL[obj->ch] = ((((pin >> PORT_SHIFT) & 0x3) * 24) + ((pin >> PIN_SHIFT) & 0x1F));
+
+ // Interrupt Wake-Up Enable
+ LPC_SYSCON->STARTERP0 |= (1 << obj->ch);
+
+ LPC_GPIO_PORT->DIR[(pin >> PORT_SHIFT) & 0x3] &= ~(1 << ((pin >> PIN_SHIFT) & 0x1F));
+
+ void (*channels_irq)(void) = NULL;
+ switch (obj->ch) {
+ case 0: channels_irq = &gpio_irq0; break;
+ case 1: channels_irq = &gpio_irq1; break;
+ case 2: channels_irq = &gpio_irq2; break;
+ case 3: channels_irq = &gpio_irq3; break;
+ case 4: channels_irq = &gpio_irq4; break;
+ case 5: channels_irq = &gpio_irq5; break;
+ case 6: channels_irq = &gpio_irq6; break;
+ case 7: channels_irq = &gpio_irq7; break;
+ }
+ NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
+ NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+ channel_ids[obj->ch] = 0;
+ LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+ unsigned int ch_bit = (1 << obj->ch);
+
+ // Clear interrupt
+ if (!(LPC_GPIO_X->ISEL & ch_bit))
+ LPC_GPIO_X->IST = ch_bit;
+
+ // Edge trigger
+ LPC_GPIO_X->ISEL &= ~ch_bit;
+ if (event == IRQ_RISE) {
+ if (enable) {
+ LPC_GPIO_X->IENR |= ch_bit;
+ } else {
+ LPC_GPIO_X->IENR &= ~ch_bit;
+ }
+ } else {
+ if (enable) {
+ LPC_GPIO_X->IENF |= ch_bit;
+ } else {
+ LPC_GPIO_X->IENF &= ~ch_bit;
+ }
+ }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj) {
+ NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+}
+
+void gpio_irq_disable(gpio_irq_t *obj) {
+ NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,400 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#if DEVICE_I2C
+
+static const PinMap PinMap_I2C_SDA[] = {
+ {P0_5 , I2C_0, 1},
+ {P1_3 , I2C_1, 3},
+ {P1_14, I2C_1, 1},
+ {P1_24, I2C_1, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+ {P0_4 , I2C_0, 1},
+ {P0_7 , I2C_1, 3},
+ {P1_11, I2C_1, 1},
+ {P1_30, I2C_1, 1},
+ {NC , NC, 0}
+};
+
+#define I2C_CONSET(x) (x->i2c->CONSET)
+#define I2C_CONCLR(x) (x->i2c->CONCLR)
+#define I2C_STAT(x) (x->i2c->STAT)
+#define I2C_DAT(x) (x->i2c->DAT)
+#define I2C_SCLL(x, val) (x->i2c->SCLL = val)
+#define I2C_SCLH(x, val) (x->i2c->SCLH = val)
+
+#warning [TODO] just copied from LPC11UXX code, need to check
+static const uint32_t I2C_addr_offset[2][4] = {
+ {0x0C, 0x20, 0x24, 0x28},
+ {0x30, 0x34, 0x38, 0x3C}
+};
+
+static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+ I2C_CONCLR(obj) = (start << 5)
+ | (stop << 4)
+ | (interrupt << 3)
+ | (acknowledge << 2);
+}
+
+static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+ I2C_CONSET(obj) = (start << 5)
+ | (stop << 4)
+ | (interrupt << 3)
+ | (acknowledge << 2);
+}
+
+// Clear the Serial Interrupt (SI)
+static inline void i2c_clear_SI(i2c_t *obj) {
+ i2c_conclr(obj, 0, 0, 1, 0);
+}
+
+static inline int i2c_status(i2c_t *obj) {
+ return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+ volatile int timeout = 0;
+ while (!(I2C_CONSET(obj) & (1 << 3))) {
+ timeout++;
+ if (timeout > 100000) return -1;
+ }
+ return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+ I2C_CONSET(obj) = 0x40;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+ LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 5) | (1 << 25));
+ LPC_SYSCON->PRESETCTRL |= ((1 << 1) | (1 << 3));
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+ // determine the SPI to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ obj->i2c = (LPC_I2C0_Type *)pinmap_merge(i2c_sda, i2c_scl);
+
+ if ((int)obj->i2c == NC) {
+ error("I2C pin mapping failed");
+ }
+
+ // enable power
+ i2c_power_enable(obj);
+
+ // set default frequency at 100k
+ i2c_frequency(obj, 100000);
+ i2c_conclr(obj, 1, 1, 1, 1);
+ i2c_interface_enable(obj);
+
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+}
+
+inline int i2c_start(i2c_t *obj) {
+ int status = 0;
+ // 8.1 Before master mode can be entered, I2CON must be initialised to:
+ // - I2EN STA STO SI AA - -
+ // - 1 0 0 0 x - -
+ // if AA = 0, it can't enter slave mode
+ i2c_conclr(obj, 1, 1, 1, 1);
+
+ // The master mode may now be entered by setting the STA bit
+ // this will generate a start condition when the bus becomes free
+ i2c_conset(obj, 1, 0, 0, 1);
+
+ i2c_wait_SI(obj);
+ status = i2c_status(obj);
+
+ // Clear start bit now transmitted, and interrupt bit
+ i2c_conclr(obj, 1, 0, 0, 0);
+ return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+ int timeout = 0;
+
+ // write the stop bit
+ i2c_conset(obj, 0, 1, 0, 0);
+ i2c_clear_SI(obj);
+
+ // wait for STO bit to reset
+ while(I2C_CONSET(obj) & (1 << 4)) {
+ timeout ++;
+ if (timeout > 100000) return 1;
+ }
+
+ return 0;
+}
+
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+ // write the data
+ I2C_DAT(obj) = value;
+
+ // clear SI to init a send
+ i2c_clear_SI(obj);
+
+ // wait and return status
+ i2c_wait_SI(obj);
+ return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+ // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
+ if (last) {
+ i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
+ } else {
+ i2c_conset(obj, 0, 0, 0, 1); // send a ACK
+ }
+
+ // accept byte
+ i2c_clear_SI(obj);
+
+ // wait for it to arrive
+ i2c_wait_SI(obj);
+
+ // return the data
+ return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+ // No peripheral clock divider on the M0
+#warning "[TODO] This should be fixed to handle system core clock correctly."
+ uint32_t PCLK = 12000000; //SystemCoreClock;
+
+ uint32_t pulse = PCLK / (hz * 2);
+
+ // I2C Rate
+ I2C_SCLL(obj, pulse);
+ I2C_SCLH(obj, pulse);
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+// 1) it can not obtain the bus
+// 2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
+// which basically turns it in to a 2)
+// 2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ int count, status;
+
+ status = i2c_start(obj);
+
+ if ((status != 0x10) && (status != 0x08)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ status = i2c_do_write(obj, (address | 0x01), 1);
+ if (status != 0x40) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ // Read in all except last byte
+ for (count = 0; count < (length - 1); count++) {
+ int value = i2c_do_read(obj, 0);
+ status = i2c_status(obj);
+ if (status != 0x50) {
+ i2c_stop(obj);
+ return count;
+ }
+ data[count] = (char) value;
+ }
+
+ // read in last byte
+ int value = i2c_do_read(obj, 1);
+ status = i2c_status(obj);
+ if (status != 0x58) {
+ i2c_stop(obj);
+ return length - 1;
+ }
+
+ data[count] = (char) value;
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ int i, status;
+
+ status = i2c_start(obj);
+
+ if ((status != 0x10) && (status != 0x08)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ status = i2c_do_write(obj, (address & 0xFE), 1);
+ if (status != 0x18) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ for (i=0; i<length; i++) {
+ status = i2c_do_write(obj, data[i], 0);
+ if(status != 0x28) {
+ i2c_stop(obj);
+ return i;
+ }
+ }
+
+ // clearing the serial interrupt here might cause an unintended rewrite of the last byte
+ // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
+ // i2c_clear_SI(obj);
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+ i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+ return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+ int ack;
+ int status = i2c_do_write(obj, (data & 0xFF), 0);
+
+ switch(status) {
+ case 0x18: case 0x28: // Master transmit ACKs
+ ack = 1;
+ break;
+ case 0x40: // Master receive address transmitted ACK
+ ack = 1;
+ break;
+ case 0xB8: // Slave transmit ACK
+ ack = 1;
+ break;
+ default:
+ ack = 0;
+ break;
+ }
+
+ return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+ if (enable_slave != 0) {
+ i2c_conclr(obj, 1, 1, 1, 0);
+ i2c_conset(obj, 0, 0, 0, 1);
+ } else {
+ i2c_conclr(obj, 1, 1, 1, 1);
+ }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+ int status;
+ int retval;
+
+ status = i2c_status(obj);
+ switch(status) {
+ case 0x60: retval = 3; break;
+ case 0x70: retval = 2; break;
+ case 0xA8: retval = 1; break;
+ default : retval = 0; break;
+ }
+
+ return(retval);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ int count = 0;
+ int status;
+
+ do {
+ i2c_clear_SI(obj);
+ i2c_wait_SI(obj);
+ status = i2c_status(obj);
+ if((status == 0x80) || (status == 0x90)) {
+ data[count] = I2C_DAT(obj) & 0xFF;
+ }
+ count++;
+ } while (((status == 0x80) || (status == 0x90) ||
+ (status == 0x060) || (status == 0x70)) && (count < length));
+
+ if(status != 0xA0) {
+ i2c_stop(obj);
+ }
+
+ i2c_clear_SI(obj);
+
+ return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ int count = 0;
+ int status;
+
+ if(length <= 0) {
+ return(0);
+ }
+
+ do {
+ status = i2c_do_write(obj, data[count], 0);
+ count++;
+ } while ((count < length) && (status == 0xB8));
+
+ if((status != 0xC0) && (status != 0xC8)) {
+ i2c_stop(obj);
+ }
+
+ i2c_clear_SI(obj);
+
+ return(count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+ uint32_t addr;
+
+ if ((idx >= 0) && (idx <= 3)) {
+ addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
+ *((uint32_t *) addr) = address & 0xFF;
+ }
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/objects.h Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_INTERRUPTIN
+struct gpio_irq_s {
+ uint32_t ch;
+};
+#endif
+
+#if DEVICE_PWMOUT
+struct pwmout_s {
+ LPC_SCT0_Type* pwm;
+ uint32_t pwm_ch;
+};
+#endif
+
+#if DEVICE_SERIAL
+struct serial_s {
+ LPC_USART0_Type *uart;
+ unsigned char index;
+};
+#endif
+
+#if DEVICE_ANALOGIN
+struct analogin_s {
+ ADCName adc;
+};
+#endif
+
+#if DEVICE_ANALOGOUT
+struct dac_s {
+ DACName dac;
+};
+#endif
+
+#if DEVICE_I2C
+struct i2c_s {
+ LPC_I2C0_Type *i2c;
+};
+#endif
+
+#if DEVICE_SPI
+struct spi_s {
+ LPC_SSP0_Type *spi;
+ unsigned char spi_n;
+};
+#endif
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pinmap.c Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "error.h"
+
+void pin_function(PinName pin, int function) {
+ if (pin == (uint32_t)NC)
+ {
+ return;
+ }
+
+ __IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin & 0x1FF));
+
+ // pin function bits: [2:0] -> 111 = (0x7)
+ *reg = (*reg & ~0x7) | (function & 0x7);
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+ if (pin == (uint32_t)NC)
+ {
+ return;
+ }
+
+ if ((pin == P0_4) || (pin == P0_5)) {
+ // The true open-drain pins PIO0_4 and PIO0_5 can be configured for different I2C-bus speeds.
+ return;
+ }
+
+ __IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin & 0x1FF));
+
+ if (mode == OpenDrain) {
+ *reg |= (1 << 10);
+ } else {
+ uint32_t tmp = *reg;
+ tmp &= ~(0x3 << 3);
+ tmp |= (mode & 0x3) << 3;
+ *reg = tmp;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/serial_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,352 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#if DEVICE_SERIAL
+#warning "[TODO] support from UART_1 to UART_4"
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+
+#define UART_NUM 5
+
+static const PinMap PinMap_UART_TX[] = {
+ {P0_19, UART_0, 1},
+ {P1_18, UART_0, 2},
+ {P1_27, UART_0, 2},
+ {P1_18, UART_1, 2},
+ {P1_0 , UART_2, 3},
+ {P1_23, UART_2, 3},
+ {P2_4 , UART_3, 1},
+ {P2_12, UART_4, 1},
+ { NC , NC , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+ {P0_18, UART_0, 1},
+ {P1_17, UART_0, 2},
+ {P1_26, UART_0, 2},
+ {P1_2 , UART_1, 3},
+ {P0_20, UART_2, 2},
+ {P1_6 , UART_2, 2},
+ {P2_3 , UART_3, 1},
+ {P2_11, UART_4, 1},
+ {NC , NC , 0}
+};
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+ int is_stdio_uart = 0;
+
+ // determine the UART to use
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+ UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+ if ((int)uart == NC) {
+ error("Serial pinout mapping failed");
+ }
+
+ obj->uart = (LPC_USART0_Type *)uart;
+ LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<12) | (1<<20) | (1<<21) | (1<<22));
+
+ // [TODO] Consider more elegant approach
+ // disconnect USBTX/RX mapping mux, for case when switching ports
+#ifdef USBTX
+ pin_function(USBTX, 0);
+ pin_function(USBRX, 0);
+#endif
+
+ // enable fifos and default rx trigger level
+ obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
+ | 0 << 1 // Rx Fifo Clear
+ | 0 << 2 // Tx Fifo Clear
+ | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
+
+ // disable irqs
+ obj->uart->IER = 0 << 0 // Rx Data available irq enable
+ | 0 << 1 // Tx Fifo empty irq enable
+ | 0 << 2; // Rx Line Status irq enable
+
+ // set default baud rate and format
+ serial_baud (obj, 9600);
+ serial_format(obj, 8, ParityNone, 1);
+
+ // pinout the chosen uart
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ // set rx/tx pins in PullUp mode
+ pin_mode(tx, PullUp);
+ pin_mode(rx, PullUp);
+
+ switch (uart) {
+ case UART_0: obj->index = 0; break;
+ case UART_1: obj->index = 1; break;
+ case UART_2: obj->index = 2; break;
+ case UART_3: obj->index = 3; break;
+ case UART_4: obj->index = 4; break;
+ }
+
+ is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+
+ if (is_stdio_uart) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj) {
+ serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+ LPC_SYSCON->USART0CLKDIV = 0x1;
+#warning "[TODO] This should be fixed to handle system core clock correctly."
+ uint32_t PCLK = 12000000; //SystemCoreClock;
+ // First we check to see if the basic divide with no DivAddVal/MulVal
+ // ratio gives us an integer result. If it does, we set DivAddVal = 0,
+ // MulVal = 1. Otherwise, we search the valid ratio value range to find
+ // the closest match. This could be more elegant, using search methods
+ // and/or lookup tables, but the brute force method is not that much
+ // slower, and is more maintainable.
+ uint16_t DL = PCLK / (16 * baudrate);
+
+ uint8_t DivAddVal = 0;
+ uint8_t MulVal = 1;
+ int hit = 0;
+ uint16_t dlv;
+ uint8_t mv, dav;
+ if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
+ int err_best = baudrate, b;
+ for (mv = 1; mv < 16 && !hit; mv++)
+ {
+ for (dav = 0; dav < mv; dav++)
+ {
+ // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
+ // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
+ // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
+ // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
+ // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
+
+ if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
+ dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
+ else // 2 bits headroom, use more precision
+ dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
+
+ // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
+ if (dlv == 0)
+ dlv = 1;
+
+ // datasheet says if dav > 0 then DL must be >= 2
+ if ((dav > 0) && (dlv < 2))
+ dlv = 2;
+
+ // integer rearrangement of the baudrate equation (with rounding)
+ b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
+
+ // check to see how we went
+ b = abs(b - baudrate);
+ if (b < err_best)
+ {
+ err_best = b;
+
+ DL = dlv;
+ MulVal = mv;
+ DivAddVal = dav;
+
+ if (b == baudrate)
+ {
+ hit = 1;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ // set LCR[DLAB] to enable writing to divider registers
+ obj->uart->LCR |= (1 << 7);
+
+ // set divider values
+ obj->uart->DLM = (DL >> 8) & 0xFF;
+ obj->uart->DLL = (DL >> 0) & 0xFF;
+ obj->uart->FDR = (uint32_t) DivAddVal << 0
+ | (uint32_t) MulVal << 4;
+
+ // clear LCR[DLAB]
+ obj->uart->LCR &= ~(1 << 7);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+ // 0: 1 stop bits, 1: 2 stop bits
+ if (stop_bits != 1 && stop_bits != 2) {
+ error("Invalid stop bits specified");
+ }
+ stop_bits -= 1;
+
+ // 0: 5 data bits ... 3: 8 data bits
+ if (data_bits < 5 || data_bits > 8) {
+ error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
+ }
+ data_bits -= 5;
+
+ int parity_enable, parity_select;
+ switch (parity) {
+ case ParityNone: parity_enable = 0; parity_select = 0; break;
+ case ParityOdd : parity_enable = 1; parity_select = 0; break;
+ case ParityEven: parity_enable = 1; parity_select = 1; break;
+ case ParityForced1: parity_enable = 1; parity_select = 2; break;
+ case ParityForced0: parity_enable = 1; parity_select = 3; break;
+ default:
+ error("Invalid serial parity setting");
+ return;
+ }
+
+ obj->uart->LCR = data_bits << 0
+ | stop_bits << 2
+ | parity_enable << 3
+ | parity_select << 4;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index) {
+ // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
+ SerialIrq irq_type;
+ switch (iir) {
+ case 1: irq_type = TxIrq; break;
+ case 2: irq_type = RxIrq; break;
+ default: return;
+ }
+
+ if (serial_irq_ids[index] != 0)
+ irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq()
+{
+ uart_irq((LPC_USART0->IIR >> 1) & 0x7, 0);
+}
+
+void uart1_irq()
+{
+ //uart_irq((LPC_USART4->IIR >> 1) & 0x7, 1);
+}
+
+void uart2_irq()
+{
+ //uart_irq((LPC_USART4->IIR >> 1) & 0x7, 2);
+}
+
+void uart3_irq()
+{
+ //uart_irq((LPC_USART4->IIR >> 1) & 0x7, 3);
+}
+
+void uart4_irq()
+{
+ //uart_irq((LPC_USART4->IIR >> 1) & 0x7, 4);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ switch ((int)obj->uart) {
+ case UART_0: irq_n = USART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+ case UART_1: irq_n = USART1_4_IRQn; vector = (uint32_t)&uart1_irq; break;
+ case UART_2: irq_n = USART2_3_IRQn; vector = (uint32_t)&uart2_irq; break;
+ case UART_3: irq_n = USART2_3_IRQn; vector = (uint32_t)&uart3_irq; break;
+ case UART_4: irq_n = USART1_4_IRQn; vector = (uint32_t)&uart4_irq; break;
+ }
+
+ if (enable) {
+ obj->uart->IER |= (1 << irq);
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+ } else { // disable
+ int all_disabled = 0;
+ SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+
+ obj->uart->IER &= ~(1 << irq);
+ all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
+
+ if (all_disabled)
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+ while (!serial_readable(obj));
+ return obj->uart->RBR;
+}
+
+void serial_putc(serial_t *obj, int c) {
+ while (!serial_writable(obj));
+ obj->uart->THR = c;
+}
+
+int serial_readable(serial_t *obj) {
+ return obj->uart->LSR & 0x01;
+}
+
+int serial_writable(serial_t *obj) {
+ return obj->uart->LSR & 0x20;
+}
+
+void serial_clear(serial_t *obj) {
+ obj->uart->FCR = 1 << 1 // rx FIFO reset
+ | 1 << 2 // tx FIFO reset
+ | 0 << 6; // interrupt depth
+}
+
+void serial_pinout_tx(PinName tx) {
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+ obj->uart->LCR |= (1 << 6);
+}
+
+void serial_break_clear(serial_t *obj) {
+ obj->uart->LCR &= ~(1 << 6);
+}
+
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/spi_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,226 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#if DEVICE_SPI
+
+static const PinMap PinMap_SPI_SCLK[] = {
+ {P0_6 , SPI_0, 0x02},
+ {P1_29, SPI_0, 0x01},
+ {P2_7 , SPI_0, 0x01},
+ {P1_20, SPI_1, 0x02},
+ {P1_27, SPI_1, 0x04},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+ {P0_9 , SPI_0, 0x01},
+ {P1_12, SPI_0, 0x01},
+ {P0_21, SPI_1, 0x02},
+ {P1_22, SPI_1, 0x01},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+ {P0_8 , SPI_0, 0x01},
+ {P1_16, SPI_0, 0x01},
+ {P0_22, SPI_1, 0x03},
+ {P1_21, SPI_1, 0x02},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+ {P0_2 , SPI_0, 0x01},
+ {P1_15, SPI_0, 0x01},
+ {P0_23, SPI_1, 0x04},
+ {P1_23, SPI_1, 0x02},
+ {NC , NC , 0}
+};
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ // determine the SPI to use
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+ obj->spi = (LPC_SSP0_Type*)pinmap_merge(spi_data, spi_cntl);
+
+ if ((int)obj->spi == NC) {
+ error("SPI pinout mapping failed");
+ }
+
+ // enable power and clocking
+ switch ((int)obj->spi) {
+ case SPI_0:
+ LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
+ LPC_SYSCON->SSP0CLKDIV = 0x01;
+ LPC_SYSCON->PRESETCTRL |= 1 << 0;
+ break;
+ case SPI_1:
+ LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
+ LPC_SYSCON->SSP1CLKDIV = 0x01;
+ LPC_SYSCON->PRESETCTRL |= 1 << 2;
+ break;
+ }
+
+ // set default format and frequency
+ if (ssel == NC) {
+ spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
+ } else {
+ spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
+ }
+ spi_frequency(obj, 1000000);
+
+ // enable the ssp channel
+ ssp_enable(obj);
+
+ // pin out the spi pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+ if (ssel != NC) {
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+ ssp_disable(obj);
+
+ if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+ error("SPI format error");
+ }
+
+ int polarity = (mode & 0x2) ? 1 : 0;
+ int phase = (mode & 0x1) ? 1 : 0;
+
+ // set it up
+ int DSS = bits - 1; // DSS (data select size)
+ int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
+ int SPH = (phase) ? 1 : 0; // SPH - clock out phase
+
+ int FRF = 0; // FRF (frame format) = SPI
+ uint32_t tmp = obj->spi->CR0;
+ tmp &= ~(0xFFFF);
+ tmp |= DSS << 0
+ | FRF << 4
+ | SPO << 6
+ | SPH << 7;
+ obj->spi->CR0 = tmp;
+
+ tmp = obj->spi->CR1;
+ tmp &= ~(0xD);
+ tmp |= 0 << 0 // LBM - loop back mode - off
+ | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
+ | 0 << 3; // SOD - slave output disable - na
+ obj->spi->CR1 = tmp;
+
+ ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+ ssp_disable(obj);
+
+ uint32_t PCLK = SystemCoreClock;
+
+ int prescaler;
+
+ for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+ int prescale_hz = PCLK / prescaler;
+
+ // calculate the divider
+ int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+
+ // check we can support the divider
+ if (divider < 256) {
+ // prescaler
+ obj->spi->CPSR = prescaler;
+
+ // divider
+ obj->spi->CR0 &= ~(0xFFFF << 8);
+ obj->spi->CR0 |= (divider - 1) << 8;
+ ssp_enable(obj);
+ return;
+ }
+ }
+ error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+ return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+ return obj->spi->CR1 |= (1 << 1);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+ return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+ return obj->spi->SR & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+ while (!ssp_writeable(obj));
+ obj->spi->DR = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+ while (!ssp_readable(obj));
+ return obj->spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+ return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+ ssp_write(obj, value);
+ return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+ return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+}
+
+int spi_slave_read(spi_t *obj) {
+ return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+ while (ssp_writeable(obj) == 0) ;
+ obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+ return ssp_busy(obj);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/us_ticker.c Tue Apr 29 11:15:07 2014 +0100
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define US_TICKER_TIMER ((LPC_CT32B0_Type *)LPC_CT32B1_BASE)
+#define US_TICKER_TIMER_IRQn CT32B1_IRQn
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+ if (us_ticker_inited) return;
+ us_ticker_inited = 1;
+
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); // Clock CT32B1
+#warning "[TODO] this should read from SystemCoreClock grobal variable."
+ uint32_t PCLK = 12000000;//SystemCoreClock;
+
+ US_TICKER_TIMER->TCR = 0x2; // reset
+
+ uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
+ US_TICKER_TIMER->PR = prescale - 1;
+ US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
+
+ NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+ NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read() {
+ if (!us_ticker_inited)
+ us_ticker_init();
+
+ return US_TICKER_TIMER->TC;
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+ // set match value
+ US_TICKER_TIMER->MR0 = timestamp;
+ // enable match interrupt
+ US_TICKER_TIMER->MCR |= 1;
+}
+
+void us_ticker_disable_interrupt(void) {
+ US_TICKER_TIMER->MCR &= ~1;
+}
+
+void us_ticker_clear_interrupt(void) {
+ US_TICKER_TIMER->IR = 1;
+}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralNames.h Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralNames.h Tue Apr 29 11:15:07 2014 +0100
@@ -41,7 +41,7 @@
} ADCName;
typedef enum {
- UART_1 = (int)USART1_BASE,
+ UART_1 = (int)USART1_BASE,
UART_2 = (int)USART2_BASE,
UART_3 = (int)USART3_BASE
} UARTName;
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/analogin_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/analogin_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -26,13 +26,13 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "analogin_api.h"
-#include "wait_api.h"
#if DEVICE_ANALOGIN
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
+#include "wait_api.h"
static const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN0
@@ -57,15 +57,14 @@
int adc_inited = 0;
void analogin_init(analogin_t *obj, PinName pin) {
-
- ADC_TypeDef *adc;
+ ADC_TypeDef *adc;
ADC_InitTypeDef ADC_InitStructure;
-
+
// Get the peripheral name from the pin and assign it to the object
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
-
+
if (obj->adc == (ADCName)NC) {
- error("ADC pin mapping failed");
+ error("ADC pin mapping failed");
}
// Configure GPIO
@@ -80,12 +79,12 @@
// Get ADC registers structure address
adc = (ADC_TypeDef *)(obj->adc);
-
+
// Enable ADC clock (14 MHz maximum)
// PCLK2 = 64 MHz --> ADC clock = 64/6 = 10.666 MHz
RCC_ADCCLKConfig(RCC_PCLK2_Div6);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
-
+
// Configure ADC
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
@@ -100,87 +99,87 @@
// Calibrate ADC
ADC_ResetCalibration(adc);
- while(ADC_GetResetCalibrationStatus(adc));
+ while (ADC_GetResetCalibrationStatus(adc));
ADC_StartCalibration(adc);
- while(ADC_GetCalibrationStatus(adc));
+ while (ADC_GetCalibrationStatus(adc));
}
}
static inline uint16_t adc_read(analogin_t *obj) {
- // Get ADC registers structure address
- ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc);
- int channel = 0;
-
- // Configure ADC channel
- switch (obj->pin) {
- case PA_0:
- channel = 0;
- break;
- case PA_1:
- channel = 1;
- break;
- case PA_2:
- channel = 2;
- break;
- case PA_3:
- channel = 3;
- break;
- case PA_4:
- channel = 4;
- break;
- case PA_5:
- channel = 5;
- break;
- case PA_6:
- channel = 6;
- break;
- case PA_7:
- channel = 7;
- break;
- case PB_0:
- channel = 8;
- break;
- case PB_1:
- channel = 9;
- break;
- case PC_0:
- channel = 10;
- break;
- case PC_1:
- channel = 11;
- break;
- case PC_2:
- channel = 12;
- break;
- case PC_3:
- channel = 13;
- break;
- case PC_4:
- channel = 14;
- break;
- case PC_5:
- channel = 15;
- break;
- default:
- return 0;
- }
+ // Get ADC registers structure address
+ ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc);
+ int channel = 0;
- ADC_RegularChannelConfig(adc, channel, 1, ADC_SampleTime_7Cycles5);
-
- ADC_SoftwareStartConvCmd(adc, ENABLE); // Start conversion
-
- while(ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion
-
- return(ADC_GetConversionValue(adc)); // Get conversion value
+ // Configure ADC channel
+ switch (obj->pin) {
+ case PA_0:
+ channel = 0;
+ break;
+ case PA_1:
+ channel = 1;
+ break;
+ case PA_2:
+ channel = 2;
+ break;
+ case PA_3:
+ channel = 3;
+ break;
+ case PA_4:
+ channel = 4;
+ break;
+ case PA_5:
+ channel = 5;
+ break;
+ case PA_6:
+ channel = 6;
+ break;
+ case PA_7:
+ channel = 7;
+ break;
+ case PB_0:
+ channel = 8;
+ break;
+ case PB_1:
+ channel = 9;
+ break;
+ case PC_0:
+ channel = 10;
+ break;
+ case PC_1:
+ channel = 11;
+ break;
+ case PC_2:
+ channel = 12;
+ break;
+ case PC_3:
+ channel = 13;
+ break;
+ case PC_4:
+ channel = 14;
+ break;
+ case PC_5:
+ channel = 15;
+ break;
+ default:
+ return 0;
+ }
+
+ ADC_RegularChannelConfig(adc, channel, 1, ADC_SampleTime_7Cycles5);
+
+ ADC_SoftwareStartConvCmd(adc, ENABLE); // Start conversion
+
+ while (ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion
+
+ return (ADC_GetConversionValue(adc)); // Get conversion value
}
uint16_t analogin_read_u16(analogin_t *obj) {
- return(adc_read(obj));
+ return (adc_read(obj));
}
float analogin_read(analogin_t *obj) {
- uint16_t value = adc_read(obj);
- return (float)value * (1.0f / (float)0xFFF); // 12 bits range
+ uint16_t value = adc_read(obj);
+ return (float)value * (1.0f / (float)0xFFF); // 12 bits range
}
#endif
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/device.h Mon Apr 28 18:15:06 2014 +0100 +++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/device.h Tue Apr 29 11:15:07 2014 +0100 @@ -37,15 +37,15 @@ #define DEVICE_INTERRUPTIN 1 #define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 +#define DEVICE_ANALOGOUT 0 // Not present on this device #define DEVICE_SERIAL 1 #define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 +#define DEVICE_I2CSLAVE 0 // Not yet supported #define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 0 +#define DEVICE_SPISLAVE 0 // Not yet supported #define DEVICE_RTC 1 @@ -63,7 +63,7 @@ #define DEVICE_STDIO_MESSAGES 1 -//#define DEVICE_ERROR_RED 0 +#define DEVICE_ERROR_RED 0 #include "objects.h"
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -33,7 +33,7 @@
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-uint32_t gpio_set(PinName pin) {
+uint32_t gpio_set(PinName pin) {
if (pin == NC) return 0;
pin_function(pin, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0));
@@ -45,11 +45,11 @@
if (pin == NC) return;
uint32_t port_index = STM_PORT(pin);
-
+
// Enable GPIO clock
uint32_t gpio_add = Set_GPIO_Clock(port_index);
GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
+
// Fill GPIO object structure for future use
obj->pin = pin;
obj->mask = gpio_set(pin);
@@ -65,8 +65,7 @@
void gpio_dir(gpio_t *obj, PinDirection direction) {
if (direction == PIN_OUTPUT) {
pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_Out_PP, 0));
- }
- else { // PIN_INPUT
+ } else { // PIN_INPUT
pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0));
}
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -29,7 +29,6 @@
*/
#include <stddef.h>
#include "cmsis.h"
-
#include "gpio_irq_api.h"
#include "pinmap.h"
#include "error.h"
@@ -53,30 +52,42 @@
uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]);
// Clear interrupt flag
- if (EXTI_GetITStatus(pin) != RESET)
- {
+ if (EXTI_GetITStatus(pin) != RESET) {
EXTI_ClearITPendingBit(pin);
}
-
+
if (channel_ids[irq_index] == 0) return;
-
+
// Check which edge has generated the irq
if ((gpio->IDR & pin) == 0) {
irq_handler(channel_ids[irq_index], IRQ_FALL);
- }
- else {
+ } else {
irq_handler(channel_ids[irq_index], IRQ_RISE);
}
}
// The irq_index is passed to the function
-static void gpio_irq0(void) {handle_interrupt_in(0);} // EXTI line 0
-static void gpio_irq1(void) {handle_interrupt_in(1);} // EXTI line 1
-static void gpio_irq2(void) {handle_interrupt_in(2);} // EXTI line 2
-static void gpio_irq3(void) {handle_interrupt_in(3);} // EXTI line 3
-static void gpio_irq4(void) {handle_interrupt_in(4);} // EXTI line 4
-static void gpio_irq5(void) {handle_interrupt_in(5);} // EXTI lines 5 to 9
-static void gpio_irq6(void) {handle_interrupt_in(6);} // EXTI lines 10 to 15
+static void gpio_irq0(void) {
+ handle_interrupt_in(0); // EXTI line 0
+}
+static void gpio_irq1(void) {
+ handle_interrupt_in(1); // EXTI line 1
+}
+static void gpio_irq2(void) {
+ handle_interrupt_in(2); // EXTI line 2
+}
+static void gpio_irq3(void) {
+ handle_interrupt_in(3); // EXTI line 3
+}
+static void gpio_irq4(void) {
+ handle_interrupt_in(4); // EXTI line 4
+}
+static void gpio_irq5(void) {
+ handle_interrupt_in(5); // EXTI lines 5 to 9
+}
+static void gpio_irq6(void) {
+ handle_interrupt_in(6); // EXTI lines 10 to 15
+}
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
@@ -143,7 +154,7 @@
// Enable GPIO clock
uint32_t gpio_add = Set_GPIO_Clock(port_index);
-
+
// Enable AFIO clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
@@ -151,13 +162,13 @@
GPIO_EXTILineConfig(port_index, pin_index);
// Configure EXTI line
- EXTI_InitTypeDef EXTI_InitStructure;
+ EXTI_InitTypeDef EXTI_InitStructure;
EXTI_InitStructure.EXTI_Line = (uint32_t)(1 << pin_index);
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
-
+
// Enable and set EXTI interrupt to the lowest priority
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = irq_n;
@@ -165,7 +176,7 @@
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
-
+
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
@@ -176,9 +187,9 @@
channel_ids[irq_index] = id;
channel_gpio[irq_index] = gpio_add;
channel_pin[irq_index] = pin_index;
-
- irq_handler = handler;
-
+
+ irq_handler = handler;
+
return 0;
}
@@ -189,47 +200,44 @@
// Disable EXTI line
EXTI_InitTypeDef EXTI_InitStructure;
EXTI_StructInit(&EXTI_InitStructure);
- EXTI_Init(&EXTI_InitStructure);
+ EXTI_Init(&EXTI_InitStructure);
obj->event = EDGE_NONE;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
EXTI_InitTypeDef EXTI_InitStructure;
-
+
uint32_t pin_index = channel_pin[obj->irq_index];
EXTI_InitStructure.EXTI_Line = (uint32_t)(1 << pin_index);
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-
+
if (event == IRQ_RISE) {
if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
obj->event = EDGE_BOTH;
- }
- else { // NONE or RISE
+ } else { // NONE or RISE
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
obj->event = EDGE_RISE;
}
}
-
+
if (event == IRQ_FALL) {
if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
obj->event = EDGE_BOTH;
- }
- else { // NONE or FALL
+ } else { // NONE or FALL
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
obj->event = EDGE_FALL;
}
}
-
+
if (enable) {
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- }
- else {
+ } else {
EXTI_InitStructure.EXTI_LineCmd = DISABLE;
}
-
+
EXTI_Init(&EXTI_InitStructure);
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h Tue Apr 29 11:15:07 2014 +0100
@@ -50,8 +50,7 @@
static inline void gpio_write(gpio_t *obj, int value) {
if (value) {
*obj->reg_set = obj->mask;
- }
- else {
+ } else {
*obj->reg_clr = obj->mask;
}
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -36,8 +36,8 @@
#include "error.h"
/* Timeout values for flags and events waiting loops. These timeouts are
- not based on accurate values, they just guarantee that the application will
- not remain stuck if the I2C communication is corrupted. */
+ not based on accurate values, they just guarantee that the application will
+ not remain stuck if the I2C communication is corrupted. */
#define FLAG_TIMEOUT ((int)0x1000)
#define LONG_TIMEOUT ((int)0x8000)
@@ -55,19 +55,19 @@
{NC, NC, 0}
};
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
// Determine the I2C to use
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
-
+
if (obj->i2c == (I2CName)NC) {
error("I2C pin mapping failed");
}
// Enable I2C clock
- if (obj->i2c == I2C_1) {
+ if (obj->i2c == I2C_1) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
}
if (obj->i2c == I2C_2) {
@@ -79,21 +79,21 @@
pin_mode(scl, OpenDrain);
pinmap_pinout(sda, PinMap_I2C_SDA);
pin_mode(sda, OpenDrain);
-
+
// Reset to clear pending flags if any
i2c_reset(obj);
-
+
// I2C configuration
- i2c_frequency(obj, 100000); // 100 kHz per default
+ i2c_frequency(obj, 100000); // 100 kHz per default
}
void i2c_frequency(i2c_t *obj, int hz) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
I2C_InitTypeDef I2C_InitStructure;
-
+
if ((hz != 0) && (hz <= 400000)) {
I2C_DeInit(i2c);
-
+
// I2C configuration
I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
@@ -102,7 +102,7 @@
I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
I2C_InitStructure.I2C_ClockSpeed = hz;
I2C_Init(i2c, &I2C_InitStructure);
-
+
I2C_Cmd(i2c, ENABLE);
}
}
@@ -110,30 +110,29 @@
inline int i2c_start(i2c_t *obj) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
int timeout;
-
+
I2C_ClearFlag(i2c, I2C_FLAG_AF); // Clear Acknowledge failure flag
-
+
// Generate the START condition
- I2C_GenerateSTART(i2c, ENABLE);
-
+ I2C_GenerateSTART(i2c, ENABLE);
+
// Wait the START condition has been correctly sent
timeout = FLAG_TIMEOUT;
- //while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_MODE_SELECT) == ERROR) {
while (I2C_GetFlagStatus(i2c, I2C_FLAG_SB) == RESET) {
timeout--;
if (timeout == 0) {
return 1;
}
}
-
+
return 0;
}
inline int i2c_stop(i2c_t *obj) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-
+
I2C_GenerateSTOP(i2c, ENABLE);
-
+
return 0;
}
@@ -142,24 +141,13 @@
int timeout;
int count;
int value;
-
+
if (length == 0) return 0;
-/*
- // Wait until the bus is not busy anymore
- timeout = LONG_TIMEOUT;
- while (I2C_GetFlagStatus(i2c, I2C_FLAG_BUSY) == SET) {
- timeout--;
- if (timeout == 0) {
- return 0;
- }
- }
-*/
-
i2c_start(obj);
// Send slave address for read
- I2C_Send7bitAddress(i2c, address, I2C_Direction_Receiver);
+ I2C_Send7bitAddress(i2c, address, I2C_Direction_Receiver);
// Wait address is acknowledged
timeout = FLAG_TIMEOUT;
@@ -169,13 +157,13 @@
return 0;
}
}
-
+
// Read all bytes except last one
for (count = 0; count < (length - 1); count++) {
value = i2c_byte_read(obj, 0);
data[count] = (char)value;
}
-
+
// If not repeated start, send stop.
// Warning: must be done BEFORE the data is read.
if (stop) {
@@ -185,7 +173,7 @@
// Read the last byte
value = i2c_byte_read(obj, 1);
data[count] = (char)value;
-
+
return length;
}
@@ -193,23 +181,12 @@
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
int timeout;
int count;
-
-/*
- // Wait until the bus is not busy anymore
- timeout = LONG_TIMEOUT;
- while (I2C_GetFlagStatus(i2c, I2C_FLAG_BUSY) == SET) {
- timeout--;
- if (timeout == 0) {
- return 0;
- }
- }
-*/
i2c_start(obj);
// Send slave address for write
I2C_Send7bitAddress(i2c, address, I2C_Direction_Transmitter);
-
+
// Wait address is acknowledged
timeout = FLAG_TIMEOUT;
while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) == ERROR) {
@@ -238,7 +215,7 @@
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
uint8_t data;
int timeout;
-
+
if (last) {
// Don't acknowledge the last byte
I2C_AcknowledgeConfig(i2c, DISABLE);
@@ -257,7 +234,7 @@
}
data = I2C_ReceiveData(i2c);
-
+
return (int)data;
}
@@ -268,27 +245,26 @@
I2C_SendData(i2c, (uint8_t)data);
// Wait until the byte is transmitted
- timeout = FLAG_TIMEOUT;
- //while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_BYTE_TRANSMITTED) == ERROR) {
+ timeout = FLAG_TIMEOUT;
while ((I2C_GetFlagStatus(i2c, I2C_FLAG_TXE) == RESET) &&
- (I2C_GetFlagStatus(i2c, I2C_FLAG_BTF) == RESET)) {
+ (I2C_GetFlagStatus(i2c, I2C_FLAG_BTF) == RESET)) {
timeout--;
if (timeout == 0) {
return 0;
}
}
-
+
return 1;
}
void i2c_reset(i2c_t *obj) {
- if (obj->i2c == I2C_1) {
+ if (obj->i2c == I2C_1) {
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
}
if (obj->i2c == I2C_2) {
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
}
}
@@ -297,7 +273,7 @@
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
uint16_t tmpreg;
-
+
// Get the old register value
tmpreg = i2c->OAR1;
// Reset address bits
@@ -319,29 +295,28 @@
#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
int i2c_slave_receive(i2c_t *obj) {
- // TO BE DONE
- return(0);
+ return (0);
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
int count = 0;
-
+
// Read all bytes
for (count = 0; count < length; count++) {
data[count] = i2c_byte_read(obj, 0);
}
-
+
return count;
}
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
int count = 0;
-
+
// Write all bytes
for (count = 0; count < length; count++) {
i2c_byte_write(obj, data[count]);
}
-
+
return count;
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/objects.h Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/objects.h Tue Apr 29 11:15:07 2014 +0100
@@ -48,7 +48,7 @@
struct port_s {
PortName port;
uint32_t mask;
- PinDirection direction;
+ PinDirection direction;
__IO uint32_t *reg_in;
__IO uint32_t *reg_out;
};
@@ -64,7 +64,7 @@
uint32_t baudrate;
uint32_t databits;
uint32_t stopbits;
- uint32_t parity;
+ uint32_t parity;
};
struct spi_s {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c Tue Apr 29 11:15:07 2014 +0100
@@ -34,16 +34,16 @@
// Alternate-function mapping
#define AF_NUM (10)
static const uint32_t AF_mapping[AF_NUM] = {
- 0, // 0 = No AF
- GPIO_Remap_SPI1, // 1
- GPIO_Remap_I2C1, // 2
- GPIO_Remap_USART1, // 3
- GPIO_Remap_USART2, // 4
- GPIO_PartialRemap_USART3, // 5
- GPIO_PartialRemap_TIM1, // 6
- GPIO_PartialRemap_TIM3, // 7
- GPIO_FullRemap_TIM2, // 8
- GPIO_FullRemap_TIM3 // 9
+ 0, // 0 = No AF
+ GPIO_Remap_SPI1, // 1
+ GPIO_Remap_I2C1, // 2
+ GPIO_Remap_USART1, // 3
+ GPIO_Remap_USART2, // 4
+ GPIO_PartialRemap_USART3, // 5
+ GPIO_PartialRemap_TIM1, // 6
+ GPIO_PartialRemap_TIM3, // 7
+ GPIO_FullRemap_TIM2, // 8
+ GPIO_FullRemap_TIM3 // 9
};
// Enable GPIO clock and return GPIO base address
@@ -98,14 +98,14 @@
if ((afnum > 0) && (afnum < AF_NUM)) {
GPIO_PinRemapConfig(AF_mapping[afnum], ENABLE);
}
-
+
// Configure GPIO
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index);
GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)mode;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(gpio, &GPIO_InitStructure);
-
+
// Disconnect JTAG-DP + SW-DP signals.
// Warning: Need to reconnect under reset
if ((pin == PA_13) || (pin == PA_14)) {
@@ -113,7 +113,7 @@
}
if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
- }
+ }
}
/**
@@ -121,7 +121,7 @@
*/
void pin_mode(PinName pin, PinMode mode) {
GPIO_InitTypeDef GPIO_InitStructure;
-
+
if (pin == NC) return;
uint32_t port_index = STM_PORT(pin);
@@ -130,35 +130,34 @@
// Enable GPIO clock
uint32_t gpio_add = Set_GPIO_Clock(port_index);
GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
+
// Configure open-drain and pull-up/down
switch (mode) {
- case PullNone:
- return;
- case PullUp:
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
- break;
- case PullDown:
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
- break;
- case OpenDrain:
- if (pin_index < 8) {
- if ((gpio->CRL & (0x03 << (pin_index * 4))) > 0) { // MODE bits = Output mode
- gpio->CRL |= (0x04 << (pin_index * 4)); // Set open-drain
+ case PullNone:
+ return;
+ case PullUp:
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+ break;
+ case PullDown:
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
+ break;
+ case OpenDrain:
+ if (pin_index < 8) {
+ if ((gpio->CRL & (0x03 << (pin_index * 4))) > 0) { // MODE bits = Output mode
+ gpio->CRL |= (0x04 << (pin_index * 4)); // Set open-drain
+ }
+ } else {
+ if ((gpio->CRH & (0x03 << ((pin_index % 8) * 4))) > 0) { // MODE bits = Output mode
+ gpio->CRH |= (0x04 << ((pin_index % 8) * 4)); // Set open-drain
+ }
}
- }
- else {
- if ((gpio->CRH & (0x03 << ((pin_index % 8) * 4))) > 0) { // MODE bits = Output mode
- gpio->CRH |= (0x04 << ((pin_index % 8) * 4)); // Set open-drain
- }
- }
- return;
- default:
- break;
+ return;
+ default:
+ break;
}
-
+
// Configure GPIO
GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index);
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(gpio, &GPIO_InitStructure);
+ GPIO_Init(gpio, &GPIO_InitStructure);
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/port_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/port_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -28,18 +28,19 @@
*******************************************************************************
*/
#include "port_api.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
#include "pinmap.h"
#include "gpio_api.h"
#include "error.h"
-#if DEVICE_PORTIN || DEVICE_PORTOUT
-
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
// low nibble = pin number
PinName port_pin(PortName port, int pin_n) {
- return (PinName)(pin_n + (port << 4));
+ return (PinName)(pin_n + (port << 4));
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
@@ -52,9 +53,9 @@
// Fill PORT object structure for future use
obj->port = port;
obj->mask = mask;
- obj->direction = dir;
+ obj->direction = dir;
obj->reg_in = &gpio->IDR;
- obj->reg_out = &gpio->ODR;
+ obj->reg_out = &gpio->ODR;
port_dir(obj, dir);
}
@@ -66,16 +67,15 @@
if (obj->mask & (1 << i)) { // If the pin is used
if (dir == PIN_OUTPUT) {
pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_Out_PP, 0));
- }
- else { // PIN_INPUT
+ } else { // PIN_INPUT
pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0));
}
}
- }
+ }
}
void port_mode(port_t *obj, PinMode mode) {
- uint32_t i;
+ uint32_t i;
for (i = 0; i < 16; i++) { // Process all pins
if (obj->mask & (1 << i)) { // If the pin is used
pin_mode(port_pin(obj->port, i), mode);
@@ -90,8 +90,7 @@
int port_read(port_t *obj) {
if (obj->direction == PIN_OUTPUT) {
return (*obj->reg_out & obj->mask);
- }
- else { // PIN_INPUT
+ } else { // PIN_INPUT
return (*obj->reg_in & obj->mask);
}
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pwmout_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pwmout_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -29,6 +29,8 @@
*/
#include "pwmout_api.h"
+#if DEVICE_PWMOUT
+
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
@@ -40,7 +42,7 @@
{PA_3, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM2_CH4 - Default (warning: not connected on D0 per default)
{PA_6, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM3_CH1 - Default
{PA_7, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM3_CH2 - Default
- //{PA_7, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 6)}, // TIM1_CH1N - GPIO_PartialRemap_TIM1
+// {PA_7, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 6)}, // TIM1_CH1N - GPIO_PartialRemap_TIM1
{PA_8, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH1 - Default
{PA_9, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH2 - Default
{PA_10, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH3 - Default
@@ -48,22 +50,22 @@
{PA_15, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 8)}, // TIM2_CH1_ETR - GPIO_FullRemap_TIM2
{PB_0, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM3_CH3 - Default
- //{PB_0, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 6)}, // TIM1_CH2N - GPIO_PartialRemap_TIM1
- {PB_1, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM3_CH4 - Default
- //{PB_1, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 6)}, // TIM1_CH3N - GPIO_PartialRemap_TIM1
+// {PB_0, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 6)}, // TIM1_CH2N - GPIO_PartialRemap_TIM1
+ {PB_1, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM3_CH4 - Default
+// {PB_1, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 6)}, // TIM1_CH3N - GPIO_PartialRemap_TIM1
{PB_3, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 8)}, // TIM2_CH2 - GPIO_FullRemap_TIM2
{PB_4, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 7)}, // TIM3_CH1 - GPIO_PartialRemap_TIM3
{PB_5, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 7)}, // TIM3_CH2 - GPIO_PartialRemap_TIM3
- //{PB_6, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH1 - Default (used by ticker)
- //{PB_7, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH2 - Default (used by ticker)
- //{PB_8, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH3 - Default (used by ticker)
- //{PB_9, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH4 - Default (used by ticker)
+// {PB_6, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH1 - Default (used by ticker)
+// {PB_7, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH2 - Default (used by ticker)
+// {PB_8, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH3 - Default (used by ticker)
+// {PB_9, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH4 - Default (used by ticker)
{PB_10, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 8)}, // TIM2_CH3 - GPIO_FullRemap_TIM2
{PB_11, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 8)}, // TIM2_CH4 - GPIO_FullRemap_TIM2
{PB_13, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH1N - Default
{PB_14, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH2N - Default
{PB_15, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH3N - Default
-
+
{PC_6, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 9)}, // TIM3_CH1 - GPIO_FullRemap_TIM3
{PC_7, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 9)}, // TIM3_CH2 - GPIO_FullRemap_TIM3
{PC_8, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 9)}, // TIM3_CH3 - GPIO_FullRemap_TIM3
@@ -71,27 +73,27 @@
{NC, NC, 0}
};
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin) {
// Get the peripheral name from the pin and assign it to the object
obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
-
+
if (obj->pwm == (PWMName)NC) {
error("PWM pinout mapping failed");
}
-
+
// Enable TIM clock
if (obj->pwm == PWM_1) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
if (obj->pwm == PWM_2) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
if (obj->pwm == PWM_3) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
if (obj->pwm == PWM_4) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
-
+
// Configure GPIO
pinmap_pinout(pin, PinMap_PWM);
-
+
obj->pin = pin;
obj->period = 0;
obj->pulse = 0;
-
+
pwmout_period_us(obj, 20000); // 20 ms per default
}
@@ -103,15 +105,15 @@
void pwmout_write(pwmout_t* obj, float value) {
TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm);
TIM_OCInitTypeDef TIM_OCInitStructure;
-
+
if (value < 0.0) {
value = 0.0;
} else if (value > 1.0) {
value = 1.0;
}
-
+
obj->pulse = (uint32_t)((float)obj->period * value);
-
+
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_Pulse = obj->pulse;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
@@ -126,14 +128,14 @@
case PA_8:
case PA_15:
case PB_4:
- //case PB_6:
+ //case PB_6:
case PC_6:
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable);
TIM_OC1Init(tim, &TIM_OCInitStructure);
break;
// Channels 1N
- //case PA_7:
+ //case PA_7:
case PB_13:
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable);
@@ -145,52 +147,52 @@
case PA_9:
case PB_3:
case PB_5:
- //case PB_7:
+ //case PB_7:
case PC_7:
- TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable);
TIM_OC2Init(tim, &TIM_OCInitStructure);
break;
// Channels 2N
- //case PB_0:
+ //case PB_0:
case PB_14:
- TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
+ TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable);
TIM_OC2Init(tim, &TIM_OCInitStructure);
- break;
- // Channels 3
+ break;
+ // Channels 3
case PA_2:
case PA_10:
case PB_0:
- //case PB_8:
+ //case PB_8:
case PB_10:
case PC_8:
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OC3PreloadConfig(tim, TIM_OCPreload_Enable);
TIM_OC3Init(tim, &TIM_OCInitStructure);
break;
- // Channels 3N
- //case PB_1:
+ // Channels 3N
+ //case PB_1:
case PB_15:
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
TIM_OC3PreloadConfig(tim, TIM_OCPreload_Enable);
TIM_OC3Init(tim, &TIM_OCInitStructure);
- break;
- // Channels 4
+ break;
+ // Channels 4
case PA_3:
case PA_11:
case PB_1:
- //case PB_9:
+ //case PB_9:
case PB_11:
case PC_9:
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OC4PreloadConfig(tim, TIM_OCPreload_Enable);
TIM_OC4Init(tim, &TIM_OCInitStructure);
- break;
+ break;
default:
return;
}
-
+
TIM_CtrlPWMOutputs(tim, ENABLE);
}
@@ -215,20 +217,20 @@
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
float dc = pwmout_read(obj);
- TIM_Cmd(tim, DISABLE);
-
+ TIM_Cmd(tim, DISABLE);
+
obj->period = us;
-
- TIM_TimeBaseStructure.TIM_Period = obj->period - 1;
- TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+
+ TIM_TimeBaseStructure.TIM_Period = obj->period - 1;
+ TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
- TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure);
// Set duty cycle again
pwmout_write(obj, dc);
-
- TIM_ARRPreloadConfig(tim, ENABLE);
+
+ TIM_ARRPreloadConfig(tim, ENABLE);
TIM_Cmd(tim, ENABLE);
}
@@ -244,3 +246,5 @@
float value = (float)us / (float)obj->period;
pwmout_write(obj, value);
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/rtc_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/rtc_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -29,40 +29,60 @@
*/
#include "rtc_api.h"
+#if DEVICE_RTC
+
+#include "wait_api.h"
+
+#define LSE_STARTUP_TIMEOUT ((uint16_t)700) // delay in ms
+
static int rtc_inited = 0;
void rtc_init(void) {
+ uint32_t StartUpCounter = 0;
+ uint32_t LSEStatus = 0;
+ uint32_t rtc_freq = 0;
+
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); // Enable PWR and Backup clock
PWR_BackupAccessCmd(ENABLE); // Allow access to Backup Domain
-
+
BKP_DeInit(); // Reset Backup Domain
-
- // Uncomment these lines if you use the LSE
- // Enable LSE and wait till it's ready
- //RCC_LSEConfig(RCC_LSE_ON);
- //while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) {}
- //RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); // Select LSE as RTC Clock Source
-
- // Uncomment these lines if you use the LSI
- // Enable LSI and wait till it's ready
- RCC_LSICmd(ENABLE);
- while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {}
- RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select LSI as RTC Clock Source
-
- RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock
-
+
+ // Enable LSE clock
+ RCC_LSEConfig(RCC_LSE_ON);
+
+ // Wait till LSE is ready
+ do {
+ LSEStatus = RCC_GetFlagStatus(RCC_FLAG_LSERDY);
+ wait_ms(1);
+ StartUpCounter++;
+ } while ((LSEStatus == 0) && (StartUpCounter <= LSE_STARTUP_TIMEOUT));
+
+ if (StartUpCounter > LSE_STARTUP_TIMEOUT) {
+ // The LSE has not started, use LSI instead.
+ // The RTC Clock may vary due to LSI frequency dispersion.
+ RCC_LSEConfig(RCC_LSE_OFF);
+ RCC_LSICmd(ENABLE); // Enable LSI
+ while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {} // Wait until ready
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select the RTC Clock Source
+ rtc_freq = 40000; // [TODO] To be measured precisely using a timer input capture
+ } else {
+ // The LSE has correctly started
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); // Select the RTC Clock Source
+ rtc_freq = LSE_VALUE;
+ }
+
+ RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock
+
RTC_WaitForSynchro(); // Wait for RTC registers synchronization
-
+
RTC_WaitForLastTask(); // Wait until last write operation on RTC registers has finished
// Set RTC period to 1 sec
- // For LSE: prescaler = RTCCLK/RTC period = 32768Hz/1Hz = 32768
- // For LSI: prescaler = RTCCLK/RTC period = 40000Hz/1Hz = 40000
- RTC_SetPrescaler(39999);
-
+ RTC_SetPrescaler(rtc_freq - 1);
+
RTC_WaitForLastTask(); // Wait until last write operation on RTC registers has finished
-
+
rtc_inited = 1;
}
@@ -84,3 +104,5 @@
RTC_SetCounter(t); // Change the current time
RTC_WaitForLastTask(); // Wait until last write operation on RTC registers has finished
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -28,6 +28,9 @@
*******************************************************************************
*/
#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
@@ -63,7 +66,7 @@
static void init_usart(serial_t *obj) {
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
USART_InitTypeDef USART_InitStructure;
-
+
USART_Cmd(usart, DISABLE);
USART_InitStructure.USART_BaudRate = obj->baudrate;
@@ -73,15 +76,15 @@
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(usart, &USART_InitStructure);
-
+
USART_Cmd(usart, ENABLE);
}
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
// Determine the UART to use (UART_1, UART_2, ...)
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
+
// Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
@@ -91,15 +94,15 @@
// Enable USART clock
if (obj->uart == UART_1) {
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
}
if (obj->uart == UART_2) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
}
if (obj->uart == UART_3) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
}
-
+
// Configure the UART pins
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
@@ -108,7 +111,7 @@
obj->baudrate = 9600;
obj->databits = USART_WordLength_8b;
obj->stopbits = USART_StopBits_1;
- obj->parity = USART_Parity_No;
+ obj->parity = USART_Parity_No;
init_usart(obj);
@@ -116,13 +119,12 @@
if (obj->uart == UART_1) obj->index = 0;
if (obj->uart == UART_2) obj->index = 1;
if (obj->uart == UART_3) obj->index = 2;
-
+
// For stdio management
if (obj->uart == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
-
}
void serial_free(serial_t *obj) {
@@ -137,29 +139,27 @@
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
if (data_bits == 8) {
obj->databits = USART_WordLength_8b;
- }
- else {
+ } else {
obj->databits = USART_WordLength_9b;
}
switch (parity) {
- case ParityOdd:
- case ParityForced0:
- obj->parity = USART_Parity_Odd;
- break;
- case ParityEven:
- case ParityForced1:
- obj->parity = USART_Parity_Even;
- break;
- default: // ParityNone
- obj->parity = USART_Parity_No;
- break;
+ case ParityOdd:
+ case ParityForced0:
+ obj->parity = USART_Parity_Odd;
+ break;
+ case ParityEven:
+ case ParityForced1:
+ obj->parity = USART_Parity_Even;
+ break;
+ default: // ParityNone
+ obj->parity = USART_Parity_No;
+ break;
}
-
+
if (stop_bits == 2) {
obj->stopbits = USART_StopBits_2;
- }
- else {
+ } else {
obj->stopbits = USART_StopBits_1;
}
@@ -205,50 +205,48 @@
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
if (obj->uart == UART_1) {
- irq_n = USART1_IRQn;
- vector = (uint32_t)&uart1_irq;
+ irq_n = USART1_IRQn;
+ vector = (uint32_t)&uart1_irq;
}
-
+
if (obj->uart == UART_2) {
- irq_n = USART2_IRQn;
- vector = (uint32_t)&uart2_irq;
+ irq_n = USART2_IRQn;
+ vector = (uint32_t)&uart2_irq;
}
if (obj->uart == UART_3) {
- irq_n = USART3_IRQn;
- vector = (uint32_t)&uart3_irq;
+ irq_n = USART3_IRQn;
+ vector = (uint32_t)&uart3_irq;
}
-
+
if (enable) {
-
+
if (irq == RxIrq) {
USART_ITConfig(usart, USART_IT_RXNE, ENABLE);
- }
- else { // TxIrq
+ } else { // TxIrq
USART_ITConfig(usart, USART_IT_TC, ENABLE);
- }
-
+ }
+
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
-
+
} else { // disable
-
+
int all_disabled = 0;
-
+
if (irq == RxIrq) {
USART_ITConfig(usart, USART_IT_RXNE, DISABLE);
// Check if TxIrq is disabled too
if ((usart->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
- }
- else { // TxIrq
+ } else { // TxIrq
USART_ITConfig(usart, USART_IT_TXE, DISABLE);
// Check if RxIrq is disabled too
- if ((usart->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
+ if ((usart->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
}
-
+
if (all_disabled) NVIC_DisableIRQ(irq_n);
-
- }
+
+ }
}
/******************************************************************************
@@ -300,3 +298,5 @@
void serial_break_clear(serial_t *obj) {
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/sleep.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/sleep.c Tue Apr 29 11:15:07 2014 +0100
@@ -28,37 +28,37 @@
*******************************************************************************
*/
#include "sleep_api.h"
+
+#if DEVICE_SLEEP
+
#include "cmsis.h"
-// This function is in the system_stm32f10x.c file
-extern void SetSysClock(void);
-
-void sleep(void)
-{
+void sleep(void) {
// Disable us_ticker update interrupt
TIM_ITConfig(TIM1, TIM_IT_Update, DISABLE);
-
+
SCB->SCR = 0; // Normal sleep mode for ARM core
__WFI();
-
+
// Re-enable us_ticker update interrupt
- TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE);
+ TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE);
}
-void deepsleep(void)
-{
+void deepsleep(void) {
// Disable us_ticker update interrupt
TIM_ITConfig(TIM1, TIM_IT_Update, DISABLE);
-
+
// Enable PWR clock
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
-
+
// Request to enter STOP mode with regulator in low power mode
PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
// After wake-up from STOP reconfigure the PLL
SetSysClock();
-
+
// Re-enable us_ticker update interrupt
- TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE);
+ TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE);
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/spi_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/spi_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -72,7 +72,7 @@
SPI_InitStructure.SPI_Mode = obj->mode;
SPI_InitStructure.SPI_NSS = obj->nss;
- SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStructure.SPI_DataSize = obj->bits;
SPI_InitStructure.SPI_CPOL = obj->cpol;
SPI_InitStructure.SPI_CPHA = obj->cpha;
@@ -90,19 +90,19 @@
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
+
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
+
obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-
+
if (obj->spi == (SPIName)NC) {
error("SPI pinout mapping failed");
}
-
+
// Enable SPI clock
if (obj->spi == SPI_1) {
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
}
if (obj->spi == SPI_2) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
@@ -112,18 +112,17 @@
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
+
// Save new values
obj->bits = SPI_DataSize_8b;
obj->cpol = SPI_CPOL_Low;
obj->cpha = SPI_CPHA_1Edge;
obj->br_presc = SPI_BaudRatePrescaler_256;
-
+
if (ssel == NC) { // Master
obj->mode = SPI_Mode_Master;
obj->nss = SPI_NSS_Soft;
- }
- else { // Slave
+ } else { // Slave
pinmap_pinout(ssel, PinMap_SPI_SSEL);
obj->mode = SPI_Mode_Slave;
obj->nss = SPI_NSS_Soft;
@@ -137,43 +136,41 @@
SPI_I2S_DeInit(spi);
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
// Save new values
if (bits == 8) {
obj->bits = SPI_DataSize_8b;
- }
- else {
+ } else {
obj->bits = SPI_DataSize_16b;
}
-
+
switch (mode) {
case 0:
- obj->cpol = SPI_CPOL_Low;
- obj->cpha = SPI_CPHA_1Edge;
- break;
+ obj->cpol = SPI_CPOL_Low;
+ obj->cpha = SPI_CPHA_1Edge;
+ break;
case 1:
- obj->cpol = SPI_CPOL_Low;
- obj->cpha = SPI_CPHA_2Edge;
- break;
+ obj->cpol = SPI_CPOL_Low;
+ obj->cpha = SPI_CPHA_2Edge;
+ break;
case 2:
- obj->cpol = SPI_CPOL_High;
- obj->cpha = SPI_CPHA_1Edge;
- break;
+ obj->cpol = SPI_CPOL_High;
+ obj->cpha = SPI_CPHA_1Edge;
+ break;
default:
- obj->cpol = SPI_CPOL_High;
- obj->cpha = SPI_CPHA_2Edge;
- break;
+ obj->cpol = SPI_CPOL_High;
+ obj->cpha = SPI_CPHA_2Edge;
+ break;
}
-
+
if (slave == 0) {
obj->mode = SPI_Mode_Master;
obj->nss = SPI_NSS_Soft;
- }
- else {
+ } else {
obj->mode = SPI_Mode_Slave;
- obj->nss = SPI_NSS_Hard;
+ obj->nss = SPI_NSS_Hard;
}
-
+
init_spi(obj);
}
@@ -182,54 +179,40 @@
// Values depend of PCLK2: 64 MHz if HSI is used, 72 MHz if HSE is used
if (hz < 500000) {
obj->br_presc = SPI_BaudRatePrescaler_256; // 250 kHz - 281 kHz
- }
- else if ((hz >= 500000) && (hz < 1000000)) {
+ } else if ((hz >= 500000) && (hz < 1000000)) {
obj->br_presc = SPI_BaudRatePrescaler_128; // 500 kHz - 563 kHz
- }
- else if ((hz >= 1000000) && (hz < 2000000)) {
+ } else if ((hz >= 1000000) && (hz < 2000000)) {
obj->br_presc = SPI_BaudRatePrescaler_64; // 1 MHz - 1.13 MHz
- }
- else if ((hz >= 2000000) && (hz < 4000000)) {
+ } else if ((hz >= 2000000) && (hz < 4000000)) {
obj->br_presc = SPI_BaudRatePrescaler_32; // 2 MHz - 2.25 MHz
- }
- else if ((hz >= 4000000) && (hz < 8000000)) {
+ } else if ((hz >= 4000000) && (hz < 8000000)) {
obj->br_presc = SPI_BaudRatePrescaler_16; // 4 MHz - 4.5 MHz
- }
- else if ((hz >= 8000000) && (hz < 16000000)) {
+ } else if ((hz >= 8000000) && (hz < 16000000)) {
obj->br_presc = SPI_BaudRatePrescaler_8; // 8 MHz - 9 MHz
- }
- else if ((hz >= 16000000) && (hz < 32000000)) {
+ } else if ((hz >= 16000000) && (hz < 32000000)) {
obj->br_presc = SPI_BaudRatePrescaler_4; // 16 MHz - 18 MHz
- }
- else { // >= 32000000
+ } else { // >= 32000000
obj->br_presc = SPI_BaudRatePrescaler_2; // 32 MHz - 36 MHz
}
}
-
+
if (obj->spi == SPI_2) {
// Values depend of PCLK1: 32 MHz if HSI is used, 36 MHz if HSE is used
if (hz < 250000) {
obj->br_presc = SPI_BaudRatePrescaler_256; // 125 kHz - 141 kHz
- }
- else if ((hz >= 250000) && (hz < 500000)) {
+ } else if ((hz >= 250000) && (hz < 500000)) {
obj->br_presc = SPI_BaudRatePrescaler_128; // 250 kHz - 281 kHz
- }
- else if ((hz >= 500000) && (hz < 1000000)) {
+ } else if ((hz >= 500000) && (hz < 1000000)) {
obj->br_presc = SPI_BaudRatePrescaler_64; // 500 kHz - 563 kHz
- }
- else if ((hz >= 1000000) && (hz < 2000000)) {
+ } else if ((hz >= 1000000) && (hz < 2000000)) {
obj->br_presc = SPI_BaudRatePrescaler_32; // 1 MHz - 1.13 MHz
- }
- else if ((hz >= 2000000) && (hz < 4000000)) {
+ } else if ((hz >= 2000000) && (hz < 4000000)) {
obj->br_presc = SPI_BaudRatePrescaler_16; // 2 MHz - 2.25 MHz
- }
- else if ((hz >= 4000000) && (hz < 8000000)) {
+ } else if ((hz >= 4000000) && (hz < 8000000)) {
obj->br_presc = SPI_BaudRatePrescaler_8; // 4 MHz - 4.5 MHz
- }
- else if ((hz >= 8000000) && (hz < 16000000)) {
+ } else if ((hz >= 8000000) && (hz < 16000000)) {
obj->br_presc = SPI_BaudRatePrescaler_4; // 8 MHz - 9 MHz
- }
- else { // >= 16000000
+ } else { // >= 16000000
obj->br_presc = SPI_BaudRatePrescaler_2; // 16 MHz - 18 MHz
}
}
@@ -242,7 +225,7 @@
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
// Check if data is received
status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_RXNE) != RESET) ? 1 : 0);
- return status;
+ return status;
}
static inline int ssp_writeable(spi_t *obj) {
@@ -254,13 +237,13 @@
}
static inline void ssp_write(spi_t *obj, int value) {
- SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_writeable(obj));
SPI_I2S_SendData(spi, (uint16_t)value);
}
static inline int ssp_read(spi_t *obj) {
- SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_readable(obj));
return (int)SPI_I2S_ReceiveData(spi);
}
@@ -287,8 +270,8 @@
}
void spi_slave_write(spi_t *obj, int value) {
- SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
- while (!ssp_writeable(obj));
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_writeable(obj));
SPI_I2S_SendData(spi, (uint16_t)value);
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c Tue Apr 29 11:15:07 2014 +0100
@@ -59,14 +59,12 @@
if (oc_rem_part > 0) {
set_compare(oc_rem_part); // Finish the remaining time left
oc_rem_part = 0;
- }
- else {
+ } else {
if (oc_int_part > 0) {
set_compare(0xFFFF);
oc_rem_part = cval; // To finish the counter loop the next time
oc_int_part--;
- }
- else {
+ } else {
us_ticker_irq_handler();
}
}
@@ -75,13 +73,13 @@
void us_ticker_init(void) {
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
-
+
if (us_ticker_inited) return;
us_ticker_inited = 1;
-
- // Enable Timer clock
+
+ // Enable timer clock
TIM_MST_RCC;
-
+
// Configure time base
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
@@ -89,15 +87,15 @@
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure);
-
+
// Configure interrupts
TIM_ITConfig(TIM_MST, TIM_IT_Update, ENABLE);
-
+
// Update interrupt used for 32-bit counter
// Output compare interrupt used for timeout feature
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)tim_irq_handler);
NVIC_EnableIRQ(TIM_MST_IRQ);
-
+
// Enable timer
TIM_Cmd(TIM_MST, ENABLE);
}
@@ -129,8 +127,7 @@
if (delta <= 0) { // This event was in the past
us_ticker_irq_handler();
- }
- else {
+ } else {
oc_int_part = (uint32_t)(delta >> 16);
oc_rem_part = (uint16_t)(delta & 0xFFFF);
if (oc_rem_part <= (0xFFFF - cval)) {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PeripheralNames.h Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PeripheralNames.h Tue Apr 29 11:15:07 2014 +0100
@@ -45,7 +45,7 @@
} DACName;
typedef enum {
- UART_1 = (int)USART1_BASE,
+ UART_1 = (int)USART1_BASE,
UART_2 = (int)USART2_BASE,
UART_3 = (int)USART3_BASE,
UART_4 = (int)UART4_BASE,
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogin_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogin_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -26,13 +26,13 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "analogin_api.h"
-#include "wait_api.h"
#if DEVICE_ANALOGIN
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
+#include "wait_api.h"
static const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN0
@@ -63,12 +63,12 @@
void analogin_init(analogin_t *obj, PinName pin) {
ADC_TypeDef *adc;
ADC_InitTypeDef ADC_InitStructure;
-
+
// Get the peripheral name from the pin and assign it to the object
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
-
+
if (obj->adc == (ADCName)NC) {
- error("ADC pin mapping failed");
+ error("ADC pin mapping failed");
}
// Configure GPIO
@@ -83,10 +83,10 @@
// Get ADC registers structure address
adc = (ADC_TypeDef *)(obj->adc);
-
+
// Enable ADC clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
-
+
// Configure ADC
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
@@ -103,92 +103,92 @@
}
static inline uint16_t adc_read(analogin_t *obj) {
- // Get ADC registers structure address
- ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc);
- uint8_t channel = 0;
-
- // Configure ADC channel
- switch (obj->pin) {
- case PA_0:
- channel = ADC_Channel_0;
- break;
- case PA_1:
- channel = ADC_Channel_1;
- break;
- case PA_2:
- channel = ADC_Channel_2;
- break;
- case PA_3:
- channel = ADC_Channel_3;
- break;
- case PA_4:
- channel = ADC_Channel_4;
- break;
- case PA_5:
- channel = ADC_Channel_5;
- break;
- case PA_6:
- channel = ADC_Channel_6;
- break;
- case PA_7:
- channel = ADC_Channel_7;
- break;
- case PB_0:
- channel = ADC_Channel_8;
- break;
- case PB_1:
- channel = ADC_Channel_9;
- break;
- case PB_12:
- channel = ADC_Channel_18;
- break;
- case PB_13:
- channel = ADC_Channel_19;
- break;
- case PB_14:
- channel = ADC_Channel_20;
- break;
- case PB_15:
- channel = ADC_Channel_21;
- break;
- case PC_0:
- channel = ADC_Channel_10;
- break;
- case PC_1:
- channel = ADC_Channel_11;
- break;
- case PC_2:
- channel = ADC_Channel_12;
- break;
- case PC_3:
- channel = ADC_Channel_13;
- break;
- case PC_4:
- channel = ADC_Channel_14;
- break;
- case PC_5:
- channel = ADC_Channel_15;
- break;
- default:
- return 0;
- }
+ // Get ADC registers structure address
+ ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc);
+ uint8_t channel = 0;
- ADC_RegularChannelConfig(adc, channel, 1, ADC_SampleTime_4Cycles);
-
- ADC_SoftwareStartConv(adc); // Start conversion
-
- while(ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion
-
- return(ADC_GetConversionValue(adc)); // Get conversion value
+ // Configure ADC channel
+ switch (obj->pin) {
+ case PA_0:
+ channel = ADC_Channel_0;
+ break;
+ case PA_1:
+ channel = ADC_Channel_1;
+ break;
+ case PA_2:
+ channel = ADC_Channel_2;
+ break;
+ case PA_3:
+ channel = ADC_Channel_3;
+ break;
+ case PA_4:
+ channel = ADC_Channel_4;
+ break;
+ case PA_5:
+ channel = ADC_Channel_5;
+ break;
+ case PA_6:
+ channel = ADC_Channel_6;
+ break;
+ case PA_7:
+ channel = ADC_Channel_7;
+ break;
+ case PB_0:
+ channel = ADC_Channel_8;
+ break;
+ case PB_1:
+ channel = ADC_Channel_9;
+ break;
+ case PB_12:
+ channel = ADC_Channel_18;
+ break;
+ case PB_13:
+ channel = ADC_Channel_19;
+ break;
+ case PB_14:
+ channel = ADC_Channel_20;
+ break;
+ case PB_15:
+ channel = ADC_Channel_21;
+ break;
+ case PC_0:
+ channel = ADC_Channel_10;
+ break;
+ case PC_1:
+ channel = ADC_Channel_11;
+ break;
+ case PC_2:
+ channel = ADC_Channel_12;
+ break;
+ case PC_3:
+ channel = ADC_Channel_13;
+ break;
+ case PC_4:
+ channel = ADC_Channel_14;
+ break;
+ case PC_5:
+ channel = ADC_Channel_15;
+ break;
+ default:
+ return 0;
+ }
+
+ ADC_RegularChannelConfig(adc, channel, 1, ADC_SampleTime_4Cycles);
+
+ ADC_SoftwareStartConv(adc); // Start conversion
+
+ while (ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion
+
+ return (ADC_GetConversionValue(adc)); // Get conversion value
}
uint16_t analogin_read_u16(analogin_t *obj) {
- return(adc_read(obj));
+ return (adc_read(obj));
}
float analogin_read(analogin_t *obj) {
- uint16_t value = adc_read(obj);
- return (float)value * (1.0f / (float)0xFFF); // 12 bits range
+ uint16_t value = adc_read(obj);
+ return (float)value * (1.0f / (float)0xFFF); // 12 bits range
}
#endif
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogout_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogout_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -43,7 +43,7 @@
void analogout_init(dac_t *obj, PinName pin) {
DAC_InitTypeDef DAC_InitStructure;
-
+
// Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
@@ -65,7 +65,7 @@
DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;
-
+
if (obj->channel == PA_4) {
DAC_Init(DAC_Channel_1, &DAC_InitStructure);
DAC_Cmd(DAC_Channel_1, ENABLE);
@@ -74,7 +74,7 @@
DAC_Init(DAC_Channel_2, &DAC_InitStructure);
DAC_Cmd(DAC_Channel_2, ENABLE);
}
-
+
analogout_write_u16(obj, 0);
}
@@ -112,10 +112,9 @@
void analogout_write_u16(dac_t *obj, uint16_t value) {
if (value > (uint16_t)RANGE_12BIT) {
- dac_write(obj, (uint16_t)RANGE_12BIT); // Max value
- }
- else {
- dac_write(obj, value);
+ dac_write(obj, (uint16_t)RANGE_12BIT); // Max value
+ } else {
+ dac_write(obj, value);
}
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -33,7 +33,7 @@
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-uint32_t gpio_set(PinName pin) {
+uint32_t gpio_set(PinName pin) {
if (pin == NC) return 0;
pin_function(pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
@@ -45,11 +45,11 @@
if (pin == NC) return;
uint32_t port_index = STM_PORT(pin);
-
+
// Enable GPIO clock
uint32_t gpio_add = Set_GPIO_Clock(port_index);
GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
+
// Fill GPIO object structure for future use
obj->pin = pin;
obj->mask = gpio_set(pin);
@@ -65,8 +65,7 @@
void gpio_dir(gpio_t *obj, PinDirection direction) {
if (direction == PIN_OUTPUT) {
pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
- }
- else { // PIN_INPUT
+ } else { // PIN_INPUT
pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
}
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_irq_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_irq_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -29,7 +29,6 @@
*/
#include <stddef.h>
#include "cmsis.h"
-
#include "gpio_irq_api.h"
#include "pinmap.h"
#include "error.h"
@@ -53,30 +52,42 @@
uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]);
// Clear interrupt flag
- if (EXTI_GetITStatus(pin) != RESET)
- {
+ if (EXTI_GetITStatus(pin) != RESET) {
EXTI_ClearITPendingBit(pin);
}
-
+
if (channel_ids[irq_index] == 0) return;
-
+
// Check which edge has generated the irq
if ((gpio->IDR & pin) == 0) {
irq_handler(channel_ids[irq_index], IRQ_FALL);
- }
- else {
+ } else {
irq_handler(channel_ids[irq_index], IRQ_RISE);
}
}
// The irq_index is passed to the function
-static void gpio_irq0(void) {handle_interrupt_in(0);} // EXTI line 0
-static void gpio_irq1(void) {handle_interrupt_in(1);} // EXTI line 1
-static void gpio_irq2(void) {handle_interrupt_in(2);} // EXTI line 2
-static void gpio_irq3(void) {handle_interrupt_in(3);} // EXTI line 3
-static void gpio_irq4(void) {handle_interrupt_in(4);} // EXTI line 4
-static void gpio_irq5(void) {handle_interrupt_in(5);} // EXTI lines 5 to 9
-static void gpio_irq6(void) {handle_interrupt_in(6);} // EXTI lines 10 to 15
+static void gpio_irq0(void) {
+ handle_interrupt_in(0); // EXTI line 0
+}
+static void gpio_irq1(void) {
+ handle_interrupt_in(1); // EXTI line 1
+}
+static void gpio_irq2(void) {
+ handle_interrupt_in(2); // EXTI line 2
+}
+static void gpio_irq3(void) {
+ handle_interrupt_in(3); // EXTI line 3
+}
+static void gpio_irq4(void) {
+ handle_interrupt_in(4); // EXTI line 4
+}
+static void gpio_irq5(void) {
+ handle_interrupt_in(5); // EXTI lines 5 to 9
+}
+static void gpio_irq6(void) {
+ handle_interrupt_in(6); // EXTI lines 10 to 15
+}
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
@@ -146,18 +157,18 @@
// Enable SYSCFG clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
+
// Connect EXTI line to pin
SYSCFG_EXTILineConfig(port_index, pin_index);
// Configure EXTI line
- EXTI_InitTypeDef EXTI_InitStructure;
+ EXTI_InitTypeDef EXTI_InitStructure;
EXTI_InitStructure.EXTI_Line = (uint32_t)(1 << pin_index);
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
-
+
// Enable and set EXTI interrupt to the lowest priority
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = irq_n;
@@ -165,7 +176,7 @@
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
-
+
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
@@ -176,9 +187,9 @@
channel_ids[irq_index] = id;
channel_gpio[irq_index] = gpio_add;
channel_pin[irq_index] = pin_index;
-
- irq_handler = handler;
-
+
+ irq_handler = handler;
+
return 0;
}
@@ -189,47 +200,44 @@
// Disable EXTI line
EXTI_InitTypeDef EXTI_InitStructure;
EXTI_StructInit(&EXTI_InitStructure);
- EXTI_Init(&EXTI_InitStructure);
+ EXTI_Init(&EXTI_InitStructure);
obj->event = EDGE_NONE;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
EXTI_InitTypeDef EXTI_InitStructure;
-
+
uint32_t pin_index = channel_pin[obj->irq_index];
EXTI_InitStructure.EXTI_Line = (uint32_t)(1 << pin_index);
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-
+
if (event == IRQ_RISE) {
if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
obj->event = EDGE_BOTH;
- }
- else { // NONE or RISE
+ } else { // NONE or RISE
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
obj->event = EDGE_RISE;
}
}
-
+
if (event == IRQ_FALL) {
if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
obj->event = EDGE_BOTH;
- }
- else { // NONE or FALL
+ } else { // NONE or FALL
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
obj->event = EDGE_FALL;
}
}
-
+
if (enable) {
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- }
- else {
+ } else {
EXTI_InitStructure.EXTI_LineCmd = DISABLE;
}
-
+
EXTI_Init(&EXTI_InitStructure);
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h Tue Apr 29 11:15:07 2014 +0100
@@ -50,8 +50,7 @@
static inline void gpio_write(gpio_t *obj, int value) {
if (value) {
*obj->reg_set = obj->mask;
- }
- else {
+ } else {
*obj->reg_clr = obj->mask;
}
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/i2c_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/i2c_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -36,8 +36,8 @@
#include "error.h"
/* Timeout values for flags and events waiting loops. These timeouts are
- not based on accurate values, they just guarantee that the application will
- not remain stuck if the I2C communication is corrupted. */
+ not based on accurate values, they just guarantee that the application will
+ not remain stuck if the I2C communication is corrupted. */
#define FLAG_TIMEOUT ((int)0x1000)
#define LONG_TIMEOUT ((int)0x8000)
@@ -55,19 +55,19 @@
{NC, NC, 0}
};
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
// Determine the I2C to use
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
-
+
if (obj->i2c == (I2CName)NC) {
error("I2C pin mapping failed");
}
// Enable I2C clock
- if (obj->i2c == I2C_1) {
+ if (obj->i2c == I2C_1) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
}
if (obj->i2c == I2C_2) {
@@ -79,12 +79,12 @@
pin_mode(scl, OpenDrain);
pinmap_pinout(sda, PinMap_I2C_SDA);
pin_mode(sda, OpenDrain);
-
+
// Reset to clear pending flags if any
i2c_reset(obj);
-
+
// I2C configuration
- i2c_frequency(obj, 100000); // 100 kHz per default
+ i2c_frequency(obj, 100000); // 100 kHz per default
}
void i2c_frequency(i2c_t *obj, int hz) {
@@ -97,7 +97,7 @@
/* Warning: To use the I2C at 400 kHz (in fast mode), the PCLK1 frequency
(I2C peripheral input clock) must be a multiple of 10 MHz.
With the actual clock configuration, the max frequency is measured at 296 kHz */
-
+
// I2C configuration
I2C_DeInit(i2c);
I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
@@ -113,12 +113,12 @@
inline int i2c_start(i2c_t *obj) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
int timeout;
-
+
I2C_ClearFlag(i2c, I2C_FLAG_AF); // Clear Acknowledge failure flag
-
+
// Generate the START condition
- I2C_GenerateSTART(i2c, ENABLE);
-
+ I2C_GenerateSTART(i2c, ENABLE);
+
// Wait the START condition has been correctly sent
timeout = FLAG_TIMEOUT;
while (I2C_GetFlagStatus(i2c, I2C_FLAG_SB) == RESET) {
@@ -127,7 +127,7 @@
return 1;
}
}
-
+
return 0;
}
@@ -135,10 +135,10 @@
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
int timeout;
volatile int temp;
-
+
if (I2C_GetFlagStatus(i2c, I2C_FLAG_MSL) == RESET) {
timeout = LONG_TIMEOUT;
- // wait for STOP
+ // wait for STOP
while (I2C_GetFlagStatus(i2c, I2C_FLAG_STOPF) == RESET) {
timeout--;
if (timeout == 0) {
@@ -147,11 +147,10 @@
}
temp = i2c->SR1;
I2C_Cmd(i2c, ENABLE);
- }
- else {
+ } else {
I2C_GenerateSTOP(i2c, ENABLE);
}
-
+
return 0;
}
@@ -160,13 +159,13 @@
int timeout;
int count;
int value;
-
+
if (length == 0) return 0;
i2c_start(obj);
// Send slave address for read
- I2C_Send7bitAddress(i2c, address, I2C_Direction_Receiver);
+ I2C_Send7bitAddress(i2c, address, I2C_Direction_Receiver);
// Wait address is acknowledged
timeout = FLAG_TIMEOUT;
@@ -176,13 +175,13 @@
return 0;
}
}
-
+
// Read all bytes except last one
for (count = 0; count < (length - 1); count++) {
value = i2c_byte_read(obj, 0);
data[count] = (char)value;
}
-
+
// If not repeated start, send stop.
// Warning: must be done BEFORE the data is read.
if (stop) {
@@ -192,7 +191,7 @@
// Read the last byte
value = i2c_byte_read(obj, 1);
data[count] = (char)value;
-
+
return length;
}
@@ -205,7 +204,7 @@
// Send slave address for write
I2C_Send7bitAddress(i2c, address, I2C_Direction_Transmitter);
-
+
// Wait address is acknowledged
timeout = FLAG_TIMEOUT;
while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) == ERROR) {
@@ -234,7 +233,7 @@
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
uint8_t data;
int timeout;
-
+
if (last) {
// Don't acknowledge the last byte
I2C_AcknowledgeConfig(i2c, DISABLE);
@@ -253,7 +252,7 @@
}
data = I2C_ReceiveData(i2c);
-
+
return (int)data;
}
@@ -266,24 +265,24 @@
// Wait until the byte is transmitted
timeout = FLAG_TIMEOUT;
while ((I2C_GetFlagStatus(i2c, I2C_FLAG_TXE) == RESET) &&
- (I2C_GetFlagStatus(i2c, I2C_FLAG_BTF) == RESET)) {
+ (I2C_GetFlagStatus(i2c, I2C_FLAG_BTF) == RESET)) {
timeout--;
if (timeout == 0) {
return 0;
}
}
-
+
return 1;
}
void i2c_reset(i2c_t *obj) {
- if (obj->i2c == I2C_1) {
+ if (obj->i2c == I2C_1) {
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
}
if (obj->i2c == I2C_2) {
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
}
}
@@ -292,7 +291,7 @@
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
uint16_t tmpreg;
-
+
// Get the old register value
tmpreg = i2c->OAR1;
// Reset address bits
@@ -314,28 +313,28 @@
#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
int i2c_slave_receive(i2c_t *obj) {
- return(0);
+ return (0);
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
int count = 0;
-
+
// Read all bytes
for (count = 0; count < length; count++) {
data[count] = i2c_byte_read(obj, 0);
}
-
+
return count;
}
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
int count = 0;
-
+
// Write all bytes
for (count = 0; count < length; count++) {
i2c_byte_write(obj, data[count]);
}
-
+
return count;
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/mbed_overrides.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/mbed_overrides.c Tue Apr 29 11:15:07 2014 +0100
@@ -25,8 +25,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-
-extern void SystemCoreClockUpdate(void);
+#include "cmsis.h"
// This function is called after RAM initialization and before main.
void mbed_sdk_init() {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/objects.h Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/objects.h Tue Apr 29 11:15:07 2014 +0100
@@ -48,7 +48,7 @@
struct port_s {
PortName port;
uint32_t mask;
- PinDirection direction;
+ PinDirection direction;
__IO uint16_t *reg_in;
__IO uint16_t *reg_out;
};
@@ -69,7 +69,7 @@
uint32_t baudrate;
uint32_t databits;
uint32_t stopbits;
- uint32_t parity;
+ uint32_t parity;
};
struct spi_s {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pinmap.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pinmap.c Tue Apr 29 11:15:07 2014 +0100
@@ -86,7 +86,7 @@
if (afnum != 0xFF) {
GPIO_PinAFConfig(gpio, (uint16_t)pin_index, afnum);
}
-
+
// Configure GPIO
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index);
@@ -95,7 +95,7 @@
GPIO_InitStructure.GPIO_OType = (GPIOOType_TypeDef)otype;
GPIO_InitStructure.GPIO_PuPd = (GPIOPuPd_TypeDef)pupd;
GPIO_Init(gpio, &GPIO_InitStructure);
-
+
// [TODO] Disconnect JTAG-DP + SW-DP signals.
// Warning: Need to reconnect under reset
//if ((pin == PA_13) || (pin == PA_14)) {
@@ -103,7 +103,7 @@
//}
//if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
//
- //}
+ //}
}
/**
@@ -124,5 +124,5 @@
if (pupd > 2) pupd = 0; // Open-drain = No pull-up/No pull-down
gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2)));
gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2));
-
+
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/port_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/port_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -28,18 +28,19 @@
*******************************************************************************
*/
#include "port_api.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
#include "pinmap.h"
#include "gpio_api.h"
#include "error.h"
-#if DEVICE_PORTIN || DEVICE_PORTOUT
-
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
// low nibble = pin number
PinName port_pin(PortName port, int pin_n) {
- return (PinName)(pin_n + (port << 4));
+ return (PinName)(pin_n + (port << 4));
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
@@ -52,9 +53,9 @@
// Fill PORT object structure for future use
obj->port = port;
obj->mask = mask;
- obj->direction = dir;
+ obj->direction = dir;
obj->reg_in = &gpio->IDR;
- obj->reg_out = &gpio->ODR;
+ obj->reg_out = &gpio->ODR;
port_dir(obj, dir);
}
@@ -66,16 +67,15 @@
if (obj->mask & (1 << i)) { // If the pin is used
if (dir == PIN_OUTPUT) {
pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
- }
- else { // PIN_INPUT
+ } else { // PIN_INPUT
pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
}
}
- }
+ }
}
void port_mode(port_t *obj, PinMode mode) {
- uint32_t i;
+ uint32_t i;
for (i = 0; i < 16; i++) { // Process all pins
if (obj->mask & (1 << i)) { // If the pin is used
pin_mode(port_pin(obj->port, i), mode);
@@ -90,8 +90,7 @@
int port_read(port_t *obj) {
if (obj->direction == PIN_OUTPUT) {
return (*obj->reg_out & obj->mask);
- }
- else { // PIN_INPUT
+ } else { // PIN_INPUT
return (*obj->reg_in & obj->mask);
}
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pwmout_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pwmout_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -29,25 +29,27 @@
*/
#include "pwmout_api.h"
+#if DEVICE_PWMOUT
+
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
// TIM5 cannot be used because already used by the us_ticker
static const PinMap PinMap_PWM[] = {
- //{PA_0, PWM_5, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM5)}, // TIM5_CH1
+// {PA_0, PWM_5, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM5)}, // TIM5_CH1
{PA_1, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM2)}, // TIM2_CH2
- //{PA_1, PWM_5, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM5)}, // TIM5_CH1
+// {PA_1, PWM_5, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM5)}, // TIM5_CH1
{PA_2, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM2)}, // TIM2_CH3
- //{PA_2, PWM_5, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM5)}, // TIM5_CH3
- //{PA_2, PWM_9, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM9)}, // TIM9_CH1
+// {PA_2, PWM_5, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM5)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM9)}, // TIM9_CH1
{PA_3, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM2)}, // TIM2_CH4
- //{PA_3, PWM_5, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM5)}, // TIM5_CH4
- //{PA_3, PWM_9, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM9)}, // TIM9_CH2
+// {PA_3, PWM_5, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM5)}, // TIM5_CH4
+// {PA_3, PWM_9, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM9)}, // TIM9_CH2
{PA_6, PWM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM3)}, // TIM3_CH1
- //{PA_6, PWM_10, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM10)}, // TIM10_CH1
+// {PA_6, PWM_10, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM10)}, // TIM10_CH1
{PA_7, PWM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM3)}, // TIM3_CH2
- //{PA_7, PWM_11, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM11)}, // TIM11_CH1
+// {PA_7, PWM_11, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM11)}, // TIM11_CH1
{PB_0, PWM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM3)}, // TIM3_CH3
{PB_1, PWM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM3)}, // TIM3_CH4
{PB_3, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM2)}, // TIM2_CH2
@@ -56,30 +58,30 @@
{PB_6, PWM_4, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM4)}, // TIM4_CH1
{PB_7, PWM_4, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM4)}, // TIM4_CH2
{PB_8, PWM_4, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM4)}, // TIM4_CH3
- //{PB_8, PWM_10, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM10)}, // TIM10_CH1
+// {PB_8, PWM_10, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM10)}, // TIM10_CH1
{PB_9, PWM_4, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM4)}, // TIM4_CH4
- //{PB_9, PWM_11, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM11)}, // TIM11_CH1
+// {PB_9, PWM_11, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM11)}, // TIM11_CH1
{PB_10, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM2)}, // TIM2_CH3
{PB_11, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM2)}, // TIM2_CH4
{PB_12, PWM_10, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM10)}, // TIM10_CH1
{PB_13, PWM_9, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM9)}, // TIM9_CH1
{PB_14, PWM_9, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM9)}, // TIM9_CH2
- {PB_15, PWM_11, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM11)}, // TIM11_CH1
+ {PB_15, PWM_11, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM11)}, // TIM11_CH1
{PC_6, PWM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM3)}, // TIM3_CH1
{PC_7, PWM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM3)}, // TIM3_CH2
{PC_8, PWM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM3)}, // TIM3_CH3
- {PC_9, PWM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM3)}, // TIM3_CH4
+ {PC_9, PWM_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_TIM3)}, // TIM3_CH4
{NC, NC, 0}
};
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin) {
// Get the peripheral name from the pin and assign it to the object
obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
-
+
if (obj->pwm == (PWMName)NC) {
error("PWM pinout mapping failed");
}
-
+
// Enable TIM clock
if (obj->pwm == PWM_2) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
if (obj->pwm == PWM_3) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
@@ -88,14 +90,14 @@
if (obj->pwm == PWM_9) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE);
if (obj->pwm == PWM_10) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10, ENABLE);
if (obj->pwm == PWM_11) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM11, ENABLE);
-
+
// Configure GPIO
pinmap_pinout(pin, PinMap_PWM);
-
+
obj->pin = pin;
obj->period = 0;
obj->pulse = 0;
-
+
pwmout_period_us(obj, 20000); // 20 ms per default
}
@@ -113,9 +115,9 @@
} else if (value > 1.0) {
value = 1.0;
}
-
+
obj->pulse = (uint32_t)((float)obj->period * value);
-
+
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_Pulse = obj->pulse;
@@ -124,15 +126,15 @@
// Configure the channels
switch (obj->pin) {
// Channels 1
- //case PA_0:
- //case PA_1:
- //case PA_2:
+ //case PA_0:
+ //case PA_1:
+ //case PA_2:
case PA_6:
- //case PA_7:
+ //case PA_7:
case PB_4:
case PB_6:
- //case PB_8:
- //case PB_9:
+ //case PB_8:
+ //case PB_9:
case PB_12:
case PB_13:
case PB_15:
@@ -142,7 +144,7 @@
break;
// Channels 2
case PA_1:
- //case PA_3:
+ //case PA_3:
case PA_7:
case PB_3:
case PB_5:
@@ -169,7 +171,7 @@
case PC_9:
TIM_OC4PreloadConfig(tim, TIM_OCPreload_Enable);
TIM_OC4Init(tim, &TIM_OCInitStructure);
- break;
+ break;
default:
return;
}
@@ -196,10 +198,10 @@
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
float dc = pwmout_read(obj);
- TIM_Cmd(tim, DISABLE);
-
+ TIM_Cmd(tim, DISABLE);
+
obj->period = us;
-
+
TIM_TimeBaseStructure.TIM_Period = obj->period - 1;
TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
@@ -208,8 +210,8 @@
// Set duty cycle again
pwmout_write(obj, dc);
-
- TIM_ARRPreloadConfig(tim, ENABLE);
+
+ TIM_ARRPreloadConfig(tim, ENABLE);
TIM_Cmd(tim, ENABLE);
}
@@ -225,3 +227,5 @@
float value = (float)us / (float)obj->period;
pwmout_write(obj, value);
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/rtc_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/rtc_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -29,36 +29,63 @@
*/
#include "rtc_api.h"
+#if DEVICE_RTC
+
+#include "wait_api.h"
+
+#define LSE_STARTUP_TIMEOUT ((uint16_t)400) // delay in ms
+
static int rtc_inited = 0;
void rtc_init(void) {
+ uint32_t StartUpCounter = 0;
+ uint32_t LSEStatus = 0;
+ uint32_t rtc_freq = 0;
+
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); // Enable PWR clock
- PWR_RTCAccessCmd(ENABLE); // Enable access to RTC
+ PWR_RTCAccessCmd(ENABLE); // Enable access to Backup domain
+
+ // Reset RTC and Backup registers
+ RCC_RTCResetCmd(ENABLE);
+ RCC_RTCResetCmd(DISABLE);
+
+ // Enable LSE clock
+ RCC_LSEConfig(RCC_LSE_ON);
- // Note: the LSI is used as RTC source clock
- // The RTC Clock may vary due to LSI frequency dispersion.
-
- RCC_LSICmd(ENABLE); // Enable LSI
-
- while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {} // Wait until ready
-
- RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select LSI as RTC Clock Source
-
- RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock
-
- RTC_WaitForSynchro(); // Wait for RTC registers synchronization
+ // Wait till LSE is ready
+ do {
+ LSEStatus = RCC_GetFlagStatus(RCC_FLAG_LSERDY);
+ wait_ms(1);
+ StartUpCounter++;
+ } while ((LSEStatus == 0) && (StartUpCounter <= LSE_STARTUP_TIMEOUT));
- uint32_t lsi_freq = 40000; // [TODO] To be measured precisely using a timer input capture
+ if (StartUpCounter > LSE_STARTUP_TIMEOUT) {
+ // The LSE has not started, use LSI instead.
+ // The RTC Clock may vary due to LSI frequency dispersion.
+ RCC_LSEConfig(RCC_LSE_OFF);
+ RCC_LSICmd(ENABLE); // Enable LSI
+ while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {} // Wait until ready
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select the RTC Clock Source
+ rtc_freq = 40000; // [TODO] To be measured precisely using a timer input capture
+ } else {
+ // The LSE has correctly started
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); // Select the RTC Clock Source
+ rtc_freq = LSE_VALUE;
+ }
RTC_InitTypeDef RTC_InitStructure;
RTC_InitStructure.RTC_AsynchPrediv = 127;
- RTC_InitStructure.RTC_SynchPrediv = (lsi_freq / 128) - 1;
+ RTC_InitStructure.RTC_SynchPrediv = (rtc_freq / 128) - 1;
RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24;
RTC_Init(&RTC_InitStructure);
-
- PWR_RTCAccessCmd(DISABLE); // Disable access to RTC
-
+
+ RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock
+
+ RTC_WaitForSynchro(); // Wait for RTC registers synchronization
+
+ PWR_RTCAccessCmd(DISABLE); // Disable access to Backup domain
+
rtc_inited = 1;
}
@@ -92,11 +119,11 @@
RTC_DateTypeDef dateStruct;
RTC_TimeTypeDef timeStruct;
struct tm timeinfo;
-
+
// Read actual date and time
RTC_GetTime(RTC_Format_BIN, &timeStruct);
RTC_GetDate(RTC_Format_BIN, &dateStruct);
-
+
// Setup a tm structure based on the RTC
timeinfo.tm_wday = dateStruct.RTC_WeekDay;
timeinfo.tm_mon = dateStruct.RTC_Month - 1;
@@ -105,11 +132,11 @@
timeinfo.tm_hour = timeStruct.RTC_Hours;
timeinfo.tm_min = timeStruct.RTC_Minutes;
timeinfo.tm_sec = timeStruct.RTC_Seconds;
-
+
// Convert to timestamp
time_t t = mktime(&timeinfo);
-
- return t;
+
+ return t;
}
void rtc_write(time_t t) {
@@ -118,7 +145,7 @@
// Convert the time into a tm
struct tm *timeinfo = localtime(&t);
-
+
// Fill RTC structures
dateStruct.RTC_WeekDay = timeinfo->tm_wday;
dateStruct.RTC_Month = timeinfo->tm_mon + 1;
@@ -128,10 +155,12 @@
timeStruct.RTC_Minutes = timeinfo->tm_min;
timeStruct.RTC_Seconds = timeinfo->tm_sec;
timeStruct.RTC_H12 = RTC_HourFormat_24;
-
+
// Change the RTC current date/time
- PWR_RTCAccessCmd(ENABLE); // Enable access to RTC
+ PWR_RTCAccessCmd(ENABLE); // Enable access to Backup domain
RTC_SetDate(RTC_Format_BIN, &dateStruct);
- RTC_SetTime(RTC_Format_BIN, &timeStruct);
- PWR_RTCAccessCmd(DISABLE); // Disable access to RTC
+ RTC_SetTime(RTC_Format_BIN, &timeStruct);
+ PWR_RTCAccessCmd(DISABLE); // Disable access to Backup domain
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/serial_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/serial_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -28,6 +28,9 @@
*******************************************************************************
*/
#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
@@ -38,7 +41,7 @@
{PA_9, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART1)},
{PB_6, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART1)},
{PB_10, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART3)},
- //{PC_10, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART3)},
+// {PC_10, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART3)},
{PC_10, UART_4, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_UART4)},
{PC_12, UART_5, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_UART5)},
{NC, NC, 0}
@@ -49,7 +52,7 @@
{PA_10, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART1)},
{PB_7, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART1)},
{PB_11, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART3)},
- //{PC_11, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART3)},
+// {PC_11, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART3)},
{PC_11, UART_4, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_UART4)},
{PD_2, UART_5, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_UART5)},
{NC, NC, 0}
@@ -67,7 +70,7 @@
static void init_usart(serial_t *obj) {
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
USART_InitTypeDef USART_InitStructure;
-
+
USART_Cmd(usart, DISABLE);
USART_InitStructure.USART_BaudRate = obj->baudrate;
@@ -77,15 +80,15 @@
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(usart, &USART_InitStructure);
-
+
USART_Cmd(usart, ENABLE);
}
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
// Determine the UART to use (UART_1, UART_2, ...)
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
+
// Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
@@ -95,19 +98,19 @@
// Enable USART clock
if (obj->uart == UART_1) {
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
}
if (obj->uart == UART_2) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
}
if (obj->uart == UART_3) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
}
if (obj->uart == UART_4) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
}
if (obj->uart == UART_5) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
}
// Configure the UART pins
@@ -120,7 +123,7 @@
obj->baudrate = 9600;
obj->databits = USART_WordLength_8b;
obj->stopbits = USART_StopBits_1;
- obj->parity = USART_Parity_No;
+ obj->parity = USART_Parity_No;
init_usart(obj);
@@ -130,12 +133,12 @@
if (obj->uart == UART_3) obj->index = 2;
if (obj->uart == UART_4) obj->index = 3;
if (obj->uart == UART_5) obj->index = 4;
-
+
// For stdio management
if (obj->uart == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
- }
+ }
}
void serial_free(serial_t *obj) {
@@ -150,29 +153,27 @@
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
if (data_bits == 8) {
obj->databits = USART_WordLength_8b;
- }
- else {
+ } else {
obj->databits = USART_WordLength_9b;
}
switch (parity) {
- case ParityOdd:
- case ParityForced0:
- obj->parity = USART_Parity_Odd;
- break;
- case ParityEven:
- case ParityForced1:
- obj->parity = USART_Parity_Even;
- break;
- default: // ParityNone
- obj->parity = USART_Parity_No;
- break;
+ case ParityOdd:
+ case ParityForced0:
+ obj->parity = USART_Parity_Odd;
+ break;
+ case ParityEven:
+ case ParityForced1:
+ obj->parity = USART_Parity_Even;
+ break;
+ default: // ParityNone
+ obj->parity = USART_Parity_No;
+ break;
}
-
+
if (stop_bits == 2) {
obj->stopbits = USART_StopBits_2;
- }
- else {
+ } else {
obj->stopbits = USART_StopBits_1;
}
@@ -197,11 +198,21 @@
}
}
-static void uart1_irq(void) {uart_irq((USART_TypeDef*)UART_1, 0);}
-static void uart2_irq(void) {uart_irq((USART_TypeDef*)UART_2, 1);}
-static void uart3_irq(void) {uart_irq((USART_TypeDef*)UART_3, 2);}
-static void uart4_irq(void) {uart_irq((USART_TypeDef*)UART_4, 3);}
-static void uart5_irq(void) {uart_irq((USART_TypeDef*)UART_5, 4);}
+static void uart1_irq(void) {
+ uart_irq((USART_TypeDef*)UART_1, 0);
+}
+static void uart2_irq(void) {
+ uart_irq((USART_TypeDef*)UART_2, 1);
+}
+static void uart3_irq(void) {
+ uart_irq((USART_TypeDef*)UART_3, 2);
+}
+static void uart4_irq(void) {
+ uart_irq((USART_TypeDef*)UART_4, 3);
+}
+static void uart5_irq(void) {
+ uart_irq((USART_TypeDef*)UART_5, 4);
+}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
@@ -214,60 +225,58 @@
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
if (obj->uart == UART_1) {
- irq_n = USART1_IRQn;
- vector = (uint32_t)&uart1_irq;
+ irq_n = USART1_IRQn;
+ vector = (uint32_t)&uart1_irq;
}
-
+
if (obj->uart == UART_2) {
- irq_n = USART2_IRQn;
- vector = (uint32_t)&uart2_irq;
+ irq_n = USART2_IRQn;
+ vector = (uint32_t)&uart2_irq;
}
if (obj->uart == UART_3) {
- irq_n = USART3_IRQn;
- vector = (uint32_t)&uart3_irq;
+ irq_n = USART3_IRQn;
+ vector = (uint32_t)&uart3_irq;
}
if (obj->uart == UART_4) {
- irq_n = UART4_IRQn;
- vector = (uint32_t)&uart4_irq;
+ irq_n = UART4_IRQn;
+ vector = (uint32_t)&uart4_irq;
}
if (obj->uart == UART_5) {
- irq_n = UART5_IRQn;
- vector = (uint32_t)&uart5_irq;
+ irq_n = UART5_IRQn;
+ vector = (uint32_t)&uart5_irq;
}
-
+
if (enable) {
-
+
if (irq == RxIrq) {
USART_ITConfig(usart, USART_IT_RXNE, ENABLE);
- }
- else { // TxIrq
+ } else { // TxIrq
USART_ITConfig(usart, USART_IT_TC, ENABLE);
- }
-
+ }
+
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
-
+
} else { // disable
-
+
int all_disabled = 0;
-
+
if (irq == RxIrq) {
USART_ITConfig(usart, USART_IT_RXNE, DISABLE);
// Check if TxIrq is disabled too
if ((usart->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
- }
- else { // TxIrq
+ } else { // TxIrq
USART_ITConfig(usart, USART_IT_TXE, DISABLE);
// Check if RxIrq is disabled too
- if ((usart->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
+ if ((usart->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
}
-
+
if (all_disabled) NVIC_DisableIRQ(irq_n);
-
- }
+
+ }
}
/******************************************************************************
@@ -319,3 +328,5 @@
void serial_break_clear(serial_t *obj) {
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/sleep.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/sleep.c Tue Apr 29 11:15:07 2014 +0100
@@ -28,33 +28,33 @@
*******************************************************************************
*/
#include "sleep_api.h"
+
+#if DEVICE_SLEEP
+
#include "cmsis.h"
-// This function is in the system_stm32l1xx.c file
-extern void SetSysClock(void);
-
// MCU SLEEP mode
-void sleep(void)
-{
+void sleep(void) {
// Enable PWR clock
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
// Request to enter SLEEP mode with regulator ON
PWR_EnterSleepMode(PWR_Regulator_ON, PWR_SLEEPEntry_WFI);
}
// MCU STOP mode (Regulator in LP mode, LSI, HSI and HSE OFF)
-void deepsleep(void)
-{
+void deepsleep(void) {
// Enable PWR clock
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
-
+
// Enable Ultra low power mode
PWR_UltraLowPowerCmd(ENABLE);
// Enter Stop Mode
- PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
-
+ PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
+
// After wake-up from STOP reconfigure the PLL
SetSysClock();
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/spi_api.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/spi_api.c Tue Apr 29 11:15:07 2014 +0100
@@ -37,29 +37,29 @@
#include "error.h"
static const PinMap PinMap_SPI_MOSI[] = {
- {PA_7, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
+ {PA_7, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
{PA_12, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
{PB_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
- //{PB_5, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
+// {PB_5, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
{PB_15, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI2)},
{PC_12, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_MISO[] = {
- {PA_6, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
+ {PA_6, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
{PA_11, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
{PB_4, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
- //{PB_4, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
+// {PB_4, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
{PB_14, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI2)},
{PC_11, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SCLK[] = {
- {PA_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
+ {PA_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
{PB_3, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
- //{PB_3, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
+// {PB_3, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
{PB_13, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI2)},
{PC_10, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
{NC, NC, 0}
@@ -67,9 +67,9 @@
static const PinMap PinMap_SPI_SSEL[] = {
{PA_4, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
- //{PA_4, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
+// {PA_4, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
{PA_15, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
- //{PA_15, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
+// {PA_15, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI3)},
{PB_12, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI2)},
{NC, NC, 0}
};
@@ -81,11 +81,11 @@
SPI_Cmd(spi, DISABLE);
SPI_InitStructure.SPI_Mode = obj->mode;
- SPI_InitStructure.SPI_NSS = obj->nss;
- SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_NSS = obj->nss;
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStructure.SPI_DataSize = obj->bits;
SPI_InitStructure.SPI_CPOL = obj->cpol;
- SPI_InitStructure.SPI_CPHA = obj->cpha;
+ SPI_InitStructure.SPI_CPHA = obj->cpha;
SPI_InitStructure.SPI_BaudRatePrescaler = obj->br_presc;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStructure.SPI_CRCPolynomial = 7;
@@ -100,43 +100,42 @@
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
+
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
+
obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-
+
if (obj->spi == (SPIName)NC) {
error("SPI pinout mapping failed");
}
-
+
// Enable SPI clock
if (obj->spi == SPI_1) {
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
}
if (obj->spi == SPI_2) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
}
if (obj->spi == SPI_3) {
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
}
-
+
// Configure the SPI pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
+
// Save new values
obj->bits = SPI_DataSize_8b;
obj->cpol = SPI_CPOL_Low;
obj->cpha = SPI_CPHA_1Edge;
obj->br_presc = SPI_BaudRatePrescaler_256;
-
+
if (ssel == NC) { // Master
obj->mode = SPI_Mode_Master;
obj->nss = SPI_NSS_Soft;
- }
- else { // Slave
+ } else { // Slave
pinmap_pinout(ssel, PinMap_SPI_SSEL);
obj->mode = SPI_Mode_Slave;
obj->nss = SPI_NSS_Soft;
@@ -150,43 +149,41 @@
SPI_I2S_DeInit(spi);
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
// Save new values
if (bits == 8) {
obj->bits = SPI_DataSize_8b;
- }
- else {
+ } else {
obj->bits = SPI_DataSize_16b;
}
-
+
switch (mode) {
case 0:
- obj->cpol = SPI_CPOL_Low;
- obj->cpha = SPI_CPHA_1Edge;
- break;
+ obj->cpol = SPI_CPOL_Low;
+ obj->cpha = SPI_CPHA_1Edge;
+ break;
case 1:
- obj->cpol = SPI_CPOL_Low;
- obj->cpha = SPI_CPHA_2Edge;
- break;
+ obj->cpol = SPI_CPOL_Low;
+ obj->cpha = SPI_CPHA_2Edge;
+ break;
case 2:
- obj->cpol = SPI_CPOL_High;
- obj->cpha = SPI_CPHA_1Edge;
- break;
+ obj->cpol = SPI_CPOL_High;
+ obj->cpha = SPI_CPHA_1Edge;
+ break;
default:
- obj->cpol = SPI_CPOL_High;
- obj->cpha = SPI_CPHA_2Edge;
- break;
+ obj->cpol = SPI_CPOL_High;
+ obj->cpha = SPI_CPHA_2Edge;
+ break;
}
-
+
if (slave == 0) {
obj->mode = SPI_Mode_Master;
obj->nss = SPI_NSS_Soft;
- }
- else {
+ } else {
obj->mode = SPI_Mode_Slave;
- obj->nss = SPI_NSS_Hard;
+ obj->nss = SPI_NSS_Hard;
}
-
+
init_spi(obj);
}
@@ -195,54 +192,39 @@
if (SystemCoreClock == 32000000) { // HSI
if (hz < 250000) {
obj->br_presc = SPI_BaudRatePrescaler_256; // 125 kHz
- }
- else if ((hz >= 250000) && (hz < 500000)) {
+ } else if ((hz >= 250000) && (hz < 500000)) {
obj->br_presc = SPI_BaudRatePrescaler_128; // 250 kHz
- }
- else if ((hz >= 500000) && (hz < 1000000)) {
+ } else if ((hz >= 500000) && (hz < 1000000)) {
obj->br_presc = SPI_BaudRatePrescaler_64; // 500 kHz
- }
- else if ((hz >= 1000000) && (hz < 2000000)) {
+ } else if ((hz >= 1000000) && (hz < 2000000)) {
obj->br_presc = SPI_BaudRatePrescaler_32; // 1 MHz
- }
- else if ((hz >= 2000000) && (hz < 4000000)) {
+ } else if ((hz >= 2000000) && (hz < 4000000)) {
obj->br_presc = SPI_BaudRatePrescaler_16; // 2 MHz
- }
- else if ((hz >= 4000000) && (hz < 8000000)) {
+ } else if ((hz >= 4000000) && (hz < 8000000)) {
obj->br_presc = SPI_BaudRatePrescaler_8; // 4 MHz
- }
- else if ((hz >= 8000000) && (hz < 16000000)) {
+ } else if ((hz >= 8000000) && (hz < 16000000)) {
obj->br_presc = SPI_BaudRatePrescaler_4; // 8 MHz
- }
- else { // >= 16000000
+ } else { // >= 16000000
obj->br_presc = SPI_BaudRatePrescaler_2; // 16 MHz
}
- }
- else { // 24 MHz - HSE
+ } else { // 24 MHz - HSE
if (hz < 180000) {
obj->br_presc = SPI_BaudRatePrescaler_256; // 94 kHz
- }
- else if ((hz >= 180000) && (hz < 350000)) {
+ } else if ((hz >= 180000) && (hz < 350000)) {
obj->br_presc = SPI_BaudRatePrescaler_128; // 188 kHz
- }
- else if ((hz >= 350000) && (hz < 750000)) {
+ } else if ((hz >= 350000) && (hz < 750000)) {
obj->br_presc = SPI_BaudRatePrescaler_64; // 375 kHz
- }
- else if ((hz >= 750000) && (hz < 1000000)) {
+ } else if ((hz >= 750000) && (hz < 1000000)) {
obj->br_presc = SPI_BaudRatePrescaler_32; // 750 kHz
+ } else if ((hz >= 1000000) && (hz < 3000000)) {
+ obj->br_presc = SPI_BaudRatePrescaler_16; // 1.5 MHz
+ } else if ((hz >= 3000000) && (hz < 6000000)) {
+ obj->br_presc = SPI_BaudRatePrescaler_8; // 3 MHz
+ } else if ((hz >= 6000000) && (hz < 12000000)) {
+ obj->br_presc = SPI_BaudRatePrescaler_4; // 6 MHz
+ } else { // >= 12000000
+ obj->br_presc = SPI_BaudRatePrescaler_2; // 12 MHz
}
- else if ((hz >= 1000000) && (hz < 3000000)) {
- obj->br_presc = SPI_BaudRatePrescaler_16; // 1.5 MHz
- }
- else if ((hz >= 3000000) && (hz < 6000000)) {
- obj->br_presc = SPI_BaudRatePrescaler_8; // 3 MHz
- }
- else if ((hz >= 6000000) && (hz < 12000000)) {
- obj->br_presc = SPI_BaudRatePrescaler_4; // 6 MHz
- }
- else { // >= 12000000
- obj->br_presc = SPI_BaudRatePrescaler_2; // 12 MHz
- }
}
init_spi(obj);
}
@@ -252,7 +234,7 @@
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
// Check if data is received
status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_RXNE) != RESET) ? 1 : 0);
- return status;
+ return status;
}
static inline int ssp_writeable(spi_t *obj) {
@@ -264,13 +246,13 @@
}
static inline void ssp_write(spi_t *obj, int value) {
- SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_writeable(obj));
SPI_I2S_SendData(spi, (uint16_t)value);
}
static inline int ssp_read(spi_t *obj) {
- SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_readable(obj));
return (int)SPI_I2S_ReceiveData(spi);
}
@@ -297,8 +279,8 @@
}
void spi_slave_write(spi_t *obj, int value) {
- SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
- while (!ssp_writeable(obj));
+ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_writeable(obj));
SPI_I2S_SendData(spi, (uint16_t)value);
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/us_ticker.c Mon Apr 28 18:15:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/us_ticker.c Tue Apr 29 11:15:07 2014 +0100
@@ -38,13 +38,13 @@
void us_ticker_init(void) {
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
-
+
if (us_ticker_inited) return;
us_ticker_inited = 1;
-
+
// Enable timer clock
TIM_MST_RCC;
-
+
// Configure time base
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.TIM_Period = 0xFFFFFFFF;
@@ -52,10 +52,10 @@
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure);
-
+
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(TIM_MST_IRQ);
-
+
// Enable timer
TIM_Cmd(TIM_MST, ENABLE);
}