Revision 9:b69faea5252c, committed 2014-10-07

Comitter:

Sissors

Date:

Tue Oct 07 09:00:51 2014 +0000

Parent:

8:97d75b6d5028

Child:

10:6ed1d9f1ef37

Commit message:

Added LPC13XX in list of defines (does compile, not verified yet to work)

Changed in this revision

--- a/BurstSPI_LPC1768.cpp	Wed Sep 03 18:46:02 2014 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,20 +0,0 @@
-#if defined(TARGET_LPC1768) || defined(TARGET_LPC1114) || defined(TARGET_LPC11U24)
-#include "BurstSPI.h"
-
-void BurstSPI::fastWrite(int data) {
-    //Wait until FIFO has space
-    while(((_spi.spi->SR) & 0x02) == 0);
-    
-    //transmit data
-    _spi.spi->DR = data;
-    }
-
-void BurstSPI::clearRX( void ) {
-    //Do it while either data in RX buffer, or while it is busy
-    while(((_spi.spi->SR) & ((1<<4) + (1<<2))) != 0) {
-        //Wait until data in RX buffer
-        while(((_spi.spi->SR) & (1<<2)) == 0);
-        int dummy = _spi.spi->DR;
-        }
-}
-#endif
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/BurstSPI_LPC_X.cpp	Tue Oct 07 09:00:51 2014 +0000
@@ -0,0 +1,20 @@
+#if defined(TARGET_LPC1768) || defined(TARGET_LPC1114) || defined(TARGET_LPC11U24) || defined(TARGET_LPC13XX)
+#include "BurstSPI.h"
+
+void BurstSPI::fastWrite(int data) {
+    //Wait until FIFO has space
+    while(((_spi.spi->SR) & 0x02) == 0);
+    
+    //transmit data
+    _spi.spi->DR = data;
+    }
+
+void BurstSPI::clearRX( void ) {
+    //Do it while either data in RX buffer, or while it is busy
+    while(((_spi.spi->SR) & ((1<<4) + (1<<2))) != 0) {
+        //Wait until data in RX buffer
+        while(((_spi.spi->SR) & (1<<2)) == 0);
+        int dummy = _spi.spi->DR;
+        }
+}
+#endif
\ No newline at end of file