LPC17xx.h File Reference

CMSIS Cortex-M3 Core Peripheral Access Layer Header File for NXP LPC17xx Device Series. More...

Go to the source code of this file.

Defines
#define	__MPU_PRESENT   1
#define	__NVIC_PRIO_BITS   5
#define	__Vendor_SysTickConfig   0
Enumerations
enum	IRQn {   NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,   SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,   WDT_IRQn = 0, TIMER0_IRQn = 1, TIMER1_IRQn = 2, TIMER2_IRQn = 3,   TIMER3_IRQn = 4, UART0_IRQn = 5, UART1_IRQn = 6, UART2_IRQn = 7,   UART3_IRQn = 8, PWM1_IRQn = 9, I2C0_IRQn = 10, I2C1_IRQn = 11,   I2C2_IRQn = 12, SPI_IRQn = 13, SSP0_IRQn = 14, SSP1_IRQn = 15,   PLL0_IRQn = 16, RTC_IRQn = 17, EINT0_IRQn = 18, EINT1_IRQn = 19,   EINT2_IRQn = 20, EINT3_IRQn = 21, ADC_IRQn = 22, BOD_IRQn = 23,   USB_IRQn = 24, CAN_IRQn = 25, DMA_IRQn = 26, I2S_IRQn = 27,   ENET_IRQn = 28, RIT_IRQn = 29, MCPWM_IRQn = 30, QEI_IRQn = 31,   PLL1_IRQn = 32 }

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Detailed Description

CMSIS Cortex-M3 Core Peripheral Access Layer Header File for NXP LPC17xx Device Series.

Version:

V1.07

Date:

19. October 2009

Note:

Copyright (C) 2009 ARM Limited. All rights reserved.

ARM Limited (ARM) is supplying this software for use with Cortex-M processor based microcontrollers. This file can be freely distributed within development tools that are supporting such ARM based processors.

THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

Definition in file LPC17xx.h.

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Define Documentation

#define __MPU_PRESENT   1

MPU present or not

Definition at line 91 of file LPC17xx.h.

#define __NVIC_PRIO_BITS   5

Number of Bits used for Priority Levels

Definition at line 92 of file LPC17xx.h.

#define __Vendor_SysTickConfig   0

Set to 1 if different SysTick Config is used

Definition at line 93 of file LPC17xx.h.

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Enumeration Type Documentation

enum IRQn

Enumerator:

NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WDT_IRQn	Watchdog Timer Interrupt
TIMER0_IRQn	Timer0 Interrupt
TIMER1_IRQn	Timer1 Interrupt
TIMER2_IRQn	Timer2 Interrupt
TIMER3_IRQn	Timer3 Interrupt
UART0_IRQn	UART0 Interrupt
UART1_IRQn	UART1 Interrupt
UART2_IRQn	UART2 Interrupt
UART3_IRQn	UART3 Interrupt
PWM1_IRQn	PWM1 Interrupt
I2C0_IRQn	I2C0 Interrupt
I2C1_IRQn	I2C1 Interrupt
I2C2_IRQn	I2C2 Interrupt
SPI_IRQn	SPI Interrupt
SSP0_IRQn	SSP0 Interrupt
SSP1_IRQn	SSP1 Interrupt
PLL0_IRQn	PLL0 Lock (Main PLL) Interrupt
RTC_IRQn	Real Time Clock Interrupt
EINT0_IRQn	External Interrupt 0 Interrupt
EINT1_IRQn	External Interrupt 1 Interrupt
EINT2_IRQn	External Interrupt 2 Interrupt
EINT3_IRQn	External Interrupt 3 Interrupt
ADC_IRQn	A/D Converter Interrupt
BOD_IRQn	Brown-Out Detect Interrupt
USB_IRQn	USB Interrupt
CAN_IRQn	CAN Interrupt
DMA_IRQn	General Purpose DMA Interrupt
I2S_IRQn	I2S Interrupt
ENET_IRQn	Ethernet Interrupt
RIT_IRQn	Repetitive Interrupt Timer Interrupt
MCPWM_IRQn	Motor Control PWM Interrupt
QEI_IRQn	Quadrature Encoder Interface Interrupt
PLL1_IRQn	PLL1 Lock (USB PLL) Interrupt

Definition at line 35 of file LPC17xx.h.